WebSVN – Kolibri OS – Diff – /drivers/include/drm/drm_edid.h


/*
 * Copyright © 2007-2008 Intel Corporation
 *   Jesse Barnes 
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 */
#ifndef __DRM_EDID_H__
#define __DRM_EDID_H__
 
#include 
 
#define EDID_LENGTH 128
#define DDC_ADDR 0x50
 
#define CEA_EXT	    0x02
#define VTB_EXT	    0x10
#define DI_EXT	    0x40
#define LS_EXT	    0x50
#define MI_EXT	    0x60
 
struct est_timings {
	u8 t1;
	u8 t2;
	u8 mfg_rsvd;
} __attribute__((packed));
 
/* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */
#define EDID_TIMING_ASPECT_SHIFT 6
#define EDID_TIMING_ASPECT_MASK  (0x3 << EDID_TIMING_ASPECT_SHIFT)
 
/* need to add 60 */
#define EDID_TIMING_VFREQ_SHIFT  0
#define EDID_TIMING_VFREQ_MASK   (0x3f << EDID_TIMING_VFREQ_SHIFT)
 
struct std_timing {
	u8 hsize; /* need to multiply by 8 then add 248 */
	u8 vfreq_aspect;
} __attribute__((packed));
 
#define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1)
#define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2)
#define DRM_EDID_PT_SEPARATE_SYNC  (3 << 3)
#define DRM_EDID_PT_STEREO         (1 << 5)
#define DRM_EDID_PT_INTERLACED     (1 << 7)
 
/* If detailed data is pixel timing */
struct detailed_pixel_timing {
	u8 hactive_lo;
	u8 hblank_lo;
	u8 hactive_hblank_hi;
	u8 vactive_lo;
	u8 vblank_lo;
	u8 vactive_vblank_hi;
	u8 hsync_offset_lo;
	u8 hsync_pulse_width_lo;
	u8 vsync_offset_pulse_width_lo;
	u8 hsync_vsync_offset_pulse_width_hi;
	u8 width_mm_lo;
	u8 height_mm_lo;
	u8 width_height_mm_hi;
	u8 hborder;
	u8 vborder;
	u8 misc;
} __attribute__((packed));
 
/* If it's not pixel timing, it'll be one of the below */
struct detailed_data_string {
	u8 str[13];
} __attribute__((packed));
 
struct detailed_data_monitor_range {
	u8 min_vfreq;
	u8 max_vfreq;
	u8 min_hfreq_khz;
	u8 max_hfreq_khz;
	u8 pixel_clock_mhz; /* need to multiply by 10 */
	u8 flags;
	union {
		struct {
			u8 reserved;
	u8 hfreq_start_khz; /* need to multiply by 2 */
	u8 c; /* need to divide by 2 */
	__le16 m;
	u8 k;
	u8 j; /* need to divide by 2 */
		} __attribute__((packed)) gtf2;
		struct {
			u8 version;
			u8 data1; /* high 6 bits: extra clock resolution */
			u8 data2; /* plus low 2 of above: max hactive */
			u8 supported_aspects;
			u8 flags; /* preferred aspect and blanking support */
			u8 supported_scalings;
			u8 preferred_refresh;
		} __attribute__((packed)) cvt;
	} formula;
} __attribute__((packed));
 
struct detailed_data_wpindex {
	u8 white_yx_lo; /* Lower 2 bits each */
	u8 white_x_hi;
	u8 white_y_hi;
	u8 gamma; /* need to divide by 100 then add 1 */
} __attribute__((packed));
 
struct detailed_data_color_point {
	u8 windex1;
	u8 wpindex1[3];
	u8 windex2;
	u8 wpindex2[3];
} __attribute__((packed));
 
struct cvt_timing {
	u8 code[3];
} __attribute__((packed));
 
struct detailed_non_pixel {
	u8 pad1;
	u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name
		    fb=color point data, fa=standard timing data,
		    f9=undefined, f8=mfg. reserved */
	u8 pad2;
	union {
		struct detailed_data_string str;
		struct detailed_data_monitor_range range;
		struct detailed_data_wpindex color;
		struct std_timing timings[6];
		struct cvt_timing cvt[4];
	} data;
} __attribute__((packed));
 
#define EDID_DETAIL_EST_TIMINGS 0xf7
#define EDID_DETAIL_CVT_3BYTE 0xf8
#define EDID_DETAIL_COLOR_MGMT_DATA 0xf9
#define EDID_DETAIL_STD_MODES 0xfa
#define EDID_DETAIL_MONITOR_CPDATA 0xfb
#define EDID_DETAIL_MONITOR_NAME 0xfc
#define EDID_DETAIL_MONITOR_RANGE 0xfd
#define EDID_DETAIL_MONITOR_STRING 0xfe
#define EDID_DETAIL_MONITOR_SERIAL 0xff
 
struct detailed_timing {
	__le16 pixel_clock; /* need to multiply by 10 KHz */
	union {
		struct detailed_pixel_timing pixel_data;
		struct detailed_non_pixel other_data;
	} data;
} __attribute__((packed));
 
#define DRM_EDID_INPUT_SERRATION_VSYNC (1 << 0)
#define DRM_EDID_INPUT_SYNC_ON_GREEN   (1 << 1)
#define DRM_EDID_INPUT_COMPOSITE_SYNC  (1 << 2)
#define DRM_EDID_INPUT_SEPARATE_SYNCS  (1 << 3)
#define DRM_EDID_INPUT_BLANK_TO_BLACK  (1 << 4)
#define DRM_EDID_INPUT_VIDEO_LEVEL     (3 << 5)
#define DRM_EDID_INPUT_DIGITAL         (1 << 7)
#define DRM_EDID_DIGITAL_DEPTH_MASK    (7 << 4)
#define DRM_EDID_DIGITAL_DEPTH_UNDEF   (0 << 4)
#define DRM_EDID_DIGITAL_DEPTH_6       (1 << 4)
#define DRM_EDID_DIGITAL_DEPTH_8       (2 << 4)
#define DRM_EDID_DIGITAL_DEPTH_10      (3 << 4)
#define DRM_EDID_DIGITAL_DEPTH_12      (4 << 4)
#define DRM_EDID_DIGITAL_DEPTH_14      (5 << 4)
#define DRM_EDID_DIGITAL_DEPTH_16      (6 << 4)
#define DRM_EDID_DIGITAL_DEPTH_RSVD    (7 << 4)
#define DRM_EDID_DIGITAL_TYPE_UNDEF    (0)
#define DRM_EDID_DIGITAL_TYPE_DVI      (1)
#define DRM_EDID_DIGITAL_TYPE_HDMI_A   (2)
#define DRM_EDID_DIGITAL_TYPE_HDMI_B   (3)
#define DRM_EDID_DIGITAL_TYPE_MDDI     (4)
#define DRM_EDID_DIGITAL_TYPE_DP       (5)
 
#define DRM_EDID_FEATURE_DEFAULT_GTF      (1 << 0)
#define DRM_EDID_FEATURE_PREFERRED_TIMING (1 << 1)
#define DRM_EDID_FEATURE_STANDARD_COLOR   (1 << 2)
/* If analog */
#define DRM_EDID_FEATURE_DISPLAY_TYPE     (3 << 3) /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */
/* If digital */
#define DRM_EDID_FEATURE_COLOR_MASK	  (3 << 3)
#define DRM_EDID_FEATURE_RGB		  (0 << 3)
#define DRM_EDID_FEATURE_RGB_YCRCB444	  (1 << 3)
#define DRM_EDID_FEATURE_RGB_YCRCB422	  (2 << 3)
#define DRM_EDID_FEATURE_RGB_YCRCB	  (3 << 3) /* both 4:4:4 and 4:2:2 */
 
#define DRM_EDID_FEATURE_PM_ACTIVE_OFF    (1 << 5)
#define DRM_EDID_FEATURE_PM_SUSPEND       (1 << 6)
#define DRM_EDID_FEATURE_PM_STANDBY       (1 << 7)
 
struct edid {
	u8 header[8];
	/* Vendor & product info */
	u8 mfg_id[2];
	u8 prod_code[2];
	u32 serial; /* FIXME: byte order */
	u8 mfg_week;
	u8 mfg_year;
	/* EDID version */
	u8 version;
	u8 revision;
	/* Display info: */
	u8 input;
	u8 width_cm;
	u8 height_cm;
	u8 gamma;
	u8 features;
	/* Color characteristics */
	u8 red_green_lo;
	u8 black_white_lo;
	u8 red_x;
	u8 red_y;
	u8 green_x;
	u8 green_y;
	u8 blue_x;
	u8 blue_y;
	u8 white_x;
	u8 white_y;
	/* Est. timings and mfg rsvd timings*/
	struct est_timings established_timings;
	/* Standard timings 1-8*/
	struct std_timing standard_timings[8];
	/* Detailing timings 1-4 */
	struct detailed_timing detailed_timings[4];
	/* Number of 128 byte ext. blocks */
	u8 extensions;
	/* Checksum */
	u8 checksum;
} __attribute__((packed));
 
#define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8))
 
struct drm_encoder;
struct drm_connector;
struct drm_display_mode;
struct hdmi_avi_infoframe;
 
void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid);
int drm_av_sync_delay(struct drm_connector *connector,
		      struct drm_display_mode *mode);
struct drm_connector *drm_select_eld(struct drm_encoder *encoder,
				     struct drm_display_mode *mode);
int drm_load_edid_firmware(struct drm_connector *connector);
 
int
drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
					 const struct drm_display_mode *mode);
 
#endif /* __DRM_EDID_H__ */

Rev 3031	Rev 3391
1	/*	1	/*
2	* Copyright © 2007-2008 Intel Corporation	2	* Copyright © 2007-2008 Intel Corporation
3	* Jesse Barnes	3	* Jesse Barnes
4	*	4	*
5	* Permission is hereby granted, free of charge, to any person obtaining a	5	* Permission is hereby granted, free of charge, to any person obtaining a
6	* copy of this software and associated documentation files (the "Software"),	6	* copy of this software and associated documentation files (the "Software"),
7	* to deal in the Software without restriction, including without limitation	7	* to deal in the Software without restriction, including without limitation
8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,	8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
9	* and/or sell copies of the Software, and to permit persons to whom the	9	* and/or sell copies of the Software, and to permit persons to whom the
10	* Software is furnished to do so, subject to the following conditions:	10	* Software is furnished to do so, subject to the following conditions:
11	*	11	*
12	* The above copyright notice and this permission notice shall be included in	12	* The above copyright notice and this permission notice shall be included in
13	* all copies or substantial portions of the Software.	13	* all copies or substantial portions of the Software.
14	*	14	*
15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR	18	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,	19	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR	20	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21	* OTHER DEALINGS IN THE SOFTWARE.	21	* OTHER DEALINGS IN THE SOFTWARE.
22	*/	22	*/
23	#ifndef __DRM_EDID_H__	23	#ifndef __DRM_EDID_H__
24	#define __DRM_EDID_H__	24	#define __DRM_EDID_H__
25		25
26	#include	26	#include
27		27
28	#define EDID_LENGTH 128	28	#define EDID_LENGTH 128
29	#define DDC_ADDR 0x50	29	#define DDC_ADDR 0x50
30		30
31	#define CEA_EXT 0x02	31	#define CEA_EXT 0x02
32	#define VTB_EXT 0x10	32	#define VTB_EXT 0x10
33	#define DI_EXT 0x40	33	#define DI_EXT 0x40
34	#define LS_EXT 0x50	34	#define LS_EXT 0x50
35	#define MI_EXT 0x60	35	#define MI_EXT 0x60
36		36
37	struct est_timings {	37	struct est_timings {
38	u8 t1;	38	u8 t1;
39	u8 t2;	39	u8 t2;
40	u8 mfg_rsvd;	40	u8 mfg_rsvd;
41	} __attribute__((packed));	41	} __attribute__((packed));
42		42
43	/* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */	43	/* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */
44	#define EDID_TIMING_ASPECT_SHIFT 6	44	#define EDID_TIMING_ASPECT_SHIFT 6
45	#define EDID_TIMING_ASPECT_MASK (0x3 << EDID_TIMING_ASPECT_SHIFT)	45	#define EDID_TIMING_ASPECT_MASK (0x3 << EDID_TIMING_ASPECT_SHIFT)
46		46
47	/* need to add 60 */	47	/* need to add 60 */
48	#define EDID_TIMING_VFREQ_SHIFT 0	48	#define EDID_TIMING_VFREQ_SHIFT 0
49	#define EDID_TIMING_VFREQ_MASK (0x3f << EDID_TIMING_VFREQ_SHIFT)	49	#define EDID_TIMING_VFREQ_MASK (0x3f << EDID_TIMING_VFREQ_SHIFT)
50		50
51	struct std_timing {	51	struct std_timing {
52	u8 hsize; /* need to multiply by 8 then add 248 */	52	u8 hsize; /* need to multiply by 8 then add 248 */
53	u8 vfreq_aspect;	53	u8 vfreq_aspect;
54	} __attribute__((packed));	54	} __attribute__((packed));
55		55
56	#define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1)	56	#define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1)
57	#define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2)	57	#define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2)
58	#define DRM_EDID_PT_SEPARATE_SYNC (3 << 3)	58	#define DRM_EDID_PT_SEPARATE_SYNC (3 << 3)
59	#define DRM_EDID_PT_STEREO (1 << 5)	59	#define DRM_EDID_PT_STEREO (1 << 5)
60	#define DRM_EDID_PT_INTERLACED (1 << 7)	60	#define DRM_EDID_PT_INTERLACED (1 << 7)
61		61
62	/* If detailed data is pixel timing */	62	/* If detailed data is pixel timing */
63	struct detailed_pixel_timing {	63	struct detailed_pixel_timing {
64	u8 hactive_lo;	64	u8 hactive_lo;
65	u8 hblank_lo;	65	u8 hblank_lo;
66	u8 hactive_hblank_hi;	66	u8 hactive_hblank_hi;
67	u8 vactive_lo;	67	u8 vactive_lo;
68	u8 vblank_lo;	68	u8 vblank_lo;
69	u8 vactive_vblank_hi;	69	u8 vactive_vblank_hi;
70	u8 hsync_offset_lo;	70	u8 hsync_offset_lo;
71	u8 hsync_pulse_width_lo;	71	u8 hsync_pulse_width_lo;
72	u8 vsync_offset_pulse_width_lo;	72	u8 vsync_offset_pulse_width_lo;
73	u8 hsync_vsync_offset_pulse_width_hi;	73	u8 hsync_vsync_offset_pulse_width_hi;
74	u8 width_mm_lo;	74	u8 width_mm_lo;
75	u8 height_mm_lo;	75	u8 height_mm_lo;
76	u8 width_height_mm_hi;	76	u8 width_height_mm_hi;
77	u8 hborder;	77	u8 hborder;
78	u8 vborder;	78	u8 vborder;
79	u8 misc;	79	u8 misc;
80	} __attribute__((packed));	80	} __attribute__((packed));
81		81
82	/* If it's not pixel timing, it'll be one of the below */	82	/* If it's not pixel timing, it'll be one of the below */
83	struct detailed_data_string {	83	struct detailed_data_string {
84	u8 str[13];	84	u8 str[13];
85	} __attribute__((packed));	85	} __attribute__((packed));
86		86
87	struct detailed_data_monitor_range {	87	struct detailed_data_monitor_range {
88	u8 min_vfreq;	88	u8 min_vfreq;
89	u8 max_vfreq;	89	u8 max_vfreq;
90	u8 min_hfreq_khz;	90	u8 min_hfreq_khz;
91	u8 max_hfreq_khz;	91	u8 max_hfreq_khz;
92	u8 pixel_clock_mhz; /* need to multiply by 10 */	92	u8 pixel_clock_mhz; /* need to multiply by 10 */
93	u8 flags;	93	u8 flags;
94	union {	94	union {
95	struct {	95	struct {
96	u8 reserved;	96	u8 reserved;
97	u8 hfreq_start_khz; /* need to multiply by 2 */	97	u8 hfreq_start_khz; /* need to multiply by 2 */
98	u8 c; /* need to divide by 2 */	98	u8 c; /* need to divide by 2 */
99	__le16 m;	99	__le16 m;
100	u8 k;	100	u8 k;
101	u8 j; /* need to divide by 2 */	101	u8 j; /* need to divide by 2 */
102	} __attribute__((packed)) gtf2;	102	} __attribute__((packed)) gtf2;
103	struct {	103	struct {
104	u8 version;	104	u8 version;
105	u8 data1; /* high 6 bits: extra clock resolution */	105	u8 data1; /* high 6 bits: extra clock resolution */
106	u8 data2; /* plus low 2 of above: max hactive */	106	u8 data2; /* plus low 2 of above: max hactive */
107	u8 supported_aspects;	107	u8 supported_aspects;
108	u8 flags; /* preferred aspect and blanking support */	108	u8 flags; /* preferred aspect and blanking support */
109	u8 supported_scalings;	109	u8 supported_scalings;
110	u8 preferred_refresh;	110	u8 preferred_refresh;
111	} __attribute__((packed)) cvt;	111	} __attribute__((packed)) cvt;
112	} formula;	112	} formula;
113	} __attribute__((packed));	113	} __attribute__((packed));
114		114
115	struct detailed_data_wpindex {	115	struct detailed_data_wpindex {
116	u8 white_yx_lo; /* Lower 2 bits each */	116	u8 white_yx_lo; /* Lower 2 bits each */
117	u8 white_x_hi;	117	u8 white_x_hi;
118	u8 white_y_hi;	118	u8 white_y_hi;
119	u8 gamma; /* need to divide by 100 then add 1 */	119	u8 gamma; /* need to divide by 100 then add 1 */
120	} __attribute__((packed));	120	} __attribute__((packed));
121		121
122	struct detailed_data_color_point {	122	struct detailed_data_color_point {
123	u8 windex1;	123	u8 windex1;
124	u8 wpindex1[3];	124	u8 wpindex1[3];
125	u8 windex2;	125	u8 windex2;
126	u8 wpindex2[3];	126	u8 wpindex2[3];
127	} __attribute__((packed));	127	} __attribute__((packed));
128		128
129	struct cvt_timing {	129	struct cvt_timing {
130	u8 code[3];	130	u8 code[3];
131	} __attribute__((packed));	131	} __attribute__((packed));
132		132
133	struct detailed_non_pixel {	133	struct detailed_non_pixel {
134	u8 pad1;	134	u8 pad1;
135	u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name	135	u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name
136	fb=color point data, fa=standard timing data,	136	fb=color point data, fa=standard timing data,
137	f9=undefined, f8=mfg. reserved */	137	f9=undefined, f8=mfg. reserved */
138	u8 pad2;	138	u8 pad2;
139	union {	139	union {
140	struct detailed_data_string str;	140	struct detailed_data_string str;
141	struct detailed_data_monitor_range range;	141	struct detailed_data_monitor_range range;
142	struct detailed_data_wpindex color;	142	struct detailed_data_wpindex color;
143	struct std_timing timings[6];	143	struct std_timing timings[6];
144	struct cvt_timing cvt[4];	144	struct cvt_timing cvt[4];
145	} data;	145	} data;
146	} __attribute__((packed));	146	} __attribute__((packed));
147		147
148	#define EDID_DETAIL_EST_TIMINGS 0xf7	148	#define EDID_DETAIL_EST_TIMINGS 0xf7
149	#define EDID_DETAIL_CVT_3BYTE 0xf8	149	#define EDID_DETAIL_CVT_3BYTE 0xf8
150	#define EDID_DETAIL_COLOR_MGMT_DATA 0xf9	150	#define EDID_DETAIL_COLOR_MGMT_DATA 0xf9
151	#define EDID_DETAIL_STD_MODES 0xfa	151	#define EDID_DETAIL_STD_MODES 0xfa
152	#define EDID_DETAIL_MONITOR_CPDATA 0xfb	152	#define EDID_DETAIL_MONITOR_CPDATA 0xfb
153	#define EDID_DETAIL_MONITOR_NAME 0xfc	153	#define EDID_DETAIL_MONITOR_NAME 0xfc
154	#define EDID_DETAIL_MONITOR_RANGE 0xfd	154	#define EDID_DETAIL_MONITOR_RANGE 0xfd
155	#define EDID_DETAIL_MONITOR_STRING 0xfe	155	#define EDID_DETAIL_MONITOR_STRING 0xfe
156	#define EDID_DETAIL_MONITOR_SERIAL 0xff	156	#define EDID_DETAIL_MONITOR_SERIAL 0xff
157		157
158	struct detailed_timing {	158	struct detailed_timing {
159	__le16 pixel_clock; /* need to multiply by 10 KHz */	159	__le16 pixel_clock; /* need to multiply by 10 KHz */
160	union {	160	union {
161	struct detailed_pixel_timing pixel_data;	161	struct detailed_pixel_timing pixel_data;
162	struct detailed_non_pixel other_data;	162	struct detailed_non_pixel other_data;
163	} data;	163	} data;
164	} __attribute__((packed));	164	} __attribute__((packed));
165		165
166	#define DRM_EDID_INPUT_SERRATION_VSYNC (1 << 0)	166	#define DRM_EDID_INPUT_SERRATION_VSYNC (1 << 0)
167	#define DRM_EDID_INPUT_SYNC_ON_GREEN (1 << 1)	167	#define DRM_EDID_INPUT_SYNC_ON_GREEN (1 << 1)
168	#define DRM_EDID_INPUT_COMPOSITE_SYNC (1 << 2)	168	#define DRM_EDID_INPUT_COMPOSITE_SYNC (1 << 2)
169	#define DRM_EDID_INPUT_SEPARATE_SYNCS (1 << 3)	169	#define DRM_EDID_INPUT_SEPARATE_SYNCS (1 << 3)
170	#define DRM_EDID_INPUT_BLANK_TO_BLACK (1 << 4)	170	#define DRM_EDID_INPUT_BLANK_TO_BLACK (1 << 4)
171	#define DRM_EDID_INPUT_VIDEO_LEVEL (3 << 5)	171	#define DRM_EDID_INPUT_VIDEO_LEVEL (3 << 5)
172	#define DRM_EDID_INPUT_DIGITAL (1 << 7)	172	#define DRM_EDID_INPUT_DIGITAL (1 << 7)
173	#define DRM_EDID_DIGITAL_DEPTH_MASK (7 << 4)	173	#define DRM_EDID_DIGITAL_DEPTH_MASK (7 << 4)
174	#define DRM_EDID_DIGITAL_DEPTH_UNDEF (0 << 4)	174	#define DRM_EDID_DIGITAL_DEPTH_UNDEF (0 << 4)
175	#define DRM_EDID_DIGITAL_DEPTH_6 (1 << 4)	175	#define DRM_EDID_DIGITAL_DEPTH_6 (1 << 4)
176	#define DRM_EDID_DIGITAL_DEPTH_8 (2 << 4)	176	#define DRM_EDID_DIGITAL_DEPTH_8 (2 << 4)
177	#define DRM_EDID_DIGITAL_DEPTH_10 (3 << 4)	177	#define DRM_EDID_DIGITAL_DEPTH_10 (3 << 4)
178	#define DRM_EDID_DIGITAL_DEPTH_12 (4 << 4)	178	#define DRM_EDID_DIGITAL_DEPTH_12 (4 << 4)
179	#define DRM_EDID_DIGITAL_DEPTH_14 (5 << 4)	179	#define DRM_EDID_DIGITAL_DEPTH_14 (5 << 4)
180	#define DRM_EDID_DIGITAL_DEPTH_16 (6 << 4)	180	#define DRM_EDID_DIGITAL_DEPTH_16 (6 << 4)
181	#define DRM_EDID_DIGITAL_DEPTH_RSVD (7 << 4)	181	#define DRM_EDID_DIGITAL_DEPTH_RSVD (7 << 4)
182	#define DRM_EDID_DIGITAL_TYPE_UNDEF (0)	182	#define DRM_EDID_DIGITAL_TYPE_UNDEF (0)
183	#define DRM_EDID_DIGITAL_TYPE_DVI (1)	183	#define DRM_EDID_DIGITAL_TYPE_DVI (1)
184	#define DRM_EDID_DIGITAL_TYPE_HDMI_A (2)	184	#define DRM_EDID_DIGITAL_TYPE_HDMI_A (2)
185	#define DRM_EDID_DIGITAL_TYPE_HDMI_B (3)	185	#define DRM_EDID_DIGITAL_TYPE_HDMI_B (3)
186	#define DRM_EDID_DIGITAL_TYPE_MDDI (4)	186	#define DRM_EDID_DIGITAL_TYPE_MDDI (4)
187	#define DRM_EDID_DIGITAL_TYPE_DP (5)	187	#define DRM_EDID_DIGITAL_TYPE_DP (5)
188		188
189	#define DRM_EDID_FEATURE_DEFAULT_GTF (1 << 0)	189	#define DRM_EDID_FEATURE_DEFAULT_GTF (1 << 0)
190	#define DRM_EDID_FEATURE_PREFERRED_TIMING (1 << 1)	190	#define DRM_EDID_FEATURE_PREFERRED_TIMING (1 << 1)
191	#define DRM_EDID_FEATURE_STANDARD_COLOR (1 << 2)	191	#define DRM_EDID_FEATURE_STANDARD_COLOR (1 << 2)
192	/* If analog */	192	/* If analog */
193	#define DRM_EDID_FEATURE_DISPLAY_TYPE (3 << 3) /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */	193	#define DRM_EDID_FEATURE_DISPLAY_TYPE (3 << 3) /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */
194	/* If digital */	194	/* If digital */
195	#define DRM_EDID_FEATURE_COLOR_MASK (3 << 3)	195	#define DRM_EDID_FEATURE_COLOR_MASK (3 << 3)
196	#define DRM_EDID_FEATURE_RGB (0 << 3)	196	#define DRM_EDID_FEATURE_RGB (0 << 3)
197	#define DRM_EDID_FEATURE_RGB_YCRCB444 (1 << 3)	197	#define DRM_EDID_FEATURE_RGB_YCRCB444 (1 << 3)
198	#define DRM_EDID_FEATURE_RGB_YCRCB422 (2 << 3)	198	#define DRM_EDID_FEATURE_RGB_YCRCB422 (2 << 3)
199	#define DRM_EDID_FEATURE_RGB_YCRCB (3 << 3) /* both 4:4:4 and 4:2:2 */	199	#define DRM_EDID_FEATURE_RGB_YCRCB (3 << 3) /* both 4:4:4 and 4:2:2 */
200		200
201	#define DRM_EDID_FEATURE_PM_ACTIVE_OFF (1 << 5)	201	#define DRM_EDID_FEATURE_PM_ACTIVE_OFF (1 << 5)
202	#define DRM_EDID_FEATURE_PM_SUSPEND (1 << 6)	202	#define DRM_EDID_FEATURE_PM_SUSPEND (1 << 6)
203	#define DRM_EDID_FEATURE_PM_STANDBY (1 << 7)	203	#define DRM_EDID_FEATURE_PM_STANDBY (1 << 7)
204		204
205	struct edid {	205	struct edid {
206	u8 header[8];	206	u8 header[8];
207	/* Vendor & product info */	207	/* Vendor & product info */
208	u8 mfg_id[2];	208	u8 mfg_id[2];
209	u8 prod_code[2];	209	u8 prod_code[2];
210	u32 serial; /* FIXME: byte order */	210	u32 serial; /* FIXME: byte order */
211	u8 mfg_week;	211	u8 mfg_week;
212	u8 mfg_year;	212	u8 mfg_year;
213	/* EDID version */	213	/* EDID version */
214	u8 version;	214	u8 version;
215	u8 revision;	215	u8 revision;
216	/* Display info: */	216	/* Display info: */
217	u8 input;	217	u8 input;
218	u8 width_cm;	218	u8 width_cm;
219	u8 height_cm;	219	u8 height_cm;
220	u8 gamma;	220	u8 gamma;
221	u8 features;	221	u8 features;
222	/* Color characteristics */	222	/* Color characteristics */
223	u8 red_green_lo;	223	u8 red_green_lo;
224	u8 black_white_lo;	224	u8 black_white_lo;
225	u8 red_x;	225	u8 red_x;
226	u8 red_y;	226	u8 red_y;
227	u8 green_x;	227	u8 green_x;
228	u8 green_y;	228	u8 green_y;
229	u8 blue_x;	229	u8 blue_x;
230	u8 blue_y;	230	u8 blue_y;
231	u8 white_x;	231	u8 white_x;
232	u8 white_y;	232	u8 white_y;
233	/* Est. timings and mfg rsvd timings*/	233	/* Est. timings and mfg rsvd timings*/
234	struct est_timings established_timings;	234	struct est_timings established_timings;
235	/* Standard timings 1-8*/	235	/* Standard timings 1-8*/
236	struct std_timing standard_timings[8];	236	struct std_timing standard_timings[8];
237	/* Detailing timings 1-4 */	237	/* Detailing timings 1-4 */
238	struct detailed_timing detailed_timings[4];	238	struct detailed_timing detailed_timings[4];
239	/* Number of 128 byte ext. blocks */	239	/* Number of 128 byte ext. blocks */
240	u8 extensions;	240	u8 extensions;
241	/* Checksum */	241	/* Checksum */
242	u8 checksum;	242	u8 checksum;
243	} __attribute__((packed));	243	} __attribute__((packed));
244		244
245	#define EDID_PRODUCT_ID(e) ((e)->prod_code[0] \| ((e)->prod_code[1] << 8))	245	#define EDID_PRODUCT_ID(e) ((e)->prod_code[0] \| ((e)->prod_code[1] << 8))
246		246
247	struct drm_encoder;	247	struct drm_encoder;
248	struct drm_connector;	248	struct drm_connector;
249	struct drm_display_mode;	249	struct drm_display_mode;
-		250	struct hdmi_avi_infoframe;
-		251
250	void drm_edid_to_eld(struct drm_connector connector, struct edid edid);	252	void drm_edid_to_eld(struct drm_connector connector, struct edid edid);
251	int drm_av_sync_delay(struct drm_connector *connector,	253	int drm_av_sync_delay(struct drm_connector *connector,
252	struct drm_display_mode *mode);	254	struct drm_display_mode *mode);
253	struct drm_connector drm_select_eld(struct drm_encoder encoder,	255	struct drm_connector drm_select_eld(struct drm_encoder encoder,
254	struct drm_display_mode *mode);	256	struct drm_display_mode *mode);
255	int drm_load_edid_firmware(struct drm_connector *connector);	257	int drm_load_edid_firmware(struct drm_connector *connector);
-		258
-		259	int
-		260	drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
-		261	const struct drm_display_mode *mode);
256		262
257	#endif /* __DRM_EDID_H__ */	263	#endif /* __DRM_EDID_H__ */

Subversion Repositories Kolibri OS

(root)/drivers/include/drm/drm_edid.h – Rev 3031 → 3391