WebSVN – Kolibri OS – Diff – /contrib/sdk/sources/libdrm/include/drm/drm_mode.h


/*
 * Copyright (c) 2007 Dave Airlie 
 * Copyright (c) 2007 Jakob Bornecrantz 
 * Copyright (c) 2008 Red Hat Inc.
 * Copyright (c) 2007-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA
 * Copyright (c) 2007-2008 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 */
 
#ifndef _DRM_MODE_H
#define _DRM_MODE_H
 
#define DRM_DISPLAY_INFO_LEN	32
#define DRM_CONNECTOR_NAME_LEN	32
#define DRM_DISPLAY_MODE_LEN	32
#define DRM_PROP_NAME_LEN	32
 
#define DRM_MODE_TYPE_BUILTIN	(1<<0)
#define DRM_MODE_TYPE_CLOCK_C	((1<<1) | DRM_MODE_TYPE_BUILTIN)
#define DRM_MODE_TYPE_CRTC_C	((1<<2) | DRM_MODE_TYPE_BUILTIN)
#define DRM_MODE_TYPE_PREFERRED	(1<<3)
#define DRM_MODE_TYPE_DEFAULT	(1<<4)
#define DRM_MODE_TYPE_USERDEF	(1<<5)
#define DRM_MODE_TYPE_DRIVER	(1<<6)
 
/* Video mode flags */
/* bit compatible with the xorg definitions. */
#define DRM_MODE_FLAG_PHSYNC	(1<<0)
#define DRM_MODE_FLAG_NHSYNC	(1<<1)
#define DRM_MODE_FLAG_PVSYNC	(1<<2)
#define DRM_MODE_FLAG_NVSYNC	(1<<3)
#define DRM_MODE_FLAG_INTERLACE	(1<<4)
#define DRM_MODE_FLAG_DBLSCAN	(1<<5)
#define DRM_MODE_FLAG_CSYNC	(1<<6)
#define DRM_MODE_FLAG_PCSYNC	(1<<7)
#define DRM_MODE_FLAG_NCSYNC	(1<<8)
#define DRM_MODE_FLAG_HSKEW	(1<<9) /* hskew provided */
#define DRM_MODE_FLAG_BCAST	(1<<10)
#define DRM_MODE_FLAG_PIXMUX	(1<<11)
#define DRM_MODE_FLAG_DBLCLK	(1<<12)
#define DRM_MODE_FLAG_CLKDIV2	(1<<13)
#define DRM_MODE_FLAG_3D_MASK			(0x1f<<14)
#define  DRM_MODE_FLAG_3D_NONE			(0<<14)
#define  DRM_MODE_FLAG_3D_FRAME_PACKING		(1<<14)
#define  DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE	(2<<14)
#define  DRM_MODE_FLAG_3D_LINE_ALTERNATIVE	(3<<14)
#define  DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL	(4<<14)
#define  DRM_MODE_FLAG_3D_L_DEPTH		(5<<14)
#define  DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH	(6<<14)
#define  DRM_MODE_FLAG_3D_TOP_AND_BOTTOM	(7<<14)
#define  DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF	(8<<14)
 
 
/* DPMS flags */
/* bit compatible with the xorg definitions. */
#define DRM_MODE_DPMS_ON	0
#define DRM_MODE_DPMS_STANDBY	1
#define DRM_MODE_DPMS_SUSPEND	2
#define DRM_MODE_DPMS_OFF	3
 
/* Scaling mode options */
#define DRM_MODE_SCALE_NONE		0 /* Unmodified timing (display or
					     software can still scale) */
#define DRM_MODE_SCALE_FULLSCREEN	1 /* Full screen, ignore aspect */
#define DRM_MODE_SCALE_CENTER		2 /* Centered, no scaling */
#define DRM_MODE_SCALE_ASPECT		3 /* Full screen, preserve aspect */
 
/* Dithering mode options */
#define DRM_MODE_DITHERING_OFF	0
#define DRM_MODE_DITHERING_ON	1
#define DRM_MODE_DITHERING_AUTO 2
 
/* Dirty info options */
#define DRM_MODE_DIRTY_OFF      0
#define DRM_MODE_DIRTY_ON       1
#define DRM_MODE_DIRTY_ANNOTATE 2
 
struct drm_mode_modeinfo {
	__u32 clock;
	__u16 hdisplay, hsync_start, hsync_end, htotal, hskew;
	__u16 vdisplay, vsync_start, vsync_end, vtotal, vscan;
 
	__u32 vrefresh;
 
	__u32 flags;
	__u32 type;
	char name[DRM_DISPLAY_MODE_LEN];
};
 
struct drm_mode_card_res {
	__u64 fb_id_ptr;
	__u64 crtc_id_ptr;
	__u64 connector_id_ptr;
	__u64 encoder_id_ptr;
	__u32 count_fbs;
	__u32 count_crtcs;
	__u32 count_connectors;
	__u32 count_encoders;
	__u32 min_width, max_width;
	__u32 min_height, max_height;
};
 
struct drm_mode_crtc {
	__u64 set_connectors_ptr;
	__u32 count_connectors;
 
	__u32 crtc_id; /**< Id */
	__u32 fb_id; /**< Id of framebuffer */
 
	__u32 x, y; /**< Position on the frameuffer */
 
	__u32 gamma_size;
	__u32 mode_valid;
	struct drm_mode_modeinfo mode;
};
 
#define DRM_MODE_PRESENT_TOP_FIELD     (1<<0)
#define DRM_MODE_PRESENT_BOTTOM_FIELD  (1<<1)
 
/* Planes blend with or override other bits on the CRTC */
struct drm_mode_set_plane {
	__u32 plane_id;
	__u32 crtc_id;
	__u32 fb_id; /* fb object contains surface format type */
	__u32 flags;
 
	/* Signed dest location allows it to be partially off screen */
	__s32 crtc_x, crtc_y;
	__u32 crtc_w, crtc_h;
 
	/* Source values are 16.16 fixed point */
	__u32 src_x, src_y;
	__u32 src_h, src_w;
};
 
struct drm_mode_get_plane {
	__u32 plane_id;
 
	__u32 crtc_id;
	__u32 fb_id;
 
	__u32 possible_crtcs;
	__u32 gamma_size;
 
	__u32 count_format_types;
	__u64 format_type_ptr;
};
 
struct drm_mode_get_plane_res {
	__u64 plane_id_ptr;
	__u32 count_planes;
};
 
#define DRM_MODE_ENCODER_NONE	0
#define DRM_MODE_ENCODER_DAC	1
#define DRM_MODE_ENCODER_TMDS	2
#define DRM_MODE_ENCODER_LVDS	3
#define DRM_MODE_ENCODER_TVDAC	4
 
 
 
 
struct drm_mode_get_encoder {
	__u32 encoder_id;
	__u32 encoder_type;
 
	__u32 crtc_id; /**< Id of crtc */
 
	__u32 possible_crtcs;
	__u32 possible_clones;
};
 
/* This is for connectors with multiple signal types. */
/* Try to match DRM_MODE_CONNECTOR_X as closely as possible. */
#define DRM_MODE_SUBCONNECTOR_Automatic	0
#define DRM_MODE_SUBCONNECTOR_Unknown	0
#define DRM_MODE_SUBCONNECTOR_DVID	3
#define DRM_MODE_SUBCONNECTOR_DVIA	4
#define DRM_MODE_SUBCONNECTOR_Composite	5
#define DRM_MODE_SUBCONNECTOR_SVIDEO	6
#define DRM_MODE_SUBCONNECTOR_Component	8
#define DRM_MODE_SUBCONNECTOR_SCART	9
 
#define DRM_MODE_CONNECTOR_Unknown	0
#define DRM_MODE_CONNECTOR_VGA		1
#define DRM_MODE_CONNECTOR_DVII		2
#define DRM_MODE_CONNECTOR_DVID		3
#define DRM_MODE_CONNECTOR_DVIA		4
#define DRM_MODE_CONNECTOR_Composite	5
#define DRM_MODE_CONNECTOR_SVIDEO	6
#define DRM_MODE_CONNECTOR_LVDS		7
#define DRM_MODE_CONNECTOR_Component	8
#define DRM_MODE_CONNECTOR_9PinDIN	9
#define DRM_MODE_CONNECTOR_DisplayPort	10
#define DRM_MODE_CONNECTOR_HDMIA	11
#define DRM_MODE_CONNECTOR_HDMIB	12
#define DRM_MODE_CONNECTOR_TV		13
#define DRM_MODE_CONNECTOR_eDP		14
 
 
 
struct drm_mode_get_connector {
 
	__u64 encoders_ptr;
	__u64 modes_ptr;
	__u64 props_ptr;
	__u64 prop_values_ptr;
 
	__u32 count_modes;
	__u32 count_props;
	__u32 count_encoders;
 
	__u32 encoder_id; /**< Current Encoder */
	__u32 connector_id; /**< Id */
	__u32 connector_type;
	__u32 connector_type_id;
 
	__u32 connection;
	__u32 mm_width, mm_height; /**< HxW in millimeters */
	__u32 subpixel;
 
 
};
 
#define DRM_MODE_PROP_PENDING	(1<<0)
#define DRM_MODE_PROP_RANGE	(1<<1)
#define DRM_MODE_PROP_IMMUTABLE	(1<<2)
#define DRM_MODE_PROP_ENUM	(1<<3) /* enumerated type with text strings */
#define DRM_MODE_PROP_BLOB	(1<<4)
#define DRM_MODE_PROP_BITMASK	(1<<5) /* bitmask of enumerated types */
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
struct drm_mode_property_enum {
	__u64 value;
	char name[DRM_PROP_NAME_LEN];
};
 
struct drm_mode_get_property {
	__u64 values_ptr; /* values and blob lengths */
	__u64 enum_blob_ptr; /* enum and blob id ptrs */
 
	__u32 prop_id;
	__u32 flags;
	char name[DRM_PROP_NAME_LEN];
 
	__u32 count_values;
	__u32 count_enum_blobs;
};
 
struct drm_mode_connector_set_property {
	__u64 value;
	__u32 prop_id;
	__u32 connector_id;
};
 
#define DRM_MODE_OBJECT_CRTC 0xcccccccc
#define DRM_MODE_OBJECT_CONNECTOR 0xc0c0c0c0
#define DRM_MODE_OBJECT_ENCODER 0xe0e0e0e0
#define DRM_MODE_OBJECT_MODE 0xdededede
#define DRM_MODE_OBJECT_PROPERTY 0xb0b0b0b0
#define DRM_MODE_OBJECT_FB 0xfbfbfbfb
#define DRM_MODE_OBJECT_BLOB 0xbbbbbbbb
#define DRM_MODE_OBJECT_PLANE 0xeeeeeeee
 
struct drm_mode_obj_get_properties {
	__u64 props_ptr;
	__u64 prop_values_ptr;
	__u32 count_props;
	__u32 obj_id;
	__u32 obj_type;
};
 
struct drm_mode_obj_set_property {
	__u64 value;
	__u32 prop_id;
	__u32 obj_id;
	__u32 obj_type;
};
 
struct drm_mode_get_blob {
	__u32 blob_id;
	__u32 length;
	__u64 data;
};
 
struct drm_mode_fb_cmd {
	__u32 fb_id;
	__u32 width, height;
	__u32 pitch;
	__u32 bpp;
	__u32 depth;
	/* driver specific handle */
	__u32 handle;
};
 
#define DRM_MODE_FB_INTERLACED (1<<0) /* for interlaced framebuffers */
 
struct drm_mode_fb_cmd2 {
	__u32 fb_id;
	__u32 width, height;
	__u32 pixel_format; /* fourcc code from drm_fourcc.h */
	__u32 flags;
 
	/*
	 * In case of planar formats, this ioctl allows up to 4
	 * buffer objects with offsets and pitches per plane.
	 * The pitch and offset order is dictated by the fourcc,
	 * e.g. NV12 (http://fourcc.org/yuv.php#NV12) is described as:
	 *
	 *   YUV 4:2:0 image with a plane of 8 bit Y samples
	 *   followed by an interleaved U/V plane containing
	 *   8 bit 2x2 subsampled colour difference samples.
	 *
	 * So it would consist of Y as offset[0] and UV as
	 * offset[1].  Note that offset[0] will generally
	 * be 0.
	 */
	__u32 handles[4];
	__u32 pitches[4]; /* pitch for each plane */
	__u32 offsets[4]; /* offset of each plane */
};
 
#define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01
#define DRM_MODE_FB_DIRTY_ANNOTATE_FILL 0x02
#define DRM_MODE_FB_DIRTY_FLAGS         0x03
 
 
 
/*
 * Mark a region of a framebuffer as dirty.
 *
 * Some hardware does not automatically update display contents
 * as a hardware or software draw to a framebuffer. This ioctl
 * allows userspace to tell the kernel and the hardware what
 * regions of the framebuffer have changed.
 *
 * The kernel or hardware is free to update more then just the
 * region specified by the clip rects. The kernel or hardware
 * may also delay and/or coalesce several calls to dirty into a
 * single update.
 *
 * Userspace may annotate the updates, the annotates are a
 * promise made by the caller that the change is either a copy
 * of pixels or a fill of a single color in the region specified.
 *
 * If the DRM_MODE_FB_DIRTY_ANNOTATE_COPY flag is given then
 * the number of updated regions are half of num_clips given,
 * where the clip rects are paired in src and dst. The width and
 * height of each one of the pairs must match.
 *
 * If the DRM_MODE_FB_DIRTY_ANNOTATE_FILL flag is given the caller
 * promises that the region specified of the clip rects is filled
 * completely with a single color as given in the color argument.
 */
 
struct drm_mode_fb_dirty_cmd {
	__u32 fb_id;
	__u32 flags;
	__u32 color;
	__u32 num_clips;
	__u64 clips_ptr;
};
 
struct drm_mode_mode_cmd {
	__u32 connector_id;
	struct drm_mode_modeinfo mode;
};
 
#define DRM_MODE_CURSOR_BO	(1<<0)
 
#define DRM_MODE_CURSOR_MOVE	(1<<1)
 
/*
 * depending on the value in flags diffrent members are used.
 *
 * CURSOR_BO uses
 *    crtc
 *    width
 *    height
 *    handle - if 0 turns the cursor of
 *
 * CURSOR_MOVE uses
 *    crtc
 *    x
 *    y
 */
struct drm_mode_cursor {
	__u32 flags;
	__u32 crtc_id;
	__s32 x;
	__s32 y;
	__u32 width;
	__u32 height;
	/* driver specific handle */
	__u32 handle;
};
 
struct drm_mode_cursor2 {
	__u32 flags;
	__u32 crtc_id;
	__s32 x;
	__s32 y;
	__u32 width;
	__u32 height;
	/* driver specific handle */
	__u32 handle;
	__s32 hot_x;
	__s32 hot_y;
};
 
struct drm_mode_crtc_lut {
	__u32 crtc_id;
	__u32 gamma_size;
 
	/* pointers to arrays */
	__u64 red;
	__u64 green;
	__u64 blue;
};
 
#define DRM_MODE_PAGE_FLIP_EVENT 0x01
#define DRM_MODE_PAGE_FLIP_ASYNC 0x02
#define DRM_MODE_PAGE_FLIP_FLAGS (DRM_MODE_PAGE_FLIP_EVENT|DRM_MODE_PAGE_FLIP_ASYNC)
 
/*
 * Request a page flip on the specified crtc.
 *
 * This ioctl will ask KMS to schedule a page flip for the specified
 * crtc.  Once any pending rendering targeting the specified fb (as of
 * ioctl time) has completed, the crtc will be reprogrammed to display
 * that fb after the next vertical refresh.  The ioctl returns
 * immediately, but subsequent rendering to the current fb will block
 * in the execbuffer ioctl until the page flip happens.  If a page
 * flip is already pending as the ioctl is called, EBUSY will be
 * returned.
 *
 * The ioctl supports one flag, DRM_MODE_PAGE_FLIP_EVENT, which will
 * request that drm sends back a vblank event (see drm.h: struct
 * drm_event_vblank) when the page flip is done.  The user_data field
 * passed in with this ioctl will be returned as the user_data field
 * in the vblank event struct.
 *
 * The reserved field must be zero until we figure out something
 * clever to use it for.
 */
 
struct drm_mode_crtc_page_flip {
	__u32 crtc_id;
	__u32 fb_id;
	__u32 flags;
	__u32 reserved;
	__u64 user_data;
};
 
/* create a dumb scanout buffer */
struct drm_mode_create_dumb {
        __u32 height;
        __u32 width;
        __u32 bpp;
        __u32 flags;
        /* handle, pitch, size will be returned */
        __u32 handle;
        __u32 pitch;
        __u64 size;
};
 
/* set up for mmap of a dumb scanout buffer */
struct drm_mode_map_dumb {
        /** Handle for the object being mapped. */
        __u32 handle;
        __u32 pad;
        /**
         * Fake offset to use for subsequent mmap call
         *
         * This is a fixed-size type for 32/64 compatibility.
         */
        __u64 offset;
};
 
struct drm_mode_destroy_dumb {
	__u32 handle;
};
 
#endif
 
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Rev 5022	Rev 5068
1	/*	1	/*
2	* Copyright (c) 2007 Dave Airlie	2	* Copyright (c) 2007 Dave Airlie
3	* Copyright (c) 2007 Jakob Bornecrantz	3	* Copyright (c) 2007 Jakob Bornecrantz
4	* Copyright (c) 2008 Red Hat Inc.	4	* Copyright (c) 2008 Red Hat Inc.
5	* Copyright (c) 2007-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA	5	* Copyright (c) 2007-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA
6	* Copyright (c) 2007-2008 Intel Corporation	6	* Copyright (c) 2007-2008 Intel Corporation
7	*	7	*
8	* Permission is hereby granted, free of charge, to any person obtaining a	8	* Permission is hereby granted, free of charge, to any person obtaining a
9	* copy of this software and associated documentation files (the "Software"),	9	* copy of this software and associated documentation files (the "Software"),
10	* to deal in the Software without restriction, including without limitation	10	* to deal in the Software without restriction, including without limitation
11	* the rights to use, copy, modify, merge, publish, distribute, sublicense,	11	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
12	* and/or sell copies of the Software, and to permit persons to whom the	12	* and/or sell copies of the Software, and to permit persons to whom the
13	* Software is furnished to do so, subject to the following conditions:	13	* Software is furnished to do so, subject to the following conditions:
14	*	14	*
15	* The above copyright notice and this permission notice shall be included in	15	* The above copyright notice and this permission notice shall be included in
16	* all copies or substantial portions of the Software.	16	* all copies or substantial portions of the Software.
17	*	17	*
18	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR	18	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,	19	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE	20	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
21	* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER	21	* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING	22	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS	23	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24	* IN THE SOFTWARE.	24	* IN THE SOFTWARE.
25	*/	25	*/
26		26
27	#ifndef _DRM_MODE_H	27	#ifndef _DRM_MODE_H
28	#define _DRM_MODE_H	28	#define _DRM_MODE_H
29		29
30	#define DRM_DISPLAY_INFO_LEN 32	30	#define DRM_DISPLAY_INFO_LEN 32
31	#define DRM_CONNECTOR_NAME_LEN 32	31	#define DRM_CONNECTOR_NAME_LEN 32
32	#define DRM_DISPLAY_MODE_LEN 32	32	#define DRM_DISPLAY_MODE_LEN 32
33	#define DRM_PROP_NAME_LEN 32	33	#define DRM_PROP_NAME_LEN 32
34		34
35	#define DRM_MODE_TYPE_BUILTIN (1<<0)	35	#define DRM_MODE_TYPE_BUILTIN (1<<0)
36	#define DRM_MODE_TYPE_CLOCK_C ((1<<1) \| DRM_MODE_TYPE_BUILTIN)	36	#define DRM_MODE_TYPE_CLOCK_C ((1<<1) \| DRM_MODE_TYPE_BUILTIN)
37	#define DRM_MODE_TYPE_CRTC_C ((1<<2) \| DRM_MODE_TYPE_BUILTIN)	37	#define DRM_MODE_TYPE_CRTC_C ((1<<2) \| DRM_MODE_TYPE_BUILTIN)
38	#define DRM_MODE_TYPE_PREFERRED (1<<3)	38	#define DRM_MODE_TYPE_PREFERRED (1<<3)
39	#define DRM_MODE_TYPE_DEFAULT (1<<4)	39	#define DRM_MODE_TYPE_DEFAULT (1<<4)
40	#define DRM_MODE_TYPE_USERDEF (1<<5)	40	#define DRM_MODE_TYPE_USERDEF (1<<5)
41	#define DRM_MODE_TYPE_DRIVER (1<<6)	41	#define DRM_MODE_TYPE_DRIVER (1<<6)
42		42
43	/* Video mode flags */	43	/* Video mode flags */
44	/* bit compatible with the xorg definitions. */	44	/* bit compatible with the xorg definitions. */
45	#define DRM_MODE_FLAG_PHSYNC (1<<0)	45	#define DRM_MODE_FLAG_PHSYNC (1<<0)
46	#define DRM_MODE_FLAG_NHSYNC (1<<1)	46	#define DRM_MODE_FLAG_NHSYNC (1<<1)
47	#define DRM_MODE_FLAG_PVSYNC (1<<2)	47	#define DRM_MODE_FLAG_PVSYNC (1<<2)
48	#define DRM_MODE_FLAG_NVSYNC (1<<3)	48	#define DRM_MODE_FLAG_NVSYNC (1<<3)
49	#define DRM_MODE_FLAG_INTERLACE (1<<4)	49	#define DRM_MODE_FLAG_INTERLACE (1<<4)
50	#define DRM_MODE_FLAG_DBLSCAN (1<<5)	50	#define DRM_MODE_FLAG_DBLSCAN (1<<5)
51	#define DRM_MODE_FLAG_CSYNC (1<<6)	51	#define DRM_MODE_FLAG_CSYNC (1<<6)
52	#define DRM_MODE_FLAG_PCSYNC (1<<7)	52	#define DRM_MODE_FLAG_PCSYNC (1<<7)
53	#define DRM_MODE_FLAG_NCSYNC (1<<8)	53	#define DRM_MODE_FLAG_NCSYNC (1<<8)
54	#define DRM_MODE_FLAG_HSKEW (1<<9) /* hskew provided */	54	#define DRM_MODE_FLAG_HSKEW (1<<9) /* hskew provided */
55	#define DRM_MODE_FLAG_BCAST (1<<10)	55	#define DRM_MODE_FLAG_BCAST (1<<10)
56	#define DRM_MODE_FLAG_PIXMUX (1<<11)	56	#define DRM_MODE_FLAG_PIXMUX (1<<11)
57	#define DRM_MODE_FLAG_DBLCLK (1<<12)	57	#define DRM_MODE_FLAG_DBLCLK (1<<12)
58	#define DRM_MODE_FLAG_CLKDIV2 (1<<13)	58	#define DRM_MODE_FLAG_CLKDIV2 (1<<13)
59	#define DRM_MODE_FLAG_3D_MASK (0x1f<<14)	59	#define DRM_MODE_FLAG_3D_MASK (0x1f<<14)
60	#define DRM_MODE_FLAG_3D_NONE (0<<14)	60	#define DRM_MODE_FLAG_3D_NONE (0<<14)
61	#define DRM_MODE_FLAG_3D_FRAME_PACKING (1<<14)	61	#define DRM_MODE_FLAG_3D_FRAME_PACKING (1<<14)
62	#define DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE (2<<14)	62	#define DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE (2<<14)
63	#define DRM_MODE_FLAG_3D_LINE_ALTERNATIVE (3<<14)	63	#define DRM_MODE_FLAG_3D_LINE_ALTERNATIVE (3<<14)
64	#define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL (4<<14)	64	#define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL (4<<14)
65	#define DRM_MODE_FLAG_3D_L_DEPTH (5<<14)	65	#define DRM_MODE_FLAG_3D_L_DEPTH (5<<14)
66	#define DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH (6<<14)	66	#define DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH (6<<14)
67	#define DRM_MODE_FLAG_3D_TOP_AND_BOTTOM (7<<14)	67	#define DRM_MODE_FLAG_3D_TOP_AND_BOTTOM (7<<14)
68	#define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF (8<<14)	68	#define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF (8<<14)
69		69
70		70
71	/* DPMS flags */	71	/* DPMS flags */
72	/* bit compatible with the xorg definitions. */	72	/* bit compatible with the xorg definitions. */
73	#define DRM_MODE_DPMS_ON 0	73	#define DRM_MODE_DPMS_ON 0
74	#define DRM_MODE_DPMS_STANDBY 1	74	#define DRM_MODE_DPMS_STANDBY 1
75	#define DRM_MODE_DPMS_SUSPEND 2	75	#define DRM_MODE_DPMS_SUSPEND 2
76	#define DRM_MODE_DPMS_OFF 3	76	#define DRM_MODE_DPMS_OFF 3
77		77
78	/* Scaling mode options */	78	/* Scaling mode options */
79	#define DRM_MODE_SCALE_NONE 0 /* Unmodified timing (display or	79	#define DRM_MODE_SCALE_NONE 0 /* Unmodified timing (display or
80	software can still scale) */	80	software can still scale) */
81	#define DRM_MODE_SCALE_FULLSCREEN 1 /* Full screen, ignore aspect */	81	#define DRM_MODE_SCALE_FULLSCREEN 1 /* Full screen, ignore aspect */
82	#define DRM_MODE_SCALE_CENTER 2 /* Centered, no scaling */	82	#define DRM_MODE_SCALE_CENTER 2 /* Centered, no scaling */
83	#define DRM_MODE_SCALE_ASPECT 3 /* Full screen, preserve aspect */	83	#define DRM_MODE_SCALE_ASPECT 3 /* Full screen, preserve aspect */
84		84
85	/* Dithering mode options */	85	/* Dithering mode options */
86	#define DRM_MODE_DITHERING_OFF 0	86	#define DRM_MODE_DITHERING_OFF 0
87	#define DRM_MODE_DITHERING_ON 1	87	#define DRM_MODE_DITHERING_ON 1
88	#define DRM_MODE_DITHERING_AUTO 2	88	#define DRM_MODE_DITHERING_AUTO 2
89		89
90	/* Dirty info options */	90	/* Dirty info options */
91	#define DRM_MODE_DIRTY_OFF 0	91	#define DRM_MODE_DIRTY_OFF 0
92	#define DRM_MODE_DIRTY_ON 1	92	#define DRM_MODE_DIRTY_ON 1
93	#define DRM_MODE_DIRTY_ANNOTATE 2	93	#define DRM_MODE_DIRTY_ANNOTATE 2
94		94
95	struct drm_mode_modeinfo {	95	struct drm_mode_modeinfo {
96	__u32 clock;	96	__u32 clock;
97	__u16 hdisplay, hsync_start, hsync_end, htotal, hskew;	97	__u16 hdisplay, hsync_start, hsync_end, htotal, hskew;
98	__u16 vdisplay, vsync_start, vsync_end, vtotal, vscan;	98	__u16 vdisplay, vsync_start, vsync_end, vtotal, vscan;
99		99
100	__u32 vrefresh;	100	__u32 vrefresh;
101		101
102	__u32 flags;	102	__u32 flags;
103	__u32 type;	103	__u32 type;
104	char name[DRM_DISPLAY_MODE_LEN];	104	char name[DRM_DISPLAY_MODE_LEN];
105	};	105	};
106		106
107	struct drm_mode_card_res {	107	struct drm_mode_card_res {
108	__u64 fb_id_ptr;	108	__u64 fb_id_ptr;
109	__u64 crtc_id_ptr;	109	__u64 crtc_id_ptr;
110	__u64 connector_id_ptr;	110	__u64 connector_id_ptr;
111	__u64 encoder_id_ptr;	111	__u64 encoder_id_ptr;
112	__u32 count_fbs;	112	__u32 count_fbs;
113	__u32 count_crtcs;	113	__u32 count_crtcs;
114	__u32 count_connectors;	114	__u32 count_connectors;
115	__u32 count_encoders;	115	__u32 count_encoders;
116	__u32 min_width, max_width;	116	__u32 min_width, max_width;
117	__u32 min_height, max_height;	117	__u32 min_height, max_height;
118	};	118	};
119		119
120	struct drm_mode_crtc {	120	struct drm_mode_crtc {
121	__u64 set_connectors_ptr;	121	__u64 set_connectors_ptr;
122	__u32 count_connectors;	122	__u32 count_connectors;
123		123
124	__u32 crtc_id; /*< Id /	124	__u32 crtc_id; /*< Id /
125	__u32 fb_id; /*< Id of framebuffer /	125	__u32 fb_id; /*< Id of framebuffer /
126		126
127	__u32 x, y; /*< Position on the frameuffer /	127	__u32 x, y; /*< Position on the frameuffer /
128		128
129	__u32 gamma_size;	129	__u32 gamma_size;
130	__u32 mode_valid;	130	__u32 mode_valid;
131	struct drm_mode_modeinfo mode;	131	struct drm_mode_modeinfo mode;
132	};	132	};
133		133
134	#define DRM_MODE_PRESENT_TOP_FIELD (1<<0)	134	#define DRM_MODE_PRESENT_TOP_FIELD (1<<0)
135	#define DRM_MODE_PRESENT_BOTTOM_FIELD (1<<1)	135	#define DRM_MODE_PRESENT_BOTTOM_FIELD (1<<1)
136		136
137	/* Planes blend with or override other bits on the CRTC */	137	/* Planes blend with or override other bits on the CRTC */
138	struct drm_mode_set_plane {	138	struct drm_mode_set_plane {
139	__u32 plane_id;	139	__u32 plane_id;
140	__u32 crtc_id;	140	__u32 crtc_id;
141	__u32 fb_id; /* fb object contains surface format type */	141	__u32 fb_id; /* fb object contains surface format type */
142	__u32 flags;	142	__u32 flags;
143		143
144	/* Signed dest location allows it to be partially off screen */	144	/* Signed dest location allows it to be partially off screen */
145	__s32 crtc_x, crtc_y;	145	__s32 crtc_x, crtc_y;
146	__u32 crtc_w, crtc_h;	146	__u32 crtc_w, crtc_h;
147		147
148	/* Source values are 16.16 fixed point */	148	/* Source values are 16.16 fixed point */
149	__u32 src_x, src_y;	149	__u32 src_x, src_y;
150	__u32 src_h, src_w;	150	__u32 src_h, src_w;
151	};	151	};
152		152
153	struct drm_mode_get_plane {	153	struct drm_mode_get_plane {
154	__u32 plane_id;	154	__u32 plane_id;
155		155
156	__u32 crtc_id;	156	__u32 crtc_id;
157	__u32 fb_id;	157	__u32 fb_id;
158		158
159	__u32 possible_crtcs;	159	__u32 possible_crtcs;
160	__u32 gamma_size;	160	__u32 gamma_size;
161		161
162	__u32 count_format_types;	162	__u32 count_format_types;
163	__u64 format_type_ptr;	163	__u64 format_type_ptr;
164	};	164	};
165		165
166	struct drm_mode_get_plane_res {	166	struct drm_mode_get_plane_res {
167	__u64 plane_id_ptr;	167	__u64 plane_id_ptr;
168	__u32 count_planes;	168	__u32 count_planes;
169	};	169	};
170		170
171	#define DRM_MODE_ENCODER_NONE 0	171	#define DRM_MODE_ENCODER_NONE 0
172	#define DRM_MODE_ENCODER_DAC 1	172	#define DRM_MODE_ENCODER_DAC 1
173	#define DRM_MODE_ENCODER_TMDS 2	173	#define DRM_MODE_ENCODER_TMDS 2
174	#define DRM_MODE_ENCODER_LVDS 3	174	#define DRM_MODE_ENCODER_LVDS 3
175	#define DRM_MODE_ENCODER_TVDAC 4	175	#define DRM_MODE_ENCODER_TVDAC 4
176	#define DRM_MODE_ENCODER_VIRTUAL 5	-
177	#define DRM_MODE_ENCODER_DSI 6	-
178	#define DRM_MODE_ENCODER_DPMST 7	-
179		176
180	struct drm_mode_get_encoder {	177	struct drm_mode_get_encoder {
181	__u32 encoder_id;	178	__u32 encoder_id;
182	__u32 encoder_type;	179	__u32 encoder_type;
183		180
184	__u32 crtc_id; /*< Id of crtc /	181	__u32 crtc_id; /*< Id of crtc /
185		182
186	__u32 possible_crtcs;	183	__u32 possible_crtcs;
187	__u32 possible_clones;	184	__u32 possible_clones;
188	};	185	};
189		186
190	/* This is for connectors with multiple signal types. */	187	/* This is for connectors with multiple signal types. */
191	/* Try to match DRM_MODE_CONNECTOR_X as closely as possible. */	188	/* Try to match DRM_MODE_CONNECTOR_X as closely as possible. */
192	#define DRM_MODE_SUBCONNECTOR_Automatic 0	189	#define DRM_MODE_SUBCONNECTOR_Automatic 0
193	#define DRM_MODE_SUBCONNECTOR_Unknown 0	190	#define DRM_MODE_SUBCONNECTOR_Unknown 0
194	#define DRM_MODE_SUBCONNECTOR_DVID 3	191	#define DRM_MODE_SUBCONNECTOR_DVID 3
195	#define DRM_MODE_SUBCONNECTOR_DVIA 4	192	#define DRM_MODE_SUBCONNECTOR_DVIA 4
196	#define DRM_MODE_SUBCONNECTOR_Composite 5	193	#define DRM_MODE_SUBCONNECTOR_Composite 5
197	#define DRM_MODE_SUBCONNECTOR_SVIDEO 6	194	#define DRM_MODE_SUBCONNECTOR_SVIDEO 6
198	#define DRM_MODE_SUBCONNECTOR_Component 8	195	#define DRM_MODE_SUBCONNECTOR_Component 8
199	#define DRM_MODE_SUBCONNECTOR_SCART 9	196	#define DRM_MODE_SUBCONNECTOR_SCART 9
200		197
201	#define DRM_MODE_CONNECTOR_Unknown 0	198	#define DRM_MODE_CONNECTOR_Unknown 0
202	#define DRM_MODE_CONNECTOR_VGA 1	199	#define DRM_MODE_CONNECTOR_VGA 1
203	#define DRM_MODE_CONNECTOR_DVII 2	200	#define DRM_MODE_CONNECTOR_DVII 2
204	#define DRM_MODE_CONNECTOR_DVID 3	201	#define DRM_MODE_CONNECTOR_DVID 3
205	#define DRM_MODE_CONNECTOR_DVIA 4	202	#define DRM_MODE_CONNECTOR_DVIA 4
206	#define DRM_MODE_CONNECTOR_Composite 5	203	#define DRM_MODE_CONNECTOR_Composite 5
207	#define DRM_MODE_CONNECTOR_SVIDEO 6	204	#define DRM_MODE_CONNECTOR_SVIDEO 6
208	#define DRM_MODE_CONNECTOR_LVDS 7	205	#define DRM_MODE_CONNECTOR_LVDS 7
209	#define DRM_MODE_CONNECTOR_Component 8	206	#define DRM_MODE_CONNECTOR_Component 8
210	#define DRM_MODE_CONNECTOR_9PinDIN 9	207	#define DRM_MODE_CONNECTOR_9PinDIN 9
211	#define DRM_MODE_CONNECTOR_DisplayPort 10	208	#define DRM_MODE_CONNECTOR_DisplayPort 10
212	#define DRM_MODE_CONNECTOR_HDMIA 11	209	#define DRM_MODE_CONNECTOR_HDMIA 11
213	#define DRM_MODE_CONNECTOR_HDMIB 12	210	#define DRM_MODE_CONNECTOR_HDMIB 12
214	#define DRM_MODE_CONNECTOR_TV 13	211	#define DRM_MODE_CONNECTOR_TV 13
215	#define DRM_MODE_CONNECTOR_eDP 14	212	#define DRM_MODE_CONNECTOR_eDP 14
216	#define DRM_MODE_CONNECTOR_VIRTUAL 15	-
217	#define DRM_MODE_CONNECTOR_DSI 16	-
218		213
219	struct drm_mode_get_connector {	214	struct drm_mode_get_connector {
220		215
221	__u64 encoders_ptr;	216	__u64 encoders_ptr;
222	__u64 modes_ptr;	217	__u64 modes_ptr;
223	__u64 props_ptr;	218	__u64 props_ptr;
224	__u64 prop_values_ptr;	219	__u64 prop_values_ptr;
225		220
226	__u32 count_modes;	221	__u32 count_modes;
227	__u32 count_props;	222	__u32 count_props;
228	__u32 count_encoders;	223	__u32 count_encoders;
229		224
230	__u32 encoder_id; /*< Current Encoder /	225	__u32 encoder_id; /*< Current Encoder /
231	__u32 connector_id; /*< Id /	226	__u32 connector_id; /*< Id /
232	__u32 connector_type;	227	__u32 connector_type;
233	__u32 connector_type_id;	228	__u32 connector_type_id;
234		229
235	__u32 connection;	230	__u32 connection;
236	__u32 mm_width, mm_height; /*< HxW in millimeters /	231	__u32 mm_width, mm_height; /*< HxW in millimeters /
237	__u32 subpixel;	232	__u32 subpixel;
238		-
239	__u32 pad;	-
240	};	233	};
241		234
242	#define DRM_MODE_PROP_PENDING (1<<0)	235	#define DRM_MODE_PROP_PENDING (1<<0)
243	#define DRM_MODE_PROP_RANGE (1<<1)	236	#define DRM_MODE_PROP_RANGE (1<<1)
244	#define DRM_MODE_PROP_IMMUTABLE (1<<2)	237	#define DRM_MODE_PROP_IMMUTABLE (1<<2)
245	#define DRM_MODE_PROP_ENUM (1<<3) /* enumerated type with text strings */	238	#define DRM_MODE_PROP_ENUM (1<<3) /* enumerated type with text strings */
246	#define DRM_MODE_PROP_BLOB (1<<4)	239	#define DRM_MODE_PROP_BLOB (1<<4)
247	#define DRM_MODE_PROP_BITMASK (1<<5) /* bitmask of enumerated types */	240	#define DRM_MODE_PROP_BITMASK (1<<5) /* bitmask of enumerated types */
248		-
249	/* non-extended types: legacy bitmask, one bit per type: */	-
250	#define DRM_MODE_PROP_LEGACY_TYPE ( \	-
251	DRM_MODE_PROP_RANGE \| \	-
252	DRM_MODE_PROP_ENUM \| \	-
253	DRM_MODE_PROP_BLOB \| \	-
254	DRM_MODE_PROP_BITMASK)	-
255		-
256	/* extended-types: rather than continue to consume a bit per type,	-
257	* grab a chunk of the bits to use as integer type id.	-
258	*/	-
259	#define DRM_MODE_PROP_EXTENDED_TYPE 0x0000ffc0	-
260	#define DRM_MODE_PROP_TYPE(n) ((n) << 6)	-
261	#define DRM_MODE_PROP_OBJECT DRM_MODE_PROP_TYPE(1)	-
262	#define DRM_MODE_PROP_SIGNED_RANGE DRM_MODE_PROP_TYPE(2)	-
263		241
264	struct drm_mode_property_enum {	242	struct drm_mode_property_enum {
265	__u64 value;	243	__u64 value;
266	char name[DRM_PROP_NAME_LEN];	244	char name[DRM_PROP_NAME_LEN];
267	};	245	};
268		246
269	struct drm_mode_get_property {	247	struct drm_mode_get_property {
270	__u64 values_ptr; /* values and blob lengths */	248	__u64 values_ptr; /* values and blob lengths */
271	__u64 enum_blob_ptr; /* enum and blob id ptrs */	249	__u64 enum_blob_ptr; /* enum and blob id ptrs */
272		250
273	__u32 prop_id;	251	__u32 prop_id;
274	__u32 flags;	252	__u32 flags;
275	char name[DRM_PROP_NAME_LEN];	253	char name[DRM_PROP_NAME_LEN];
276		254
277	__u32 count_values;	255	__u32 count_values;
278	__u32 count_enum_blobs;	256	__u32 count_enum_blobs;
279	};	257	};
280		258
281	struct drm_mode_connector_set_property {	259	struct drm_mode_connector_set_property {
282	__u64 value;	260	__u64 value;
283	__u32 prop_id;	261	__u32 prop_id;
284	__u32 connector_id;	262	__u32 connector_id;
285	};	263	};
-		264
-		265	#define DRM_MODE_OBJECT_CRTC 0xcccccccc
-		266	#define DRM_MODE_OBJECT_CONNECTOR 0xc0c0c0c0
-		267	#define DRM_MODE_OBJECT_ENCODER 0xe0e0e0e0
-		268	#define DRM_MODE_OBJECT_MODE 0xdededede
-		269	#define DRM_MODE_OBJECT_PROPERTY 0xb0b0b0b0
-		270	#define DRM_MODE_OBJECT_FB 0xfbfbfbfb
-		271	#define DRM_MODE_OBJECT_BLOB 0xbbbbbbbb
-		272	#define DRM_MODE_OBJECT_PLANE 0xeeeeeeee
286		273
287	struct drm_mode_obj_get_properties {	274	struct drm_mode_obj_get_properties {
288	__u64 props_ptr;	275	__u64 props_ptr;
289	__u64 prop_values_ptr;	276	__u64 prop_values_ptr;
290	__u32 count_props;	277	__u32 count_props;
291	__u32 obj_id;	278	__u32 obj_id;
292	__u32 obj_type;	279	__u32 obj_type;
293	};	280	};
294		281
295	struct drm_mode_obj_set_property {	282	struct drm_mode_obj_set_property {
296	__u64 value;	283	__u64 value;
297	__u32 prop_id;	284	__u32 prop_id;
298	__u32 obj_id;	285	__u32 obj_id;
299	__u32 obj_type;	286	__u32 obj_type;
300	};	287	};
301		288
302	struct drm_mode_get_blob {	289	struct drm_mode_get_blob {
303	__u32 blob_id;	290	__u32 blob_id;
304	__u32 length;	291	__u32 length;
305	__u64 data;	292	__u64 data;
306	};	293	};
307		294
308	struct drm_mode_fb_cmd {	295	struct drm_mode_fb_cmd {
309	__u32 fb_id;	296	__u32 fb_id;
310	__u32 width, height;	297	__u32 width, height;
311	__u32 pitch;	298	__u32 pitch;
312	__u32 bpp;	299	__u32 bpp;
313	__u32 depth;	300	__u32 depth;
314	/* driver specific handle */	301	/* driver specific handle */
315	__u32 handle;	302	__u32 handle;
316	};	303	};
317		304
318	#define DRM_MODE_FB_INTERLACED (1<<0) /* for interlaced framebuffers */	305	#define DRM_MODE_FB_INTERLACED (1<<0) /* for interlaced framebuffers */
319		306
320	struct drm_mode_fb_cmd2 {	307	struct drm_mode_fb_cmd2 {
321	__u32 fb_id;	308	__u32 fb_id;
322	__u32 width, height;	309	__u32 width, height;
323	__u32 pixel_format; /* fourcc code from drm_fourcc.h */	310	__u32 pixel_format; /* fourcc code from drm_fourcc.h */
324	__u32 flags;	311	__u32 flags;
325		312
326	/*	313	/*
327	* In case of planar formats, this ioctl allows up to 4	314	* In case of planar formats, this ioctl allows up to 4
328	* buffer objects with offsets and pitches per plane.	315	* buffer objects with offsets and pitches per plane.
329	* The pitch and offset order is dictated by the fourcc,	316	* The pitch and offset order is dictated by the fourcc,
330	* e.g. NV12 (http://fourcc.org/yuv.php#NV12) is described as:	317	* e.g. NV12 (http://fourcc.org/yuv.php#NV12) is described as:
331	*	318	*
332	* YUV 4:2:0 image with a plane of 8 bit Y samples	319	* YUV 4:2:0 image with a plane of 8 bit Y samples
333	* followed by an interleaved U/V plane containing	320	* followed by an interleaved U/V plane containing
334	* 8 bit 2x2 subsampled colour difference samples.	321	* 8 bit 2x2 subsampled colour difference samples.
335	*	322	*
336	* So it would consist of Y as offset[0] and UV as	323	* So it would consist of Y as offset[0] and UV as
337	* offset[1]. Note that offset[0] will generally	324	* offset[1]. Note that offset[0] will generally
338	* be 0.	325	* be 0.
339	*/	326	*/
340	__u32 handles[4];	327	__u32 handles[4];
341	__u32 pitches[4]; /* pitch for each plane */	328	__u32 pitches[4]; /* pitch for each plane */
342	__u32 offsets[4]; /* offset of each plane */	329	__u32 offsets[4]; /* offset of each plane */
343	};	330	};
344		331
345	#define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01	332	#define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01
346	#define DRM_MODE_FB_DIRTY_ANNOTATE_FILL 0x02	333	#define DRM_MODE_FB_DIRTY_ANNOTATE_FILL 0x02
347	#define DRM_MODE_FB_DIRTY_FLAGS 0x03	334	#define DRM_MODE_FB_DIRTY_FLAGS 0x03
348		-
349	#define DRM_MODE_FB_DIRTY_MAX_CLIPS 256	-
350		335
351	/*	336	/*
352	* Mark a region of a framebuffer as dirty.	337	* Mark a region of a framebuffer as dirty.
353	*	338	*
354	* Some hardware does not automatically update display contents	339	* Some hardware does not automatically update display contents
355	* as a hardware or software draw to a framebuffer. This ioctl	340	* as a hardware or software draw to a framebuffer. This ioctl
356	* allows userspace to tell the kernel and the hardware what	341	* allows userspace to tell the kernel and the hardware what
357	* regions of the framebuffer have changed.	342	* regions of the framebuffer have changed.
358	*	343	*
359	* The kernel or hardware is free to update more then just the	344	* The kernel or hardware is free to update more then just the
360	* region specified by the clip rects. The kernel or hardware	345	* region specified by the clip rects. The kernel or hardware
361	* may also delay and/or coalesce several calls to dirty into a	346	* may also delay and/or coalesce several calls to dirty into a
362	* single update.	347	* single update.
363	*	348	*
364	* Userspace may annotate the updates, the annotates are a	349	* Userspace may annotate the updates, the annotates are a
365	* promise made by the caller that the change is either a copy	350	* promise made by the caller that the change is either a copy
366	* of pixels or a fill of a single color in the region specified.	351	* of pixels or a fill of a single color in the region specified.
367	*	352	*
368	* If the DRM_MODE_FB_DIRTY_ANNOTATE_COPY flag is given then	353	* If the DRM_MODE_FB_DIRTY_ANNOTATE_COPY flag is given then
369	* the number of updated regions are half of num_clips given,	354	* the number of updated regions are half of num_clips given,
370	* where the clip rects are paired in src and dst. The width and	355	* where the clip rects are paired in src and dst. The width and
371	* height of each one of the pairs must match.	356	* height of each one of the pairs must match.
372	*	357	*
373	* If the DRM_MODE_FB_DIRTY_ANNOTATE_FILL flag is given the caller	358	* If the DRM_MODE_FB_DIRTY_ANNOTATE_FILL flag is given the caller
374	* promises that the region specified of the clip rects is filled	359	* promises that the region specified of the clip rects is filled
375	* completely with a single color as given in the color argument.	360	* completely with a single color as given in the color argument.
376	*/	361	*/
377		362
378	struct drm_mode_fb_dirty_cmd {	363	struct drm_mode_fb_dirty_cmd {
379	__u32 fb_id;	364	__u32 fb_id;
380	__u32 flags;	365	__u32 flags;
381	__u32 color;	366	__u32 color;
382	__u32 num_clips;	367	__u32 num_clips;
383	__u64 clips_ptr;	368	__u64 clips_ptr;
384	};	369	};
385		370
386	struct drm_mode_mode_cmd {	371	struct drm_mode_mode_cmd {
387	__u32 connector_id;	372	__u32 connector_id;
388	struct drm_mode_modeinfo mode;	373	struct drm_mode_modeinfo mode;
389	};	374	};
390		375
391	#define DRM_MODE_CURSOR_BO 0x01	376	#define DRM_MODE_CURSOR_BO (1<<0)
392	#define DRM_MODE_CURSOR_MOVE 0x02	-
393	#define DRM_MODE_CURSOR_FLAGS 0x03	377	#define DRM_MODE_CURSOR_MOVE (1<<1)
394		378
395	/*	379	/*
396	* depending on the value in flags different members are used.	380	* depending on the value in flags diffrent members are used.
397	*	381	*
398	* CURSOR_BO uses	382	* CURSOR_BO uses
399	* crtc_id	383	* crtc
400	* width	384	* width
401	* height	385	* height
402	* handle - if 0 turns the cursor off	386	* handle - if 0 turns the cursor of
403	*	387	*
404	* CURSOR_MOVE uses	388	* CURSOR_MOVE uses
405	* crtc_id	389	* crtc
406	* x	390	* x
407	* y	391	* y
408	*/	392	*/
409	struct drm_mode_cursor {	393	struct drm_mode_cursor {
410	__u32 flags;	394	__u32 flags;
411	__u32 crtc_id;	395	__u32 crtc_id;
412	__s32 x;	396	__s32 x;
413	__s32 y;	397	__s32 y;
414	__u32 width;	398	__u32 width;
415	__u32 height;	399	__u32 height;
416	/* driver specific handle */	400	/* driver specific handle */
417	__u32 handle;	401	__u32 handle;
418	};	402	};
419		403
420	struct drm_mode_cursor2 {	404	struct drm_mode_cursor2 {
421	__u32 flags;	405	__u32 flags;
422	__u32 crtc_id;	406	__u32 crtc_id;
423	__s32 x;	407	__s32 x;
424	__s32 y;	408	__s32 y;
425	__u32 width;	409	__u32 width;
426	__u32 height;	410	__u32 height;
427	/* driver specific handle */	411	/* driver specific handle */
428	__u32 handle;	412	__u32 handle;
429	__s32 hot_x;	413	__s32 hot_x;
430	__s32 hot_y;	414	__s32 hot_y;
431	};	415	};
432		416
433	struct drm_mode_crtc_lut {	417	struct drm_mode_crtc_lut {
434	__u32 crtc_id;	418	__u32 crtc_id;
435	__u32 gamma_size;	419	__u32 gamma_size;
436		420
437	/* pointers to arrays */	421	/* pointers to arrays */
438	__u64 red;	422	__u64 red;
439	__u64 green;	423	__u64 green;
440	__u64 blue;	424	__u64 blue;
441	};	425	};
442		426
443	#define DRM_MODE_PAGE_FLIP_EVENT 0x01	427	#define DRM_MODE_PAGE_FLIP_EVENT 0x01
444	#define DRM_MODE_PAGE_FLIP_ASYNC 0x02	428	#define DRM_MODE_PAGE_FLIP_ASYNC 0x02
445	#define DRM_MODE_PAGE_FLIP_FLAGS (DRM_MODE_PAGE_FLIP_EVENT\|DRM_MODE_PAGE_FLIP_ASYNC)	429	#define DRM_MODE_PAGE_FLIP_FLAGS (DRM_MODE_PAGE_FLIP_EVENT\|DRM_MODE_PAGE_FLIP_ASYNC)
446		430
447	/*	431	/*
448	* Request a page flip on the specified crtc.	432	* Request a page flip on the specified crtc.
449	*	433	*
450	* This ioctl will ask KMS to schedule a page flip for the specified	434	* This ioctl will ask KMS to schedule a page flip for the specified
451	* crtc. Once any pending rendering targeting the specified fb (as of	435	* crtc. Once any pending rendering targeting the specified fb (as of
452	* ioctl time) has completed, the crtc will be reprogrammed to display	436	* ioctl time) has completed, the crtc will be reprogrammed to display
453	* that fb after the next vertical refresh. The ioctl returns	437	* that fb after the next vertical refresh. The ioctl returns
454	* immediately, but subsequent rendering to the current fb will block	438	* immediately, but subsequent rendering to the current fb will block
455	* in the execbuffer ioctl until the page flip happens. If a page	439	* in the execbuffer ioctl until the page flip happens. If a page
456	* flip is already pending as the ioctl is called, EBUSY will be	440	* flip is already pending as the ioctl is called, EBUSY will be
457	* returned.	441	* returned.
458	*	442	*
459	* The ioctl supports one flag, DRM_MODE_PAGE_FLIP_EVENT, which will	443	* The ioctl supports one flag, DRM_MODE_PAGE_FLIP_EVENT, which will
460	* request that drm sends back a vblank event (see drm.h: struct	444	* request that drm sends back a vblank event (see drm.h: struct
461	* drm_event_vblank) when the page flip is done. The user_data field	445	* drm_event_vblank) when the page flip is done. The user_data field
462	* passed in with this ioctl will be returned as the user_data field	446	* passed in with this ioctl will be returned as the user_data field
463	* in the vblank event struct.	447	* in the vblank event struct.
464	*	448	*
465	* The reserved field must be zero until we figure out something	449	* The reserved field must be zero until we figure out something
466	* clever to use it for.	450	* clever to use it for.
467	*/	451	*/
468		452
469	struct drm_mode_crtc_page_flip {	453	struct drm_mode_crtc_page_flip {
470	__u32 crtc_id;	454	__u32 crtc_id;
471	__u32 fb_id;	455	__u32 fb_id;
472	__u32 flags;	456	__u32 flags;
473	__u32 reserved;	457	__u32 reserved;
474	__u64 user_data;	458	__u64 user_data;
475	};	459	};
476		460
477	/* create a dumb scanout buffer */	461	/* create a dumb scanout buffer */
478	struct drm_mode_create_dumb {	462	struct drm_mode_create_dumb {
479	__u32 height;	463	__u32 height;
480	__u32 width;	464	__u32 width;
481	__u32 bpp;	465	__u32 bpp;
482	__u32 flags;	466	__u32 flags;
483	/* handle, pitch, size will be returned */	467	/* handle, pitch, size will be returned */
484	__u32 handle;	468	__u32 handle;
485	__u32 pitch;	469	__u32 pitch;
486	__u64 size;	470	__u64 size;
487	};	471	};
488		472
489	/* set up for mmap of a dumb scanout buffer */	473	/* set up for mmap of a dumb scanout buffer */
490	struct drm_mode_map_dumb {	474	struct drm_mode_map_dumb {
491	/** Handle for the object being mapped. */	475	/** Handle for the object being mapped. */

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(root)/contrib/sdk/sources/libdrm/include/drm/drm_mode.h – Rev 5022 → 5068