WebSVN – Kolibri OS – Diff – /drivers/video/drm/radeon/radeon_device.c


/*
 * Copyright 2008 Advanced Micro Devices, Inc.
 * Copyright 2008 Red Hat Inc.
 * Copyright 2009 Jerome Glisse.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Dave Airlie
 *          Alex Deucher
 *          Jerome Glisse
 */
//#include 
 
#include 
#include 
#include 
#include "radeon_reg.h"
#include "radeon.h"
#include "radeon_asic.h"
#include "atom.h"
#include "display.h"
 
#include 
 
 
int radeon_dynclks          = -1;
int radeon_r4xx_atom        = 0;
int radeon_agpmode          = -1;
int radeon_gart_size        = 512; /* default gart size */
int radeon_benchmarking     = 0;
int radeon_connector_table  = 0;
int radeon_tv               = 0;
int radeon_modeset          = 1;
int radeon_new_pll          = 1;
int radeon_vram_limit       = 0;
int radeon_audio            = 0;
 
extern display_t *rdisplay;
 
void parse_cmdline(char *cmdline, videomode_t *mode, char *log, int *kms);
int init_display(struct radeon_device *rdev, videomode_t *mode);
int init_display_kms(struct radeon_device *rdev, videomode_t *mode);
 
int get_modes(videomode_t *mode, int *count);
int set_user_mode(videomode_t *mode);
int r100_2D_test(struct radeon_device *rdev);
 
 
 /* Legacy VGA regions */
#define VGA_RSRC_NONE          0x00
#define VGA_RSRC_LEGACY_IO     0x01
#define VGA_RSRC_LEGACY_MEM    0x02
#define VGA_RSRC_LEGACY_MASK   (VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM)
/* Non-legacy access */
#define VGA_RSRC_NORMAL_IO     0x04
#define VGA_RSRC_NORMAL_MEM    0x08
 
 
 
/*
 * Clear GPU surface registers.
 */
void radeon_surface_init(struct radeon_device *rdev)
{
    /* FIXME: check this out */
    if (rdev->family < CHIP_R600) {
        int i;
 
		for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
           radeon_clear_surface_reg(rdev, i);
        }
		/* enable surfaces */
		WREG32(RADEON_SURFACE_CNTL, 0);
    }
}
 
/*
 * GPU scratch registers helpers function.
 */
void radeon_scratch_init(struct radeon_device *rdev)
{
    int i;
 
    /* FIXME: check this out */
    if (rdev->family < CHIP_R300) {
        rdev->scratch.num_reg = 5;
    } else {
        rdev->scratch.num_reg = 7;
    }
    for (i = 0; i < rdev->scratch.num_reg; i++) {
        rdev->scratch.free[i] = true;
        rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4);
    }
}
 
int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
{
	int i;
 
	for (i = 0; i < rdev->scratch.num_reg; i++) {
		if (rdev->scratch.free[i]) {
			rdev->scratch.free[i] = false;
			*reg = rdev->scratch.reg[i];
			return 0;
		}
	}
	return -EINVAL;
}
 
void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
{
	int i;
 
	for (i = 0; i < rdev->scratch.num_reg; i++) {
		if (rdev->scratch.reg[i] == reg) {
			rdev->scratch.free[i] = true;
			return;
		}
	}
}
 
/*
 * MC common functions
 */
int radeon_mc_setup(struct radeon_device *rdev)
{
	uint32_t tmp;
 
	/* Some chips have an "issue" with the memory controller, the
	 * location must be aligned to the size. We just align it down,
	 * too bad if we walk over the top of system memory, we don't
	 * use DMA without a remapped anyway.
	 * Affected chips are rv280, all r3xx, and all r4xx, but not IGP
	 */
	/* FGLRX seems to setup like this, VRAM a 0, then GART.
	 */
	/*
	 * Note: from R6xx the address space is 40bits but here we only
	 * use 32bits (still have to see a card which would exhaust 4G
	 * address space).
	 */
	if (rdev->mc.vram_location != 0xFFFFFFFFUL) {
		/* vram location was already setup try to put gtt after
		 * if it fits */
		tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
		tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
		if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
			rdev->mc.gtt_location = tmp;
		} else {
			if (rdev->mc.gtt_size >= rdev->mc.vram_location) {
				printk(KERN_ERR "[drm] GTT too big to fit "
				       "before or after vram location.\n");
				return -EINVAL;
			}
			rdev->mc.gtt_location = 0;
		}
	} else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) {
		/* gtt location was already setup try to put vram before
		 * if it fits */
		if (rdev->mc.mc_vram_size < rdev->mc.gtt_location) {
			rdev->mc.vram_location = 0;
		} else {
			tmp = rdev->mc.gtt_location + rdev->mc.gtt_size;
			tmp += (rdev->mc.mc_vram_size - 1);
			tmp &= ~(rdev->mc.mc_vram_size - 1);
			if ((0xFFFFFFFFUL - tmp) >= rdev->mc.mc_vram_size) {
				rdev->mc.vram_location = tmp;
			} else {
				printk(KERN_ERR "[drm] vram too big to fit "
				       "before or after GTT location.\n");
				return -EINVAL;
			}
		}
	} else {
		rdev->mc.vram_location = 0;
		tmp = rdev->mc.mc_vram_size;
		tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
		rdev->mc.gtt_location = tmp;
	}
	rdev->mc.vram_start = rdev->mc.vram_location;
	rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
	rdev->mc.gtt_start = rdev->mc.gtt_location;
	rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
	DRM_INFO("radeon: VRAM %uM\n", (unsigned)(rdev->mc.mc_vram_size >> 20));
	DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n",
		 (unsigned)rdev->mc.vram_location,
		 (unsigned)(rdev->mc.vram_location + rdev->mc.mc_vram_size - 1));
	DRM_INFO("radeon: GTT %uM\n", (unsigned)(rdev->mc.gtt_size >> 20));
	DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n",
		 (unsigned)rdev->mc.gtt_location,
		 (unsigned)(rdev->mc.gtt_location + rdev->mc.gtt_size - 1));
	return 0;
}
 
 
/*
 * GPU helpers function.
 */
bool radeon_card_posted(struct radeon_device *rdev)
{
	uint32_t reg;
 
	/* first check CRTCs */
	if (ASIC_IS_AVIVO(rdev)) {
		reg = RREG32(AVIVO_D1CRTC_CONTROL) |
		      RREG32(AVIVO_D2CRTC_CONTROL);
		if (reg & AVIVO_CRTC_EN) {
			return true;
		}
	} else {
		reg = RREG32(RADEON_CRTC_GEN_CNTL) |
		      RREG32(RADEON_CRTC2_GEN_CNTL);
		if (reg & RADEON_CRTC_EN) {
			return true;
		}
	}
 
	/* then check MEM_SIZE, in case the crtcs are off */
	if (rdev->family >= CHIP_R600)
		reg = RREG32(R600_CONFIG_MEMSIZE);
	else
		reg = RREG32(RADEON_CONFIG_MEMSIZE);
 
	if (reg)
		return true;
 
	return false;
 
}
 
bool radeon_boot_test_post_card(struct radeon_device *rdev)
{
	if (radeon_card_posted(rdev))
		return true;
 
	if (rdev->bios) {
		DRM_INFO("GPU not posted. posting now...\n");
		if (rdev->is_atom_bios)
			atom_asic_init(rdev->mode_info.atom_context);
		else
			radeon_combios_asic_init(rdev->ddev);
		return true;
	} else {
		dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
		return false;
	}
}
 
int radeon_dummy_page_init(struct radeon_device *rdev)
{
    rdev->dummy_page.page = AllocPage();
	if (rdev->dummy_page.page == NULL)
		return -ENOMEM;
    rdev->dummy_page.addr = MapIoMem(rdev->dummy_page.page, 4096, 5);
	if (!rdev->dummy_page.addr) {
//       __free_page(rdev->dummy_page.page);
		rdev->dummy_page.page = NULL;
		return -ENOMEM;
	}
	return 0;
}
 
void radeon_dummy_page_fini(struct radeon_device *rdev)
{
	if (rdev->dummy_page.page == NULL)
		return;
    KernelFree(rdev->dummy_page.addr);
	rdev->dummy_page.page = NULL;
}
 
 
/*
 * Registers accessors functions.
 */
uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
{
    DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
    BUG_ON(1);
    return 0;
}
 
void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
{
    DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
          reg, v);
    BUG_ON(1);
}
 
void radeon_register_accessor_init(struct radeon_device *rdev)
{
    rdev->mc_rreg = &radeon_invalid_rreg;
    rdev->mc_wreg = &radeon_invalid_wreg;
    rdev->pll_rreg = &radeon_invalid_rreg;
    rdev->pll_wreg = &radeon_invalid_wreg;
    rdev->pciep_rreg = &radeon_invalid_rreg;
    rdev->pciep_wreg = &radeon_invalid_wreg;
 
    /* Don't change order as we are overridding accessor. */
    if (rdev->family < CHIP_RV515) {
		rdev->pcie_reg_mask = 0xff;
	} else {
		rdev->pcie_reg_mask = 0x7ff;
    }
    /* FIXME: not sure here */
    if (rdev->family <= CHIP_R580) {
        rdev->pll_rreg = &r100_pll_rreg;
        rdev->pll_wreg = &r100_pll_wreg;
    }
	if (rdev->family >= CHIP_R420) {
		rdev->mc_rreg = &r420_mc_rreg;
		rdev->mc_wreg = &r420_mc_wreg;
	}
    if (rdev->family >= CHIP_RV515) {
        rdev->mc_rreg = &rv515_mc_rreg;
        rdev->mc_wreg = &rv515_mc_wreg;
    }
    if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
        rdev->mc_rreg = &rs400_mc_rreg;
        rdev->mc_wreg = &rs400_mc_wreg;
    }
    if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
        rdev->mc_rreg = &rs690_mc_rreg;
        rdev->mc_wreg = &rs690_mc_wreg;
    }
    if (rdev->family == CHIP_RS600) {
        rdev->mc_rreg = &rs600_mc_rreg;
        rdev->mc_wreg = &rs600_mc_wreg;
    }
	if (rdev->family >= CHIP_R600) {
		rdev->pciep_rreg = &r600_pciep_rreg;
		rdev->pciep_wreg = &r600_pciep_wreg;
	}
}
 
 
/*
 * ASIC
 */
int radeon_asic_init(struct radeon_device *rdev)
{
    radeon_register_accessor_init(rdev);
	switch (rdev->family) {
	case CHIP_R100:
	case CHIP_RV100:
	case CHIP_RS100:
	case CHIP_RV200:
	case CHIP_RS200:
	case CHIP_R200:
	case CHIP_RV250:
	case CHIP_RS300:
	case CHIP_RV280:
        rdev->asic = &r100_asic;
		break;
	case CHIP_R300:
	case CHIP_R350:
	case CHIP_RV350:
	case CHIP_RV380:
        rdev->asic = &r300_asic;
		if (rdev->flags & RADEON_IS_PCIE) {
			rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
			rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
		}
		break;
	case CHIP_R420:
	case CHIP_R423:
	case CHIP_RV410:
        rdev->asic = &r420_asic;
		break;
	case CHIP_RS400:
	case CHIP_RS480:
       rdev->asic = &rs400_asic;
		break;
	case CHIP_RS600:
        rdev->asic = &rs600_asic;
		break;
	case CHIP_RS690:
	case CHIP_RS740:
        rdev->asic = &rs690_asic;
		break;
	case CHIP_RV515:
        rdev->asic = &rv515_asic;
		break;
	case CHIP_R520:
	case CHIP_RV530:
	case CHIP_RV560:
	case CHIP_RV570:
	case CHIP_R580:
        rdev->asic = &r520_asic;
		break;
	case CHIP_R600:
	case CHIP_RV610:
	case CHIP_RV630:
	case CHIP_RV620:
	case CHIP_RV635:
	case CHIP_RV670:
	case CHIP_RS780:
	case CHIP_RS880:
		rdev->asic = &r600_asic;
		break;
	case CHIP_RV770:
	case CHIP_RV730:
	case CHIP_RV710:
	case CHIP_RV740:
		rdev->asic = &rv770_asic;
		break;
	default:
		/* FIXME: not supported yet */
		return -EINVAL;
	}
 
	if (rdev->flags & RADEON_IS_IGP) {
		rdev->asic->get_memory_clock = NULL;
		rdev->asic->set_memory_clock = NULL;
	}
 
	return 0;
}
 
 
/*
 * Wrapper around modesetting bits.
 */
int radeon_clocks_init(struct radeon_device *rdev)
{
	int r;
 
    r = radeon_static_clocks_init(rdev->ddev);
	if (r) {
		return r;
	}
	DRM_INFO("Clocks initialized !\n");
	return 0;
}
 
void radeon_clocks_fini(struct radeon_device *rdev)
{
}
 
/* ATOM accessor methods */
static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
{
    struct radeon_device *rdev = info->dev->dev_private;
    uint32_t r;
 
    r = rdev->pll_rreg(rdev, reg);
    return r;
}
 
static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
{
    struct radeon_device *rdev = info->dev->dev_private;
 
    rdev->pll_wreg(rdev, reg, val);
}
 
static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
{
    struct radeon_device *rdev = info->dev->dev_private;
    uint32_t r;
 
    r = rdev->mc_rreg(rdev, reg);
    return r;
}
 
static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
{
    struct radeon_device *rdev = info->dev->dev_private;
 
    rdev->mc_wreg(rdev, reg, val);
}
 
static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
{
    struct radeon_device *rdev = info->dev->dev_private;
 
    WREG32(reg*4, val);
}
 
static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
{
    struct radeon_device *rdev = info->dev->dev_private;
    uint32_t r;
 
    r = RREG32(reg*4);
    return r;
}
 
int radeon_atombios_init(struct radeon_device *rdev)
{
	struct card_info *atom_card_info =
	    kzalloc(sizeof(struct card_info), GFP_KERNEL);
 
	if (!atom_card_info)
		return -ENOMEM;
 
	rdev->mode_info.atom_card_info = atom_card_info;
	atom_card_info->dev = rdev->ddev;
	atom_card_info->reg_read = cail_reg_read;
	atom_card_info->reg_write = cail_reg_write;
	atom_card_info->mc_read = cail_mc_read;
	atom_card_info->mc_write = cail_mc_write;
	atom_card_info->pll_read = cail_pll_read;
	atom_card_info->pll_write = cail_pll_write;
 
	rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
    radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
	atom_allocate_fb_scratch(rdev->mode_info.atom_context);
    return 0;
}
 
void radeon_atombios_fini(struct radeon_device *rdev)
{
	if (rdev->mode_info.atom_context) {
		kfree(rdev->mode_info.atom_context->scratch);
	kfree(rdev->mode_info.atom_context);
	}
	kfree(rdev->mode_info.atom_card_info);
}
 
int radeon_combios_init(struct radeon_device *rdev)
{
	radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
	return 0;
}
 
void radeon_combios_fini(struct radeon_device *rdev)
{
}
 
/* if we get transitioned to only one device, tak VGA back */
static unsigned int radeon_vga_set_decode(void *cookie, bool state)
{
	struct radeon_device *rdev = cookie;
	radeon_vga_set_state(rdev, state);
	if (state)
		return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
		       VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
	else
		return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
}
 
void radeon_agp_disable(struct radeon_device *rdev)
{
	rdev->flags &= ~RADEON_IS_AGP;
	if (rdev->family >= CHIP_R600) {
		DRM_INFO("Forcing AGP to PCIE mode\n");
		rdev->flags |= RADEON_IS_PCIE;
	} else if (rdev->family >= CHIP_RV515 ||
			rdev->family == CHIP_RV380 ||
			rdev->family == CHIP_RV410 ||
			rdev->family == CHIP_R423) {
		DRM_INFO("Forcing AGP to PCIE mode\n");
		rdev->flags |= RADEON_IS_PCIE;
		rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
		rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
	} else {
		DRM_INFO("Forcing AGP to PCI mode\n");
		rdev->flags |= RADEON_IS_PCI;
		rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
		rdev->asic->gart_set_page = &r100_pci_gart_set_page;
	}
	rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
}
 
void radeon_check_arguments(struct radeon_device *rdev)
{
	/* vramlimit must be a power of two */
	switch (radeon_vram_limit) {
	case 0:
	case 4:
	case 8:
	case 16:
	case 32:
	case 64:
	case 128:
	case 256:
	case 512:
	case 1024:
	case 2048:
	case 4096:
		break;
	default:
		dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
				radeon_vram_limit);
		radeon_vram_limit = 0;
		break;
	}
	radeon_vram_limit = radeon_vram_limit << 20;
	/* gtt size must be power of two and greater or equal to 32M */
	switch (radeon_gart_size) {
	case 4:
	case 8:
	case 16:
		dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n",
				radeon_gart_size);
		radeon_gart_size = 512;
		break;
	case 32:
	case 64:
	case 128:
	case 256:
	case 512:
	case 1024:
	case 2048:
	case 4096:
		break;
	default:
		dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
				radeon_gart_size);
		radeon_gart_size = 512;
		break;
	}
	rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
	/* AGP mode can only be -1, 1, 2, 4, 8 */
	switch (radeon_agpmode) {
	case -1:
	case 0:
	case 1:
	case 2:
	case 4:
	case 8:
		break;
	default:
		dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
				"-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
		radeon_agpmode = 0;
		break;
	}
}
 
int radeon_device_init(struct radeon_device *rdev,
               struct drm_device *ddev,
               struct pci_dev *pdev,
               uint32_t flags)
{
	int r;
	int dma_bits;
 
    DRM_INFO("radeon: Initializing kernel modesetting.\n");
    rdev->shutdown = false;
    rdev->ddev = ddev;
    rdev->pdev = pdev;
    rdev->flags = flags;
    rdev->family = flags & RADEON_FAMILY_MASK;
    rdev->is_atom_bios = false;
    rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
    rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
    rdev->gpu_lockup = false;
	rdev->accel_working = false;
    /* mutex initialization are all done here so we
     * can recall function without having locking issues */
 //   mutex_init(&rdev->cs_mutex);
 //   mutex_init(&rdev->ib_pool.mutex);
 //   mutex_init(&rdev->cp.mutex);
 //   rwlock_init(&rdev->fence_drv.lock);
 
	/* Set asic functions */
	r = radeon_asic_init(rdev);
	if (r)
		return r;
	radeon_check_arguments(rdev);
 
	if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
		radeon_agp_disable(rdev);
    }
 
	/* set DMA mask + need_dma32 flags.
	 * PCIE - can handle 40-bits.
	 * IGP - can handle 40-bits (in theory)
	 * AGP - generally dma32 is safest
	 * PCI - only dma32
	 */
	rdev->need_dma32 = false;
	if (rdev->flags & RADEON_IS_AGP)
		rdev->need_dma32 = true;
	if (rdev->flags & RADEON_IS_PCI)
		rdev->need_dma32 = true;
 
	dma_bits = rdev->need_dma32 ? 32 : 40;
	r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
    if (r) {
        printk(KERN_WARNING "radeon: No suitable DMA available.\n");
    }
 
    /* Registers mapping */
    /* TODO: block userspace mapping of io register */
    rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
 
    rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
 
    rdev->rmmio =  (void*)MapIoMem(rdev->rmmio_base, rdev->rmmio_size,
                                   PG_SW+PG_NOCACHE);
 
    if (rdev->rmmio == NULL) {
        return -ENOMEM;
    }
    DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
    DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
 
	/* if we have > 1 VGA cards, then disable the radeon VGA resources */
//	r = vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
//	if (r) {
//		return -EINVAL;
//	}
 
	r = radeon_init(rdev);
	if (r)
            return r;
 
	if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
		/* Acceleration not working on AGP card try again
		 * with fallback to PCI or PCIE GART
		 */
		radeon_gpu_reset(rdev);
		radeon_fini(rdev);
		radeon_agp_disable(rdev);
		r = radeon_init(rdev);
		if (r)
		return r;
	}
//	if (radeon_testing) {
//		radeon_test_moves(rdev);
//    }
//	if (radeon_benchmarking) {
//		radeon_benchmark(rdev);
//    }
	return 0;
}
 
 
/*
 * Driver load/unload
 */
int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
{
    struct radeon_device *rdev;
    int r;
 
    ENTER();
 
    rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
    if (rdev == NULL) {
        return -ENOMEM;
    };
 
    dev->dev_private = (void *)rdev;
 
    /* update BUS flag */
    if (drm_device_is_agp(dev)) {
        flags |= RADEON_IS_AGP;
    } else if (drm_device_is_pcie(dev)) {
        flags |= RADEON_IS_PCIE;
    } else {
        flags |= RADEON_IS_PCI;
    }
 
    /* radeon_device_init should report only fatal error
     * like memory allocation failure or iomapping failure,
     * or memory manager initialization failure, it must
     * properly initialize the GPU MC controller and permit
     * VRAM allocation
     */
    r = radeon_device_init(rdev, dev, dev->pdev, flags);
    if (r) {
        DRM_ERROR("Fatal error while trying to initialize radeon.\n");
        return r;
    }
    /* Again modeset_init should fail only on fatal error
     * otherwise it should provide enough functionalities
     * for shadowfb to run
     */
    if( radeon_modeset )
    {
        r = radeon_modeset_init(rdev);
        if (r) {
            return r;
        }
    };
    return 0;
}
 
videomode_t usermode;
 
 
int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent)
{
    static struct drm_device *dev;
    int ret;
 
    ENTER();
 
    dev = kzalloc(sizeof(*dev), 0);
    if (!dev)
        return -ENOMEM;
 
 //   ret = pci_enable_device(pdev);
 //   if (ret)
 //       goto err_g1;
 
 //   pci_set_master(pdev);
 
 //   if ((ret = drm_fill_in_dev(dev, pdev, ent, driver))) {
 //       printk(KERN_ERR "DRM: Fill_in_dev failed.\n");
 //       goto err_g2;
 //   }
 
    dev->pdev = pdev;
    dev->pci_device = pdev->device;
    dev->pci_vendor = pdev->vendor;
 
    ret = radeon_driver_load_kms(dev, ent->driver_data );
    if (ret)
        goto err_g4;
 
    if( radeon_modeset )
        init_display_kms(dev->dev_private, &usermode);
    else
        init_display(dev->dev_private, &usermode);
 
    LEAVE();
 
    return 0;
 
err_g4:
//    drm_put_minor(&dev->primary);
//err_g3:
//    if (drm_core_check_feature(dev, DRIVER_MODESET))
//        drm_put_minor(&dev->control);
//err_g2:
//    pci_disable_device(pdev);
//err_g1:
    free(dev);
 
    LEAVE();
 
    return ret;
}
 
resource_size_t drm_get_resource_start(struct drm_device *dev, unsigned int resource)
{
    return pci_resource_start(dev->pdev, resource);
}
 
resource_size_t drm_get_resource_len(struct drm_device *dev, unsigned int resource)
{
    return pci_resource_len(dev->pdev, resource);
}
 
 
uint32_t __div64_32(uint64_t *n, uint32_t base)
{
        uint64_t rem = *n;
        uint64_t b = base;
        uint64_t res, d = 1;
        uint32_t high = rem >> 32;
 
        /* Reduce the thing a bit first */
        res = 0;
        if (high >= base) {
                high /= base;
                res = (uint64_t) high << 32;
                rem -= (uint64_t) (high*base) << 32;
        }
 
        while ((int64_t)b > 0 && b < rem) {
                b = b+b;
                d = d+d;
        }
 
        do {
                if (rem >= b) {
                        rem -= b;
                        res += d;
                }
                b >>= 1;
                d >>= 1;
        } while (d);
 
        *n = res;
        return rem;
}
 
 
static struct pci_device_id pciidlist[] = {
    radeon_PCI_IDS
};
 
 
#define API_VERSION     0x01000100
 
#define SRV_GETVERSION  0
#define SRV_ENUM_MODES  1
#define SRV_SET_MODE    2
 
int _stdcall display_handler(ioctl_t *io)
{
    int    retval = -1;
    u32_t *inp;
    u32_t *outp;
 
    inp = io->input;
    outp = io->output;
 
    switch(io->io_code)
    {
        case SRV_GETVERSION:
            if(io->out_size==4)
            {
                *outp  = API_VERSION;
                retval = 0;
            }
            break;
 
        case SRV_ENUM_MODES:
            dbgprintf("SRV_ENUM_MODES inp %x inp_size %x out_size %x\n",
                       inp, io->inp_size, io->out_size );
 
            if( radeon_modeset &&
                (outp != NULL) && (io->out_size == 4) &&
                (io->inp_size == *outp * sizeof(videomode_t)) )
            {
                retval = get_modes((videomode_t*)inp, outp);
            };
            break;
 
        case SRV_SET_MODE:
            dbgprintf("SRV_SET_MODE inp %x inp_size %x\n",
                       inp, io->inp_size);
 
            if(  radeon_modeset   &&
                (inp != NULL) &&
                (io->inp_size == sizeof(videomode_t)) )
            {
                retval = set_user_mode((videomode_t*)inp);
            };
            break;
    };
 
    return retval;
}
 
static char  log[256];
static pci_dev_t device;
 
u32_t drvEntry(int action, char *cmdline)
{
    struct radeon_device *rdev = NULL;
 
    struct pci_device_id  *ent;
 
    int     err;
    u32_t   retval = 0;
 
    if(action != 1)
        return 0;
 
    if( GetService("DISPLAY") != 0 )
        return 0;
 
    if( cmdline && *cmdline )
        parse_cmdline(cmdline, &usermode, log, &radeon_modeset);
 
    if(!dbg_open(log))
    {
        strcpy(log, "/rd/1/drivers/atikms.log");
 
        if(!dbg_open(log))
        {
            printf("Can't open %s\nExit\n", log);
            return 0;
        };
    }
    dbgprintf("Radeon RC9 cmdline %s\n", cmdline);
 
    enum_pci_devices();
 
    ent = find_pci_device(&device, pciidlist);
 
    if( unlikely(ent == NULL) )
    {
        dbgprintf("device not found\n");
        return 0;
    };
 
    dbgprintf("device %x:%x\n", device.pci_dev.vendor,
                                device.pci_dev.device);
 
    err = drm_get_dev(&device.pci_dev, ent);
 
    rdev = rdisplay->ddev->dev_private;
 
    if( (rdev->asic == &r600_asic) ||
        (rdev->asic == &rv770_asic))
        r600_2D_test(rdev);
    else
        r100_2D_test(rdev);
 
    err = RegService("DISPLAY", display_handler);
 
    if( err != 0)
        dbgprintf("Set DISPLAY handler\n");
 
    return err;
};

Rev 1414	Rev 1428
1	/*	1	/*
2	* Copyright 2008 Advanced Micro Devices, Inc.	2	* Copyright 2008 Advanced Micro Devices, Inc.
3	* Copyright 2008 Red Hat Inc.	3	* Copyright 2008 Red Hat Inc.
4	* Copyright 2009 Jerome Glisse.	4	* Copyright 2009 Jerome Glisse.
5	*	5	*
6	* Permission is hereby granted, free of charge, to any person obtaining a	6	* Permission is hereby granted, free of charge, to any person obtaining a
7	* copy of this software and associated documentation files (the "Software"),	7	* copy of this software and associated documentation files (the "Software"),
8	* to deal in the Software without restriction, including without limitation	8	* to deal in the Software without restriction, including without limitation
9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
10	* and/or sell copies of the Software, and to permit persons to whom the	10	* and/or sell copies of the Software, and to permit persons to whom the
11	* Software is furnished to do so, subject to the following conditions:	11	* Software is furnished to do so, subject to the following conditions:
12	*	12	*
13	* The above copyright notice and this permission notice shall be included in	13	* The above copyright notice and this permission notice shall be included in
14	* all copies or substantial portions of the Software.	14	* all copies or substantial portions of the Software.
15	*	15	*
16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR	19	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22	* OTHER DEALINGS IN THE SOFTWARE.	22	* OTHER DEALINGS IN THE SOFTWARE.
23	*	23	*
24	* Authors: Dave Airlie	24	* Authors: Dave Airlie
25	* Alex Deucher	25	* Alex Deucher
26	* Jerome Glisse	26	* Jerome Glisse
27	*/	27	*/
28	//#include	28	//#include
29		29
30	#include	30	#include
31	#include	31	#include
32	#include	32	#include
33	#include "radeon_reg.h"	33	#include "radeon_reg.h"
34	#include "radeon.h"	34	#include "radeon.h"
35	#include "radeon_asic.h"	35	#include "radeon_asic.h"
36	#include "atom.h"	36	#include "atom.h"
-		37	#include "display.h"
37		38
38	#include	39	#include
39		40
40		41
41	int radeon_dynclks = -1;	42	int radeon_dynclks = -1;
42	int radeon_r4xx_atom = 0;	43	int radeon_r4xx_atom = 0;
43	int radeon_agpmode = -1;	44	int radeon_agpmode = -1;
44	int radeon_gart_size = 512; /* default gart size */	45	int radeon_gart_size = 512; /* default gart size */
45	int radeon_benchmarking = 0;	46	int radeon_benchmarking = 0;
46	int radeon_connector_table = 0;	47	int radeon_connector_table = 0;
47	int radeon_tv = 0;	48	int radeon_tv = 0;
48	int radeon_modeset = 1;	49	int radeon_modeset = 1;
49	int radeon_new_pll = 1;	50	int radeon_new_pll = 1;
50	int radeon_vram_limit = 0;	51	int radeon_vram_limit = 0;
51	int radeon_audio = 0;	52	int radeon_audio = 0;
-		53
52		54	extern display_t *rdisplay;
53		55
54	void parse_cmdline(char cmdline, videomode_t mode, char log, int kms);	56	void parse_cmdline(char cmdline, videomode_t mode, char log, int kms);
55	int init_display(struct radeon_device rdev, videomode_t mode);	57	int init_display(struct radeon_device rdev, videomode_t mode);
56	int init_display_kms(struct radeon_device rdev, videomode_t mode);	58	int init_display_kms(struct radeon_device rdev, videomode_t mode);
57		59
58	int get_modes(videomode_t mode, int count);	60	int get_modes(videomode_t mode, int count);
59	int set_user_mode(videomode_t *mode);	61	int set_user_mode(videomode_t *mode);
-		62	int r100_2D_test(struct radeon_device *rdev);
60		63
61		64
62	/* Legacy VGA regions */	65	/* Legacy VGA regions */
63	#define VGA_RSRC_NONE 0x00	66	#define VGA_RSRC_NONE 0x00
64	#define VGA_RSRC_LEGACY_IO 0x01	67	#define VGA_RSRC_LEGACY_IO 0x01
65	#define VGA_RSRC_LEGACY_MEM 0x02	68	#define VGA_RSRC_LEGACY_MEM 0x02
66	#define VGA_RSRC_LEGACY_MASK (VGA_RSRC_LEGACY_IO \| VGA_RSRC_LEGACY_MEM)	69	#define VGA_RSRC_LEGACY_MASK (VGA_RSRC_LEGACY_IO \| VGA_RSRC_LEGACY_MEM)
67	/* Non-legacy access */	70	/* Non-legacy access */
68	#define VGA_RSRC_NORMAL_IO 0x04	71	#define VGA_RSRC_NORMAL_IO 0x04
69	#define VGA_RSRC_NORMAL_MEM 0x08	72	#define VGA_RSRC_NORMAL_MEM 0x08
70		73
71		74
72		75
73	/*	76	/*
74	* Clear GPU surface registers.	77	* Clear GPU surface registers.
75	*/	78	*/
76	void radeon_surface_init(struct radeon_device *rdev)	79	void radeon_surface_init(struct radeon_device *rdev)
77	{	80	{
78	/* FIXME: check this out */	81	/* FIXME: check this out */
79	if (rdev->family < CHIP_R600) {	82	if (rdev->family < CHIP_R600) {
80	int i;	83	int i;
81		84
82	for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {	85	for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
83	radeon_clear_surface_reg(rdev, i);	86	radeon_clear_surface_reg(rdev, i);
84	}	87	}
85	/* enable surfaces */	88	/* enable surfaces */
86	WREG32(RADEON_SURFACE_CNTL, 0);	89	WREG32(RADEON_SURFACE_CNTL, 0);
87	}	90	}
88	}	91	}
89		92
90	/*	93	/*
91	* GPU scratch registers helpers function.	94	* GPU scratch registers helpers function.
92	*/	95	*/
93	void radeon_scratch_init(struct radeon_device *rdev)	96	void radeon_scratch_init(struct radeon_device *rdev)
94	{	97	{
95	int i;	98	int i;
96		99
97	/* FIXME: check this out */	100	/* FIXME: check this out */
98	if (rdev->family < CHIP_R300) {	101	if (rdev->family < CHIP_R300) {
99	rdev->scratch.num_reg = 5;	102	rdev->scratch.num_reg = 5;
100	} else {	103	} else {
101	rdev->scratch.num_reg = 7;	104	rdev->scratch.num_reg = 7;
102	}	105	}
103	for (i = 0; i < rdev->scratch.num_reg; i++) {	106	for (i = 0; i < rdev->scratch.num_reg; i++) {
104	rdev->scratch.free[i] = true;	107	rdev->scratch.free[i] = true;
105	rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4);	108	rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4);
106	}	109	}
107	}	110	}
108		111
109	int radeon_scratch_get(struct radeon_device rdev, uint32_t reg)	112	int radeon_scratch_get(struct radeon_device rdev, uint32_t reg)
110	{	113	{
111	int i;	114	int i;
112		115
113	for (i = 0; i < rdev->scratch.num_reg; i++) {	116	for (i = 0; i < rdev->scratch.num_reg; i++) {
114	if (rdev->scratch.free[i]) {	117	if (rdev->scratch.free[i]) {
115	rdev->scratch.free[i] = false;	118	rdev->scratch.free[i] = false;
116	*reg = rdev->scratch.reg[i];	119	*reg = rdev->scratch.reg[i];
117	return 0;	120	return 0;
118	}	121	}
119	}	122	}
120	return -EINVAL;	123	return -EINVAL;
121	}	124	}
122		125
123	void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)	126	void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
124	{	127	{
125	int i;	128	int i;
126		129
127	for (i = 0; i < rdev->scratch.num_reg; i++) {	130	for (i = 0; i < rdev->scratch.num_reg; i++) {
128	if (rdev->scratch.reg[i] == reg) {	131	if (rdev->scratch.reg[i] == reg) {
129	rdev->scratch.free[i] = true;	132	rdev->scratch.free[i] = true;
130	return;	133	return;
131	}	134	}
132	}	135	}
133	}	136	}
134		137
135	/*	138	/*
136	* MC common functions	139	* MC common functions
137	*/	140	*/
138	int radeon_mc_setup(struct radeon_device *rdev)	141	int radeon_mc_setup(struct radeon_device *rdev)
139	{	142	{
140	uint32_t tmp;	143	uint32_t tmp;
141		144
142	/* Some chips have an "issue" with the memory controller, the	145	/* Some chips have an "issue" with the memory controller, the
143	* location must be aligned to the size. We just align it down,	146	* location must be aligned to the size. We just align it down,
144	* too bad if we walk over the top of system memory, we don't	147	* too bad if we walk over the top of system memory, we don't
145	* use DMA without a remapped anyway.	148	* use DMA without a remapped anyway.
146	* Affected chips are rv280, all r3xx, and all r4xx, but not IGP	149	* Affected chips are rv280, all r3xx, and all r4xx, but not IGP
147	*/	150	*/
148	/* FGLRX seems to setup like this, VRAM a 0, then GART.	151	/* FGLRX seems to setup like this, VRAM a 0, then GART.
149	*/	152	*/
150	/*	153	/*
151	* Note: from R6xx the address space is 40bits but here we only	154	* Note: from R6xx the address space is 40bits but here we only
152	* use 32bits (still have to see a card which would exhaust 4G	155	* use 32bits (still have to see a card which would exhaust 4G
153	* address space).	156	* address space).
154	*/	157	*/
155	if (rdev->mc.vram_location != 0xFFFFFFFFUL) {	158	if (rdev->mc.vram_location != 0xFFFFFFFFUL) {
156	/* vram location was already setup try to put gtt after	159	/* vram location was already setup try to put gtt after
157	* if it fits */	160	* if it fits */
158	tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;	161	tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
159	tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);	162	tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
160	if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {	163	if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
161	rdev->mc.gtt_location = tmp;	164	rdev->mc.gtt_location = tmp;
162	} else {	165	} else {
163	if (rdev->mc.gtt_size >= rdev->mc.vram_location) {	166	if (rdev->mc.gtt_size >= rdev->mc.vram_location) {
164	printk(KERN_ERR "[drm] GTT too big to fit "	167	printk(KERN_ERR "[drm] GTT too big to fit "
165	"before or after vram location.\n");	168	"before or after vram location.\n");
166	return -EINVAL;	169	return -EINVAL;
167	}	170	}
168	rdev->mc.gtt_location = 0;	171	rdev->mc.gtt_location = 0;
169	}	172	}
170	} else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) {	173	} else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) {
171	/* gtt location was already setup try to put vram before	174	/* gtt location was already setup try to put vram before
172	* if it fits */	175	* if it fits */
173	if (rdev->mc.mc_vram_size < rdev->mc.gtt_location) {	176	if (rdev->mc.mc_vram_size < rdev->mc.gtt_location) {
174	rdev->mc.vram_location = 0;	177	rdev->mc.vram_location = 0;
175	} else {	178	} else {
176	tmp = rdev->mc.gtt_location + rdev->mc.gtt_size;	179	tmp = rdev->mc.gtt_location + rdev->mc.gtt_size;
177	tmp += (rdev->mc.mc_vram_size - 1);	180	tmp += (rdev->mc.mc_vram_size - 1);
178	tmp &= ~(rdev->mc.mc_vram_size - 1);	181	tmp &= ~(rdev->mc.mc_vram_size - 1);
179	if ((0xFFFFFFFFUL - tmp) >= rdev->mc.mc_vram_size) {	182	if ((0xFFFFFFFFUL - tmp) >= rdev->mc.mc_vram_size) {
180	rdev->mc.vram_location = tmp;	183	rdev->mc.vram_location = tmp;
181	} else {	184	} else {
182	printk(KERN_ERR "[drm] vram too big to fit "	185	printk(KERN_ERR "[drm] vram too big to fit "
183	"before or after GTT location.\n");	186	"before or after GTT location.\n");
184	return -EINVAL;	187	return -EINVAL;
185	}	188	}
186	}	189	}
187	} else {	190	} else {
188	rdev->mc.vram_location = 0;	191	rdev->mc.vram_location = 0;
189	tmp = rdev->mc.mc_vram_size;	192	tmp = rdev->mc.mc_vram_size;
190	tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);	193	tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
191	rdev->mc.gtt_location = tmp;	194	rdev->mc.gtt_location = tmp;
192	}	195	}
193	rdev->mc.vram_start = rdev->mc.vram_location;	196	rdev->mc.vram_start = rdev->mc.vram_location;
194	rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;	197	rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
195	rdev->mc.gtt_start = rdev->mc.gtt_location;	198	rdev->mc.gtt_start = rdev->mc.gtt_location;
196	rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;	199	rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
197	DRM_INFO("radeon: VRAM %uM\n", (unsigned)(rdev->mc.mc_vram_size >> 20));	200	DRM_INFO("radeon: VRAM %uM\n", (unsigned)(rdev->mc.mc_vram_size >> 20));
198	DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n",	201	DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n",
199	(unsigned)rdev->mc.vram_location,	202	(unsigned)rdev->mc.vram_location,
200	(unsigned)(rdev->mc.vram_location + rdev->mc.mc_vram_size - 1));	203	(unsigned)(rdev->mc.vram_location + rdev->mc.mc_vram_size - 1));
201	DRM_INFO("radeon: GTT %uM\n", (unsigned)(rdev->mc.gtt_size >> 20));	204	DRM_INFO("radeon: GTT %uM\n", (unsigned)(rdev->mc.gtt_size >> 20));
202	DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n",	205	DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n",
203	(unsigned)rdev->mc.gtt_location,	206	(unsigned)rdev->mc.gtt_location,
204	(unsigned)(rdev->mc.gtt_location + rdev->mc.gtt_size - 1));	207	(unsigned)(rdev->mc.gtt_location + rdev->mc.gtt_size - 1));
205	return 0;	208	return 0;
206	}	209	}
207		210
208		211
209	/*	212	/*
210	* GPU helpers function.	213	* GPU helpers function.
211	*/	214	*/
212	bool radeon_card_posted(struct radeon_device *rdev)	215	bool radeon_card_posted(struct radeon_device *rdev)
213	{	216	{
214	uint32_t reg;	217	uint32_t reg;
215		218
216	/* first check CRTCs */	219	/* first check CRTCs */
217	if (ASIC_IS_AVIVO(rdev)) {	220	if (ASIC_IS_AVIVO(rdev)) {
218	reg = RREG32(AVIVO_D1CRTC_CONTROL) \|	221	reg = RREG32(AVIVO_D1CRTC_CONTROL) \|
219	RREG32(AVIVO_D2CRTC_CONTROL);	222	RREG32(AVIVO_D2CRTC_CONTROL);
220	if (reg & AVIVO_CRTC_EN) {	223	if (reg & AVIVO_CRTC_EN) {
221	return true;	224	return true;
222	}	225	}
223	} else {	226	} else {
224	reg = RREG32(RADEON_CRTC_GEN_CNTL) \|	227	reg = RREG32(RADEON_CRTC_GEN_CNTL) \|
225	RREG32(RADEON_CRTC2_GEN_CNTL);	228	RREG32(RADEON_CRTC2_GEN_CNTL);
226	if (reg & RADEON_CRTC_EN) {	229	if (reg & RADEON_CRTC_EN) {
227	return true;	230	return true;
228	}	231	}
229	}	232	}
230		233
231	/* then check MEM_SIZE, in case the crtcs are off */	234	/* then check MEM_SIZE, in case the crtcs are off */
232	if (rdev->family >= CHIP_R600)	235	if (rdev->family >= CHIP_R600)
233	reg = RREG32(R600_CONFIG_MEMSIZE);	236	reg = RREG32(R600_CONFIG_MEMSIZE);
234	else	237	else
235	reg = RREG32(RADEON_CONFIG_MEMSIZE);	238	reg = RREG32(RADEON_CONFIG_MEMSIZE);
236		239
237	if (reg)	240	if (reg)
238	return true;	241	return true;
239		242
240	return false;	243	return false;
241		244
242	}	245	}
243		246
244	bool radeon_boot_test_post_card(struct radeon_device *rdev)	247	bool radeon_boot_test_post_card(struct radeon_device *rdev)
245	{	248	{
246	if (radeon_card_posted(rdev))	249	if (radeon_card_posted(rdev))
247	return true;	250	return true;
248		251
249	if (rdev->bios) {	252	if (rdev->bios) {
250	DRM_INFO("GPU not posted. posting now...\n");	253	DRM_INFO("GPU not posted. posting now...\n");
251	if (rdev->is_atom_bios)	254	if (rdev->is_atom_bios)
252	atom_asic_init(rdev->mode_info.atom_context);	255	atom_asic_init(rdev->mode_info.atom_context);
253	else	256	else
254	radeon_combios_asic_init(rdev->ddev);	257	radeon_combios_asic_init(rdev->ddev);
255	return true;	258	return true;
256	} else {	259	} else {
257	dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");	260	dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
258	return false;	261	return false;
259	}	262	}
260	}	263	}
261		264
262	int radeon_dummy_page_init(struct radeon_device *rdev)	265	int radeon_dummy_page_init(struct radeon_device *rdev)
263	{	266	{
264	rdev->dummy_page.page = AllocPage();	267	rdev->dummy_page.page = AllocPage();
265	if (rdev->dummy_page.page == NULL)	268	if (rdev->dummy_page.page == NULL)
266	return -ENOMEM;	269	return -ENOMEM;
267	rdev->dummy_page.addr = MapIoMem(rdev->dummy_page.page, 4096, 5);	270	rdev->dummy_page.addr = MapIoMem(rdev->dummy_page.page, 4096, 5);
268	if (!rdev->dummy_page.addr) {	271	if (!rdev->dummy_page.addr) {
269	// __free_page(rdev->dummy_page.page);	272	// __free_page(rdev->dummy_page.page);
270	rdev->dummy_page.page = NULL;	273	rdev->dummy_page.page = NULL;
271	return -ENOMEM;	274	return -ENOMEM;
272	}	275	}
273	return 0;	276	return 0;
274	}	277	}
275		278
276	void radeon_dummy_page_fini(struct radeon_device *rdev)	279	void radeon_dummy_page_fini(struct radeon_device *rdev)
277	{	280	{
278	if (rdev->dummy_page.page == NULL)	281	if (rdev->dummy_page.page == NULL)
279	return;	282	return;
280	KernelFree(rdev->dummy_page.addr);	283	KernelFree(rdev->dummy_page.addr);
281	rdev->dummy_page.page = NULL;	284	rdev->dummy_page.page = NULL;
282	}	285	}
283		286
284		287
285	/*	288	/*
286	* Registers accessors functions.	289	* Registers accessors functions.
287	*/	290	*/
288	uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)	291	uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
289	{	292	{
290	DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);	293	DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
291	BUG_ON(1);	294	BUG_ON(1);
292	return 0;	295	return 0;
293	}	296	}
294		297
295	void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)	298	void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
296	{	299	{
297	DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",	300	DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
298	reg, v);	301	reg, v);
299	BUG_ON(1);	302	BUG_ON(1);
300	}	303	}
301		304
302	void radeon_register_accessor_init(struct radeon_device *rdev)	305	void radeon_register_accessor_init(struct radeon_device *rdev)
303	{	306	{
304	rdev->mc_rreg = &radeon_invalid_rreg;	307	rdev->mc_rreg = &radeon_invalid_rreg;
305	rdev->mc_wreg = &radeon_invalid_wreg;	308	rdev->mc_wreg = &radeon_invalid_wreg;
306	rdev->pll_rreg = &radeon_invalid_rreg;	309	rdev->pll_rreg = &radeon_invalid_rreg;
307	rdev->pll_wreg = &radeon_invalid_wreg;	310	rdev->pll_wreg = &radeon_invalid_wreg;
308	rdev->pciep_rreg = &radeon_invalid_rreg;	311	rdev->pciep_rreg = &radeon_invalid_rreg;
309	rdev->pciep_wreg = &radeon_invalid_wreg;	312	rdev->pciep_wreg = &radeon_invalid_wreg;
310		313
311	/* Don't change order as we are overridding accessor. */	314	/* Don't change order as we are overridding accessor. */
312	if (rdev->family < CHIP_RV515) {	315	if (rdev->family < CHIP_RV515) {
313	rdev->pcie_reg_mask = 0xff;	316	rdev->pcie_reg_mask = 0xff;
314	} else {	317	} else {
315	rdev->pcie_reg_mask = 0x7ff;	318	rdev->pcie_reg_mask = 0x7ff;
316	}	319	}
317	/* FIXME: not sure here */	320	/* FIXME: not sure here */
318	if (rdev->family <= CHIP_R580) {	321	if (rdev->family <= CHIP_R580) {
319	rdev->pll_rreg = &r100_pll_rreg;	322	rdev->pll_rreg = &r100_pll_rreg;
320	rdev->pll_wreg = &r100_pll_wreg;	323	rdev->pll_wreg = &r100_pll_wreg;
321	}	324	}
322	if (rdev->family >= CHIP_R420) {	325	if (rdev->family >= CHIP_R420) {
323	rdev->mc_rreg = &r420_mc_rreg;	326	rdev->mc_rreg = &r420_mc_rreg;
324	rdev->mc_wreg = &r420_mc_wreg;	327	rdev->mc_wreg = &r420_mc_wreg;
325	}	328	}
326	if (rdev->family >= CHIP_RV515) {	329	if (rdev->family >= CHIP_RV515) {
327	rdev->mc_rreg = &rv515_mc_rreg;	330	rdev->mc_rreg = &rv515_mc_rreg;
328	rdev->mc_wreg = &rv515_mc_wreg;	331	rdev->mc_wreg = &rv515_mc_wreg;
329	}	332	}
330	if (rdev->family == CHIP_RS400 \|\| rdev->family == CHIP_RS480) {	333	if (rdev->family == CHIP_RS400 \|\| rdev->family == CHIP_RS480) {
331	rdev->mc_rreg = &rs400_mc_rreg;	334	rdev->mc_rreg = &rs400_mc_rreg;
332	rdev->mc_wreg = &rs400_mc_wreg;	335	rdev->mc_wreg = &rs400_mc_wreg;
333	}	336	}
334	if (rdev->family == CHIP_RS690 \|\| rdev->family == CHIP_RS740) {	337	if (rdev->family == CHIP_RS690 \|\| rdev->family == CHIP_RS740) {
335	rdev->mc_rreg = &rs690_mc_rreg;	338	rdev->mc_rreg = &rs690_mc_rreg;
336	rdev->mc_wreg = &rs690_mc_wreg;	339	rdev->mc_wreg = &rs690_mc_wreg;
337	}	340	}
338	if (rdev->family == CHIP_RS600) {	341	if (rdev->family == CHIP_RS600) {
339	rdev->mc_rreg = &rs600_mc_rreg;	342	rdev->mc_rreg = &rs600_mc_rreg;
340	rdev->mc_wreg = &rs600_mc_wreg;	343	rdev->mc_wreg = &rs600_mc_wreg;
341	}	344	}
342	if (rdev->family >= CHIP_R600) {	345	if (rdev->family >= CHIP_R600) {
343	rdev->pciep_rreg = &r600_pciep_rreg;	346	rdev->pciep_rreg = &r600_pciep_rreg;
344	rdev->pciep_wreg = &r600_pciep_wreg;	347	rdev->pciep_wreg = &r600_pciep_wreg;
345	}	348	}
346	}	349	}
347		350
348		351
349	/*	352	/*
350	* ASIC	353	* ASIC
351	*/	354	*/
352	int radeon_asic_init(struct radeon_device *rdev)	355	int radeon_asic_init(struct radeon_device *rdev)
353	{	356	{
354	radeon_register_accessor_init(rdev);	357	radeon_register_accessor_init(rdev);
355	switch (rdev->family) {	358	switch (rdev->family) {
356	case CHIP_R100:	359	case CHIP_R100:
357	case CHIP_RV100:	360	case CHIP_RV100:
358	case CHIP_RS100:	361	case CHIP_RS100:
359	case CHIP_RV200:	362	case CHIP_RV200:
360	case CHIP_RS200:	363	case CHIP_RS200:
361	case CHIP_R200:	364	case CHIP_R200:
362	case CHIP_RV250:	365	case CHIP_RV250:
363	case CHIP_RS300:	366	case CHIP_RS300:
364	case CHIP_RV280:	367	case CHIP_RV280:
365	rdev->asic = &r100_asic;	368	rdev->asic = &r100_asic;
366	break;	369	break;
367	case CHIP_R300:	370	case CHIP_R300:
368	case CHIP_R350:	371	case CHIP_R350:
369	case CHIP_RV350:	372	case CHIP_RV350:
370	case CHIP_RV380:	373	case CHIP_RV380:
371	rdev->asic = &r300_asic;	374	rdev->asic = &r300_asic;
372	if (rdev->flags & RADEON_IS_PCIE) {	375	if (rdev->flags & RADEON_IS_PCIE) {
373	rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;	376	rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
374	rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;	377	rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
375	}	378	}
376	break;	379	break;
377	case CHIP_R420:	380	case CHIP_R420:
378	case CHIP_R423:	381	case CHIP_R423:
379	case CHIP_RV410:	382	case CHIP_RV410:
380	rdev->asic = &r420_asic;	383	rdev->asic = &r420_asic;
381	break;	384	break;
382	case CHIP_RS400:	385	case CHIP_RS400:
383	case CHIP_RS480:	386	case CHIP_RS480:
384	rdev->asic = &rs400_asic;	387	rdev->asic = &rs400_asic;
385	break;	388	break;
386	case CHIP_RS600:	389	case CHIP_RS600:
387	rdev->asic = &rs600_asic;	390	rdev->asic = &rs600_asic;
388	break;	391	break;
389	case CHIP_RS690:	392	case CHIP_RS690:
390	case CHIP_RS740:	393	case CHIP_RS740:
391	rdev->asic = &rs690_asic;	394	rdev->asic = &rs690_asic;
392	break;	395	break;
393	case CHIP_RV515:	396	case CHIP_RV515:
394	rdev->asic = &rv515_asic;	397	rdev->asic = &rv515_asic;
395	break;	398	break;
396	case CHIP_R520:	399	case CHIP_R520:
397	case CHIP_RV530:	400	case CHIP_RV530:
398	case CHIP_RV560:	401	case CHIP_RV560:
399	case CHIP_RV570:	402	case CHIP_RV570:
400	case CHIP_R580:	403	case CHIP_R580:
401	rdev->asic = &r520_asic;	404	rdev->asic = &r520_asic;
402	break;	405	break;
403	case CHIP_R600:	406	case CHIP_R600:
404	case CHIP_RV610:	407	case CHIP_RV610:
405	case CHIP_RV630:	408	case CHIP_RV630:
406	case CHIP_RV620:	409	case CHIP_RV620:
407	case CHIP_RV635:	410	case CHIP_RV635:
408	case CHIP_RV670:	411	case CHIP_RV670:
409	case CHIP_RS780:	412	case CHIP_RS780:
410	case CHIP_RS880:	413	case CHIP_RS880:
411	rdev->asic = &r600_asic;	414	rdev->asic = &r600_asic;
412	break;	415	break;
413	case CHIP_RV770:	416	case CHIP_RV770:
414	case CHIP_RV730:	417	case CHIP_RV730:
415	case CHIP_RV710:	418	case CHIP_RV710:
416	case CHIP_RV740:	419	case CHIP_RV740:
417	rdev->asic = &rv770_asic;	420	rdev->asic = &rv770_asic;
418	break;	421	break;
419	default:	422	default:
420	/* FIXME: not supported yet */	423	/* FIXME: not supported yet */
421	return -EINVAL;	424	return -EINVAL;
422	}	425	}
423		426
424	if (rdev->flags & RADEON_IS_IGP) {	427	if (rdev->flags & RADEON_IS_IGP) {
425	rdev->asic->get_memory_clock = NULL;	428	rdev->asic->get_memory_clock = NULL;
426	rdev->asic->set_memory_clock = NULL;	429	rdev->asic->set_memory_clock = NULL;
427	}	430	}
428		431
429	return 0;	432	return 0;
430	}	433	}
431		434
432		435
433	/*	436	/*
434	* Wrapper around modesetting bits.	437	* Wrapper around modesetting bits.
435	*/	438	*/
436	int radeon_clocks_init(struct radeon_device *rdev)	439	int radeon_clocks_init(struct radeon_device *rdev)
437	{	440	{
438	int r;	441	int r;
439		442
440	r = radeon_static_clocks_init(rdev->ddev);	443	r = radeon_static_clocks_init(rdev->ddev);
441	if (r) {	444	if (r) {
442	return r;	445	return r;
443	}	446	}
444	DRM_INFO("Clocks initialized !\n");	447	DRM_INFO("Clocks initialized !\n");
445	return 0;	448	return 0;
446	}	449	}
447		450
448	void radeon_clocks_fini(struct radeon_device *rdev)	451	void radeon_clocks_fini(struct radeon_device *rdev)
449	{	452	{
450	}	453	}
451		454
452	/* ATOM accessor methods */	455	/* ATOM accessor methods */
453	static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)	456	static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
454	{	457	{
455	struct radeon_device *rdev = info->dev->dev_private;	458	struct radeon_device *rdev = info->dev->dev_private;
456	uint32_t r;	459	uint32_t r;
457		460
458	r = rdev->pll_rreg(rdev, reg);	461	r = rdev->pll_rreg(rdev, reg);
459	return r;	462	return r;
460	}	463	}
461		464
462	static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)	465	static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
463	{	466	{
464	struct radeon_device *rdev = info->dev->dev_private;	467	struct radeon_device *rdev = info->dev->dev_private;
465		468
466	rdev->pll_wreg(rdev, reg, val);	469	rdev->pll_wreg(rdev, reg, val);
467	}	470	}
468		471
469	static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)	472	static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
470	{	473	{
471	struct radeon_device *rdev = info->dev->dev_private;	474	struct radeon_device *rdev = info->dev->dev_private;
472	uint32_t r;	475	uint32_t r;
473		476
474	r = rdev->mc_rreg(rdev, reg);	477	r = rdev->mc_rreg(rdev, reg);
475	return r;	478	return r;
476	}	479	}
477		480
478	static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)	481	static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
479	{	482	{
480	struct radeon_device *rdev = info->dev->dev_private;	483	struct radeon_device *rdev = info->dev->dev_private;
481		484
482	rdev->mc_wreg(rdev, reg, val);	485	rdev->mc_wreg(rdev, reg, val);
483	}	486	}
484		487
485	static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)	488	static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
486	{	489	{
487	struct radeon_device *rdev = info->dev->dev_private;	490	struct radeon_device *rdev = info->dev->dev_private;
488		491
489	WREG32(reg*4, val);	492	WREG32(reg*4, val);
490	}	493	}
491		494
492	static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)	495	static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
493	{	496	{
494	struct radeon_device *rdev = info->dev->dev_private;	497	struct radeon_device *rdev = info->dev->dev_private;
495	uint32_t r;	498	uint32_t r;
496		499
497	r = RREG32(reg*4);	500	r = RREG32(reg*4);

Subversion Repositories Kolibri OS

(root)/drivers/video/drm/radeon/radeon_device.c @ 2175 – Rev 1414 → 1428