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1 | #include |
1 | #include |
2 | #include |
2 | #include |
3 | #include |
3 | #include |
4 | #include "radeon_reg.h" |
4 | #include "radeon_reg.h" |
5 | #include "radeon.h" |
5 | #include "radeon.h" |
6 | #include "bitmap.h" |
6 | #include "bitmap.h" |
7 | 7 | ||
8 | void __init dmi_scan_machine(void); |
8 | void __init dmi_scan_machine(void); |
9 | 9 | ||
10 | #define KMS_DEV_CLOSE 0 |
10 | #define KMS_DEV_CLOSE 0 |
11 | #define KMS_DEV_INIT 1 |
11 | #define KMS_DEV_INIT 1 |
12 | #define KMS_DEV_READY 2 |
12 | #define KMS_DEV_READY 2 |
13 | 13 | ||
14 | struct pci_device { |
14 | struct pci_device { |
15 | uint16_t domain; |
15 | uint16_t domain; |
16 | uint8_t bus; |
16 | uint8_t bus; |
17 | uint8_t dev; |
17 | uint8_t dev; |
18 | uint8_t func; |
18 | uint8_t func; |
19 | uint16_t vendor_id; |
19 | uint16_t vendor_id; |
20 | uint16_t device_id; |
20 | uint16_t device_id; |
21 | uint16_t subvendor_id; |
21 | uint16_t subvendor_id; |
22 | uint16_t subdevice_id; |
22 | uint16_t subdevice_id; |
23 | uint32_t device_class; |
23 | uint32_t device_class; |
24 | uint8_t revision; |
24 | uint8_t revision; |
25 | }; |
25 | }; |
26 | 26 | ||
27 | struct drm_device *main_device; |
27 | struct drm_device *main_device; |
28 | struct drm_file *drm_file_handlers[256]; |
28 | struct drm_file *drm_file_handlers[256]; |
29 | 29 | ||
30 | videomode_t usermode; |
30 | videomode_t usermode; |
31 | 31 | ||
32 | void cpu_detect1(); |
32 | void cpu_detect1(); |
33 | 33 | ||
34 | int _stdcall display_handler(ioctl_t *io); |
34 | int _stdcall display_handler(ioctl_t *io); |
35 | static char log[256]; |
35 | static char log[256]; |
36 | 36 | ||
37 | unsigned long volatile jiffies; |
37 | unsigned long volatile jiffies; |
38 | u64 jiffies_64; |
38 | u64 jiffies_64; |
39 | 39 | ||
40 | struct workqueue_struct *system_wq; |
40 | struct workqueue_struct *system_wq; |
41 | int driver_wq_state; |
41 | int driver_wq_state; |
42 | 42 | ||
43 | int x86_clflush_size; |
43 | int x86_clflush_size; |
44 | 44 | ||
45 | void ati_driver_thread() |
45 | void ati_driver_thread() |
46 | { |
46 | { |
47 | struct radeon_device *rdev = NULL; |
47 | struct radeon_device *rdev = NULL; |
48 | struct workqueue_struct *cwq = NULL; |
48 | struct workqueue_struct *cwq = NULL; |
49 | // static int dpms = 1; |
49 | // static int dpms = 1; |
50 | // static int dpms_lock = 0; |
50 | // static int dpms_lock = 0; |
51 | // oskey_t key; |
51 | // oskey_t key; |
52 | unsigned long irqflags; |
52 | unsigned long irqflags; |
53 | int tmp; |
53 | int tmp; |
54 | 54 | ||
55 | printf("%s\n",__FUNCTION__); |
55 | printf("%s\n",__FUNCTION__); |
56 | 56 | ||
57 | while(driver_wq_state == KMS_DEV_INIT) |
57 | while(driver_wq_state == KMS_DEV_INIT) |
58 | { |
58 | { |
59 | jiffies = GetTimerTicks(); |
59 | jiffies = GetTimerTicks(); |
60 | jiffies_64 = jiffies; |
60 | jiffies_64 = jiffies; |
61 | delay(1); |
61 | delay(1); |
62 | }; |
62 | }; |
63 | 63 | ||
64 | rdev = main_device->dev_private; |
64 | rdev = main_device->dev_private; |
65 | // cwq = rdev->wq; |
65 | // cwq = rdev->wq; |
66 | 66 | ||
67 | asm volatile("int $0x40":"=a"(tmp):"a"(66),"b"(1),"c"(1)); |
67 | asm volatile("int $0x40":"=a"(tmp):"a"(66),"b"(1),"c"(1)); |
68 | asm volatile("int $0x40":"=a"(tmp):"a"(66),"b"(4),"c"(0x46),"d"(0x330)); |
68 | asm volatile("int $0x40":"=a"(tmp):"a"(66),"b"(4),"c"(0x46),"d"(0x330)); |
69 | asm volatile("int $0x40":"=a"(tmp):"a"(66),"b"(4),"c"(0xC6),"d"(0x330)); |
69 | asm volatile("int $0x40":"=a"(tmp):"a"(66),"b"(4),"c"(0xC6),"d"(0x330)); |
70 | 70 | ||
71 | while(driver_wq_state != KMS_DEV_CLOSE) |
71 | while(driver_wq_state != KMS_DEV_CLOSE) |
72 | { |
72 | { |
73 | jiffies = GetTimerTicks(); |
73 | jiffies = GetTimerTicks(); |
74 | #if 0 |
74 | #if 0 |
75 | key = get_key(); |
75 | key = get_key(); |
76 | 76 | ||
77 | if( (key.val != 1) && (key.state == 0x02)) |
77 | if( (key.val != 1) && (key.state == 0x02)) |
78 | { |
78 | { |
79 | if(key.code == 0x46 && dpms_lock == 0) |
79 | if(key.code == 0x46 && dpms_lock == 0) |
80 | { |
80 | { |
81 | dpms_lock = 1; |
81 | dpms_lock = 1; |
82 | if(dpms == 1) |
82 | if(dpms == 1) |
83 | { |
83 | { |
84 | i915_dpms(main_device, DRM_MODE_DPMS_OFF); |
84 | i915_dpms(main_device, DRM_MODE_DPMS_OFF); |
85 | printf("dpms off\n"); |
85 | printf("dpms off\n"); |
86 | } |
86 | } |
87 | else |
87 | else |
88 | { |
88 | { |
89 | i915_dpms(main_device, DRM_MODE_DPMS_ON); |
89 | i915_dpms(main_device, DRM_MODE_DPMS_ON); |
90 | printf("dpms on\n"); |
90 | printf("dpms on\n"); |
91 | }; |
91 | }; |
92 | dpms ^= 1; |
92 | dpms ^= 1; |
93 | } |
93 | } |
94 | else if(key.code == 0xC6) |
94 | else if(key.code == 0xC6) |
95 | dpms_lock = 0; |
95 | dpms_lock = 0; |
96 | }; |
96 | }; |
97 | spin_lock_irqsave(&cwq->lock, irqflags); |
97 | spin_lock_irqsave(&cwq->lock, irqflags); |
98 | 98 | ||
99 | while (!list_empty(&cwq->worklist)) |
99 | while (!list_empty(&cwq->worklist)) |
100 | { |
100 | { |
101 | struct work_struct *work = list_entry(cwq->worklist.next, |
101 | struct work_struct *work = list_entry(cwq->worklist.next, |
102 | struct work_struct, entry); |
102 | struct work_struct, entry); |
103 | work_func_t f = work->func; |
103 | work_func_t f = work->func; |
104 | list_del_init(cwq->worklist.next); |
104 | list_del_init(cwq->worklist.next); |
105 | 105 | ||
106 | spin_unlock_irqrestore(&cwq->lock, irqflags); |
106 | spin_unlock_irqrestore(&cwq->lock, irqflags); |
107 | f(work); |
107 | f(work); |
108 | spin_lock_irqsave(&cwq->lock, irqflags); |
108 | spin_lock_irqsave(&cwq->lock, irqflags); |
109 | } |
109 | } |
110 | 110 | ||
111 | spin_unlock_irqrestore(&cwq->lock, irqflags); |
111 | spin_unlock_irqrestore(&cwq->lock, irqflags); |
112 | #endif |
112 | #endif |
113 | 113 | ||
114 | delay(1); |
114 | delay(1); |
115 | }; |
115 | }; |
116 | 116 | ||
117 | asm volatile ("int $0x40"::"a"(-1)); |
117 | asm volatile ("int $0x40"::"a"(-1)); |
118 | } |
118 | } |
119 | 119 | ||
120 | u32 __attribute__((externally_visible)) drvEntry(int action, char *cmdline) |
120 | u32 __attribute__((externally_visible)) drvEntry(int action, char *cmdline) |
121 | { |
121 | { |
122 | struct radeon_device *rdev = NULL; |
122 | struct radeon_device *rdev = NULL; |
123 | 123 | ||
124 | const struct pci_device_id *ent; |
124 | const struct pci_device_id *ent; |
125 | 125 | ||
126 | int err = 0; |
126 | int err = 0; |
127 | 127 | ||
128 | if(action != 1) |
128 | if(action != 1) |
129 | { |
129 | { |
130 | driver_wq_state = KMS_DEV_CLOSE; |
130 | driver_wq_state = KMS_DEV_CLOSE; |
131 | return 0; |
131 | return 0; |
132 | }; |
132 | }; |
133 | 133 | ||
134 | if( GetService("DISPLAY") != 0 ) |
134 | if( GetService("DISPLAY") != 0 ) |
135 | return 0; |
135 | return 0; |
136 | 136 | ||
137 | printf("Radeon v3.19-rc1 cmdline %s\n", cmdline); |
137 | printf("Radeon v3.19-rc2 cmdline %s\n", cmdline); |
138 | 138 | ||
139 | if( cmdline && *cmdline ) |
139 | if( cmdline && *cmdline ) |
140 | parse_cmdline(cmdline, &usermode, log, &radeon_modeset); |
140 | parse_cmdline(cmdline, &usermode, log, &radeon_modeset); |
141 | 141 | ||
142 | if( *log && !dbg_open(log)) |
142 | if( *log && !dbg_open(log)) |
143 | { |
143 | { |
144 | printf("Can't open %s\nExit\n", log); |
144 | printf("Can't open %s\nExit\n", log); |
145 | return 0; |
145 | return 0; |
146 | } |
146 | } |
147 | 147 | ||
148 | cpu_detect1(); |
148 | cpu_detect1(); |
149 | 149 | ||
150 | err = enum_pci_devices(); |
150 | err = enum_pci_devices(); |
151 | if( unlikely(err != 0) ) |
151 | if( unlikely(err != 0) ) |
152 | { |
152 | { |
153 | dbgprintf("Device enumeration failed\n"); |
153 | dbgprintf("Device enumeration failed\n"); |
154 | return 0; |
154 | return 0; |
155 | } |
155 | } |
156 | 156 | ||
157 | driver_wq_state = KMS_DEV_INIT; |
157 | driver_wq_state = KMS_DEV_INIT; |
158 | CreateKernelThread(ati_driver_thread); |
158 | CreateKernelThread(ati_driver_thread); |
159 | 159 | ||
160 | err = ati_init(); |
160 | err = ati_init(); |
161 | if(unlikely(err!= 0)) |
161 | if(unlikely(err!= 0)) |
162 | { |
162 | { |
163 | driver_wq_state = KMS_DEV_CLOSE; |
163 | driver_wq_state = KMS_DEV_CLOSE; |
164 | dbgprintf("Epic Fail :(\n"); |
164 | dbgprintf("Epic Fail :(\n"); |
165 | return 0; |
165 | return 0; |
166 | }; |
166 | }; |
167 | 167 | ||
168 | driver_wq_state = KMS_DEV_READY; |
168 | driver_wq_state = KMS_DEV_READY; |
169 | 169 | ||
170 | rdev = main_device->dev_private; |
170 | rdev = main_device->dev_private; |
171 | printf("current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev)); |
171 | printf("current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev)); |
172 | printf("current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev)); |
172 | printf("current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev)); |
173 | 173 | ||
174 | err = RegService("DISPLAY", display_handler); |
174 | err = RegService("DISPLAY", display_handler); |
175 | 175 | ||
176 | if( err != 0) |
176 | if( err != 0) |
177 | dbgprintf("DISPLAY service installed\n"); |
177 | dbgprintf("DISPLAY service installed\n"); |
178 | 178 | ||
179 | 179 | ||
180 | return err; |
180 | return err; |
181 | }; |
181 | }; |
182 | 182 | ||
183 | 183 | ||
184 | 184 | ||
185 | #define CURRENT_API 0x0200 /* 2.00 */ |
185 | #define CURRENT_API 0x0200 /* 2.00 */ |
186 | #define COMPATIBLE_API 0x0100 /* 1.00 */ |
186 | #define COMPATIBLE_API 0x0100 /* 1.00 */ |
187 | 187 | ||
188 | #define API_VERSION (COMPATIBLE_API << 16) | CURRENT_API |
188 | #define API_VERSION (COMPATIBLE_API << 16) | CURRENT_API |
189 | 189 | ||
190 | #define SRV_GETVERSION 0 |
190 | #define SRV_GETVERSION 0 |
191 | #define SRV_ENUM_MODES 1 |
191 | #define SRV_ENUM_MODES 1 |
192 | #define SRV_SET_MODE 2 |
192 | #define SRV_SET_MODE 2 |
193 | #define SRV_GET_CAPS 3 |
193 | #define SRV_GET_CAPS 3 |
194 | 194 | ||
195 | #define SRV_CREATE_SURFACE 10 |
195 | #define SRV_CREATE_SURFACE 10 |
196 | #define SRV_DESTROY_SURFACE 11 |
196 | #define SRV_DESTROY_SURFACE 11 |
197 | #define SRV_LOCK_SURFACE 12 |
197 | #define SRV_LOCK_SURFACE 12 |
198 | #define SRV_UNLOCK_SURFACE 13 |
198 | #define SRV_UNLOCK_SURFACE 13 |
199 | #define SRV_RESIZE_SURFACE 14 |
199 | #define SRV_RESIZE_SURFACE 14 |
200 | #define SRV_BLIT_BITMAP 15 |
200 | #define SRV_BLIT_BITMAP 15 |
201 | #define SRV_BLIT_TEXTURE 16 |
201 | #define SRV_BLIT_TEXTURE 16 |
202 | #define SRV_BLIT_VIDEO 17 |
202 | #define SRV_BLIT_VIDEO 17 |
203 | 203 | ||
204 | 204 | ||
205 | 205 | ||
206 | int r600_video_blit(uint64_t src_offset, int x, int y, |
206 | int r600_video_blit(uint64_t src_offset, int x, int y, |
207 | int w, int h, int pitch); |
207 | int w, int h, int pitch); |
208 | 208 | ||
209 | #define check_input(size) \ |
209 | #define check_input(size) \ |
210 | if( unlikely((inp==NULL)||(io->inp_size != (size))) ) \ |
210 | if( unlikely((inp==NULL)||(io->inp_size != (size))) ) \ |
211 | break; |
211 | break; |
212 | 212 | ||
213 | #define check_output(size) \ |
213 | #define check_output(size) \ |
214 | if( unlikely((outp==NULL)||(io->out_size != (size))) ) \ |
214 | if( unlikely((outp==NULL)||(io->out_size != (size))) ) \ |
215 | break; |
215 | break; |
216 | 216 | ||
217 | int _stdcall display_handler(ioctl_t *io) |
217 | int _stdcall display_handler(ioctl_t *io) |
218 | { |
218 | { |
219 | int retval = -1; |
219 | int retval = -1; |
220 | u32 *inp; |
220 | u32 *inp; |
221 | u32 *outp; |
221 | u32 *outp; |
222 | 222 | ||
223 | inp = io->input; |
223 | inp = io->input; |
224 | outp = io->output; |
224 | outp = io->output; |
225 | 225 | ||
226 | switch(io->io_code) |
226 | switch(io->io_code) |
227 | { |
227 | { |
228 | case SRV_GETVERSION: |
228 | case SRV_GETVERSION: |
229 | check_output(4); |
229 | check_output(4); |
230 | *outp = API_VERSION; |
230 | *outp = API_VERSION; |
231 | retval = 0; |
231 | retval = 0; |
232 | break; |
232 | break; |
233 | 233 | ||
234 | case SRV_ENUM_MODES: |
234 | case SRV_ENUM_MODES: |
235 | // dbgprintf("SRV_ENUM_MODES inp %x inp_size %x out_size %x\n", |
235 | // dbgprintf("SRV_ENUM_MODES inp %x inp_size %x out_size %x\n", |
236 | // inp, io->inp_size, io->out_size ); |
236 | // inp, io->inp_size, io->out_size ); |
237 | check_output(4); |
237 | check_output(4); |
238 | if( radeon_modeset) |
238 | if( radeon_modeset) |
239 | retval = get_videomodes((videomode_t*)inp, outp); |
239 | retval = get_videomodes((videomode_t*)inp, outp); |
240 | break; |
240 | break; |
241 | 241 | ||
242 | case SRV_SET_MODE: |
242 | case SRV_SET_MODE: |
243 | // dbgprintf("SRV_SET_MODE inp %x inp_size %x\n", |
243 | // dbgprintf("SRV_SET_MODE inp %x inp_size %x\n", |
244 | // inp, io->inp_size); |
244 | // inp, io->inp_size); |
245 | check_input(sizeof(videomode_t)); |
245 | check_input(sizeof(videomode_t)); |
246 | if( radeon_modeset ) |
246 | if( radeon_modeset ) |
247 | retval = set_user_mode((videomode_t*)inp); |
247 | retval = set_user_mode((videomode_t*)inp); |
248 | break; |
248 | break; |
249 | /* |
249 | /* |
250 | case SRV_GET_CAPS: |
250 | case SRV_GET_CAPS: |
251 | retval = get_driver_caps((hwcaps_t*)inp); |
251 | retval = get_driver_caps((hwcaps_t*)inp); |
252 | break; |
252 | break; |
253 | 253 | ||
254 | case SRV_CREATE_SURFACE: |
254 | case SRV_CREATE_SURFACE: |
255 | // check_input(8); |
255 | // check_input(8); |
256 | retval = create_surface(main_drm_device, (struct io_call_10*)inp); |
256 | retval = create_surface(main_drm_device, (struct io_call_10*)inp); |
257 | break; |
257 | break; |
258 | 258 | ||
259 | case SRV_LOCK_SURFACE: |
259 | case SRV_LOCK_SURFACE: |
260 | retval = lock_surface((struct io_call_12*)inp); |
260 | retval = lock_surface((struct io_call_12*)inp); |
261 | break; |
261 | break; |
262 | 262 | ||
263 | case SRV_BLIT_BITMAP: |
263 | case SRV_BLIT_BITMAP: |
264 | srv_blit_bitmap( inp[0], inp[1], inp[2], |
264 | srv_blit_bitmap( inp[0], inp[1], inp[2], |
265 | inp[3], inp[4], inp[5], inp[6]); |
265 | inp[3], inp[4], inp[5], inp[6]); |
266 | */ |
266 | */ |
267 | }; |
267 | }; |
268 | 268 | ||
269 | return retval; |
269 | return retval; |
270 | } |
270 | } |
271 | 271 | ||
272 | 272 | ||
273 | #define PCI_CLASS_REVISION 0x08 |
273 | #define PCI_CLASS_REVISION 0x08 |
274 | #define PCI_CLASS_DISPLAY_VGA 0x0300 |
274 | #define PCI_CLASS_DISPLAY_VGA 0x0300 |
275 | 275 | ||
276 | int pci_scan_filter(u32 id, u32 busnr, u32 devfn) |
276 | int pci_scan_filter(u32 id, u32 busnr, u32 devfn) |
277 | { |
277 | { |
278 | u16 vendor, device; |
278 | u16 vendor, device; |
279 | u32 class; |
279 | u32 class; |
280 | int ret = 0; |
280 | int ret = 0; |
281 | 281 | ||
282 | vendor = id & 0xffff; |
282 | vendor = id & 0xffff; |
283 | device = (id >> 16) & 0xffff; |
283 | device = (id >> 16) & 0xffff; |
284 | 284 | ||
285 | if(vendor == 0x1002) |
285 | if(vendor == 0x1002) |
286 | { |
286 | { |
287 | class = PciRead32(busnr, devfn, PCI_CLASS_REVISION); |
287 | class = PciRead32(busnr, devfn, PCI_CLASS_REVISION); |
288 | class >>= 16; |
288 | class >>= 16; |
289 | 289 | ||
290 | if( class == PCI_CLASS_DISPLAY_VGA) |
290 | if( class == PCI_CLASS_DISPLAY_VGA) |
291 | ret = 1; |
291 | ret = 1; |
292 | } |
292 | } |
293 | return ret; |
293 | return ret; |
294 | } |
294 | } |
295 | 295 | ||
296 | 296 | ||
297 | int seq_printf(struct seq_file *m, const char *f, ...) |
297 | int seq_printf(struct seq_file *m, const char *f, ...) |
298 | { |
298 | { |
299 | // int ret; |
299 | // int ret; |
300 | // va_list args; |
300 | // va_list args; |
301 | 301 | ||
302 | // va_start(args, f); |
302 | // va_start(args, f); |
303 | // ret = seq_vprintf(m, f, args); |
303 | // ret = seq_vprintf(m, f, args); |
304 | // va_end(args); |
304 | // va_end(args); |
305 | 305 | ||
306 | // return ret; |
306 | // return ret; |
307 | return 0; |
307 | return 0; |
308 | } |
308 | } |
309 | 309 | ||
310 | s64 div64_s64(s64 dividend, s64 divisor) |
310 | s64 div64_s64(s64 dividend, s64 divisor) |
311 | { |
311 | { |
312 | s64 quot, t; |
312 | s64 quot, t; |
313 | 313 | ||
314 | quot = div64_u64(abs64(dividend), abs64(divisor)); |
314 | quot = div64_u64(abs64(dividend), abs64(divisor)); |
315 | t = (dividend ^ divisor) >> 63; |
315 | t = (dividend ^ divisor) >> 63; |
316 | 316 | ||
317 | return (quot ^ t) - t; |
317 | return (quot ^ t) - t; |
318 | }><> |
318 | }><> |