4,7 → 4,7 |
#define LINE_2P 3 |
#define BLIT 4 |
#define COMPIZ 5 |
#define PIXMAP 6 |
#define PX_CREATE 6 |
#define PIXBLIT 7 |
#define PIXLOCK 8 |
#define PIXUNLOCK 9 |
16,18 → 16,90 |
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typedef struct |
{ |
pixmap_t *dstpix; |
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int x; |
int y; |
u32_t w; |
u32_t h; |
}pt_t; |
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/*********** Clipping **********/ |
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typedef struct |
{ |
int xmin; |
int ymin; |
int xmax; |
int ymax; |
}clip_t, *PTRclip; |
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#define CLIP_TOP 1 |
#define CLIP_BOTTOM 2 |
#define CLIP_RIGHT 4 |
#define CLIP_LEFT 8 |
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int LineClip ( clip_t *clip, int *x1, int *y1, int *x2, int *y2 ); |
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int BlockClip( clip_t *clip, int *x1, int *y1, int *x2, int* y2 ); |
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typedef struct |
{ |
unsigned width; |
unsigned height; |
u32_t format; |
u32_t flags; |
unsigned pitch; |
void *mapped; |
u32_t handle; |
}pixmap_t; |
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typedef struct |
{ |
unsigned width; |
unsigned height; |
u32_t format; |
u32_t flags; |
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unsigned pitch; |
void *mapped; |
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unsigned pitch_offset; |
void *local; |
}local_pixmap_t; |
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//int CreatePixmap(userpixmap_t *io); |
//int DestroyPixmap(userpixmap_t *io); |
//int LockPixmap(userpixmap_t *io); |
//int UnlockPixmap(userpixmap_t *io); |
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#define PX_LOCK 1 |
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typedef struct |
{ |
local_pixmap_t *dstpix; |
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struct |
{ |
int x0; |
int y0; |
}; |
union |
{ |
struct |
{ |
int x1; |
int y1; |
}; |
struct |
{ |
int w; |
int h; |
}; |
}; |
color_t color; |
}draw_t; |
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typedef struct |
{ |
pixmap_t *dstpix; |
local_pixmap_t *dstpix; |
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int x; |
int y; |
53,31 → 125,11 |
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typedef struct |
{ |
int x0; |
int y0; |
int x1; |
int y1; |
u32 color; |
}line2p_t; |
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typedef struct |
{ |
pixmap_t *pixmap; |
void *usermap; |
u32_t format; |
u32_t pitch; |
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u32_t width; |
u32_t height; |
}userpixmap_t; |
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typedef struct |
{ |
pixmap_t *dstpix; |
local_pixmap_t *dstpix; |
int dst_x; |
int dst_y; |
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pixmap_t *srcpix; |
local_pixmap_t *srcpix; |
int src_x; |
int src_y; |
int w; |
85,94 → 137,18 |
}pixblit_t; |
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int LineClip( int *x1, int *y1, int *x2, int *y2 ); |
int BlockClip( int *x1, int *y1, int *x2, int* y2); |
int Line2P(draw_t *draw); |
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int DrawRect(draw_t * draw); |
int FillRect(fill_t * fill); |
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int Line2P(line2p_t *draw); |
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int Blit(blit_t *blit); |
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int RadeonComposite( blit_t *blit); |
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int CreatePixmap(userpixmap_t *io); |
int DestroyPixmap(userpixmap_t *io); |
int LockPixmap(userpixmap_t *io); |
int UnlockPixmap(userpixmap_t *io); |
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int PixBlit(pixblit_t* blit); |
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# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) |
# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) |
# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4) |
# define RADEON_GMC_BRUSH_NONE (15 << 4) |
# define RADEON_GMC_DST_16BPP (4 << 8) |
# define RADEON_GMC_DST_24BPP (5 << 8) |
# define RADEON_GMC_DST_32BPP (6 << 8) |
# define RADEON_GMC_DST_DATATYPE_SHIFT 8 |
# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12) |
# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24) |
# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24) |
# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28) |
# define RADEON_GMC_WR_MSK_DIS (1 << 30) |
# define RADEON_ROP3_S 0x00cc0000 |
# define RADEON_ROP3_P 0x00f00000 |
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#define RADEON_CP_PACKET0 0x00000000 |
#define RADEON_CP_PACKET1 0x40000000 |
#define RADEON_CP_PACKET2 0x80000000 |
#define RADEON_CP_PACKET3 0xC0000000 |
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# define RADEON_CNTL_PAINT 0x00009100 |
# define RADEON_CNTL_BITBLT 0x00009200 |
# define RADEON_CNTL_TRANBLT 0x00009C00 |
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# define RADEON_CNTL_PAINT_POLYLINE 0x00009500 |
# define RADEON_CNTL_PAINT_MULTI 0x00009A00 |
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#define CP_PACKET0(reg, n) \ |
(RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2)) |
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#define CP_PACKET1(reg0, reg1) \ |
(RADEON_CP_PACKET1 | (((reg1) >> 2) << 11) | ((reg0) >> 2)) |
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#define CP_PACKET2() \ |
(RADEON_CP_PACKET2) |
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#define CP_PACKET3( pkt, n ) \ |
(RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) |
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#define BEGIN_RING( n ) do { \ |
ring = rhd.ring_base; \ |
write = rhd.ring_wp; \ |
} while (0) |
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#define ADVANCE_RING() |
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#define OUT_RING( x ) do { \ |
ring[write++] = (x); \ |
} while (0) |
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#define OUT_RING_REG(reg, val) \ |
do { \ |
OUT_RING(CP_PACKET0(reg, 0)); \ |
OUT_RING(val); \ |
} while (0) |
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#define DRM_MEMORYBARRIER() __asm volatile("lock; addl $0,0(%%esp)" : : : "memory"); |
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#define COMMIT_RING() do { \ |
rhd.ring_wp = write & 0x1FFF; \ |
/* Flush writes to ring */ \ |
DRM_MEMORYBARRIER(); \ |
/*GET_RING_HEAD( dev_priv ); */ \ |
OUTREG( RADEON_CP_RB_WPTR, rhd.ring_wp); \ |
/* read from PCI bus to ensure correct posting */ \ |
INREG( RADEON_CP_RB_RPTR ); \ |
} while (0) |
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