| 84,46 → 84,32 |
|---|
| |
| macro virt_to_dma reg |
| { |
| if defined E3C59X_LINUX |
| sub reg, [virt_addr] |
| add reg, [dma_addr] |
| end if |
| sub reg, OS_BASE |
| } |
| |
| macro dma_to_virt reg |
| { |
| if defined E3C59X_LINUX |
| sub reg, [dma_addr] |
| add reg, [virt_addr] |
| end if |
| add reg, OS_BASE |
| } |
| |
| macro zero_to_virt reg |
| { |
| if defined E3C59X_LINUX |
| add reg, [virt_addr] |
| end if |
| |
| } |
| |
| macro virt_to_zero reg |
| { |
| if defined E3C59X_LINUX |
| sub reg, [virt_addr] |
| end if |
| |
| } |
| |
| macro zero_to_dma reg |
| { |
| if defined E3C59X_LINUX |
| add reg, [dma_addr] |
| end if |
| sub reg, OS_BASE |
| } |
| |
| macro dma_to_zero reg |
| { |
| if defined E3C59X_LINUX |
| sub reg, [dma_addr] |
| end if |
| add reg, OS_BASE |
| } |
| |
| macro strtbl name, [string] |
| 368,6 → 354,7 |
|---|
| iglobal |
| e3c59x_ver_id: db 17 |
| endg |
| |
| uglobal |
| e3c59x_full_bus_master: db 0 |
| e3c59x_has_hwcksm: db 0 |
| 1567,14 → 1554,15 |
|---|
| lea edx, [ebp+E3C59X_REG_COMMAND] |
| mov ax, (01011b shl 11) |
| out dx, ax |
| ; wait for TxReset to complete |
| mov ecx, 2000 |
| ; Wait for TxReset to complete |
| mov ecx, 200000 |
| .tx_reset_loop: |
| in ax, dx |
| test ah, 10000b ; check CmdInProgress |
| jz .tx_enable |
| jz .tx_set_prev |
| dec ecx |
| jns .tx_reset_loop |
| .tx_set_prev: |
| test byte [e3c59x_full_bus_master], 0xff |
| jz .tx_enable |
| ; init last_dpd |
| 2148,7 → 2136,7 |
|---|
| mov ebx, ecx |
| test byte [e3c59x_has_hwcksm], 0xff |
| jz @f |
| or ebx, (1 shl 26) ; set AddTcpChecksum |
| ;;; or ebx, (1 shl 26) ; set AddTcpChecksum |
| @@: |
| or ebx, 0x8000 ; transmission complete notification |
| or ecx, 0x80000000 ; last fragment |