612,22 → 612,140 |
.hpd_sense = &r600_hpd_sense, |
.hpd_set_polarity = &r600_hpd_set_polarity, |
}; |
#if 0 |
|
static struct radeon_asic evergreen_asic = { |
.init = &evergreen_init, |
// .fini = &evergreen_fini, |
// .suspend = &evergreen_suspend, |
// .resume = &evergreen_resume, |
.cp_commit = NULL, |
.cp_commit = &r600_cp_commit, |
.asic_reset = &evergreen_asic_reset, |
.vga_set_state = &r600_vga_set_state, |
.gart_tlb_flush = &r600_pcie_gart_tlb_flush, |
.gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, |
.gart_set_page = &rs600_gart_set_page, |
.ring_test = &r600_ring_test, |
// .ring_ib_execute = &r600_ring_ib_execute, |
// .irq_set = &r600_irq_set, |
// .irq_process = &r600_irq_process, |
.fence_ring_emit = &r600_fence_ring_emit, |
// .cs_parse = &r600_cs_parse, |
// .copy_blit = &r600_copy_blit, |
// .copy_dma = &r600_copy_blit, |
// .copy = &r600_copy_blit, |
.get_engine_clock = &radeon_atom_get_engine_clock, |
.set_engine_clock = &radeon_atom_set_engine_clock, |
.get_memory_clock = &radeon_atom_get_memory_clock, |
.set_memory_clock = &radeon_atom_set_memory_clock, |
.get_pcie_lanes = &r600_get_pcie_lanes, |
.set_pcie_lanes = &r600_set_pcie_lanes, |
.set_clock_gating = NULL, |
.set_surface_reg = r600_set_surface_reg, |
.clear_surface_reg = r600_clear_surface_reg, |
.bandwidth_update = &evergreen_bandwidth_update, |
|
}; |
#if 0 |
static struct radeon_asic sumo_asic = { |
.init = &evergreen_init, |
.fini = &evergreen_fini, |
.suspend = &evergreen_suspend, |
.resume = &evergreen_resume, |
.cp_commit = &r600_cp_commit, |
.gpu_is_lockup = &evergreen_gpu_is_lockup, |
.asic_reset = &evergreen_asic_reset, |
.vga_set_state = &r600_vga_set_state, |
.gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, |
.gart_set_page = &rs600_gart_set_page, |
.ring_test = &r600_ring_test, |
.ring_ib_execute = &evergreen_ring_ib_execute, |
.irq_set = &evergreen_irq_set, |
.irq_process = &evergreen_irq_process, |
.get_vblank_counter = &evergreen_get_vblank_counter, |
.fence_ring_emit = &r600_fence_ring_emit, |
.cs_parse = &evergreen_cs_parse, |
.copy_blit = &evergreen_copy_blit, |
.copy_dma = &evergreen_copy_blit, |
.copy = &evergreen_copy_blit, |
.get_engine_clock = &radeon_atom_get_engine_clock, |
.set_engine_clock = &radeon_atom_set_engine_clock, |
.get_memory_clock = NULL, |
.set_memory_clock = NULL, |
.get_pcie_lanes = NULL, |
.set_pcie_lanes = NULL, |
.set_clock_gating = NULL, |
.set_surface_reg = r600_set_surface_reg, |
.clear_surface_reg = r600_clear_surface_reg, |
.bandwidth_update = &evergreen_bandwidth_update, |
.gui_idle = &r600_gui_idle, |
.pm_misc = &evergreen_pm_misc, |
.pm_prepare = &evergreen_pm_prepare, |
.pm_finish = &evergreen_pm_finish, |
.pm_init_profile = &rs780_pm_init_profile, |
.pm_get_dynpm_state = &r600_pm_get_dynpm_state, |
.pre_page_flip = &evergreen_pre_page_flip, |
.page_flip = &evergreen_page_flip, |
.post_page_flip = &evergreen_post_page_flip, |
}; |
|
static struct radeon_asic btc_asic = { |
.init = &evergreen_init, |
.fini = &evergreen_fini, |
.suspend = &evergreen_suspend, |
.resume = &evergreen_resume, |
.cp_commit = &r600_cp_commit, |
.gpu_is_lockup = &evergreen_gpu_is_lockup, |
.asic_reset = &evergreen_asic_reset, |
.vga_set_state = &r600_vga_set_state, |
.gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, |
.gart_set_page = &rs600_gart_set_page, |
.ring_test = NULL, |
// .ring_ib_execute = &r600_ring_ib_execute, |
// .irq_set = &r600_irq_set, |
// .irq_process = &r600_irq_process, |
.get_vblank_counter = &evergreen_get_vblank_counter, |
.fence_ring_emit = &r600_fence_ring_emit, |
.cs_parse = &evergreen_cs_parse, |
.copy_blit = &evergreen_copy_blit, |
.copy_dma = &evergreen_copy_blit, |
.copy = &evergreen_copy_blit, |
.get_engine_clock = &radeon_atom_get_engine_clock, |
.set_engine_clock = &radeon_atom_set_engine_clock, |
.get_memory_clock = &radeon_atom_get_memory_clock, |
.set_memory_clock = &radeon_atom_set_memory_clock, |
.get_pcie_lanes = NULL, |
.set_pcie_lanes = NULL, |
.set_clock_gating = NULL, |
.set_surface_reg = r600_set_surface_reg, |
.clear_surface_reg = r600_clear_surface_reg, |
.bandwidth_update = &evergreen_bandwidth_update, |
.gui_idle = &r600_gui_idle, |
.pm_misc = &evergreen_pm_misc, |
.pm_prepare = &evergreen_pm_prepare, |
.pm_finish = &evergreen_pm_finish, |
.pm_init_profile = &r600_pm_init_profile, |
.pm_get_dynpm_state = &r600_pm_get_dynpm_state, |
.pre_page_flip = &evergreen_pre_page_flip, |
.page_flip = &evergreen_page_flip, |
.post_page_flip = &evergreen_post_page_flip, |
}; |
|
static struct radeon_asic cayman_asic = { |
.init = &cayman_init, |
.fini = &cayman_fini, |
.suspend = &cayman_suspend, |
.resume = &cayman_resume, |
.cp_commit = &r600_cp_commit, |
.gpu_is_lockup = &cayman_gpu_is_lockup, |
.asic_reset = &cayman_asic_reset, |
.vga_set_state = &r600_vga_set_state, |
.gart_tlb_flush = &cayman_pcie_gart_tlb_flush, |
.gart_set_page = &rs600_gart_set_page, |
.ring_test = &r600_ring_test, |
.ring_ib_execute = &evergreen_ring_ib_execute, |
.irq_set = &evergreen_irq_set, |
.irq_process = &evergreen_irq_process, |
.get_vblank_counter = &evergreen_get_vblank_counter, |
.fence_ring_emit = &r600_fence_ring_emit, |
// .cs_parse = &r600_cs_parse, |
// .copy_blit = &r600_copy_blit, |
// .copy_dma = &r600_copy_blit, |
641,10 → 759,15 |
.set_surface_reg = r600_set_surface_reg, |
.clear_surface_reg = r600_clear_surface_reg, |
.bandwidth_update = &evergreen_bandwidth_update, |
.hpd_init = &evergreen_hpd_init, |
.hpd_fini = &evergreen_hpd_fini, |
.hpd_sense = &evergreen_hpd_sense, |
.hpd_set_polarity = &evergreen_hpd_set_polarity, |
.gui_idle = &r600_gui_idle, |
.pm_misc = &evergreen_pm_misc, |
.pm_prepare = &evergreen_pm_prepare, |
.pm_finish = &evergreen_pm_finish, |
.pm_init_profile = &r600_pm_init_profile, |
.pm_get_dynpm_state = &r600_pm_get_dynpm_state, |
.pre_page_flip = &evergreen_pre_page_flip, |
.page_flip = &evergreen_page_flip, |
.post_page_flip = &evergreen_post_page_flip, |
}; |
#endif |
|
651,6 → 774,13 |
int radeon_asic_init(struct radeon_device *rdev) |
{ |
radeon_register_accessor_init(rdev); |
|
/* set the number of crtcs */ |
if (rdev->flags & RADEON_SINGLE_CRTC) |
rdev->num_crtc = 1; |
else |
rdev->num_crtc = 2; |
|
switch (rdev->family) { |
case CHIP_R100: |
case CHIP_RV100: |
725,6 → 855,18 |
case CHIP_RV740: |
rdev->asic = &rv770_asic; |
break; |
case CHIP_CEDAR: |
case CHIP_REDWOOD: |
case CHIP_JUNIPER: |
case CHIP_CYPRESS: |
case CHIP_HEMLOCK: |
/* set num crtcs */ |
if (rdev->family == CHIP_CEDAR) |
rdev->num_crtc = 4; |
else |
rdev->num_crtc = 6; |
rdev->asic = &evergreen_asic; |
break; |
default: |
/* FIXME: not supported yet */ |
return -EINVAL; |
735,18 → 877,6 |
rdev->asic->set_memory_clock = NULL; |
} |
|
/* set the number of crtcs */ |
if (rdev->flags & RADEON_SINGLE_CRTC) |
rdev->num_crtc = 1; |
else { |
if (ASIC_IS_DCE41(rdev)) |
rdev->num_crtc = 2; |
else if (ASIC_IS_DCE4(rdev)) |
rdev->num_crtc = 6; |
else |
rdev->num_crtc = 2; |
} |
|
return 0; |
} |
|