| 330,8 → 330,10 |
|---|
| misc |= ATOM_COMPOSITESYNC; |
| if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
| misc |= ATOM_INTERLACE; |
| if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
| misc |= ATOM_DOUBLE_CLOCK_MODE; |
| if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
| misc |= ATOM_DOUBLE_CLOCK_MODE; |
| misc |= ATOM_H_REPLICATIONBY2 | ATOM_V_REPLICATIONBY2; |
| |
| args.susModeMiscInfo.usAccess = cpu_to_le16(misc); |
| args.ucCRTC = radeon_crtc->crtc_id; |
| 374,8 → 376,10 |
|---|
| misc |= ATOM_COMPOSITESYNC; |
| if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
| misc |= ATOM_INTERLACE; |
| if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
| misc |= ATOM_DOUBLE_CLOCK_MODE; |
| if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
| misc |= ATOM_DOUBLE_CLOCK_MODE; |
| misc |= ATOM_H_REPLICATIONBY2 | ATOM_V_REPLICATIONBY2; |
| |
| args.susModeMiscInfo.usAccess = cpu_to_le16(misc); |
| args.ucCRTC = radeon_crtc->crtc_id; |
| 606,6 → 610,13 |
|---|
| } |
| } |
| |
| if (radeon_encoder->is_mst_encoder) { |
| struct radeon_encoder_mst *mst_enc = radeon_encoder->enc_priv; |
| struct radeon_connector_atom_dig *dig_connector = mst_enc->connector->con_priv; |
| |
| dp_clock = dig_connector->dp_clock; |
| } |
| |
| /* use recommended ref_div for ss */ |
| if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
| if (radeon_crtc->ss_enabled) { |
| 952,7 → 963,9 |
|---|
| radeon_crtc->bpc = 8; |
| radeon_crtc->ss_enabled = false; |
| |
| if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || |
| if (radeon_encoder->is_mst_encoder) { |
| radeon_dp_mst_prepare_pll(crtc, mode); |
| } else if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || |
| (radeon_encoder_get_dp_bridge_encoder_id(radeon_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) { |
| struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
| struct drm_connector *connector = |
| 1405,6 → 1418,9 |
|---|
| (x << 16) | y); |
| viewport_w = crtc->mode.hdisplay; |
| viewport_h = (crtc->mode.vdisplay + 1) & ~1; |
| if ((rdev->family >= CHIP_BONAIRE) && |
| (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)) |
| viewport_h *= 2; |
| WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset, |
| (viewport_w << 16) | viewport_h); |
| |
| 1851,10 → 1867,9 |
|---|
| return pll; |
| } |
| /* otherwise, pick one of the plls */ |
| if ((rdev->family == CHIP_KAVERI) || |
| (rdev->family == CHIP_KABINI) || |
| if ((rdev->family == CHIP_KABINI) || |
| (rdev->family == CHIP_MULLINS)) { |
| /* KB/KV/ML has PPLL1 and PPLL2 */ |
| /* KB/ML has PPLL1 and PPLL2 */ |
| pll_in_use = radeon_get_pll_use_mask(crtc); |
| if (!(pll_in_use & (1 << ATOM_PPLL2))) |
| return ATOM_PPLL2; |
| 1863,7 → 1878,7 |
|---|
| DRM_ERROR("unable to allocate a PPLL\n"); |
| return ATOM_PPLL_INVALID; |
| } else { |
| /* CI has PPLL0, PPLL1, and PPLL2 */ |
| /* CI/KV has PPLL0, PPLL1, and PPLL2 */ |
| pll_in_use = radeon_get_pll_use_mask(crtc); |
| if (!(pll_in_use & (1 << ATOM_PPLL2))) |
| return ATOM_PPLL2; |
| 2067,6 → 2082,12 |
|---|
| radeon_crtc->connector = NULL; |
| return false; |
| } |
| if (radeon_crtc->encoder) { |
| struct radeon_encoder *radeon_encoder = |
| to_radeon_encoder(radeon_crtc->encoder); |
| |
| radeon_crtc->output_csc = radeon_encoder->output_csc; |
| } |
| if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) |
| return false; |
| if (!atombios_crtc_prepare_pll(crtc, adjusted_mode)) |
| 2155,6 → 2176,7 |
|---|
| case ATOM_PPLL0: |
| /* disable the ppll */ |
| if ((rdev->family == CHIP_ARUBA) || |
| (rdev->family == CHIP_KAVERI) || |
| (rdev->family == CHIP_BONAIRE) || |
| (rdev->family == CHIP_HAWAII)) |
| atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, |