| 1696,8 → 1696,7 |
|---|
| return ATOM_PPLL2; |
| DRM_ERROR("unable to allocate a PPLL\n"); |
| return ATOM_PPLL_INVALID; |
| } else { |
| if (ASIC_IS_AVIVO(rdev)) { |
| } else if (ASIC_IS_AVIVO(rdev)) { |
| /* in DP mode, the DP ref clock can come from either PPLL |
| * depending on the asic: |
| * DCE3: PPLL1 or PPLL2 |
| 1715,10 → 1714,20 |
|---|
| } |
| /* all other cases */ |
| pll_in_use = radeon_get_pll_use_mask(crtc); |
| /* the order shouldn't matter here, but we probably |
| * need this until we have atomic modeset |
| */ |
| if (rdev->flags & RADEON_IS_IGP) { |
| if (!(pll_in_use & (1 << ATOM_PPLL1))) |
| return ATOM_PPLL1; |
| if (!(pll_in_use & (1 << ATOM_PPLL2))) |
| return ATOM_PPLL2; |
| } else { |
| if (!(pll_in_use & (1 << ATOM_PPLL2))) |
| return ATOM_PPLL2; |
| if (!(pll_in_use & (1 << ATOM_PPLL1))) |
| return ATOM_PPLL1; |
| } |
| DRM_ERROR("unable to allocate a PPLL\n"); |
| return ATOM_PPLL_INVALID; |
| } else { |
| 1726,7 → 1735,6 |
|---|
| return radeon_crtc->crtc_id; |
| } |
| } |
| } |
| |
| void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev) |
| { |