| 959,139 → 959,4 |
|---|
| } |
| |
| |
| /* We give fast paths for the really cool registers */ |
| #define NEEDS_FORCE_WAKE(dev_priv, reg) \ |
| ((HAS_FORCE_WAKE((dev_priv)->dev)) && \ |
| ((reg) < 0x40000) && \ |
| ((reg) != FORCEWAKE)) |
| |
| static bool IS_DISPLAYREG(u32 reg) |
| { |
| /* |
| * This should make it easier to transition modules over to the |
| * new register block scheme, since we can do it incrementally. |
| */ |
| if (reg >= VLV_DISPLAY_BASE) |
| return false; |
| |
| if (reg >= RENDER_RING_BASE && |
| reg < RENDER_RING_BASE + 0xff) |
| return false; |
| if (reg >= GEN6_BSD_RING_BASE && |
| reg < GEN6_BSD_RING_BASE + 0xff) |
| return false; |
| if (reg >= BLT_RING_BASE && |
| reg < BLT_RING_BASE + 0xff) |
| return false; |
| |
| if (reg == PGTBL_ER) |
| return false; |
| |
| if (reg >= IPEIR_I965 && |
| reg < HWSTAM) |
| return false; |
| |
| if (reg == MI_MODE) |
| return false; |
| |
| if (reg == GFX_MODE_GEN7) |
| return false; |
| |
| if (reg == RENDER_HWS_PGA_GEN7 || |
| reg == BSD_HWS_PGA_GEN7 || |
| reg == BLT_HWS_PGA_GEN7) |
| return false; |
| |
| if (reg == GEN6_BSD_SLEEP_PSMI_CONTROL || |
| reg == GEN6_BSD_RNCID) |
| return false; |
| |
| if (reg == GEN6_BLITTER_ECOSKPD) |
| return false; |
| |
| if (reg >= 0x4000c && |
| reg <= 0x4002c) |
| return false; |
| |
| if (reg >= 0x4f000 && |
| reg <= 0x4f08f) |
| return false; |
| |
| if (reg >= 0x4f100 && |
| reg <= 0x4f11f) |
| return false; |
| |
| if (reg >= VLV_MASTER_IER && |
| reg <= GEN6_PMIER) |
| return false; |
| |
| if (reg >= FENCE_REG_SANDYBRIDGE_0 && |
| reg < (FENCE_REG_SANDYBRIDGE_0 + (16*8))) |
| return false; |
| |
| if (reg >= VLV_IIR_RW && |
| reg <= VLV_ISR) |
| return false; |
| |
| if (reg == FORCEWAKE_VLV || |
| reg == FORCEWAKE_ACK_VLV) |
| return false; |
| |
| if (reg == GEN6_GDRST) |
| return false; |
| |
| switch (reg) { |
| case _3D_CHICKEN3: |
| case IVB_CHICKEN3: |
| case GEN7_COMMON_SLICE_CHICKEN1: |
| case GEN7_L3CNTLREG1: |
| case GEN7_L3_CHICKEN_MODE_REGISTER: |
| case GEN7_ROW_CHICKEN2: |
| case GEN7_L3SQCREG4: |
| case GEN7_SQ_CHICKEN_MBCUNIT_CONFIG: |
| case GEN7_HALF_SLICE_CHICKEN1: |
| case GEN6_MBCTL: |
| case GEN6_UCGCTL2: |
| return false; |
| default: |
| break; |
| } |
| |
| return true; |
| } |
| |
| /* We give fast paths for the really cool registers */ |
| #define NEEDS_FORCE_WAKE(dev_priv, reg) \ |
| ((HAS_FORCE_WAKE((dev_priv)->dev)) && \ |
| ((reg) < 0x40000) && \ |
| ((reg) != FORCEWAKE)) |
| static void |
| ilk_dummy_write(struct drm_i915_private *dev_priv) |
| { |
| /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up |
| * the chip from rc6 before touching it for real. MI_MODE is masked, |
| * hence harmless to write 0 into. */ |
| I915_WRITE_NOTRACE(MI_MODE, 0); |
| } |
| |
| static void |
| hsw_unclaimed_reg_clear(struct drm_i915_private *dev_priv, u32 reg) |
| { |
| if (HAS_FPGA_DBG_UNCLAIMED(dev_priv->dev) && |
| (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) { |
| DRM_ERROR("Unknown unclaimed register before writing to %x\n", |
| reg); |
| I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
| } |
| } |
| |
| static void |
| hsw_unclaimed_reg_check(struct drm_i915_private *dev_priv, u32 reg) |
| { |
| if (HAS_FPGA_DBG_UNCLAIMED(dev_priv->dev) && |
| (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) { |
| DRM_ERROR("Unclaimed write to %x\n", reg); |
| I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
| } |
| } |
| |