106,32 → 106,6 |
} |
|
/** |
* Sets up the hardware status page for devices that need a physical address |
* in the register. |
*/ |
static int i915_init_phys_hws(struct drm_device *dev) |
{ |
drm_i915_private_t *dev_priv = dev->dev_private; |
|
/* Program Hardware Status Page */ |
dev_priv->status_page_dmah = |
drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE); |
|
if (!dev_priv->status_page_dmah) { |
DRM_ERROR("Can not allocate hardware status page\n"); |
return -ENOMEM; |
} |
|
memset((void __force __iomem *)dev_priv->status_page_dmah->vaddr, |
0, PAGE_SIZE); |
|
i915_write_hws_pga(dev); |
|
DRM_DEBUG_DRIVER("Enabled hardware status page\n"); |
return 0; |
} |
|
/** |
* Frees the hardware status page, whether it's a physical address or a virtual |
* address set up by the X Server. |
*/ |
171,7 → 145,7 |
|
ring->head = I915_READ_HEAD(ring) & HEAD_ADDR; |
ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR; |
ring->space = ring->head - (ring->tail + 8); |
ring->space = ring->head - (ring->tail + I915_RING_FREE_SPACE); |
if (ring->space < 0) |
ring->space += ring->size; |
|
455,16 → 429,16 |
drm_i915_private_t *dev_priv = dev->dev_private; |
struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
|
dev_priv->counter++; |
if (dev_priv->counter > 0x7FFFFFFFUL) |
dev_priv->counter = 0; |
dev_priv->dri1.counter++; |
if (dev_priv->dri1.counter > 0x7FFFFFFFUL) |
dev_priv->dri1.counter = 0; |
if (master_priv->sarea_priv) |
master_priv->sarea_priv->last_enqueue = dev_priv->counter; |
master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter; |
|
if (BEGIN_LP_RING(4) == 0) { |
OUT_RING(MI_STORE_DWORD_INDEX); |
OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
OUT_RING(dev_priv->counter); |
OUT_RING(dev_priv->dri1.counter); |
OUT_RING(0); |
ADVANCE_LP_RING(); |
} |
606,12 → 580,12 |
|
ADVANCE_LP_RING(); |
|
master_priv->sarea_priv->last_enqueue = dev_priv->counter++; |
master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter++; |
|
if (BEGIN_LP_RING(4) == 0) { |
OUT_RING(MI_STORE_DWORD_INDEX); |
OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
OUT_RING(dev_priv->counter); |
OUT_RING(dev_priv->dri1.counter); |
OUT_RING(0); |
ADVANCE_LP_RING(); |
} |
622,10 → 596,8 |
|
static int i915_quiescent(struct drm_device *dev) |
{ |
struct intel_ring_buffer *ring = LP_RING(dev->dev_private); |
|
i915_kernel_lost_context(dev); |
return intel_wait_ring_idle(ring); |
return intel_ring_idle(LP_RING(dev->dev_private)); |
} |
|
static int i915_flush_ioctl(struct drm_device *dev, void *data, |
779,21 → 751,21 |
|
DRM_DEBUG_DRIVER("\n"); |
|
dev_priv->counter++; |
if (dev_priv->counter > 0x7FFFFFFFUL) |
dev_priv->counter = 1; |
dev_priv->dri1.counter++; |
if (dev_priv->dri1.counter > 0x7FFFFFFFUL) |
dev_priv->dri1.counter = 1; |
if (master_priv->sarea_priv) |
master_priv->sarea_priv->last_enqueue = dev_priv->counter; |
master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter; |
|
if (BEGIN_LP_RING(4) == 0) { |
OUT_RING(MI_STORE_DWORD_INDEX); |
OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
OUT_RING(dev_priv->counter); |
OUT_RING(dev_priv->dri1.counter); |
OUT_RING(MI_USER_INTERRUPT); |
ADVANCE_LP_RING(); |
} |
|
return dev_priv->counter; |
return dev_priv->dri1.counter; |
} |
|
static int i915_wait_irq(struct drm_device * dev, int irq_nr) |
824,7 → 796,7 |
|
if (ret == -EBUSY) { |
DRM_ERROR("EBUSY -- rec: %d emitted: %d\n", |
READ_BREADCRUMB(dev_priv), (int)dev_priv->counter); |
READ_BREADCRUMB(dev_priv), (int)dev_priv->dri1.counter); |
} |
|
return ret; |
1018,6 → 990,12 |
case I915_PARAM_HAS_PRIME_VMAP_FLUSH: |
value = 1; |
break; |
case I915_PARAM_HAS_SECURE_BATCHES: |
value = capable(CAP_SYS_ADMIN); |
break; |
case I915_PARAM_HAS_PINNED_BATCHES: |
value = 1; |
break; |
default: |
DRM_DEBUG_DRIVER("Unknown parameter %d\n", |
param->param); |
1074,7 → 1052,7 |
{ |
drm_i915_private_t *dev_priv = dev->dev_private; |
drm_i915_hws_addr_t *hws = data; |
struct intel_ring_buffer *ring = LP_RING(dev_priv); |
struct intel_ring_buffer *ring; |
|
if (drm_core_check_feature(dev, DRIVER_MODESET)) |
return -ENODEV; |
1094,6 → 1072,7 |
|
DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr); |
|
ring = LP_RING(dev_priv); |
ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12); |
|
dev_priv->dri1.gfx_hws_cpu_addr = |
1299,19 → 1278,7 |
|
info = (struct intel_device_info *) flags; |
|
#if 0 |
/* Refuse to load on gen6+ without kms enabled. */ |
if (info->gen >= 6 && !drm_core_check_feature(dev, DRIVER_MODESET)) |
return -ENODEV; |
|
/* i915 has 4 more counters */ |
dev->counters += 4; |
dev->types[6] = _DRM_STAT_IRQ; |
dev->types[7] = _DRM_STAT_PRIMARY; |
dev->types[8] = _DRM_STAT_SECONDARY; |
dev->types[9] = _DRM_STAT_DMA; |
#endif |
|
dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL); |
if (dev_priv == NULL) |
return -ENOMEM; |
1327,26 → 1294,14 |
goto free_priv; |
} |
|
ret = intel_gmch_probe(dev_priv->bridge_dev, dev->pdev, NULL); |
if (!ret) { |
DRM_ERROR("failed to set up gmch\n"); |
ret = -EIO; |
ret = i915_gem_gtt_init(dev); |
if (ret) |
goto put_bridge; |
} |
|
dev_priv->mm.gtt = intel_gtt_get(); |
if (!dev_priv->mm.gtt) { |
DRM_ERROR("Failed to initialize GTT\n"); |
ret = -ENODEV; |
goto put_gmch; |
} |
|
|
pci_set_master(dev->pdev); |
|
/* overlay on gen2 is broken and can't address above 1G */ |
// if (IS_GEN2(dev)) |
// dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30)); |
|
/* 965GM sometimes incorrectly writes to hardware status page (HWS) |
* using 32bit addressing, overwriting memory if HWS is located |
1356,8 → 1311,6 |
* behaviour if any general state is accessed within a page above 4GB, |
* which also needs to be handled carefully. |
*/ |
// if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
// dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32)); |
|
mmio_bar = IS_GEN2(dev) ? 1 : 0; |
/* Before gen4, the registers and the GTT are behind different BARs. |
1382,11 → 1335,7 |
aperture_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT; |
dev_priv->mm.gtt_base_addr = dev_priv->mm.gtt->gma_bus_addr; |
|
DRM_INFO("gtt_base_addr %x aperture_size %d\n", |
dev_priv->mm.gtt_base_addr, aperture_size ); |
|
// i915_mtrr_setup(dev_priv, dev_priv->mm.gtt_base_addr, |
// aperture_size); |
|
/* The i915 workqueue is primarily used for batched retirement of |
* requests (and thus managing bo) once the task has been completed |
1419,18 → 1368,10 |
intel_setup_gmbus(dev); |
intel_opregion_setup(dev); |
|
/* Make sure the bios did its job and set up vital registers */ |
intel_setup_bios(dev); |
|
i915_gem_load(dev); |
|
/* Init HWS */ |
if (!I915_NEED_GFX_HWS(dev)) { |
ret = i915_init_phys_hws(dev); |
if (ret) |
goto out_gem_unload; |
} |
|
/* On the 945G/GM, the chipset reports the MSI capability on the |
* integrated graphics even though the support isn't actually there |
* according to the published specs. It doesn't appear to function |
1448,6 → 1389,8 |
spin_lock_init(&dev_priv->rps.lock); |
spin_lock_init(&dev_priv->dpio_lock); |
|
mutex_init(&dev_priv->rps.hw_lock); |
|
if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) |
dev_priv->num_pipe = 3; |
else if (IS_MOBILE(dev) || !IS_GEN2(dev)) |
1469,13 → 1412,8 |
} |
|
/* Must be done after probing outputs */ |
// intel_opregion_init(dev); |
// acpi_video_register(); |
|
// setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed, |
// (unsigned long) dev); |
|
|
if (IS_GEN5(dev)) |
intel_gpu_ips_init(dev_priv); |
|
1547,6 → 1485,7 |
if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
intel_fbdev_fini(dev); |
intel_modeset_cleanup(dev); |
cancel_work_sync(&dev_priv->console_resume_work); |
|
/* |
* free the memory space allocated for the child device |