| /drivers/video/drm/radeon/Makefile |
|---|
| 55,6 → 55,7 |
| radeon_device.c \ |
| evergreen.c \ |
| evergreen_blit_shaders.c \ |
| evergreen_blit_kms.c \ |
| cayman_blit_shaders.c \ |
| radeon_clocks.c \ |
| atom.c \ |
| 62,6 → 63,7 |
| radeon_agp.c \ |
| radeon_asic.c \ |
| radeon_atombios.c \ |
| radeon_benchmark.c \ |
| radeon_bios.c \ |
| radeon_combios.c \ |
| radeon_connectors.c \ |
| 88,6 → 90,8 |
| r520.c \ |
| r600.c \ |
| r600_audio.c \ |
| r600_blit_kms.c \ |
| r600_blit_shaders.c \ |
| r600_hdmi.c \ |
| rs400.c \ |
| rs600.c \ |
| /drivers/video/drm/radeon/Makefile.lto |
|---|
| 55,6 → 55,7 |
| radeon_device.c \ |
| evergreen.c \ |
| evergreen_blit_shaders.c \ |
| evergreen_blit_kms.c \ |
| cayman_blit_shaders.c \ |
| radeon_clocks.c \ |
| atom.c \ |
| 62,6 → 63,7 |
| radeon_agp.c \ |
| radeon_asic.c \ |
| radeon_atombios.c \ |
| radeon_benchmark.c \ |
| radeon_bios.c \ |
| radeon_combios.c \ |
| radeon_connectors.c \ |
| 88,6 → 90,8 |
| r520.c \ |
| r600.c \ |
| r600_audio.c \ |
| r600_blit_kms.c \ |
| r600_blit_shaders.c \ |
| r600_hdmi.c \ |
| rs400.c \ |
| rs600.c \ |
| /drivers/video/drm/radeon/cmdline.c |
|---|
| 6,6 → 6,8 |
| #include "radeon.h" |
| #include "radeon_object.h" |
| extern int radeon_benchmarking; |
| static int my_atoi(char **cmd) |
| { |
| char* p = *cmd; |
| 74,8 → 76,8 |
| { |
| switch(*p++) |
| { |
| case 'm': |
| p = parse_mode(p, mode); |
| case 'b': |
| radeon_benchmarking = 1; |
| break; |
| case 'l': |
| 82,6 → 84,10 |
| p = parse_path(p, log); |
| break; |
| case 'm': |
| p = parse_mode(p, mode); |
| break; |
| case 'n': |
| *kms = 0; |
| }; |
| /drivers/video/drm/radeon/evergreen.c |
|---|
| 319,12 → 319,10 |
| break; |
| } |
| } |
| // if (rdev->irq.installed) |
| // evergreen_irq_set(rdev); |
| if (rdev->irq.installed) |
| evergreen_irq_set(rdev); |
| } |
| #if 0 |
| void evergreen_hpd_fini(struct radeon_device *rdev) |
| { |
| struct drm_device *dev = rdev->ddev; |
| 363,7 → 361,6 |
| } |
| } |
| #endif |
| /* watermark setup */ |
| static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev, |
| 978,17 → 975,19 |
| { |
| save->vga_control[0] = RREG32(D1VGA_CONTROL); |
| save->vga_control[1] = RREG32(D2VGA_CONTROL); |
| save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL); |
| save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL); |
| save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL); |
| save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL); |
| save->vga_render_control = RREG32(VGA_RENDER_CONTROL); |
| save->vga_hdp_control = RREG32(VGA_HDP_CONTROL); |
| save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET); |
| save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); |
| if (!(rdev->flags & RADEON_IS_IGP)) { |
| if (rdev->num_crtc >= 4) { |
| save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL); |
| save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL); |
| save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET); |
| save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); |
| } |
| if (rdev->num_crtc >= 6) { |
| save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL); |
| save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL); |
| save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET); |
| save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); |
| } |
| 997,25 → 996,31 |
| WREG32(VGA_RENDER_CONTROL, 0); |
| WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1); |
| WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1); |
| if (!(rdev->flags & RADEON_IS_IGP)) { |
| if (rdev->num_crtc >= 4) { |
| WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1); |
| WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1); |
| } |
| if (rdev->num_crtc >= 6) { |
| WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1); |
| WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1); |
| } |
| WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); |
| WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); |
| if (!(rdev->flags & RADEON_IS_IGP)) { |
| if (rdev->num_crtc >= 4) { |
| WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); |
| WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); |
| } |
| if (rdev->num_crtc >= 6) { |
| WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); |
| WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); |
| } |
| WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); |
| WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); |
| if (!(rdev->flags & RADEON_IS_IGP)) { |
| if (rdev->num_crtc >= 4) { |
| WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); |
| WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); |
| } |
| if (rdev->num_crtc >= 6) { |
| WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); |
| WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); |
| } |
| 1022,11 → 1027,15 |
| WREG32(D1VGA_CONTROL, 0); |
| WREG32(D2VGA_CONTROL, 0); |
| if (rdev->num_crtc >= 4) { |
| WREG32(EVERGREEN_D3VGA_CONTROL, 0); |
| WREG32(EVERGREEN_D4VGA_CONTROL, 0); |
| } |
| if (rdev->num_crtc >= 6) { |
| WREG32(EVERGREEN_D5VGA_CONTROL, 0); |
| WREG32(EVERGREEN_D6VGA_CONTROL, 0); |
| } |
| } |
| void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save) |
| { |
| 1048,7 → 1057,7 |
| WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET, |
| (u32)rdev->mc.vram_start); |
| if (!(rdev->flags & RADEON_IS_IGP)) { |
| if (rdev->num_crtc >= 4) { |
| WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET, |
| upper_32_bits(rdev->mc.vram_start)); |
| WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET, |
| 1066,7 → 1075,8 |
| (u32)rdev->mc.vram_start); |
| WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET, |
| (u32)rdev->mc.vram_start); |
| } |
| if (rdev->num_crtc >= 6) { |
| WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET, |
| upper_32_bits(rdev->mc.vram_start)); |
| WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET, |
| 1094,31 → 1104,41 |
| /* Restore video state */ |
| WREG32(D1VGA_CONTROL, save->vga_control[0]); |
| WREG32(D2VGA_CONTROL, save->vga_control[1]); |
| if (rdev->num_crtc >= 4) { |
| WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]); |
| WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]); |
| } |
| if (rdev->num_crtc >= 6) { |
| WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]); |
| WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]); |
| } |
| WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1); |
| WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1); |
| if (!(rdev->flags & RADEON_IS_IGP)) { |
| if (rdev->num_crtc >= 4) { |
| WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1); |
| WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1); |
| } |
| if (rdev->num_crtc >= 6) { |
| WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1); |
| WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1); |
| } |
| WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]); |
| WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]); |
| if (!(rdev->flags & RADEON_IS_IGP)) { |
| if (rdev->num_crtc >= 4) { |
| WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]); |
| WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]); |
| } |
| if (rdev->num_crtc >= 6) { |
| WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]); |
| WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]); |
| } |
| WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); |
| WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); |
| if (!(rdev->flags & RADEON_IS_IGP)) { |
| if (rdev->num_crtc >= 4) { |
| WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); |
| WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); |
| } |
| if (rdev->num_crtc >= 6) { |
| WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); |
| WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); |
| } |
| 1970,7 → 1990,7 |
| gb_backend_map = 0x66442200; |
| break; |
| case CHIP_JUNIPER: |
| gb_backend_map = 0x00006420; |
| gb_backend_map = 0x00002200; |
| break; |
| default: |
| gb_backend_map = |
| 2410,9 → 2430,11 |
| WREG32(GRBM_INT_CNTL, 0); |
| WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); |
| WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); |
| if (!(rdev->flags & RADEON_IS_IGP)) { |
| if (rdev->num_crtc >= 4) { |
| WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); |
| WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); |
| } |
| if (rdev->num_crtc >= 6) { |
| WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); |
| WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); |
| } |
| 2419,9 → 2441,11 |
| WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); |
| WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); |
| if (!(rdev->flags & RADEON_IS_IGP)) { |
| if (rdev->num_crtc >= 4) { |
| WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); |
| WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); |
| } |
| if (rdev->num_crtc >= 6) { |
| WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); |
| WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); |
| } |
| 2443,6 → 2467,526 |
| WREG32(DC_HPD6_INT_CONTROL, tmp); |
| } |
| int evergreen_irq_set(struct radeon_device *rdev) |
| { |
| u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; |
| u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0; |
| u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6; |
| u32 grbm_int_cntl = 0; |
| u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0; |
| if (!rdev->irq.installed) { |
| WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); |
| return -EINVAL; |
| } |
| /* don't enable anything if the ih is disabled */ |
| if (!rdev->ih.enabled) { |
| r600_disable_interrupts(rdev); |
| /* force the active interrupt state to all disabled */ |
| evergreen_disable_interrupt_state(rdev); |
| return 0; |
| } |
| hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; |
| hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN; |
| hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN; |
| hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN; |
| hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; |
| hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; |
| if (rdev->irq.sw_int) { |
| DRM_DEBUG("evergreen_irq_set: sw int\n"); |
| cp_int_cntl |= RB_INT_ENABLE; |
| cp_int_cntl |= TIME_STAMP_INT_ENABLE; |
| } |
| if (rdev->irq.crtc_vblank_int[0] || |
| rdev->irq.pflip[0]) { |
| DRM_DEBUG("evergreen_irq_set: vblank 0\n"); |
| crtc1 |= VBLANK_INT_MASK; |
| } |
| if (rdev->irq.crtc_vblank_int[1] || |
| rdev->irq.pflip[1]) { |
| DRM_DEBUG("evergreen_irq_set: vblank 1\n"); |
| crtc2 |= VBLANK_INT_MASK; |
| } |
| if (rdev->irq.crtc_vblank_int[2] || |
| rdev->irq.pflip[2]) { |
| DRM_DEBUG("evergreen_irq_set: vblank 2\n"); |
| crtc3 |= VBLANK_INT_MASK; |
| } |
| if (rdev->irq.crtc_vblank_int[3] || |
| rdev->irq.pflip[3]) { |
| DRM_DEBUG("evergreen_irq_set: vblank 3\n"); |
| crtc4 |= VBLANK_INT_MASK; |
| } |
| if (rdev->irq.crtc_vblank_int[4] || |
| rdev->irq.pflip[4]) { |
| DRM_DEBUG("evergreen_irq_set: vblank 4\n"); |
| crtc5 |= VBLANK_INT_MASK; |
| } |
| if (rdev->irq.crtc_vblank_int[5] || |
| rdev->irq.pflip[5]) { |
| DRM_DEBUG("evergreen_irq_set: vblank 5\n"); |
| crtc6 |= VBLANK_INT_MASK; |
| } |
| if (rdev->irq.hpd[0]) { |
| DRM_DEBUG("evergreen_irq_set: hpd 1\n"); |
| hpd1 |= DC_HPDx_INT_EN; |
| } |
| if (rdev->irq.hpd[1]) { |
| DRM_DEBUG("evergreen_irq_set: hpd 2\n"); |
| hpd2 |= DC_HPDx_INT_EN; |
| } |
| if (rdev->irq.hpd[2]) { |
| DRM_DEBUG("evergreen_irq_set: hpd 3\n"); |
| hpd3 |= DC_HPDx_INT_EN; |
| } |
| if (rdev->irq.hpd[3]) { |
| DRM_DEBUG("evergreen_irq_set: hpd 4\n"); |
| hpd4 |= DC_HPDx_INT_EN; |
| } |
| if (rdev->irq.hpd[4]) { |
| DRM_DEBUG("evergreen_irq_set: hpd 5\n"); |
| hpd5 |= DC_HPDx_INT_EN; |
| } |
| if (rdev->irq.hpd[5]) { |
| DRM_DEBUG("evergreen_irq_set: hpd 6\n"); |
| hpd6 |= DC_HPDx_INT_EN; |
| } |
| if (rdev->irq.gui_idle) { |
| DRM_DEBUG("gui idle\n"); |
| grbm_int_cntl |= GUI_IDLE_INT_ENABLE; |
| } |
| WREG32(CP_INT_CNTL, cp_int_cntl); |
| WREG32(GRBM_INT_CNTL, grbm_int_cntl); |
| WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1); |
| WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2); |
| if (rdev->num_crtc >= 4) { |
| WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3); |
| WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4); |
| } |
| if (rdev->num_crtc >= 6) { |
| WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5); |
| WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6); |
| } |
| WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1); |
| WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2); |
| if (rdev->num_crtc >= 4) { |
| WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3); |
| WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4); |
| } |
| if (rdev->num_crtc >= 6) { |
| WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5); |
| WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6); |
| } |
| WREG32(DC_HPD1_INT_CONTROL, hpd1); |
| WREG32(DC_HPD2_INT_CONTROL, hpd2); |
| WREG32(DC_HPD3_INT_CONTROL, hpd3); |
| WREG32(DC_HPD4_INT_CONTROL, hpd4); |
| WREG32(DC_HPD5_INT_CONTROL, hpd5); |
| WREG32(DC_HPD6_INT_CONTROL, hpd6); |
| return 0; |
| } |
| static inline void evergreen_irq_ack(struct radeon_device *rdev) |
| { |
| u32 tmp; |
| rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS); |
| rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); |
| rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2); |
| rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3); |
| rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4); |
| rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5); |
| rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET); |
| rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET); |
| if (rdev->num_crtc >= 4) { |
| rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET); |
| rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET); |
| } |
| if (rdev->num_crtc >= 6) { |
| rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET); |
| rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET); |
| } |
| if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED) |
| WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); |
| if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED) |
| WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); |
| if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) |
| WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK); |
| if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) |
| WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK); |
| if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) |
| WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK); |
| if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) |
| WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK); |
| if (rdev->num_crtc >= 4) { |
| if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED) |
| WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); |
| if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED) |
| WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); |
| if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) |
| WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK); |
| if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) |
| WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK); |
| if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) |
| WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK); |
| if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) |
| WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK); |
| } |
| if (rdev->num_crtc >= 6) { |
| if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED) |
| WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); |
| if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED) |
| WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); |
| if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) |
| WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK); |
| if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) |
| WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK); |
| if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) |
| WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK); |
| if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) |
| WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK); |
| } |
| if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) { |
| tmp = RREG32(DC_HPD1_INT_CONTROL); |
| tmp |= DC_HPDx_INT_ACK; |
| WREG32(DC_HPD1_INT_CONTROL, tmp); |
| } |
| if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) { |
| tmp = RREG32(DC_HPD2_INT_CONTROL); |
| tmp |= DC_HPDx_INT_ACK; |
| WREG32(DC_HPD2_INT_CONTROL, tmp); |
| } |
| if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) { |
| tmp = RREG32(DC_HPD3_INT_CONTROL); |
| tmp |= DC_HPDx_INT_ACK; |
| WREG32(DC_HPD3_INT_CONTROL, tmp); |
| } |
| if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) { |
| tmp = RREG32(DC_HPD4_INT_CONTROL); |
| tmp |= DC_HPDx_INT_ACK; |
| WREG32(DC_HPD4_INT_CONTROL, tmp); |
| } |
| if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) { |
| tmp = RREG32(DC_HPD5_INT_CONTROL); |
| tmp |= DC_HPDx_INT_ACK; |
| WREG32(DC_HPD5_INT_CONTROL, tmp); |
| } |
| if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) { |
| tmp = RREG32(DC_HPD5_INT_CONTROL); |
| tmp |= DC_HPDx_INT_ACK; |
| WREG32(DC_HPD6_INT_CONTROL, tmp); |
| } |
| } |
| static inline u32 evergreen_get_ih_wptr(struct radeon_device *rdev) |
| { |
| u32 wptr, tmp; |
| if (rdev->wb.enabled) |
| wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]); |
| else |
| wptr = RREG32(IH_RB_WPTR); |
| if (wptr & RB_OVERFLOW) { |
| /* When a ring buffer overflow happen start parsing interrupt |
| * from the last not overwritten vector (wptr + 16). Hopefully |
| * this should allow us to catchup. |
| */ |
| dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n", |
| wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask); |
| rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; |
| tmp = RREG32(IH_RB_CNTL); |
| tmp |= IH_WPTR_OVERFLOW_CLEAR; |
| WREG32(IH_RB_CNTL, tmp); |
| } |
| return (wptr & rdev->ih.ptr_mask); |
| } |
| int evergreen_irq_process(struct radeon_device *rdev) |
| { |
| u32 wptr; |
| u32 rptr; |
| u32 src_id, src_data; |
| u32 ring_index; |
| unsigned long flags; |
| bool queue_hotplug = false; |
| if (!rdev->ih.enabled || rdev->shutdown) |
| return IRQ_NONE; |
| wptr = evergreen_get_ih_wptr(rdev); |
| rptr = rdev->ih.rptr; |
| DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); |
| spin_lock_irqsave(&rdev->ih.lock, flags); |
| if (rptr == wptr) { |
| spin_unlock_irqrestore(&rdev->ih.lock, flags); |
| return IRQ_NONE; |
| } |
| restart_ih: |
| /* display interrupts */ |
| evergreen_irq_ack(rdev); |
| rdev->ih.wptr = wptr; |
| while (rptr != wptr) { |
| /* wptr/rptr are in bytes! */ |
| ring_index = rptr / 4; |
| src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff; |
| src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff; |
| switch (src_id) { |
| case 1: /* D1 vblank/vline */ |
| switch (src_data) { |
| case 0: /* D1 vblank */ |
| if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) { |
| if (rdev->irq.crtc_vblank_int[0]) { |
| // drm_handle_vblank(rdev->ddev, 0); |
| rdev->pm.vblank_sync = true; |
| // wake_up(&rdev->irq.vblank_queue); |
| } |
| // if (rdev->irq.pflip[0]) |
| // radeon_crtc_handle_flip(rdev, 0); |
| rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT; |
| DRM_DEBUG("IH: D1 vblank\n"); |
| } |
| break; |
| case 1: /* D1 vline */ |
| if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) { |
| rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT; |
| DRM_DEBUG("IH: D1 vline\n"); |
| } |
| break; |
| default: |
| DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
| break; |
| } |
| break; |
| case 2: /* D2 vblank/vline */ |
| switch (src_data) { |
| case 0: /* D2 vblank */ |
| if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) { |
| if (rdev->irq.crtc_vblank_int[1]) { |
| // drm_handle_vblank(rdev->ddev, 1); |
| rdev->pm.vblank_sync = true; |
| // wake_up(&rdev->irq.vblank_queue); |
| } |
| // if (rdev->irq.pflip[1]) |
| // radeon_crtc_handle_flip(rdev, 1); |
| rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT; |
| DRM_DEBUG("IH: D2 vblank\n"); |
| } |
| break; |
| case 1: /* D2 vline */ |
| if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) { |
| rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT; |
| DRM_DEBUG("IH: D2 vline\n"); |
| } |
| break; |
| default: |
| DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
| break; |
| } |
| break; |
| case 3: /* D3 vblank/vline */ |
| switch (src_data) { |
| case 0: /* D3 vblank */ |
| if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) { |
| if (rdev->irq.crtc_vblank_int[2]) { |
| // drm_handle_vblank(rdev->ddev, 2); |
| rdev->pm.vblank_sync = true; |
| // wake_up(&rdev->irq.vblank_queue); |
| } |
| // if (rdev->irq.pflip[2]) |
| // radeon_crtc_handle_flip(rdev, 2); |
| rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT; |
| DRM_DEBUG("IH: D3 vblank\n"); |
| } |
| break; |
| case 1: /* D3 vline */ |
| if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) { |
| rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT; |
| DRM_DEBUG("IH: D3 vline\n"); |
| } |
| break; |
| default: |
| DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
| break; |
| } |
| break; |
| case 4: /* D4 vblank/vline */ |
| switch (src_data) { |
| case 0: /* D4 vblank */ |
| if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) { |
| if (rdev->irq.crtc_vblank_int[3]) { |
| // drm_handle_vblank(rdev->ddev, 3); |
| rdev->pm.vblank_sync = true; |
| // wake_up(&rdev->irq.vblank_queue); |
| } |
| // if (rdev->irq.pflip[3]) |
| // radeon_crtc_handle_flip(rdev, 3); |
| rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT; |
| DRM_DEBUG("IH: D4 vblank\n"); |
| } |
| break; |
| case 1: /* D4 vline */ |
| if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) { |
| rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT; |
| DRM_DEBUG("IH: D4 vline\n"); |
| } |
| break; |
| default: |
| DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
| break; |
| } |
| break; |
| case 5: /* D5 vblank/vline */ |
| switch (src_data) { |
| case 0: /* D5 vblank */ |
| if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) { |
| if (rdev->irq.crtc_vblank_int[4]) { |
| // drm_handle_vblank(rdev->ddev, 4); |
| rdev->pm.vblank_sync = true; |
| // wake_up(&rdev->irq.vblank_queue); |
| } |
| // if (rdev->irq.pflip[4]) |
| // radeon_crtc_handle_flip(rdev, 4); |
| rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT; |
| DRM_DEBUG("IH: D5 vblank\n"); |
| } |
| break; |
| case 1: /* D5 vline */ |
| if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) { |
| rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT; |
| DRM_DEBUG("IH: D5 vline\n"); |
| } |
| break; |
| default: |
| DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
| break; |
| } |
| break; |
| case 6: /* D6 vblank/vline */ |
| switch (src_data) { |
| case 0: /* D6 vblank */ |
| if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) { |
| if (rdev->irq.crtc_vblank_int[5]) { |
| // drm_handle_vblank(rdev->ddev, 5); |
| rdev->pm.vblank_sync = true; |
| // wake_up(&rdev->irq.vblank_queue); |
| } |
| // if (rdev->irq.pflip[5]) |
| // radeon_crtc_handle_flip(rdev, 5); |
| rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT; |
| DRM_DEBUG("IH: D6 vblank\n"); |
| } |
| break; |
| case 1: /* D6 vline */ |
| if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) { |
| rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT; |
| DRM_DEBUG("IH: D6 vline\n"); |
| } |
| break; |
| default: |
| DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
| break; |
| } |
| break; |
| case 42: /* HPD hotplug */ |
| switch (src_data) { |
| case 0: |
| if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) { |
| rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT; |
| queue_hotplug = true; |
| DRM_DEBUG("IH: HPD1\n"); |
| } |
| break; |
| case 1: |
| if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) { |
| rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT; |
| queue_hotplug = true; |
| DRM_DEBUG("IH: HPD2\n"); |
| } |
| break; |
| case 2: |
| if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) { |
| rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT; |
| queue_hotplug = true; |
| DRM_DEBUG("IH: HPD3\n"); |
| } |
| break; |
| case 3: |
| if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) { |
| rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT; |
| queue_hotplug = true; |
| DRM_DEBUG("IH: HPD4\n"); |
| } |
| break; |
| case 4: |
| if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) { |
| rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT; |
| queue_hotplug = true; |
| DRM_DEBUG("IH: HPD5\n"); |
| } |
| break; |
| case 5: |
| if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) { |
| rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT; |
| queue_hotplug = true; |
| DRM_DEBUG("IH: HPD6\n"); |
| } |
| break; |
| default: |
| DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
| break; |
| } |
| break; |
| case 176: /* CP_INT in ring buffer */ |
| case 177: /* CP_INT in IB1 */ |
| case 178: /* CP_INT in IB2 */ |
| DRM_DEBUG("IH: CP int: 0x%08x\n", src_data); |
| radeon_fence_process(rdev); |
| break; |
| case 181: /* CP EOP event */ |
| DRM_DEBUG("IH: CP EOP\n"); |
| radeon_fence_process(rdev); |
| break; |
| case 233: /* GUI IDLE */ |
| DRM_DEBUG("IH: GUI idle\n"); |
| rdev->pm.gui_idle = true; |
| // wake_up(&rdev->irq.idle_queue); |
| break; |
| default: |
| DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); |
| break; |
| } |
| /* wptr/rptr are in bytes! */ |
| rptr += 16; |
| rptr &= rdev->ih.ptr_mask; |
| } |
| /* make sure wptr hasn't changed while processing */ |
| wptr = evergreen_get_ih_wptr(rdev); |
| if (wptr != rdev->ih.wptr) |
| goto restart_ih; |
| // if (queue_hotplug) |
| // schedule_work(&rdev->hotplug_work); |
| rdev->ih.rptr = rptr; |
| WREG32(IH_RB_RPTR, rdev->ih.rptr); |
| spin_unlock_irqrestore(&rdev->ih.lock, flags); |
| return IRQ_HANDLED; |
| } |
| static int evergreen_startup(struct radeon_device *rdev) |
| { |
| int r; |
| 2483,7 → 3027,7 |
| return r; |
| } |
| evergreen_gpu_init(rdev); |
| #if 0 |
| r = evergreen_blit_init(rdev); |
| if (r) { |
| evergreen_blit_fini(rdev); |
| 2495,9 → 3039,15 |
| r = radeon_wb_init(rdev); |
| if (r) |
| return r; |
| #endif |
| /* Enable IRQ */ |
| r = r600_irq_init(rdev); |
| if (r) { |
| DRM_ERROR("radeon: IH init failed (%d).\n", r); |
| // radeon_irq_kms_fini(rdev); |
| return r; |
| } |
| evergreen_irq_set(rdev); |
| r = radeon_ring_init(rdev, rdev->cp.ring_size); |
| if (r) |
| 2516,7 → 3066,26 |
| int evergreen_copy_blit(struct radeon_device *rdev, |
| uint64_t src_offset, uint64_t dst_offset, |
| unsigned num_pages, struct radeon_fence *fence) |
| { |
| int r; |
| mutex_lock(&rdev->r600_blit.mutex); |
| rdev->r600_blit.vb_ib = NULL; |
| r = evergreen_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE); |
| if (r) { |
| if (rdev->r600_blit.vb_ib) |
| radeon_ib_free(rdev, &rdev->r600_blit.vb_ib); |
| mutex_unlock(&rdev->r600_blit.mutex); |
| return r; |
| } |
| evergreen_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE); |
| evergreen_blit_done_copy(rdev, fence); |
| mutex_unlock(&rdev->r600_blit.mutex); |
| return 0; |
| } |
| /* Plan is to move initialization in that function and use |
| * helper function so that radeon_device_init pretty much |
| 2566,6 → 3135,9 |
| /* Initialize clocks */ |
| radeon_get_clock_info(rdev->ddev); |
| /* Fence driver */ |
| r = radeon_fence_driver_init(rdev); |
| if (r) |
| return r; |
| /* initialize AGP */ |
| if (rdev->flags & RADEON_IS_AGP) { |
| r = radeon_agp_init(rdev); |
| 2581,12 → 3153,15 |
| if (r) |
| return r; |
| r = radeon_irq_kms_init(rdev); |
| if (r) |
| return r; |
| rdev->cp.ring_obj = NULL; |
| r600_ring_init(rdev, 1024 * 1024); |
| // rdev->ih.ring_obj = NULL; |
| // r600_ih_ring_init(rdev, 64 * 1024); |
| rdev->ih.ring_obj = NULL; |
| r600_ih_ring_init(rdev, 64 * 1024); |
| r = r600_pcie_gart_init(rdev); |
| if (r) |
| 2599,7 → 3174,17 |
| rdev->accel_working = false; |
| } |
| if (rdev->accel_working) { |
| r = radeon_ib_pool_init(rdev); |
| if (r) { |
| DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r); |
| rdev->accel_working = false; |
| } |
| r = r600_ib_test(rdev); |
| if (r) { |
| DRM_ERROR("radeon: failed testing IB (%d).\n", r); |
| rdev->accel_working = false; |
| } |
| } |
| return 0; |
| } |
| /drivers/video/drm/radeon/evergreen_blit_kms.c |
|---|
| 0,0 → 1,988 |
| /* |
| * Copyright 2010 Advanced Micro Devices, Inc. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice (including the next |
| * paragraph) shall be included in all copies or substantial portions of the |
| * Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| * DEALINGS IN THE SOFTWARE. |
| * |
| * Authors: |
| * Alex Deucher <alexander.deucher@amd.com> |
| */ |
| #include "drmP.h" |
| #include "drm.h" |
| #include "radeon_drm.h" |
| #include "radeon.h" |
| #include "evergreend.h" |
| #include "evergreen_blit_shaders.h" |
| #include "cayman_blit_shaders.h" |
| #define DI_PT_RECTLIST 0x11 |
| #define DI_INDEX_SIZE_16_BIT 0x0 |
| #define DI_SRC_SEL_AUTO_INDEX 0x2 |
| #define FMT_8 0x1 |
| #define FMT_5_6_5 0x8 |
| #define FMT_8_8_8_8 0x1a |
| #define COLOR_8 0x1 |
| #define COLOR_5_6_5 0x8 |
| #define COLOR_8_8_8_8 0x1a |
| /* emits 17 */ |
| static void |
| set_render_target(struct radeon_device *rdev, int format, |
| int w, int h, u64 gpu_addr) |
| { |
| u32 cb_color_info; |
| int pitch, slice; |
| h = ALIGN(h, 8); |
| if (h < 8) |
| h = 8; |
| cb_color_info = ((format << 2) | (1 << 24) | (1 << 8)); |
| pitch = (w / 8) - 1; |
| slice = ((w * h) / 64) - 1; |
| radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 15)); |
| radeon_ring_write(rdev, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_START) >> 2); |
| radeon_ring_write(rdev, gpu_addr >> 8); |
| radeon_ring_write(rdev, pitch); |
| radeon_ring_write(rdev, slice); |
| radeon_ring_write(rdev, 0); |
| radeon_ring_write(rdev, cb_color_info); |
| radeon_ring_write(rdev, (1 << 4)); |
| radeon_ring_write(rdev, (w - 1) | ((h - 1) << 16)); |
| radeon_ring_write(rdev, 0); |
| radeon_ring_write(rdev, 0); |
| radeon_ring_write(rdev, 0); |
| radeon_ring_write(rdev, 0); |
| radeon_ring_write(rdev, 0); |
| radeon_ring_write(rdev, 0); |
| radeon_ring_write(rdev, 0); |
| radeon_ring_write(rdev, 0); |
| } |
| /* emits 5dw */ |
| static void |
| cp_set_surface_sync(struct radeon_device *rdev, |
| u32 sync_type, u32 size, |
| u64 mc_addr) |
| { |
| u32 cp_coher_size; |
| if (size == 0xffffffff) |
| cp_coher_size = 0xffffffff; |
| else |
| cp_coher_size = ((size + 255) >> 8); |
| radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3)); |
| radeon_ring_write(rdev, sync_type); |
| radeon_ring_write(rdev, cp_coher_size); |
| radeon_ring_write(rdev, mc_addr >> 8); |
| radeon_ring_write(rdev, 10); /* poll interval */ |
| } |
| /* emits 11dw + 1 surface sync = 16dw */ |
| static void |
| set_shaders(struct radeon_device *rdev) |
| { |
| u64 gpu_addr; |
| /* VS */ |
| gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset; |
| radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 3)); |
| radeon_ring_write(rdev, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_START) >> 2); |
| radeon_ring_write(rdev, gpu_addr >> 8); |
| radeon_ring_write(rdev, 2); |
| radeon_ring_write(rdev, 0); |
| /* PS */ |
| gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset; |
| radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 4)); |
| radeon_ring_write(rdev, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_START) >> 2); |
| radeon_ring_write(rdev, gpu_addr >> 8); |
| radeon_ring_write(rdev, 1); |
| radeon_ring_write(rdev, 0); |
| radeon_ring_write(rdev, 2); |
| gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset; |
| cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr); |
| } |
| /* emits 10 + 1 sync (5) = 15 */ |
| static void |
| set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr) |
| { |
| u32 sq_vtx_constant_word2, sq_vtx_constant_word3; |
| /* high addr, stride */ |
| sq_vtx_constant_word2 = ((upper_32_bits(gpu_addr) & 0xff) | (16 << 8)); |
| #ifdef __BIG_ENDIAN |
| sq_vtx_constant_word2 |= (2 << 30); |
| #endif |
| /* xyzw swizzles */ |
| sq_vtx_constant_word3 = (0 << 3) | (1 << 6) | (2 << 9) | (3 << 12); |
| radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 8)); |
| radeon_ring_write(rdev, 0x580); |
| radeon_ring_write(rdev, gpu_addr & 0xffffffff); |
| radeon_ring_write(rdev, 48 - 1); /* size */ |
| radeon_ring_write(rdev, sq_vtx_constant_word2); |
| radeon_ring_write(rdev, sq_vtx_constant_word3); |
| radeon_ring_write(rdev, 0); |
| radeon_ring_write(rdev, 0); |
| radeon_ring_write(rdev, 0); |
| radeon_ring_write(rdev, SQ_TEX_VTX_VALID_BUFFER << 30); |
| if ((rdev->family == CHIP_CEDAR) || |
| (rdev->family == CHIP_PALM) || |
| (rdev->family == CHIP_SUMO) || |
| (rdev->family == CHIP_SUMO2) || |
| (rdev->family == CHIP_CAICOS)) |
| cp_set_surface_sync(rdev, |
| PACKET3_TC_ACTION_ENA, 48, gpu_addr); |
| else |
| cp_set_surface_sync(rdev, |
| PACKET3_VC_ACTION_ENA, 48, gpu_addr); |
| } |
| /* emits 10 */ |
| static void |
| set_tex_resource(struct radeon_device *rdev, |
| int format, int w, int h, int pitch, |
| u64 gpu_addr) |
| { |
| u32 sq_tex_resource_word0, sq_tex_resource_word1; |
| u32 sq_tex_resource_word4, sq_tex_resource_word7; |
| if (h < 1) |
| h = 1; |
| sq_tex_resource_word0 = (1 << 0); /* 2D */ |
| sq_tex_resource_word0 |= ((((pitch >> 3) - 1) << 6) | |
| ((w - 1) << 18)); |
| sq_tex_resource_word1 = ((h - 1) << 0) | (1 << 28); |
| /* xyzw swizzles */ |
| sq_tex_resource_word4 = (0 << 16) | (1 << 19) | (2 << 22) | (3 << 25); |
| sq_tex_resource_word7 = format | (SQ_TEX_VTX_VALID_TEXTURE << 30); |
| radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 8)); |
| radeon_ring_write(rdev, 0); |
| radeon_ring_write(rdev, sq_tex_resource_word0); |
| radeon_ring_write(rdev, sq_tex_resource_word1); |
| radeon_ring_write(rdev, gpu_addr >> 8); |
| radeon_ring_write(rdev, gpu_addr >> 8); |
| radeon_ring_write(rdev, sq_tex_resource_word4); |
| radeon_ring_write(rdev, 0); |
| radeon_ring_write(rdev, 0); |
| radeon_ring_write(rdev, sq_tex_resource_word7); |
| } |
| /* emits 12 */ |
| static void |
| set_scissors(struct radeon_device *rdev, int x1, int y1, |
| int x2, int y2) |
| { |
| /* workaround some hw bugs */ |
| if (x2 == 0) |
| x1 = 1; |
| if (y2 == 0) |
| y1 = 1; |
| if (rdev->family == CHIP_CAYMAN) { |
| if ((x2 == 1) && (y2 == 1)) |
| x2 = 2; |
| } |
| radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); |
| radeon_ring_write(rdev, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2); |
| radeon_ring_write(rdev, (x1 << 0) | (y1 << 16)); |
| radeon_ring_write(rdev, (x2 << 0) | (y2 << 16)); |
| radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); |
| radeon_ring_write(rdev, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2); |
| radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31)); |
| radeon_ring_write(rdev, (x2 << 0) | (y2 << 16)); |
| radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); |
| radeon_ring_write(rdev, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2); |
| radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31)); |
| radeon_ring_write(rdev, (x2 << 0) | (y2 << 16)); |
| } |
| /* emits 10 */ |
| static void |
| draw_auto(struct radeon_device *rdev) |
| { |
| radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
| radeon_ring_write(rdev, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_START) >> 2); |
| radeon_ring_write(rdev, DI_PT_RECTLIST); |
| radeon_ring_write(rdev, PACKET3(PACKET3_INDEX_TYPE, 0)); |
| radeon_ring_write(rdev, |
| #ifdef __BIG_ENDIAN |
| (2 << 2) | |
| #endif |
| DI_INDEX_SIZE_16_BIT); |
| radeon_ring_write(rdev, PACKET3(PACKET3_NUM_INSTANCES, 0)); |
| radeon_ring_write(rdev, 1); |
| radeon_ring_write(rdev, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1)); |
| radeon_ring_write(rdev, 3); |
| radeon_ring_write(rdev, DI_SRC_SEL_AUTO_INDEX); |
| } |
| /* emits 39 */ |
| static void |
| set_default_state(struct radeon_device *rdev) |
| { |
| u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2, sq_gpr_resource_mgmt_3; |
| u32 sq_thread_resource_mgmt, sq_thread_resource_mgmt_2; |
| u32 sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2, sq_stack_resource_mgmt_3; |
| int num_ps_gprs, num_vs_gprs, num_temp_gprs; |
| int num_gs_gprs, num_es_gprs, num_hs_gprs, num_ls_gprs; |
| int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads; |
| int num_hs_threads, num_ls_threads; |
| int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries; |
| int num_hs_stack_entries, num_ls_stack_entries; |
| u64 gpu_addr; |
| int dwords; |
| /* set clear context state */ |
| radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0)); |
| radeon_ring_write(rdev, 0); |
| if (rdev->family < CHIP_CAYMAN) { |
| switch (rdev->family) { |
| case CHIP_CEDAR: |
| default: |
| num_ps_gprs = 93; |
| num_vs_gprs = 46; |
| num_temp_gprs = 4; |
| num_gs_gprs = 31; |
| num_es_gprs = 31; |
| num_hs_gprs = 23; |
| num_ls_gprs = 23; |
| num_ps_threads = 96; |
| num_vs_threads = 16; |
| num_gs_threads = 16; |
| num_es_threads = 16; |
| num_hs_threads = 16; |
| num_ls_threads = 16; |
| num_ps_stack_entries = 42; |
| num_vs_stack_entries = 42; |
| num_gs_stack_entries = 42; |
| num_es_stack_entries = 42; |
| num_hs_stack_entries = 42; |
| num_ls_stack_entries = 42; |
| break; |
| case CHIP_REDWOOD: |
| num_ps_gprs = 93; |
| num_vs_gprs = 46; |
| num_temp_gprs = 4; |
| num_gs_gprs = 31; |
| num_es_gprs = 31; |
| num_hs_gprs = 23; |
| num_ls_gprs = 23; |
| num_ps_threads = 128; |
| num_vs_threads = 20; |
| num_gs_threads = 20; |
| num_es_threads = 20; |
| num_hs_threads = 20; |
| num_ls_threads = 20; |
| num_ps_stack_entries = 42; |
| num_vs_stack_entries = 42; |
| num_gs_stack_entries = 42; |
| num_es_stack_entries = 42; |
| num_hs_stack_entries = 42; |
| num_ls_stack_entries = 42; |
| break; |
| case CHIP_JUNIPER: |
| num_ps_gprs = 93; |
| num_vs_gprs = 46; |
| num_temp_gprs = 4; |
| num_gs_gprs = 31; |
| num_es_gprs = 31; |
| num_hs_gprs = 23; |
| num_ls_gprs = 23; |
| num_ps_threads = 128; |
| num_vs_threads = 20; |
| num_gs_threads = 20; |
| num_es_threads = 20; |
| num_hs_threads = 20; |
| num_ls_threads = 20; |
| num_ps_stack_entries = 85; |
| num_vs_stack_entries = 85; |
| num_gs_stack_entries = 85; |
| num_es_stack_entries = 85; |
| num_hs_stack_entries = 85; |
| num_ls_stack_entries = 85; |
| break; |
| case CHIP_CYPRESS: |
| case CHIP_HEMLOCK: |
| num_ps_gprs = 93; |
| num_vs_gprs = 46; |
| num_temp_gprs = 4; |
| num_gs_gprs = 31; |
| num_es_gprs = 31; |
| num_hs_gprs = 23; |
| num_ls_gprs = 23; |
| num_ps_threads = 128; |
| num_vs_threads = 20; |
| num_gs_threads = 20; |
| num_es_threads = 20; |
| num_hs_threads = 20; |
| num_ls_threads = 20; |
| num_ps_stack_entries = 85; |
| num_vs_stack_entries = 85; |
| num_gs_stack_entries = 85; |
| num_es_stack_entries = 85; |
| num_hs_stack_entries = 85; |
| num_ls_stack_entries = 85; |
| break; |
| case CHIP_PALM: |
| num_ps_gprs = 93; |
| num_vs_gprs = 46; |
| num_temp_gprs = 4; |
| num_gs_gprs = 31; |
| num_es_gprs = 31; |
| num_hs_gprs = 23; |
| num_ls_gprs = 23; |
| num_ps_threads = 96; |
| num_vs_threads = 16; |
| num_gs_threads = 16; |
| num_es_threads = 16; |
| num_hs_threads = 16; |
| num_ls_threads = 16; |
| num_ps_stack_entries = 42; |
| num_vs_stack_entries = 42; |
| num_gs_stack_entries = 42; |
| num_es_stack_entries = 42; |
| num_hs_stack_entries = 42; |
| num_ls_stack_entries = 42; |
| break; |
| case CHIP_SUMO: |
| num_ps_gprs = 93; |
| num_vs_gprs = 46; |
| num_temp_gprs = 4; |
| num_gs_gprs = 31; |
| num_es_gprs = 31; |
| num_hs_gprs = 23; |
| num_ls_gprs = 23; |
| num_ps_threads = 96; |
| num_vs_threads = 25; |
| num_gs_threads = 25; |
| num_es_threads = 25; |
| num_hs_threads = 25; |
| num_ls_threads = 25; |
| num_ps_stack_entries = 42; |
| num_vs_stack_entries = 42; |
| num_gs_stack_entries = 42; |
| num_es_stack_entries = 42; |
| num_hs_stack_entries = 42; |
| num_ls_stack_entries = 42; |
| break; |
| case CHIP_SUMO2: |
| num_ps_gprs = 93; |
| num_vs_gprs = 46; |
| num_temp_gprs = 4; |
| num_gs_gprs = 31; |
| num_es_gprs = 31; |
| num_hs_gprs = 23; |
| num_ls_gprs = 23; |
| num_ps_threads = 96; |
| num_vs_threads = 25; |
| num_gs_threads = 25; |
| num_es_threads = 25; |
| num_hs_threads = 25; |
| num_ls_threads = 25; |
| num_ps_stack_entries = 85; |
| num_vs_stack_entries = 85; |
| num_gs_stack_entries = 85; |
| num_es_stack_entries = 85; |
| num_hs_stack_entries = 85; |
| num_ls_stack_entries = 85; |
| break; |
| case CHIP_BARTS: |
| num_ps_gprs = 93; |
| num_vs_gprs = 46; |
| num_temp_gprs = 4; |
| num_gs_gprs = 31; |
| num_es_gprs = 31; |
| num_hs_gprs = 23; |
| num_ls_gprs = 23; |
| num_ps_threads = 128; |
| num_vs_threads = 20; |
| num_gs_threads = 20; |
| num_es_threads = 20; |
| num_hs_threads = 20; |
| num_ls_threads = 20; |
| num_ps_stack_entries = 85; |
| num_vs_stack_entries = 85; |
| num_gs_stack_entries = 85; |
| num_es_stack_entries = 85; |
| num_hs_stack_entries = 85; |
| num_ls_stack_entries = 85; |
| break; |
| case CHIP_TURKS: |
| num_ps_gprs = 93; |
| num_vs_gprs = 46; |
| num_temp_gprs = 4; |
| num_gs_gprs = 31; |
| num_es_gprs = 31; |
| num_hs_gprs = 23; |
| num_ls_gprs = 23; |
| num_ps_threads = 128; |
| num_vs_threads = 20; |
| num_gs_threads = 20; |
| num_es_threads = 20; |
| num_hs_threads = 20; |
| num_ls_threads = 20; |
| num_ps_stack_entries = 42; |
| num_vs_stack_entries = 42; |
| num_gs_stack_entries = 42; |
| num_es_stack_entries = 42; |
| num_hs_stack_entries = 42; |
| num_ls_stack_entries = 42; |
| break; |
| case CHIP_CAICOS: |
| num_ps_gprs = 93; |
| num_vs_gprs = 46; |
| num_temp_gprs = 4; |
| num_gs_gprs = 31; |
| num_es_gprs = 31; |
| num_hs_gprs = 23; |
| num_ls_gprs = 23; |
| num_ps_threads = 128; |
| num_vs_threads = 10; |
| num_gs_threads = 10; |
| num_es_threads = 10; |
| num_hs_threads = 10; |
| num_ls_threads = 10; |
| num_ps_stack_entries = 42; |
| num_vs_stack_entries = 42; |
| num_gs_stack_entries = 42; |
| num_es_stack_entries = 42; |
| num_hs_stack_entries = 42; |
| num_ls_stack_entries = 42; |
| break; |
| } |
| if ((rdev->family == CHIP_CEDAR) || |
| (rdev->family == CHIP_PALM) || |
| (rdev->family == CHIP_SUMO) || |
| (rdev->family == CHIP_SUMO2) || |
| (rdev->family == CHIP_CAICOS)) |
| sq_config = 0; |
| else |
| sq_config = VC_ENABLE; |
| sq_config |= (EXPORT_SRC_C | |
| CS_PRIO(0) | |
| LS_PRIO(0) | |
| HS_PRIO(0) | |
| PS_PRIO(0) | |
| VS_PRIO(1) | |
| GS_PRIO(2) | |
| ES_PRIO(3)); |
| sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(num_ps_gprs) | |
| NUM_VS_GPRS(num_vs_gprs) | |
| NUM_CLAUSE_TEMP_GPRS(num_temp_gprs)); |
| sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(num_gs_gprs) | |
| NUM_ES_GPRS(num_es_gprs)); |
| sq_gpr_resource_mgmt_3 = (NUM_HS_GPRS(num_hs_gprs) | |
| NUM_LS_GPRS(num_ls_gprs)); |
| sq_thread_resource_mgmt = (NUM_PS_THREADS(num_ps_threads) | |
| NUM_VS_THREADS(num_vs_threads) | |
| NUM_GS_THREADS(num_gs_threads) | |
| NUM_ES_THREADS(num_es_threads)); |
| sq_thread_resource_mgmt_2 = (NUM_HS_THREADS(num_hs_threads) | |
| NUM_LS_THREADS(num_ls_threads)); |
| sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(num_ps_stack_entries) | |
| NUM_VS_STACK_ENTRIES(num_vs_stack_entries)); |
| sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(num_gs_stack_entries) | |
| NUM_ES_STACK_ENTRIES(num_es_stack_entries)); |
| sq_stack_resource_mgmt_3 = (NUM_HS_STACK_ENTRIES(num_hs_stack_entries) | |
| NUM_LS_STACK_ENTRIES(num_ls_stack_entries)); |
| /* disable dyn gprs */ |
| radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
| radeon_ring_write(rdev, (SQ_DYN_GPR_CNTL_PS_FLUSH_REQ - PACKET3_SET_CONFIG_REG_START) >> 2); |
| radeon_ring_write(rdev, 0); |
| /* setup LDS */ |
| radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
| radeon_ring_write(rdev, (SQ_LDS_RESOURCE_MGMT - PACKET3_SET_CONFIG_REG_START) >> 2); |
| radeon_ring_write(rdev, 0x10001000); |
| /* SQ config */ |
| radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 11)); |
| radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_START) >> 2); |
| radeon_ring_write(rdev, sq_config); |
| radeon_ring_write(rdev, sq_gpr_resource_mgmt_1); |
| radeon_ring_write(rdev, sq_gpr_resource_mgmt_2); |
| radeon_ring_write(rdev, sq_gpr_resource_mgmt_3); |
| radeon_ring_write(rdev, 0); |
| radeon_ring_write(rdev, 0); |
| radeon_ring_write(rdev, sq_thread_resource_mgmt); |
| radeon_ring_write(rdev, sq_thread_resource_mgmt_2); |
| radeon_ring_write(rdev, sq_stack_resource_mgmt_1); |
| radeon_ring_write(rdev, sq_stack_resource_mgmt_2); |
| radeon_ring_write(rdev, sq_stack_resource_mgmt_3); |
| } |
| /* CONTEXT_CONTROL */ |
| radeon_ring_write(rdev, 0xc0012800); |
| radeon_ring_write(rdev, 0x80000000); |
| radeon_ring_write(rdev, 0x80000000); |
| /* SQ_VTX_BASE_VTX_LOC */ |
| radeon_ring_write(rdev, 0xc0026f00); |
| radeon_ring_write(rdev, 0x00000000); |
| radeon_ring_write(rdev, 0x00000000); |
| radeon_ring_write(rdev, 0x00000000); |
| /* SET_SAMPLER */ |
| radeon_ring_write(rdev, 0xc0036e00); |
| radeon_ring_write(rdev, 0x00000000); |
| radeon_ring_write(rdev, 0x00000012); |
| radeon_ring_write(rdev, 0x00000000); |
| radeon_ring_write(rdev, 0x00000000); |
| /* set to DX10/11 mode */ |
| radeon_ring_write(rdev, PACKET3(PACKET3_MODE_CONTROL, 0)); |
| radeon_ring_write(rdev, 1); |
| /* emit an IB pointing at default state */ |
| dwords = ALIGN(rdev->r600_blit.state_len, 0x10); |
| gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset; |
| radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); |
| radeon_ring_write(rdev, gpu_addr & 0xFFFFFFFC); |
| radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF); |
| radeon_ring_write(rdev, dwords); |
| } |
| static inline uint32_t i2f(uint32_t input) |
| { |
| u32 result, i, exponent, fraction; |
| if ((input & 0x3fff) == 0) |
| result = 0; /* 0 is a special case */ |
| else { |
| exponent = 140; /* exponent biased by 127; */ |
| fraction = (input & 0x3fff) << 10; /* cheat and only |
| handle numbers below 2^^15 */ |
| for (i = 0; i < 14; i++) { |
| if (fraction & 0x800000) |
| break; |
| else { |
| fraction = fraction << 1; /* keep |
| shifting left until top bit = 1 */ |
| exponent = exponent - 1; |
| } |
| } |
| result = exponent << 23 | (fraction & 0x7fffff); /* mask |
| off top bit; assumed 1 */ |
| } |
| return result; |
| } |
| int evergreen_blit_init(struct radeon_device *rdev) |
| { |
| u32 obj_size; |
| int i, r, dwords; |
| void *ptr; |
| u32 packet2s[16]; |
| int num_packet2s = 0; |
| /* pin copy shader into vram if already initialized */ |
| if (rdev->r600_blit.shader_obj) |
| goto done; |
| mutex_init(&rdev->r600_blit.mutex); |
| rdev->r600_blit.state_offset = 0; |
| if (rdev->family < CHIP_CAYMAN) |
| rdev->r600_blit.state_len = evergreen_default_size; |
| else |
| rdev->r600_blit.state_len = cayman_default_size; |
| dwords = rdev->r600_blit.state_len; |
| while (dwords & 0xf) { |
| packet2s[num_packet2s++] = cpu_to_le32(PACKET2(0)); |
| dwords++; |
| } |
| obj_size = dwords * 4; |
| obj_size = ALIGN(obj_size, 256); |
| rdev->r600_blit.vs_offset = obj_size; |
| if (rdev->family < CHIP_CAYMAN) |
| obj_size += evergreen_vs_size * 4; |
| else |
| obj_size += cayman_vs_size * 4; |
| obj_size = ALIGN(obj_size, 256); |
| rdev->r600_blit.ps_offset = obj_size; |
| if (rdev->family < CHIP_CAYMAN) |
| obj_size += evergreen_ps_size * 4; |
| else |
| obj_size += cayman_ps_size * 4; |
| obj_size = ALIGN(obj_size, 256); |
| r = radeon_bo_create(rdev, obj_size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM, |
| &rdev->r600_blit.shader_obj); |
| if (r) { |
| DRM_ERROR("evergreen failed to allocate shader\n"); |
| return r; |
| } |
| DRM_DEBUG("evergreen blit allocated bo %08x vs %08x ps %08x\n", |
| obj_size, |
| rdev->r600_blit.vs_offset, rdev->r600_blit.ps_offset); |
| r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); |
| if (unlikely(r != 0)) |
| return r; |
| r = radeon_bo_kmap(rdev->r600_blit.shader_obj, &ptr); |
| if (r) { |
| DRM_ERROR("failed to map blit object %d\n", r); |
| return r; |
| } |
| if (rdev->family < CHIP_CAYMAN) { |
| memcpy(ptr + rdev->r600_blit.state_offset, |
| evergreen_default_state, rdev->r600_blit.state_len * 4); |
| if (num_packet2s) |
| memcpy(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4), |
| packet2s, num_packet2s * 4); |
| for (i = 0; i < evergreen_vs_size; i++) |
| *(u32 *)((unsigned long)ptr + rdev->r600_blit.vs_offset + i * 4) = cpu_to_le32(evergreen_vs[i]); |
| for (i = 0; i < evergreen_ps_size; i++) |
| *(u32 *)((unsigned long)ptr + rdev->r600_blit.ps_offset + i * 4) = cpu_to_le32(evergreen_ps[i]); |
| } else { |
| memcpy(ptr + rdev->r600_blit.state_offset, |
| cayman_default_state, rdev->r600_blit.state_len * 4); |
| if (num_packet2s) |
| memcpy(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4), |
| packet2s, num_packet2s * 4); |
| for (i = 0; i < cayman_vs_size; i++) |
| *(u32 *)((unsigned long)ptr + rdev->r600_blit.vs_offset + i * 4) = cpu_to_le32(cayman_vs[i]); |
| for (i = 0; i < cayman_ps_size; i++) |
| *(u32 *)((unsigned long)ptr + rdev->r600_blit.ps_offset + i * 4) = cpu_to_le32(cayman_ps[i]); |
| } |
| radeon_bo_kunmap(rdev->r600_blit.shader_obj); |
| radeon_bo_unreserve(rdev->r600_blit.shader_obj); |
| done: |
| r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); |
| if (unlikely(r != 0)) |
| return r; |
| r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM, |
| &rdev->r600_blit.shader_gpu_addr); |
| radeon_bo_unreserve(rdev->r600_blit.shader_obj); |
| if (r) { |
| dev_err(rdev->dev, "(%d) pin blit object failed\n", r); |
| return r; |
| } |
| // radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); |
| return 0; |
| } |
| void evergreen_blit_fini(struct radeon_device *rdev) |
| { |
| int r; |
| // radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); |
| if (rdev->r600_blit.shader_obj == NULL) |
| return; |
| /* If we can't reserve the bo, unref should be enough to destroy |
| * it when it becomes idle. |
| */ |
| r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); |
| if (!r) { |
| radeon_bo_unpin(rdev->r600_blit.shader_obj); |
| radeon_bo_unreserve(rdev->r600_blit.shader_obj); |
| } |
| radeon_bo_unref(&rdev->r600_blit.shader_obj); |
| } |
| static int evergreen_vb_ib_get(struct radeon_device *rdev) |
| { |
| int r; |
| r = radeon_ib_get(rdev, &rdev->r600_blit.vb_ib); |
| if (r) { |
| DRM_ERROR("failed to get IB for vertex buffer\n"); |
| return r; |
| } |
| rdev->r600_blit.vb_total = 64*1024; |
| rdev->r600_blit.vb_used = 0; |
| return 0; |
| } |
| static void evergreen_vb_ib_put(struct radeon_device *rdev) |
| { |
| radeon_fence_emit(rdev, rdev->r600_blit.vb_ib->fence); |
| radeon_ib_free(rdev, &rdev->r600_blit.vb_ib); |
| } |
| int evergreen_blit_prepare_copy(struct radeon_device *rdev, int size_bytes) |
| { |
| int r; |
| int ring_size, line_size; |
| int max_size; |
| /* loops of emits + fence emit possible */ |
| int dwords_per_loop = 74, num_loops; |
| r = evergreen_vb_ib_get(rdev); |
| if (r) |
| return r; |
| /* 8 bpp vs 32 bpp for xfer unit */ |
| if (size_bytes & 3) |
| line_size = 8192; |
| else |
| line_size = 8192 * 4; |
| max_size = 8192 * line_size; |
| /* major loops cover the max size transfer */ |
| num_loops = ((size_bytes + max_size) / max_size); |
| /* minor loops cover the extra non aligned bits */ |
| num_loops += ((size_bytes % line_size) ? 1 : 0); |
| /* calculate number of loops correctly */ |
| ring_size = num_loops * dwords_per_loop; |
| /* set default + shaders */ |
| ring_size += 55; /* shaders + def state */ |
| ring_size += 10; /* fence emit for VB IB */ |
| ring_size += 5; /* done copy */ |
| ring_size += 10; /* fence emit for done copy */ |
| r = radeon_ring_lock(rdev, ring_size); |
| if (r) |
| return r; |
| set_default_state(rdev); /* 36 */ |
| set_shaders(rdev); /* 16 */ |
| return 0; |
| } |
| void evergreen_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence) |
| { |
| int r; |
| if (rdev->r600_blit.vb_ib) |
| evergreen_vb_ib_put(rdev); |
| if (fence) |
| r = radeon_fence_emit(rdev, fence); |
| radeon_ring_unlock_commit(rdev); |
| } |
| void evergreen_kms_blit_copy(struct radeon_device *rdev, |
| u64 src_gpu_addr, u64 dst_gpu_addr, |
| int size_bytes) |
| { |
| int max_bytes; |
| u64 vb_gpu_addr; |
| u32 *vb; |
| DRM_DEBUG("emitting copy %16llx %16llx %d %d\n", src_gpu_addr, dst_gpu_addr, |
| size_bytes, rdev->r600_blit.vb_used); |
| vb = (u32 *)(rdev->r600_blit.vb_ib->ptr + rdev->r600_blit.vb_used); |
| if ((size_bytes & 3) || (src_gpu_addr & 3) || (dst_gpu_addr & 3)) { |
| max_bytes = 8192; |
| while (size_bytes) { |
| int cur_size = size_bytes; |
| int src_x = src_gpu_addr & 255; |
| int dst_x = dst_gpu_addr & 255; |
| int h = 1; |
| src_gpu_addr = src_gpu_addr & ~255ULL; |
| dst_gpu_addr = dst_gpu_addr & ~255ULL; |
| if (!src_x && !dst_x) { |
| h = (cur_size / max_bytes); |
| if (h > 8192) |
| h = 8192; |
| if (h == 0) |
| h = 1; |
| else |
| cur_size = max_bytes; |
| } else { |
| if (cur_size > max_bytes) |
| cur_size = max_bytes; |
| if (cur_size > (max_bytes - dst_x)) |
| cur_size = (max_bytes - dst_x); |
| if (cur_size > (max_bytes - src_x)) |
| cur_size = (max_bytes - src_x); |
| } |
| if ((rdev->r600_blit.vb_used + 48) > rdev->r600_blit.vb_total) { |
| // WARN_ON(1); |
| } |
| vb[0] = i2f(dst_x); |
| vb[1] = 0; |
| vb[2] = i2f(src_x); |
| vb[3] = 0; |
| vb[4] = i2f(dst_x); |
| vb[5] = i2f(h); |
| vb[6] = i2f(src_x); |
| vb[7] = i2f(h); |
| vb[8] = i2f(dst_x + cur_size); |
| vb[9] = i2f(h); |
| vb[10] = i2f(src_x + cur_size); |
| vb[11] = i2f(h); |
| /* src 10 */ |
| set_tex_resource(rdev, FMT_8, |
| src_x + cur_size, h, src_x + cur_size, |
| src_gpu_addr); |
| /* 5 */ |
| cp_set_surface_sync(rdev, |
| PACKET3_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr); |
| /* dst 17 */ |
| set_render_target(rdev, COLOR_8, |
| dst_x + cur_size, h, |
| dst_gpu_addr); |
| /* scissors 12 */ |
| set_scissors(rdev, dst_x, 0, dst_x + cur_size, h); |
| /* 15 */ |
| vb_gpu_addr = rdev->r600_blit.vb_ib->gpu_addr + rdev->r600_blit.vb_used; |
| set_vtx_resource(rdev, vb_gpu_addr); |
| /* draw 10 */ |
| draw_auto(rdev); |
| /* 5 */ |
| cp_set_surface_sync(rdev, |
| PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA, |
| cur_size * h, dst_gpu_addr); |
| vb += 12; |
| rdev->r600_blit.vb_used += 12 * 4; |
| src_gpu_addr += cur_size * h; |
| dst_gpu_addr += cur_size * h; |
| size_bytes -= cur_size * h; |
| } |
| } else { |
| max_bytes = 8192 * 4; |
| while (size_bytes) { |
| int cur_size = size_bytes; |
| int src_x = (src_gpu_addr & 255); |
| int dst_x = (dst_gpu_addr & 255); |
| int h = 1; |
| src_gpu_addr = src_gpu_addr & ~255ULL; |
| dst_gpu_addr = dst_gpu_addr & ~255ULL; |
| if (!src_x && !dst_x) { |
| h = (cur_size / max_bytes); |
| if (h > 8192) |
| h = 8192; |
| if (h == 0) |
| h = 1; |
| else |
| cur_size = max_bytes; |
| } else { |
| if (cur_size > max_bytes) |
| cur_size = max_bytes; |
| if (cur_size > (max_bytes - dst_x)) |
| cur_size = (max_bytes - dst_x); |
| if (cur_size > (max_bytes - src_x)) |
| cur_size = (max_bytes - src_x); |
| } |
| if ((rdev->r600_blit.vb_used + 48) > rdev->r600_blit.vb_total) { |
| // WARN_ON(1); |
| } |
| vb[0] = i2f(dst_x / 4); |
| vb[1] = 0; |
| vb[2] = i2f(src_x / 4); |
| vb[3] = 0; |
| vb[4] = i2f(dst_x / 4); |
| vb[5] = i2f(h); |
| vb[6] = i2f(src_x / 4); |
| vb[7] = i2f(h); |
| vb[8] = i2f((dst_x + cur_size) / 4); |
| vb[9] = i2f(h); |
| vb[10] = i2f((src_x + cur_size) / 4); |
| vb[11] = i2f(h); |
| /* src 10 */ |
| set_tex_resource(rdev, FMT_8_8_8_8, |
| (src_x + cur_size) / 4, |
| h, (src_x + cur_size) / 4, |
| src_gpu_addr); |
| /* 5 */ |
| cp_set_surface_sync(rdev, |
| PACKET3_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr); |
| /* dst 17 */ |
| set_render_target(rdev, COLOR_8_8_8_8, |
| (dst_x + cur_size) / 4, h, |
| dst_gpu_addr); |
| /* scissors 12 */ |
| set_scissors(rdev, (dst_x / 4), 0, (dst_x + cur_size / 4), h); |
| /* Vertex buffer setup 15 */ |
| vb_gpu_addr = rdev->r600_blit.vb_ib->gpu_addr + rdev->r600_blit.vb_used; |
| set_vtx_resource(rdev, vb_gpu_addr); |
| /* draw 10 */ |
| draw_auto(rdev); |
| /* 5 */ |
| cp_set_surface_sync(rdev, |
| PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA, |
| cur_size * h, dst_gpu_addr); |
| /* 74 ring dwords per loop */ |
| vb += 12; |
| rdev->r600_blit.vb_used += 12 * 4; |
| src_gpu_addr += cur_size * h; |
| dst_gpu_addr += cur_size * h; |
| size_bytes -= cur_size * h; |
| } |
| } |
| } |
| /drivers/video/drm/radeon/ni.c |
|---|
| 1376,10 → 1376,26 |
| return r; |
| cayman_gpu_init(rdev); |
| r = evergreen_blit_init(rdev); |
| if (r) { |
| // evergreen_blit_fini(rdev); |
| rdev->asic->copy = NULL; |
| dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); |
| } |
| /* allocate wb buffer */ |
| r = radeon_wb_init(rdev); |
| if (r) |
| return r; |
| /* Enable IRQ */ |
| r = r600_irq_init(rdev); |
| if (r) { |
| DRM_ERROR("radeon: IH init failed (%d).\n", r); |
| // radeon_irq_kms_fini(rdev); |
| return r; |
| } |
| evergreen_irq_set(rdev); |
| r = radeon_ring_init(rdev, rdev->cp.ring_size); |
| if (r) |
| 1442,6 → 1458,9 |
| /* Initialize clocks */ |
| radeon_get_clock_info(rdev->ddev); |
| /* Fence driver */ |
| r = radeon_fence_driver_init(rdev); |
| if (r) |
| return r; |
| /* initialize memory controller */ |
| r = evergreen_mc_init(rdev); |
| if (r) |
| 1451,10 → 1470,15 |
| if (r) |
| return r; |
| r = radeon_irq_kms_init(rdev); |
| if (r) |
| return r; |
| rdev->cp.ring_obj = NULL; |
| r600_ring_init(rdev, 1024 * 1024); |
| rdev->ih.ring_obj = NULL; |
| r600_ih_ring_init(rdev, 64 * 1024); |
| r = r600_pcie_gart_init(rdev); |
| if (r) |
| 1467,7 → 1491,17 |
| rdev->accel_working = false; |
| } |
| if (rdev->accel_working) { |
| r = radeon_ib_pool_init(rdev); |
| if (r) { |
| DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r); |
| rdev->accel_working = false; |
| } |
| r = r600_ib_test(rdev); |
| if (r) { |
| DRM_ERROR("radeon: failed testing IB (%d).\n", r); |
| rdev->accel_working = false; |
| } |
| } |
| /* Don't start up if the MC ucode is missing. |
| * The default clocks and voltages before the MC ucode |
| /drivers/video/drm/radeon/r100.c |
|---|
| 151,17 → 151,17 |
| struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
| switch (radeon_connector->hpd.hpd) { |
| case RADEON_HPD_1: |
| // rdev->irq.hpd[0] = true; |
| rdev->irq.hpd[0] = true; |
| break; |
| case RADEON_HPD_2: |
| // rdev->irq.hpd[1] = true; |
| rdev->irq.hpd[1] = true; |
| break; |
| default: |
| break; |
| } |
| } |
| // if (rdev->irq.installed) |
| // r100_irq_set(rdev); |
| if (rdev->irq.installed) |
| r100_irq_set(rdev); |
| } |
| void r100_hpd_fini(struct radeon_device *rdev) |
| 173,10 → 173,10 |
| struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
| switch (radeon_connector->hpd.hpd) { |
| case RADEON_HPD_1: |
| // rdev->irq.hpd[0] = false; |
| rdev->irq.hpd[0] = false; |
| break; |
| case RADEON_HPD_2: |
| // rdev->irq.hpd[1] = false; |
| rdev->irq.hpd[1] = false; |
| break; |
| default: |
| break; |
| 269,7 → 269,39 |
| radeon_gart_table_ram_free(rdev); |
| } |
| int r100_irq_set(struct radeon_device *rdev) |
| { |
| uint32_t tmp = 0; |
| if (!rdev->irq.installed) { |
| WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); |
| WREG32(R_000040_GEN_INT_CNTL, 0); |
| return -EINVAL; |
| } |
| if (rdev->irq.sw_int) { |
| tmp |= RADEON_SW_INT_ENABLE; |
| } |
| if (rdev->irq.gui_idle) { |
| tmp |= RADEON_GUI_IDLE_MASK; |
| } |
| if (rdev->irq.crtc_vblank_int[0] || |
| rdev->irq.pflip[0]) { |
| tmp |= RADEON_CRTC_VBLANK_MASK; |
| } |
| if (rdev->irq.crtc_vblank_int[1] || |
| rdev->irq.pflip[1]) { |
| tmp |= RADEON_CRTC2_VBLANK_MASK; |
| } |
| if (rdev->irq.hpd[0]) { |
| tmp |= RADEON_FP_DETECT_MASK; |
| } |
| if (rdev->irq.hpd[1]) { |
| tmp |= RADEON_FP2_DETECT_MASK; |
| } |
| WREG32(RADEON_GEN_INT_CNTL, tmp); |
| return 0; |
| } |
| void r100_irq_disable(struct radeon_device *rdev) |
| { |
| u32 tmp; |
| 281,7 → 313,6 |
| WREG32(R_000044_GEN_INT_STATUS, tmp); |
| } |
| #if 0 |
| static inline uint32_t r100_irq_ack(struct radeon_device *rdev) |
| { |
| uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS); |
| 301,9 → 332,83 |
| return irqs & irq_mask; |
| } |
| #endif |
| int r100_irq_process(struct radeon_device *rdev) |
| { |
| uint32_t status, msi_rearm; |
| bool queue_hotplug = false; |
| /* reset gui idle ack. the status bit is broken */ |
| rdev->irq.gui_idle_acked = false; |
| status = r100_irq_ack(rdev); |
| if (!status) { |
| return IRQ_NONE; |
| } |
| if (rdev->shutdown) { |
| return IRQ_NONE; |
| } |
| while (status) { |
| /* SW interrupt */ |
| if (status & RADEON_SW_INT_TEST) { |
| radeon_fence_process(rdev); |
| } |
| /* gui idle interrupt */ |
| if (status & RADEON_GUI_IDLE_STAT) { |
| rdev->irq.gui_idle_acked = true; |
| rdev->pm.gui_idle = true; |
| // wake_up(&rdev->irq.idle_queue); |
| } |
| /* Vertical blank interrupts */ |
| if (status & RADEON_CRTC_VBLANK_STAT) { |
| if (rdev->irq.crtc_vblank_int[0]) { |
| // drm_handle_vblank(rdev->ddev, 0); |
| rdev->pm.vblank_sync = true; |
| // wake_up(&rdev->irq.vblank_queue); |
| } |
| // if (rdev->irq.pflip[0]) |
| // radeon_crtc_handle_flip(rdev, 0); |
| } |
| if (status & RADEON_CRTC2_VBLANK_STAT) { |
| if (rdev->irq.crtc_vblank_int[1]) { |
| // drm_handle_vblank(rdev->ddev, 1); |
| rdev->pm.vblank_sync = true; |
| // wake_up(&rdev->irq.vblank_queue); |
| } |
| // if (rdev->irq.pflip[1]) |
| // radeon_crtc_handle_flip(rdev, 1); |
| } |
| if (status & RADEON_FP_DETECT_STAT) { |
| queue_hotplug = true; |
| DRM_DEBUG("HPD1\n"); |
| } |
| if (status & RADEON_FP2_DETECT_STAT) { |
| queue_hotplug = true; |
| DRM_DEBUG("HPD2\n"); |
| } |
| status = r100_irq_ack(rdev); |
| } |
| /* reset gui idle ack. the status bit is broken */ |
| rdev->irq.gui_idle_acked = false; |
| // if (queue_hotplug) |
| // schedule_work(&rdev->hotplug_work); |
| if (rdev->msi_enabled) { |
| switch (rdev->family) { |
| case CHIP_RS400: |
| case CHIP_RS480: |
| msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM; |
| WREG32(RADEON_AIC_CNTL, msi_rearm); |
| WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM); |
| break; |
| default: |
| msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN; |
| WREG32(RADEON_MSI_REARM_EN, msi_rearm); |
| WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN); |
| break; |
| } |
| } |
| return IRQ_HANDLED; |
| } |
| u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc) |
| { |
| if (crtc == 0) |
| 338,8 → 443,6 |
| radeon_ring_write(rdev, RADEON_SW_INT_FIRE); |
| } |
| #if 0 |
| int r100_copy_blit(struct radeon_device *rdev, |
| uint64_t src_offset, |
| uint64_t dst_offset, |
| 413,9 → 516,6 |
| return r; |
| } |
| #endif |
| static int r100_cp_wait_for_idle(struct radeon_device *rdev) |
| { |
| unsigned i; |
| 1617,7 → 1717,7 |
| void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp) |
| { |
| lockup->last_cp_rptr = cp->rptr; |
| lockup->last_jiffies = 0; //jiffies; |
| lockup->last_jiffies = GetTimerTicks(); |
| } |
| /** |
| 1645,18 → 1745,17 |
| { |
| unsigned long cjiffies, elapsed; |
| #if 0 |
| cjiffies = jiffies; |
| cjiffies = GetTimerTicks(); |
| if (!time_after(cjiffies, lockup->last_jiffies)) { |
| /* likely a wrap around */ |
| lockup->last_cp_rptr = cp->rptr; |
| lockup->last_jiffies = jiffies; |
| lockup->last_jiffies = GetTimerTicks(); |
| return false; |
| } |
| if (cp->rptr != lockup->last_cp_rptr) { |
| /* CP is still working no lockup */ |
| lockup->last_cp_rptr = cp->rptr; |
| lockup->last_jiffies = jiffies; |
| lockup->last_jiffies = GetTimerTicks(); |
| return false; |
| } |
| elapsed = jiffies_to_msecs(cjiffies - lockup->last_jiffies); |
| 1664,8 → 1763,6 |
| dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed); |
| return true; |
| } |
| #endif |
| /* give a chance to the GPU ... */ |
| return false; |
| } |
| 3195,8 → 3292,6 |
| return r; |
| } |
| #if 0 |
| void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) |
| { |
| radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1)); |
| 3283,7 → 3378,6 |
| } |
| return 0; |
| } |
| #endif |
| void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save) |
| { |
| 3436,8 → 3530,14 |
| if (r) |
| return r; |
| } |
| /* allocate wb buffer */ |
| r = radeon_wb_init(rdev); |
| if (r) |
| return r; |
| /* Enable IRQ */ |
| // r100_irq_set(rdev); |
| r100_irq_set(rdev); |
| rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
| /* 1M ring buffer */ |
| r = r100_cp_init(rdev, 1024 * 1024); |
| 3445,11 → 3545,11 |
| dev_err(rdev->dev, "failed initializing CP (%d).\n", r); |
| return r; |
| } |
| // r = r100_ib_init(rdev); |
| // if (r) { |
| // dev_err(rdev->dev, "failled initializing IB (%d).\n", r); |
| // return r; |
| // } |
| r = r100_ib_init(rdev); |
| if (r) { |
| dev_err(rdev->dev, "failed initializing IB (%d).\n", r); |
| return r; |
| } |
| return 0; |
| } |
| 3530,12 → 3630,12 |
| /* initialize VRAM */ |
| r100_mc_init(rdev); |
| /* Fence driver */ |
| // r = radeon_fence_driver_init(rdev); |
| // if (r) |
| // return r; |
| // r = radeon_irq_kms_init(rdev); |
| // if (r) |
| // return r; |
| r = radeon_fence_driver_init(rdev); |
| if (r) |
| return r; |
| r = radeon_irq_kms_init(rdev); |
| if (r) |
| return r; |
| /* Memory manager */ |
| r = radeon_bo_init(rdev); |
| if (r) |
| /drivers/video/drm/radeon/r200.c |
|---|
| 82,6 → 82,7 |
| vtx_size += 3; |
| return vtx_size; |
| } |
| #endif |
| int r200_copy_dma(struct radeon_device *rdev, |
| uint64_t src_offset, |
| 126,8 → 127,8 |
| radeon_ring_unlock_commit(rdev); |
| return r; |
| } |
| #if 0 |
| static int r200_get_vtx_size_1(uint32_t vtx_fmt_1) |
| { |
| int vtx_size, i, tex_size; |
| /drivers/video/drm/radeon/r300.c |
|---|
| 1395,9 → 1395,13 |
| return r; |
| } |
| /* allocate wb buffer */ |
| r = radeon_wb_init(rdev); |
| if (r) |
| return r; |
| /* Enable IRQ */ |
| // r100_irq_set(rdev); |
| r100_irq_set(rdev); |
| rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
| /* 1M ring buffer */ |
| r = r100_cp_init(rdev, 1024 * 1024); |
| 1405,11 → 1409,11 |
| dev_err(rdev->dev, "failed initializing CP (%d).\n", r); |
| return r; |
| } |
| // r = r100_ib_init(rdev); |
| // if (r) { |
| // dev_err(rdev->dev, "failled initializing IB (%d).\n", r); |
| // return r; |
| // } |
| r = r100_ib_init(rdev); |
| if (r) { |
| dev_err(rdev->dev, "failed initializing IB (%d).\n", r); |
| return r; |
| } |
| return 0; |
| } |
| 1467,12 → 1471,12 |
| /* initialize memory controller */ |
| r300_mc_init(rdev); |
| /* Fence driver */ |
| // r = radeon_fence_driver_init(rdev); |
| // if (r) |
| // return r; |
| // r = radeon_irq_kms_init(rdev); |
| // if (r) |
| // return r; |
| r = radeon_fence_driver_init(rdev); |
| if (r) |
| return r; |
| r = radeon_irq_kms_init(rdev); |
| if (r) |
| return r; |
| /* Memory manager */ |
| r = radeon_bo_init(rdev); |
| if (r) |
| /drivers/video/drm/radeon/r420.c |
|---|
| 209,7 → 209,14 |
| return r; |
| } |
| r420_pipes_init(rdev); |
| /* allocate wb buffer */ |
| r = radeon_wb_init(rdev); |
| if (r) |
| return r; |
| /* Enable IRQ */ |
| r100_irq_set(rdev); |
| rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
| /* 1M ring buffer */ |
| r = r100_cp_init(rdev, 1024 * 1024); |
| 218,6 → 225,11 |
| return r; |
| } |
| r420_cp_errata_init(rdev); |
| r = r100_ib_init(rdev); |
| if (r) { |
| dev_err(rdev->dev, "failed initializing IB (%d).\n", r); |
| return r; |
| } |
| return 0; |
| } |
| 302,7 → 314,14 |
| r300_mc_init(rdev); |
| r420_debugfs(rdev); |
| /* Fence driver */ |
| r = radeon_fence_driver_init(rdev); |
| if (r) { |
| return r; |
| } |
| r = radeon_irq_kms_init(rdev); |
| if (r) { |
| return r; |
| } |
| /* Memory manager */ |
| r = radeon_bo_init(rdev); |
| if (r) { |
| /drivers/video/drm/radeon/r520.c |
|---|
| 181,7 → 181,14 |
| if (r) |
| return r; |
| } |
| /* allocate wb buffer */ |
| r = radeon_wb_init(rdev); |
| if (r) |
| return r; |
| /* Enable IRQ */ |
| rs600_irq_set(rdev); |
| rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
| /* 1M ring buffer */ |
| r = r100_cp_init(rdev, 1024 * 1024); |
| 189,6 → 196,11 |
| dev_err(rdev->dev, "failed initializing CP (%d).\n", r); |
| return r; |
| } |
| r = r100_ib_init(rdev); |
| if (r) { |
| dev_err(rdev->dev, "failed initializing IB (%d).\n", r); |
| return r; |
| } |
| return 0; |
| } |
| 246,6 → 258,12 |
| r520_mc_init(rdev); |
| rv515_debugfs(rdev); |
| /* Fence driver */ |
| r = radeon_fence_driver_init(rdev); |
| if (r) |
| return r; |
| r = radeon_irq_kms_init(rdev); |
| if (r) |
| return r; |
| /* Memory manager */ |
| r = radeon_bo_init(rdev); |
| if (r) |
| /drivers/video/drm/radeon/r600.c |
|---|
| 1871,7 → 1871,27 |
| } |
| } |
| int r600_copy_blit(struct radeon_device *rdev, |
| uint64_t src_offset, uint64_t dst_offset, |
| unsigned num_pages, struct radeon_fence *fence) |
| { |
| int r; |
| mutex_lock(&rdev->r600_blit.mutex); |
| rdev->r600_blit.vb_ib = NULL; |
| r = r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE); |
| if (r) { |
| // if (rdev->r600_blit.vb_ib) |
| // radeon_ib_free(rdev, &rdev->r600_blit.vb_ib); |
| mutex_unlock(&rdev->r600_blit.mutex); |
| return r; |
| } |
| r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE); |
| r600_blit_done_copy(rdev, fence); |
| mutex_unlock(&rdev->r600_blit.mutex); |
| return 0; |
| } |
| int r600_set_surface_reg(struct radeon_device *rdev, int reg, |
| uint32_t tiling_flags, uint32_t pitch, |
| uint32_t offset, uint32_t obj_size) |
| 1909,7 → 1929,27 |
| return r; |
| } |
| r600_gpu_init(rdev); |
| r = r600_blit_init(rdev); |
| if (r) { |
| // r600_blit_fini(rdev); |
| rdev->asic->copy = NULL; |
| dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); |
| } |
| /* allocate wb buffer */ |
| r = radeon_wb_init(rdev); |
| if (r) |
| return r; |
| /* Enable IRQ */ |
| r = r600_irq_init(rdev); |
| if (r) { |
| DRM_ERROR("radeon: IH init failed (%d).\n", r); |
| // radeon_irq_kms_fini(rdev); |
| return r; |
| } |
| r600_irq_set(rdev); |
| r = radeon_ring_init(rdev, rdev->cp.ring_size); |
| if (r) |
| return r; |
| 2028,19 → 2068,19 |
| rdev->accel_working = false; |
| } |
| if (rdev->accel_working) { |
| // r = radeon_ib_pool_init(rdev); |
| // if (r) { |
| // DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r); |
| // rdev->accel_working = false; |
| // } |
| // r = r600_ib_test(rdev); |
| // if (r) { |
| // DRM_ERROR("radeon: failled testing IB (%d).\n", r); |
| // rdev->accel_working = false; |
| // } |
| r = radeon_ib_pool_init(rdev); |
| if (r) { |
| dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
| rdev->accel_working = false; |
| } else { |
| r = r600_ib_test(rdev); |
| if (r) { |
| dev_err(rdev->dev, "IB test failed (%d).\n", r); |
| rdev->accel_working = false; |
| } |
| if (r) |
| return r; /* TODO error handling */ |
| } |
| } |
| return 0; |
| } |
| 2423,8 → 2463,6 |
| u32 hdmi1, hdmi2; |
| u32 d1grph = 0, d2grph = 0; |
| ENTER(); |
| if (!rdev->irq.installed) { |
| WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); |
| return -EINVAL; |
| 2530,8 → 2568,6 |
| WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3); |
| } |
| LEAVE(); |
| return 0; |
| } |
| 2825,11 → 2861,11 |
| case 177: /* CP_INT in IB1 */ |
| case 178: /* CP_INT in IB2 */ |
| DRM_DEBUG("IH: CP int: 0x%08x\n", src_data); |
| // radeon_fence_process(rdev); |
| radeon_fence_process(rdev); |
| break; |
| case 181: /* CP EOP event */ |
| DRM_DEBUG("IH: CP EOP\n"); |
| // radeon_fence_process(rdev); |
| radeon_fence_process(rdev); |
| break; |
| case 233: /* GUI IDLE */ |
| DRM_DEBUG("IH: GUI idle\n"); |
| /drivers/video/drm/radeon/r600_audio.c |
|---|
| 26,6 → 26,7 |
| #include "drmP.h" |
| #include "radeon.h" |
| #include "radeon_reg.h" |
| #include "radeon_asic.h" |
| #include "atom.h" |
| #define AUDIO_TIMER_INTERVALL 100 /* 1/10 sekund should be enough */ |
| /drivers/video/drm/radeon/r600_blit_kms.c |
|---|
| 0,0 → 1,845 |
| /* |
| * Copyright 2009 Advanced Micro Devices, Inc. |
| * Copyright 2009 Red Hat Inc. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice (including the next |
| * paragraph) shall be included in all copies or substantial portions of the |
| * Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| * DEALINGS IN THE SOFTWARE. |
| * |
| */ |
| #include "drmP.h" |
| #include "drm.h" |
| #include "radeon_drm.h" |
| #include "radeon.h" |
| #include "r600d.h" |
| #include "r600_blit_shaders.h" |
| #define DI_PT_RECTLIST 0x11 |
| #define DI_INDEX_SIZE_16_BIT 0x0 |
| #define DI_SRC_SEL_AUTO_INDEX 0x2 |
| #define FMT_8 0x1 |
| #define FMT_5_6_5 0x8 |
| #define FMT_8_8_8_8 0x1a |
| #define COLOR_8 0x1 |
| #define COLOR_5_6_5 0x8 |
| #define COLOR_8_8_8_8 0x1a |
| /* emits 21 on rv770+, 23 on r600 */ |
| static void |
| set_render_target(struct radeon_device *rdev, int format, |
| int w, int h, u64 gpu_addr) |
| { |
| u32 cb_color_info; |
| int pitch, slice; |
| h = ALIGN(h, 8); |
| if (h < 8) |
| h = 8; |
| cb_color_info = ((format << 2) | (1 << 27) | (1 << 8)); |
| pitch = (w / 8) - 1; |
| slice = ((w * h) / 64) - 1; |
| radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
| radeon_ring_write(rdev, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
| radeon_ring_write(rdev, gpu_addr >> 8); |
| if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770) { |
| radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_BASE_UPDATE, 0)); |
| radeon_ring_write(rdev, 2 << 0); |
| } |
| radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
| radeon_ring_write(rdev, (CB_COLOR0_SIZE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
| radeon_ring_write(rdev, (pitch << 0) | (slice << 10)); |
| radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
| radeon_ring_write(rdev, (CB_COLOR0_VIEW - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
| radeon_ring_write(rdev, 0); |
| radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
| radeon_ring_write(rdev, (CB_COLOR0_INFO - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
| radeon_ring_write(rdev, cb_color_info); |
| radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
| radeon_ring_write(rdev, (CB_COLOR0_TILE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
| radeon_ring_write(rdev, 0); |
| radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
| radeon_ring_write(rdev, (CB_COLOR0_FRAG - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
| radeon_ring_write(rdev, 0); |
| radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
| radeon_ring_write(rdev, (CB_COLOR0_MASK - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
| radeon_ring_write(rdev, 0); |
| } |
| /* emits 5dw */ |
| static void |
| cp_set_surface_sync(struct radeon_device *rdev, |
| u32 sync_type, u32 size, |
| u64 mc_addr) |
| { |
| u32 cp_coher_size; |
| if (size == 0xffffffff) |
| cp_coher_size = 0xffffffff; |
| else |
| cp_coher_size = ((size + 255) >> 8); |
| radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3)); |
| radeon_ring_write(rdev, sync_type); |
| radeon_ring_write(rdev, cp_coher_size); |
| radeon_ring_write(rdev, mc_addr >> 8); |
| radeon_ring_write(rdev, 10); /* poll interval */ |
| } |
| /* emits 21dw + 1 surface sync = 26dw */ |
| static void |
| set_shaders(struct radeon_device *rdev) |
| { |
| u64 gpu_addr; |
| u32 sq_pgm_resources; |
| /* setup shader regs */ |
| sq_pgm_resources = (1 << 0); |
| /* VS */ |
| gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset; |
| radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
| radeon_ring_write(rdev, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
| radeon_ring_write(rdev, gpu_addr >> 8); |
| radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
| radeon_ring_write(rdev, (SQ_PGM_RESOURCES_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
| radeon_ring_write(rdev, sq_pgm_resources); |
| radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
| radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
| radeon_ring_write(rdev, 0); |
| /* PS */ |
| gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset; |
| radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
| radeon_ring_write(rdev, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
| radeon_ring_write(rdev, gpu_addr >> 8); |
| radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
| radeon_ring_write(rdev, (SQ_PGM_RESOURCES_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
| radeon_ring_write(rdev, sq_pgm_resources | (1 << 28)); |
| radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
| radeon_ring_write(rdev, (SQ_PGM_EXPORTS_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
| radeon_ring_write(rdev, 2); |
| radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); |
| radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
| radeon_ring_write(rdev, 0); |
| gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset; |
| cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr); |
| } |
| /* emits 9 + 1 sync (5) = 14*/ |
| static void |
| set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr) |
| { |
| u32 sq_vtx_constant_word2; |
| sq_vtx_constant_word2 = ((upper_32_bits(gpu_addr) & 0xff) | (16 << 8)); |
| #ifdef __BIG_ENDIAN |
| sq_vtx_constant_word2 |= (2 << 30); |
| #endif |
| radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 7)); |
| radeon_ring_write(rdev, 0x460); |
| radeon_ring_write(rdev, gpu_addr & 0xffffffff); |
| radeon_ring_write(rdev, 48 - 1); |
| radeon_ring_write(rdev, sq_vtx_constant_word2); |
| radeon_ring_write(rdev, 1 << 0); |
| radeon_ring_write(rdev, 0); |
| radeon_ring_write(rdev, 0); |
| radeon_ring_write(rdev, SQ_TEX_VTX_VALID_BUFFER << 30); |
| if ((rdev->family == CHIP_RV610) || |
| (rdev->family == CHIP_RV620) || |
| (rdev->family == CHIP_RS780) || |
| (rdev->family == CHIP_RS880) || |
| (rdev->family == CHIP_RV710)) |
| cp_set_surface_sync(rdev, |
| PACKET3_TC_ACTION_ENA, 48, gpu_addr); |
| else |
| cp_set_surface_sync(rdev, |
| PACKET3_VC_ACTION_ENA, 48, gpu_addr); |
| } |
| /* emits 9 */ |
| static void |
| set_tex_resource(struct radeon_device *rdev, |
| int format, int w, int h, int pitch, |
| u64 gpu_addr) |
| { |
| uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4; |
| if (h < 1) |
| h = 1; |
| sq_tex_resource_word0 = (1 << 0) | (1 << 3); |
| sq_tex_resource_word0 |= ((((pitch >> 3) - 1) << 8) | |
| ((w - 1) << 19)); |
| sq_tex_resource_word1 = (format << 26); |
| sq_tex_resource_word1 |= ((h - 1) << 0); |
| sq_tex_resource_word4 = ((1 << 14) | |
| (0 << 16) | |
| (1 << 19) | |
| (2 << 22) | |
| (3 << 25)); |
| radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 7)); |
| radeon_ring_write(rdev, 0); |
| radeon_ring_write(rdev, sq_tex_resource_word0); |
| radeon_ring_write(rdev, sq_tex_resource_word1); |
| radeon_ring_write(rdev, gpu_addr >> 8); |
| radeon_ring_write(rdev, gpu_addr >> 8); |
| radeon_ring_write(rdev, sq_tex_resource_word4); |
| radeon_ring_write(rdev, 0); |
| radeon_ring_write(rdev, SQ_TEX_VTX_VALID_TEXTURE << 30); |
| } |
| /* emits 12 */ |
| static void |
| set_scissors(struct radeon_device *rdev, int x1, int y1, |
| int x2, int y2) |
| { |
| radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); |
| radeon_ring_write(rdev, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
| radeon_ring_write(rdev, (x1 << 0) | (y1 << 16)); |
| radeon_ring_write(rdev, (x2 << 0) | (y2 << 16)); |
| radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); |
| radeon_ring_write(rdev, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
| radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31)); |
| radeon_ring_write(rdev, (x2 << 0) | (y2 << 16)); |
| radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); |
| radeon_ring_write(rdev, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); |
| radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31)); |
| radeon_ring_write(rdev, (x2 << 0) | (y2 << 16)); |
| } |
| /* emits 10 */ |
| static void |
| draw_auto(struct radeon_device *rdev) |
| { |
| radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
| radeon_ring_write(rdev, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); |
| radeon_ring_write(rdev, DI_PT_RECTLIST); |
| radeon_ring_write(rdev, PACKET3(PACKET3_INDEX_TYPE, 0)); |
| radeon_ring_write(rdev, |
| #ifdef __BIG_ENDIAN |
| (2 << 2) | |
| #endif |
| DI_INDEX_SIZE_16_BIT); |
| radeon_ring_write(rdev, PACKET3(PACKET3_NUM_INSTANCES, 0)); |
| radeon_ring_write(rdev, 1); |
| radeon_ring_write(rdev, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1)); |
| radeon_ring_write(rdev, 3); |
| radeon_ring_write(rdev, DI_SRC_SEL_AUTO_INDEX); |
| } |
| /* emits 14 */ |
| static void |
| set_default_state(struct radeon_device *rdev) |
| { |
| u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2; |
| u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2; |
| int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs; |
| int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads; |
| int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries; |
| u64 gpu_addr; |
| int dwords; |
| switch (rdev->family) { |
| case CHIP_R600: |
| num_ps_gprs = 192; |
| num_vs_gprs = 56; |
| num_temp_gprs = 4; |
| num_gs_gprs = 0; |
| num_es_gprs = 0; |
| num_ps_threads = 136; |
| num_vs_threads = 48; |
| num_gs_threads = 4; |
| num_es_threads = 4; |
| num_ps_stack_entries = 128; |
| num_vs_stack_entries = 128; |
| num_gs_stack_entries = 0; |
| num_es_stack_entries = 0; |
| break; |
| case CHIP_RV630: |
| case CHIP_RV635: |
| num_ps_gprs = 84; |
| num_vs_gprs = 36; |
| num_temp_gprs = 4; |
| num_gs_gprs = 0; |
| num_es_gprs = 0; |
| num_ps_threads = 144; |
| num_vs_threads = 40; |
| num_gs_threads = 4; |
| num_es_threads = 4; |
| num_ps_stack_entries = 40; |
| num_vs_stack_entries = 40; |
| num_gs_stack_entries = 32; |
| num_es_stack_entries = 16; |
| break; |
| case CHIP_RV610: |
| case CHIP_RV620: |
| case CHIP_RS780: |
| case CHIP_RS880: |
| default: |
| num_ps_gprs = 84; |
| num_vs_gprs = 36; |
| num_temp_gprs = 4; |
| num_gs_gprs = 0; |
| num_es_gprs = 0; |
| num_ps_threads = 136; |
| num_vs_threads = 48; |
| num_gs_threads = 4; |
| num_es_threads = 4; |
| num_ps_stack_entries = 40; |
| num_vs_stack_entries = 40; |
| num_gs_stack_entries = 32; |
| num_es_stack_entries = 16; |
| break; |
| case CHIP_RV670: |
| num_ps_gprs = 144; |
| num_vs_gprs = 40; |
| num_temp_gprs = 4; |
| num_gs_gprs = 0; |
| num_es_gprs = 0; |
| num_ps_threads = 136; |
| num_vs_threads = 48; |
| num_gs_threads = 4; |
| num_es_threads = 4; |
| num_ps_stack_entries = 40; |
| num_vs_stack_entries = 40; |
| num_gs_stack_entries = 32; |
| num_es_stack_entries = 16; |
| break; |
| case CHIP_RV770: |
| num_ps_gprs = 192; |
| num_vs_gprs = 56; |
| num_temp_gprs = 4; |
| num_gs_gprs = 0; |
| num_es_gprs = 0; |
| num_ps_threads = 188; |
| num_vs_threads = 60; |
| num_gs_threads = 0; |
| num_es_threads = 0; |
| num_ps_stack_entries = 256; |
| num_vs_stack_entries = 256; |
| num_gs_stack_entries = 0; |
| num_es_stack_entries = 0; |
| break; |
| case CHIP_RV730: |
| case CHIP_RV740: |
| num_ps_gprs = 84; |
| num_vs_gprs = 36; |
| num_temp_gprs = 4; |
| num_gs_gprs = 0; |
| num_es_gprs = 0; |
| num_ps_threads = 188; |
| num_vs_threads = 60; |
| num_gs_threads = 0; |
| num_es_threads = 0; |
| num_ps_stack_entries = 128; |
| num_vs_stack_entries = 128; |
| num_gs_stack_entries = 0; |
| num_es_stack_entries = 0; |
| break; |
| case CHIP_RV710: |
| num_ps_gprs = 192; |
| num_vs_gprs = 56; |
| num_temp_gprs = 4; |
| num_gs_gprs = 0; |
| num_es_gprs = 0; |
| num_ps_threads = 144; |
| num_vs_threads = 48; |
| num_gs_threads = 0; |
| num_es_threads = 0; |
| num_ps_stack_entries = 128; |
| num_vs_stack_entries = 128; |
| num_gs_stack_entries = 0; |
| num_es_stack_entries = 0; |
| break; |
| } |
| if ((rdev->family == CHIP_RV610) || |
| (rdev->family == CHIP_RV620) || |
| (rdev->family == CHIP_RS780) || |
| (rdev->family == CHIP_RS880) || |
| (rdev->family == CHIP_RV710)) |
| sq_config = 0; |
| else |
| sq_config = VC_ENABLE; |
| sq_config |= (DX9_CONSTS | |
| ALU_INST_PREFER_VECTOR | |
| PS_PRIO(0) | |
| VS_PRIO(1) | |
| GS_PRIO(2) | |
| ES_PRIO(3)); |
| sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(num_ps_gprs) | |
| NUM_VS_GPRS(num_vs_gprs) | |
| NUM_CLAUSE_TEMP_GPRS(num_temp_gprs)); |
| sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(num_gs_gprs) | |
| NUM_ES_GPRS(num_es_gprs)); |
| sq_thread_resource_mgmt = (NUM_PS_THREADS(num_ps_threads) | |
| NUM_VS_THREADS(num_vs_threads) | |
| NUM_GS_THREADS(num_gs_threads) | |
| NUM_ES_THREADS(num_es_threads)); |
| sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(num_ps_stack_entries) | |
| NUM_VS_STACK_ENTRIES(num_vs_stack_entries)); |
| sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(num_gs_stack_entries) | |
| NUM_ES_STACK_ENTRIES(num_es_stack_entries)); |
| /* emit an IB pointing at default state */ |
| dwords = ALIGN(rdev->r600_blit.state_len, 0x10); |
| gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset; |
| radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); |
| radeon_ring_write(rdev, |
| #ifdef __BIG_ENDIAN |
| (2 << 0) | |
| #endif |
| (gpu_addr & 0xFFFFFFFC)); |
| radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF); |
| radeon_ring_write(rdev, dwords); |
| /* SQ config */ |
| radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 6)); |
| radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); |
| radeon_ring_write(rdev, sq_config); |
| radeon_ring_write(rdev, sq_gpr_resource_mgmt_1); |
| radeon_ring_write(rdev, sq_gpr_resource_mgmt_2); |
| radeon_ring_write(rdev, sq_thread_resource_mgmt); |
| radeon_ring_write(rdev, sq_stack_resource_mgmt_1); |
| radeon_ring_write(rdev, sq_stack_resource_mgmt_2); |
| } |
| static inline uint32_t i2f(uint32_t input) |
| { |
| u32 result, i, exponent, fraction; |
| if ((input & 0x3fff) == 0) |
| result = 0; /* 0 is a special case */ |
| else { |
| exponent = 140; /* exponent biased by 127; */ |
| fraction = (input & 0x3fff) << 10; /* cheat and only |
| handle numbers below 2^^15 */ |
| for (i = 0; i < 14; i++) { |
| if (fraction & 0x800000) |
| break; |
| else { |
| fraction = fraction << 1; /* keep |
| shifting left until top bit = 1 */ |
| exponent = exponent - 1; |
| } |
| } |
| result = exponent << 23 | (fraction & 0x7fffff); /* mask |
| off top bit; assumed 1 */ |
| } |
| return result; |
| } |
| int r600_blit_init(struct radeon_device *rdev) |
| { |
| u32 obj_size; |
| int i, r, dwords; |
| void *ptr; |
| u32 packet2s[16]; |
| int num_packet2s = 0; |
| ENTER(); |
| /* pin copy shader into vram if already initialized */ |
| if (rdev->r600_blit.shader_obj) |
| goto done; |
| mutex_init(&rdev->r600_blit.mutex); |
| rdev->r600_blit.state_offset = 0; |
| if (rdev->family >= CHIP_RV770) |
| rdev->r600_blit.state_len = r7xx_default_size; |
| else |
| rdev->r600_blit.state_len = r6xx_default_size; |
| dwords = rdev->r600_blit.state_len; |
| while (dwords & 0xf) { |
| packet2s[num_packet2s++] = cpu_to_le32(PACKET2(0)); |
| dwords++; |
| } |
| obj_size = dwords * 4; |
| obj_size = ALIGN(obj_size, 256); |
| rdev->r600_blit.vs_offset = obj_size; |
| obj_size += r6xx_vs_size * 4; |
| obj_size = ALIGN(obj_size, 256); |
| rdev->r600_blit.ps_offset = obj_size; |
| obj_size += r6xx_ps_size * 4; |
| obj_size = ALIGN(obj_size, 256); |
| r = radeon_bo_create(rdev, obj_size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM, |
| &rdev->r600_blit.shader_obj); |
| if (r) { |
| DRM_ERROR("r600 failed to allocate shader\n"); |
| return r; |
| } |
| DRM_DEBUG("r6xx blit allocated bo %08x vs %08x ps %08x\n", |
| obj_size, |
| rdev->r600_blit.vs_offset, rdev->r600_blit.ps_offset); |
| r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); |
| if (unlikely(r != 0)) |
| return r; |
| r = radeon_bo_kmap(rdev->r600_blit.shader_obj, &ptr); |
| if (r) { |
| DRM_ERROR("failed to map blit object %d\n", r); |
| return r; |
| } |
| if (rdev->family >= CHIP_RV770) |
| memcpy(ptr + rdev->r600_blit.state_offset, |
| r7xx_default_state, rdev->r600_blit.state_len * 4); |
| else |
| memcpy(ptr + rdev->r600_blit.state_offset, |
| r6xx_default_state, rdev->r600_blit.state_len * 4); |
| if (num_packet2s) |
| memcpy(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4), |
| packet2s, num_packet2s * 4); |
| for (i = 0; i < r6xx_vs_size; i++) |
| *(u32 *)((unsigned long)ptr + rdev->r600_blit.vs_offset + i * 4) = cpu_to_le32(r6xx_vs[i]); |
| for (i = 0; i < r6xx_ps_size; i++) |
| *(u32 *)((unsigned long)ptr + rdev->r600_blit.ps_offset + i * 4) = cpu_to_le32(r6xx_ps[i]); |
| radeon_bo_kunmap(rdev->r600_blit.shader_obj); |
| radeon_bo_unreserve(rdev->r600_blit.shader_obj); |
| done: |
| r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); |
| if (unlikely(r != 0)) |
| return r; |
| r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM, |
| &rdev->r600_blit.shader_gpu_addr); |
| radeon_bo_unreserve(rdev->r600_blit.shader_obj); |
| if (r) { |
| dev_err(rdev->dev, "(%d) pin blit object failed\n", r); |
| return r; |
| } |
| // radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); |
| LEAVE(); |
| return 0; |
| } |
| void r600_blit_fini(struct radeon_device *rdev) |
| { |
| int r; |
| // radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); |
| if (rdev->r600_blit.shader_obj == NULL) |
| return; |
| /* If we can't reserve the bo, unref should be enough to destroy |
| * it when it becomes idle. |
| */ |
| r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); |
| if (!r) { |
| radeon_bo_unpin(rdev->r600_blit.shader_obj); |
| radeon_bo_unreserve(rdev->r600_blit.shader_obj); |
| } |
| radeon_bo_unref(&rdev->r600_blit.shader_obj); |
| } |
| static int r600_vb_ib_get(struct radeon_device *rdev) |
| { |
| int r; |
| r = radeon_ib_get(rdev, &rdev->r600_blit.vb_ib); |
| if (r) { |
| DRM_ERROR("failed to get IB for vertex buffer\n"); |
| return r; |
| } |
| rdev->r600_blit.vb_total = 64*1024; |
| rdev->r600_blit.vb_used = 0; |
| return 0; |
| } |
| static void r600_vb_ib_put(struct radeon_device *rdev) |
| { |
| radeon_fence_emit(rdev, rdev->r600_blit.vb_ib->fence); |
| radeon_ib_free(rdev, &rdev->r600_blit.vb_ib); |
| } |
| int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes) |
| { |
| int r; |
| int ring_size, line_size; |
| int max_size; |
| /* loops of emits 64 + fence emit possible */ |
| int dwords_per_loop = 76, num_loops; |
| r = r600_vb_ib_get(rdev); |
| if (r) |
| return r; |
| /* set_render_target emits 2 extra dwords on rv6xx */ |
| if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770) |
| dwords_per_loop += 2; |
| /* 8 bpp vs 32 bpp for xfer unit */ |
| if (size_bytes & 3) |
| line_size = 8192; |
| else |
| line_size = 8192*4; |
| max_size = 8192 * line_size; |
| /* major loops cover the max size transfer */ |
| num_loops = ((size_bytes + max_size) / max_size); |
| /* minor loops cover the extra non aligned bits */ |
| num_loops += ((size_bytes % line_size) ? 1 : 0); |
| /* calculate number of loops correctly */ |
| ring_size = num_loops * dwords_per_loop; |
| /* set default + shaders */ |
| ring_size += 40; /* shaders + def state */ |
| ring_size += 10; /* fence emit for VB IB */ |
| ring_size += 5; /* done copy */ |
| ring_size += 10; /* fence emit for done copy */ |
| r = radeon_ring_lock(rdev, ring_size); |
| if (r) |
| return r; |
| set_default_state(rdev); /* 14 */ |
| set_shaders(rdev); /* 26 */ |
| return 0; |
| } |
| void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence) |
| { |
| int r; |
| if (rdev->r600_blit.vb_ib) |
| r600_vb_ib_put(rdev); |
| if (fence) |
| r = radeon_fence_emit(rdev, fence); |
| radeon_ring_unlock_commit(rdev); |
| } |
| void r600_kms_blit_copy(struct radeon_device *rdev, |
| u64 src_gpu_addr, u64 dst_gpu_addr, |
| int size_bytes) |
| { |
| int max_bytes; |
| u64 vb_gpu_addr; |
| u32 *vb; |
| DRM_DEBUG("emitting copy %16llx %16llx %d %d\n", src_gpu_addr, dst_gpu_addr, |
| size_bytes, rdev->r600_blit.vb_used); |
| vb = (u32 *)(rdev->r600_blit.vb_ib->ptr + rdev->r600_blit.vb_used); |
| if ((size_bytes & 3) || (src_gpu_addr & 3) || (dst_gpu_addr & 3)) { |
| max_bytes = 8192; |
| while (size_bytes) { |
| int cur_size = size_bytes; |
| int src_x = src_gpu_addr & 255; |
| int dst_x = dst_gpu_addr & 255; |
| int h = 1; |
| src_gpu_addr = src_gpu_addr & ~255ULL; |
| dst_gpu_addr = dst_gpu_addr & ~255ULL; |
| if (!src_x && !dst_x) { |
| h = (cur_size / max_bytes); |
| if (h > 8192) |
| h = 8192; |
| if (h == 0) |
| h = 1; |
| else |
| cur_size = max_bytes; |
| } else { |
| if (cur_size > max_bytes) |
| cur_size = max_bytes; |
| if (cur_size > (max_bytes - dst_x)) |
| cur_size = (max_bytes - dst_x); |
| if (cur_size > (max_bytes - src_x)) |
| cur_size = (max_bytes - src_x); |
| } |
| if ((rdev->r600_blit.vb_used + 48) > rdev->r600_blit.vb_total) { |
| // WARN_ON(1); |
| } |
| vb[0] = i2f(dst_x); |
| vb[1] = 0; |
| vb[2] = i2f(src_x); |
| vb[3] = 0; |
| vb[4] = i2f(dst_x); |
| vb[5] = i2f(h); |
| vb[6] = i2f(src_x); |
| vb[7] = i2f(h); |
| vb[8] = i2f(dst_x + cur_size); |
| vb[9] = i2f(h); |
| vb[10] = i2f(src_x + cur_size); |
| vb[11] = i2f(h); |
| /* src 9 */ |
| set_tex_resource(rdev, FMT_8, |
| src_x + cur_size, h, src_x + cur_size, |
| src_gpu_addr); |
| /* 5 */ |
| cp_set_surface_sync(rdev, |
| PACKET3_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr); |
| /* dst 23 */ |
| set_render_target(rdev, COLOR_8, |
| dst_x + cur_size, h, |
| dst_gpu_addr); |
| /* scissors 12 */ |
| set_scissors(rdev, dst_x, 0, dst_x + cur_size, h); |
| /* 14 */ |
| vb_gpu_addr = rdev->r600_blit.vb_ib->gpu_addr + rdev->r600_blit.vb_used; |
| set_vtx_resource(rdev, vb_gpu_addr); |
| /* draw 10 */ |
| draw_auto(rdev); |
| /* 5 */ |
| cp_set_surface_sync(rdev, |
| PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA, |
| cur_size * h, dst_gpu_addr); |
| vb += 12; |
| rdev->r600_blit.vb_used += 12 * 4; |
| src_gpu_addr += cur_size * h; |
| dst_gpu_addr += cur_size * h; |
| size_bytes -= cur_size * h; |
| } |
| } else { |
| max_bytes = 8192 * 4; |
| while (size_bytes) { |
| int cur_size = size_bytes; |
| int src_x = (src_gpu_addr & 255); |
| int dst_x = (dst_gpu_addr & 255); |
| int h = 1; |
| src_gpu_addr = src_gpu_addr & ~255ULL; |
| dst_gpu_addr = dst_gpu_addr & ~255ULL; |
| if (!src_x && !dst_x) { |
| h = (cur_size / max_bytes); |
| if (h > 8192) |
| h = 8192; |
| if (h == 0) |
| h = 1; |
| else |
| cur_size = max_bytes; |
| } else { |
| if (cur_size > max_bytes) |
| cur_size = max_bytes; |
| if (cur_size > (max_bytes - dst_x)) |
| cur_size = (max_bytes - dst_x); |
| if (cur_size > (max_bytes - src_x)) |
| cur_size = (max_bytes - src_x); |
| } |
| if ((rdev->r600_blit.vb_used + 48) > rdev->r600_blit.vb_total) { |
| // WARN_ON(1); |
| } |
| vb[0] = i2f(dst_x / 4); |
| vb[1] = 0; |
| vb[2] = i2f(src_x / 4); |
| vb[3] = 0; |
| vb[4] = i2f(dst_x / 4); |
| vb[5] = i2f(h); |
| vb[6] = i2f(src_x / 4); |
| vb[7] = i2f(h); |
| vb[8] = i2f((dst_x + cur_size) / 4); |
| vb[9] = i2f(h); |
| vb[10] = i2f((src_x + cur_size) / 4); |
| vb[11] = i2f(h); |
| /* src 9 */ |
| set_tex_resource(rdev, FMT_8_8_8_8, |
| (src_x + cur_size) / 4, |
| h, (src_x + cur_size) / 4, |
| src_gpu_addr); |
| /* 5 */ |
| cp_set_surface_sync(rdev, |
| PACKET3_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr); |
| /* dst 23 */ |
| set_render_target(rdev, COLOR_8_8_8_8, |
| (dst_x + cur_size) / 4, h, |
| dst_gpu_addr); |
| /* scissors 12 */ |
| set_scissors(rdev, (dst_x / 4), 0, (dst_x + cur_size / 4), h); |
| /* Vertex buffer setup 14 */ |
| vb_gpu_addr = rdev->r600_blit.vb_ib->gpu_addr + rdev->r600_blit.vb_used; |
| set_vtx_resource(rdev, vb_gpu_addr); |
| /* draw 10 */ |
| draw_auto(rdev); |
| /* 5 */ |
| cp_set_surface_sync(rdev, |
| PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA, |
| cur_size * h, dst_gpu_addr); |
| /* 78 ring dwords per loop */ |
| vb += 12; |
| rdev->r600_blit.vb_used += 12 * 4; |
| src_gpu_addr += cur_size * h; |
| dst_gpu_addr += cur_size * h; |
| size_bytes -= cur_size * h; |
| } |
| } |
| } |
| /drivers/video/drm/radeon/r600_blit_shaders.c |
|---|
| 0,0 → 1,710 |
| /* |
| * Copyright 2009 Advanced Micro Devices, Inc. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice (including the next |
| * paragraph) shall be included in all copies or substantial portions of the |
| * Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| * DEALINGS IN THE SOFTWARE. |
| * |
| * Authors: |
| * Alex Deucher <alexander.deucher@amd.com> |
| */ |
| #include <linux/types.h> |
| #include <linux/kernel.h> |
| /* |
| * R6xx+ cards need to use the 3D engine to blit data which requires |
| * quite a bit of hw state setup. Rather than pull the whole 3D driver |
| * (which normally generates the 3D state) into the DRM, we opt to use |
| * statically generated state tables. The regsiter state and shaders |
| * were hand generated to support blitting functionality. See the 3D |
| * driver or documentation for descriptions of the registers and |
| * shader instructions. |
| */ |
| const u32 r6xx_default_state[] = |
| { |
| 0xc0002400, /* START_3D_CMDBUF */ |
| 0x00000000, |
| 0xc0012800, /* CONTEXT_CONTROL */ |
| 0x80000000, |
| 0x80000000, |
| 0xc0016800, |
| 0x00000010, |
| 0x00008000, /* WAIT_UNTIL */ |
| 0xc0016800, |
| 0x00000542, |
| 0x07000003, /* TA_CNTL_AUX */ |
| 0xc0016800, |
| 0x000005c5, |
| 0x00000000, /* VC_ENHANCE */ |
| 0xc0016800, |
| 0x00000363, |
| 0x00000000, /* SQ_DYN_GPR_CNTL_PS_FLUSH_REQ */ |
| 0xc0016800, |
| 0x0000060c, |
| 0x82000000, /* DB_DEBUG */ |
| 0xc0016800, |
| 0x0000060e, |
| 0x01020204, /* DB_WATERMARKS */ |
| 0xc0026f00, |
| 0x00000000, |
| 0x00000000, /* SQ_VTX_BASE_VTX_LOC */ |
| 0x00000000, /* SQ_VTX_START_INST_LOC */ |
| 0xc0096900, |
| 0x0000022a, |
| 0x00000000, /* SQ_ESGS_RING_ITEMSIZE */ |
| 0x00000000, |
| 0x00000000, |
| 0x00000000, |
| 0x00000000, |
| 0x00000000, |
| 0x00000000, |
| 0x00000000, |
| 0x00000000, |
| 0xc0016900, |
| 0x00000004, |
| 0x00000000, /* DB_DEPTH_INFO */ |
| 0xc0026900, |
| 0x0000000a, |
| 0x00000000, /* DB_STENCIL_CLEAR */ |
| 0x00000000, /* DB_DEPTH_CLEAR */ |
| 0xc0016900, |
| 0x00000200, |
| 0x00000000, /* DB_DEPTH_CONTROL */ |
| 0xc0026900, |
| 0x00000343, |
| 0x00000060, /* DB_RENDER_CONTROL */ |
| 0x00000040, /* DB_RENDER_OVERRIDE */ |
| 0xc0016900, |
| 0x00000351, |
| 0x0000aa00, /* DB_ALPHA_TO_MASK */ |
| 0xc00f6900, |
| 0x00000100, |
| 0x00000800, /* VGT_MAX_VTX_INDX */ |
| 0x00000000, /* VGT_MIN_VTX_INDX */ |
| 0x00000000, /* VGT_INDX_OFFSET */ |
| 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */ |
| 0x00000000, /* SX_ALPHA_TEST_CONTROL */ |
| 0x00000000, /* CB_BLEND_RED */ |
| 0x00000000, |
| 0x00000000, |
| 0x00000000, |
| 0x00000000, /* CB_FOG_RED */ |
| 0x00000000, |
| 0x00000000, |
| 0x00000000, /* DB_STENCILREFMASK */ |
| 0x00000000, /* DB_STENCILREFMASK_BF */ |
| 0x00000000, /* SX_ALPHA_REF */ |
| 0xc0046900, |
| 0x0000030c, |
| 0x01000000, /* CB_CLRCMP_CNTL */ |
| 0x00000000, |
| 0x00000000, |
| 0x00000000, |
| 0xc0046900, |
| 0x00000048, |
| 0x3f800000, /* CB_CLEAR_RED */ |
| 0x00000000, |
| 0x3f800000, |
| 0x3f800000, |
| 0xc0016900, |
| 0x00000080, |
| 0x00000000, /* PA_SC_WINDOW_OFFSET */ |
| 0xc00a6900, |
| 0x00000083, |
| 0x0000ffff, /* PA_SC_CLIP_RECT_RULE */ |
| 0x00000000, /* PA_SC_CLIPRECT_0_TL */ |
| 0x20002000, |
| 0x00000000, |
| 0x20002000, |
| 0x00000000, |
| 0x20002000, |
| 0x00000000, |
| 0x20002000, |
| 0x00000000, /* PA_SC_EDGERULE */ |
| 0xc0406900, |
| 0x00000094, |
| 0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */ |
| 0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */ |
| 0x80000000, /* PA_SC_VPORT_SCISSOR_1_TL */ |
| 0x20002000, |
| 0x80000000, |
| 0x20002000, |
| 0x80000000, |
| 0x20002000, |
| 0x80000000, |
| 0x20002000, |
| 0x80000000, |
| 0x20002000, |
| 0x80000000, |
| 0x20002000, |
| 0x80000000, |
| 0x20002000, |
| 0x80000000, |
| 0x20002000, |
| 0x80000000, |
| 0x20002000, |
| 0x80000000, |
| 0x20002000, |
| 0x80000000, |
| 0x20002000, |
| 0x80000000, |
| 0x20002000, |
| 0x80000000, |
| 0x20002000, |
| 0x80000000, |
| 0x20002000, |
| 0x80000000, |
| 0x20002000, |
| 0x00000000, /* PA_SC_VPORT_ZMIN_0 */ |
| 0x3f800000, |
| 0x00000000, |
| 0x3f800000, |
| 0x00000000, |
| 0x3f800000, |
| 0x00000000, |
| 0x3f800000, |
| 0x00000000, |
| 0x3f800000, |
| 0x00000000, |
| 0x3f800000, |
| 0x00000000, |
| 0x3f800000, |
| 0x00000000, |
| 0x3f800000, |
| 0x00000000, |
| 0x3f800000, |
| 0x00000000, |
| 0x3f800000, |
| 0x00000000, |
| 0x3f800000, |
| 0x00000000, |
| 0x3f800000, |
| 0x00000000, |
| 0x3f800000, |
| 0x00000000, |
| 0x3f800000, |
| 0x00000000, |
| 0x3f800000, |
| 0x00000000, |
| 0x3f800000, |
| 0xc0026900, |
| 0x00000292, |
| 0x00000000, /* PA_SC_MPASS_PS_CNTL */ |
| 0x00004010, /* PA_SC_MODE_CNTL */ |
| 0xc0096900, |
| 0x00000300, |
| 0x00000000, /* PA_SC_LINE_CNTL */ |
| 0x00000000, /* PA_SC_AA_CONFIG */ |
| 0x0000002d, /* PA_SU_VTX_CNTL */ |
| 0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */ |
| 0x3f800000, |
| 0x3f800000, |
| 0x3f800000, |
| 0x00000000, /* PA_SC_SAMPLE_LOCS_MCTX */ |
| 0x00000000, |
| 0xc0016900, |
| 0x00000312, |
| 0xffffffff, /* PA_SC_AA_MASK */ |
| 0xc0066900, |
| 0x0000037e, |
| 0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */ |
| 0x00000000, /* PA_SU_POLY_OFFSET_CLAMP */ |
| 0x00000000, /* PA_SU_POLY_OFFSET_FRONT_SCALE */ |
| 0x00000000, /* PA_SU_POLY_OFFSET_FRONT_OFFSET */ |
| 0x00000000, /* PA_SU_POLY_OFFSET_BACK_SCALE */ |
| 0x00000000, /* PA_SU_POLY_OFFSET_BACK_OFFSET */ |
| 0xc0046900, |
| 0x000001b6, |
| 0x00000000, /* SPI_INPUT_Z */ |
| 0x00000000, /* SPI_FOG_CNTL */ |
| 0x00000000, /* SPI_FOG_FUNC_SCALE */ |
| 0x00000000, /* SPI_FOG_FUNC_BIAS */ |
| 0xc0016900, |
| 0x00000225, |
| 0x00000000, /* SQ_PGM_START_FS */ |
| 0xc0016900, |
| 0x00000229, |
| 0x00000000, /* SQ_PGM_RESOURCES_FS */ |
| 0xc0016900, |
| 0x00000237, |
| 0x00000000, /* SQ_PGM_CF_OFFSET_FS */ |
| 0xc0026900, |
| 0x000002a8, |
| 0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */ |
| 0x00000000, /* VGT_INSTANCE_STEP_RATE_1 */ |
| 0xc0116900, |
| 0x00000280, |
| 0x00000000, /* PA_SU_POINT_SIZE */ |
| 0x00000000, /* PA_SU_POINT_MINMAX */ |
| 0x00000008, /* PA_SU_LINE_CNTL */ |
| 0x00000000, /* PA_SC_LINE_STIPPLE */ |
| 0x00000000, /* VGT_OUTPUT_PATH_CNTL */ |
| 0x00000000, /* VGT_HOS_CNTL */ |
| 0x00000000, /* VGT_HOS_MAX_TESS_LEVEL */ |
| 0x00000000, /* VGT_HOS_MIN_TESS_LEVEL */ |
| 0x00000000, /* VGT_HOS_REUSE_DEPTH */ |
| 0x00000000, /* VGT_GROUP_PRIM_TYPE */ |
| 0x00000000, /* VGT_GROUP_FIRST_DECR */ |
| 0x00000000, /* VGT_GROUP_DECR */ |
| 0x00000000, /* VGT_GROUP_VECT_0_CNTL */ |
| 0x00000000, /* VGT_GROUP_VECT_1_CNTL */ |
| 0x00000000, /* VGT_GROUP_VECT_0_FMT_CNTL */ |
| 0x00000000, /* VGT_GROUP_VECT_1_FMT_CNTL */ |
| 0x00000000, /* VGT_GS_MODE */ |
| 0xc0016900, |
| 0x000002a1, |
| 0x00000000, /* VGT_PRIMITIVEID_EN */ |
| 0xc0016900, |
| 0x000002a5, |
| 0x00000000, /* VGT_MULTI_PRIM_ID_RESET_EN */ |
| 0xc0036900, |
| 0x000002ac, |
| 0x00000000, /* VGT_STRMOUT_EN */ |
| 0x00000000, /* VGT_REUSE_OFF */ |
| 0x00000000, /* VGT_VTX_CNT_EN */ |
| 0xc0016900, |
| 0x000002c8, |
| 0x00000000, /* VGT_STRMOUT_BUFFER_EN */ |
| 0xc0076900, |
| 0x00000202, |
| 0x00cc0000, /* CB_COLOR_CONTROL */ |
| 0x00000210, /* DB_SHADER_CNTL */ |
| 0x00010000, /* PA_CL_CLIP_CNTL */ |
| 0x00000244, /* PA_SU_SC_MODE_CNTL */ |
| 0x00000100, /* PA_CL_VTE_CNTL */ |
| 0x00000000, /* PA_CL_VS_OUT_CNTL */ |
| 0x00000000, /* PA_CL_NANINF_CNTL */ |
| 0xc0026900, |
| 0x0000008e, |
| 0x0000000f, /* CB_TARGET_MASK */ |
| 0x0000000f, /* CB_SHADER_MASK */ |
| 0xc0016900, |
| 0x000001e8, |
| 0x00000001, /* CB_SHADER_CONTROL */ |
| 0xc0016900, |
| 0x00000185, |
| 0x00000000, /* SPI_VS_OUT_ID_0 */ |
| 0xc0016900, |
| 0x00000191, |
| 0x00000b00, /* SPI_PS_INPUT_CNTL_0 */ |
| 0xc0056900, |
| 0x000001b1, |
| 0x00000000, /* SPI_VS_OUT_CONFIG */ |
| 0x00000000, /* SPI_THREAD_GROUPING */ |
| 0x00000001, /* SPI_PS_IN_CONTROL_0 */ |
| 0x00000000, /* SPI_PS_IN_CONTROL_1 */ |
| 0x00000000, /* SPI_INTERP_CONTROL_0 */ |
| 0xc0036e00, /* SET_SAMPLER */ |
| 0x00000000, |
| 0x00000012, |
| 0x00000000, |
| 0x00000000, |
| }; |
| const u32 r7xx_default_state[] = |
| { |
| 0xc0012800, /* CONTEXT_CONTROL */ |
| 0x80000000, |
| 0x80000000, |
| 0xc0016800, |
| 0x00000010, |
| 0x00008000, /* WAIT_UNTIL */ |
| 0xc0016800, |
| 0x00000542, |
| 0x07000002, /* TA_CNTL_AUX */ |
| 0xc0016800, |
| 0x000005c5, |
| 0x00000000, /* VC_ENHANCE */ |
| 0xc0016800, |
| 0x00000363, |
| 0x00004000, /* SQ_DYN_GPR_CNTL_PS_FLUSH_REQ */ |
| 0xc0016800, |
| 0x0000060c, |
| 0x00000000, /* DB_DEBUG */ |
| 0xc0016800, |
| 0x0000060e, |
| 0x00420204, /* DB_WATERMARKS */ |
| 0xc0026f00, |
| 0x00000000, |
| 0x00000000, /* SQ_VTX_BASE_VTX_LOC */ |
| 0x00000000, /* SQ_VTX_START_INST_LOC */ |
| 0xc0096900, |
| 0x0000022a, |
| 0x00000000, /* SQ_ESGS_RING_ITEMSIZE */ |
| 0x00000000, |
| 0x00000000, |
| 0x00000000, |
| 0x00000000, |
| 0x00000000, |
| 0x00000000, |
| 0x00000000, |
| 0x00000000, |
| 0xc0016900, |
| 0x00000004, |
| 0x00000000, /* DB_DEPTH_INFO */ |
| 0xc0026900, |
| 0x0000000a, |
| 0x00000000, /* DB_STENCIL_CLEAR */ |
| 0x00000000, /* DB_DEPTH_CLEAR */ |
| 0xc0016900, |
| 0x00000200, |
| 0x00000000, /* DB_DEPTH_CONTROL */ |
| 0xc0026900, |
| 0x00000343, |
| 0x00000060, /* DB_RENDER_CONTROL */ |
| 0x00000000, /* DB_RENDER_OVERRIDE */ |
| 0xc0016900, |
| 0x00000351, |
| 0x0000aa00, /* DB_ALPHA_TO_MASK */ |
| 0xc0096900, |
| 0x00000100, |
| 0x00000800, /* VGT_MAX_VTX_INDX */ |
| 0x00000000, /* VGT_MIN_VTX_INDX */ |
| 0x00000000, /* VGT_INDX_OFFSET */ |
| 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */ |
| 0x00000000, /* SX_ALPHA_TEST_CONTROL */ |
| 0x00000000, /* CB_BLEND_RED */ |
| 0x00000000, |
| 0x00000000, |
| 0x00000000, |
| 0xc0036900, |
| 0x0000010c, |
| 0x00000000, /* DB_STENCILREFMASK */ |
| 0x00000000, /* DB_STENCILREFMASK_BF */ |
| 0x00000000, /* SX_ALPHA_REF */ |
| 0xc0046900, |
| 0x0000030c, /* CB_CLRCMP_CNTL */ |
| 0x01000000, |
| 0x00000000, |
| 0x00000000, |
| 0x00000000, |
| 0xc0016900, |
| 0x00000080, |
| 0x00000000, /* PA_SC_WINDOW_OFFSET */ |
| 0xc00a6900, |
| 0x00000083, |
| 0x0000ffff, /* PA_SC_CLIP_RECT_RULE */ |
| 0x00000000, /* PA_SC_CLIPRECT_0_TL */ |
| 0x20002000, |
| 0x00000000, |
| 0x20002000, |
| 0x00000000, |
| 0x20002000, |
| 0x00000000, |
| 0x20002000, |
| 0xaaaaaaaa, /* PA_SC_EDGERULE */ |
| 0xc0406900, |
| 0x00000094, |
| 0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */ |
| 0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */ |
| 0x80000000, /* PA_SC_VPORT_SCISSOR_1_TL */ |
| 0x20002000, |
| 0x80000000, |
| 0x20002000, |
| 0x80000000, |
| 0x20002000, |
| 0x80000000, |
| 0x20002000, |
| 0x80000000, |
| 0x20002000, |
| 0x80000000, |
| 0x20002000, |
| 0x80000000, |
| 0x20002000, |
| 0x80000000, |
| 0x20002000, |
| 0x80000000, |
| 0x20002000, |
| 0x80000000, |
| 0x20002000, |
| 0x80000000, |
| 0x20002000, |
| 0x80000000, |
| 0x20002000, |
| 0x80000000, |
| 0x20002000, |
| 0x80000000, |
| 0x20002000, |
| 0x80000000, |
| 0x20002000, |
| 0x00000000, /* PA_SC_VPORT_ZMIN_0 */ |
| 0x3f800000, |
| 0x00000000, |
| 0x3f800000, |
| 0x00000000, |
| 0x3f800000, |
| 0x00000000, |
| 0x3f800000, |
| 0x00000000, |
| 0x3f800000, |
| 0x00000000, |
| 0x3f800000, |
| 0x00000000, |
| 0x3f800000, |
| 0x00000000, |
| 0x3f800000, |
| 0x00000000, |
| 0x3f800000, |
| 0x00000000, |
| 0x3f800000, |
| 0x00000000, |
| 0x3f800000, |
| 0x00000000, |
| 0x3f800000, |
| 0x00000000, |
| 0x3f800000, |
| 0x00000000, |
| 0x3f800000, |
| 0x00000000, |
| 0x3f800000, |
| 0x00000000, |
| 0x3f800000, |
| 0xc0026900, |
| 0x00000292, |
| 0x00000000, /* PA_SC_MPASS_PS_CNTL */ |
| 0x00514000, /* PA_SC_MODE_CNTL */ |
| 0xc0096900, |
| 0x00000300, |
| 0x00000000, /* PA_SC_LINE_CNTL */ |
| 0x00000000, /* PA_SC_AA_CONFIG */ |
| 0x0000002d, /* PA_SU_VTX_CNTL */ |
| 0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */ |
| 0x3f800000, |
| 0x3f800000, |
| 0x3f800000, |
| 0x00000000, /* PA_SC_SAMPLE_LOCS_MCTX */ |
| 0x00000000, |
| 0xc0016900, |
| 0x00000312, |
| 0xffffffff, /* PA_SC_AA_MASK */ |
| 0xc0066900, |
| 0x0000037e, |
| 0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */ |
| 0x00000000, /* PA_SU_POLY_OFFSET_CLAMP */ |
| 0x00000000, /* PA_SU_POLY_OFFSET_FRONT_SCALE */ |
| 0x00000000, /* PA_SU_POLY_OFFSET_FRONT_OFFSET */ |
| 0x00000000, /* PA_SU_POLY_OFFSET_BACK_SCALE */ |
| 0x00000000, /* PA_SU_POLY_OFFSET_BACK_OFFSET */ |
| 0xc0046900, |
| 0x000001b6, |
| 0x00000000, /* SPI_INPUT_Z */ |
| 0x00000000, /* SPI_FOG_CNTL */ |
| 0x00000000, /* SPI_FOG_FUNC_SCALE */ |
| 0x00000000, /* SPI_FOG_FUNC_BIAS */ |
| 0xc0016900, |
| 0x00000225, |
| 0x00000000, /* SQ_PGM_START_FS */ |
| 0xc0016900, |
| 0x00000229, |
| 0x00000000, /* SQ_PGM_RESOURCES_FS */ |
| 0xc0016900, |
| 0x00000237, |
| 0x00000000, /* SQ_PGM_CF_OFFSET_FS */ |
| 0xc0026900, |
| 0x000002a8, |
| 0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */ |
| 0x00000000, /* VGT_INSTANCE_STEP_RATE_1 */ |
| 0xc0116900, |
| 0x00000280, |
| 0x00000000, /* PA_SU_POINT_SIZE */ |
| 0x00000000, /* PA_SU_POINT_MINMAX */ |
| 0x00000008, /* PA_SU_LINE_CNTL */ |
| 0x00000000, /* PA_SC_LINE_STIPPLE */ |
| 0x00000000, /* VGT_OUTPUT_PATH_CNTL */ |
| 0x00000000, /* VGT_HOS_CNTL */ |
| 0x00000000, /* VGT_HOS_MAX_TESS_LEVEL */ |
| 0x00000000, /* VGT_HOS_MIN_TESS_LEVEL */ |
| 0x00000000, /* VGT_HOS_REUSE_DEPTH */ |
| 0x00000000, /* VGT_GROUP_PRIM_TYPE */ |
| 0x00000000, /* VGT_GROUP_FIRST_DECR */ |
| 0x00000000, /* VGT_GROUP_DECR */ |
| 0x00000000, /* VGT_GROUP_VECT_0_CNTL */ |
| 0x00000000, /* VGT_GROUP_VECT_1_CNTL */ |
| 0x00000000, /* VGT_GROUP_VECT_0_FMT_CNTL */ |
| 0x00000000, /* VGT_GROUP_VECT_1_FMT_CNTL */ |
| 0x00000000, /* VGT_GS_MODE */ |
| 0xc0016900, |
| 0x000002a1, |
| 0x00000000, /* VGT_PRIMITIVEID_EN */ |
| 0xc0016900, |
| 0x000002a5, |
| 0x00000000, /* VGT_MULTI_PRIM_ID_RESET_EN */ |
| 0xc0036900, |
| 0x000002ac, |
| 0x00000000, /* VGT_STRMOUT_EN */ |
| 0x00000000, /* VGT_REUSE_OFF */ |
| 0x00000000, /* VGT_VTX_CNT_EN */ |
| 0xc0016900, |
| 0x000002c8, |
| 0x00000000, /* VGT_STRMOUT_BUFFER_EN */ |
| 0xc0076900, |
| 0x00000202, |
| 0x00cc0000, /* CB_COLOR_CONTROL */ |
| 0x00000210, /* DB_SHADER_CNTL */ |
| 0x00010000, /* PA_CL_CLIP_CNTL */ |
| 0x00000244, /* PA_SU_SC_MODE_CNTL */ |
| 0x00000100, /* PA_CL_VTE_CNTL */ |
| 0x00000000, /* PA_CL_VS_OUT_CNTL */ |
| 0x00000000, /* PA_CL_NANINF_CNTL */ |
| 0xc0026900, |
| 0x0000008e, |
| 0x0000000f, /* CB_TARGET_MASK */ |
| 0x0000000f, /* CB_SHADER_MASK */ |
| 0xc0016900, |
| 0x000001e8, |
| 0x00000001, /* CB_SHADER_CONTROL */ |
| 0xc0016900, |
| 0x00000185, |
| 0x00000000, /* SPI_VS_OUT_ID_0 */ |
| 0xc0016900, |
| 0x00000191, |
| 0x00000b00, /* SPI_PS_INPUT_CNTL_0 */ |
| 0xc0056900, |
| 0x000001b1, |
| 0x00000000, /* SPI_VS_OUT_CONFIG */ |
| 0x00000001, /* SPI_THREAD_GROUPING */ |
| 0x00000001, /* SPI_PS_IN_CONTROL_0 */ |
| 0x00000000, /* SPI_PS_IN_CONTROL_1 */ |
| 0x00000000, /* SPI_INTERP_CONTROL_0 */ |
| 0xc0036e00, /* SET_SAMPLER */ |
| 0x00000000, |
| 0x00000012, |
| 0x00000000, |
| 0x00000000, |
| }; |
| /* same for r6xx/r7xx */ |
| const u32 r6xx_vs[] = |
| { |
| 0x00000004, |
| 0x81000000, |
| 0x0000203c, |
| 0x94000b08, |
| 0x00004000, |
| 0x14200b1a, |
| 0x00000000, |
| 0x00000000, |
| 0x3c000000, |
| 0x68cd1000, |
| #ifdef __BIG_ENDIAN |
| 0x000a0000, |
| #else |
| 0x00080000, |
| #endif |
| 0x00000000, |
| }; |
| const u32 r6xx_ps[] = |
| { |
| 0x00000002, |
| 0x80800000, |
| 0x00000000, |
| 0x94200688, |
| 0x00000010, |
| 0x000d1000, |
| 0xb0800000, |
| 0x00000000, |
| }; |
| const u32 r6xx_ps_size = ARRAY_SIZE(r6xx_ps); |
| const u32 r6xx_vs_size = ARRAY_SIZE(r6xx_vs); |
| const u32 r6xx_default_size = ARRAY_SIZE(r6xx_default_state); |
| const u32 r7xx_default_size = ARRAY_SIZE(r7xx_default_state); |
| /drivers/video/drm/radeon/r600_blit_shaders.h |
|---|
| 0,0 → 1,38 |
| /* |
| * Copyright 2009 Advanced Micro Devices, Inc. |
| * Copyright 2009 Red Hat Inc. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice (including the next |
| * paragraph) shall be included in all copies or substantial portions of the |
| * Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| * DEALINGS IN THE SOFTWARE. |
| * |
| */ |
| #ifndef R600_BLIT_SHADERS_H |
| #define R600_BLIT_SHADERS_H |
| extern const u32 r6xx_ps[]; |
| extern const u32 r6xx_vs[]; |
| extern const u32 r7xx_default_state[]; |
| extern const u32 r6xx_default_state[]; |
| extern const u32 r6xx_ps_size, r6xx_vs_size; |
| extern const u32 r6xx_default_size, r7xx_default_size; |
| #endif |
| /drivers/video/drm/radeon/radeon.h |
|---|
| 295,6 → 295,7 |
| uint32_t seq; |
| bool emited; |
| bool signaled; |
| evhandle_t evnt; |
| }; |
| int radeon_fence_driver_init(struct radeon_device *rdev); |
| /drivers/video/drm/radeon/radeon_asic.c |
|---|
| 134,6 → 134,7 |
| // .suspend = &r100_suspend, |
| // .resume = &r100_resume, |
| // .vga_set_state = &r100_vga_set_state, |
| .gpu_is_lockup = &r100_gpu_is_lockup, |
| .asic_reset = &r100_asic_reset, |
| .gart_tlb_flush = &r100_pci_gart_tlb_flush, |
| .gart_set_page = &r100_pci_gart_set_page, |
| 140,15 → 141,15 |
| .cp_commit = &r100_cp_commit, |
| .ring_start = &r100_ring_start, |
| .ring_test = &r100_ring_test, |
| // .ring_ib_execute = &r100_ring_ib_execute, |
| // .irq_set = &r100_irq_set, |
| // .irq_process = &r100_irq_process, |
| .ring_ib_execute = &r100_ring_ib_execute, |
| .irq_set = &r100_irq_set, |
| .irq_process = &r100_irq_process, |
| // .get_vblank_counter = &r100_get_vblank_counter, |
| .fence_ring_emit = &r100_fence_ring_emit, |
| // .cs_parse = &r100_cs_parse, |
| // .copy_blit = &r100_copy_blit, |
| // .copy_dma = NULL, |
| // .copy = &r100_copy_blit, |
| .copy_blit = &r100_copy_blit, |
| .copy_dma = NULL, |
| .copy = &r100_copy_blit, |
| .get_engine_clock = &radeon_legacy_get_engine_clock, |
| .set_engine_clock = &radeon_legacy_set_engine_clock, |
| .get_memory_clock = &radeon_legacy_get_memory_clock, |
| 172,6 → 173,7 |
| // .suspend = &r100_suspend, |
| // .resume = &r100_resume, |
| // .vga_set_state = &r100_vga_set_state, |
| .gpu_is_lockup = &r100_gpu_is_lockup, |
| .asic_reset = &r100_asic_reset, |
| .gart_tlb_flush = &r100_pci_gart_tlb_flush, |
| .gart_set_page = &r100_pci_gart_set_page, |
| 178,15 → 180,15 |
| .cp_commit = &r100_cp_commit, |
| .ring_start = &r100_ring_start, |
| .ring_test = &r100_ring_test, |
| // .ring_ib_execute = &r100_ring_ib_execute, |
| // .irq_set = &r100_irq_set, |
| // .irq_process = &r100_irq_process, |
| .ring_ib_execute = &r100_ring_ib_execute, |
| .irq_set = &r100_irq_set, |
| .irq_process = &r100_irq_process, |
| // .get_vblank_counter = &r100_get_vblank_counter, |
| .fence_ring_emit = &r100_fence_ring_emit, |
| // .cs_parse = &r100_cs_parse, |
| // .copy_blit = &r100_copy_blit, |
| // .copy_dma = NULL, |
| // .copy = &r100_copy_blit, |
| .copy_blit = &r100_copy_blit, |
| .copy_dma = &r200_copy_dma, |
| .copy = &r100_copy_blit, |
| .get_engine_clock = &radeon_legacy_get_engine_clock, |
| .set_engine_clock = &radeon_legacy_set_engine_clock, |
| .get_memory_clock = &radeon_legacy_get_memory_clock, |
| 215,15 → 217,15 |
| .cp_commit = &r100_cp_commit, |
| .ring_start = &r300_ring_start, |
| .ring_test = &r100_ring_test, |
| // .ring_ib_execute = &r100_ring_ib_execute, |
| // .irq_set = &r100_irq_set, |
| // .irq_process = &r100_irq_process, |
| .ring_ib_execute = &r100_ring_ib_execute, |
| .irq_set = &r100_irq_set, |
| .irq_process = &r100_irq_process, |
| // .get_vblank_counter = &r100_get_vblank_counter, |
| .fence_ring_emit = &r300_fence_ring_emit, |
| // .cs_parse = &r300_cs_parse, |
| // .copy_blit = &r100_copy_blit, |
| // .copy_dma = &r300_copy_dma, |
| // .copy = &r100_copy_blit, |
| .copy_blit = &r100_copy_blit, |
| .copy_dma = &r200_copy_dma, |
| .copy = &r100_copy_blit, |
| .get_engine_clock = &radeon_legacy_get_engine_clock, |
| .set_engine_clock = &radeon_legacy_set_engine_clock, |
| .get_memory_clock = &radeon_legacy_get_memory_clock, |
| 253,15 → 255,15 |
| .cp_commit = &r100_cp_commit, |
| .ring_start = &r300_ring_start, |
| .ring_test = &r100_ring_test, |
| // .ring_ib_execute = &r100_ring_ib_execute, |
| // .irq_set = &r100_irq_set, |
| // .irq_process = &r100_irq_process, |
| .ring_ib_execute = &r100_ring_ib_execute, |
| .irq_set = &r100_irq_set, |
| .irq_process = &r100_irq_process, |
| // .get_vblank_counter = &r100_get_vblank_counter, |
| .fence_ring_emit = &r300_fence_ring_emit, |
| // .cs_parse = &r300_cs_parse, |
| // .copy_blit = &r100_copy_blit, |
| // .copy_dma = &r300_copy_dma, |
| // .copy = &r100_copy_blit, |
| .copy_blit = &r100_copy_blit, |
| .copy_dma = &r200_copy_dma, |
| .copy = &r100_copy_blit, |
| .get_engine_clock = &radeon_legacy_get_engine_clock, |
| .set_engine_clock = &radeon_legacy_set_engine_clock, |
| .get_memory_clock = &radeon_legacy_get_memory_clock, |
| 290,15 → 292,15 |
| .cp_commit = &r100_cp_commit, |
| .ring_start = &r300_ring_start, |
| .ring_test = &r100_ring_test, |
| // .ring_ib_execute = &r100_ring_ib_execute, |
| // .irq_set = &r100_irq_set, |
| // .irq_process = &r100_irq_process, |
| .ring_ib_execute = &r100_ring_ib_execute, |
| .irq_set = &r100_irq_set, |
| .irq_process = &r100_irq_process, |
| // .get_vblank_counter = &r100_get_vblank_counter, |
| .fence_ring_emit = &r300_fence_ring_emit, |
| // .cs_parse = &r300_cs_parse, |
| // .copy_blit = &r100_copy_blit, |
| // .copy_dma = &r300_copy_dma, |
| // .copy = &r100_copy_blit, |
| .copy_blit = &r100_copy_blit, |
| .copy_dma = &r200_copy_dma, |
| .copy = &r100_copy_blit, |
| .get_engine_clock = &radeon_atom_get_engine_clock, |
| .set_engine_clock = &radeon_atom_set_engine_clock, |
| .get_memory_clock = &radeon_atom_get_memory_clock, |
| 328,15 → 330,15 |
| .cp_commit = &r100_cp_commit, |
| .ring_start = &r300_ring_start, |
| .ring_test = &r100_ring_test, |
| // .ring_ib_execute = &r100_ring_ib_execute, |
| // .irq_set = &r100_irq_set, |
| // .irq_process = &r100_irq_process, |
| .ring_ib_execute = &r100_ring_ib_execute, |
| .irq_set = &r100_irq_set, |
| .irq_process = &r100_irq_process, |
| // .get_vblank_counter = &r100_get_vblank_counter, |
| .fence_ring_emit = &r300_fence_ring_emit, |
| // .cs_parse = &r300_cs_parse, |
| // .copy_blit = &r100_copy_blit, |
| // .copy_dma = &r300_copy_dma, |
| // .copy = &r100_copy_blit, |
| .copy_blit = &r100_copy_blit, |
| .copy_dma = &r200_copy_dma, |
| .copy = &r100_copy_blit, |
| .get_engine_clock = &radeon_legacy_get_engine_clock, |
| .set_engine_clock = &radeon_legacy_set_engine_clock, |
| .get_memory_clock = &radeon_legacy_get_memory_clock, |
| 366,15 → 368,15 |
| .cp_commit = &r100_cp_commit, |
| .ring_start = &r300_ring_start, |
| .ring_test = &r100_ring_test, |
| // .ring_ib_execute = &r100_ring_ib_execute, |
| // .irq_set = &rs600_irq_set, |
| // .irq_process = &rs600_irq_process, |
| .ring_ib_execute = &r100_ring_ib_execute, |
| .irq_set = &rs600_irq_set, |
| .irq_process = &rs600_irq_process, |
| // .get_vblank_counter = &rs600_get_vblank_counter, |
| .fence_ring_emit = &r300_fence_ring_emit, |
| // .cs_parse = &r300_cs_parse, |
| // .copy_blit = &r100_copy_blit, |
| // .copy_dma = &r300_copy_dma, |
| // .copy = &r100_copy_blit, |
| .copy_blit = &r100_copy_blit, |
| .copy_dma = &r200_copy_dma, |
| .copy = &r100_copy_blit, |
| .get_engine_clock = &radeon_atom_get_engine_clock, |
| .set_engine_clock = &radeon_atom_set_engine_clock, |
| .get_memory_clock = &radeon_atom_get_memory_clock, |
| 404,15 → 406,15 |
| .cp_commit = &r100_cp_commit, |
| .ring_start = &r300_ring_start, |
| .ring_test = &r100_ring_test, |
| // .ring_ib_execute = &r100_ring_ib_execute, |
| // .irq_set = &rs600_irq_set, |
| // .irq_process = &rs600_irq_process, |
| .ring_ib_execute = &r100_ring_ib_execute, |
| .irq_set = &rs600_irq_set, |
| .irq_process = &rs600_irq_process, |
| // .get_vblank_counter = &rs600_get_vblank_counter, |
| .fence_ring_emit = &r300_fence_ring_emit, |
| // .cs_parse = &r300_cs_parse, |
| // .copy_blit = &r100_copy_blit, |
| // .copy_dma = &r300_copy_dma, |
| // .copy = &r300_copy_dma, |
| .copy_blit = &r100_copy_blit, |
| .copy_dma = &r200_copy_dma, |
| .copy = &r200_copy_dma, |
| .get_engine_clock = &radeon_atom_get_engine_clock, |
| .set_engine_clock = &radeon_atom_set_engine_clock, |
| .get_memory_clock = &radeon_atom_get_memory_clock, |
| 442,15 → 444,15 |
| .cp_commit = &r100_cp_commit, |
| .ring_start = &rv515_ring_start, |
| .ring_test = &r100_ring_test, |
| // .ring_ib_execute = &r100_ring_ib_execute, |
| // .irq_set = &rs600_irq_set, |
| // .irq_process = &rs600_irq_process, |
| .ring_ib_execute = &r100_ring_ib_execute, |
| .irq_set = &rs600_irq_set, |
| .irq_process = &rs600_irq_process, |
| // .get_vblank_counter = &rs600_get_vblank_counter, |
| .fence_ring_emit = &r300_fence_ring_emit, |
| // .cs_parse = &r300_cs_parse, |
| // .copy_blit = &r100_copy_blit, |
| // .copy_dma = &r300_copy_dma, |
| // .copy = &r100_copy_blit, |
| .copy_blit = &r100_copy_blit, |
| .copy_dma = &r200_copy_dma, |
| .copy = &r100_copy_blit, |
| .get_engine_clock = &radeon_atom_get_engine_clock, |
| .set_engine_clock = &radeon_atom_set_engine_clock, |
| .get_memory_clock = &radeon_atom_get_memory_clock, |
| 480,15 → 482,15 |
| .cp_commit = &r100_cp_commit, |
| .ring_start = &rv515_ring_start, |
| .ring_test = &r100_ring_test, |
| // .ring_ib_execute = &r100_ring_ib_execute, |
| // .irq_set = &rs600_irq_set, |
| // .irq_process = &rs600_irq_process, |
| .ring_ib_execute = &r100_ring_ib_execute, |
| .irq_set = &rs600_irq_set, |
| .irq_process = &rs600_irq_process, |
| // .get_vblank_counter = &rs600_get_vblank_counter, |
| .fence_ring_emit = &r300_fence_ring_emit, |
| // .cs_parse = &r300_cs_parse, |
| // .copy_blit = &r100_copy_blit, |
| // .copy_dma = &r300_copy_dma, |
| // .copy = &r100_copy_blit, |
| .copy_blit = &r100_copy_blit, |
| .copy_dma = &r200_copy_dma, |
| .copy = &r100_copy_blit, |
| .get_engine_clock = &radeon_atom_get_engine_clock, |
| .set_engine_clock = &radeon_atom_set_engine_clock, |
| .get_memory_clock = &radeon_atom_get_memory_clock, |
| 517,20 → 519,20 |
| .gart_tlb_flush = &r600_pcie_gart_tlb_flush, |
| .gart_set_page = &rs600_gart_set_page, |
| .ring_test = &r600_ring_test, |
| // .ring_ib_execute = &r600_ring_ib_execute, |
| .ring_ib_execute = &r600_ring_ib_execute, |
| .irq_set = &r600_irq_set, |
| .irq_process = &r600_irq_process, |
| .fence_ring_emit = &r600_fence_ring_emit, |
| // .cs_parse = &r600_cs_parse, |
| // .copy_blit = &r600_copy_blit, |
| // .copy_dma = &r600_copy_blit, |
| // .copy = &r600_copy_blit, |
| .copy_blit = &r600_copy_blit, |
| .copy_dma = &r600_copy_blit, |
| .copy = &r600_copy_blit, |
| .get_engine_clock = &radeon_atom_get_engine_clock, |
| .set_engine_clock = &radeon_atom_set_engine_clock, |
| .get_memory_clock = &radeon_atom_get_memory_clock, |
| .set_memory_clock = &radeon_atom_set_memory_clock, |
| .get_pcie_lanes = &rv370_get_pcie_lanes, |
| .set_pcie_lanes = NULL, |
| .get_pcie_lanes = &r600_get_pcie_lanes, |
| .set_pcie_lanes = &r600_set_pcie_lanes, |
| .set_clock_gating = NULL, |
| .set_surface_reg = r600_set_surface_reg, |
| .clear_surface_reg = r600_clear_surface_reg, |
| 554,14 → 556,14 |
| .gart_tlb_flush = &r600_pcie_gart_tlb_flush, |
| .gart_set_page = &rs600_gart_set_page, |
| .ring_test = &r600_ring_test, |
| // .ring_ib_execute = &r600_ring_ib_execute, |
| .ring_ib_execute = &r600_ring_ib_execute, |
| .irq_set = &r600_irq_set, |
| .irq_process = &r600_irq_process, |
| .fence_ring_emit = &r600_fence_ring_emit, |
| // .cs_parse = &r600_cs_parse, |
| // .copy_blit = &r600_copy_blit, |
| // .copy_dma = &r600_copy_blit, |
| // .copy = &r600_copy_blit, |
| .copy_blit = &r600_copy_blit, |
| .copy_dma = &r600_copy_blit, |
| .copy = &r600_copy_blit, |
| .get_engine_clock = &radeon_atom_get_engine_clock, |
| .set_engine_clock = &radeon_atom_set_engine_clock, |
| .get_memory_clock = NULL, |
| 594,15 → 596,15 |
| .irq_process = &r600_irq_process, |
| .fence_ring_emit = &r600_fence_ring_emit, |
| // .cs_parse = &r600_cs_parse, |
| // .copy_blit = &r600_copy_blit, |
| // .copy_dma = &r600_copy_blit, |
| // .copy = &r600_copy_blit, |
| .copy_blit = &r600_copy_blit, |
| .copy_dma = &r600_copy_blit, |
| .copy = &r600_copy_blit, |
| .get_engine_clock = &radeon_atom_get_engine_clock, |
| .set_engine_clock = &radeon_atom_set_engine_clock, |
| .get_memory_clock = &radeon_atom_get_memory_clock, |
| .set_memory_clock = &radeon_atom_set_memory_clock, |
| .get_pcie_lanes = &rv370_get_pcie_lanes, |
| .set_pcie_lanes = NULL, |
| .get_pcie_lanes = &r600_get_pcie_lanes, |
| .set_pcie_lanes = &r600_set_pcie_lanes, |
| .set_clock_gating = &radeon_atom_set_clock_gating, |
| .set_surface_reg = r600_set_surface_reg, |
| .clear_surface_reg = r600_clear_surface_reg, |
| 624,14 → 626,14 |
| .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, |
| .gart_set_page = &rs600_gart_set_page, |
| .ring_test = &r600_ring_test, |
| // .ring_ib_execute = &r600_ring_ib_execute, |
| // .irq_set = &r600_irq_set, |
| // .irq_process = &r600_irq_process, |
| .ring_ib_execute = &evergreen_ring_ib_execute, |
| .irq_set = &evergreen_irq_set, |
| .irq_process = &evergreen_irq_process, |
| .fence_ring_emit = &r600_fence_ring_emit, |
| // .cs_parse = &r600_cs_parse, |
| // .copy_blit = &r600_copy_blit, |
| // .copy_dma = &r600_copy_blit, |
| // .copy = &r600_copy_blit, |
| // .cs_parse = &evergreen_cs_parse, |
| .copy_blit = &evergreen_copy_blit, |
| .copy_dma = &evergreen_copy_blit, |
| .copy = &evergreen_copy_blit, |
| .get_engine_clock = &radeon_atom_get_engine_clock, |
| .set_engine_clock = &radeon_atom_set_engine_clock, |
| .get_memory_clock = &radeon_atom_get_memory_clock, |
| 642,6 → 644,10 |
| .set_surface_reg = r600_set_surface_reg, |
| .clear_surface_reg = r600_clear_surface_reg, |
| .bandwidth_update = &evergreen_bandwidth_update, |
| .hpd_init = &evergreen_hpd_init, |
| .hpd_fini = &evergreen_hpd_fini, |
| .hpd_sense = &evergreen_hpd_sense, |
| .hpd_set_polarity = &evergreen_hpd_set_polarity, |
| }; |
| 656,14 → 662,14 |
| .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, |
| .gart_set_page = &rs600_gart_set_page, |
| .ring_test = &r600_ring_test, |
| // .ring_ib_execute = &r600_ring_ib_execute, |
| // .irq_set = &r600_irq_set, |
| // .irq_process = &r600_irq_process, |
| .ring_ib_execute = &evergreen_ring_ib_execute, |
| .irq_set = &evergreen_irq_set, |
| .irq_process = &evergreen_irq_process, |
| .fence_ring_emit = &r600_fence_ring_emit, |
| // .cs_parse = &r600_cs_parse, |
| // .copy_blit = &r600_copy_blit, |
| // .copy_dma = &r600_copy_blit, |
| // .copy = &r600_copy_blit, |
| .copy_blit = &evergreen_copy_blit, |
| .copy_dma = &evergreen_copy_blit, |
| .copy = &evergreen_copy_blit, |
| .get_engine_clock = &radeon_atom_get_engine_clock, |
| .set_engine_clock = &radeon_atom_set_engine_clock, |
| .get_memory_clock = NULL, |
| 674,9 → 680,12 |
| .set_surface_reg = r600_set_surface_reg, |
| .clear_surface_reg = r600_clear_surface_reg, |
| .bandwidth_update = &evergreen_bandwidth_update, |
| .hpd_init = &evergreen_hpd_init, |
| .hpd_fini = &evergreen_hpd_fini, |
| .hpd_sense = &evergreen_hpd_sense, |
| .hpd_set_polarity = &evergreen_hpd_set_polarity, |
| }; |
| static struct radeon_asic btc_asic = { |
| .init = &evergreen_init, |
| // .fini = &evergreen_fini, |
| 688,14 → 697,14 |
| .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, |
| .gart_set_page = &rs600_gart_set_page, |
| .ring_test = &r600_ring_test, |
| // .ring_ib_execute = &r600_ring_ib_execute, |
| // .irq_set = &r600_irq_set, |
| // .irq_process = &r600_irq_process, |
| .ring_ib_execute = &evergreen_ring_ib_execute, |
| .irq_set = &evergreen_irq_set, |
| .irq_process = &evergreen_irq_process, |
| .fence_ring_emit = &r600_fence_ring_emit, |
| // .cs_parse = &r600_cs_parse, |
| // .copy_blit = &r600_copy_blit, |
| // .copy_dma = &r600_copy_blit, |
| // .copy = &r600_copy_blit, |
| // .cs_parse = &evergreen_cs_parse, |
| .copy_blit = &evergreen_copy_blit, |
| .copy_dma = &evergreen_copy_blit, |
| .copy = &evergreen_copy_blit, |
| .get_engine_clock = &radeon_atom_get_engine_clock, |
| .set_engine_clock = &radeon_atom_set_engine_clock, |
| .get_memory_clock = &radeon_atom_get_memory_clock, |
| 707,7 → 716,9 |
| .clear_surface_reg = r600_clear_surface_reg, |
| .bandwidth_update = &evergreen_bandwidth_update, |
| .hpd_init = &evergreen_hpd_init, |
| .hpd_fini = &evergreen_hpd_fini, |
| .hpd_sense = &evergreen_hpd_sense, |
| .hpd_set_polarity = &evergreen_hpd_set_polarity, |
| }; |
| static struct radeon_asic cayman_asic = { |
| 721,14 → 732,14 |
| .gart_tlb_flush = &cayman_pcie_gart_tlb_flush, |
| .gart_set_page = &rs600_gart_set_page, |
| .ring_test = &r600_ring_test, |
| // .ring_ib_execute = &r600_ring_ib_execute, |
| // .irq_set = &r600_irq_set, |
| // .irq_process = &r600_irq_process, |
| .ring_ib_execute = &evergreen_ring_ib_execute, |
| .irq_set = &evergreen_irq_set, |
| .irq_process = &evergreen_irq_process, |
| .fence_ring_emit = &r600_fence_ring_emit, |
| // .cs_parse = &r600_cs_parse, |
| // .copy_blit = &r600_copy_blit, |
| // .copy_dma = &r600_copy_blit, |
| // .copy = &r600_copy_blit, |
| // .cs_parse = &evergreen_cs_parse, |
| .copy_blit = &evergreen_copy_blit, |
| .copy_dma = &evergreen_copy_blit, |
| .copy = &evergreen_copy_blit, |
| .get_engine_clock = &radeon_atom_get_engine_clock, |
| .set_engine_clock = &radeon_atom_set_engine_clock, |
| .get_memory_clock = &radeon_atom_get_memory_clock, |
| 739,6 → 750,10 |
| .set_surface_reg = r600_set_surface_reg, |
| .clear_surface_reg = r600_clear_surface_reg, |
| .bandwidth_update = &evergreen_bandwidth_update, |
| .hpd_init = &evergreen_hpd_init, |
| .hpd_fini = &evergreen_hpd_fini, |
| .hpd_sense = &evergreen_hpd_sense, |
| .hpd_set_polarity = &evergreen_hpd_set_polarity, |
| }; |
| int radeon_asic_init(struct radeon_device *rdev) |
| /drivers/video/drm/radeon/radeon_benchmark.c |
|---|
| 0,0 → 1,185 |
| /* |
| * Copyright 2009 Jerome Glisse. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice shall be included in |
| * all copies or substantial portions of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| * OTHER DEALINGS IN THE SOFTWARE. |
| * |
| * Authors: Jerome Glisse |
| */ |
| #include <drm/drmP.h> |
| #include <drm/radeon_drm.h> |
| #include "radeon_reg.h" |
| #include "radeon.h" |
| unsigned int inline jiffies_to_msecs(const unsigned long j) |
| { |
| return (10 * j); |
| }; |
| void radeon_benchmark_move(struct radeon_device *rdev, unsigned bsize, |
| unsigned sdomain, unsigned ddomain) |
| { |
| struct radeon_bo *dobj = NULL; |
| struct radeon_bo *sobj = NULL; |
| struct radeon_fence *fence = NULL; |
| uint64_t saddr, daddr; |
| unsigned long start_jiffies; |
| unsigned long end_jiffies; |
| unsigned long time; |
| unsigned i, n, size; |
| int r; |
| ENTER(); |
| size = bsize; |
| n = 2; //1024; |
| dbgprintf("source domain %x\n", sdomain); |
| r = radeon_bo_create(rdev, size, PAGE_SIZE, true, sdomain, &sobj); |
| if (r) { |
| goto out_cleanup; |
| } |
| r = radeon_bo_reserve(sobj, false); |
| if (unlikely(r != 0)) |
| goto out_cleanup; |
| r = radeon_bo_pin(sobj, sdomain, &saddr); |
| // radeon_bo_unreserve(sobj); |
| if (r) { |
| goto out_cleanup; |
| } |
| dbgprintf("destination domain %x\n", ddomain); |
| r = radeon_bo_create(rdev, size, PAGE_SIZE, true, ddomain, &dobj); |
| if (r) { |
| goto out_cleanup; |
| } |
| r = radeon_bo_reserve(dobj, false); |
| if (unlikely(r != 0)) |
| goto out_cleanup; |
| r = radeon_bo_pin(dobj, ddomain, &daddr); |
| // radeon_bo_unreserve(dobj); |
| if (r) { |
| goto out_cleanup; |
| } |
| dbgprintf("done\n"); |
| /* r100 doesn't have dma engine so skip the test */ |
| if (rdev->asic->copy_dma) { |
| dbgprintf("copy dma\n"); |
| start_jiffies = GetTimerTicks(); |
| for (i = 0; i < n; i++) { |
| r = radeon_fence_create(rdev, &fence); |
| if (r) { |
| goto out_cleanup; |
| } |
| r = radeon_copy_dma(rdev, saddr, daddr, |
| size / RADEON_GPU_PAGE_SIZE, fence); |
| if (r) { |
| goto out_cleanup; |
| } |
| r = radeon_fence_wait(fence, false); |
| if (r) { |
| goto out_cleanup; |
| } |
| radeon_fence_unref(&fence); |
| } |
| end_jiffies = GetTimerTicks(); |
| time = end_jiffies - start_jiffies; |
| time = jiffies_to_msecs(time); |
| if (time > 0) { |
| i = ((n * size) >> 10) / time; |
| printk(KERN_INFO "radeon: dma %u bo moves of %ukb from" |
| " %d to %d in %lums (%ukb/ms %ukb/s %uM/s)\n", |
| n, size >> 10, |
| sdomain, ddomain, time, |
| i, i * 1000, (i * 1000) / 1024); |
| } |
| } |
| start_jiffies = GetTimerTicks(); |
| for (i = 0; i < n; i++) { |
| r = radeon_fence_create(rdev, &fence); |
| if (r) { |
| goto out_cleanup; |
| } |
| r = radeon_copy_blit(rdev, saddr, daddr, size / RADEON_GPU_PAGE_SIZE, fence); |
| if (r) { |
| goto out_cleanup; |
| } |
| r = radeon_fence_wait(fence, false); |
| if (r) { |
| goto out_cleanup; |
| } |
| radeon_fence_unref(&fence); |
| } |
| end_jiffies = GetTimerTicks(); |
| time = end_jiffies - start_jiffies; |
| time = jiffies_to_msecs(time); |
| if (time > 0) { |
| i = ((n * size) >> 10) / time; |
| printk(KERN_INFO "radeon: blit %u bo moves of %ukb from %d to %d" |
| " in %lums (%ukb/ms %ukb/s %uM/s)\n", n, size >> 10, |
| sdomain, ddomain, time, i, i * 1000, (i * 1000) / 1024); |
| } |
| out_cleanup: |
| dbgprintf("cleanup\n"); |
| if (sobj) { |
| r = radeon_bo_reserve(sobj, false); |
| if (likely(r == 0)) { |
| radeon_bo_unpin(sobj); |
| radeon_bo_unreserve(sobj); |
| } |
| radeon_bo_unref(&sobj); |
| } |
| if (dobj) { |
| r = radeon_bo_reserve(dobj, false); |
| if (likely(r == 0)) { |
| radeon_bo_unpin(dobj); |
| radeon_bo_unreserve(dobj); |
| } |
| radeon_bo_unref(&dobj); |
| } |
| if (fence) { |
| radeon_fence_unref(&fence); |
| } |
| if (r) { |
| printk(KERN_WARNING "Error while benchmarking BO move.\n"); |
| } |
| LEAVE(); |
| } |
| void radeon_benchmark(struct radeon_device *rdev) |
| { |
| radeon_benchmark_move(rdev, 8192*4096, RADEON_GEM_DOMAIN_GTT, |
| RADEON_GEM_DOMAIN_VRAM); |
| radeon_benchmark_move(rdev, 8192*4096, RADEON_GEM_DOMAIN_VRAM, |
| RADEON_GEM_DOMAIN_GTT); |
| radeon_benchmark_move(rdev, 8192*4096, RADEON_GEM_DOMAIN_VRAM, |
| RADEON_GEM_DOMAIN_VRAM); |
| } |
| /drivers/video/drm/radeon/radeon_bios.c |
|---|
| 332,7 → 332,7 |
| seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); |
| viph_control = RREG32(RADEON_VIPH_CONTROL); |
| bus_cntl = RREG32(RADEON_BUS_CNTL); |
| bus_cntl = RREG32(RV370_BUS_CNTL); |
| d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); |
| d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); |
| vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); |
| 351,7 → 351,7 |
| WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); |
| /* enable the rom */ |
| WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); |
| WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM)); |
| /* Disable VGA mode */ |
| WREG32(AVIVO_D1VGA_CONTROL, |
| 368,7 → 368,7 |
| /* restore regs */ |
| WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); |
| WREG32(RADEON_VIPH_CONTROL, viph_control); |
| WREG32(RADEON_BUS_CNTL, bus_cntl); |
| WREG32(RV370_BUS_CNTL, bus_cntl); |
| WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); |
| WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); |
| WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); |
| 391,6 → 391,9 |
| seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); |
| viph_control = RREG32(RADEON_VIPH_CONTROL); |
| if (rdev->flags & RADEON_IS_PCIE) |
| bus_cntl = RREG32(RV370_BUS_CNTL); |
| else |
| bus_cntl = RREG32(RADEON_BUS_CNTL); |
| crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL); |
| crtc2_gen_cntl = 0; |
| 413,6 → 416,9 |
| WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); |
| /* enable the rom */ |
| if (rdev->flags & RADEON_IS_PCIE) |
| WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM)); |
| else |
| WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); |
| /* Turn off mem requests and CRTC for both controllers */ |
| 440,6 → 446,9 |
| /* restore regs */ |
| WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); |
| WREG32(RADEON_VIPH_CONTROL, viph_control); |
| if (rdev->flags & RADEON_IS_PCIE) |
| WREG32(RV370_BUS_CNTL, bus_cntl); |
| else |
| WREG32(RADEON_BUS_CNTL, bus_cntl); |
| WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); |
| if (!(rdev->flags & RADEON_SINGLE_CRTC)) { |
| /drivers/video/drm/radeon/radeon_connectors.c |
|---|
| 52,6 → 52,12 |
| struct radeon_device *rdev = dev->dev_private; |
| struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
| /* bail if the connector does not have hpd pin, e.g., |
| * VGA, TV, etc. |
| */ |
| if (radeon_connector->hpd.hpd == RADEON_HPD_NONE) |
| return; |
| radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); |
| /* powering up/down the eDP panel generates hpd events which |
| /drivers/video/drm/radeon/radeon_device.c |
|---|
| 716,12 → 716,12 |
| mutex_init(&rdev->ib_pool.mutex); |
| mutex_init(&rdev->cp.mutex); |
| mutex_init(&rdev->dc_hw_i2c_mutex); |
| // if (rdev->family >= CHIP_R600) |
| // spin_lock_init(&rdev->ih.lock); |
| if (rdev->family >= CHIP_R600) |
| spin_lock_init(&rdev->ih.lock); |
| mutex_init(&rdev->gem.mutex); |
| mutex_init(&rdev->pm.mutex); |
| mutex_init(&rdev->vram_mutex); |
| // rwlock_init(&rdev->fence_drv.lock); |
| rwlock_init(&rdev->fence_drv.lock); |
| INIT_LIST_HEAD(&rdev->gem.objects); |
| /* Set asic functions */ |
| 793,9 → 793,9 |
| // if (radeon_testing) { |
| // radeon_test_moves(rdev); |
| // } |
| // if (radeon_benchmarking) { |
| // radeon_benchmark(rdev); |
| // } |
| if (radeon_benchmarking) { |
| radeon_benchmark(rdev); |
| } |
| return 0; |
| } |
| 1071,12 → 1071,6 |
| rdev = rdisplay->ddev->dev_private; |
| // if( (rdev->asic == &r600_asic) || |
| // (rdev->asic == &rv770_asic)) |
| // r600_2D_test(rdev); |
| // else if (rdev->asic != &evergreen_asic) |
| // r100_2D_test(rdev); |
| err = RegService("DISPLAY", display_handler); |
| if( err != 0) |
| /drivers/video/drm/radeon/radeon_fence.c |
|---|
| 101,14 → 101,13 |
| bool wake = false; |
| unsigned long cjiffies; |
| #if 0 |
| seq = radeon_fence_read(rdev); |
| if (seq != rdev->fence_drv.last_seq) { |
| rdev->fence_drv.last_seq = seq; |
| rdev->fence_drv.last_jiffies = jiffies; |
| // rdev->fence_drv.last_timeout = RADEON_FENCE_JIFFIES_TIMEOUT; |
| rdev->fence_drv.last_jiffies = GetTimerTicks(); |
| rdev->fence_drv.last_timeout = RADEON_FENCE_JIFFIES_TIMEOUT; |
| } else { |
| cjiffies = jiffies; |
| cjiffies = GetTimerTicks(); |
| if (time_after(cjiffies, rdev->fence_drv.last_jiffies)) { |
| cjiffies -= rdev->fence_drv.last_jiffies; |
| if (time_after(rdev->fence_drv.last_timeout, cjiffies)) { |
| 138,6 → 137,8 |
| } |
| /* all fence previous to this one are considered as signaled */ |
| if (n) { |
| kevent_t event; |
| event.code = -1; |
| i = n; |
| do { |
| n = i->prev; |
| 144,27 → 145,16 |
| list_move_tail(i, &rdev->fence_drv.signaled); |
| fence = list_entry(i, struct radeon_fence, list); |
| fence->signaled = true; |
| // dbgprintf("fence %x done\n", fence); |
| RaiseEvent(fence->evnt, 0, &event); |
| i = n; |
| } while (i != &rdev->fence_drv.emited); |
| wake = true; |
| } |
| #endif |
| return wake; |
| } |
| static void radeon_fence_destroy(struct kref *kref) |
| { |
| unsigned long irq_flags; |
| struct radeon_fence *fence; |
| fence = container_of(kref, struct radeon_fence, kref); |
| write_lock_irqsave(&fence->rdev->fence_drv.lock, irq_flags); |
| list_del(&fence->list); |
| fence->emited = false; |
| write_unlock_irqrestore(&fence->rdev->fence_drv.lock, irq_flags); |
| kfree(fence); |
| } |
| int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence) |
| { |
| unsigned long irq_flags; |
| 173,6 → 163,8 |
| if ((*fence) == NULL) { |
| return -ENOMEM; |
| } |
| (*fence)->evnt = CreateEvent(NULL, MANUAL_DESTROY); |
| // kref_init(&((*fence)->kref)); |
| (*fence)->rdev = rdev; |
| (*fence)->emited = false; |
| 231,8 → 223,6 |
| if (radeon_fence_signaled(fence)) { |
| return 0; |
| } |
| #if 0 |
| timeout = rdev->fence_drv.last_timeout; |
| retry: |
| /* save current sequence used to check for GPU lockup */ |
| 240,8 → 230,11 |
| // trace_radeon_fence_wait_begin(rdev->ddev, seq); |
| if (intr) { |
| radeon_irq_kms_sw_irq_get(rdev); |
| r = wait_event_interruptible_timeout(rdev->fence_drv.queue, |
| radeon_fence_signaled(fence), timeout); |
| // r = wait_event_interruptible_timeout(rdev->fence_drv.queue, |
| // radeon_fence_signaled(fence), timeout); |
| WaitEvent(fence->evnt); |
| radeon_irq_kms_sw_irq_put(rdev); |
| if (unlikely(r < 0)) { |
| return r; |
| 248,8 → 241,11 |
| } |
| } else { |
| radeon_irq_kms_sw_irq_get(rdev); |
| r = wait_event_timeout(rdev->fence_drv.queue, |
| radeon_fence_signaled(fence), timeout); |
| // r = wait_event_timeout(rdev->fence_drv.queue, |
| // radeon_fence_signaled(fence), timeout); |
| WaitEvent(fence->evnt); |
| radeon_irq_kms_sw_irq_put(rdev); |
| } |
| // trace_radeon_fence_wait_end(rdev->ddev, seq); |
| 272,20 → 268,21 |
| * as signaled for now |
| */ |
| rdev->gpu_lockup = true; |
| r = radeon_gpu_reset(rdev); |
| if (r) |
| return r; |
| radeon_fence_write(rdev, fence->seq); |
| rdev->gpu_lockup = false; |
| // r = radeon_gpu_reset(rdev); |
| // if (r) |
| // return r; |
| return true; |
| // radeon_fence_write(rdev, fence->seq); |
| // rdev->gpu_lockup = false; |
| } |
| // timeout = RADEON_FENCE_JIFFIES_TIMEOUT; |
| timeout = RADEON_FENCE_JIFFIES_TIMEOUT; |
| write_lock_irqsave(&rdev->fence_drv.lock, irq_flags); |
| // rdev->fence_drv.last_timeout = RADEON_FENCE_JIFFIES_TIMEOUT; |
| // rdev->fence_drv.last_jiffies = jiffies; |
| rdev->fence_drv.last_timeout = RADEON_FENCE_JIFFIES_TIMEOUT; |
| rdev->fence_drv.last_jiffies = GetTimerTicks(); |
| write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); |
| goto retry; |
| } |
| #endif |
| return 0; |
| } |
| 346,12 → 343,20 |
| void radeon_fence_unref(struct radeon_fence **fence) |
| { |
| unsigned long irq_flags; |
| struct radeon_fence *tmp = *fence; |
| *fence = NULL; |
| if(tmp) |
| { |
| write_lock_irqsave(&tmp->rdev->fence_drv.lock, irq_flags); |
| list_del(&tmp->list); |
| tmp->emited = false; |
| write_unlock_irqrestore(&tmp->rdev->fence_drv.lock, irq_flags); |
| }; |
| } |
| #if 0 |
| void radeon_fence_process(struct radeon_device *rdev) |
| { |
| unsigned long irq_flags; |
| 360,13 → 365,8 |
| write_lock_irqsave(&rdev->fence_drv.lock, irq_flags); |
| wake = radeon_fence_poll_locked(rdev); |
| write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); |
| if (wake) { |
| wake_up_all(&rdev->fence_drv.queue); |
| } |
| } |
| #endif |
| int radeon_fence_driver_init(struct radeon_device *rdev) |
| { |
| unsigned long irq_flags; |
| /drivers/video/drm/radeon/radeon_gart.c |
|---|
| 184,11 → 184,8 |
| uint64_t page_base; |
| int i, j; |
| ENTER(); |
| dbgprintf("offset %x pages %x list %x\n", |
| offset, pages, pagelist); |
| // dbgprintf("offset %x pages %d list %x\n", |
| // offset, pages, pagelist); |
| if (!rdev->gart.ready) { |
| WARN(1, "trying to bind memory to unitialized GART !\n"); |
| return -EINVAL; |
| /drivers/video/drm/radeon/radeon_irq_kms.c |
|---|
| 88,7 → 88,7 |
| void irq_handler_kms() |
| { |
| dbgprintf("%s\n",__FUNCTION__); |
| // dbgprintf("%s\n",__FUNCTION__); |
| radeon_irq_process(main_device); |
| } |
| /drivers/video/drm/radeon/radeon_object_kos.c |
|---|
| 136,6 → 136,8 |
| num_pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT; |
| size = num_pages << PAGE_SHIFT; |
| if (num_pages == 0) { |
| dbgprintf("Illegal buffer object size.\n"); |
| return -EINVAL; |
| /drivers/video/drm/radeon/radeon_reg.h |
|---|
| 300,6 → 300,8 |
| # define RADEON_BUS_READ_BURST (1 << 30) |
| #define RADEON_BUS_CNTL1 0x0034 |
| # define RADEON_BUS_WAIT_ON_LOCK_EN (1 << 4) |
| #define RV370_BUS_CNTL 0x004c |
| # define RV370_BUS_BIOS_DIS_ROM (1 << 2) |
| /* rv370/rv380, rv410, r423/r430/r480, r5xx */ |
| #define RADEON_MSI_REARM_EN 0x0160 |
| # define RV370_MSI_REARM_EN (1 << 0) |
| /drivers/video/drm/radeon/radeon_ring.c |
|---|
| 71,20 → 71,20 |
| } |
| rdev->ib_pool.head_id = (nib->idx + 1) & (RADEON_IB_POOL_SIZE - 1); |
| nib->free = false; |
| // if (nib->fence) { |
| // mutex_unlock(&rdev->ib_pool.mutex); |
| // r = radeon_fence_wait(nib->fence, false); |
| // if (r) { |
| // dev_err(rdev->dev, "error waiting fence of IB(%u:0x%016lX:%u)\n", |
| // nib->idx, (unsigned long)nib->gpu_addr, nib->length_dw); |
| // mutex_lock(&rdev->ib_pool.mutex); |
| // nib->free = true; |
| // mutex_unlock(&rdev->ib_pool.mutex); |
| // radeon_fence_unref(&fence); |
| // return r; |
| // } |
| // mutex_lock(&rdev->ib_pool.mutex); |
| // } |
| if (nib->fence) { |
| mutex_unlock(&rdev->ib_pool.mutex); |
| r = radeon_fence_wait(nib->fence, false); |
| if (r) { |
| dev_err(rdev->dev, "error waiting fence of IB(%u:0x%016lX:%u)\n", |
| nib->idx, (unsigned long)nib->gpu_addr, nib->length_dw); |
| mutex_lock(&rdev->ib_pool.mutex); |
| nib->free = true; |
| mutex_unlock(&rdev->ib_pool.mutex); |
| radeon_fence_unref(&fence); |
| return r; |
| } |
| mutex_lock(&rdev->ib_pool.mutex); |
| } |
| radeon_fence_unref(&nib->fence); |
| nib->fence = fence; |
| nib->length_dw = 0; |
| /drivers/video/drm/radeon/rs400.c |
|---|
| 400,8 → 400,14 |
| r = rs400_gart_enable(rdev); |
| if (r) |
| return r; |
| /* allocate wb buffer */ |
| r = radeon_wb_init(rdev); |
| if (r) |
| return r; |
| /* Enable IRQ */ |
| // r100_irq_set(rdev); |
| r100_irq_set(rdev); |
| rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
| /* 1M ring buffer */ |
| r = r100_cp_init(rdev, 1024 * 1024); |
| 409,11 → 415,11 |
| dev_err(rdev->dev, "failed initializing CP (%d).\n", r); |
| return r; |
| } |
| // r = r100_ib_init(rdev); |
| // if (r) { |
| // dev_err(rdev->dev, "failled initializing IB (%d).\n", r); |
| // return r; |
| // } |
| r = r100_ib_init(rdev); |
| if (r) { |
| dev_err(rdev->dev, "failed initializing IB (%d).\n", r); |
| return r; |
| } |
| return 0; |
| } |
| 462,12 → 468,12 |
| /* initialize memory controller */ |
| rs400_mc_init(rdev); |
| /* Fence driver */ |
| // r = radeon_fence_driver_init(rdev); |
| // if (r) |
| // return r; |
| // r = radeon_irq_kms_init(rdev); |
| // if (r) |
| // return r; |
| r = radeon_fence_driver_init(rdev); |
| if (r) |
| return r; |
| r = radeon_irq_kms_init(rdev); |
| if (r) |
| return r; |
| /* Memory manager */ |
| r = radeon_bo_init(rdev); |
| if (r) |
| /drivers/video/drm/radeon/rs600.c |
|---|
| 108,19 → 108,19 |
| case RADEON_HPD_1: |
| WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, |
| S_007D00_DC_HOT_PLUG_DETECT1_EN(1)); |
| // rdev->irq.hpd[0] = true; |
| rdev->irq.hpd[0] = true; |
| break; |
| case RADEON_HPD_2: |
| WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, |
| S_007D10_DC_HOT_PLUG_DETECT2_EN(1)); |
| // rdev->irq.hpd[1] = true; |
| rdev->irq.hpd[1] = true; |
| break; |
| default: |
| break; |
| } |
| } |
| // if (rdev->irq.installed) |
| // rs600_irq_set(rdev); |
| if (rdev->irq.installed) |
| rs600_irq_set(rdev); |
| } |
| void rs600_hpd_fini(struct radeon_device *rdev) |
| 134,12 → 134,12 |
| case RADEON_HPD_1: |
| WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL, |
| S_007D00_DC_HOT_PLUG_DETECT1_EN(0)); |
| // rdev->irq.hpd[0] = false; |
| rdev->irq.hpd[0] = false; |
| break; |
| case RADEON_HPD_2: |
| WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL, |
| S_007D10_DC_HOT_PLUG_DETECT2_EN(0)); |
| // rdev->irq.hpd[1] = false; |
| rdev->irq.hpd[1] = false; |
| break; |
| default: |
| break; |
| 257,7 → 257,7 |
| return radeon_gart_table_vram_alloc(rdev); |
| } |
| int rs600_gart_enable(struct radeon_device *rdev) |
| static int rs600_gart_enable(struct radeon_device *rdev) |
| { |
| u32 tmp; |
| int r, i; |
| 271,8 → 271,8 |
| return r; |
| radeon_gart_restore(rdev); |
| /* Enable bus master */ |
| tmp = RREG32(R_00004C_BUS_CNTL) & C_00004C_BUS_MASTER_DIS; |
| WREG32(R_00004C_BUS_CNTL, tmp); |
| tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; |
| WREG32(RADEON_BUS_CNTL, tmp); |
| /* FIXME: setup default page */ |
| WREG32_MC(R_000100_MC_PT0_CNTL, |
| (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) | |
| 365,8 → 365,6 |
| return 0; |
| } |
| #if 0 |
| int rs600_irq_set(struct radeon_device *rdev) |
| { |
| uint32_t tmp = 0; |
| 459,8 → 457,81 |
| rs600_irq_ack(rdev); |
| } |
| #endif |
| int rs600_irq_process(struct radeon_device *rdev) |
| { |
| u32 status, msi_rearm; |
| bool queue_hotplug = false; |
| /* reset gui idle ack. the status bit is broken */ |
| rdev->irq.gui_idle_acked = false; |
| status = rs600_irq_ack(rdev); |
| if (!status && !rdev->irq.stat_regs.r500.disp_int) { |
| return IRQ_NONE; |
| } |
| while (status || rdev->irq.stat_regs.r500.disp_int) { |
| /* SW interrupt */ |
| if (G_000044_SW_INT(status)) { |
| radeon_fence_process(rdev); |
| } |
| /* GUI idle */ |
| if (G_000040_GUI_IDLE(status)) { |
| rdev->irq.gui_idle_acked = true; |
| rdev->pm.gui_idle = true; |
| // wake_up(&rdev->irq.idle_queue); |
| } |
| /* Vertical blank interrupts */ |
| if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
| if (rdev->irq.crtc_vblank_int[0]) { |
| // drm_handle_vblank(rdev->ddev, 0); |
| rdev->pm.vblank_sync = true; |
| // wake_up(&rdev->irq.vblank_queue); |
| } |
| // if (rdev->irq.pflip[0]) |
| // radeon_crtc_handle_flip(rdev, 0); |
| } |
| if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
| if (rdev->irq.crtc_vblank_int[1]) { |
| // drm_handle_vblank(rdev->ddev, 1); |
| rdev->pm.vblank_sync = true; |
| // wake_up(&rdev->irq.vblank_queue); |
| } |
| // if (rdev->irq.pflip[1]) |
| // radeon_crtc_handle_flip(rdev, 1); |
| } |
| if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
| queue_hotplug = true; |
| DRM_DEBUG("HPD1\n"); |
| } |
| if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { |
| queue_hotplug = true; |
| DRM_DEBUG("HPD2\n"); |
| } |
| status = rs600_irq_ack(rdev); |
| } |
| /* reset gui idle ack. the status bit is broken */ |
| rdev->irq.gui_idle_acked = false; |
| // if (queue_hotplug) |
| // schedule_work(&rdev->hotplug_work); |
| if (rdev->msi_enabled) { |
| switch (rdev->family) { |
| case CHIP_RS600: |
| case CHIP_RS690: |
| case CHIP_RS740: |
| msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM; |
| WREG32(RADEON_BUS_CNTL, msi_rearm); |
| WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM); |
| break; |
| default: |
| msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN; |
| WREG32(RADEON_MSI_REARM_EN, msi_rearm); |
| WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN); |
| break; |
| } |
| } |
| return IRQ_HANDLED; |
| } |
| u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc) |
| { |
| if (crtc == 0) |
| 602,8 → 673,14 |
| r = rs600_gart_enable(rdev); |
| if (r) |
| return r; |
| /* allocate wb buffer */ |
| r = radeon_wb_init(rdev); |
| if (r) |
| return r; |
| /* Enable IRQ */ |
| // rs600_irq_set(rdev); |
| rs600_irq_set(rdev); |
| rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
| /* 1M ring buffer */ |
| r = r100_cp_init(rdev, 1024 * 1024); |
| 611,11 → 688,11 |
| dev_err(rdev->dev, "failed initializing CP (%d).\n", r); |
| return r; |
| } |
| // r = r100_ib_init(rdev); |
| // if (r) { |
| // dev_err(rdev->dev, "failled initializing IB (%d).\n", r); |
| // return r; |
| // } |
| r = r100_ib_init(rdev); |
| if (r) { |
| dev_err(rdev->dev, "failed initializing IB (%d).\n", r); |
| return r; |
| } |
| return 0; |
| } |
| 663,12 → 740,12 |
| rs600_mc_init(rdev); |
| rs600_debugfs(rdev); |
| /* Fence driver */ |
| // r = radeon_fence_driver_init(rdev); |
| // if (r) |
| // return r; |
| // r = radeon_irq_kms_init(rdev); |
| // if (r) |
| // return r; |
| r = radeon_fence_driver_init(rdev); |
| if (r) |
| return r; |
| r = radeon_irq_kms_init(rdev); |
| if (r) |
| return r; |
| /* Memory manager */ |
| r = radeon_bo_init(rdev); |
| if (r) |
| /drivers/video/drm/radeon/rs690.c |
|---|
| 615,8 → 615,14 |
| r = rs400_gart_enable(rdev); |
| if (r) |
| return r; |
| /* allocate wb buffer */ |
| r = radeon_wb_init(rdev); |
| if (r) |
| return r; |
| /* Enable IRQ */ |
| // rs600_irq_set(rdev); |
| rs600_irq_set(rdev); |
| rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
| /* 1M ring buffer */ |
| r = r100_cp_init(rdev, 1024 * 1024); |
| 624,11 → 630,11 |
| dev_err(rdev->dev, "failed initializing CP (%d).\n", r); |
| return r; |
| } |
| // r = r100_ib_init(rdev); |
| // if (r) { |
| // dev_err(rdev->dev, "failled initializing IB (%d).\n", r); |
| // return r; |
| // } |
| r = r100_ib_init(rdev); |
| if (r) { |
| dev_err(rdev->dev, "failed initializing IB (%d).\n", r); |
| return r; |
| } |
| return 0; |
| } |
| 678,12 → 684,12 |
| rs690_mc_init(rdev); |
| rv515_debugfs(rdev); |
| /* Fence driver */ |
| // r = radeon_fence_driver_init(rdev); |
| // if (r) |
| // return r; |
| // r = radeon_irq_kms_init(rdev); |
| // if (r) |
| // return r; |
| r = radeon_fence_driver_init(rdev); |
| if (r) |
| return r; |
| r = radeon_irq_kms_init(rdev); |
| if (r) |
| return r; |
| /* Memory manager */ |
| r = radeon_bo_init(rdev); |
| if (r) |
| /drivers/video/drm/radeon/rv515.c |
|---|
| 386,8 → 386,14 |
| if (r) |
| return r; |
| } |
| /* allocate wb buffer */ |
| r = radeon_wb_init(rdev); |
| if (r) |
| return r; |
| /* Enable IRQ */ |
| // rs600_irq_set(rdev); |
| rs600_irq_set(rdev); |
| rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
| /* 1M ring buffer */ |
| r = r100_cp_init(rdev, 1024 * 1024); |
| 395,11 → 401,11 |
| dev_err(rdev->dev, "failed initializing CP (%d).\n", r); |
| return r; |
| } |
| // r = r100_ib_init(rdev); |
| // if (r) { |
| // dev_err(rdev->dev, "failled initializing IB (%d).\n", r); |
| // return r; |
| // } |
| r = r100_ib_init(rdev); |
| if (r) { |
| dev_err(rdev->dev, "failed initializing IB (%d).\n", r); |
| return r; |
| } |
| return 0; |
| } |
| 457,12 → 463,12 |
| rv515_mc_init(rdev); |
| rv515_debugfs(rdev); |
| /* Fence driver */ |
| // r = radeon_fence_driver_init(rdev); |
| // if (r) |
| // return r; |
| // r = radeon_irq_kms_init(rdev); |
| // if (r) |
| // return r; |
| r = radeon_fence_driver_init(rdev); |
| if (r) |
| return r; |
| r = radeon_irq_kms_init(rdev); |
| if (r) |
| return r; |
| /* Memory manager */ |
| r = radeon_bo_init(rdev); |
| if (r) |
| /drivers/video/drm/radeon/rv770.c |
|---|
| 1088,6 → 1088,13 |
| if (r) |
| return r; |
| rv770_gpu_init(rdev); |
| r = r600_blit_init(rdev); |
| if (r) { |
| // r600_blit_fini(rdev); |
| rdev->asic->copy = NULL; |
| dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); |
| } |
| /* allocate wb buffer */ |
| r = radeon_wb_init(rdev); |
| if (r) |