/drivers/video/Intel-2D/pixlib2.c |
---|
File deleted |
/drivers/video/Intel-2D/intel_driver.h |
---|
116,9 → 116,7 |
int gen; |
}; |
//void intel_detect_chipset(ScrnInfoPtr scrn, |
// EntityInfoPtr ent, |
// struct pci_device *pci); |
const struct intel_device_info *intel_detect_chipset(struct pci_device *pci); |
#endif /* INTEL_DRIVER_H */ |
/drivers/video/Intel-2D/pciaccess.h |
---|
0,0 → 1,537 |
/* |
* (C) Copyright IBM Corporation 2006 |
* Copyright 2009 Red Hat, Inc. |
* All Rights Reserved. |
* |
* Permission is hereby granted, free of charge, to any person obtaining a |
* copy of this software and associated documentation files (the "Software"), |
* to deal in the Software without restriction, including without limitation |
* on the rights to use, copy, modify, merge, publish, distribute, sub |
* license, and/or sell copies of the Software, and to permit persons to whom |
* the Software is furnished to do so, subject to the following conditions: |
* |
* The above copyright notice and this permission notice (including the next |
* paragraph) shall be included in all copies or substantial portions of the |
* Software. |
* |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
* IBM AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
* DEALINGS IN THE SOFTWARE. |
*/ |
/* |
* Copyright (c) 2007 Paulo R. Zanoni, Tiago Vignatti |
* |
* Permission is hereby granted, free of charge, to any person |
* obtaining a copy of this software and associated documentation |
* files (the "Software"), to deal in the Software without |
* restriction, including without limitation the rights to use, |
* copy, modify, merge, publish, distribute, sublicense, and/or sell |
* copies of the Software, and to permit persons to whom the |
* Software is furnished to do so, subject to the following |
* conditions: |
* |
* The above copyright notice and this permission notice shall be |
* included in all copies or substantial portions of the Software. |
* |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES |
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT |
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
* OTHER DEALINGS IN THE SOFTWARE. |
* |
*/ |
/** |
* \file pciaccess.h |
* |
* \author Ian Romanick <idr@us.ibm.com> |
*/ |
#ifndef PCIACCESS_H |
#define PCIACCESS_H |
#include <inttypes.h> |
#if __GNUC__ >= 3 |
#define __deprecated __attribute__((deprecated)) |
#else |
#define __deprecated |
#endif |
typedef uint64_t pciaddr_t; |
struct pci_device; |
struct pci_device_iterator; |
struct pci_id_match; |
struct pci_slot_match; |
#ifdef __cplusplus |
extern "C" { |
#endif |
int pci_device_has_kernel_driver(struct pci_device *dev); |
int pci_device_is_boot_vga(struct pci_device *dev); |
int pci_device_read_rom(struct pci_device *dev, void *buffer); |
int __deprecated pci_device_map_region(struct pci_device *dev, |
unsigned region, int write_enable); |
int __deprecated pci_device_unmap_region(struct pci_device *dev, |
unsigned region); |
int pci_device_map_range(struct pci_device *dev, pciaddr_t base, |
pciaddr_t size, unsigned map_flags, void **addr); |
int pci_device_unmap_range(struct pci_device *dev, void *memory, |
pciaddr_t size); |
int __deprecated pci_device_map_memory_range(struct pci_device *dev, |
pciaddr_t base, pciaddr_t size, int write_enable, void **addr); |
int __deprecated pci_device_unmap_memory_range(struct pci_device *dev, |
void *memory, pciaddr_t size); |
int pci_device_probe(struct pci_device *dev); |
const struct pci_agp_info *pci_device_get_agp_info(struct pci_device *dev); |
const struct pci_bridge_info *pci_device_get_bridge_info( |
struct pci_device *dev); |
const struct pci_pcmcia_bridge_info *pci_device_get_pcmcia_bridge_info( |
struct pci_device *dev); |
int pci_device_get_bridge_buses(struct pci_device *dev, int *primary_bus, |
int *secondary_bus, int *subordinate_bus); |
int pci_system_init(void); |
void pci_system_init_dev_mem(int fd); |
void pci_system_cleanup(void); |
struct pci_device_iterator *pci_slot_match_iterator_create( |
const struct pci_slot_match *match); |
struct pci_device_iterator *pci_id_match_iterator_create( |
const struct pci_id_match *match); |
void pci_iterator_destroy(struct pci_device_iterator *iter); |
struct pci_device *pci_device_next(struct pci_device_iterator *iter); |
struct pci_device *pci_device_find_by_slot(uint32_t domain, uint32_t bus, |
uint32_t dev, uint32_t func); |
struct pci_device *pci_device_get_parent_bridge(struct pci_device *dev); |
void pci_get_strings(const struct pci_id_match *m, |
const char **device_name, const char **vendor_name, |
const char **subdevice_name, const char **subvendor_name); |
const char *pci_device_get_device_name(const struct pci_device *dev); |
const char *pci_device_get_subdevice_name(const struct pci_device *dev); |
const char *pci_device_get_vendor_name(const struct pci_device *dev); |
const char *pci_device_get_subvendor_name(const struct pci_device *dev); |
void pci_device_enable(struct pci_device *dev); |
int pci_device_cfg_read (struct pci_device *dev, void *data, |
pciaddr_t offset, pciaddr_t size, pciaddr_t *bytes_read); |
int pci_device_cfg_read_u8 (struct pci_device *dev, uint8_t *data, |
pciaddr_t offset); |
int pci_device_cfg_read_u16(struct pci_device *dev, uint16_t *data, |
pciaddr_t offset); |
int pci_device_cfg_read_u32(struct pci_device *dev, uint32_t *data, |
pciaddr_t offset); |
int pci_device_cfg_write (struct pci_device *dev, const void *data, |
pciaddr_t offset, pciaddr_t size, pciaddr_t *bytes_written); |
int pci_device_cfg_write_u8 (struct pci_device *dev, uint8_t data, |
pciaddr_t offset); |
int pci_device_cfg_write_u16(struct pci_device *dev, uint16_t data, |
pciaddr_t offset); |
int pci_device_cfg_write_u32(struct pci_device *dev, uint32_t data, |
pciaddr_t offset); |
int pci_device_cfg_write_bits(struct pci_device *dev, uint32_t mask, |
uint32_t data, pciaddr_t offset); |
#ifdef __cplusplus |
} |
#endif |
/** |
* \name Mapping flags passed to \c pci_device_map_range |
*/ |
/*@{*/ |
#define PCI_DEV_MAP_FLAG_WRITABLE (1U<<0) |
#define PCI_DEV_MAP_FLAG_WRITE_COMBINE (1U<<1) |
#define PCI_DEV_MAP_FLAG_CACHABLE (1U<<2) |
/*@}*/ |
#define PCI_MATCH_ANY (~0) |
/** |
* Compare two PCI ID values (either vendor or device). This is used |
* internally to compare the fields of \c pci_id_match to the fields of |
* \c pci_device. |
*/ |
#define PCI_ID_COMPARE(a, b) \ |
(((a) == PCI_MATCH_ANY) || ((a) == (b))) |
/** |
*/ |
struct pci_id_match { |
/** |
* \name Device / vendor matching controls |
* |
* Control the search based on the device, vendor, subdevice, or subvendor |
* IDs. Setting any of these fields to \c PCI_MATCH_ANY will cause the |
* field to not be used in the comparison. |
*/ |
/*@{*/ |
uint32_t vendor_id; |
uint32_t device_id; |
uint32_t subvendor_id; |
uint32_t subdevice_id; |
/*@}*/ |
/** |
* \name Device class matching controls |
* |
*/ |
/*@{*/ |
uint32_t device_class; |
uint32_t device_class_mask; |
/*@}*/ |
intptr_t match_data; |
}; |
/** |
*/ |
struct pci_slot_match { |
/** |
* \name Device slot matching controls |
* |
* Control the search based on the domain, bus, slot, and function of |
* the device. Setting any of these fields to \c PCI_MATCH_ANY will cause |
* the field to not be used in the comparison. |
*/ |
/*@{*/ |
uint32_t domain; |
uint32_t bus; |
uint32_t dev; |
uint32_t func; |
/*@}*/ |
intptr_t match_data; |
}; |
/** |
* BAR descriptor for a PCI device. |
*/ |
struct pci_mem_region { |
/** |
* When the region is mapped, this is the pointer to the memory. |
* |
* This field is \b only set when the deprecated \c pci_device_map_region |
* interface is used. Use \c pci_device_map_range instead. |
* |
* \deprecated |
*/ |
void *memory; |
/** |
* Base physical address of the region within its bus / domain. |
* |
* \warning |
* This address is really only useful to other devices in the same |
* domain. It's probably \b not the address applications will ever |
* use. |
* |
* \warning |
* Most (all?) platform back-ends leave this field unset. |
*/ |
pciaddr_t bus_addr; |
/** |
* Base physical address of the region from the CPU's point of view. |
* |
* This address is typically passed to \c pci_device_map_range to create |
* a mapping of the region to the CPU's virtual address space. |
*/ |
pciaddr_t base_addr; |
/** |
* Size, in bytes, of the region. |
*/ |
pciaddr_t size; |
/** |
* Is the region I/O ports or memory? |
*/ |
unsigned is_IO:1; |
/** |
* Is the memory region prefetchable? |
* |
* \note |
* This can only be set if \c is_IO is not set. |
*/ |
unsigned is_prefetchable:1; |
/** |
* Is the memory at a 64-bit address? |
* |
* \note |
* This can only be set if \c is_IO is not set. |
*/ |
unsigned is_64:1; |
}; |
/** |
* PCI device. |
* |
* Contains all of the information about a particular PCI device. |
*/ |
struct pci_device { |
/** |
* \name Device bus identification. |
* |
* Complete bus identification, including domain, of the device. On |
* platforms that do not support PCI domains (e.g., 32-bit x86 hardware), |
* the domain will always be zero. |
*/ |
/*@{*/ |
uint16_t domain; |
uint8_t bus; |
uint8_t dev; |
uint8_t func; |
/*@}*/ |
/** |
* \name Vendor / device ID |
* |
* The vendor ID, device ID, and sub-IDs for the device. |
*/ |
/*@{*/ |
uint16_t vendor_id; |
uint16_t device_id; |
uint16_t subvendor_id; |
uint16_t subdevice_id; |
/*@}*/ |
/** |
* Device's class, subclass, and programming interface packed into a |
* single 32-bit value. The class is at bits [23:16], subclass is at |
* bits [15:8], and programming interface is at [7:0]. |
*/ |
uint32_t device_class; |
/** |
* Device revision number, as read from the configuration header. |
*/ |
uint8_t revision; |
/** |
* BAR descriptors for the device. |
*/ |
struct pci_mem_region regions[6]; |
/** |
* Size, in bytes, of the device's expansion ROM. |
*/ |
pciaddr_t rom_size; |
/** |
* IRQ associated with the device. If there is no IRQ, this value will |
* be -1. |
*/ |
int irq; |
/** |
* Storage for user data. Users of the library can store arbitrary |
* data in this pointer. The library will not use it for any purpose. |
* It is the user's responsability to free this memory before destroying |
* the \c pci_device structure. |
*/ |
intptr_t user_data; |
/** |
* Used by the VGA arbiter. Type of resource decoded by the device and |
* the file descriptor (/dev/vga_arbiter). */ |
int vgaarb_rsrc; |
}; |
/** |
* Description of the AGP capability of the device. |
* |
* \sa pci_device_get_agp_info |
*/ |
struct pci_agp_info { |
/** |
* Offset of the AGP registers in the devices configuration register |
* space. This is generally used so that the offset of the AGP command |
* register can be determined. |
*/ |
unsigned config_offset; |
/** |
* \name AGP major / minor version. |
*/ |
/*@{*/ |
uint8_t major_version; |
uint8_t minor_version; |
/*@}*/ |
/** |
* Logical OR of the supported AGP rates. For example, a value of 0x07 |
* means that the device can support 1x, 2x, and 4x. A value of 0x0c |
* means that the device can support 8x and 4x. |
*/ |
uint8_t rates; |
unsigned int fast_writes:1; /**< Are fast-writes supported? */ |
unsigned int addr64:1; |
unsigned int htrans:1; |
unsigned int gart64:1; |
unsigned int coherent:1; |
unsigned int sideband:1; /**< Is side-band addressing supported? */ |
unsigned int isochronus:1; |
uint8_t async_req_size; |
uint8_t calibration_cycle_timing; |
uint8_t max_requests; |
}; |
/** |
* Description of a PCI-to-PCI bridge device. |
* |
* \sa pci_device_get_bridge_info |
*/ |
struct pci_bridge_info { |
uint8_t primary_bus; |
uint8_t secondary_bus; |
uint8_t subordinate_bus; |
uint8_t secondary_latency_timer; |
uint8_t io_type; |
uint8_t mem_type; |
uint8_t prefetch_mem_type; |
uint16_t secondary_status; |
uint16_t bridge_control; |
uint32_t io_base; |
uint32_t io_limit; |
uint32_t mem_base; |
uint32_t mem_limit; |
uint64_t prefetch_mem_base; |
uint64_t prefetch_mem_limit; |
}; |
/** |
* Description of a PCI-to-PCMCIA bridge device. |
* |
* \sa pci_device_get_pcmcia_bridge_info |
*/ |
struct pci_pcmcia_bridge_info { |
uint8_t primary_bus; |
uint8_t card_bus; |
uint8_t subordinate_bus; |
uint8_t cardbus_latency_timer; |
uint16_t secondary_status; |
uint16_t bridge_control; |
struct { |
uint32_t base; |
uint32_t limit; |
} io[2]; |
struct { |
uint32_t base; |
uint32_t limit; |
} mem[2]; |
}; |
/** |
* VGA Arbiter definitions, functions and related. |
*/ |
/* Legacy VGA regions */ |
#define VGA_ARB_RSRC_NONE 0x00 |
#define VGA_ARB_RSRC_LEGACY_IO 0x01 |
#define VGA_ARB_RSRC_LEGACY_MEM 0x02 |
/* Non-legacy access */ |
#define VGA_ARB_RSRC_NORMAL_IO 0x04 |
#define VGA_ARB_RSRC_NORMAL_MEM 0x08 |
int pci_device_vgaarb_init (void); |
void pci_device_vgaarb_fini (void); |
int pci_device_vgaarb_set_target (struct pci_device *dev); |
/* use the targetted device */ |
int pci_device_vgaarb_decodes (int new_vga_rsrc); |
int pci_device_vgaarb_lock (void); |
int pci_device_vgaarb_trylock (void); |
int pci_device_vgaarb_unlock (void); |
/* return the current device count + resource decodes for the device */ |
int pci_device_vgaarb_get_info (struct pci_device *dev, int *vga_count, int *rsrc_decodes); |
/* |
* I/O space access. |
*/ |
struct pci_io_handle; |
struct pci_io_handle *pci_device_open_io(struct pci_device *dev, pciaddr_t base, |
pciaddr_t size); |
struct pci_io_handle *pci_legacy_open_io(struct pci_device *dev, pciaddr_t base, |
pciaddr_t size); |
void pci_device_close_io(struct pci_device *dev, struct pci_io_handle *handle); |
uint32_t pci_io_read32(struct pci_io_handle *handle, uint32_t reg); |
uint16_t pci_io_read16(struct pci_io_handle *handle, uint32_t reg); |
uint8_t pci_io_read8(struct pci_io_handle *handle, uint32_t reg); |
void pci_io_write32(struct pci_io_handle *handle, uint32_t reg, uint32_t data); |
void pci_io_write16(struct pci_io_handle *handle, uint32_t reg, uint16_t data); |
void pci_io_write8(struct pci_io_handle *handle, uint32_t reg, uint8_t data); |
/* |
* Legacy memory access |
*/ |
int pci_device_map_legacy(struct pci_device *dev, pciaddr_t base, |
pciaddr_t size, unsigned map_flags, void **addr); |
int pci_device_unmap_legacy(struct pci_device *dev, void *addr, pciaddr_t size); |
#endif /* PCIACCESS_H */ |
/drivers/video/Intel-2D/picture.h |
---|
0,0 → 1,320 |
/* |
* |
* Copyright © 2000 SuSE, Inc. |
* |
* Permission to use, copy, modify, distribute, and sell this software and its |
* documentation for any purpose is hereby granted without fee, provided that |
* the above copyright notice appear in all copies and that both that |
* copyright notice and this permission notice appear in supporting |
* documentation, and that the name of SuSE not be used in advertising or |
* publicity pertaining to distribution of the software without specific, |
* written prior permission. SuSE makes no representations about the |
* suitability of this software for any purpose. It is provided "as is" |
* without express or implied warranty. |
* |
* SuSE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING ALL |
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL SuSE |
* BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION |
* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN |
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
* |
* Author: Keith Packard, SuSE, Inc. |
*/ |
#ifndef _PICTURE_H_ |
#define _PICTURE_H_ |
//#include "privates.h" |
#include <pixman.h> |
typedef unsigned long Picture; |
typedef unsigned long PictFormat; |
typedef struct _Pixmap *PixmapPtr; |
typedef struct _Picture *PicturePtr; |
typedef struct _Drawable *DrawablePtr; |
typedef struct _PictFormat *PictFormatPtr; |
typedef struct pixman_transform PictTransform, *PictTransformPtr; |
typedef struct _Private PrivateRec, *PrivatePtr; |
/* |
* While the protocol is generous in format support, the |
* sample implementation allows only packed RGB and GBR |
* representations for data to simplify software rendering, |
*/ |
#define PICT_FORMAT(bpp,type,a,r,g,b) PIXMAN_FORMAT(bpp, type, a, r, g, b) |
/* |
* gray/color formats use a visual index instead of argb |
*/ |
#define PICT_VISFORMAT(bpp,type,vi) (((bpp) << 24) | \ |
((type) << 16) | \ |
((vi))) |
#define PICT_FORMAT_BPP(f) PIXMAN_FORMAT_BPP(f) |
#define PICT_FORMAT_TYPE(f) PIXMAN_FORMAT_TYPE(f) |
#define PICT_FORMAT_A(f) PIXMAN_FORMAT_A(f) |
#define PICT_FORMAT_R(f) PIXMAN_FORMAT_R(f) |
#define PICT_FORMAT_G(f) PIXMAN_FORMAT_G(f) |
#define PICT_FORMAT_B(f) PIXMAN_FORMAT_B(f) |
#define PICT_FORMAT_RGB(f) PIXMAN_FORMAT_RGB(f) |
#define PICT_FORMAT_VIS(f) PIXMAN_FORMAT_VIS(f) |
#define PICT_TYPE_OTHER PIXMAN_TYPE_OTHER |
#define PICT_TYPE_A PIXMAN_TYPE_A |
#define PICT_TYPE_ARGB PIXMAN_TYPE_ARGB |
#define PICT_TYPE_ABGR PIXMAN_TYPE_ABGR |
#define PICT_TYPE_COLOR PIXMAN_TYPE_COLOR |
#define PICT_TYPE_GRAY PIXMAN_TYPE_GRAY |
#define PICT_TYPE_BGRA PIXMAN_TYPE_BGRA |
#define PICT_FORMAT_COLOR(f) PIXMAN_FORMAT_COLOR(f) |
/* 32bpp formats */ |
typedef enum _PictFormatShort { |
PICT_a2r10g10b10 = PIXMAN_a2r10g10b10, |
PICT_x2r10g10b10 = PIXMAN_x2r10g10b10, |
PICT_a2b10g10r10 = PIXMAN_a2b10g10r10, |
PICT_x2b10g10r10 = PIXMAN_x2b10g10r10, |
PICT_a8r8g8b8 = PIXMAN_a8r8g8b8, |
PICT_x8r8g8b8 = PIXMAN_x8r8g8b8, |
PICT_a8b8g8r8 = PIXMAN_a8b8g8r8, |
PICT_x8b8g8r8 = PIXMAN_x8b8g8r8, |
PICT_b8g8r8a8 = PIXMAN_b8g8r8a8, |
PICT_b8g8r8x8 = PIXMAN_b8g8r8x8, |
/* 24bpp formats */ |
PICT_r8g8b8 = PIXMAN_r8g8b8, |
PICT_b8g8r8 = PIXMAN_b8g8r8, |
/* 16bpp formats */ |
PICT_r5g6b5 = PIXMAN_r5g6b5, |
PICT_b5g6r5 = PIXMAN_b5g6r5, |
PICT_a1r5g5b5 = PIXMAN_a1r5g5b5, |
PICT_x1r5g5b5 = PIXMAN_x1r5g5b5, |
PICT_a1b5g5r5 = PIXMAN_a1b5g5r5, |
PICT_x1b5g5r5 = PIXMAN_x1b5g5r5, |
PICT_a4r4g4b4 = PIXMAN_a4r4g4b4, |
PICT_x4r4g4b4 = PIXMAN_x4r4g4b4, |
PICT_a4b4g4r4 = PIXMAN_a4b4g4r4, |
PICT_x4b4g4r4 = PIXMAN_x4b4g4r4, |
/* 8bpp formats */ |
PICT_a8 = PIXMAN_a8, |
PICT_r3g3b2 = PIXMAN_r3g3b2, |
PICT_b2g3r3 = PIXMAN_b2g3r3, |
PICT_a2r2g2b2 = PIXMAN_a2r2g2b2, |
PICT_a2b2g2r2 = PIXMAN_a2b2g2r2, |
PICT_c8 = PIXMAN_c8, |
PICT_g8 = PIXMAN_g8, |
PICT_x4a4 = PIXMAN_x4a4, |
PICT_x4c4 = PIXMAN_x4c4, |
PICT_x4g4 = PIXMAN_x4g4, |
/* 4bpp formats */ |
PICT_a4 = PIXMAN_a4, |
PICT_r1g2b1 = PIXMAN_r1g2b1, |
PICT_b1g2r1 = PIXMAN_b1g2r1, |
PICT_a1r1g1b1 = PIXMAN_a1r1g1b1, |
PICT_a1b1g1r1 = PIXMAN_a1b1g1r1, |
PICT_c4 = PIXMAN_c4, |
PICT_g4 = PIXMAN_g4, |
/* 1bpp formats */ |
PICT_a1 = PIXMAN_a1, |
PICT_g1 = PIXMAN_g1 |
} PictFormatShort; |
/* |
* For dynamic indexed visuals (GrayScale and PseudoColor), these control the |
* selection of colors allocated for drawing to Pictures. The default |
* policy depends on the size of the colormap: |
* |
* Size Default Policy |
* ---------------------------- |
* < 64 PolicyMono |
* < 256 PolicyGray |
* 256 PolicyColor (only on PseudoColor) |
* |
* The actual allocation code lives in miindex.c, and so is |
* austensibly server dependent, but that code does: |
* |
* PolicyMono Allocate no additional colors, use black and white |
* PolicyGray Allocate 13 gray levels (11 cells used) |
* PolicyColor Allocate a 4x4x4 cube and 13 gray levels (71 cells used) |
* PolicyAll Allocate as big a cube as possible, fill with gray (all) |
* |
* Here's a picture to help understand how many colors are |
* actually allocated (this is just the gray ramp): |
* |
* gray level |
* all 0000 1555 2aaa 4000 5555 6aaa 8000 9555 aaaa bfff d555 eaaa ffff |
* b/w 0000 ffff |
* 4x4x4 5555 aaaa |
* extra 1555 2aaa 4000 6aaa 8000 9555 bfff d555 eaaa |
* |
* The default colormap supplies two gray levels (black/white), the |
* 4x4x4 cube allocates another two and nine more are allocated to fill |
* in the 13 levels. When the 4x4x4 cube is not allocated, a total of |
* 11 cells are allocated. |
*/ |
#define PictureCmapPolicyInvalid -1 |
#define PictureCmapPolicyDefault 0 |
#define PictureCmapPolicyMono 1 |
#define PictureCmapPolicyGray 2 |
#define PictureCmapPolicyColor 3 |
#define PictureCmapPolicyAll 4 |
//extern _X_EXPORT int PictureCmapPolicy; |
//extern _X_EXPORT int PictureParseCmapPolicy(const char *name); |
//extern _X_EXPORT int RenderErrBase; |
/* Fixed point updates from Carl Worth, USC, Information Sciences Institute */ |
typedef pixman_fixed_32_32_t xFixed_32_32; |
typedef pixman_fixed_48_16_t xFixed_48_16; |
#define MAX_FIXED_48_16 pixman_max_fixed_48_16 |
#define MIN_FIXED_48_16 pixman_min_fixed_48_16 |
typedef pixman_fixed_1_31_t xFixed_1_31; |
typedef pixman_fixed_1_16_t xFixed_1_16; |
typedef pixman_fixed_16_16_t xFixed_16_16; |
/* |
* An unadorned "xFixed" is the same as xFixed_16_16, |
* (since it's quite common in the code) |
*/ |
typedef pixman_fixed_t xFixed; |
#define XFIXED_BITS 16 |
#define xFixedToInt(f) pixman_fixed_to_int(f) |
#define IntToxFixed(i) pixman_int_to_fixed(i) |
#define xFixedE pixman_fixed_e |
#define xFixed1 pixman_fixed_1 |
#define xFixed1MinusE pixman_fixed_1_minus_e |
#define xFixedFrac(f) pixman_fixed_frac(f) |
#define xFixedFloor(f) pixman_fixed_floor(f) |
#define xFixedCeil(f) pixman_fixed_ceil(f) |
#define xFixedFraction(f) pixman_fixed_fraction(f) |
#define xFixedMod2(f) pixman_fixed_mod2(f) |
/* whether 't' is a well defined not obviously empty trapezoid */ |
#define xTrapezoidValid(t) ((t)->left.p1.y != (t)->left.p2.y && \ |
(t)->right.p1.y != (t)->right.p2.y && \ |
(int) ((t)->bottom - (t)->top) > 0) |
/* |
* Standard NTSC luminance conversions: |
* |
* y = r * 0.299 + g * 0.587 + b * 0.114 |
* |
* Approximate this for a bit more speed: |
* |
* y = (r * 153 + g * 301 + b * 58) / 512 |
* |
* This gives 17 bits of luminance; to get 15 bits, lop the low two |
*/ |
#define CvtR8G8B8toY15(s) (((((s) >> 16) & 0xff) * 153 + \ |
(((s) >> 8) & 0xff) * 301 + \ |
(((s) ) & 0xff) * 58) >> 2) |
typedef struct _Drawable { |
unsigned char type; /* DRAWABLE_<type> */ |
unsigned char class; /* specific to type */ |
unsigned char depth; |
unsigned char bitsPerPixel; |
unsigned int id; /* resource id */ |
short x; /* window: screen absolute, pixmap: 0 */ |
short y; /* window: screen absolute, pixmap: 0 */ |
unsigned short width; |
unsigned short height; |
} DrawableRec; |
typedef struct _Pixmap { |
DrawableRec drawable; |
PrivateRec *devPrivates; |
int refcnt; |
int devKind; /* This is the pitch of the pixmap, typically width*bpp/8. */ |
// DevUnion devPrivate; /* When !NULL, devPrivate.ptr points to the raw pixel data. */ |
#ifdef COMPOSITE |
short screen_x; |
short screen_y; |
#endif |
struct intel_pixmap *private; |
unsigned usage_hint; /* see CREATE_PIXMAP_USAGE_* */ |
PixmapPtr master_pixmap; /* pointer to master copy of pixmap for pixmap sharing */ |
} PixmapRec; |
typedef struct _PictFormat { |
uint32_t id; |
uint32_t format; /* except bpp */ |
unsigned char type; |
unsigned char depth; |
// DirectFormatRec direct; |
// IndexFormatRec index; |
} PictFormatRec; |
typedef struct _Picture { |
DrawablePtr pDrawable; |
PictFormatPtr pFormat; |
PictFormatShort format; /* PICT_FORMAT */ |
int refcnt; |
uint32_t id; |
unsigned int repeat:1; |
unsigned int graphicsExposures:1; |
unsigned int subWindowMode:1; |
unsigned int polyEdge:1; |
unsigned int polyMode:1; |
unsigned int freeCompClip:1; |
unsigned int clientClipType:2; |
unsigned int componentAlpha:1; |
unsigned int repeatType:2; |
unsigned int filter:3; |
// unsigned int stateChanges:CPLastBit; |
// unsigned int unused:18 - CPLastBit; |
// PicturePtr alphaMap; |
PictTransform *transform; |
// SourcePictPtr pSourcePict; |
// xFixed *filter_params; |
// int filter_nparams; |
} PictureRec; |
#define RepeatNone 0 |
#define RepeatNormal 1 |
#define RepeatPad 2 |
#define RepeatReflect 3 |
#define PictFilterNearest 0 |
#define PictFilterBilinear 1 |
#define PictFilterFast 2 |
#define PictFilterGood 3 |
#define PictFilterBest 4 |
#define PictFilterConvolution 5 |
#endif /* _PICTURE_H_ */ |
/drivers/video/Intel-2D/pixlib-sna.c |
---|
0,0 → 1,282 |
// -kr -i4 -ts4 -bls -bl -bli0 |
#include <stdio.h> |
#include <malloc.h> |
#include <stdbool.h> |
#include <pixlib2.h> |
#include <kos32sys.h> |
#define DISPLAY_VERSION 0x0200 /* 2.00 */ |
#define SRV_GETVERSION 0 |
#define SRV_GET_CAPS 3 |
#define BUFFER_SIZE(n) ((n)*sizeof(uint32_t)) |
#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask)) |
#define ALIGN(x,a) __ALIGN_MASK(x,(typeof(x))(a)-1) |
#define to_surface(x) (surface_t*)((x)->handle) |
typedef struct |
{ |
uint32_t width; |
uint32_t height; |
void *data; |
uint32_t pitch; |
uint32_t bo; |
uint32_t bo_size; |
uint32_t flags; |
} surface_t; |
int sna_init(uint32_t service); |
void sna_fini(); |
int sna_create_bitmap(bitmap_t * bitmap); |
int sna_destroy_bitmap(bitmap_t * bitmap); |
int sna_lock_bitmap(bitmap_t * bitmap); |
int sna_resize_bitmap(bitmap_t *bitmap); |
//int sna_blit_copy(bitmap_t * src_bitmap, int dst_x, int dst_y, |
// int w, int h, int src_x, int src_y); |
int sna_blit_tex(bitmap_t * src_bitmap, bool scale, int dst_x, int dst_y, |
int w, int h, int src_x, int src_y); |
static uint32_t service; |
static uint32_t hw_caps; |
uint32_t init_pixlib(uint32_t caps) |
{ |
uint32_t api_version; |
ioctl_t io; |
if (service != 0) |
return caps & hw_caps; |
service = get_service("DISPLAY"); |
if (service == 0) |
goto fail; |
io.handle = service; |
io.io_code = SRV_GETVERSION; |
io.input = NULL; |
io.inp_size = 0; |
io.output = &api_version; |
io.out_size = BUFFER_SIZE(1); |
if (call_service(&io) != 0) |
goto fail; |
if ((DISPLAY_VERSION > (api_version & 0xFFFF)) || |
(DISPLAY_VERSION < (api_version >> 16))) |
goto fail; |
hw_caps = sna_init(service); |
if (hw_caps) |
printf("2D caps %s%s%s\n", |
(hw_caps & HW_BIT_BLIT) != 0 ? "HW_BIT_BLIT " : "", |
(hw_caps & HW_TEX_BLIT) != 0 ? "HW_TEX_BLIT " : "", |
(hw_caps & HW_VID_BLIT) != 0 ? "HW_VID_BLIT " : ""); |
return caps & hw_caps; |
fail: |
service = 0; |
return 0; |
}; |
void done_pixlib() |
{ |
if (hw_caps != 0) |
sna_fini(); |
}; |
int create_bitmap(bitmap_t * bitmap) |
{ |
uint32_t size, bo_size; |
uint32_t pitch, max_pitch; |
void *buffer; |
surface_t *sf; |
bitmap->handle = -1; |
bitmap->data = (void *) -1; |
bitmap->pitch = -1; |
if (bitmap->flags &= hw_caps) |
return sna_create_bitmap(bitmap); |
pitch = ALIGN(bitmap->width * 4, 16); |
max_pitch = ALIGN(bitmap->max_width * 4, 16); |
size = ALIGN(pitch * bitmap->height, 4096); |
bo_size = ALIGN(max_pitch * bitmap->max_height, 4096); |
if (bo_size < size) |
bo_size = size; |
sf = malloc(sizeof(*sf)); |
if (sf == NULL) |
return -1; |
buffer = user_alloc(bo_size); |
if (buffer == NULL) |
{ |
free(sf); |
return -1; |
}; |
sf->width = bitmap->width; |
sf->height = bitmap->height; |
sf->data = buffer; |
sf->pitch = pitch; |
sf->bo = 0; |
sf->bo_size = bo_size; |
sf->flags = bitmap->flags; |
bitmap->handle = (uint32_t) sf; |
// printf("create bitmap %p handle %p data %p w %d h%d\n", |
// bitmap, bitmap->handle, bitmap->data, bitmap->width, bitmap->height); |
return 0; |
}; |
int destroy_bitmap(bitmap_t * bitmap) |
{ |
surface_t *sf = to_surface(bitmap); |
if (sf->flags & hw_caps) |
return sna_destroy_bitmap(bitmap); |
user_free(sf->data); |
free(sf); |
bitmap->handle = -1; |
bitmap->data = (void *) -1; |
bitmap->pitch = -1; |
return 0; |
}; |
int lock_bitmap(bitmap_t * bitmap) |
{ |
surface_t *sf = to_surface(bitmap); |
if (bitmap->data != (void *) -1) |
return 0; |
if (sf->flags & hw_caps) |
return sna_lock_bitmap(bitmap); |
bitmap->data = sf->data; |
bitmap->pitch = sf->pitch; |
return 0; |
}; |
int blit_bitmap(bitmap_t * bitmap, int dst_x, int dst_y, |
int w, int h, int src_x, int src_y) |
{ |
struct blit_call bc; |
int ret; |
surface_t *sf = to_surface(bitmap); |
if (sf->flags & hw_caps & HW_BIT_BLIT) |
return sna_blit_tex(bitmap, false, dst_x, dst_y, w, h, src_x, src_y); |
bc.dstx = dst_x; |
bc.dsty = dst_y; |
bc.w = w; |
bc.h = h; |
bc.srcx = 0; |
bc.srcy = 0; |
bc.srcw = w; |
bc.srch = h; |
bc.stride = sf->pitch; |
bc.bitmap = sf->data; |
__asm__ __volatile__( |
"int $0x40":"=a"(ret):"a"(73), "b"(0x00), |
"c"(&bc):"memory"); |
bitmap->data = (void *) -1; |
bitmap->pitch = -1; |
return ret; |
}; |
int fplay_blit_bitmap(bitmap_t * bitmap, int dst_x, int dst_y, int w, int h) |
{ |
struct blit_call bc; |
int ret; |
surface_t *sf = to_surface(bitmap); |
if (sf->flags & hw_caps & HW_TEX_BLIT) |
return sna_blit_tex(bitmap, true, dst_x, dst_y, w, h, 0, 0); |
bc.dstx = dst_x; |
bc.dsty = dst_y; |
bc.w = w; |
bc.h = h; |
bc.srcx = 0; |
bc.srcy = 0; |
bc.srcw = w; |
bc.srch = h; |
bc.stride = sf->pitch; |
bc.bitmap = sf->data; |
__asm__ __volatile__( |
"int $0x40":"=a"(ret):"a"(73), "b"(0x00), |
"c"(&bc):"memory"); |
bitmap->data = (void *) -1; |
bitmap->pitch = -1; |
return ret; |
}; |
int resize_bitmap(bitmap_t * bitmap) |
{ |
uint32_t size; |
uint32_t pitch; |
// printf("%s\n", __FUNCTION__); |
surface_t *sf = to_surface(bitmap); |
if (sf->flags & hw_caps) |
{ |
return sna_resize_bitmap(bitmap); |
}; |
pitch = ALIGN(bitmap->width * 4, 16); |
size = ALIGN(pitch * bitmap->height, 4096); |
bitmap->pitch = -1; |
bitmap->data = (void *) -1; |
if (size > sf->bo_size) |
{ |
sf->data = user_realloc(sf->data, size); /* grow buffer */ |
if (sf->data == NULL) |
return -1; |
sf->bo_size = size; |
} else if (size < sf->bo_size) |
user_unmap(sf->data, size, sf->bo_size - size); /* unmap unused pages */ |
sf->width = bitmap->width; |
sf->height = bitmap->height; |
sf->pitch = pitch; |
return 0; |
}; |
/drivers/video/Intel-2D/pixlib-uxa.c |
---|
0,0 → 1,282 |
// -kr -i4 -ts4 -bls -bl -bli0 |
#include <stdio.h> |
#include <malloc.h> |
#include <stdbool.h> |
#include <pixlib2.h> |
#include <kos32sys.h> |
#define DISPLAY_VERSION 0x0200 /* 2.00 */ |
#define SRV_GETVERSION 0 |
#define SRV_GET_CAPS 3 |
#define BUFFER_SIZE(n) ((n)*sizeof(uint32_t)) |
#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask)) |
#define ALIGN(x,a) __ALIGN_MASK(x,(typeof(x))(a)-1) |
#define to_surface(x) (surface_t*)((x)->handle) |
typedef struct |
{ |
uint32_t width; |
uint32_t height; |
void *data; |
uint32_t pitch; |
uint32_t bo; |
uint32_t bo_size; |
uint32_t flags; |
} surface_t; |
int uxa_init(uint32_t service); |
void uxa_fini(); |
int sna_create_bitmap(bitmap_t * bitmap); |
int sna_destroy_bitmap(bitmap_t * bitmap); |
int sna_lock_bitmap(bitmap_t * bitmap); |
int sna_resize_bitmap(bitmap_t *bitmap); |
//int sna_blit_copy(bitmap_t * src_bitmap, int dst_x, int dst_y, |
// int w, int h, int src_x, int src_y); |
int sna_blit_tex(bitmap_t * src_bitmap, bool scale, int dst_x, int dst_y, |
int w, int h, int src_x, int src_y); |
static uint32_t service; |
static uint32_t hw_caps; |
uint32_t init_pixlib(uint32_t caps) |
{ |
uint32_t api_version; |
ioctl_t io; |
if (service != 0) |
return caps & hw_caps; |
service = get_service("DISPLAY"); |
if (service == 0) |
goto fail; |
io.handle = service; |
io.io_code = SRV_GETVERSION; |
io.input = NULL; |
io.inp_size = 0; |
io.output = &api_version; |
io.out_size = BUFFER_SIZE(1); |
if (call_service(&io) != 0) |
goto fail; |
if ((DISPLAY_VERSION > (api_version & 0xFFFF)) || |
(DISPLAY_VERSION < (api_version >> 16))) |
goto fail; |
hw_caps = uxa_init(service); |
if (hw_caps) |
printf("2D caps %s%s%s\n", |
(hw_caps & HW_BIT_BLIT) != 0 ? "HW_BIT_BLIT " : "", |
(hw_caps & HW_TEX_BLIT) != 0 ? "HW_TEX_BLIT " : "", |
(hw_caps & HW_VID_BLIT) != 0 ? "HW_VID_BLIT " : ""); |
return caps & hw_caps; |
fail: |
service = 0; |
return 0; |
}; |
void done_pixlib() |
{ |
// if (hw_caps != 0) |
// uxa_fini(); |
}; |
int create_bitmap(bitmap_t * bitmap) |
{ |
uint32_t size, bo_size; |
uint32_t pitch, max_pitch; |
void *buffer; |
surface_t *sf; |
bitmap->handle = -1; |
bitmap->data = (void *) -1; |
bitmap->pitch = -1; |
// if (bitmap->flags &= hw_caps) |
// return sna_create_bitmap(bitmap); |
pitch = ALIGN(bitmap->width * 4, 16); |
max_pitch = ALIGN(bitmap->max_width * 4, 16); |
size = ALIGN(pitch * bitmap->height, 4096); |
bo_size = ALIGN(max_pitch * bitmap->max_height, 4096); |
if (bo_size < size) |
bo_size = size; |
sf = malloc(sizeof(*sf)); |
if (sf == NULL) |
return -1; |
buffer = user_alloc(bo_size); |
if (buffer == NULL) |
{ |
free(sf); |
return -1; |
}; |
sf->width = bitmap->width; |
sf->height = bitmap->height; |
sf->data = buffer; |
sf->pitch = pitch; |
sf->bo = 0; |
sf->bo_size = bo_size; |
sf->flags = bitmap->flags; |
bitmap->handle = (uint32_t) sf; |
// printf("create bitmap %p handle %p data %p w %d h%d\n", |
// bitmap, bitmap->handle, bitmap->data, bitmap->width, bitmap->height); |
return 0; |
}; |
int destroy_bitmap(bitmap_t * bitmap) |
{ |
surface_t *sf = to_surface(bitmap); |
// if (sf->flags & hw_caps) |
// return sna_destroy_bitmap(bitmap); |
user_free(sf->data); |
free(sf); |
bitmap->handle = -1; |
bitmap->data = (void *) -1; |
bitmap->pitch = -1; |
return 0; |
}; |
int lock_bitmap(bitmap_t * bitmap) |
{ |
surface_t *sf = to_surface(bitmap); |
if (bitmap->data != (void *) -1) |
return 0; |
// if (sf->flags & hw_caps) |
// return sna_lock_bitmap(bitmap); |
bitmap->data = sf->data; |
bitmap->pitch = sf->pitch; |
return 0; |
}; |
int blit_bitmap(bitmap_t * bitmap, int dst_x, int dst_y, |
int w, int h, int src_x, int src_y) |
{ |
struct blit_call bc; |
int ret; |
surface_t *sf = to_surface(bitmap); |
// if (sf->flags & hw_caps & HW_BIT_BLIT) |
// return sna_blit_tex(bitmap, false, dst_x, dst_y, w, h, src_x, src_y); |
bc.dstx = dst_x; |
bc.dsty = dst_y; |
bc.w = w; |
bc.h = h; |
bc.srcx = 0; |
bc.srcy = 0; |
bc.srcw = w; |
bc.srch = h; |
bc.stride = sf->pitch; |
bc.bitmap = sf->data; |
__asm__ __volatile__( |
"int $0x40":"=a"(ret):"a"(73), "b"(0x00), |
"c"(&bc):"memory"); |
bitmap->data = (void *) -1; |
bitmap->pitch = -1; |
return ret; |
}; |
int fplay_blit_bitmap(bitmap_t * bitmap, int dst_x, int dst_y, int w, int h) |
{ |
struct blit_call bc; |
int ret; |
surface_t *sf = to_surface(bitmap); |
// if (sf->flags & hw_caps & HW_TEX_BLIT) |
// return sna_blit_tex(bitmap, true, dst_x, dst_y, w, h, 0, 0); |
bc.dstx = dst_x; |
bc.dsty = dst_y; |
bc.w = w; |
bc.h = h; |
bc.srcx = 0; |
bc.srcy = 0; |
bc.srcw = w; |
bc.srch = h; |
bc.stride = sf->pitch; |
bc.bitmap = sf->data; |
__asm__ __volatile__( |
"int $0x40":"=a"(ret):"a"(73), "b"(0x00), |
"c"(&bc):"memory"); |
bitmap->data = (void *) -1; |
bitmap->pitch = -1; |
return ret; |
}; |
int resize_bitmap(bitmap_t * bitmap) |
{ |
uint32_t size; |
uint32_t pitch; |
// printf("%s\n", __FUNCTION__); |
surface_t *sf = to_surface(bitmap); |
// if (sf->flags & hw_caps) |
// { |
// return sna_resize_bitmap(bitmap); |
// }; |
pitch = ALIGN(bitmap->width * 4, 16); |
size = ALIGN(pitch * bitmap->height, 4096); |
bitmap->pitch = -1; |
bitmap->data = (void *) -1; |
if (size > sf->bo_size) |
{ |
sf->data = user_realloc(sf->data, size); /* grow buffer */ |
if (sf->data == NULL) |
return -1; |
sf->bo_size = size; |
} else if (size < sf->bo_size) |
user_unmap(sf->data, size, sf->bo_size - size); /* unmap unused pages */ |
sf->width = bitmap->width; |
sf->height = bitmap->height; |
sf->pitch = pitch; |
return 0; |
}; |
/drivers/video/Intel-2D/render_program/exa_sf.g4b |
---|
0,0 → 1,15 |
{ 0x00400031, 0x20c01fbd, 0x0069002c, 0x01110001 }, |
{ 0x00400001, 0x206003be, 0x00690060, 0x00000000 }, |
{ 0x00400040, 0x20e077bd, 0x00690080, 0x006940a0 }, |
{ 0x00400041, 0x202077be, 0x006900e0, 0x000000c0 }, |
{ 0x00400040, 0x20e077bd, 0x006900a0, 0x00694060 }, |
{ 0x00400041, 0x204077be, 0x006900e0, 0x000000c8 }, |
{ 0x00600031, 0x20001fbc, 0x008d0000, 0x8640c800 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
/drivers/video/Intel-2D/render_program/exa_sf.g4b.gen5 |
---|
0,0 → 1,15 |
{ 0x00400031, 0x20c01fbd, 0x1069002c, 0x02100001 }, |
{ 0x00400001, 0x206003be, 0x00690060, 0x00000000 }, |
{ 0x00400040, 0x20e077bd, 0x00690080, 0x006940a0 }, |
{ 0x00400041, 0x202077be, 0x006900e0, 0x000000c0 }, |
{ 0x00400040, 0x20e077bd, 0x006900a0, 0x00694060 }, |
{ 0x00400041, 0x204077be, 0x006900e0, 0x000000c8 }, |
{ 0x00600031, 0x20001fbc, 0x648d0000, 0x8808c800 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
/drivers/video/Intel-2D/render_program/exa_sf.g5b |
---|
0,0 → 1,7 |
{ 0x00400031, 0x20c01fbd, 0x1069002c, 0x02100001 }, |
{ 0x00400001, 0x206003be, 0x00690060, 0x00000000 }, |
{ 0x00400040, 0x20e077bd, 0x00690080, 0x006940a0 }, |
{ 0x00400041, 0x202077be, 0x006900e0, 0x000000c0 }, |
{ 0x00400040, 0x20e077bd, 0x006900a0, 0x00694060 }, |
{ 0x00400041, 0x204077be, 0x006900e0, 0x000000c8 }, |
{ 0x00600031, 0x20001fbc, 0x648d0000, 0x8808c800 }, |
/drivers/video/Intel-2D/render_program/exa_sf_mask.g4b |
---|
0,0 → 1,15 |
{ 0x00400031, 0x20c01fbd, 0x0069002c, 0x01110001 }, |
{ 0x00600001, 0x206003be, 0x008d0060, 0x00000000 }, |
{ 0x00600040, 0x20e077bd, 0x008d0080, 0x008d40a0 }, |
{ 0x00600041, 0x202077be, 0x008d00e0, 0x000000c0 }, |
{ 0x00600040, 0x20e077bd, 0x008d00a0, 0x008d4060 }, |
{ 0x00600041, 0x204077be, 0x008d00e0, 0x000000c8 }, |
{ 0x00600031, 0x20001fbc, 0x008d0000, 0x8640c800 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
/drivers/video/Intel-2D/render_program/exa_sf_mask.g4b.gen5 |
---|
0,0 → 1,15 |
{ 0x00400031, 0x20c01fbd, 0x1069002c, 0x02100001 }, |
{ 0x00600001, 0x206003be, 0x008d0060, 0x00000000 }, |
{ 0x00600040, 0x20e077bd, 0x008d0080, 0x008d40a0 }, |
{ 0x00600041, 0x202077be, 0x008d00e0, 0x000000c0 }, |
{ 0x00600040, 0x20e077bd, 0x008d00a0, 0x008d4060 }, |
{ 0x00600041, 0x204077be, 0x008d00e0, 0x000000c8 }, |
{ 0x00600031, 0x20001fbc, 0x648d0000, 0x8808c800 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
/drivers/video/Intel-2D/render_program/exa_sf_mask.g5b |
---|
0,0 → 1,7 |
{ 0x00400031, 0x20c01fbd, 0x1069002c, 0x02100001 }, |
{ 0x00600001, 0x206003be, 0x008d0060, 0x00000000 }, |
{ 0x00600040, 0x20e077bd, 0x008d0080, 0x008d40a0 }, |
{ 0x00600041, 0x202077be, 0x008d00e0, 0x000000c0 }, |
{ 0x00600040, 0x20e077bd, 0x008d00a0, 0x008d4060 }, |
{ 0x00600041, 0x204077be, 0x008d00e0, 0x000000c8 }, |
{ 0x00600031, 0x20001fbc, 0x648d0000, 0x8808c800 }, |
/drivers/video/Intel-2D/render_program/exa_wm_ca.g4b |
---|
0,0 → 1,4 |
{ 0x00802041, 0x21c077bd, 0x008d01c0, 0x008d02c0 }, |
{ 0x00802041, 0x220077bd, 0x008d0200, 0x008d0300 }, |
{ 0x00802041, 0x224077bd, 0x008d0240, 0x008d0340 }, |
{ 0x00802041, 0x228077bd, 0x008d0280, 0x008d0380 }, |
/drivers/video/Intel-2D/render_program/exa_wm_ca.g4b.gen5 |
---|
0,0 → 1,4 |
{ 0x00802041, 0x21c077bd, 0x008d01c0, 0x008d02c0 }, |
{ 0x00802041, 0x220077bd, 0x008d0200, 0x008d0300 }, |
{ 0x00802041, 0x224077bd, 0x008d0240, 0x008d0340 }, |
{ 0x00802041, 0x228077bd, 0x008d0280, 0x008d0380 }, |
/drivers/video/Intel-2D/render_program/exa_wm_ca.g5b |
---|
0,0 → 1,4 |
{ 0x00802041, 0x21c077bd, 0x008d01c0, 0x008d02c0 }, |
{ 0x00802041, 0x220077bd, 0x008d0200, 0x008d0300 }, |
{ 0x00802041, 0x224077bd, 0x008d0240, 0x008d0340 }, |
{ 0x00802041, 0x228077bd, 0x008d0280, 0x008d0380 }, |
/drivers/video/Intel-2D/render_program/exa_wm_ca.g6b |
---|
0,0 → 1,4 |
{ 0x00800041, 0x21c077bd, 0x008d01c0, 0x008d02c0 }, |
{ 0x00800041, 0x220077bd, 0x008d0200, 0x008d0300 }, |
{ 0x00800041, 0x224077bd, 0x008d0240, 0x008d0340 }, |
{ 0x00800041, 0x228077bd, 0x008d0280, 0x008d0380 }, |
/drivers/video/Intel-2D/render_program/exa_wm_ca_srcalpha.g4b |
---|
0,0 → 1,4 |
{ 0x00802041, 0x21c077bd, 0x008d02c0, 0x008d0280 }, |
{ 0x00802041, 0x220077bd, 0x008d0300, 0x008d0280 }, |
{ 0x00802041, 0x224077bd, 0x008d0340, 0x008d0280 }, |
{ 0x00802041, 0x228077bd, 0x008d0380, 0x008d0280 }, |
/drivers/video/Intel-2D/render_program/exa_wm_ca_srcalpha.g4b.gen5 |
---|
0,0 → 1,4 |
{ 0x00802041, 0x21c077bd, 0x008d02c0, 0x008d0280 }, |
{ 0x00802041, 0x220077bd, 0x008d0300, 0x008d0280 }, |
{ 0x00802041, 0x224077bd, 0x008d0340, 0x008d0280 }, |
{ 0x00802041, 0x228077bd, 0x008d0380, 0x008d0280 }, |
/drivers/video/Intel-2D/render_program/exa_wm_ca_srcalpha.g5b |
---|
0,0 → 1,4 |
{ 0x00802041, 0x21c077bd, 0x008d02c0, 0x008d0280 }, |
{ 0x00802041, 0x220077bd, 0x008d0300, 0x008d0280 }, |
{ 0x00802041, 0x224077bd, 0x008d0340, 0x008d0280 }, |
{ 0x00802041, 0x228077bd, 0x008d0380, 0x008d0280 }, |
/drivers/video/Intel-2D/render_program/exa_wm_ca_srcalpha.g6b |
---|
0,0 → 1,4 |
{ 0x00800041, 0x21c077bd, 0x008d02c0, 0x008d0280 }, |
{ 0x00800041, 0x220077bd, 0x008d0300, 0x008d0280 }, |
{ 0x00800041, 0x224077bd, 0x008d0340, 0x008d0280 }, |
{ 0x00800041, 0x228077bd, 0x008d0380, 0x008d0280 }, |
/drivers/video/Intel-2D/render_program/exa_wm_mask_affine.g4b |
---|
0,0 → 1,8 |
{ 0x00802041, 0x23c077bd, 0x008d0100, 0x000000a0 }, |
{ 0x00802041, 0x238077bd, 0x008d0140, 0x000000a4 }, |
{ 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 }, |
{ 0x00802040, 0x210077be, 0x008d03c0, 0x000000ac }, |
{ 0x00802041, 0x23c077bd, 0x008d0100, 0x000000b0 }, |
{ 0x00802041, 0x238077bd, 0x008d0140, 0x000000b4 }, |
{ 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 }, |
{ 0x00802040, 0x214077be, 0x008d03c0, 0x000000bc }, |
/drivers/video/Intel-2D/render_program/exa_wm_mask_affine.g4b.gen5 |
---|
0,0 → 1,8 |
{ 0x00802041, 0x23c077bd, 0x008d0100, 0x000000a0 }, |
{ 0x00802041, 0x238077bd, 0x008d0140, 0x000000a4 }, |
{ 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 }, |
{ 0x00802040, 0x210077be, 0x008d03c0, 0x000000ac }, |
{ 0x00802041, 0x23c077bd, 0x008d0100, 0x000000b0 }, |
{ 0x00802041, 0x238077bd, 0x008d0140, 0x000000b4 }, |
{ 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 }, |
{ 0x00802040, 0x214077be, 0x008d03c0, 0x000000bc }, |
/drivers/video/Intel-2D/render_program/exa_wm_mask_affine.g5b |
---|
0,0 → 1,4 |
{ 0x00802059, 0x200077bc, 0x000000a0, 0x008d0100 }, |
{ 0x00802048, 0x210077be, 0x000000a4, 0x008d0140 }, |
{ 0x00802059, 0x200077bc, 0x000000b0, 0x008d0100 }, |
{ 0x00802048, 0x214077be, 0x000000b4, 0x008d0140 }, |
/drivers/video/Intel-2D/render_program/exa_wm_mask_affine.g6b |
---|
0,0 → 1,4 |
{ 0x0060005a, 0x210077be, 0x00000100, 0x008d0040 }, |
{ 0x0060005a, 0x212077be, 0x00000100, 0x008d0080 }, |
{ 0x0060005a, 0x214077be, 0x00000110, 0x008d0040 }, |
{ 0x0060005a, 0x216077be, 0x00000110, 0x008d0080 }, |
/drivers/video/Intel-2D/render_program/exa_wm_mask_affine.g7b |
---|
0,0 → 1,4 |
{ 0x0060005a, 0x290077bd, 0x00000100, 0x008d0040 }, |
{ 0x0060005a, 0x292077bd, 0x00000100, 0x008d0080 }, |
{ 0x0060005a, 0x294077bd, 0x00000110, 0x008d0040 }, |
{ 0x0060005a, 0x296077bd, 0x00000110, 0x008d0080 }, |
/drivers/video/Intel-2D/render_program/exa_wm_mask_projective.g4b |
---|
0,0 → 1,16 |
{ 0x00802041, 0x23c077bd, 0x008d0100, 0x000000c0 }, |
{ 0x00802041, 0x238077bd, 0x008d0140, 0x000000c4 }, |
{ 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 }, |
{ 0x00802040, 0x23c077bd, 0x008d03c0, 0x000000cc }, |
{ 0x00600031, 0x21801fbd, 0x008d03c0, 0x01110001 }, |
{ 0x00600031, 0x21a01fbd, 0x008d03e0, 0x01110001 }, |
{ 0x00802041, 0x23c077bd, 0x008d0100, 0x000000a0 }, |
{ 0x00802041, 0x238077bd, 0x008d0140, 0x000000a4 }, |
{ 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 }, |
{ 0x00802040, 0x23c077bd, 0x008d03c0, 0x000000ac }, |
{ 0x00802041, 0x210077be, 0x008d03c0, 0x008d0180 }, |
{ 0x00802041, 0x23c077bd, 0x008d0100, 0x000000b0 }, |
{ 0x00802041, 0x238077bd, 0x008d0140, 0x000000b4 }, |
{ 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 }, |
{ 0x00802040, 0x23c077bd, 0x008d03c0, 0x000000bc }, |
{ 0x00802041, 0x214077be, 0x008d03c0, 0x008d0180 }, |
/drivers/video/Intel-2D/render_program/exa_wm_mask_projective.g4b.gen5 |
---|
0,0 → 1,16 |
{ 0x00802041, 0x23c077bd, 0x008d0100, 0x000000c0 }, |
{ 0x00802041, 0x238077bd, 0x008d0140, 0x000000c4 }, |
{ 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 }, |
{ 0x00802040, 0x23c077bd, 0x008d03c0, 0x000000cc }, |
{ 0x00600031, 0x21801fbd, 0x108d03c0, 0x02100001 }, |
{ 0x00600031, 0x21a01fbd, 0x108d03e0, 0x02100001 }, |
{ 0x00802041, 0x23c077bd, 0x008d0100, 0x000000a0 }, |
{ 0x00802041, 0x238077bd, 0x008d0140, 0x000000a4 }, |
{ 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 }, |
{ 0x00802040, 0x23c077bd, 0x008d03c0, 0x000000ac }, |
{ 0x00802041, 0x210077be, 0x008d03c0, 0x008d0180 }, |
{ 0x00802041, 0x23c077bd, 0x008d0100, 0x000000b0 }, |
{ 0x00802041, 0x238077bd, 0x008d0140, 0x000000b4 }, |
{ 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 }, |
{ 0x00802040, 0x23c077bd, 0x008d03c0, 0x000000bc }, |
{ 0x00802041, 0x214077be, 0x008d03c0, 0x008d0180 }, |
/drivers/video/Intel-2D/render_program/exa_wm_mask_projective.g5b |
---|
0,0 → 1,16 |
{ 0x00802041, 0x23c077bd, 0x008d0100, 0x000000c0 }, |
{ 0x00802041, 0x238077bd, 0x008d0140, 0x000000c4 }, |
{ 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 }, |
{ 0x00802040, 0x23c077bd, 0x008d03c0, 0x000000cc }, |
{ 0x00600031, 0x21801fbd, 0x108d03c0, 0x02100001 }, |
{ 0x00600031, 0x21a01fbd, 0x108d03e0, 0x02100001 }, |
{ 0x00802041, 0x23c077bd, 0x008d0100, 0x000000a0 }, |
{ 0x00802041, 0x238077bd, 0x008d0140, 0x000000a4 }, |
{ 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 }, |
{ 0x00802040, 0x23c077bd, 0x008d03c0, 0x000000ac }, |
{ 0x00802041, 0x210077be, 0x008d03c0, 0x008d0180 }, |
{ 0x00802041, 0x23c077bd, 0x008d0100, 0x000000b0 }, |
{ 0x00802041, 0x238077bd, 0x008d0140, 0x000000b4 }, |
{ 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 }, |
{ 0x00802040, 0x23c077bd, 0x008d03c0, 0x000000bc }, |
{ 0x00802041, 0x214077be, 0x008d03c0, 0x008d0180 }, |
/drivers/video/Intel-2D/render_program/exa_wm_mask_projective.g6b |
---|
0,0 → 1,12 |
{ 0x0060005a, 0x23c077bd, 0x00000120, 0x008d0040 }, |
{ 0x0060005a, 0x23e077bd, 0x00000120, 0x008d0080 }, |
{ 0x01600038, 0x218003bd, 0x008d03c0, 0x00000000 }, |
{ 0x01600038, 0x21a003bd, 0x008d03e0, 0x00000000 }, |
{ 0x0060005a, 0x23c077bd, 0x00000100, 0x008d0040 }, |
{ 0x0060005a, 0x23e077bd, 0x00000100, 0x008d0080 }, |
{ 0x00600041, 0x210077be, 0x008d03c0, 0x008d0180 }, |
{ 0x00600041, 0x212077be, 0x008d03e0, 0x008d01a0 }, |
{ 0x0060005a, 0x23c077bd, 0x00000110, 0x008d0040 }, |
{ 0x0060005a, 0x23e077bd, 0x00000110, 0x008d0080 }, |
{ 0x00600041, 0x214077be, 0x008d03c0, 0x008d0180 }, |
{ 0x00600041, 0x216077be, 0x008d03e0, 0x008d01a0 }, |
/drivers/video/Intel-2D/render_program/exa_wm_mask_projective.g7b |
---|
0,0 → 1,12 |
{ 0x0060005a, 0x23c077bd, 0x00000120, 0x008d0040 }, |
{ 0x0060005a, 0x23e077bd, 0x00000120, 0x008d0080 }, |
{ 0x01600038, 0x218003bd, 0x008d03c0, 0x00000000 }, |
{ 0x01600038, 0x21a003bd, 0x008d03e0, 0x00000000 }, |
{ 0x0060005a, 0x23c077bd, 0x00000100, 0x008d0040 }, |
{ 0x0060005a, 0x23e077bd, 0x00000100, 0x008d0080 }, |
{ 0x00600041, 0x290077bd, 0x008d03c0, 0x008d0180 }, |
{ 0x00600041, 0x292077bd, 0x008d03e0, 0x008d01a0 }, |
{ 0x0060005a, 0x23c077bd, 0x00000110, 0x008d0040 }, |
{ 0x0060005a, 0x23e077bd, 0x00000110, 0x008d0080 }, |
{ 0x00600041, 0x294077bd, 0x008d03c0, 0x008d0180 }, |
{ 0x00600041, 0x296077bd, 0x008d03e0, 0x008d01a0 }, |
/drivers/video/Intel-2D/render_program/exa_wm_mask_sample_a.g4b |
---|
0,0 → 1,3 |
{ 0x00000201, 0x20080061, 0x00000000, 0x00007000 }, |
{ 0x00600001, 0x20e00022, 0x008d0000, 0x00000000 }, |
{ 0x07800031, 0x23801c09, 0x00000000, 0x02520102 }, |
/drivers/video/Intel-2D/render_program/exa_wm_mask_sample_a.g4b.gen5 |
---|
0,0 → 1,3 |
{ 0x00000201, 0x20080061, 0x00000000, 0x00007000 }, |
{ 0x00600001, 0x20e00022, 0x008d0000, 0x00000000 }, |
{ 0x07800031, 0x23801c09, 0x20000000, 0x0a2a0102 }, |
/drivers/video/Intel-2D/render_program/exa_wm_mask_sample_a.g5b |
---|
0,0 → 1,3 |
{ 0x00000201, 0x20080061, 0x00000000, 0x00007000 }, |
{ 0x00600001, 0x20e00022, 0x008d0000, 0x00000000 }, |
{ 0x07800031, 0x23801c09, 0x20000000, 0x0a2a0102 }, |
/drivers/video/Intel-2D/render_program/exa_wm_mask_sample_a.g6b |
---|
0,0 → 1,3 |
{ 0x00000201, 0x20080061, 0x00000000, 0x00007000 }, |
{ 0x00600001, 0x20e00022, 0x008d0000, 0x00000000 }, |
{ 0x02800031, 0x23801cc9, 0x000000e0, 0x0a2a0102 }, |
/drivers/video/Intel-2D/render_program/exa_wm_mask_sample_a.g7b |
---|
0,0 → 1,3 |
{ 0x00000201, 0x20080061, 0x00000000, 0x00007000 }, |
{ 0x00600001, 0x28e00021, 0x008d0000, 0x00000000 }, |
{ 0x02800031, 0x23801ca9, 0x000008e0, 0x0a2c0102 }, |
/drivers/video/Intel-2D/render_program/exa_wm_mask_sample_argb.g4b |
---|
0,0 → 1,3 |
{ 0x00000201, 0x20080061, 0x00000000, 0x00000000 }, |
{ 0x00600001, 0x20e00022, 0x008d0000, 0x00000000 }, |
{ 0x07800031, 0x22c01c09, 0x00000000, 0x02580102 }, |
/drivers/video/Intel-2D/render_program/exa_wm_mask_sample_argb.g4b.gen5 |
---|
0,0 → 1,3 |
{ 0x00000201, 0x20080061, 0x00000000, 0x00000000 }, |
{ 0x00600001, 0x20e00022, 0x008d0000, 0x00000000 }, |
{ 0x07800031, 0x22c01c09, 0x20000000, 0x0a8a0102 }, |
/drivers/video/Intel-2D/render_program/exa_wm_mask_sample_argb.g5b |
---|
0,0 → 1,3 |
{ 0x00000201, 0x20080061, 0x00000000, 0x00000000 }, |
{ 0x00600001, 0x20e00022, 0x008d0000, 0x00000000 }, |
{ 0x07800031, 0x22c01c09, 0x20000000, 0x0a8a0102 }, |
/drivers/video/Intel-2D/render_program/exa_wm_mask_sample_argb.g6b |
---|
0,0 → 1,3 |
{ 0x00000201, 0x20080061, 0x00000000, 0x00000000 }, |
{ 0x00600001, 0x20e00022, 0x008d0000, 0x00000000 }, |
{ 0x02800031, 0x22c01cc9, 0x000000e0, 0x0a8a0102 }, |
/drivers/video/Intel-2D/render_program/exa_wm_mask_sample_argb.g7b |
---|
0,0 → 1,3 |
{ 0x00000201, 0x20080061, 0x00000000, 0x00000000 }, |
{ 0x00600001, 0x28e00021, 0x008d0000, 0x00000000 }, |
{ 0x02800031, 0x22c01ca9, 0x000008e0, 0x0a8c0102 }, |
/drivers/video/Intel-2D/render_program/exa_wm_noca.g4b |
---|
0,0 → 1,4 |
{ 0x00802041, 0x21c077bd, 0x008d01c0, 0x008d0380 }, |
{ 0x00802041, 0x220077bd, 0x008d0200, 0x008d0380 }, |
{ 0x00802041, 0x224077bd, 0x008d0240, 0x008d0380 }, |
{ 0x00802041, 0x228077bd, 0x008d0280, 0x008d0380 }, |
/drivers/video/Intel-2D/render_program/exa_wm_noca.g4b.gen5 |
---|
0,0 → 1,4 |
{ 0x00802041, 0x21c077bd, 0x008d01c0, 0x008d0380 }, |
{ 0x00802041, 0x220077bd, 0x008d0200, 0x008d0380 }, |
{ 0x00802041, 0x224077bd, 0x008d0240, 0x008d0380 }, |
{ 0x00802041, 0x228077bd, 0x008d0280, 0x008d0380 }, |
/drivers/video/Intel-2D/render_program/exa_wm_noca.g5b |
---|
0,0 → 1,4 |
{ 0x00802041, 0x21c077bd, 0x008d01c0, 0x008d0380 }, |
{ 0x00802041, 0x220077bd, 0x008d0200, 0x008d0380 }, |
{ 0x00802041, 0x224077bd, 0x008d0240, 0x008d0380 }, |
{ 0x00802041, 0x228077bd, 0x008d0280, 0x008d0380 }, |
/drivers/video/Intel-2D/render_program/exa_wm_noca.g6b |
---|
0,0 → 1,4 |
{ 0x00800041, 0x21c077bd, 0x008d01c0, 0x008d0380 }, |
{ 0x00800041, 0x220077bd, 0x008d0200, 0x008d0380 }, |
{ 0x00800041, 0x224077bd, 0x008d0240, 0x008d0380 }, |
{ 0x00800041, 0x228077bd, 0x008d0280, 0x008d0380 }, |
/drivers/video/Intel-2D/render_program/exa_wm_src_affine.g4b |
---|
0,0 → 1,8 |
{ 0x00802041, 0x23c077bd, 0x008d0100, 0x00000060 }, |
{ 0x00802041, 0x238077bd, 0x008d0140, 0x00000064 }, |
{ 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 }, |
{ 0x00802040, 0x204077be, 0x008d03c0, 0x0000006c }, |
{ 0x00802041, 0x23c077bd, 0x008d0100, 0x00000070 }, |
{ 0x00802041, 0x238077bd, 0x008d0140, 0x00000074 }, |
{ 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 }, |
{ 0x00802040, 0x208077be, 0x008d03c0, 0x0000007c }, |
/drivers/video/Intel-2D/render_program/exa_wm_src_affine.g4b.gen5 |
---|
0,0 → 1,8 |
{ 0x00802041, 0x23c077bd, 0x008d0100, 0x00000060 }, |
{ 0x00802041, 0x238077bd, 0x008d0140, 0x00000064 }, |
{ 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 }, |
{ 0x00802040, 0x204077be, 0x008d03c0, 0x0000006c }, |
{ 0x00802041, 0x23c077bd, 0x008d0100, 0x00000070 }, |
{ 0x00802041, 0x238077bd, 0x008d0140, 0x00000074 }, |
{ 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 }, |
{ 0x00802040, 0x208077be, 0x008d03c0, 0x0000007c }, |
/drivers/video/Intel-2D/render_program/exa_wm_src_affine.g5b |
---|
0,0 → 1,4 |
{ 0x00802059, 0x200077bc, 0x00000060, 0x008d0100 }, |
{ 0x00802048, 0x204077be, 0x00000064, 0x008d0140 }, |
{ 0x00802059, 0x200077bc, 0x00000070, 0x008d0100 }, |
{ 0x00802048, 0x208077be, 0x00000074, 0x008d0140 }, |
/drivers/video/Intel-2D/render_program/exa_wm_src_affine.g6b |
---|
0,0 → 1,4 |
{ 0x0060005a, 0x204077be, 0x000000c0, 0x008d0040 }, |
{ 0x0060005a, 0x206077be, 0x000000c0, 0x008d0080 }, |
{ 0x0060005a, 0x208077be, 0x000000d0, 0x008d0040 }, |
{ 0x0060005a, 0x20a077be, 0x000000d0, 0x008d0080 }, |
/drivers/video/Intel-2D/render_program/exa_wm_src_affine.g7b |
---|
0,0 → 1,4 |
{ 0x0060005a, 0x284077bd, 0x000000c0, 0x008d0040 }, |
{ 0x0060005a, 0x286077bd, 0x000000c0, 0x008d0080 }, |
{ 0x0060005a, 0x288077bd, 0x000000d0, 0x008d0040 }, |
{ 0x0060005a, 0x28a077bd, 0x000000d0, 0x008d0080 }, |
/drivers/video/Intel-2D/render_program/exa_wm_src_projective.g4b |
---|
0,0 → 1,16 |
{ 0x00802041, 0x23c077bd, 0x008d0100, 0x00000080 }, |
{ 0x00802041, 0x238077bd, 0x008d0140, 0x00000084 }, |
{ 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 }, |
{ 0x00802040, 0x23c077bd, 0x008d03c0, 0x0000008c }, |
{ 0x00600031, 0x21801fbd, 0x008d03c0, 0x01110001 }, |
{ 0x00600031, 0x21a01fbd, 0x008d03e0, 0x01110001 }, |
{ 0x00802041, 0x23c077bd, 0x008d0100, 0x00000060 }, |
{ 0x00802041, 0x238077bd, 0x008d0140, 0x00000064 }, |
{ 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 }, |
{ 0x00802040, 0x23c077bd, 0x008d03c0, 0x0000006c }, |
{ 0x00802041, 0x204077be, 0x008d03c0, 0x008d0180 }, |
{ 0x00802041, 0x23c077bd, 0x008d0100, 0x00000070 }, |
{ 0x00802041, 0x238077bd, 0x008d0140, 0x00000074 }, |
{ 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 }, |
{ 0x00802040, 0x23c077bd, 0x008d03c0, 0x0000007c }, |
{ 0x00802041, 0x208077be, 0x008d03c0, 0x008d0180 }, |
/drivers/video/Intel-2D/render_program/exa_wm_src_projective.g4b.gen5 |
---|
0,0 → 1,16 |
{ 0x00802041, 0x23c077bd, 0x008d0100, 0x00000080 }, |
{ 0x00802041, 0x238077bd, 0x008d0140, 0x00000084 }, |
{ 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 }, |
{ 0x00802040, 0x23c077bd, 0x008d03c0, 0x0000008c }, |
{ 0x00600031, 0x21801fbd, 0x108d03c0, 0x02100001 }, |
{ 0x00600031, 0x21a01fbd, 0x108d03e0, 0x02100001 }, |
{ 0x00802041, 0x23c077bd, 0x008d0100, 0x00000060 }, |
{ 0x00802041, 0x238077bd, 0x008d0140, 0x00000064 }, |
{ 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 }, |
{ 0x00802040, 0x23c077bd, 0x008d03c0, 0x0000006c }, |
{ 0x00802041, 0x204077be, 0x008d03c0, 0x008d0180 }, |
{ 0x00802041, 0x23c077bd, 0x008d0100, 0x00000070 }, |
{ 0x00802041, 0x238077bd, 0x008d0140, 0x00000074 }, |
{ 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 }, |
{ 0x00802040, 0x23c077bd, 0x008d03c0, 0x0000007c }, |
{ 0x00802041, 0x208077be, 0x008d03c0, 0x008d0180 }, |
/drivers/video/Intel-2D/render_program/exa_wm_src_projective.g5b |
---|
0,0 → 1,16 |
{ 0x00802041, 0x23c077bd, 0x008d0100, 0x00000080 }, |
{ 0x00802041, 0x238077bd, 0x008d0140, 0x00000084 }, |
{ 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 }, |
{ 0x00802040, 0x23c077bd, 0x008d03c0, 0x0000008c }, |
{ 0x00600031, 0x21801fbd, 0x108d03c0, 0x02100001 }, |
{ 0x00600031, 0x21a01fbd, 0x108d03e0, 0x02100001 }, |
{ 0x00802041, 0x23c077bd, 0x008d0100, 0x00000060 }, |
{ 0x00802041, 0x238077bd, 0x008d0140, 0x00000064 }, |
{ 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 }, |
{ 0x00802040, 0x23c077bd, 0x008d03c0, 0x0000006c }, |
{ 0x00802041, 0x204077be, 0x008d03c0, 0x008d0180 }, |
{ 0x00802041, 0x23c077bd, 0x008d0100, 0x00000070 }, |
{ 0x00802041, 0x238077bd, 0x008d0140, 0x00000074 }, |
{ 0x00802040, 0x23c077bd, 0x008d03c0, 0x008d0380 }, |
{ 0x00802040, 0x23c077bd, 0x008d03c0, 0x0000007c }, |
{ 0x00802041, 0x208077be, 0x008d03c0, 0x008d0180 }, |
/drivers/video/Intel-2D/render_program/exa_wm_src_projective.g6b |
---|
0,0 → 1,12 |
{ 0x0060005a, 0x23c077bd, 0x000000e0, 0x008d0040 }, |
{ 0x0060005a, 0x23e077bd, 0x000000e0, 0x008d0080 }, |
{ 0x01600038, 0x218003bd, 0x008d03c0, 0x00000000 }, |
{ 0x01600038, 0x21a003bd, 0x008d03e0, 0x00000000 }, |
{ 0x0060005a, 0x23c077bd, 0x000000c0, 0x008d0040 }, |
{ 0x0060005a, 0x23e077bd, 0x000000c0, 0x008d0080 }, |
{ 0x00600041, 0x204077be, 0x008d03c0, 0x008d0180 }, |
{ 0x00600041, 0x206077be, 0x008d03e0, 0x008d01a0 }, |
{ 0x0060005a, 0x23c077bd, 0x000000d0, 0x008d0040 }, |
{ 0x0060005a, 0x23e077bd, 0x000000d0, 0x008d0080 }, |
{ 0x00600041, 0x208077be, 0x008d03c0, 0x008d0180 }, |
{ 0x00600041, 0x20a077be, 0x008d03e0, 0x008d01a0 }, |
/drivers/video/Intel-2D/render_program/exa_wm_src_projective.g7b |
---|
0,0 → 1,12 |
{ 0x0060005a, 0x23c077bd, 0x000000e0, 0x008d0040 }, |
{ 0x0060005a, 0x23e077bd, 0x000000e0, 0x008d0080 }, |
{ 0x01600038, 0x218003bd, 0x008d03c0, 0x00000000 }, |
{ 0x01600038, 0x21a003bd, 0x008d03e0, 0x00000000 }, |
{ 0x0060005a, 0x23c077bd, 0x000000c0, 0x008d0040 }, |
{ 0x0060005a, 0x23e077bd, 0x000000c0, 0x008d0080 }, |
{ 0x00600041, 0x284077bd, 0x008d03c0, 0x008d0180 }, |
{ 0x00600041, 0x286077bd, 0x008d03e0, 0x008d01a0 }, |
{ 0x0060005a, 0x23c077bd, 0x000000d0, 0x008d0040 }, |
{ 0x0060005a, 0x23e077bd, 0x000000d0, 0x008d0080 }, |
{ 0x00600041, 0x288077bd, 0x008d03c0, 0x008d0180 }, |
{ 0x00600041, 0x28a077bd, 0x008d03e0, 0x008d01a0 }, |
/drivers/video/Intel-2D/render_program/exa_wm_src_sample_a.g4b |
---|
0,0 → 1,3 |
{ 0x00000201, 0x20080061, 0x00000000, 0x00007000 }, |
{ 0x00600001, 0x20200022, 0x008d0000, 0x00000000 }, |
{ 0x01800031, 0x22801c09, 0x00000000, 0x02520001 }, |
/drivers/video/Intel-2D/render_program/exa_wm_src_sample_a.g4b.gen5 |
---|
0,0 → 1,3 |
{ 0x00000201, 0x20080061, 0x00000000, 0x00007000 }, |
{ 0x00600001, 0x20200022, 0x008d0000, 0x00000000 }, |
{ 0x01800031, 0x22801c09, 0x20000000, 0x0a2a0001 }, |
/drivers/video/Intel-2D/render_program/exa_wm_src_sample_a.g5b |
---|
0,0 → 1,3 |
{ 0x00000201, 0x20080061, 0x00000000, 0x00007000 }, |
{ 0x00600001, 0x20200022, 0x008d0000, 0x00000000 }, |
{ 0x01800031, 0x22801c09, 0x20000000, 0x0a2a0001 }, |
/drivers/video/Intel-2D/render_program/exa_wm_src_sample_a.g6b |
---|
0,0 → 1,3 |
{ 0x00000201, 0x20080061, 0x00000000, 0x00007000 }, |
{ 0x00600001, 0x20200022, 0x008d0000, 0x00000000 }, |
{ 0x02800031, 0x22801cc9, 0x00000020, 0x0a2a0001 }, |
/drivers/video/Intel-2D/render_program/exa_wm_src_sample_a.g7b |
---|
0,0 → 1,3 |
{ 0x00000201, 0x20080061, 0x00000000, 0x00007000 }, |
{ 0x00600001, 0x28200021, 0x008d0000, 0x00000000 }, |
{ 0x02800031, 0x22801ca9, 0x00000820, 0x0a2c0001 }, |
/drivers/video/Intel-2D/render_program/exa_wm_src_sample_argb.g4b |
---|
0,0 → 1,3 |
{ 0x00000201, 0x20080061, 0x00000000, 0x00000000 }, |
{ 0x00600001, 0x20200022, 0x008d0000, 0x00000000 }, |
{ 0x01800031, 0x21c01c09, 0x00000000, 0x02580001 }, |
/drivers/video/Intel-2D/render_program/exa_wm_src_sample_argb.g4b.gen5 |
---|
0,0 → 1,3 |
{ 0x00000201, 0x20080061, 0x00000000, 0x00000000 }, |
{ 0x00600001, 0x20200022, 0x008d0000, 0x00000000 }, |
{ 0x01800031, 0x21c01c09, 0x20000000, 0x0a8a0001 }, |
/drivers/video/Intel-2D/render_program/exa_wm_src_sample_argb.g5b |
---|
0,0 → 1,2 |
{ 0x00000201, 0x20080061, 0x00000000, 0x00000000 }, |
{ 0x01800031, 0x21c01d29, 0x208d0000, 0x0a8a0001 }, |
/drivers/video/Intel-2D/render_program/exa_wm_src_sample_argb.g6b |
---|
0,0 → 1,3 |
{ 0x00000201, 0x20080061, 0x00000000, 0x00000000 }, |
{ 0x00600001, 0x20200022, 0x008d0000, 0x00000000 }, |
{ 0x02800031, 0x21c01cc9, 0x00000020, 0x0a8a0001 }, |
/drivers/video/Intel-2D/render_program/exa_wm_src_sample_argb.g7b |
---|
0,0 → 1,3 |
{ 0x00000201, 0x20080061, 0x00000000, 0x00000000 }, |
{ 0x00600001, 0x28200021, 0x008d0000, 0x00000000 }, |
{ 0x02800031, 0x21c01ca9, 0x00000820, 0x0a8c0001 }, |
/drivers/video/Intel-2D/render_program/exa_wm_src_sample_planar.g4b |
---|
0,0 → 1,5 |
{ 0x00000201, 0x20080061, 0x00000000, 0x0000e000 }, |
{ 0x00600001, 0x20200022, 0x008d0000, 0x00000000 }, |
{ 0x01800031, 0x22001c09, 0x00000000, 0x02520001 }, |
{ 0x01800031, 0x21c01c09, 0x00000000, 0x02520003 }, |
{ 0x01800031, 0x22401c09, 0x00000000, 0x02520005 }, |
/drivers/video/Intel-2D/render_program/exa_wm_src_sample_planar.g4b.gen5 |
---|
0,0 → 1,5 |
{ 0x00000201, 0x20080061, 0x00000000, 0x0000e000 }, |
{ 0x00600001, 0x20200022, 0x008d0000, 0x00000000 }, |
{ 0x01800031, 0x22001c09, 0x20000000, 0x0a2a0001 }, |
{ 0x01800031, 0x21c01c09, 0x20000000, 0x0a2a0003 }, |
{ 0x01800031, 0x22401c09, 0x20000000, 0x0a2a0005 }, |
/drivers/video/Intel-2D/render_program/exa_wm_src_sample_planar.g5b |
---|
0,0 → 1,5 |
{ 0x00000201, 0x20080061, 0x00000000, 0x0000e000 }, |
{ 0x00600001, 0x20200022, 0x008d0000, 0x00000000 }, |
{ 0x01800031, 0x22001c09, 0x20000000, 0x0a2a0001 }, |
{ 0x01800031, 0x21c01c09, 0x20000000, 0x0a2a0003 }, |
{ 0x01800031, 0x22401c09, 0x20000000, 0x0a2a0005 }, |
/drivers/video/Intel-2D/render_program/exa_wm_src_sample_planar.g6b |
---|
0,0 → 1,5 |
{ 0x00000201, 0x20080061, 0x00000000, 0x0000e000 }, |
{ 0x00600001, 0x20200022, 0x008d0000, 0x00000000 }, |
{ 0x02800031, 0x22001cc9, 0x00000020, 0x0a2a0001 }, |
{ 0x02800031, 0x21c01cc9, 0x00000020, 0x0a2a0003 }, |
{ 0x02800031, 0x22401cc9, 0x00000020, 0x0a2a0005 }, |
/drivers/video/Intel-2D/render_program/exa_wm_src_sample_planar.g7b |
---|
0,0 → 1,5 |
{ 0x00000201, 0x20080061, 0x00000000, 0x0000e000 }, |
{ 0x00600001, 0x28200021, 0x008d0000, 0x00000000 }, |
{ 0x02800031, 0x22001ca9, 0x00000820, 0x0a2c0001 }, |
{ 0x02800031, 0x21c01ca9, 0x00000820, 0x0a2c0003 }, |
{ 0x02800031, 0x22401ca9, 0x00000820, 0x0a2c0005 }, |
/drivers/video/Intel-2D/render_program/exa_wm_write.g4b |
---|
0,0 → 1,18 |
{ 0x00600001, 0x204003be, 0x008d01c0, 0x00000000 }, |
{ 0x00600001, 0x206003be, 0x008d0200, 0x00000000 }, |
{ 0x00600001, 0x208003be, 0x008d0240, 0x00000000 }, |
{ 0x00600001, 0x20a003be, 0x008d0280, 0x00000000 }, |
{ 0x00601001, 0x20c003be, 0x008d01e0, 0x00000000 }, |
{ 0x00601001, 0x20e003be, 0x008d0220, 0x00000000 }, |
{ 0x00601001, 0x210003be, 0x008d0260, 0x00000000 }, |
{ 0x00601001, 0x212003be, 0x008d02a0, 0x00000000 }, |
{ 0x00600201, 0x20200022, 0x008d0020, 0x00000000 }, |
{ 0x00800031, 0x24001d28, 0x008d0000, 0x85a04800 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
/drivers/video/Intel-2D/render_program/exa_wm_write.g4b.gen5 |
---|
0,0 → 1,18 |
{ 0x00600001, 0x204003be, 0x008d01c0, 0x00000000 }, |
{ 0x00600001, 0x206003be, 0x008d0200, 0x00000000 }, |
{ 0x00600001, 0x208003be, 0x008d0240, 0x00000000 }, |
{ 0x00600001, 0x20a003be, 0x008d0280, 0x00000000 }, |
{ 0x00601001, 0x20c003be, 0x008d01e0, 0x00000000 }, |
{ 0x00601001, 0x20e003be, 0x008d0220, 0x00000000 }, |
{ 0x00601001, 0x210003be, 0x008d0260, 0x00000000 }, |
{ 0x00601001, 0x212003be, 0x008d02a0, 0x00000000 }, |
{ 0x00600201, 0x20200022, 0x008d0020, 0x00000000 }, |
{ 0x00800031, 0x24001d28, 0x548d0000, 0x94084800 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
/drivers/video/Intel-2D/render_program/exa_wm_write.g5b |
---|
0,0 → 1,6 |
{ 0x00802001, 0x304003be, 0x008d01c0, 0x00000000 }, |
{ 0x00802001, 0x306003be, 0x008d0200, 0x00000000 }, |
{ 0x00802001, 0x308003be, 0x008d0240, 0x00000000 }, |
{ 0x00802001, 0x30a003be, 0x008d0280, 0x00000000 }, |
{ 0x00600201, 0x202003be, 0x008d0020, 0x00000000 }, |
{ 0x00800031, 0x24001d28, 0x548d0000, 0x94084800 }, |
/drivers/video/Intel-2D/render_program/exa_wm_write.g6b |
---|
0,0 → 1,17 |
{ 0x00600001, 0x204003be, 0x008d01c0, 0x00000000 }, |
{ 0x00600001, 0x206003be, 0x008d01e0, 0x00000000 }, |
{ 0x00600001, 0x208003be, 0x008d0200, 0x00000000 }, |
{ 0x00600001, 0x20a003be, 0x008d0220, 0x00000000 }, |
{ 0x00600001, 0x20c003be, 0x008d0240, 0x00000000 }, |
{ 0x00600001, 0x20e003be, 0x008d0260, 0x00000000 }, |
{ 0x00600001, 0x210003be, 0x008d0280, 0x00000000 }, |
{ 0x00600001, 0x212003be, 0x008d02a0, 0x00000000 }, |
{ 0x05800031, 0x24001cc8, 0x00000040, 0x90019000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
/drivers/video/Intel-2D/render_program/exa_wm_write.g7b |
---|
0,0 → 1,17 |
{ 0x00600001, 0x284003bd, 0x008d01c0, 0x00000000 }, |
{ 0x00600001, 0x286003bd, 0x008d01e0, 0x00000000 }, |
{ 0x00600001, 0x288003bd, 0x008d0200, 0x00000000 }, |
{ 0x00600001, 0x28a003bd, 0x008d0220, 0x00000000 }, |
{ 0x00600001, 0x28c003bd, 0x008d0240, 0x00000000 }, |
{ 0x00600001, 0x28e003bd, 0x008d0260, 0x00000000 }, |
{ 0x00600001, 0x290003bd, 0x008d0280, 0x00000000 }, |
{ 0x00600001, 0x292003bd, 0x008d02a0, 0x00000000 }, |
{ 0x05800031, 0x24001ca8, 0x00000840, 0x90031000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, |
/drivers/video/Intel-2D/render_program/exa_wm_xy.g4b |
---|
0,0 → 1,4 |
{ 0x00800040, 0x23c06d29, 0x00480028, 0x10101010 }, |
{ 0x00800040, 0x23806d29, 0x0048002a, 0x11001100 }, |
{ 0x00802040, 0x2100753d, 0x008d03c0, 0x00004020 }, |
{ 0x00802040, 0x2140753d, 0x008d0380, 0x00004024 }, |
/drivers/video/Intel-2D/render_program/exa_wm_xy.g4b.gen5 |
---|
0,0 → 1,4 |
{ 0x00800040, 0x23c06d29, 0x00480028, 0x10101010 }, |
{ 0x00800040, 0x23806d29, 0x0048002a, 0x11001100 }, |
{ 0x00802040, 0x2100753d, 0x008d03c0, 0x00004020 }, |
{ 0x00802040, 0x2140753d, 0x008d0380, 0x00004024 }, |
/drivers/video/Intel-2D/render_program/exa_wm_xy.g5b |
---|
0,0 → 1,4 |
{ 0x00800040, 0x23c06d29, 0x00480028, 0x10101010 }, |
{ 0x00800040, 0x23806d29, 0x0048002a, 0x11001100 }, |
{ 0x00802040, 0x2100753d, 0x008d03c0, 0x00004020 }, |
{ 0x00802040, 0x2140753d, 0x008d0380, 0x00004024 }, |
/drivers/video/Intel-2D/render_program/exa_wm_yuv_rgb.g4b |
---|
0,0 → 1,12 |
{ 0x00802040, 0x23007fbd, 0x008d0200, 0xbd808081 }, |
{ 0x00802041, 0x23007fbd, 0x008d0300, 0x3f94fdf4 }, |
{ 0x00802040, 0x22c07fbd, 0x008d01c0, 0xbf008084 }, |
{ 0x00802040, 0x23407fbd, 0x008d0240, 0xbf008084 }, |
{ 0x00802001, 0x240003bc, 0x008d0300, 0x00000000 }, |
{ 0x80802048, 0x21c07fbd, 0x008d02c0, 0x3fcc49ba }, |
{ 0x00802001, 0x240003bc, 0x008d0300, 0x00000000 }, |
{ 0x00802048, 0x24007fbc, 0x008d02c0, 0xbf5020c5 }, |
{ 0x80802048, 0x22007fbd, 0x008d0340, 0xbec8b439 }, |
{ 0x00802001, 0x240003bc, 0x008d0300, 0x00000000 }, |
{ 0x80802048, 0x22407fbd, 0x008d0340, 0x40011687 }, |
{ 0x00802001, 0x228003fd, 0x00000000, 0x3f800000 }, |
/drivers/video/Intel-2D/render_program/exa_wm_yuv_rgb.g4b.gen5 |
---|
0,0 → 1,12 |
{ 0x00802040, 0x23007fbd, 0x008d0200, 0xbd808081 }, |
{ 0x00802041, 0x23007fbd, 0x008d0300, 0x3f94fdf4 }, |
{ 0x00802040, 0x22c07fbd, 0x008d01c0, 0xbf008084 }, |
{ 0x00802040, 0x23407fbd, 0x008d0240, 0xbf008084 }, |
{ 0x00802001, 0x240003bc, 0x008d0300, 0x00000000 }, |
{ 0x80802048, 0x21c07fbd, 0x008d02c0, 0x3fcc49ba }, |
{ 0x00802001, 0x240003bc, 0x008d0300, 0x00000000 }, |
{ 0x00802048, 0x24007fbc, 0x008d02c0, 0xbf5020c5 }, |
{ 0x80802048, 0x22007fbd, 0x008d0340, 0xbec8b439 }, |
{ 0x00802001, 0x240003bc, 0x008d0300, 0x00000000 }, |
{ 0x80802048, 0x22407fbd, 0x008d0340, 0x40011687 }, |
{ 0x00802001, 0x228003fd, 0x00000000, 0x3f800000 }, |
/drivers/video/Intel-2D/render_program/exa_wm_yuv_rgb.g5b |
---|
0,0 → 1,12 |
{ 0x00802040, 0x23007fbd, 0x008d0200, 0xbd808081 }, |
{ 0x00802041, 0x23007fbd, 0x008d0300, 0x3f94fdf4 }, |
{ 0x00802040, 0x22c07fbd, 0x008d01c0, 0xbf008084 }, |
{ 0x00802040, 0x23407fbd, 0x008d0240, 0xbf008084 }, |
{ 0x00802001, 0x240003bc, 0x008d0300, 0x00000000 }, |
{ 0x80802048, 0x21c07fbd, 0x008d02c0, 0x3fcc49ba }, |
{ 0x00802001, 0x240003bc, 0x008d0300, 0x00000000 }, |
{ 0x00802048, 0x24007fbc, 0x008d02c0, 0xbf5020c5 }, |
{ 0x80802048, 0x22007fbd, 0x008d0340, 0xbec8b439 }, |
{ 0x00802001, 0x240003bc, 0x008d0300, 0x00000000 }, |
{ 0x80802048, 0x22407fbd, 0x008d0340, 0x40011687 }, |
{ 0x00802001, 0x228003fd, 0x00000000, 0x3f800000 }, |
/drivers/video/Intel-2D/render_program/exa_wm_yuv_rgb.g6b |
---|
0,0 → 1,12 |
{ 0x00800040, 0x23007fbd, 0x008d0200, 0xbd808081 }, |
{ 0x00800041, 0x23007fbd, 0x008d0300, 0x3f94fdf4 }, |
{ 0x00800040, 0x22c07fbd, 0x008d01c0, 0xbf008084 }, |
{ 0x00800040, 0x23407fbd, 0x008d0240, 0xbf008084 }, |
{ 0x00800001, 0x240003bc, 0x008d0300, 0x00000000 }, |
{ 0x80800048, 0x21c07fbd, 0x008d02c0, 0x3fcc49ba }, |
{ 0x00800001, 0x240003bc, 0x008d0300, 0x00000000 }, |
{ 0x00800048, 0x24007fbc, 0x008d02c0, 0xbf5020c5 }, |
{ 0x80800048, 0x22007fbd, 0x008d0340, 0xbec8b439 }, |
{ 0x00800001, 0x240003bc, 0x008d0300, 0x00000000 }, |
{ 0x80800048, 0x22407fbd, 0x008d0340, 0x40011687 }, |
{ 0x00800001, 0x228003fd, 0x00000000, 0x3f800000 }, |
/drivers/video/Intel-2D/render_program/exa_wm_yuv_rgb.g7b |
---|
0,0 → 1,12 |
{ 0x00800040, 0x23007fbd, 0x008d0200, 0xbd808081 }, |
{ 0x00800041, 0x23007fbd, 0x008d0300, 0x3f94fdf4 }, |
{ 0x00800040, 0x22c07fbd, 0x008d01c0, 0xbf008084 }, |
{ 0x00800040, 0x23407fbd, 0x008d0240, 0xbf008084 }, |
{ 0x00800001, 0x240003bc, 0x008d0300, 0x00000000 }, |
{ 0x80800048, 0x21c07fbd, 0x008d02c0, 0x3fcc49ba }, |
{ 0x00800001, 0x240003bc, 0x008d0300, 0x00000000 }, |
{ 0x00800048, 0x24007fbc, 0x008d02c0, 0xbf5020c5 }, |
{ 0x80800048, 0x22007fbd, 0x008d0340, 0xbec8b439 }, |
{ 0x00800001, 0x240003bc, 0x008d0300, 0x00000000 }, |
{ 0x80800048, 0x22407fbd, 0x008d0340, 0x40011687 }, |
{ 0x00800001, 0x228003fd, 0x00000000, 0x3f800000 }, |
/drivers/video/Intel-2D/sna/intel.h |
---|
File deleted |
/drivers/video/Intel-2D/sna/pciaccess.h |
---|
File deleted |
/drivers/video/Intel-2D/sna/kgem.c |
---|
880,7 → 880,7 |
static bool kgem_init_pinned_batches(struct kgem *kgem) |
{ |
int count[2] = { 2, 1 }; |
int count[2] = { 2, 2 }; |
int size[2] = { 1, 2 }; |
int n, i; |
/drivers/video/Intel-2D/sna/kgem.h |
---|
398,7 → 398,7 |
if (kgem->mode == mode) |
return; |
// kgem->context_switch(kgem, mode); |
kgem->context_switch(kgem, mode); |
kgem->mode = mode; |
} |
407,7 → 407,7 |
assert(kgem->mode == KGEM_NONE); |
assert(kgem->nbatch == 0); |
assert(!kgem->wedged); |
// kgem->context_switch(kgem, mode); |
kgem->context_switch(kgem, mode); |
kgem->mode = mode; |
} |
/drivers/video/Intel-2D/sna/sna.c |
---|
39,14 → 39,14 |
#include <memory.h> |
#include <malloc.h> |
#include <kos32sys.h> |
#include <pixlib2.h> |
#include "i915_pciids.h" |
#include "compiler.h" |
#include "sna.h" |
#include "intel_driver.h" |
#include <pixlib2.h> |
#include <kos32sys.h> |
#define to_surface(x) (surface_t*)((x)->handle) |
static struct sna_fb sna_fb; |
92,8 → 92,6 |
void kgem_close_batches(struct kgem *kgem); |
void sna_bo_destroy(struct kgem *kgem, struct kgem_bo *bo); |
const struct intel_device_info * |
intel_detect_chipset(struct pci_device *pci); |
static bool sna_solid_cache_init(struct sna *sna); |
936,28 → 934,8 |
return (const struct intel_device_info*)ent->match_data; |
else |
return &intel_generic_info; |
#if 0 |
for (i = 0; intel_chipsets[i].name != NULL; i++) { |
if (DEVICE_ID(pci) == intel_chipsets[i].token) { |
name = intel_chipsets[i].name; |
break; |
} |
} |
if (name == NULL) { |
xf86DrvMsg(scrn->scrnIndex, X_WARNING, "unknown chipset\n"); |
name = "unknown"; |
} else { |
xf86DrvMsg(scrn->scrnIndex, from, |
"Integrated Graphics Chipset: Intel(R) %s\n", |
name); |
} |
scrn->chipset = name; |
#endif |
} |
int intel_get_device_id(int fd) |
{ |
struct drm_i915_getparam gp; |
/drivers/video/Intel-2D/sna/sna.h |
---|
37,12 → 37,12 |
#ifndef _SNA_H_ |
#define _SNA_H_ |
#include <stdint.h> |
#ifdef HAVE_CONFIG_H |
#include "config.h" |
#endif |
#include <stdint.h> |
#include "compiler.h" |
51,8 → 51,8 |
#include <errno.h> |
#include <kos32sys.h> |
#include "pciaccess.h" |
#include "intel_driver.h" |
#include "pciaccess.h" |
#include <drm.h> |
#include <i915_drm.h> |
382,6 → 382,7 |
struct sna_fb |
{ |
uint32_t name; |
uint32_t width; |
uint32_t height; |
uint32_t pitch; |
/drivers/video/Intel-2D/uxa/brw_defines.h |
---|
0,0 → 1,881 |
/************************************************************************** |
* |
* Copyright 2005 Tungsten Graphics, Inc., Cedar Park, Texas. |
* All Rights Reserved. |
* |
* Permission is hereby granted, free of charge, to any person obtaining a |
* copy of this software and associated documentation files (the |
* "Software"), to deal in the Software without restriction, including |
* without limitation the rights to use, copy, modify, merge, publish, |
* distribute, sub license, and/or sell copies of the Software, and to |
* permit persons to whom the Software is furnished to do so, subject to |
* the following conditions: |
* |
* The above copyright notice and this permission notice (including the |
* next paragraph) shall be included in all copies or substantial portions |
* of the Software. |
* |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
* |
**************************************************************************/ |
#ifndef BRW_DEFINES_H |
#define BRW_DEFINES_H |
/* |
*/ |
#if 0 |
#define MI_NOOP 0x00 |
#define MI_USER_INTERRUPT 0x02 |
#define MI_WAIT_FOR_EVENT 0x03 |
#define MI_FLUSH 0x04 |
#define MI_REPORT_HEAD 0x07 |
#define MI_ARB_ON_OFF 0x08 |
#define MI_BATCH_BUFFER_END 0x0A |
#define MI_OVERLAY_FLIP 0x11 |
#define MI_LOAD_SCAN_LINES_INCL 0x12 |
#define MI_LOAD_SCAN_LINES_EXCL 0x13 |
#define MI_DISPLAY_BUFFER_INFO 0x14 |
#define MI_SET_CONTEXT 0x18 |
#define MI_STORE_DATA_IMM 0x20 |
#define MI_STORE_DATA_INDEX 0x21 |
#define MI_LOAD_REGISTER_IMM 0x22 |
#define MI_STORE_REGISTER_MEM 0x24 |
#define MI_BATCH_BUFFER_START 0x31 |
#define MI_SYNCHRONOUS_FLIP 0x0 |
#define MI_ASYNCHRONOUS_FLIP 0x1 |
#define MI_BUFFER_SECURE 0x0 |
#define MI_BUFFER_NONSECURE 0x1 |
#define MI_ARBITRATE_AT_CHAIN_POINTS 0x0 |
#define MI_ARBITRATE_BETWEEN_INSTS 0x1 |
#define MI_NO_ARBITRATION 0x3 |
#define MI_CONDITION_CODE_WAIT_DISABLED 0x0 |
#define MI_CONDITION_CODE_WAIT_0 0x1 |
#define MI_CONDITION_CODE_WAIT_1 0x2 |
#define MI_CONDITION_CODE_WAIT_2 0x3 |
#define MI_CONDITION_CODE_WAIT_3 0x4 |
#define MI_CONDITION_CODE_WAIT_4 0x5 |
#define MI_DISPLAY_PIPE_A 0x0 |
#define MI_DISPLAY_PIPE_B 0x1 |
#define MI_DISPLAY_PLANE_A 0x0 |
#define MI_DISPLAY_PLANE_B 0x1 |
#define MI_DISPLAY_PLANE_C 0x2 |
#define MI_STANDARD_FLIP 0x0 |
#define MI_ENQUEUE_FLIP_PERFORM_BASE_FRAME_NUMBER_LOAD 0x1 |
#define MI_ENQUEUE_FLIP_TARGET_FRAME_NUMBER_RELATIVE 0x2 |
#define MI_ENQUEUE_FLIP_ABSOLUTE_TARGET_FRAME_NUMBER 0x3 |
#define MI_PHYSICAL_ADDRESS 0x0 |
#define MI_VIRTUAL_ADDRESS 0x1 |
#define MI_BUFFER_MEMORY_MAIN 0x0 |
#define MI_BUFFER_MEMORY_GTT 0x2 |
#define MI_BUFFER_MEMORY_PER_PROCESS_GTT 0x3 |
#define MI_FLIP_CONTINUE 0x0 |
#define MI_FLIP_ON 0x1 |
#define MI_FLIP_OFF 0x2 |
#define MI_UNTRUSTED_REGISTER_SPACE 0x0 |
#define MI_TRUSTED_REGISTER_SPACE 0x1 |
#endif |
/* 3D state: |
*/ |
#define _3DOP_3DSTATE_PIPELINED 0x0 |
#define _3DOP_3DSTATE_NONPIPELINED 0x1 |
#define _3DOP_3DCONTROL 0x2 |
#define _3DOP_3DPRIMITIVE 0x3 |
#define _3DSTATE_PIPELINED_POINTERS 0x00 |
#define _3DSTATE_BINDING_TABLE_POINTERS 0x01 |
#define _3DSTATE_VERTEX_BUFFERS 0x08 |
#define _3DSTATE_VERTEX_ELEMENTS 0x09 |
#define _3DSTATE_INDEX_BUFFER 0x0A |
#define _3DSTATE_VF_STATISTICS 0x0B |
#define _3DSTATE_DRAWING_RECTANGLE 0x00 |
#define _3DSTATE_CONSTANT_COLOR 0x01 |
#define _3DSTATE_SAMPLER_PALETTE_LOAD 0x02 |
#define _3DSTATE_CHROMA_KEY 0x04 |
#define _3DSTATE_DEPTH_BUFFER 0x05 |
#define _3DSTATE_POLY_STIPPLE_OFFSET 0x06 |
#define _3DSTATE_POLY_STIPPLE_PATTERN 0x07 |
#define _3DSTATE_LINE_STIPPLE 0x08 |
#define _3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP 0x09 |
#define _3DCONTROL 0x00 |
#define _3DPRIMITIVE 0x00 |
#define PIPE_CONTROL_NOWRITE 0x00 |
#define PIPE_CONTROL_WRITEIMMEDIATE 0x01 |
#define PIPE_CONTROL_WRITEDEPTH 0x02 |
#define PIPE_CONTROL_WRITETIMESTAMP 0x03 |
#define PIPE_CONTROL_GTTWRITE_PROCESS_LOCAL 0x00 |
#define PIPE_CONTROL_GTTWRITE_GLOBAL 0x01 |
#define _3DPRIM_POINTLIST 0x01 |
#define _3DPRIM_LINELIST 0x02 |
#define _3DPRIM_LINESTRIP 0x03 |
#define _3DPRIM_TRILIST 0x04 |
#define _3DPRIM_TRISTRIP 0x05 |
#define _3DPRIM_TRIFAN 0x06 |
#define _3DPRIM_QUADLIST 0x07 |
#define _3DPRIM_QUADSTRIP 0x08 |
#define _3DPRIM_LINELIST_ADJ 0x09 |
#define _3DPRIM_LINESTRIP_ADJ 0x0A |
#define _3DPRIM_TRILIST_ADJ 0x0B |
#define _3DPRIM_TRISTRIP_ADJ 0x0C |
#define _3DPRIM_TRISTRIP_REVERSE 0x0D |
#define _3DPRIM_POLYGON 0x0E |
#define _3DPRIM_RECTLIST 0x0F |
#define _3DPRIM_LINELOOP 0x10 |
#define _3DPRIM_POINTLIST_BF 0x11 |
#define _3DPRIM_LINESTRIP_CONT 0x12 |
#define _3DPRIM_LINESTRIP_BF 0x13 |
#define _3DPRIM_LINESTRIP_CONT_BF 0x14 |
#define _3DPRIM_TRIFAN_NOSTIPPLE 0x15 |
#define _3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL 0 |
#define _3DPRIM_VERTEXBUFFER_ACCESS_RANDOM 1 |
#define BRW_ANISORATIO_2 0 |
#define BRW_ANISORATIO_4 1 |
#define BRW_ANISORATIO_6 2 |
#define BRW_ANISORATIO_8 3 |
#define BRW_ANISORATIO_10 4 |
#define BRW_ANISORATIO_12 5 |
#define BRW_ANISORATIO_14 6 |
#define BRW_ANISORATIO_16 7 |
#define BRW_BLENDFACTOR_ONE 0x1 |
#define BRW_BLENDFACTOR_SRC_COLOR 0x2 |
#define BRW_BLENDFACTOR_SRC_ALPHA 0x3 |
#define BRW_BLENDFACTOR_DST_ALPHA 0x4 |
#define BRW_BLENDFACTOR_DST_COLOR 0x5 |
#define BRW_BLENDFACTOR_SRC_ALPHA_SATURATE 0x6 |
#define BRW_BLENDFACTOR_CONST_COLOR 0x7 |
#define BRW_BLENDFACTOR_CONST_ALPHA 0x8 |
#define BRW_BLENDFACTOR_SRC1_COLOR 0x9 |
#define BRW_BLENDFACTOR_SRC1_ALPHA 0x0A |
#define BRW_BLENDFACTOR_ZERO 0x11 |
#define BRW_BLENDFACTOR_INV_SRC_COLOR 0x12 |
#define BRW_BLENDFACTOR_INV_SRC_ALPHA 0x13 |
#define BRW_BLENDFACTOR_INV_DST_ALPHA 0x14 |
#define BRW_BLENDFACTOR_INV_DST_COLOR 0x15 |
#define BRW_BLENDFACTOR_INV_CONST_COLOR 0x17 |
#define BRW_BLENDFACTOR_INV_CONST_ALPHA 0x18 |
#define BRW_BLENDFACTOR_INV_SRC1_COLOR 0x19 |
#define BRW_BLENDFACTOR_INV_SRC1_ALPHA 0x1A |
#define BRW_BLENDFUNCTION_ADD 0 |
#define BRW_BLENDFUNCTION_SUBTRACT 1 |
#define BRW_BLENDFUNCTION_REVERSE_SUBTRACT 2 |
#define BRW_BLENDFUNCTION_MIN 3 |
#define BRW_BLENDFUNCTION_MAX 4 |
#define BRW_ALPHATEST_FORMAT_UNORM8 0 |
#define BRW_ALPHATEST_FORMAT_FLOAT32 1 |
#define BRW_CHROMAKEY_KILL_ON_ANY_MATCH 0 |
#define BRW_CHROMAKEY_REPLACE_BLACK 1 |
#define BRW_CLIP_API_OGL 0 |
#define BRW_CLIP_API_DX 1 |
#define BRW_CLIPMODE_NORMAL 0 |
#define BRW_CLIPMODE_CLIP_ALL 1 |
#define BRW_CLIPMODE_CLIP_NON_REJECTED 2 |
#define BRW_CLIPMODE_REJECT_ALL 3 |
#define BRW_CLIPMODE_ACCEPT_ALL 4 |
#define BRW_CLIP_NDCSPACE 0 |
#define BRW_CLIP_SCREENSPACE 1 |
#define BRW_COMPAREFUNCTION_ALWAYS 0 |
#define BRW_COMPAREFUNCTION_NEVER 1 |
#define BRW_COMPAREFUNCTION_LESS 2 |
#define BRW_COMPAREFUNCTION_EQUAL 3 |
#define BRW_COMPAREFUNCTION_LEQUAL 4 |
#define BRW_COMPAREFUNCTION_GREATER 5 |
#define BRW_COMPAREFUNCTION_NOTEQUAL 6 |
#define BRW_COMPAREFUNCTION_GEQUAL 7 |
#define BRW_COVERAGE_PIXELS_HALF 0 |
#define BRW_COVERAGE_PIXELS_1 1 |
#define BRW_COVERAGE_PIXELS_2 2 |
#define BRW_COVERAGE_PIXELS_4 3 |
#define BRW_CULLMODE_BOTH 0 |
#define BRW_CULLMODE_NONE 1 |
#define BRW_CULLMODE_FRONT 2 |
#define BRW_CULLMODE_BACK 3 |
#define BRW_DEFAULTCOLOR_R8G8B8A8_UNORM 0 |
#define BRW_DEFAULTCOLOR_R32G32B32A32_FLOAT 1 |
#define BRW_DEPTHFORMAT_D32_FLOAT_S8X24_UINT 0 |
#define BRW_DEPTHFORMAT_D32_FLOAT 1 |
#define BRW_DEPTHFORMAT_D24_UNORM_S8_UINT 2 |
#define BRW_DEPTHFORMAT_D16_UNORM 5 |
#define BRW_FLOATING_POINT_IEEE_754 0 |
#define BRW_FLOATING_POINT_NON_IEEE_754 1 |
#define BRW_FRONTWINDING_CW 0 |
#define BRW_FRONTWINDING_CCW 1 |
#define BRW_INDEX_BYTE 0 |
#define BRW_INDEX_WORD 1 |
#define BRW_INDEX_DWORD 2 |
#define BRW_LOGICOPFUNCTION_CLEAR 0 |
#define BRW_LOGICOPFUNCTION_NOR 1 |
#define BRW_LOGICOPFUNCTION_AND_INVERTED 2 |
#define BRW_LOGICOPFUNCTION_COPY_INVERTED 3 |
#define BRW_LOGICOPFUNCTION_AND_REVERSE 4 |
#define BRW_LOGICOPFUNCTION_INVERT 5 |
#define BRW_LOGICOPFUNCTION_XOR 6 |
#define BRW_LOGICOPFUNCTION_NAND 7 |
#define BRW_LOGICOPFUNCTION_AND 8 |
#define BRW_LOGICOPFUNCTION_EQUIV 9 |
#define BRW_LOGICOPFUNCTION_NOOP 10 |
#define BRW_LOGICOPFUNCTION_OR_INVERTED 11 |
#define BRW_LOGICOPFUNCTION_COPY 12 |
#define BRW_LOGICOPFUNCTION_OR_REVERSE 13 |
#define BRW_LOGICOPFUNCTION_OR 14 |
#define BRW_LOGICOPFUNCTION_SET 15 |
#define BRW_MAPFILTER_NEAREST 0x0 |
#define BRW_MAPFILTER_LINEAR 0x1 |
#define BRW_MAPFILTER_ANISOTROPIC 0x2 |
#define BRW_MIPFILTER_NONE 0 |
#define BRW_MIPFILTER_NEAREST 1 |
#define BRW_MIPFILTER_LINEAR 3 |
#define BRW_POLYGON_FRONT_FACING 0 |
#define BRW_POLYGON_BACK_FACING 1 |
#define BRW_PREFILTER_ALWAYS 0x0 |
#define BRW_PREFILTER_NEVER 0x1 |
#define BRW_PREFILTER_LESS 0x2 |
#define BRW_PREFILTER_EQUAL 0x3 |
#define BRW_PREFILTER_LEQUAL 0x4 |
#define BRW_PREFILTER_GREATER 0x5 |
#define BRW_PREFILTER_NOTEQUAL 0x6 |
#define BRW_PREFILTER_GEQUAL 0x7 |
#define BRW_PROVOKING_VERTEX_0 0 |
#define BRW_PROVOKING_VERTEX_1 1 |
#define BRW_PROVOKING_VERTEX_2 2 |
#define BRW_RASTRULE_UPPER_LEFT 0 |
#define BRW_RASTRULE_UPPER_RIGHT 1 |
#define BRW_RENDERTARGET_CLAMPRANGE_UNORM 0 |
#define BRW_RENDERTARGET_CLAMPRANGE_SNORM 1 |
#define BRW_RENDERTARGET_CLAMPRANGE_FORMAT 2 |
#define BRW_STENCILOP_KEEP 0 |
#define BRW_STENCILOP_ZERO 1 |
#define BRW_STENCILOP_REPLACE 2 |
#define BRW_STENCILOP_INCRSAT 3 |
#define BRW_STENCILOP_DECRSAT 4 |
#define BRW_STENCILOP_INCR 5 |
#define BRW_STENCILOP_DECR 6 |
#define BRW_STENCILOP_INVERT 7 |
#define BRW_SURFACE_MIPMAPLAYOUT_BELOW 0 |
#define BRW_SURFACE_MIPMAPLAYOUT_RIGHT 1 |
#define BRW_SURFACEFORMAT_R32G32B32A32_FLOAT 0x000 |
#define BRW_SURFACEFORMAT_R32G32B32A32_SINT 0x001 |
#define BRW_SURFACEFORMAT_R32G32B32A32_UINT 0x002 |
#define BRW_SURFACEFORMAT_R32G32B32A32_UNORM 0x003 |
#define BRW_SURFACEFORMAT_R32G32B32A32_SNORM 0x004 |
#define BRW_SURFACEFORMAT_R64G64_FLOAT 0x005 |
#define BRW_SURFACEFORMAT_R32G32B32X32_FLOAT 0x006 |
#define BRW_SURFACEFORMAT_R32G32B32A32_SSCALED 0x007 |
#define BRW_SURFACEFORMAT_R32G32B32A32_USCALED 0x008 |
#define BRW_SURFACEFORMAT_R32G32B32_FLOAT 0x040 |
#define BRW_SURFACEFORMAT_R32G32B32_SINT 0x041 |
#define BRW_SURFACEFORMAT_R32G32B32_UINT 0x042 |
#define BRW_SURFACEFORMAT_R32G32B32_UNORM 0x043 |
#define BRW_SURFACEFORMAT_R32G32B32_SNORM 0x044 |
#define BRW_SURFACEFORMAT_R32G32B32_SSCALED 0x045 |
#define BRW_SURFACEFORMAT_R32G32B32_USCALED 0x046 |
#define BRW_SURFACEFORMAT_R16G16B16A16_UNORM 0x080 |
#define BRW_SURFACEFORMAT_R16G16B16A16_SNORM 0x081 |
#define BRW_SURFACEFORMAT_R16G16B16A16_SINT 0x082 |
#define BRW_SURFACEFORMAT_R16G16B16A16_UINT 0x083 |
#define BRW_SURFACEFORMAT_R16G16B16A16_FLOAT 0x084 |
#define BRW_SURFACEFORMAT_R32G32_FLOAT 0x085 |
#define BRW_SURFACEFORMAT_R32G32_SINT 0x086 |
#define BRW_SURFACEFORMAT_R32G32_UINT 0x087 |
#define BRW_SURFACEFORMAT_R32_FLOAT_X8X24_TYPELESS 0x088 |
#define BRW_SURFACEFORMAT_X32_TYPELESS_G8X24_UINT 0x089 |
#define BRW_SURFACEFORMAT_L32A32_FLOAT 0x08A |
#define BRW_SURFACEFORMAT_R32G32_UNORM 0x08B |
#define BRW_SURFACEFORMAT_R32G32_SNORM 0x08C |
#define BRW_SURFACEFORMAT_R64_FLOAT 0x08D |
#define BRW_SURFACEFORMAT_R16G16B16X16_UNORM 0x08E |
#define BRW_SURFACEFORMAT_R16G16B16X16_FLOAT 0x08F |
#define BRW_SURFACEFORMAT_A32X32_FLOAT 0x090 |
#define BRW_SURFACEFORMAT_L32X32_FLOAT 0x091 |
#define BRW_SURFACEFORMAT_I32X32_FLOAT 0x092 |
#define BRW_SURFACEFORMAT_R16G16B16A16_SSCALED 0x093 |
#define BRW_SURFACEFORMAT_R16G16B16A16_USCALED 0x094 |
#define BRW_SURFACEFORMAT_R32G32_SSCALED 0x095 |
#define BRW_SURFACEFORMAT_R32G32_USCALED 0x096 |
#define BRW_SURFACEFORMAT_B8G8R8A8_UNORM 0x0C0 |
#define BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB 0x0C1 |
#define BRW_SURFACEFORMAT_R10G10B10A2_UNORM 0x0C2 |
#define BRW_SURFACEFORMAT_R10G10B10A2_UNORM_SRGB 0x0C3 |
#define BRW_SURFACEFORMAT_R10G10B10A2_UINT 0x0C4 |
#define BRW_SURFACEFORMAT_R10G10B10_SNORM_A2_UNORM 0x0C5 |
#define BRW_SURFACEFORMAT_R8G8B8A8_UNORM 0x0C7 |
#define BRW_SURFACEFORMAT_R8G8B8A8_UNORM_SRGB 0x0C8 |
#define BRW_SURFACEFORMAT_R8G8B8A8_SNORM 0x0C9 |
#define BRW_SURFACEFORMAT_R8G8B8A8_SINT 0x0CA |
#define BRW_SURFACEFORMAT_R8G8B8A8_UINT 0x0CB |
#define BRW_SURFACEFORMAT_R16G16_UNORM 0x0CC |
#define BRW_SURFACEFORMAT_R16G16_SNORM 0x0CD |
#define BRW_SURFACEFORMAT_R16G16_SINT 0x0CE |
#define BRW_SURFACEFORMAT_R16G16_UINT 0x0CF |
#define BRW_SURFACEFORMAT_R16G16_FLOAT 0x0D0 |
#define BRW_SURFACEFORMAT_B10G10R10A2_UNORM 0x0D1 |
#define BRW_SURFACEFORMAT_B10G10R10A2_UNORM_SRGB 0x0D2 |
#define BRW_SURFACEFORMAT_R11G11B10_FLOAT 0x0D3 |
#define BRW_SURFACEFORMAT_R32_SINT 0x0D6 |
#define BRW_SURFACEFORMAT_R32_UINT 0x0D7 |
#define BRW_SURFACEFORMAT_R32_FLOAT 0x0D8 |
#define BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS 0x0D9 |
#define BRW_SURFACEFORMAT_X24_TYPELESS_G8_UINT 0x0DA |
#define BRW_SURFACEFORMAT_L16A16_UNORM 0x0DF |
#define BRW_SURFACEFORMAT_I24X8_UNORM 0x0E0 |
#define BRW_SURFACEFORMAT_L24X8_UNORM 0x0E1 |
#define BRW_SURFACEFORMAT_A24X8_UNORM 0x0E2 |
#define BRW_SURFACEFORMAT_I32_FLOAT 0x0E3 |
#define BRW_SURFACEFORMAT_L32_FLOAT 0x0E4 |
#define BRW_SURFACEFORMAT_A32_FLOAT 0x0E5 |
#define BRW_SURFACEFORMAT_B8G8R8X8_UNORM 0x0E9 |
#define BRW_SURFACEFORMAT_B8G8R8X8_UNORM_SRGB 0x0EA |
#define BRW_SURFACEFORMAT_R8G8B8X8_UNORM 0x0EB |
#define BRW_SURFACEFORMAT_R8G8B8X8_UNORM_SRGB 0x0EC |
#define BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP 0x0ED |
#define BRW_SURFACEFORMAT_B10G10R10X2_UNORM 0x0EE |
#define BRW_SURFACEFORMAT_L16A16_FLOAT 0x0F0 |
#define BRW_SURFACEFORMAT_R32_UNORM 0x0F1 |
#define BRW_SURFACEFORMAT_R32_SNORM 0x0F2 |
#define BRW_SURFACEFORMAT_R10G10B10X2_USCALED 0x0F3 |
#define BRW_SURFACEFORMAT_R8G8B8A8_SSCALED 0x0F4 |
#define BRW_SURFACEFORMAT_R8G8B8A8_USCALED 0x0F5 |
#define BRW_SURFACEFORMAT_R16G16_SSCALED 0x0F6 |
#define BRW_SURFACEFORMAT_R16G16_USCALED 0x0F7 |
#define BRW_SURFACEFORMAT_R32_SSCALED 0x0F8 |
#define BRW_SURFACEFORMAT_R32_USCALED 0x0F9 |
#define BRW_SURFACEFORMAT_B5G6R5_UNORM 0x100 |
#define BRW_SURFACEFORMAT_B5G6R5_UNORM_SRGB 0x101 |
#define BRW_SURFACEFORMAT_B5G5R5A1_UNORM 0x102 |
#define BRW_SURFACEFORMAT_B5G5R5A1_UNORM_SRGB 0x103 |
#define BRW_SURFACEFORMAT_B4G4R4A4_UNORM 0x104 |
#define BRW_SURFACEFORMAT_B4G4R4A4_UNORM_SRGB 0x105 |
#define BRW_SURFACEFORMAT_R8G8_UNORM 0x106 |
#define BRW_SURFACEFORMAT_R8G8_SNORM 0x107 |
#define BRW_SURFACEFORMAT_R8G8_SINT 0x108 |
#define BRW_SURFACEFORMAT_R8G8_UINT 0x109 |
#define BRW_SURFACEFORMAT_R16_UNORM 0x10A |
#define BRW_SURFACEFORMAT_R16_SNORM 0x10B |
#define BRW_SURFACEFORMAT_R16_SINT 0x10C |
#define BRW_SURFACEFORMAT_R16_UINT 0x10D |
#define BRW_SURFACEFORMAT_R16_FLOAT 0x10E |
#define BRW_SURFACEFORMAT_I16_UNORM 0x111 |
#define BRW_SURFACEFORMAT_L16_UNORM 0x112 |
#define BRW_SURFACEFORMAT_A16_UNORM 0x113 |
#define BRW_SURFACEFORMAT_L8A8_UNORM 0x114 |
#define BRW_SURFACEFORMAT_I16_FLOAT 0x115 |
#define BRW_SURFACEFORMAT_L16_FLOAT 0x116 |
#define BRW_SURFACEFORMAT_A16_FLOAT 0x117 |
#define BRW_SURFACEFORMAT_R5G5_SNORM_B6_UNORM 0x119 |
#define BRW_SURFACEFORMAT_B5G5R5X1_UNORM 0x11A |
#define BRW_SURFACEFORMAT_B5G5R5X1_UNORM_SRGB 0x11B |
#define BRW_SURFACEFORMAT_R8G8_SSCALED 0x11C |
#define BRW_SURFACEFORMAT_R8G8_USCALED 0x11D |
#define BRW_SURFACEFORMAT_R16_SSCALED 0x11E |
#define BRW_SURFACEFORMAT_R16_USCALED 0x11F |
#define BRW_SURFACEFORMAT_R8_UNORM 0x140 |
#define BRW_SURFACEFORMAT_R8_SNORM 0x141 |
#define BRW_SURFACEFORMAT_R8_SINT 0x142 |
#define BRW_SURFACEFORMAT_R8_UINT 0x143 |
#define BRW_SURFACEFORMAT_A8_UNORM 0x144 |
#define BRW_SURFACEFORMAT_I8_UNORM 0x145 |
#define BRW_SURFACEFORMAT_L8_UNORM 0x146 |
#define BRW_SURFACEFORMAT_P4A4_UNORM 0x147 |
#define BRW_SURFACEFORMAT_A4P4_UNORM 0x148 |
#define BRW_SURFACEFORMAT_R8_SSCALED 0x149 |
#define BRW_SURFACEFORMAT_R8_USCALED 0x14A |
#define BRW_SURFACEFORMAT_R1_UINT 0x181 |
#define BRW_SURFACEFORMAT_YCRCB_NORMAL 0x182 |
#define BRW_SURFACEFORMAT_YCRCB_SWAPUVY 0x183 |
#define BRW_SURFACEFORMAT_BC1_UNORM 0x186 |
#define BRW_SURFACEFORMAT_BC2_UNORM 0x187 |
#define BRW_SURFACEFORMAT_BC3_UNORM 0x188 |
#define BRW_SURFACEFORMAT_BC4_UNORM 0x189 |
#define BRW_SURFACEFORMAT_BC5_UNORM 0x18A |
#define BRW_SURFACEFORMAT_BC1_UNORM_SRGB 0x18B |
#define BRW_SURFACEFORMAT_BC2_UNORM_SRGB 0x18C |
#define BRW_SURFACEFORMAT_BC3_UNORM_SRGB 0x18D |
#define BRW_SURFACEFORMAT_MONO8 0x18E |
#define BRW_SURFACEFORMAT_YCRCB_SWAPUV 0x18F |
#define BRW_SURFACEFORMAT_YCRCB_SWAPY 0x190 |
#define BRW_SURFACEFORMAT_DXT1_RGB 0x191 |
#define BRW_SURFACEFORMAT_FXT1 0x192 |
#define BRW_SURFACEFORMAT_R8G8B8_UNORM 0x193 |
#define BRW_SURFACEFORMAT_R8G8B8_SNORM 0x194 |
#define BRW_SURFACEFORMAT_R8G8B8_SSCALED 0x195 |
#define BRW_SURFACEFORMAT_R8G8B8_USCALED 0x196 |
#define BRW_SURFACEFORMAT_R64G64B64A64_FLOAT 0x197 |
#define BRW_SURFACEFORMAT_R64G64B64_FLOAT 0x198 |
#define BRW_SURFACEFORMAT_BC4_SNORM 0x199 |
#define BRW_SURFACEFORMAT_BC5_SNORM 0x19A |
#define BRW_SURFACEFORMAT_R16G16B16_UNORM 0x19C |
#define BRW_SURFACEFORMAT_R16G16B16_SNORM 0x19D |
#define BRW_SURFACEFORMAT_R16G16B16_SSCALED 0x19E |
#define BRW_SURFACEFORMAT_R16G16B16_USCALED 0x19F |
#define BRW_SURFACERETURNFORMAT_FLOAT32 0 |
#define BRW_SURFACERETURNFORMAT_S1 1 |
#define BRW_SURFACE_1D 0 |
#define BRW_SURFACE_2D 1 |
#define BRW_SURFACE_3D 2 |
#define BRW_SURFACE_CUBE 3 |
#define BRW_SURFACE_BUFFER 4 |
#define BRW_SURFACE_NULL 7 |
#define BRW_BORDER_COLOR_MODE_DEFAULT 0 |
#define BRW_BORDER_COLOR_MODE_LEGACY 1 |
#define HSW_SCS_ZERO 0 |
#define HSW_SCS_ONE 1 |
#define HSW_SCS_RED 4 |
#define HSW_SCS_GREEN 5 |
#define HSW_SCS_BLUE 6 |
#define HSW_SCS_ALPHA 7 |
#define BRW_TEXCOORDMODE_WRAP 0 |
#define BRW_TEXCOORDMODE_MIRROR 1 |
#define BRW_TEXCOORDMODE_CLAMP 2 |
#define BRW_TEXCOORDMODE_CUBE 3 |
#define BRW_TEXCOORDMODE_CLAMP_BORDER 4 |
#define BRW_TEXCOORDMODE_MIRROR_ONCE 5 |
#define BRW_THREAD_PRIORITY_NORMAL 0 |
#define BRW_THREAD_PRIORITY_HIGH 1 |
#define BRW_TILEWALK_XMAJOR 0 |
#define BRW_TILEWALK_YMAJOR 1 |
#define BRW_VERTEX_SUBPIXEL_PRECISION_8BITS 0 |
#define BRW_VERTEX_SUBPIXEL_PRECISION_4BITS 1 |
#define BRW_VERTEXBUFFER_ACCESS_VERTEXDATA 0 |
#define BRW_VERTEXBUFFER_ACCESS_INSTANCEDATA 1 |
#define BRW_VFCOMPONENT_NOSTORE 0 |
#define BRW_VFCOMPONENT_STORE_SRC 1 |
#define BRW_VFCOMPONENT_STORE_0 2 |
#define BRW_VFCOMPONENT_STORE_1_FLT 3 |
#define BRW_VFCOMPONENT_STORE_1_INT 4 |
#define BRW_VFCOMPONENT_STORE_VID 5 |
#define BRW_VFCOMPONENT_STORE_IID 6 |
#define BRW_VFCOMPONENT_STORE_PID 7 |
/* Execution Unit (EU) defines |
*/ |
#define BRW_ALIGN_1 0 |
#define BRW_ALIGN_16 1 |
#define BRW_ADDRESS_DIRECT 0 |
#define BRW_ADDRESS_REGISTER_INDIRECT_REGISTER 1 |
#define BRW_CHANNEL_X 0 |
#define BRW_CHANNEL_Y 1 |
#define BRW_CHANNEL_Z 2 |
#define BRW_CHANNEL_W 3 |
#define BRW_COMPRESSION_NONE 0 |
#define BRW_COMPRESSION_2NDHALF 1 |
#define BRW_COMPRESSION_COMPRESSED 2 |
#define BRW_CONDITIONAL_NONE 0 |
#define BRW_CONDITIONAL_Z 1 |
#define BRW_CONDITIONAL_NZ 2 |
#define BRW_CONDITIONAL_EQ 1 /* Z */ |
#define BRW_CONDITIONAL_NEQ 2 /* NZ */ |
#define BRW_CONDITIONAL_G 3 |
#define BRW_CONDITIONAL_GE 4 |
#define BRW_CONDITIONAL_L 5 |
#define BRW_CONDITIONAL_LE 6 |
#define BRW_CONDITIONAL_C 7 |
#define BRW_CONDITIONAL_O 8 |
#define BRW_DEBUG_NONE 0 |
#define BRW_DEBUG_BREAKPOINT 1 |
#define BRW_DEPENDENCY_NORMAL 0 |
#define BRW_DEPENDENCY_NOTCLEARED 1 |
#define BRW_DEPENDENCY_NOTCHECKED 2 |
#define BRW_DEPENDENCY_DISABLE 3 |
#define BRW_EXECUTE_1 0 |
#define BRW_EXECUTE_2 1 |
#define BRW_EXECUTE_4 2 |
#define BRW_EXECUTE_8 3 |
#define BRW_EXECUTE_16 4 |
#define BRW_EXECUTE_32 5 |
#define BRW_HORIZONTAL_STRIDE_0 0 |
#define BRW_HORIZONTAL_STRIDE_1 1 |
#define BRW_HORIZONTAL_STRIDE_2 2 |
#define BRW_HORIZONTAL_STRIDE_4 3 |
#define BRW_INSTRUCTION_NORMAL 0 |
#define BRW_INSTRUCTION_SATURATE 1 |
#define BRW_MASK_ENABLE 0 |
#define BRW_MASK_DISABLE 1 |
#define BRW_OPCODE_MOV 1 |
#define BRW_OPCODE_SEL 2 |
#define BRW_OPCODE_NOT 4 |
#define BRW_OPCODE_AND 5 |
#define BRW_OPCODE_OR 6 |
#define BRW_OPCODE_XOR 7 |
#define BRW_OPCODE_SHR 8 |
#define BRW_OPCODE_SHL 9 |
#define BRW_OPCODE_RSR 10 |
#define BRW_OPCODE_RSL 11 |
#define BRW_OPCODE_ASR 12 |
#define BRW_OPCODE_CMP 16 |
#define BRW_OPCODE_JMPI 32 |
#define BRW_OPCODE_IF 34 |
#define BRW_OPCODE_IFF 35 |
#define BRW_OPCODE_ELSE 36 |
#define BRW_OPCODE_ENDIF 37 |
#define BRW_OPCODE_DO 38 |
#define BRW_OPCODE_WHILE 39 |
#define BRW_OPCODE_BREAK 40 |
#define BRW_OPCODE_CONTINUE 41 |
#define BRW_OPCODE_HALT 42 |
#define BRW_OPCODE_MSAVE 44 |
#define BRW_OPCODE_MRESTORE 45 |
#define BRW_OPCODE_PUSH 46 |
#define BRW_OPCODE_POP 47 |
#define BRW_OPCODE_WAIT 48 |
#define BRW_OPCODE_SEND 49 |
#define BRW_OPCODE_ADD 64 |
#define BRW_OPCODE_MUL 65 |
#define BRW_OPCODE_AVG 66 |
#define BRW_OPCODE_FRC 67 |
#define BRW_OPCODE_RNDU 68 |
#define BRW_OPCODE_RNDD 69 |
#define BRW_OPCODE_RNDE 70 |
#define BRW_OPCODE_RNDZ 71 |
#define BRW_OPCODE_MAC 72 |
#define BRW_OPCODE_MACH 73 |
#define BRW_OPCODE_LZD 74 |
#define BRW_OPCODE_SAD2 80 |
#define BRW_OPCODE_SADA2 81 |
#define BRW_OPCODE_DP4 84 |
#define BRW_OPCODE_DPH 85 |
#define BRW_OPCODE_DP3 86 |
#define BRW_OPCODE_DP2 87 |
#define BRW_OPCODE_DPA2 88 |
#define BRW_OPCODE_LINE 89 |
#define BRW_OPCODE_NOP 126 |
#define BRW_PREDICATE_NONE 0 |
#define BRW_PREDICATE_NORMAL 1 |
#define BRW_PREDICATE_ALIGN1_ANYV 2 |
#define BRW_PREDICATE_ALIGN1_ALLV 3 |
#define BRW_PREDICATE_ALIGN1_ANY2H 4 |
#define BRW_PREDICATE_ALIGN1_ALL2H 5 |
#define BRW_PREDICATE_ALIGN1_ANY4H 6 |
#define BRW_PREDICATE_ALIGN1_ALL4H 7 |
#define BRW_PREDICATE_ALIGN1_ANY8H 8 |
#define BRW_PREDICATE_ALIGN1_ALL8H 9 |
#define BRW_PREDICATE_ALIGN1_ANY16H 10 |
#define BRW_PREDICATE_ALIGN1_ALL16H 11 |
#define BRW_PREDICATE_ALIGN16_REPLICATE_X 2 |
#define BRW_PREDICATE_ALIGN16_REPLICATE_Y 3 |
#define BRW_PREDICATE_ALIGN16_REPLICATE_Z 4 |
#define BRW_PREDICATE_ALIGN16_REPLICATE_W 5 |
#define BRW_PREDICATE_ALIGN16_ANY4H 6 |
#define BRW_PREDICATE_ALIGN16_ALL4H 7 |
#define BRW_ARCHITECTURE_REGISTER_FILE 0 |
#define BRW_GENERAL_REGISTER_FILE 1 |
#define BRW_MESSAGE_REGISTER_FILE 2 |
#define BRW_IMMEDIATE_VALUE 3 |
#define BRW_REGISTER_TYPE_UD 0 |
#define BRW_REGISTER_TYPE_D 1 |
#define BRW_REGISTER_TYPE_UW 2 |
#define BRW_REGISTER_TYPE_W 3 |
#define BRW_REGISTER_TYPE_UB 4 |
#define BRW_REGISTER_TYPE_B 5 |
#define BRW_REGISTER_TYPE_VF 5 /* packed float vector, immediates only? */ |
#define BRW_REGISTER_TYPE_HF 6 |
#define BRW_REGISTER_TYPE_V 6 /* packed int vector, immediates only, uword dest only */ |
#define BRW_REGISTER_TYPE_F 7 |
#define BRW_ARF_NULL 0x00 |
#define BRW_ARF_ADDRESS 0x10 |
#define BRW_ARF_ACCUMULATOR 0x20 |
#define BRW_ARF_FLAG 0x30 |
#define BRW_ARF_MASK 0x40 |
#define BRW_ARF_MASK_STACK 0x50 |
#define BRW_ARF_MASK_STACK_DEPTH 0x60 |
#define BRW_ARF_STATE 0x70 |
#define BRW_ARF_CONTROL 0x80 |
#define BRW_ARF_NOTIFICATION_COUNT 0x90 |
#define BRW_ARF_IP 0xA0 |
#define BRW_AMASK 0 |
#define BRW_IMASK 1 |
#define BRW_LMASK 2 |
#define BRW_CMASK 3 |
#define BRW_THREAD_NORMAL 0 |
#define BRW_THREAD_ATOMIC 1 |
#define BRW_THREAD_SWITCH 2 |
#define BRW_VERTICAL_STRIDE_0 0 |
#define BRW_VERTICAL_STRIDE_1 1 |
#define BRW_VERTICAL_STRIDE_2 2 |
#define BRW_VERTICAL_STRIDE_4 3 |
#define BRW_VERTICAL_STRIDE_8 4 |
#define BRW_VERTICAL_STRIDE_16 5 |
#define BRW_VERTICAL_STRIDE_32 6 |
#define BRW_VERTICAL_STRIDE_64 7 |
#define BRW_VERTICAL_STRIDE_128 8 |
#define BRW_VERTICAL_STRIDE_256 9 |
#define BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL 0xF |
#define BRW_WIDTH_1 0 |
#define BRW_WIDTH_2 1 |
#define BRW_WIDTH_4 2 |
#define BRW_WIDTH_8 3 |
#define BRW_WIDTH_16 4 |
#define BRW_STATELESS_BUFFER_BOUNDARY_1K 0 |
#define BRW_STATELESS_BUFFER_BOUNDARY_2K 1 |
#define BRW_STATELESS_BUFFER_BOUNDARY_4K 2 |
#define BRW_STATELESS_BUFFER_BOUNDARY_8K 3 |
#define BRW_STATELESS_BUFFER_BOUNDARY_16K 4 |
#define BRW_STATELESS_BUFFER_BOUNDARY_32K 5 |
#define BRW_STATELESS_BUFFER_BOUNDARY_64K 6 |
#define BRW_STATELESS_BUFFER_BOUNDARY_128K 7 |
#define BRW_STATELESS_BUFFER_BOUNDARY_256K 8 |
#define BRW_STATELESS_BUFFER_BOUNDARY_512K 9 |
#define BRW_STATELESS_BUFFER_BOUNDARY_1M 10 |
#define BRW_STATELESS_BUFFER_BOUNDARY_2M 11 |
#define BRW_POLYGON_FACING_FRONT 0 |
#define BRW_POLYGON_FACING_BACK 1 |
#define BRW_MESSAGE_TARGET_NULL 0 |
#define BRW_MESSAGE_TARGET_MATH 1 |
#define BRW_MESSAGE_TARGET_SAMPLER 2 |
#define BRW_MESSAGE_TARGET_GATEWAY 3 |
#define BRW_MESSAGE_TARGET_DATAPORT_READ 4 |
#define BRW_MESSAGE_TARGET_DATAPORT_WRITE 5 |
#define BRW_MESSAGE_TARGET_URB 6 |
#define BRW_MESSAGE_TARGET_THREAD_SPAWNER 7 |
#define BRW_SAMPLER_RETURN_FORMAT_FLOAT32 0 |
#define BRW_SAMPLER_RETURN_FORMAT_UINT32 2 |
#define BRW_SAMPLER_RETURN_FORMAT_SINT32 3 |
#define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE 0 |
#define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE 0 |
#define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS 0 |
#define BRW_SAMPLER_MESSAGE_SIMD8_KILLPIX 1 |
#define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD 1 |
#define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD 1 |
#define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS 2 |
#define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS 2 |
#define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_COMPARE 0 |
#define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE 2 |
#define BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO 2 |
#define BRW_SAMPLER_MESSAGE_SIMD8_RESINFO 2 |
#define BRW_SAMPLER_MESSAGE_SIMD16_RESINFO 2 |
#define BRW_SAMPLER_MESSAGE_SIMD4X2_LD 3 |
#define BRW_SAMPLER_MESSAGE_SIMD8_LD 3 |
#define BRW_SAMPLER_MESSAGE_SIMD16_LD 3 |
#define BRW_DATAPORT_OWORD_BLOCK_1_OWORDLOW 0 |
#define BRW_DATAPORT_OWORD_BLOCK_1_OWORDHIGH 1 |
#define BRW_DATAPORT_OWORD_BLOCK_2_OWORDS 2 |
#define BRW_DATAPORT_OWORD_BLOCK_4_OWORDS 3 |
#define BRW_DATAPORT_OWORD_BLOCK_8_OWORDS 4 |
#define BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD 0 |
#define BRW_DATAPORT_OWORD_DUAL_BLOCK_4OWORDS 2 |
#define BRW_DATAPORT_DWORD_SCATTERED_BLOCK_8DWORDS 2 |
#define BRW_DATAPORT_DWORD_SCATTERED_BLOCK_16DWORDS 3 |
#define BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ 0 |
#define BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 1 |
#define BRW_DATAPORT_READ_MESSAGE_DWORD_BLOCK_READ 2 |
#define BRW_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 3 |
#define BRW_DATAPORT_READ_TARGET_DATA_CACHE 0 |
#define BRW_DATAPORT_READ_TARGET_RENDER_CACHE 1 |
#define BRW_DATAPORT_READ_TARGET_SAMPLER_CACHE 2 |
#define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE 0 |
#define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED 1 |
#define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01 2 |
#define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23 3 |
#define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01 4 |
#define BRW_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE 0 |
#define BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE 1 |
#define BRW_DATAPORT_WRITE_MESSAGE_DWORD_BLOCK_WRITE 2 |
#define BRW_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE 3 |
#define BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE 4 |
#define BRW_DATAPORT_WRITE_MESSAGE_STREAMED_VERTEX_BUFFER_WRITE 5 |
#define BRW_DATAPORT_WRITE_MESSAGE_FLUSH_RENDER_CACHE 7 |
#define BRW_MATH_FUNCTION_INV 1 |
#define BRW_MATH_FUNCTION_LOG 2 |
#define BRW_MATH_FUNCTION_EXP 3 |
#define BRW_MATH_FUNCTION_SQRT 4 |
#define BRW_MATH_FUNCTION_RSQ 5 |
#define BRW_MATH_FUNCTION_SIN 6 /* was 7 */ |
#define BRW_MATH_FUNCTION_COS 7 /* was 8 */ |
#define BRW_MATH_FUNCTION_SINCOS 8 /* was 6 */ |
#define BRW_MATH_FUNCTION_TAN 9 |
#define BRW_MATH_FUNCTION_POW 10 |
#define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER 11 |
#define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT 12 |
#define BRW_MATH_FUNCTION_INT_DIV_REMAINDER 13 |
#define BRW_MATH_INTEGER_UNSIGNED 0 |
#define BRW_MATH_INTEGER_SIGNED 1 |
#define BRW_MATH_PRECISION_FULL 0 |
#define BRW_MATH_PRECISION_PARTIAL 1 |
#define BRW_MATH_SATURATE_NONE 0 |
#define BRW_MATH_SATURATE_SATURATE 1 |
#define BRW_MATH_DATA_VECTOR 0 |
#define BRW_MATH_DATA_SCALAR 1 |
#define BRW_URB_OPCODE_WRITE 0 |
#define BRW_URB_SWIZZLE_NONE 0 |
#define BRW_URB_SWIZZLE_INTERLEAVE 1 |
#define BRW_URB_SWIZZLE_TRANSPOSE 2 |
#define BRW_SCRATCH_SPACE_SIZE_1K 0 |
#define BRW_SCRATCH_SPACE_SIZE_2K 1 |
#define BRW_SCRATCH_SPACE_SIZE_4K 2 |
#define BRW_SCRATCH_SPACE_SIZE_8K 3 |
#define BRW_SCRATCH_SPACE_SIZE_16K 4 |
#define BRW_SCRATCH_SPACE_SIZE_32K 5 |
#define BRW_SCRATCH_SPACE_SIZE_64K 6 |
#define BRW_SCRATCH_SPACE_SIZE_128K 7 |
#define BRW_SCRATCH_SPACE_SIZE_256K 8 |
#define BRW_SCRATCH_SPACE_SIZE_512K 9 |
#define BRW_SCRATCH_SPACE_SIZE_1M 10 |
#define BRW_SCRATCH_SPACE_SIZE_2M 11 |
#define CMD_URB_FENCE 0x6000 |
#define CMD_CONST_BUFFER_STATE 0x6001 |
#define CMD_CONST_BUFFER 0x6002 |
#define CMD_STATE_BASE_ADDRESS 0x6101 |
#define CMD_STATE_INSN_POINTER 0x6102 |
#define CMD_PIPELINE_SELECT 0x6104 |
#define CMD_PIPELINED_STATE_POINTERS 0x7800 |
#define CMD_BINDING_TABLE_PTRS 0x7801 |
#define CMD_VERTEX_BUFFER 0x7808 |
#define CMD_VERTEX_ELEMENT 0x7809 |
#define CMD_INDEX_BUFFER 0x780a |
#define CMD_VF_STATISTICS 0x780b |
#define CMD_DRAW_RECT 0x7900 |
#define CMD_BLEND_CONSTANT_COLOR 0x7901 |
#define CMD_CHROMA_KEY 0x7904 |
#define CMD_DEPTH_BUFFER 0x7905 |
#define CMD_POLY_STIPPLE_OFFSET 0x7906 |
#define CMD_POLY_STIPPLE_PATTERN 0x7907 |
#define CMD_LINE_STIPPLE_PATTERN 0x7908 |
#define CMD_GLOBAL_DEPTH_OFFSET_CLAMP 0x7908 |
#define CMD_PIPE_CONTROL 0x7a00 |
#define CMD_3D_PRIM 0x7b00 |
#define CMD_MI_FLUSH 0x0200 |
/* Various values from the R0 vertex header: |
*/ |
#define R02_PRIM_END 0x1 |
#define R02_PRIM_START 0x2 |
/* media pipeline */ |
#define BRW_VFE_MODE_GENERIC 0x0 |
#define BRW_VFE_MODE_VLD_MPEG2 0x1 |
#define BRW_VFE_MODE_IS 0x2 |
#define BRW_VFE_MODE_AVC_MC 0x4 |
#define BRW_VFE_MODE_AVC_IT 0x7 |
#define BRW_VFE_MODE_VC1_IT 0xB |
#define BRW_VFE_DEBUG_COUNTER_FREE 0 |
#define BRW_VFE_DEBUG_COUNTER_FROZEN 1 |
#define BRW_VFE_DEBUG_COUNTER_ONCE 2 |
#define BRW_VFE_DEBUG_COUNTER_ALWAYS 3 |
/* VLD_STATE */ |
#define BRW_MPEG_TOP_FIELD 1 |
#define BRW_MPEG_BOTTOM_FIELD 2 |
#define BRW_MPEG_FRAME 3 |
#define BRW_MPEG_QSCALE_LINEAR 0 |
#define BRW_MPEG_QSCALE_NONLINEAR 1 |
#define BRW_MPEG_ZIGZAG_SCAN 0 |
#define BRW_MPEG_ALTER_VERTICAL_SCAN 1 |
#define BRW_MPEG_I_PICTURE 1 |
#define BRW_MPEG_P_PICTURE 2 |
#define BRW_MPEG_B_PICTURE 3 |
#endif |
/drivers/video/Intel-2D/uxa/brw_structs.h |
---|
0,0 → 1,1723 |
/************************************************************************** |
* |
* Copyright 2005 Tungsten Graphics, Inc., Cedar Park, Texas. |
* All Rights Reserved. |
* |
* Permission is hereby granted, free of charge, to any person obtaining a |
* copy of this software and associated documentation files (the |
* "Software"), to deal in the Software without restriction, including |
* without limitation the rights to use, copy, modify, merge, publish, |
* distribute, sub license, and/or sell copies of the Software, and to |
* permit persons to whom the Software is furnished to do so, subject to |
* the following conditions: |
* |
* The above copyright notice and this permission notice (including the |
* next paragraph) shall be included in all copies or substantial portions |
* of the Software. |
* |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
* |
**************************************************************************/ |
#ifndef BRW_STRUCTS_H |
#define BRW_STRUCTS_H |
/* Command packets: |
*/ |
struct header |
{ |
unsigned int length:16; |
unsigned int opcode:16; |
}; |
union header_union |
{ |
struct header bits; |
unsigned int dword; |
}; |
struct brw_3d_control |
{ |
struct |
{ |
unsigned int length:8; |
unsigned int notify_enable:1; |
unsigned int pad:3; |
unsigned int wc_flush_enable:1; |
unsigned int depth_stall_enable:1; |
unsigned int operation:2; |
unsigned int opcode:16; |
} header; |
struct |
{ |
unsigned int pad:2; |
unsigned int dest_addr_type:1; |
unsigned int dest_addr:29; |
} dest; |
unsigned int dword2; |
unsigned int dword3; |
}; |
struct brw_3d_primitive |
{ |
struct |
{ |
unsigned int length:8; |
unsigned int pad:2; |
unsigned int topology:5; |
unsigned int indexed:1; |
unsigned int opcode:16; |
} header; |
unsigned int verts_per_instance; |
unsigned int start_vert_location; |
unsigned int instance_count; |
unsigned int start_instance_location; |
unsigned int base_vert_location; |
}; |
/* These seem to be passed around as function args, so it works out |
* better to keep them as #defines: |
*/ |
#define BRW_FLUSH_READ_CACHE 0x1 |
#define BRW_FLUSH_STATE_CACHE 0x2 |
#define BRW_INHIBIT_FLUSH_RENDER_CACHE 0x4 |
#define BRW_FLUSH_SNAPSHOT_COUNTERS 0x8 |
struct brw_mi_flush |
{ |
unsigned int flags:4; |
unsigned int pad:12; |
unsigned int opcode:16; |
}; |
struct brw_vf_statistics |
{ |
unsigned int statistics_enable:1; |
unsigned int pad:15; |
unsigned int opcode:16; |
}; |
struct brw_binding_table_pointers |
{ |
struct header header; |
unsigned int vs; |
unsigned int gs; |
unsigned int clp; |
unsigned int sf; |
unsigned int wm; |
}; |
struct brw_blend_constant_color |
{ |
struct header header; |
float blend_constant_color[4]; |
}; |
struct brw_depthbuffer |
{ |
union header_union header; |
union { |
struct { |
unsigned int pitch:18; |
unsigned int format:3; |
unsigned int pad:4; |
unsigned int depth_offset_disable:1; |
unsigned int tile_walk:1; |
unsigned int tiled_surface:1; |
unsigned int pad2:1; |
unsigned int surface_type:3; |
} bits; |
unsigned int dword; |
} dword1; |
unsigned int dword2_base_addr; |
union { |
struct { |
unsigned int pad:1; |
unsigned int mipmap_layout:1; |
unsigned int lod:4; |
unsigned int width:13; |
unsigned int height:13; |
} bits; |
unsigned int dword; |
} dword3; |
union { |
struct { |
unsigned int pad:12; |
unsigned int min_array_element:9; |
unsigned int depth:11; |
} bits; |
unsigned int dword; |
} dword4; |
}; |
struct brw_drawrect |
{ |
struct header header; |
unsigned int xmin:16; |
unsigned int ymin:16; |
unsigned int xmax:16; |
unsigned int ymax:16; |
unsigned int xorg:16; |
unsigned int yorg:16; |
}; |
struct brw_global_depth_offset_clamp |
{ |
struct header header; |
float depth_offset_clamp; |
}; |
struct brw_indexbuffer |
{ |
union { |
struct |
{ |
unsigned int length:8; |
unsigned int index_format:2; |
unsigned int cut_index_enable:1; |
unsigned int pad:5; |
unsigned int opcode:16; |
} bits; |
unsigned int dword; |
} header; |
unsigned int buffer_start; |
unsigned int buffer_end; |
}; |
struct brw_line_stipple |
{ |
struct header header; |
struct |
{ |
unsigned int pattern:16; |
unsigned int pad:16; |
} bits0; |
struct |
{ |
unsigned int repeat_count:9; |
unsigned int pad:7; |
unsigned int inverse_repeat_count:16; |
} bits1; |
}; |
struct brw_pipelined_state_pointers |
{ |
struct header header; |
struct { |
unsigned int pad:5; |
unsigned int offset:27; |
} vs; |
struct |
{ |
unsigned int enable:1; |
unsigned int pad:4; |
unsigned int offset:27; |
} gs; |
struct |
{ |
unsigned int enable:1; |
unsigned int pad:4; |
unsigned int offset:27; |
} clp; |
struct |
{ |
unsigned int pad:5; |
unsigned int offset:27; |
} sf; |
struct |
{ |
unsigned int pad:5; |
unsigned int offset:27; |
} wm; |
struct |
{ |
unsigned int pad:5; |
unsigned int offset:27; /* KW: check me! */ |
} cc; |
}; |
struct brw_polygon_stipple_offset |
{ |
struct header header; |
struct { |
unsigned int y_offset:5; |
unsigned int pad:3; |
unsigned int x_offset:5; |
unsigned int pad0:19; |
} bits0; |
}; |
struct brw_polygon_stipple |
{ |
struct header header; |
unsigned int stipple[32]; |
}; |
struct brw_pipeline_select |
{ |
struct |
{ |
unsigned int pipeline_select:1; |
unsigned int pad:15; |
unsigned int opcode:16; |
} header; |
}; |
struct brw_pipe_control |
{ |
struct |
{ |
unsigned int length:8; |
unsigned int notify_enable:1; |
unsigned int pad:2; |
unsigned int instruction_state_cache_flush_enable:1; |
unsigned int write_cache_flush_enable:1; |
unsigned int depth_stall_enable:1; |
unsigned int post_sync_operation:2; |
unsigned int opcode:16; |
} header; |
struct |
{ |
unsigned int pad:2; |
unsigned int dest_addr_type:1; |
unsigned int dest_addr:29; |
} bits1; |
unsigned int data0; |
unsigned int data1; |
}; |
struct brw_urb_fence |
{ |
struct |
{ |
unsigned int length:8; |
unsigned int vs_realloc:1; |
unsigned int gs_realloc:1; |
unsigned int clp_realloc:1; |
unsigned int sf_realloc:1; |
unsigned int vfe_realloc:1; |
unsigned int cs_realloc:1; |
unsigned int pad:2; |
unsigned int opcode:16; |
} header; |
struct |
{ |
unsigned int vs_fence:10; |
unsigned int gs_fence:10; |
unsigned int clp_fence:10; |
unsigned int pad:2; |
} bits0; |
struct |
{ |
unsigned int sf_fence:10; |
unsigned int vf_fence:10; |
unsigned int cs_fence:10; |
unsigned int pad:2; |
} bits1; |
}; |
struct brw_constant_buffer_state /* previously brw_command_streamer */ |
{ |
struct header header; |
struct |
{ |
unsigned int nr_urb_entries:3; |
unsigned int pad:1; |
unsigned int urb_entry_size:5; |
unsigned int pad0:23; |
} bits0; |
}; |
struct brw_constant_buffer |
{ |
struct |
{ |
unsigned int length:8; |
unsigned int valid:1; |
unsigned int pad:7; |
unsigned int opcode:16; |
} header; |
struct |
{ |
unsigned int buffer_length:6; |
unsigned int buffer_address:26; |
} bits0; |
}; |
struct brw_state_base_address |
{ |
struct header header; |
struct |
{ |
unsigned int modify_enable:1; |
unsigned int pad:4; |
unsigned int general_state_address:27; |
} bits0; |
struct |
{ |
unsigned int modify_enable:1; |
unsigned int pad:4; |
unsigned int surface_state_address:27; |
} bits1; |
struct |
{ |
unsigned int modify_enable:1; |
unsigned int pad:4; |
unsigned int indirect_object_state_address:27; |
} bits2; |
struct |
{ |
unsigned int modify_enable:1; |
unsigned int pad:11; |
unsigned int general_state_upper_bound:20; |
} bits3; |
struct |
{ |
unsigned int modify_enable:1; |
unsigned int pad:11; |
unsigned int indirect_object_state_upper_bound:20; |
} bits4; |
}; |
struct brw_state_prefetch |
{ |
struct header header; |
struct |
{ |
unsigned int prefetch_count:3; |
unsigned int pad:3; |
unsigned int prefetch_pointer:26; |
} bits0; |
}; |
struct brw_system_instruction_pointer |
{ |
struct header header; |
struct |
{ |
unsigned int pad:4; |
unsigned int system_instruction_pointer:28; |
} bits0; |
}; |
/* State structs for the various fixed function units: |
*/ |
struct thread0 |
{ |
unsigned int pad0:1; |
unsigned int grf_reg_count:3; |
unsigned int pad1:2; |
unsigned int kernel_start_pointer:26; |
}; |
struct thread1 |
{ |
unsigned int ext_halt_exception_enable:1; |
unsigned int sw_exception_enable:1; |
unsigned int mask_stack_exception_enable:1; |
unsigned int timeout_exception_enable:1; |
unsigned int illegal_op_exception_enable:1; |
unsigned int pad0:3; |
unsigned int depth_coef_urb_read_offset:6; /* WM only */ |
unsigned int pad1:2; |
unsigned int floating_point_mode:1; |
unsigned int thread_priority:1; |
unsigned int binding_table_entry_count:8; |
unsigned int pad3:5; |
unsigned int single_program_flow:1; |
}; |
struct thread2 |
{ |
unsigned int per_thread_scratch_space:4; |
unsigned int pad0:6; |
unsigned int scratch_space_base_pointer:22; |
}; |
struct thread3 |
{ |
unsigned int dispatch_grf_start_reg:4; |
unsigned int urb_entry_read_offset:6; |
unsigned int pad0:1; |
unsigned int urb_entry_read_length:6; |
unsigned int pad1:1; |
unsigned int const_urb_entry_read_offset:6; |
unsigned int pad2:1; |
unsigned int const_urb_entry_read_length:6; |
unsigned int pad3:1; |
}; |
struct brw_clip_unit_state |
{ |
struct thread0 thread0; |
struct thread1 thread1; |
struct thread2 thread2; |
struct thread3 thread3; |
struct |
{ |
unsigned int pad0:9; |
unsigned int gs_output_stats:1; /* not always */ |
unsigned int stats_enable:1; |
unsigned int nr_urb_entries:7; |
unsigned int pad1:1; |
unsigned int urb_entry_allocation_size:5; |
unsigned int pad2:1; |
unsigned int max_threads:6; /* may be less */ |
unsigned int pad3:1; |
} thread4; |
struct |
{ |
unsigned int pad0:13; |
unsigned int clip_mode:3; |
unsigned int userclip_enable_flags:8; |
unsigned int userclip_must_clip:1; |
unsigned int pad1:1; |
unsigned int guard_band_enable:1; |
unsigned int viewport_z_clip_enable:1; |
unsigned int viewport_xy_clip_enable:1; |
unsigned int vertex_position_space:1; |
unsigned int api_mode:1; |
unsigned int pad2:1; |
} clip5; |
struct |
{ |
unsigned int pad0:5; |
unsigned int clipper_viewport_state_ptr:27; |
} clip6; |
float viewport_xmin; |
float viewport_xmax; |
float viewport_ymin; |
float viewport_ymax; |
}; |
struct brw_cc_unit_state |
{ |
struct |
{ |
unsigned int pad0:3; |
unsigned int bf_stencil_pass_depth_pass_op:3; |
unsigned int bf_stencil_pass_depth_fail_op:3; |
unsigned int bf_stencil_fail_op:3; |
unsigned int bf_stencil_func:3; |
unsigned int bf_stencil_enable:1; |
unsigned int pad1:2; |
unsigned int stencil_write_enable:1; |
unsigned int stencil_pass_depth_pass_op:3; |
unsigned int stencil_pass_depth_fail_op:3; |
unsigned int stencil_fail_op:3; |
unsigned int stencil_func:3; |
unsigned int stencil_enable:1; |
} cc0; |
struct |
{ |
unsigned int bf_stencil_ref:8; |
unsigned int stencil_write_mask:8; |
unsigned int stencil_test_mask:8; |
unsigned int stencil_ref:8; |
} cc1; |
struct |
{ |
unsigned int logicop_enable:1; |
unsigned int pad0:10; |
unsigned int depth_write_enable:1; |
unsigned int depth_test_function:3; |
unsigned int depth_test:1; |
unsigned int bf_stencil_write_mask:8; |
unsigned int bf_stencil_test_mask:8; |
} cc2; |
struct |
{ |
unsigned int pad0:8; |
unsigned int alpha_test_func:3; |
unsigned int alpha_test:1; |
unsigned int blend_enable:1; |
unsigned int ia_blend_enable:1; |
unsigned int pad1:1; |
unsigned int alpha_test_format:1; |
unsigned int pad2:16; |
} cc3; |
struct |
{ |
unsigned int pad0:5; |
unsigned int cc_viewport_state_offset:27; |
} cc4; |
struct |
{ |
unsigned int pad0:2; |
unsigned int ia_dest_blend_factor:5; |
unsigned int ia_src_blend_factor:5; |
unsigned int ia_blend_function:3; |
unsigned int statistics_enable:1; |
unsigned int logicop_func:4; |
unsigned int pad1:11; |
unsigned int dither_enable:1; |
} cc5; |
struct |
{ |
unsigned int clamp_post_alpha_blend:1; |
unsigned int clamp_pre_alpha_blend:1; |
unsigned int clamp_range:2; |
unsigned int pad0:11; |
unsigned int y_dither_offset:2; |
unsigned int x_dither_offset:2; |
unsigned int dest_blend_factor:5; |
unsigned int src_blend_factor:5; |
unsigned int blend_function:3; |
} cc6; |
struct { |
union { |
float f; |
unsigned char ub[4]; |
} alpha_ref; |
} cc7; |
}; |
struct brw_sf_unit_state |
{ |
struct thread0 thread0; |
struct { |
unsigned int pad0:7; |
unsigned int sw_exception_enable:1; |
unsigned int pad1:3; |
unsigned int mask_stack_exception_enable:1; |
unsigned int pad2:1; |
unsigned int illegal_op_exception_enable:1; |
unsigned int pad3:2; |
unsigned int floating_point_mode:1; |
unsigned int thread_priority:1; |
unsigned int binding_table_entry_count:8; |
unsigned int pad4:5; |
unsigned int single_program_flow:1; |
} sf1; |
struct thread2 thread2; |
struct thread3 thread3; |
struct |
{ |
unsigned int pad0:10; |
unsigned int stats_enable:1; |
unsigned int nr_urb_entries:7; |
unsigned int pad1:1; |
unsigned int urb_entry_allocation_size:5; |
unsigned int pad2:1; |
unsigned int max_threads:6; |
unsigned int pad3:1; |
} thread4; |
struct |
{ |
unsigned int front_winding:1; |
unsigned int viewport_transform:1; |
unsigned int pad0:3; |
unsigned int sf_viewport_state_offset:27; |
} sf5; |
struct |
{ |
unsigned int pad0:9; |
unsigned int dest_org_vbias:4; |
unsigned int dest_org_hbias:4; |
unsigned int scissor:1; |
unsigned int disable_2x2_trifilter:1; |
unsigned int disable_zero_pix_trifilter:1; |
unsigned int point_rast_rule:2; |
unsigned int line_endcap_aa_region_width:2; |
unsigned int line_width:4; |
unsigned int fast_scissor_disable:1; |
unsigned int cull_mode:2; |
unsigned int aa_enable:1; |
} sf6; |
struct |
{ |
unsigned int point_size:11; |
unsigned int use_point_size_state:1; |
unsigned int subpixel_precision:1; |
unsigned int sprite_point:1; |
unsigned int pad0:11; |
unsigned int trifan_pv:2; |
unsigned int linestrip_pv:2; |
unsigned int tristrip_pv:2; |
unsigned int line_last_pixel_enable:1; |
} sf7; |
}; |
struct brw_gs_unit_state |
{ |
struct thread0 thread0; |
struct thread1 thread1; |
struct thread2 thread2; |
struct thread3 thread3; |
struct |
{ |
unsigned int pad0:10; |
unsigned int stats_enable:1; |
unsigned int nr_urb_entries:7; |
unsigned int pad1:1; |
unsigned int urb_entry_allocation_size:5; |
unsigned int pad2:1; |
unsigned int max_threads:1; |
unsigned int pad3:6; |
} thread4; |
struct |
{ |
unsigned int sampler_count:3; |
unsigned int pad0:2; |
unsigned int sampler_state_pointer:27; |
} gs5; |
struct |
{ |
unsigned int max_vp_index:4; |
unsigned int pad0:26; |
unsigned int reorder_enable:1; |
unsigned int pad1:1; |
} gs6; |
}; |
struct brw_vs_unit_state |
{ |
struct thread0 thread0; |
struct thread1 thread1; |
struct thread2 thread2; |
struct thread3 thread3; |
struct |
{ |
unsigned int pad0:10; |
unsigned int stats_enable:1; |
unsigned int nr_urb_entries:7; |
unsigned int pad1:1; |
unsigned int urb_entry_allocation_size:5; |
unsigned int pad2:1; |
unsigned int max_threads:4; |
unsigned int pad3:3; |
} thread4; |
struct |
{ |
unsigned int sampler_count:3; |
unsigned int pad0:2; |
unsigned int sampler_state_pointer:27; |
} vs5; |
struct |
{ |
unsigned int vs_enable:1; |
unsigned int vert_cache_disable:1; |
unsigned int pad0:30; |
} vs6; |
}; |
struct brw_wm_unit_state |
{ |
struct thread0 thread0; |
struct thread1 thread1; |
struct thread2 thread2; |
struct thread3 thread3; |
struct { |
unsigned int stats_enable:1; |
unsigned int pad0:1; |
unsigned int sampler_count:3; |
unsigned int sampler_state_pointer:27; |
} wm4; |
struct |
{ |
unsigned int enable_8_pix:1; |
unsigned int enable_16_pix:1; |
unsigned int enable_32_pix:1; |
unsigned int pad0:7; |
unsigned int legacy_global_depth_bias:1; |
unsigned int line_stipple:1; |
unsigned int depth_offset:1; |
unsigned int polygon_stipple:1; |
unsigned int line_aa_region_width:2; |
unsigned int line_endcap_aa_region_width:2; |
unsigned int early_depth_test:1; |
unsigned int thread_dispatch_enable:1; |
unsigned int program_uses_depth:1; |
unsigned int program_computes_depth:1; |
unsigned int program_uses_killpixel:1; |
unsigned int legacy_line_rast: 1; |
unsigned int transposed_urb_read:1; |
unsigned int max_threads:7; |
} wm5; |
float global_depth_offset_constant; |
float global_depth_offset_scale; |
struct { |
unsigned int pad0:1; |
unsigned int grf_reg_count_1:3; |
unsigned int pad1:2; |
unsigned int kernel_start_pointer_1:26; |
} wm8; |
struct { |
unsigned int pad0:1; |
unsigned int grf_reg_count_2:3; |
unsigned int pad1:2; |
unsigned int kernel_start_pointer_2:26; |
} wm9; |
struct { |
unsigned int pad0:1; |
unsigned int grf_reg_count_3:3; |
unsigned int pad1:2; |
unsigned int kernel_start_pointer_3:26; |
} wm10; |
}; |
struct brw_wm_unit_state_padded { |
struct brw_wm_unit_state state; |
char pad[64 - sizeof(struct brw_wm_unit_state)]; |
}; |
/* The hardware supports two different modes for border color. The |
* default (OpenGL) mode uses floating-point color channels, while the |
* legacy mode uses 4 bytes. |
* |
* More significantly, the legacy mode respects the components of the |
* border color for channels not present in the source, (whereas the |
* default mode will ignore the border color's alpha channel and use |
* alpha==1 for an RGB source, for example). |
* |
* The legacy mode matches the semantics specified by the Render |
* extension. |
*/ |
struct brw_sampler_default_border_color { |
float color[4]; |
}; |
struct brw_sampler_legacy_border_color { |
uint8_t color[4]; |
}; |
struct brw_sampler_state |
{ |
struct |
{ |
unsigned int shadow_function:3; |
unsigned int lod_bias:11; |
unsigned int min_filter:3; |
unsigned int mag_filter:3; |
unsigned int mip_filter:2; |
unsigned int base_level:5; |
unsigned int pad:1; |
unsigned int lod_preclamp:1; |
unsigned int border_color_mode:1; |
unsigned int pad0:1; |
unsigned int disable:1; |
} ss0; |
struct |
{ |
unsigned int r_wrap_mode:3; |
unsigned int t_wrap_mode:3; |
unsigned int s_wrap_mode:3; |
unsigned int pad:3; |
unsigned int max_lod:10; |
unsigned int min_lod:10; |
} ss1; |
struct |
{ |
unsigned int pad:5; |
unsigned int border_color_pointer:27; |
} ss2; |
struct |
{ |
unsigned int pad:19; |
unsigned int max_aniso:3; |
unsigned int chroma_key_mode:1; |
unsigned int chroma_key_index:2; |
unsigned int chroma_key_enable:1; |
unsigned int monochrome_filter_width:3; |
unsigned int monochrome_filter_height:3; |
} ss3; |
}; |
struct brw_clipper_viewport |
{ |
float xmin; |
float xmax; |
float ymin; |
float ymax; |
}; |
struct brw_cc_viewport |
{ |
float min_depth; |
float max_depth; |
}; |
struct brw_sf_viewport |
{ |
struct { |
float m00; |
float m11; |
float m22; |
float m30; |
float m31; |
float m32; |
} viewport; |
struct { |
short xmin; |
short ymin; |
short xmax; |
short ymax; |
} scissor; |
}; |
/* Documented in the subsystem/shared-functions/sampler chapter... |
*/ |
struct brw_surface_state |
{ |
struct { |
unsigned int cube_pos_z:1; |
unsigned int cube_neg_z:1; |
unsigned int cube_pos_y:1; |
unsigned int cube_neg_y:1; |
unsigned int cube_pos_x:1; |
unsigned int cube_neg_x:1; |
unsigned int pad:3; |
unsigned int render_cache_read_mode:1; |
unsigned int mipmap_layout_mode:1; |
unsigned int vert_line_stride_ofs:1; |
unsigned int vert_line_stride:1; |
unsigned int color_blend:1; |
unsigned int writedisable_blue:1; |
unsigned int writedisable_green:1; |
unsigned int writedisable_red:1; |
unsigned int writedisable_alpha:1; |
unsigned int surface_format:9; |
unsigned int data_return_format:1; |
unsigned int pad0:1; |
unsigned int surface_type:3; |
} ss0; |
struct { |
unsigned int base_addr; |
} ss1; |
struct { |
unsigned int render_target_rotation:2; |
unsigned int mip_count:4; |
unsigned int width:13; |
unsigned int height:13; |
} ss2; |
struct { |
unsigned int tile_walk:1; |
unsigned int tiled_surface:1; |
unsigned int pad:1; |
unsigned int pitch:18; |
unsigned int depth:11; |
} ss3; |
struct { |
unsigned int pad:19; |
unsigned int min_array_elt:9; |
unsigned int min_lod:4; |
} ss4; |
struct { |
unsigned int pad:20; |
unsigned int y_offset:4; |
unsigned int pad2:1; |
unsigned int x_offset:7; |
} ss5; |
}; |
struct brw_vertex_buffer_state |
{ |
struct { |
unsigned int pitch:11; |
unsigned int pad:15; |
unsigned int access_type:1; |
unsigned int vb_index:5; |
} vb0; |
unsigned int start_addr; |
unsigned int max_index; |
#if 1 |
unsigned int instance_data_step_rate; /* not included for sequential/random vertices? */ |
#endif |
}; |
#define BRW_VBP_MAX 17 |
struct brw_vb_array_state { |
struct header header; |
struct brw_vertex_buffer_state vb[BRW_VBP_MAX]; |
}; |
struct brw_vertex_element_state |
{ |
struct |
{ |
unsigned int src_offset:11; |
unsigned int pad:5; |
unsigned int src_format:9; |
unsigned int pad0:1; |
unsigned int valid:1; |
unsigned int vertex_buffer_index:5; |
} ve0; |
struct |
{ |
unsigned int dst_offset:8; |
unsigned int pad:8; |
unsigned int vfcomponent3:4; |
unsigned int vfcomponent2:4; |
unsigned int vfcomponent1:4; |
unsigned int vfcomponent0:4; |
} ve1; |
}; |
#define BRW_VEP_MAX 18 |
struct brw_vertex_element_packet { |
struct header header; |
struct brw_vertex_element_state ve[BRW_VEP_MAX]; /* note: less than _TNL_ATTRIB_MAX */ |
}; |
struct brw_urb_immediate { |
unsigned int opcode:4; |
unsigned int offset:6; |
unsigned int swizzle_control:2; |
unsigned int pad:1; |
unsigned int allocate:1; |
unsigned int used:1; |
unsigned int complete:1; |
unsigned int response_length:4; |
unsigned int msg_length:4; |
unsigned int msg_target:4; |
unsigned int pad1:3; |
unsigned int end_of_thread:1; |
}; |
/* Instruction format for the execution units: |
*/ |
struct brw_instruction |
{ |
struct |
{ |
unsigned int opcode:7; |
unsigned int pad:1; |
unsigned int access_mode:1; |
unsigned int mask_control:1; |
unsigned int dependency_control:2; |
unsigned int compression_control:2; |
unsigned int thread_control:2; |
unsigned int predicate_control:4; |
unsigned int predicate_inverse:1; |
unsigned int execution_size:3; |
unsigned int destreg__conditonalmod:4; /* destreg - send, conditionalmod - others */ |
unsigned int pad0:2; |
unsigned int debug_control:1; |
unsigned int saturate:1; |
} header; |
union { |
struct |
{ |
unsigned int dest_reg_file:2; |
unsigned int dest_reg_type:3; |
unsigned int src0_reg_file:2; |
unsigned int src0_reg_type:3; |
unsigned int src1_reg_file:2; |
unsigned int src1_reg_type:3; |
unsigned int pad:1; |
unsigned int dest_subreg_nr:5; |
unsigned int dest_reg_nr:8; |
unsigned int dest_horiz_stride:2; |
unsigned int dest_address_mode:1; |
} da1; |
struct |
{ |
unsigned int dest_reg_file:2; |
unsigned int dest_reg_type:3; |
unsigned int src0_reg_file:2; |
unsigned int src0_reg_type:3; |
unsigned int pad:6; |
int dest_indirect_offset:10; /* offset against the deref'd address reg */ |
unsigned int dest_subreg_nr:3; /* subnr for the address reg a0.x */ |
unsigned int dest_horiz_stride:2; |
unsigned int dest_address_mode:1; |
} ia1; |
struct |
{ |
unsigned int dest_reg_file:2; |
unsigned int dest_reg_type:3; |
unsigned int src0_reg_file:2; |
unsigned int src0_reg_type:3; |
unsigned int src1_reg_file:2; |
unsigned int src1_reg_type:3; |
unsigned int pad0:1; |
unsigned int dest_writemask:4; |
unsigned int dest_subreg_nr:1; |
unsigned int dest_reg_nr:8; |
unsigned int pad1:2; |
unsigned int dest_address_mode:1; |
} da16; |
struct |
{ |
unsigned int dest_reg_file:2; |
unsigned int dest_reg_type:3; |
unsigned int src0_reg_file:2; |
unsigned int src0_reg_type:3; |
unsigned int pad0:6; |
unsigned int dest_writemask:4; |
int dest_indirect_offset:6; |
unsigned int dest_subreg_nr:3; |
unsigned int pad1:2; |
unsigned int dest_address_mode:1; |
} ia16; |
} bits1; |
union { |
struct |
{ |
unsigned int src0_subreg_nr:5; |
unsigned int src0_reg_nr:8; |
unsigned int src0_abs:1; |
unsigned int src0_negate:1; |
unsigned int src0_address_mode:1; |
unsigned int src0_horiz_stride:2; |
unsigned int src0_width:3; |
unsigned int src0_vert_stride:4; |
unsigned int flag_reg_nr:1; |
unsigned int pad:6; |
} da1; |
struct |
{ |
int src0_indirect_offset:10; |
unsigned int src0_subreg_nr:3; |
unsigned int src0_abs:1; |
unsigned int src0_negate:1; |
unsigned int src0_address_mode:1; |
unsigned int src0_horiz_stride:2; |
unsigned int src0_width:3; |
unsigned int src0_vert_stride:4; |
unsigned int flag_reg_nr:1; |
unsigned int pad:6; |
} ia1; |
struct |
{ |
unsigned int src0_swz_x:2; |
unsigned int src0_swz_y:2; |
unsigned int src0_subreg_nr:1; |
unsigned int src0_reg_nr:8; |
unsigned int src0_abs:1; |
unsigned int src0_negate:1; |
unsigned int src0_address_mode:1; |
unsigned int src0_swz_z:2; |
unsigned int src0_swz_w:2; |
unsigned int pad0:1; |
unsigned int src0_vert_stride:4; |
unsigned int flag_reg_nr:1; |
unsigned int pad1:6; |
} da16; |
struct |
{ |
unsigned int src0_swz_x:2; |
unsigned int src0_swz_y:2; |
int src0_indirect_offset:6; |
unsigned int src0_subreg_nr:3; |
unsigned int src0_abs:1; |
unsigned int src0_negate:1; |
unsigned int src0_address_mode:1; |
unsigned int src0_swz_z:2; |
unsigned int src0_swz_w:2; |
unsigned int pad0:1; |
unsigned int src0_vert_stride:4; |
unsigned int flag_reg_nr:1; |
unsigned int pad1:6; |
} ia16; |
} bits2; |
union |
{ |
struct |
{ |
unsigned int src1_subreg_nr:5; |
unsigned int src1_reg_nr:8; |
unsigned int src1_abs:1; |
unsigned int src1_negate:1; |
unsigned int pad:1; |
unsigned int src1_horiz_stride:2; |
unsigned int src1_width:3; |
unsigned int src1_vert_stride:4; |
unsigned int pad0:7; |
} da1; |
struct |
{ |
unsigned int src1_swz_x:2; |
unsigned int src1_swz_y:2; |
unsigned int src1_subreg_nr:1; |
unsigned int src1_reg_nr:8; |
unsigned int src1_abs:1; |
unsigned int src1_negate:1; |
unsigned int pad0:1; |
unsigned int src1_swz_z:2; |
unsigned int src1_swz_w:2; |
unsigned int pad1:1; |
unsigned int src1_vert_stride:4; |
unsigned int pad2:7; |
} da16; |
struct |
{ |
int src1_indirect_offset:10; |
unsigned int src1_subreg_nr:3; |
unsigned int src1_abs:1; |
unsigned int src1_negate:1; |
unsigned int pad0:1; |
unsigned int src1_horiz_stride:2; |
unsigned int src1_width:3; |
unsigned int src1_vert_stride:4; |
unsigned int flag_reg_nr:1; |
unsigned int pad1:6; |
} ia1; |
struct |
{ |
unsigned int src1_swz_x:2; |
unsigned int src1_swz_y:2; |
int src1_indirect_offset:6; |
unsigned int src1_subreg_nr:3; |
unsigned int src1_abs:1; |
unsigned int src1_negate:1; |
unsigned int pad0:1; |
unsigned int src1_swz_z:2; |
unsigned int src1_swz_w:2; |
unsigned int pad1:1; |
unsigned int src1_vert_stride:4; |
unsigned int flag_reg_nr:1; |
unsigned int pad2:6; |
} ia16; |
struct |
{ |
int jump_count:16; /* note: signed */ |
unsigned int pop_count:4; |
unsigned int pad0:12; |
} if_else; |
struct { |
unsigned int function:4; |
unsigned int int_type:1; |
unsigned int precision:1; |
unsigned int saturate:1; |
unsigned int data_type:1; |
unsigned int pad0:8; |
unsigned int response_length:4; |
unsigned int msg_length:4; |
unsigned int msg_target:4; |
unsigned int pad1:3; |
unsigned int end_of_thread:1; |
} math; |
struct { |
unsigned int binding_table_index:8; |
unsigned int sampler:4; |
unsigned int return_format:2; |
unsigned int msg_type:2; |
unsigned int response_length:4; |
unsigned int msg_length:4; |
unsigned int msg_target:4; |
unsigned int pad1:3; |
unsigned int end_of_thread:1; |
} sampler; |
struct brw_urb_immediate urb; |
struct { |
unsigned int binding_table_index:8; |
unsigned int msg_control:4; |
unsigned int msg_type:2; |
unsigned int target_cache:2; |
unsigned int response_length:4; |
unsigned int msg_length:4; |
unsigned int msg_target:4; |
unsigned int pad1:3; |
unsigned int end_of_thread:1; |
} dp_read; |
struct { |
unsigned int binding_table_index:8; |
unsigned int msg_control:3; |
unsigned int pixel_scoreboard_clear:1; |
unsigned int msg_type:3; |
unsigned int send_commit_msg:1; |
unsigned int response_length:4; |
unsigned int msg_length:4; |
unsigned int msg_target:4; |
unsigned int pad1:3; |
unsigned int end_of_thread:1; |
} dp_write; |
struct { |
unsigned int pad:16; |
unsigned int response_length:4; |
unsigned int msg_length:4; |
unsigned int msg_target:4; |
unsigned int pad1:3; |
unsigned int end_of_thread:1; |
} generic; |
unsigned int ud; |
} bits3; |
}; |
/* media pipeline */ |
struct brw_vfe_state { |
struct { |
unsigned int per_thread_scratch_space:4; |
unsigned int pad3:3; |
unsigned int extend_vfe_state_present:1; |
unsigned int pad2:2; |
unsigned int scratch_base:22; |
} vfe0; |
struct { |
unsigned int debug_counter_control:2; |
unsigned int children_present:1; |
unsigned int vfe_mode:4; |
unsigned int pad2:2; |
unsigned int num_urb_entries:7; |
unsigned int urb_entry_alloc_size:9; |
unsigned int max_threads:7; |
} vfe1; |
struct { |
unsigned int pad4:4; |
unsigned int interface_descriptor_base:28; |
} vfe2; |
}; |
struct brw_vld_state { |
struct { |
unsigned int pad6:6; |
unsigned int scan_order:1; |
unsigned int intra_vlc_format:1; |
unsigned int quantizer_scale_type:1; |
unsigned int concealment_motion_vector:1; |
unsigned int frame_predict_frame_dct:1; |
unsigned int top_field_first:1; |
unsigned int picture_structure:2; |
unsigned int intra_dc_precision:2; |
unsigned int f_code_0_0:4; |
unsigned int f_code_0_1:4; |
unsigned int f_code_1_0:4; |
unsigned int f_code_1_1:4; |
} vld0; |
struct { |
unsigned int pad2:9; |
unsigned int picture_coding_type:2; |
unsigned int pad:21; |
} vld1; |
struct { |
unsigned int index_0:4; |
unsigned int index_1:4; |
unsigned int index_2:4; |
unsigned int index_3:4; |
unsigned int index_4:4; |
unsigned int index_5:4; |
unsigned int index_6:4; |
unsigned int index_7:4; |
} desc_remap_table0; |
struct { |
unsigned int index_8:4; |
unsigned int index_9:4; |
unsigned int index_10:4; |
unsigned int index_11:4; |
unsigned int index_12:4; |
unsigned int index_13:4; |
unsigned int index_14:4; |
unsigned int index_15:4; |
} desc_remap_table1; |
}; |
struct brw_interface_descriptor { |
struct { |
unsigned int grf_reg_blocks:4; |
unsigned int pad:2; |
unsigned int kernel_start_pointer:26; |
} desc0; |
struct { |
unsigned int pad:7; |
unsigned int software_exception:1; |
unsigned int pad2:3; |
unsigned int maskstack_exception:1; |
unsigned int pad3:1; |
unsigned int illegal_opcode_exception:1; |
unsigned int pad4:2; |
unsigned int floating_point_mode:1; |
unsigned int thread_priority:1; |
unsigned int single_program_flow:1; |
unsigned int pad5:1; |
unsigned int const_urb_entry_read_offset:6; |
unsigned int const_urb_entry_read_len:6; |
} desc1; |
struct { |
unsigned int pad:2; |
unsigned int sampler_count:3; |
unsigned int sampler_state_pointer:27; |
} desc2; |
struct { |
unsigned int binding_table_entry_count:5; |
unsigned int binding_table_pointer:27; |
} desc3; |
}; |
struct gen6_blend_state |
{ |
struct { |
unsigned int dest_blend_factor:5; |
unsigned int source_blend_factor:5; |
unsigned int pad3:1; |
unsigned int blend_func:3; |
unsigned int pad2:1; |
unsigned int ia_dest_blend_factor:5; |
unsigned int ia_source_blend_factor:5; |
unsigned int pad1:1; |
unsigned int ia_blend_func:3; |
unsigned int pad0:1; |
unsigned int ia_blend_enable:1; |
unsigned int blend_enable:1; |
} blend0; |
struct { |
unsigned int post_blend_clamp_enable:1; |
unsigned int pre_blend_clamp_enable:1; |
unsigned int clamp_range:2; |
unsigned int pad0:4; |
unsigned int x_dither_offset:2; |
unsigned int y_dither_offset:2; |
unsigned int dither_enable:1; |
unsigned int alpha_test_func:3; |
unsigned int alpha_test_enable:1; |
unsigned int pad1:1; |
unsigned int logic_op_func:4; |
unsigned int logic_op_enable:1; |
unsigned int pad2:1; |
unsigned int write_disable_b:1; |
unsigned int write_disable_g:1; |
unsigned int write_disable_r:1; |
unsigned int write_disable_a:1; |
unsigned int pad3:1; |
unsigned int alpha_to_coverage_dither:1; |
unsigned int alpha_to_one:1; |
unsigned int alpha_to_coverage:1; |
} blend1; |
}; |
struct gen6_color_calc_state |
{ |
struct { |
unsigned int alpha_test_format:1; |
unsigned int pad0:14; |
unsigned int round_disable:1; |
unsigned int bf_stencil_ref:8; |
unsigned int stencil_ref:8; |
} cc0; |
union { |
float alpha_ref_f; |
struct { |
unsigned int ui:8; |
unsigned int pad0:24; |
} alpha_ref_fi; |
} cc1; |
float constant_r; |
float constant_g; |
float constant_b; |
float constant_a; |
}; |
struct gen6_depth_stencil_state |
{ |
struct { |
unsigned int pad0:3; |
unsigned int bf_stencil_pass_depth_pass_op:3; |
unsigned int bf_stencil_pass_depth_fail_op:3; |
unsigned int bf_stencil_fail_op:3; |
unsigned int bf_stencil_func:3; |
unsigned int bf_stencil_enable:1; |
unsigned int pad1:2; |
unsigned int stencil_write_enable:1; |
unsigned int stencil_pass_depth_pass_op:3; |
unsigned int stencil_pass_depth_fail_op:3; |
unsigned int stencil_fail_op:3; |
unsigned int stencil_func:3; |
unsigned int stencil_enable:1; |
} ds0; |
struct { |
unsigned int bf_stencil_write_mask:8; |
unsigned int bf_stencil_test_mask:8; |
unsigned int stencil_write_mask:8; |
unsigned int stencil_test_mask:8; |
} ds1; |
struct { |
unsigned int pad0:26; |
unsigned int depth_write_enable:1; |
unsigned int depth_test_func:3; |
unsigned int pad1:1; |
unsigned int depth_test_enable:1; |
} ds2; |
}; |
struct gen7_surface_state |
{ |
struct { |
unsigned int cube_pos_z:1; |
unsigned int cube_neg_z:1; |
unsigned int cube_pos_y:1; |
unsigned int cube_neg_y:1; |
unsigned int cube_pos_x:1; |
unsigned int cube_neg_x:1; |
unsigned int pad2:2; |
unsigned int render_cache_read_write:1; |
unsigned int pad1:1; |
unsigned int surface_array_spacing:1; |
unsigned int vert_line_stride_ofs:1; |
unsigned int vert_line_stride:1; |
unsigned int tile_walk:1; |
unsigned int tiled_surface:1; |
unsigned int horizontal_alignment:1; |
unsigned int vertical_alignment:2; |
unsigned int surface_format:9; /**< BRW_SURFACEFORMAT_x */ |
unsigned int pad0:1; |
unsigned int is_array:1; |
unsigned int surface_type:3; /**< BRW_SURFACE_1D/2D/3D/CUBE */ |
} ss0; |
struct { |
unsigned int base_addr; |
} ss1; |
struct { |
unsigned int width:14; |
unsigned int pad1:2; |
unsigned int height:14; |
unsigned int pad0:2; |
} ss2; |
struct { |
unsigned int pitch:18; |
unsigned int pad:3; |
unsigned int depth:11; |
} ss3; |
struct { |
unsigned int multisample_position_palette_index:3; |
unsigned int num_multisamples:3; |
unsigned int multisampled_surface_storage_format:1; |
unsigned int render_target_view_extent:11; |
unsigned int min_array_elt:11; |
unsigned int rotation:2; |
unsigned int pad0:1; |
} ss4; |
struct { |
unsigned int mip_count:4; |
unsigned int min_lod:4; |
unsigned int pad1:12; |
unsigned int y_offset:4; |
unsigned int pad0:1; |
unsigned int x_offset:7; |
} ss5; |
struct { |
unsigned int pad; /* Multisample Control Surface stuff */ |
} ss6; |
struct { |
unsigned int resource_min_lod:12; |
unsigned int pad0:4; |
unsigned int shader_chanel_select_a:3; |
unsigned int shader_chanel_select_b:3; |
unsigned int shader_chanel_select_g:3; |
unsigned int shader_chanel_select_r:3; |
unsigned int alpha_clear_color:1; |
unsigned int blue_clear_color:1; |
unsigned int green_clear_color:1; |
unsigned int red_clear_color:1; |
} ss7; |
}; |
struct gen7_sampler_state |
{ |
struct |
{ |
unsigned int aniso_algorithm:1; |
unsigned int lod_bias:13; |
unsigned int min_filter:3; |
unsigned int mag_filter:3; |
unsigned int mip_filter:2; |
unsigned int base_level:5; |
unsigned int pad1:1; |
unsigned int lod_preclamp:1; |
unsigned int default_color_mode:1; |
unsigned int pad0:1; |
unsigned int disable:1; |
} ss0; |
struct |
{ |
unsigned int cube_control_mode:1; |
unsigned int shadow_function:3; |
unsigned int pad:4; |
unsigned int max_lod:12; |
unsigned int min_lod:12; |
} ss1; |
struct |
{ |
unsigned int pad:5; |
unsigned int default_color_pointer:27; |
} ss2; |
struct |
{ |
unsigned int r_wrap_mode:3; |
unsigned int t_wrap_mode:3; |
unsigned int s_wrap_mode:3; |
unsigned int pad:1; |
unsigned int non_normalized_coord:1; |
unsigned int trilinear_quality:2; |
unsigned int address_round:6; |
unsigned int max_aniso:3; |
unsigned int chroma_key_mode:1; |
unsigned int chroma_key_index:2; |
unsigned int chroma_key_enable:1; |
unsigned int pad0:6; |
} ss3; |
}; |
#endif |
/drivers/video/Intel-2D/uxa/common.h |
---|
0,0 → 1,71 |
/************************************************************************** |
Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas. |
Copyright © 2002 David Dawes |
All Rights Reserved. |
Permission is hereby granted, free of charge, to any person obtaining a |
copy of this software and associated documentation files (the |
"Software"), to deal in the Software without restriction, including |
without limitation the rights to use, copy, modify, merge, publish, |
distribute, sub license, and/or sell copies of the Software, and to |
permit persons to whom the Software is furnished to do so, subject to |
the following conditions: |
The above copyright notice and this permission notice (including the |
next paragraph) shall be included in all copies or substantial portions |
of the Software. |
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR |
ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
**************************************************************************/ |
/* |
* Authors: |
* Keith Whitwell <keith@tungstengraphics.com> |
* David Dawes <dawes@xfree86.org> |
* |
*/ |
#ifndef _INTEL_COMMON_H_ |
#define _INTEL_COMMON_H_ |
//#include <xf86.h> |
/* Provide substitutes for gcc's __FUNCTION__ on other compilers */ |
#if !defined(__GNUC__) && !defined(__FUNCTION__) |
# if defined(__STDC__) && (__STDC_VERSION__>=199901L) /* C99 */ |
# define __FUNCTION__ __func__ |
# else |
# define __FUNCTION__ "" |
# endif |
#endif |
#define PFX __FILE__,__LINE__,__FUNCTION__ |
#define FUNCTION_NAME __FUNCTION__ |
#define KB(x) ((x) * 1024) |
#define MB(x) ((x) * KB(1024)) |
/** |
* Hints to CreatePixmap to tell the driver how the pixmap is going to be |
* used. |
* |
* Compare to CREATE_PIXMAP_USAGE_* in the server. |
*/ |
enum { |
INTEL_CREATE_PIXMAP_TILING_X = 0x10000000, |
INTEL_CREATE_PIXMAP_TILING_Y = 0x20000000, |
INTEL_CREATE_PIXMAP_TILING_NONE = 0x40000000, |
INTEL_CREATE_PIXMAP_DRI2 = 0x80000000, |
}; |
#endif /* _INTEL_COMMON_H_ */ |
/drivers/video/Intel-2D/uxa/i830_reg.h |
---|
0,0 → 1,805 |
/************************************************************************** |
* |
* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
* All Rights Reserved. |
* |
* Permission is hereby granted, free of charge, to any person obtaining a |
* copy of this software and associated documentation files (the |
* "Software"), to deal in the Software without restriction, including |
* without limitation the rights to use, copy, modify, merge, publish, |
* distribute, sub license, and/or sell copies of the Software, and to |
* permit persons to whom the Software is furnished to do so, subject to |
* the following conditions: |
* |
* The above copyright notice and this permission notice (including the |
* next paragraph) shall be included in all copies or substantial portions |
* of the Software. |
* |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
* |
**************************************************************************/ |
#ifndef _I830_REG_H_ |
#define _I830_REG_H_ |
#define I830_SET_FIELD( var, mask, value ) (var &= ~(mask), var |= value) |
/* Flush */ |
#define MI_FLUSH (0x04<<23) |
#define MI_FLUSH_DW (0x26<<23) |
#define MI_WRITE_DIRTY_STATE (1<<4) |
#define MI_END_SCENE (1<<3) |
#define MI_GLOBAL_SNAPSHOT_COUNT_RESET (1<<3) |
#define MI_INHIBIT_RENDER_CACHE_FLUSH (1<<2) |
#define MI_STATE_INSTRUCTION_CACHE_FLUSH (1<<1) |
#define MI_INVALIDATE_MAP_CACHE (1<<0) |
/* broadwater flush bits */ |
#define BRW_MI_GLOBAL_SNAPSHOT_RESET (1 << 3) |
#define MI_BATCH_BUFFER_END (0xA << 23) |
/* Noop */ |
#define MI_NOOP 0x00 |
#define MI_NOOP_WRITE_ID (1<<22) |
#define MI_NOOP_ID_MASK (1<<22 - 1) |
/* Wait for Events */ |
#define MI_WAIT_FOR_EVENT (0x03<<23) |
#define MI_WAIT_FOR_PIPEB_SVBLANK (1<<18) |
#define MI_WAIT_FOR_PIPEA_SVBLANK (1<<17) |
#define MI_WAIT_FOR_OVERLAY_FLIP (1<<16) |
#define MI_WAIT_FOR_PIPEB_VBLANK (1<<7) |
#define MI_WAIT_FOR_PIPEB_SCAN_LINE_WINDOW (1<<5) |
#define MI_WAIT_FOR_PIPEA_VBLANK (1<<3) |
#define MI_WAIT_FOR_PIPEA_SCAN_LINE_WINDOW (1<<1) |
/* Set the scan line for MI_WAIT_FOR_PIPE?_SCAN_LINE_WINDOW */ |
#define MI_LOAD_SCAN_LINES_INCL (0x12<<23) |
#define MI_LOAD_SCAN_LINES_DISPLAY_PIPEA (0) |
#define MI_LOAD_SCAN_LINES_DISPLAY_PIPEB (0x1<<20) |
/* BLT commands */ |
#define COLOR_BLT_CMD ((2<<29)|(0x40<<22)|(0x3)) |
#define COLOR_BLT_WRITE_ALPHA (1<<21) |
#define COLOR_BLT_WRITE_RGB (1<<20) |
#define XY_COLOR_BLT_CMD ((2<<29)|(0x50<<22)|(0x4)) |
#define XY_COLOR_BLT_WRITE_ALPHA (1<<21) |
#define XY_COLOR_BLT_WRITE_RGB (1<<20) |
#define XY_COLOR_BLT_TILED (1<<11) |
#define XY_SETUP_CLIP_BLT_CMD ((2<<29)|(3<<22)|1) |
#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) |
#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21) |
#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20) |
#define XY_SRC_COPY_BLT_SRC_TILED (1<<15) |
#define XY_SRC_COPY_BLT_DST_TILED (1<<11) |
#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|0x4) |
#define SRC_COPY_BLT_WRITE_ALPHA (1<<21) |
#define SRC_COPY_BLT_WRITE_RGB (1<<20) |
#define XY_PAT_BLT_IMMEDIATE ((2<<29)|(0x72<<22)) |
#define XY_MONO_PAT_BLT_CMD ((0x2<<29)|(0x52<<22)|0x7) |
#define XY_MONO_PAT_VERT_SEED ((1<<10)|(1<<9)|(1<<8)) |
#define XY_MONO_PAT_HORT_SEED ((1<<14)|(1<<13)|(1<<12)) |
#define XY_MONO_PAT_BLT_WRITE_ALPHA (1<<21) |
#define XY_MONO_PAT_BLT_WRITE_RGB (1<<20) |
#define XY_MONO_SRC_BLT_CMD ((0x2<<29)|(0x54<<22)|(0x6)) |
#define XY_MONO_SRC_BLT_WRITE_ALPHA (1<<21) |
#define XY_MONO_SRC_BLT_WRITE_RGB (1<<20) |
#define CMD_3D (0x3<<29) |
#define PRIM3D_INLINE (CMD_3D | (0x1f<<24)) |
#define PRIM3D_TRILIST (0x0<<18) |
#define PRIM3D_TRISTRIP (0x1<<18) |
#define PRIM3D_TRISTRIP_RVRSE (0x2<<18) |
#define PRIM3D_TRIFAN (0x3<<18) |
#define PRIM3D_POLY (0x4<<18) |
#define PRIM3D_LINELIST (0x5<<18) |
#define PRIM3D_LINESTRIP (0x6<<18) |
#define PRIM3D_RECTLIST (0x7<<18) |
#define PRIM3D_POINTLIST (0x8<<18) |
#define PRIM3D_DIB (0x9<<18) |
#define PRIM3D_CLEAR_RECT (0xa<<18) |
#define PRIM3D_ZONE_INIT (0xd<<18) |
#define PRIM3D_MASK (0x1f<<18) |
#define _3DSTATE_AA_CMD (CMD_3D | (0x06<<24)) |
#define AA_LINE_ECAAR_WIDTH_ENABLE (1<<16) |
#define AA_LINE_ECAAR_WIDTH_0_5 0 |
#define AA_LINE_ECAAR_WIDTH_1_0 (1<<14) |
#define AA_LINE_ECAAR_WIDTH_2_0 (2<<14) |
#define AA_LINE_ECAAR_WIDTH_4_0 (3<<14) |
#define AA_LINE_REGION_WIDTH_ENABLE (1<<8) |
#define AA_LINE_REGION_WIDTH_0_5 0 |
#define AA_LINE_REGION_WIDTH_1_0 (1<<6) |
#define AA_LINE_REGION_WIDTH_2_0 (2<<6) |
#define AA_LINE_REGION_WIDTH_4_0 (3<<6) |
#define AA_LINE_ENABLE ((1<<1) | 1) |
#define AA_LINE_DISABLE (1<<1) |
#define _3DSTATE_BUF_INFO_CMD (CMD_3D | (0x1d<<24) | (0x8e<<16) | 1) |
/* Dword 1 */ |
#define BUF_3D_ID_COLOR_BACK (0x3<<24) |
#define BUF_3D_ID_DEPTH (0x7<<24) |
#define BUF_3D_USE_FENCE (1<<23) |
#define BUF_3D_TILED_SURFACE (1<<22) |
#define BUF_3D_TILE_WALK_X 0 |
#define BUF_3D_TILE_WALK_Y (1<<21) |
#define BUF_3D_PITCH(x) (((x)/4)<<2) |
/* Dword 2 */ |
#define BUF_3D_ADDR(x) ((x) & ~0x3) |
#define _3DSTATE_COLOR_FACTOR_CMD (CMD_3D | (0x1d<<24) | (0x1<<16)) |
#define _3DSTATE_COLOR_FACTOR_N_CMD(stage) (CMD_3D | (0x1d<<24) | \ |
((0x90+(stage))<<16)) |
#define _3DSTATE_CONST_BLEND_COLOR_CMD (CMD_3D | (0x1d<<24) | (0x88<<16)) |
#define _3DSTATE_DFLT_DIFFUSE_CMD (CMD_3D | (0x1d<<24) | (0x99<<16)) |
#define _3DSTATE_DFLT_SPEC_CMD (CMD_3D | (0x1d<<24) | (0x9a<<16)) |
#define _3DSTATE_DFLT_Z_CMD (CMD_3D | (0x1d<<24) | (0x98<<16)) |
#define _3DSTATE_DST_BUF_VARS_CMD (CMD_3D | (0x1d<<24) | (0x85<<16)) |
/* Dword 1 */ |
#define DSTORG_HORT_BIAS(x) ((x)<<20) |
#define DSTORG_VERT_BIAS(x) ((x)<<16) |
#define COLOR_4_2_2_CHNL_WRT_ALL 0 |
#define COLOR_4_2_2_CHNL_WRT_Y (1<<12) |
#define COLOR_4_2_2_CHNL_WRT_CR (2<<12) |
#define COLOR_4_2_2_CHNL_WRT_CB (3<<12) |
#define COLOR_4_2_2_CHNL_WRT_CRCB (4<<12) |
#define COLR_BUF_8BIT 0 |
#define COLR_BUF_RGB555 (1<<8) |
#define COLR_BUF_RGB565 (2<<8) |
#define COLR_BUF_ARGB8888 (3<<8) |
#define COLR_BUF_ARGB4444 (8<<8) |
#define COLR_BUF_ARGB1555 (9<<8) |
#define DEPTH_IS_Z 0 |
#define DEPTH_IS_W (1<<6) |
#define DEPTH_FRMT_16_FIXED 0 |
#define DEPTH_FRMT_16_FLOAT (1<<2) |
#define DEPTH_FRMT_24_FIXED_8_OTHER (2<<2) |
#define DEPTH_FRMT_24_FLOAT_8_OTHER (3<<2) |
#define VERT_LINE_STRIDE_1 (1<<1) |
#define VERT_LINE_STRIDE_0 0 |
#define VERT_LINE_STRIDE_OFS_1 1 |
#define VERT_LINE_STRIDE_OFS_0 0 |
#define _3DSTATE_DRAW_RECT_CMD (CMD_3D|(0x1d<<24)|(0x80<<16)|3) |
/* Dword 1 */ |
#define DRAW_RECT_DIS_DEPTH_OFS (1<<30) |
#define DRAW_DITHER_OFS_X(x) ((x)<<26) |
#define DRAW_DITHER_OFS_Y(x) ((x)<<24) |
/* Dword 2 */ |
#define DRAW_YMIN(x) ((x)<<16) |
#define DRAW_XMIN(x) (x) |
/* Dword 3 */ |
#define DRAW_YMAX(x) ((x)<<16) |
#define DRAW_XMAX(x) (x) |
/* Dword 4 */ |
#define DRAW_YORG(x) ((x)<<16) |
#define DRAW_XORG(x) (x) |
#define _3DSTATE_ENABLES_1_CMD (CMD_3D|(0x3<<24)) |
#define ENABLE_LOGIC_OP_MASK ((1<<23)|(1<<22)) |
#define ENABLE_LOGIC_OP ((1<<23)|(1<<22)) |
#define DISABLE_LOGIC_OP (1<<23) |
#define ENABLE_STENCIL_TEST ((1<<21)|(1<<20)) |
#define DISABLE_STENCIL_TEST (1<<21) |
#define ENABLE_DEPTH_BIAS ((1<<11)|(1<<10)) |
#define DISABLE_DEPTH_BIAS (1<<11) |
#define ENABLE_SPEC_ADD_MASK ((1<<9)|(1<<8)) |
#define ENABLE_SPEC_ADD ((1<<9)|(1<<8)) |
#define DISABLE_SPEC_ADD (1<<9) |
#define ENABLE_DIS_FOG_MASK ((1<<7)|(1<<6)) |
#define ENABLE_FOG ((1<<7)|(1<<6)) |
#define DISABLE_FOG (1<<7) |
#define ENABLE_DIS_ALPHA_TEST_MASK ((1<<5)|(1<<4)) |
#define ENABLE_ALPHA_TEST ((1<<5)|(1<<4)) |
#define DISABLE_ALPHA_TEST (1<<5) |
#define ENABLE_DIS_CBLEND_MASK ((1<<3)|(1<<2)) |
#define ENABLE_COLOR_BLEND ((1<<3)|(1<<2)) |
#define DISABLE_COLOR_BLEND (1<<3) |
#define ENABLE_DIS_DEPTH_TEST_MASK ((1<<1)|1) |
#define ENABLE_DEPTH_TEST ((1<<1)|1) |
#define DISABLE_DEPTH_TEST (1<<1) |
/* _3DSTATE_ENABLES_2, p138 */ |
#define _3DSTATE_ENABLES_2_CMD (CMD_3D|(0x4<<24)) |
#define ENABLE_STENCIL_WRITE ((1<<21)|(1<<20)) |
#define DISABLE_STENCIL_WRITE (1<<21) |
#define ENABLE_TEX_CACHE ((1<<17)|(1<<16)) |
#define DISABLE_TEX_CACHE (1<<17) |
#define ENABLE_DITHER ((1<<9)|(1<<8)) |
#define DISABLE_DITHER (1<<9) |
#define ENABLE_COLOR_MASK (1<<10) |
#define WRITEMASK_ALPHA (1<<7) |
#define WRITEMASK_ALPHA_SHIFT 7 |
#define WRITEMASK_RED (1<<6) |
#define WRITEMASK_RED_SHIFT 6 |
#define WRITEMASK_GREEN (1<<5) |
#define WRITEMASK_GREEN_SHIFT 5 |
#define WRITEMASK_BLUE (1<<4) |
#define WRITEMASK_BLUE_SHIFT 4 |
#define WRITEMASK_MASK ((1<<4)|(1<<5)|(1<<6)|(1<<7)) |
#define ENABLE_COLOR_WRITE ((1<<3)|(1<<2)) |
#define DISABLE_COLOR_WRITE (1<<3) |
#define ENABLE_DIS_DEPTH_WRITE_MASK 0x3 |
#define ENABLE_DEPTH_WRITE ((1<<1)|1) |
#define DISABLE_DEPTH_WRITE (1<<1) |
/* _3DSTATE_FOG_COLOR, p139 */ |
#define _3DSTATE_FOG_COLOR_CMD (CMD_3D|(0x15<<24)) |
#define FOG_COLOR_RED(x) ((x)<<16) |
#define FOG_COLOR_GREEN(x) ((x)<<8) |
#define FOG_COLOR_BLUE(x) (x) |
/* _3DSTATE_FOG_MODE, p140 */ |
#define _3DSTATE_FOG_MODE_CMD (CMD_3D|(0x1d<<24)|(0x89<<16)|2) |
/* Dword 1 */ |
#define FOGFUNC_ENABLE (1<<31) |
#define FOGFUNC_VERTEX 0 |
#define FOGFUNC_PIXEL_EXP (1<<28) |
#define FOGFUNC_PIXEL_EXP2 (2<<28) |
#define FOGFUNC_PIXEL_LINEAR (3<<28) |
#define FOGSRC_INDEX_Z (1<<27) |
#define FOGSRC_INDEX_W ((1<<27)|(1<<25)) |
#define FOG_LINEAR_CONST (1<<24) |
#define FOG_CONST_1(x) ((x)<<4) |
#define ENABLE_FOG_DENSITY (1<<23) |
/* Dword 2 */ |
#define FOG_CONST_2(x) (x) |
/* Dword 3 */ |
#define FOG_DENSITY(x) (x) |
/* _3DSTATE_INDEPENDENT_ALPHA_BLEND, p142 */ |
#define _3DSTATE_INDPT_ALPHA_BLEND_CMD (CMD_3D|(0x0b<<24)) |
#define ENABLE_INDPT_ALPHA_BLEND ((1<<23)|(1<<22)) |
#define DISABLE_INDPT_ALPHA_BLEND (1<<23) |
#define ALPHA_BLENDFUNC_MASK 0x3f0000 |
#define ENABLE_ALPHA_BLENDFUNC (1<<21) |
#define ABLENDFUNC_ADD 0 |
#define ABLENDFUNC_SUB (1<<16) |
#define ABLENDFUNC_RVSE_SUB (2<<16) |
#define ABLENDFUNC_MIN (3<<16) |
#define ABLENDFUNC_MAX (4<<16) |
#define SRC_DST_ABLEND_MASK 0xfff |
#define ENABLE_SRC_ABLEND_FACTOR (1<<11) |
#define SRC_ABLEND_FACT(x) ((x)<<6) |
#define ENABLE_DST_ABLEND_FACTOR (1<<5) |
#define DST_ABLEND_FACT(x) (x) |
#define BLENDFACTOR_ZERO 0x01 |
#define BLENDFACTOR_ONE 0x02 |
#define BLENDFACTOR_SRC_COLR 0x03 |
#define BLENDFACTOR_INV_SRC_COLR 0x04 |
#define BLENDFACTOR_SRC_ALPHA 0x05 |
#define BLENDFACTOR_INV_SRC_ALPHA 0x06 |
#define BLENDFACTOR_DST_ALPHA 0x07 |
#define BLENDFACTOR_INV_DST_ALPHA 0x08 |
#define BLENDFACTOR_DST_COLR 0x09 |
#define BLENDFACTOR_INV_DST_COLR 0x0a |
#define BLENDFACTOR_SRC_ALPHA_SATURATE 0x0b |
#define BLENDFACTOR_CONST_COLOR 0x0c |
#define BLENDFACTOR_INV_CONST_COLOR 0x0d |
#define BLENDFACTOR_CONST_ALPHA 0x0e |
#define BLENDFACTOR_INV_CONST_ALPHA 0x0f |
#define BLENDFACTOR_MASK 0x0f |
/* _3DSTATE_MAP_BLEND_ARG, p152 */ |
#define _3DSTATE_MAP_BLEND_ARG_CMD(stage) (CMD_3D|(0x0e<<24)|((stage)<<20)) |
#define TEXPIPE_COLOR 0 |
#define TEXPIPE_ALPHA (1<<18) |
#define TEXPIPE_KILL (2<<18) |
#define TEXBLEND_ARG0 0 |
#define TEXBLEND_ARG1 (1<<15) |
#define TEXBLEND_ARG2 (2<<15) |
#define TEXBLEND_ARG3 (3<<15) |
#define TEXBLENDARG_MODIFY_PARMS (1<<6) |
#define TEXBLENDARG_REPLICATE_ALPHA (1<<5) |
#define TEXBLENDARG_INV_ARG (1<<4) |
#define TEXBLENDARG_ONE 0 |
#define TEXBLENDARG_FACTOR 0x01 |
#define TEXBLENDARG_ACCUM 0x02 |
#define TEXBLENDARG_DIFFUSE 0x03 |
#define TEXBLENDARG_SPEC 0x04 |
#define TEXBLENDARG_CURRENT 0x05 |
#define TEXBLENDARG_TEXEL0 0x06 |
#define TEXBLENDARG_TEXEL1 0x07 |
#define TEXBLENDARG_TEXEL2 0x08 |
#define TEXBLENDARG_TEXEL3 0x09 |
#define TEXBLENDARG_FACTOR_N 0x0e |
/* _3DSTATE_MAP_BLEND_OP, p155 */ |
#define _3DSTATE_MAP_BLEND_OP_CMD(stage) (CMD_3D|(0x0d<<24)|((stage)<<20)) |
#if 0 |
# define TEXPIPE_COLOR 0 |
# define TEXPIPE_ALPHA (1<<18) |
# define TEXPIPE_KILL (2<<18) |
#endif |
#define ENABLE_TEXOUTPUT_WRT_SEL (1<<17) |
#define TEXOP_OUTPUT_CURRENT 0 |
#define TEXOP_OUTPUT_ACCUM (1<<15) |
#define ENABLE_TEX_CNTRL_STAGE ((1<<12)|(1<<11)) |
#define DISABLE_TEX_CNTRL_STAGE (1<<12) |
#define TEXOP_SCALE_SHIFT 9 |
#define TEXOP_SCALE_1X (0 << TEXOP_SCALE_SHIFT) |
#define TEXOP_SCALE_2X (1 << TEXOP_SCALE_SHIFT) |
#define TEXOP_SCALE_4X (2 << TEXOP_SCALE_SHIFT) |
#define TEXOP_MODIFY_PARMS (1<<8) |
#define TEXOP_LAST_STAGE (1<<7) |
#define TEXBLENDOP_KILLPIXEL 0x02 |
#define TEXBLENDOP_ARG1 0x01 |
#define TEXBLENDOP_ARG2 0x02 |
#define TEXBLENDOP_MODULATE 0x03 |
#define TEXBLENDOP_ADD 0x06 |
#define TEXBLENDOP_ADDSIGNED 0x07 |
#define TEXBLENDOP_BLEND 0x08 |
#define TEXBLENDOP_BLEND_AND_ADD 0x09 |
#define TEXBLENDOP_SUBTRACT 0x0a |
#define TEXBLENDOP_DOT3 0x0b |
#define TEXBLENDOP_DOT4 0x0c |
#define TEXBLENDOP_MODULATE_AND_ADD 0x0d |
#define TEXBLENDOP_MODULATE_2X_AND_ADD 0x0e |
#define TEXBLENDOP_MODULATE_4X_AND_ADD 0x0f |
/* _3DSTATE_MAP_BUMP_TABLE, p160 TODO */ |
/* _3DSTATE_MAP_COLOR_CHROMA_KEY, p161 TODO */ |
#define _3DSTATE_MAP_COORD_TRANSFORM ((3<<29)|(0x1d<<24)|(0x8c<<16)) |
#define DISABLE_TEX_TRANSFORM (1<<28) |
#define TEXTURE_SET(x) (x<<29) |
#define _3DSTATE_VERTEX_TRANSFORM ((3<<29)|(0x1d<<24)|(0x8b<<16)) |
#define DISABLE_VIEWPORT_TRANSFORM (1<<31) |
#define DISABLE_PERSPECTIVE_DIVIDE (1<<29) |
/* _3DSTATE_MAP_COORD_SET_BINDINGS, p162 */ |
#define _3DSTATE_MAP_COORD_SETBIND_CMD (CMD_3D|(0x1d<<24)|(0x02<<16)) |
#define TEXBIND_MASK3 ((1<<15)|(1<<14)|(1<<13)|(1<<12)) |
#define TEXBIND_MASK2 ((1<<11)|(1<<10)|(1<<9)|(1<<8)) |
#define TEXBIND_MASK1 ((1<<7)|(1<<6)|(1<<5)|(1<<4)) |
#define TEXBIND_MASK0 ((1<<3)|(1<<2)|(1<<1)|1) |
#define TEXBIND_SET3(x) ((x)<<12) |
#define TEXBIND_SET2(x) ((x)<<8) |
#define TEXBIND_SET1(x) ((x)<<4) |
#define TEXBIND_SET0(x) (x) |
#define TEXCOORDSRC_KEEP 0 |
#define TEXCOORDSRC_DEFAULT 0x01 |
#define TEXCOORDSRC_VTXSET_0 0x08 |
#define TEXCOORDSRC_VTXSET_1 0x09 |
#define TEXCOORDSRC_VTXSET_2 0x0a |
#define TEXCOORDSRC_VTXSET_3 0x0b |
#define TEXCOORDSRC_VTXSET_4 0x0c |
#define TEXCOORDSRC_VTXSET_5 0x0d |
#define TEXCOORDSRC_VTXSET_6 0x0e |
#define TEXCOORDSRC_VTXSET_7 0x0f |
#define MAP_UNIT(unit) ((unit)<<16) |
#define MAP_UNIT_MASK (0x7<<16) |
/* _3DSTATE_MAP_COORD_SETS, p164 */ |
#define _3DSTATE_MAP_COORD_SET_CMD (CMD_3D|(0x1c<<24)|(0x01<<19)) |
#define TEXCOORD_SET(n) ((n)<<16) |
#define ENABLE_TEXCOORD_PARAMS (1<<15) |
#define TEXCOORDS_ARE_NORMAL (1<<14) |
#define TEXCOORDS_ARE_IN_TEXELUNITS 0 |
#define TEXCOORDTYPE_CARTESIAN 0 |
#define TEXCOORDTYPE_HOMOGENEOUS (1<<11) |
#define TEXCOORDTYPE_VECTOR (2<<11) |
#define TEXCOORDTYPE_MASK (0x7<<11) |
#define ENABLE_ADDR_V_CNTL (1<<7) |
#define ENABLE_ADDR_U_CNTL (1<<3) |
#define TEXCOORD_ADDR_V_MODE(x) ((x)<<4) |
#define TEXCOORD_ADDR_U_MODE(x) (x) |
#define TEXCOORDMODE_WRAP 0 |
#define TEXCOORDMODE_MIRROR 1 |
#define TEXCOORDMODE_CLAMP 2 |
#define TEXCOORDMODE_WRAP_SHORTEST 3 |
#define TEXCOORDMODE_CLAMP_BORDER 4 |
#define TEXCOORD_ADDR_V_MASK 0x70 |
#define TEXCOORD_ADDR_U_MASK 0x7 |
/* _3DSTATE_MAP_CUBE, p168 TODO */ |
#define _3DSTATE_MAP_CUBE (CMD_3D|(0x1c<<24)|(0x0a<<19)) |
#define CUBE_NEGX_ENABLE (1<<5) |
#define CUBE_POSX_ENABLE (1<<4) |
#define CUBE_NEGY_ENABLE (1<<3) |
#define CUBE_POSY_ENABLE (1<<2) |
#define CUBE_NEGZ_ENABLE (1<<1) |
#define CUBE_POSZ_ENABLE (1<<0) |
#define _3DSTATE_MAP_INFO_CMD (CMD_3D|(0x1d<<24)|(0x0<<16)|3) |
#define TEXMAP_INDEX(x) ((x)<<28) |
#define MAP_SURFACE_8BIT (1<<24) |
#define MAP_SURFACE_16BIT (2<<24) |
#define MAP_SURFACE_32BIT (3<<24) |
#define MAP_FORMAT_2D (0) |
#define MAP_FORMAT_3D_CUBE (1<<11) |
/* _3DSTATE_MODES_1, p190 */ |
#define _3DSTATE_MODES_1_CMD (CMD_3D|(0x08<<24)) |
#define BLENDFUNC_MASK 0x3f0000 |
#define ENABLE_COLR_BLND_FUNC (1<<21) |
#define BLENDFUNC_ADD 0 |
#define BLENDFUNC_SUB (1<<16) |
#define BLENDFUNC_RVRSE_SUB (2<<16) |
#define BLENDFUNC_MIN (3<<16) |
#define BLENDFUNC_MAX (4<<16) |
#define SRC_DST_BLND_MASK 0xfff |
#define ENABLE_SRC_BLND_FACTOR (1<<11) |
#define ENABLE_DST_BLND_FACTOR (1<<5) |
#define SRC_BLND_FACT(x) ((x)<<6) |
#define DST_BLND_FACT(x) (x) |
/* _3DSTATE_MODES_2, p192 */ |
#define _3DSTATE_MODES_2_CMD (CMD_3D|(0x0f<<24)) |
#define ENABLE_GLOBAL_DEPTH_BIAS (1<<22) |
#define GLOBAL_DEPTH_BIAS(x) ((x)<<14) |
#define ENABLE_ALPHA_TEST_FUNC (1<<13) |
#define ENABLE_ALPHA_REF_VALUE (1<<8) |
#define ALPHA_TEST_FUNC(x) ((x)<<9) |
#define ALPHA_REF_VALUE(x) (x) |
#define ALPHA_TEST_REF_MASK 0x3fff |
/* _3DSTATE_MODES_3, p193 */ |
#define _3DSTATE_MODES_3_CMD (CMD_3D|(0x02<<24)) |
#define DEPTH_TEST_FUNC_MASK 0x1f0000 |
#define ENABLE_DEPTH_TEST_FUNC (1<<20) |
/* Uses COMPAREFUNC */ |
#define DEPTH_TEST_FUNC(x) ((x)<<16) |
#define ENABLE_ALPHA_SHADE_MODE (1<<11) |
#define ENABLE_FOG_SHADE_MODE (1<<9) |
#define ENABLE_SPEC_SHADE_MODE (1<<7) |
#define ENABLE_COLOR_SHADE_MODE (1<<5) |
#define ALPHA_SHADE_MODE(x) ((x)<<10) |
#define FOG_SHADE_MODE(x) ((x)<<8) |
#define SPEC_SHADE_MODE(x) ((x)<<6) |
#define COLOR_SHADE_MODE(x) ((x)<<4) |
#define CULLMODE_MASK 0xf |
#define ENABLE_CULL_MODE (1<<3) |
#define CULLMODE_BOTH 0 |
#define CULLMODE_NONE 1 |
#define CULLMODE_CW 2 |
#define CULLMODE_CCW 3 |
#define SHADE_MODE_LINEAR 0 |
#define SHADE_MODE_FLAT 0x1 |
/* _3DSTATE_MODES_4, p195 */ |
#define _3DSTATE_MODES_4_CMD (CMD_3D|(0x16<<24)) |
#define ENABLE_LOGIC_OP_FUNC (1<<23) |
#define LOGIC_OP_FUNC(x) ((x)<<18) |
#define LOGICOP_MASK ((1<<18)|(1<<19)|(1<<20)|(1<<21)) |
#define LOGICOP_CLEAR 0 |
#define LOGICOP_NOR 0x1 |
#define LOGICOP_AND_INV 0x2 |
#define LOGICOP_COPY_INV 0x3 |
#define LOGICOP_AND_RVRSE 0x4 |
#define LOGICOP_INV 0x5 |
#define LOGICOP_XOR 0x6 |
#define LOGICOP_NAND 0x7 |
#define LOGICOP_AND 0x8 |
#define LOGICOP_EQUIV 0x9 |
#define LOGICOP_NOOP 0xa |
#define LOGICOP_OR_INV 0xb |
#define LOGICOP_COPY 0xc |
#define LOGICOP_OR_RVRSE 0xd |
#define LOGICOP_OR 0xe |
#define LOGICOP_SET 0xf |
#define MODE4_ENABLE_STENCIL_TEST_MASK ((1<<17)|(0xff00)) |
#define ENABLE_STENCIL_TEST_MASK (1<<17) |
#define STENCIL_TEST_MASK(x) ((x)<<8) |
#define MODE4_ENABLE_STENCIL_WRITE_MASK ((1<<16)|(0x00ff)) |
#define ENABLE_STENCIL_WRITE_MASK (1<<16) |
#define STENCIL_WRITE_MASK(x) ((x)&0xff) |
/* _3DSTATE_MODES_5, p196 */ |
#define _3DSTATE_MODES_5_CMD (CMD_3D|(0x0c<<24)) |
#define ENABLE_SPRITE_POINT_TEX (1<<23) |
#define SPRITE_POINT_TEX_ON (1<<22) |
#define SPRITE_POINT_TEX_OFF 0 |
#define FLUSH_RENDER_CACHE (1<<18) |
#define FLUSH_TEXTURE_CACHE (1<<16) |
#define FIXED_LINE_WIDTH_MASK 0xfc00 |
#define ENABLE_FIXED_LINE_WIDTH (1<<15) |
#define FIXED_LINE_WIDTH(x) ((x)<<10) |
#define FIXED_POINT_WIDTH_MASK 0x3ff |
#define ENABLE_FIXED_POINT_WIDTH (1<<9) |
#define FIXED_POINT_WIDTH(x) (x) |
/* _3DSTATE_RASTERIZATION_RULES, p198 */ |
#define _3DSTATE_RASTER_RULES_CMD (CMD_3D|(0x07<<24)) |
#define ENABLE_POINT_RASTER_RULE (1<<15) |
#define OGL_POINT_RASTER_RULE (1<<13) |
#define ENABLE_LINE_STRIP_PROVOKE_VRTX (1<<8) |
#define ENABLE_TRI_FAN_PROVOKE_VRTX (1<<5) |
#define ENABLE_TRI_STRIP_PROVOKE_VRTX (1<<2) |
#define LINE_STRIP_PROVOKE_VRTX(x) ((x)<<6) |
#define TRI_FAN_PROVOKE_VRTX(x) ((x)<<3) |
#define TRI_STRIP_PROVOKE_VRTX(x) (x) |
/* _3DSTATE_SCISSOR_ENABLE, p200 */ |
#define _3DSTATE_SCISSOR_ENABLE_CMD (CMD_3D|(0x1c<<24)|(0x10<<19)) |
#define ENABLE_SCISSOR_RECT ((1<<1) | 1) |
#define DISABLE_SCISSOR_RECT (1<<1) |
/* _3DSTATE_SCISSOR_RECTANGLE_0, p201 */ |
#define _3DSTATE_SCISSOR_RECT_0_CMD (CMD_3D|(0x1d<<24)|(0x81<<16)|1) |
/* Dword 1 */ |
#define SCISSOR_RECT_0_YMIN(x) ((x)<<16) |
#define SCISSOR_RECT_0_XMIN(x) (x) |
/* Dword 2 */ |
#define SCISSOR_RECT_0_YMAX(x) ((x)<<16) |
#define SCISSOR_RECT_0_XMAX(x) (x) |
/* _3DSTATE_STENCIL_TEST, p202 */ |
#define _3DSTATE_STENCIL_TEST_CMD (CMD_3D|(0x09<<24)) |
#define ENABLE_STENCIL_PARMS (1<<23) |
#define STENCIL_OPS_MASK (0xffc000) |
#define STENCIL_FAIL_OP(x) ((x)<<20) |
#define STENCIL_PASS_DEPTH_FAIL_OP(x) ((x)<<17) |
#define STENCIL_PASS_DEPTH_PASS_OP(x) ((x)<<14) |
#define ENABLE_STENCIL_TEST_FUNC_MASK ((1<<13)|(1<<12)|(1<<11)|(1<<10)|(1<<9)) |
#define ENABLE_STENCIL_TEST_FUNC (1<<13) |
/* Uses COMPAREFUNC */ |
#define STENCIL_TEST_FUNC(x) ((x)<<9) |
#define STENCIL_REF_VALUE_MASK ((1<<8)|0xff) |
#define ENABLE_STENCIL_REF_VALUE (1<<8) |
#define STENCIL_REF_VALUE(x) (x) |
/* _3DSTATE_VERTEX_FORMAT, p204 */ |
#define _3DSTATE_VFT0_CMD (CMD_3D|(0x05<<24)) |
#define VFT0_POINT_WIDTH (1<<12) |
#define VFT0_TEX_COUNT_MASK (7<<8) |
#define VFT0_TEX_COUNT_SHIFT 8 |
#define VFT0_TEX_COUNT(x) ((x)<<8) |
#define VFT0_SPEC (1<<7) |
#define VFT0_DIFFUSE (1<<6) |
#define VFT0_DEPTH_OFFSET (1<<5) |
#define VFT0_XYZ (1<<1) |
#define VFT0_XYZW (2<<1) |
#define VFT0_XY (3<<1) |
#define VFT0_XYW (4<<1) |
#define VFT0_XYZW_MASK (7<<1) |
/* _3DSTATE_VERTEX_FORMAT_2, p206 */ |
#define _3DSTATE_VERTEX_FORMAT_2_CMD (CMD_3D|(0x0a<<24)) |
#define VFT1_TEX7_FMT(x) ((x)<<14) |
#define VFT1_TEX6_FMT(x) ((x)<<12) |
#define VFT1_TEX5_FMT(x) ((x)<<10) |
#define VFT1_TEX4_FMT(x) ((x)<<8) |
#define VFT1_TEX3_FMT(x) ((x)<<6) |
#define VFT1_TEX2_FMT(x) ((x)<<4) |
#define VFT1_TEX1_FMT(x) ((x)<<2) |
#define VFT1_TEX0_FMT(x) (x) |
#define VFT1_TEX0_MASK 3 |
#define VFT1_TEX1_SHIFT 2 |
#define TEXCOORDFMT_2D 0 |
#define TEXCOORDFMT_3D 1 |
#define TEXCOORDFMT_4D 2 |
#define TEXCOORDFMT_1D 3 |
/*New stuff picked up along the way */ |
#define MLC_LOD_BIAS_MASK ((1<<7)-1) |
/* _3DSTATE_VERTEX_TRANSFORM, p207 */ |
#define _3DSTATE_VERTEX_TRANS_CMD (CMD_3D|(0x1d<<24)|(0x8b<<16)|0) |
#define _3DSTATE_VERTEX_TRANS_MTX_CMD (CMD_3D|(0x1d<<24)|(0x8b<<16)|6) |
/* Dword 1 */ |
#define ENABLE_VIEWPORT_TRANSFORM ((1<<31)|(1<<30)) |
#define DISABLE_VIEWPORT_TRANSFORM (1<<31) |
#define ENABLE_PERSP_DIVIDE ((1<<29)|(1<<28)) |
#define DISABLE_PERSP_DIVIDE (1<<29) |
#define VRTX_TRANS_LOAD_MATRICES 0x7421 |
#define VRTX_TRANS_NO_LOAD_MATRICES 0x0000 |
/* Dword 2 -> 7 are matrix elements */ |
/* _3DSTATE_W_STATE, p209 */ |
#define _3DSTATE_W_STATE_CMD (CMD_3D|(0x1d<<24)|(0x8d<<16)|1) |
/* Dword 1 */ |
#define MAGIC_W_STATE_DWORD1 0x00000008 |
/* Dword 2 */ |
#define WFAR_VALUE(x) (x) |
/* Stipple command, carried over from the i810, apparently: |
*/ |
#define _3DSTATE_STIPPLE (CMD_3D|(0x1d<<24)|(0x83<<16)) |
#define ST1_ENABLE (1<<16) |
#define ST1_MASK (0xffff) |
#define _3DSTATE_LOAD_STATE_IMMEDIATE_1 (CMD_3D|(0x1d<<24)|(0x04<<16)) |
#define I1_LOAD_S(n) (1<<((n)+4)) |
#define S3_POINT_WIDTH_SHIFT 23 |
#define S3_LINE_WIDTH_SHIFT 19 |
#define S3_ALPHA_SHADE_MODE_SHIFT 18 |
#define S3_FOG_SHADE_MODE_SHIFT 17 |
#define S3_SPEC_SHADE_MODE_SHIFT 16 |
#define S3_COLOR_SHADE_MODE_SHIFT 15 |
#define S3_CULL_MODE_SHIFT 13 |
#define S3_CULLMODE_BOTH (0) |
#define S3_CULLMODE_NONE (1<<13) |
#define S3_CULLMODE_CW (2<<13) |
#define S3_CULLMODE_CCW (3<<13) |
#define S3_POINT_WIDTH_PRESENT (1<<12) |
#define S3_SPEC_FOG_PRESENT (1<<11) |
#define S3_DIFFUSE_PRESENT (1<<10) |
#define S3_DEPTH_OFFSET_PRESENT (1<<9) |
#define S3_POSITION_SHIFT 6 |
#define S3_VERTEXHAS_XYZ (1<<6) |
#define S3_VERTEXHAS_XYZW (2<<6) |
#define S3_VERTEXHAS_XY (3<<6) |
#define S3_VERTEXHAS_XYW (4<<6) |
#define S3_ENABLE_SPEC_ADD (1<<5) |
#define S3_ENABLE_FOG (1<<4) |
#define S3_ENABLE_LOCAL_DEPTH_BIAS (1<<3) |
#define S3_ENABLE_SPRITE_POINT (1<<1) |
#define S3_ENABLE_ANTIALIASING 1 |
#define S8_ENABLE_ALPHA_TEST (1<<31) |
#define S8_ALPHA_TEST_FUNC_SHIFT 28 |
#define S8_ALPHA_REFVALUE_SHIFT 20 |
#define S8_ENABLE_DEPTH_TEST (1<<19) |
#define S8_DEPTH_TEST_FUNC_SHIFT 16 |
#define S8_ENABLE_COLOR_BLEND (1<<15) |
#define S8_COLOR_BLEND_FUNC_SHIFT 12 |
#define S8_BLENDFUNC_ADD (0) |
#define S8_BLENDFUNC_SUB (1<<12) |
#define S8_BLENDFUNC_RVRSE_SUB (2<<12) |
#define S8_BLENDFUNC_MIN (3<<12) |
#define S8_BLENDFUNC_MAX (4<<12) |
#define S8_SRC_BLEND_FACTOR_SHIFT 8 |
#define S8_DST_BLEND_FACTOR_SHIFT 4 |
#define S8_ENABLE_DEPTH_BUFFER_WRITE (1<<3) |
#define S8_ENABLE_COLOR_BUFFER_WRITE (1<<2) |
#define _3DSTATE_LOAD_STATE_IMMEDIATE_2 (CMD_3D|(0x1d<<24)|(0x03<<16)) |
#define LOAD_TEXTURE_MAP(x) (1<<((x)+11)) |
#define LOAD_TEXTURE_BLEND_STAGE(x) (1<<((x)+7)) |
#define LOAD_GLOBAL_COLOR_FACTOR (1<<6) |
#define TM0S0_ADDRESS_MASK 0xfffffffc |
#define TM0S0_USE_FENCE (1<<1) |
#define TM0S1_HEIGHT_SHIFT 21 |
#define TM0S1_WIDTH_SHIFT 10 |
#define TM0S1_PALETTE_SELECT (1<<9) |
#define TM0S1_MAPSURF_FORMAT_MASK (0x7 << 6) |
#define TM0S1_MAPSURF_FORMAT_SHIFT 6 |
#define MAPSURF_8BIT_INDEXED (0<<6) |
#define MAPSURF_8BIT (1<<6) |
#define MAPSURF_16BIT (2<<6) |
#define MAPSURF_32BIT (3<<6) |
#define MAPSURF_411 (4<<6) |
#define MAPSURF_422 (5<<6) |
#define MAPSURF_COMPRESSED (6<<6) |
#define MAPSURF_4BIT_INDEXED (7<<6) |
#define TM0S1_MT_FORMAT_MASK (0x7 << 3) |
#define TM0S1_MT_FORMAT_SHIFT 3 |
#define MT_4BIT_IDX_ARGB8888 (7<<3) /* SURFACE_4BIT_INDEXED */ |
#define MT_8BIT_IDX_RGB565 (0<<3) /* SURFACE_8BIT_INDEXED */ |
#define MT_8BIT_IDX_ARGB1555 (1<<3) |
#define MT_8BIT_IDX_ARGB4444 (2<<3) |
#define MT_8BIT_IDX_AY88 (3<<3) |
#define MT_8BIT_IDX_ABGR8888 (4<<3) |
#define MT_8BIT_IDX_BUMP_88DVDU (5<<3) |
#define MT_8BIT_IDX_BUMP_655LDVDU (6<<3) |
#define MT_8BIT_IDX_ARGB8888 (7<<3) |
#define MT_8BIT_I8 (0<<3) /* SURFACE_8BIT */ |
#define MT_8BIT_L8 (1<<3) |
#define MT_8BIT_A8 (4<<3) |
#define MT_16BIT_RGB565 (0<<3) /* SURFACE_16BIT */ |
#define MT_16BIT_ARGB1555 (1<<3) |
#define MT_16BIT_ARGB4444 (2<<3) |
#define MT_16BIT_AY88 (3<<3) |
#define MT_16BIT_DIB_ARGB1555_8888 (4<<3) |
#define MT_16BIT_BUMP_88DVDU (5<<3) |
#define MT_16BIT_BUMP_655LDVDU (6<<3) |
#define MT_16BIT_DIB_RGB565_8888 (7<<3) |
#define MT_32BIT_ARGB8888 (0<<3) /* SURFACE_32BIT */ |
#define MT_32BIT_ABGR8888 (1<<3) |
#define MT_32BIT_XRGB8888 (2<<3) |
#define MT_32BIT_XBGR8888 (3<<3) |
#define MT_32BIT_BUMP_XLDVDU_8888 (6<<3) |
#define MT_32BIT_DIB_8888 (7<<3) |
#define MT_411_YUV411 (0<<3) /* SURFACE_411 */ |
#define MT_422_YCRCB_SWAPY (0<<3) /* SURFACE_422 */ |
#define MT_422_YCRCB_NORMAL (1<<3) |
#define MT_422_YCRCB_SWAPUV (2<<3) |
#define MT_422_YCRCB_SWAPUVY (3<<3) |
#define MT_COMPRESS_DXT1 (0<<3) /* SURFACE_COMPRESSED */ |
#define MT_COMPRESS_DXT2_3 (1<<3) |
#define MT_COMPRESS_DXT4_5 (2<<3) |
#define MT_COMPRESS_FXT1 (3<<3) |
#define TM0S1_COLORSPACE_CONVERSION (1 << 2) |
#define TM0S1_TILED_SURFACE (1 << 1) |
#define TM0S1_TILE_WALK (1 << 0) |
#define TM0S2_PITCH_SHIFT 21 |
#define TM0S2_CUBE_FACE_ENA_SHIFT 15 |
#define TM0S2_CUBE_FACE_ENA_MASK (1<<15) |
#define TM0S2_MAP_FORMAT (1<<14) |
#define TM0S2_MAP_2D (0<<14) |
#define TM0S2_MAP_3D_CUBE (1<<14) |
#define TM0S2_VERTICAL_LINE_STRIDE (1<<13) |
#define TM0S2_VERITCAL_LINE_STRIDE_OFF (1<<12) |
#define TM0S2_OUTPUT_CHAN_SHIFT 10 |
#define TM0S2_OUTPUT_CHAN_MASK (3<<10) |
#define TM0S3_MIP_FILTER_MASK (0x3<<30) |
#define TM0S3_MIP_FILTER_SHIFT 30 |
#define MIPFILTER_NONE 0 |
#define MIPFILTER_NEAREST 1 |
#define MIPFILTER_LINEAR 3 |
#define TM0S3_MAG_FILTER_MASK (0x3<<28) |
#define TM0S3_MAG_FILTER_SHIFT 28 |
#define TM0S3_MIN_FILTER_MASK (0x3<<26) |
#define TM0S3_MIN_FILTER_SHIFT 26 |
#define FILTER_NEAREST 0 |
#define FILTER_LINEAR 1 |
#define FILTER_ANISOTROPIC 2 |
#define TM0S3_LOD_BIAS_SHIFT 17 |
#define TM0S3_LOD_BIAS_MASK (0x1ff<<17) |
#define TM0S3_MAX_MIP_SHIFT 9 |
#define TM0S3_MAX_MIP_MASK (0xff<<9) |
#define TM0S3_MIN_MIP_SHIFT 3 |
#define TM0S3_MIN_MIP_MASK (0x3f<<3) |
#define TM0S3_KILL_PIXEL (1<<2) |
#define TM0S3_KEYED_FILTER (1<<1) |
#define TM0S3_CHROMA_KEY (1<<0) |
/* _3DSTATE_MAP_TEXEL_STREAM, p188 */ |
#define _3DSTATE_MAP_TEX_STREAM_CMD (CMD_3D|(0x1c<<24)|(0x05<<19)) |
#define DISABLE_TEX_STREAM_BUMP (1<<12) |
#define ENABLE_TEX_STREAM_BUMP ((1<<12)|(1<<11)) |
#define TEX_MODIFY_UNIT_0 0 |
#define TEX_MODIFY_UNIT_1 (1<<8) |
#define ENABLE_TEX_STREAM_COORD_SET (1<<7) |
#define TEX_STREAM_COORD_SET(x) ((x)<<4) |
#define ENABLE_TEX_STREAM_MAP_IDX (1<<3) |
#define TEX_STREAM_MAP_IDX(x) (x) |
#define FLUSH_MAP_CACHE (1<<0) |
#define _3DSTATE_MAP_FILTER_CMD (CMD_3D|(0x1c<<24)|(0x02<<19)) |
#define FILTER_TEXMAP_INDEX(x) ((x) << 16) |
#define MAG_MODE_FILTER_ENABLE (1 << 5) |
#define MIN_MODE_FILTER_ENABLE (1 << 2) |
#define MAG_MAPFILTER_NEAREST (0 << 3) |
#define MAG_MAPFILTER_LINEAR (1 << 3) |
#define MAG_MAPFILTER_ANISOTROPIC (2 << 3) |
#define MIN_MAPFILTER_NEAREST (0) |
#define MIN_MAPFILTER_LINEAR (1) |
#define MIN_MAPFILTER_ANISOTROPIC (2) |
#define ENABLE_KEYS (1<<15) |
#define DISABLE_COLOR_KEY 0 |
#define DISABLE_CHROMA_KEY 0 |
#define DISABLE_KILL_PIXEL 0 |
#define ENABLE_MIP_MODE_FILTER (1 << 9) |
#define MIPFILTER_NONE 0 |
#define MIPFILTER_NEAREST 1 |
#define MIPFILTER_LINEAR 3 |
#endif |
/drivers/video/Intel-2D/uxa/i965_3d.c |
---|
0,0 → 1,443 |
/* |
* Copyright © 2011 Intel Corporation |
* |
* Permission is hereby granted, free of charge, to any person obtaining a |
* copy of this software and associated documentation files (the "Software"), |
* to deal in the Software without restriction, including without limitation |
* the rights to use, copy, modify, merge, publish, distribute, sublicense, |
* and/or sell copies of the Software, and to permit persons to whom the |
* Software is furnished to do so, subject to the following conditions: |
* |
* The above copyright notice and this permission notice (including the next |
* paragraph) shall be included in all copies or substantial portions of the |
* Software. |
* |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
* DEALINGS IN THE SOFTWARE. |
*/ |
#ifdef HAVE_CONFIG_H |
#include "config.h" |
#endif |
#include <string.h> |
#include "intel.h" |
#include "i965_reg.h" |
#include "brw_defines.h" |
#include "brw_structs.h" |
void |
gen6_upload_invariant_states(intel_screen_private *intel) |
{ |
Bool ivb = INTEL_INFO(intel)->gen >= 070; |
OUT_BATCH(BRW_PIPE_CONTROL | (4 - 2)); |
OUT_BATCH(BRW_PIPE_CONTROL_IS_FLUSH | |
BRW_PIPE_CONTROL_WC_FLUSH | |
BRW_PIPE_CONTROL_DEPTH_CACHE_FLUSH | |
BRW_PIPE_CONTROL_NOWRITE); |
OUT_BATCH(0); /* write address */ |
OUT_BATCH(0); /* write data */ |
OUT_BATCH(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D); |
OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE | ((ivb ? 4 : 3) - 2)); |
OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER | |
GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_1); /* 1 sample/pixel */ |
OUT_BATCH(0); |
if (ivb) |
OUT_BATCH(0); |
OUT_BATCH(GEN6_3DSTATE_SAMPLE_MASK | (2 - 2)); |
OUT_BATCH(1); |
/* Set system instruction pointer */ |
OUT_BATCH(BRW_STATE_SIP | 0); |
OUT_BATCH(0); |
} |
void |
gen6_upload_viewport_state_pointers(intel_screen_private *intel, |
drm_intel_bo *cc_vp_bo) |
{ |
OUT_BATCH(GEN6_3DSTATE_VIEWPORT_STATE_POINTERS | |
GEN6_3DSTATE_VIEWPORT_STATE_MODIFY_CC | |
(4 - 2)); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_RELOC(cc_vp_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); |
} |
void |
gen7_upload_viewport_state_pointers(intel_screen_private *intel, |
drm_intel_bo *cc_vp_bo) |
{ |
OUT_BATCH(GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC | (2 - 2)); |
OUT_RELOC(cc_vp_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); |
OUT_BATCH(GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CL | (2 - 2)); |
OUT_BATCH(0); |
} |
void |
gen6_upload_urb(intel_screen_private *intel) |
{ |
OUT_BATCH(GEN6_3DSTATE_URB | (3 - 2)); |
OUT_BATCH(((1 - 1) << GEN6_3DSTATE_URB_VS_SIZE_SHIFT) | |
(24 << GEN6_3DSTATE_URB_VS_ENTRIES_SHIFT)); /* at least 24 on GEN6 */ |
OUT_BATCH((0 << GEN6_3DSTATE_URB_GS_SIZE_SHIFT) | |
(0 << GEN6_3DSTATE_URB_GS_ENTRIES_SHIFT)); /* no GS thread */ |
} |
/* |
* URB layout on GEN7 |
* ---------------------------------------- |
* | PS Push Constants (8KB) | VS entries | |
* ---------------------------------------- |
*/ |
void |
gen7_upload_urb(intel_screen_private *intel) |
{ |
unsigned int num_urb_entries = 32; |
if (IS_HSW(intel)) |
num_urb_entries = 64; |
OUT_BATCH(GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS | (2 - 2)); |
OUT_BATCH(8); /* in 1KBs */ |
OUT_BATCH(GEN7_3DSTATE_URB_VS | (2 - 2)); |
OUT_BATCH( |
(num_urb_entries << GEN7_URB_ENTRY_NUMBER_SHIFT) | |
(2 - 1) << GEN7_URB_ENTRY_SIZE_SHIFT | |
(1 << GEN7_URB_STARTING_ADDRESS_SHIFT)); |
OUT_BATCH(GEN7_3DSTATE_URB_GS | (2 - 2)); |
OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT) | |
(1 << GEN7_URB_STARTING_ADDRESS_SHIFT)); |
OUT_BATCH(GEN7_3DSTATE_URB_HS | (2 - 2)); |
OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT) | |
(2 << GEN7_URB_STARTING_ADDRESS_SHIFT)); |
OUT_BATCH(GEN7_3DSTATE_URB_DS | (2 - 2)); |
OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT) | |
(2 << GEN7_URB_STARTING_ADDRESS_SHIFT)); |
} |
void |
gen6_upload_cc_state_pointers(intel_screen_private *intel, |
drm_intel_bo *blend_bo, |
drm_intel_bo *cc_bo, |
drm_intel_bo *depth_stencil_bo, |
uint32_t blend_offset) |
{ |
OUT_BATCH(GEN6_3DSTATE_CC_STATE_POINTERS | (4 - 2)); |
if (blend_bo) |
OUT_RELOC(blend_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, |
blend_offset | 1); |
else |
OUT_BATCH(0); |
if (depth_stencil_bo) |
OUT_RELOC(depth_stencil_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1); |
else |
OUT_BATCH(0); |
if (cc_bo) |
OUT_RELOC(cc_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1); |
else |
OUT_BATCH(0); |
} |
void |
gen7_upload_cc_state_pointers(intel_screen_private *intel, |
drm_intel_bo *blend_bo, |
drm_intel_bo *cc_bo, |
drm_intel_bo *depth_stencil_bo, |
uint32_t blend_offset) |
{ |
OUT_BATCH(GEN7_3DSTATE_BLEND_STATE_POINTERS | (2 - 2)); |
if (blend_bo) |
OUT_RELOC(blend_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, |
blend_offset | 1); |
else |
OUT_BATCH(0); |
OUT_BATCH(GEN6_3DSTATE_CC_STATE_POINTERS | (2 - 2)); |
if (cc_bo) |
OUT_RELOC(cc_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1); |
else |
OUT_BATCH(0); |
OUT_BATCH(GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS | (2 - 2)); |
if (depth_stencil_bo) |
OUT_RELOC(depth_stencil_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1); |
else |
OUT_BATCH(0); |
} |
void |
gen6_upload_sampler_state_pointers(intel_screen_private *intel, |
drm_intel_bo *sampler_bo) |
{ |
OUT_BATCH(GEN6_3DSTATE_SAMPLER_STATE_POINTERS | |
GEN6_3DSTATE_SAMPLER_STATE_MODIFY_PS | |
(4 - 2)); |
OUT_BATCH(0); /* VS */ |
OUT_BATCH(0); /* GS */ |
OUT_RELOC(sampler_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); |
} |
void |
gen7_upload_sampler_state_pointers(intel_screen_private *intel, |
drm_intel_bo *sampler_bo) |
{ |
OUT_BATCH(GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS | (2 - 2)); |
OUT_RELOC(sampler_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); |
} |
void |
gen7_upload_bypass_states(intel_screen_private *intel) |
{ |
/* bypass GS */ |
OUT_BATCH(GEN6_3DSTATE_CONSTANT_GS | (7 - 2)); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(GEN6_3DSTATE_GS | (7 - 2)); |
OUT_BATCH(0); /* without GS kernel */ |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); /* pass-through */ |
OUT_BATCH(GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS | (2 - 2)); |
OUT_BATCH(0); |
/* disable HS */ |
OUT_BATCH(GEN7_3DSTATE_CONSTANT_HS | (7 - 2)); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(GEN7_3DSTATE_HS | (7 - 2)); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS | (2 - 2)); |
OUT_BATCH(0); |
/* Disable TE */ |
OUT_BATCH(GEN7_3DSTATE_TE | (4 - 2)); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
/* Disable DS */ |
OUT_BATCH(GEN7_3DSTATE_CONSTANT_DS | (7 - 2)); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(GEN7_3DSTATE_DS | (6 - 2)); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS | (2 - 2)); |
OUT_BATCH(0); |
/* Disable STREAMOUT */ |
OUT_BATCH(GEN7_3DSTATE_STREAMOUT | (3 - 2)); |
OUT_BATCH(0); |
OUT_BATCH(0); |
} |
void |
gen6_upload_vs_state(intel_screen_private *intel) |
{ |
Bool ivb = INTEL_INFO(intel)->gen >= 070; |
/* disable VS constant buffer */ |
OUT_BATCH(GEN6_3DSTATE_CONSTANT_VS | ((ivb ? 7 : 5) - 2)); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
if (ivb) { |
OUT_BATCH(0); |
OUT_BATCH(0); |
} |
OUT_BATCH(GEN6_3DSTATE_VS | (6 - 2)); |
OUT_BATCH(0); /* without VS kernel */ |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); /* pass-through */ |
} |
void |
gen6_upload_gs_state(intel_screen_private *intel) |
{ |
/* disable GS constant buffer */ |
OUT_BATCH(GEN6_3DSTATE_CONSTANT_GS | (5 - 2)); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(GEN6_3DSTATE_GS | (7 - 2)); |
OUT_BATCH(0); /* without GS kernel */ |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); /* pass-through */ |
} |
void |
gen6_upload_clip_state(intel_screen_private *intel) |
{ |
OUT_BATCH(GEN6_3DSTATE_CLIP | (4 - 2)); |
OUT_BATCH(0); |
OUT_BATCH(0); /* pass-through */ |
OUT_BATCH(0); |
} |
void |
gen6_upload_sf_state(intel_screen_private *intel, |
int num_sf_outputs, |
int read_offset) |
{ |
OUT_BATCH(GEN6_3DSTATE_SF | (20 - 2)); |
OUT_BATCH((num_sf_outputs << GEN6_3DSTATE_SF_NUM_OUTPUTS_SHIFT) | |
(1 << GEN6_3DSTATE_SF_URB_ENTRY_READ_LENGTH_SHIFT) | |
(read_offset << GEN6_3DSTATE_SF_URB_ENTRY_READ_OFFSET_SHIFT)); |
OUT_BATCH(0); |
OUT_BATCH(GEN6_3DSTATE_SF_CULL_NONE); |
OUT_BATCH(2 << GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT); /* DW4 */ |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); /* DW9 */ |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); /* DW14 */ |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); /* DW19 */ |
} |
void |
gen7_upload_sf_state(intel_screen_private *intel, |
int num_sf_outputs, |
int read_offset) |
{ |
OUT_BATCH(GEN7_3DSTATE_SBE | (14 - 2)); |
OUT_BATCH((num_sf_outputs << GEN7_SBE_NUM_OUTPUTS_SHIFT) | |
(1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT) | |
(read_offset << GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT)); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); /* DW4 */ |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); /* DW9 */ |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(GEN6_3DSTATE_SF | (7 - 2)); |
OUT_BATCH(0); |
OUT_BATCH(GEN6_3DSTATE_SF_CULL_NONE); |
OUT_BATCH(2 << GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
} |
void |
gen6_upload_binding_table(intel_screen_private *intel, |
uint32_t ps_binding_table_offset) |
{ |
/* Binding table pointers */ |
OUT_BATCH(BRW_3DSTATE_BINDING_TABLE_POINTERS | |
GEN6_3DSTATE_BINDING_TABLE_MODIFY_PS | |
(4 - 2)); |
OUT_BATCH(0); /* VS */ |
OUT_BATCH(0); /* GS */ |
/* Only the PS uses the binding table */ |
OUT_BATCH(ps_binding_table_offset); |
} |
void |
gen7_upload_binding_table(intel_screen_private *intel, |
uint32_t ps_binding_table_offset) |
{ |
OUT_BATCH(GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS | (2 - 2)); |
OUT_BATCH(ps_binding_table_offset); |
} |
void |
gen6_upload_depth_buffer_state(intel_screen_private *intel) |
{ |
OUT_BATCH(BRW_3DSTATE_DEPTH_BUFFER | (7 - 2)); |
OUT_BATCH((BRW_SURFACE_NULL << BRW_3DSTATE_DEPTH_BUFFER_TYPE_SHIFT) | |
(BRW_DEPTHFORMAT_D32_FLOAT << BRW_3DSTATE_DEPTH_BUFFER_FORMAT_SHIFT)); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(BRW_3DSTATE_CLEAR_PARAMS | (2 - 2)); |
OUT_BATCH(0); |
} |
void |
gen7_upload_depth_buffer_state(intel_screen_private *intel) |
{ |
OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER | (7 - 2)); |
OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) | (BRW_SURFACE_NULL << 29)); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS | (3 - 2)); |
OUT_BATCH(0); |
OUT_BATCH(0); |
} |
/drivers/video/Intel-2D/uxa/i965_reg.h |
---|
0,0 → 1,503 |
/************************************************************************** |
* |
* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
* All Rights Reserved. |
* |
* Permission is hereby granted, free of charge, to any person obtaining a |
* copy of this software and associated documentation files (the |
* "Software"), to deal in the Software without restriction, including |
* without limitation the rights to use, copy, modify, merge, publish, |
* distribute, sub license, and/or sell copies of the Software, and to |
* permit persons to whom the Software is furnished to do so, subject to |
* the following conditions: |
* |
* The above copyright notice and this permission notice (including the |
* next paragraph) shall be included in all copies or substantial portions |
* of the Software. |
* |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
* |
**************************************************************************/ |
/* |
* New regs for broadwater -- we need to split this file up sensibly somehow. |
*/ |
#define BRW_3D(Pipeline,Opcode,Subopcode) ((3 << 29) | \ |
((Pipeline) << 27) | \ |
((Opcode) << 24) | \ |
((Subopcode) << 16)) |
#define BRW_URB_FENCE BRW_3D(0, 0, 0) |
#define BRW_CS_URB_STATE BRW_3D(0, 0, 1) |
#define BRW_CONSTANT_BUFFER BRW_3D(0, 0, 2) |
#define BRW_STATE_PREFETCH BRW_3D(0, 0, 3) |
#define BRW_STATE_BASE_ADDRESS BRW_3D(0, 1, 1) |
#define BRW_STATE_SIP BRW_3D(0, 1, 2) |
#define BRW_PIPELINE_SELECT BRW_3D(0, 1, 4) |
#define NEW_PIPELINE_SELECT BRW_3D(1, 1, 4) |
#define BRW_MEDIA_STATE_POINTERS BRW_3D(2, 0, 0) |
#define BRW_MEDIA_OBJECT BRW_3D(2, 1, 0) |
#define BRW_3DSTATE_PIPELINED_POINTERS BRW_3D(3, 0, 0) |
#define BRW_3DSTATE_BINDING_TABLE_POINTERS BRW_3D(3, 0, 1) |
# define GEN6_3DSTATE_BINDING_TABLE_MODIFY_PS (1 << 12)/* for GEN6 */ |
# define GEN6_3DSTATE_BINDING_TABLE_MODIFY_GS (1 << 9) /* for GEN6 */ |
# define GEN6_3DSTATE_BINDING_TABLE_MODIFY_VS (1 << 8) /* for GEN6 */ |
#define BRW_3DSTATE_VERTEX_BUFFERS BRW_3D(3, 0, 8) |
#define BRW_3DSTATE_VERTEX_ELEMENTS BRW_3D(3, 0, 9) |
#define BRW_3DSTATE_INDEX_BUFFER BRW_3D(3, 0, 0xa) |
#define BRW_3DSTATE_VF_STATISTICS BRW_3D(3, 0, 0xb) |
#define BRW_3DSTATE_DRAWING_RECTANGLE BRW_3D(3, 1, 0) |
#define BRW_3DSTATE_CONSTANT_COLOR BRW_3D(3, 1, 1) |
#define BRW_3DSTATE_SAMPLER_PALETTE_LOAD BRW_3D(3, 1, 2) |
#define BRW_3DSTATE_CHROMA_KEY BRW_3D(3, 1, 4) |
#define BRW_3DSTATE_DEPTH_BUFFER BRW_3D(3, 1, 5) |
# define BRW_3DSTATE_DEPTH_BUFFER_TYPE_SHIFT 29 |
# define BRW_3DSTATE_DEPTH_BUFFER_FORMAT_SHIFT 18 |
#define BRW_3DSTATE_POLY_STIPPLE_OFFSET BRW_3D(3, 1, 6) |
#define BRW_3DSTATE_POLY_STIPPLE_PATTERN BRW_3D(3, 1, 7) |
#define BRW_3DSTATE_LINE_STIPPLE BRW_3D(3, 1, 8) |
#define BRW_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP BRW_3D(3, 1, 9) |
/* These two are BLC and CTG only, not BW or CL */ |
#define BRW_3DSTATE_AA_LINE_PARAMS BRW_3D(3, 1, 0xa) |
#define BRW_3DSTATE_GS_SVB_INDEX BRW_3D(3, 1, 0xb) |
#define BRW_PIPE_CONTROL BRW_3D(3, 2, 0) |
#define BRW_3DPRIMITIVE BRW_3D(3, 3, 0) |
#define BRW_3DSTATE_CLEAR_PARAMS BRW_3D(3, 1, 0x10) |
/* DW1 */ |
# define BRW_3DSTATE_DEPTH_CLEAR_VALID (1 << 15) |
/* for GEN6+ */ |
#define GEN6_3DSTATE_SAMPLER_STATE_POINTERS BRW_3D(3, 0, 0x02) |
# define GEN6_3DSTATE_SAMPLER_STATE_MODIFY_PS (1 << 12) |
# define GEN6_3DSTATE_SAMPLER_STATE_MODIFY_GS (1 << 9) |
# define GEN6_3DSTATE_SAMPLER_STATE_MODIFY_VS (1 << 8) |
#define GEN6_3DSTATE_URB BRW_3D(3, 0, 0x05) |
/* DW1 */ |
# define GEN6_3DSTATE_URB_VS_SIZE_SHIFT 16 |
# define GEN6_3DSTATE_URB_VS_ENTRIES_SHIFT 0 |
/* DW2 */ |
# define GEN6_3DSTATE_URB_GS_ENTRIES_SHIFT 8 |
# define GEN6_3DSTATE_URB_GS_SIZE_SHIFT 0 |
#define GEN6_3DSTATE_VIEWPORT_STATE_POINTERS BRW_3D(3, 0, 0x0d) |
# define GEN6_3DSTATE_VIEWPORT_STATE_MODIFY_CC (1 << 12) |
# define GEN6_3DSTATE_VIEWPORT_STATE_MODIFY_SF (1 << 11) |
# define GEN6_3DSTATE_VIEWPORT_STATE_MODIFY_CLIP (1 << 10) |
#define GEN6_3DSTATE_CC_STATE_POINTERS BRW_3D(3, 0, 0x0e) |
#define GEN6_3DSTATE_VS BRW_3D(3, 0, 0x10) |
#define GEN6_3DSTATE_GS BRW_3D(3, 0, 0x11) |
/* DW4 */ |
# define GEN6_3DSTATE_GS_DISPATCH_START_GRF_SHIFT 0 |
#define GEN6_3DSTATE_CLIP BRW_3D(3, 0, 0x12) |
#define GEN6_3DSTATE_SF BRW_3D(3, 0, 0x13) |
/* DW1 */ |
# define GEN6_3DSTATE_SF_NUM_OUTPUTS_SHIFT 22 |
# define GEN6_3DSTATE_SF_URB_ENTRY_READ_LENGTH_SHIFT 11 |
# define GEN6_3DSTATE_SF_URB_ENTRY_READ_OFFSET_SHIFT 4 |
/* DW2 */ |
/* DW3 */ |
# define GEN6_3DSTATE_SF_CULL_BOTH (0 << 29) |
# define GEN6_3DSTATE_SF_CULL_NONE (1 << 29) |
# define GEN6_3DSTATE_SF_CULL_FRONT (2 << 29) |
# define GEN6_3DSTATE_SF_CULL_BACK (3 << 29) |
/* DW4 */ |
# define GEN6_3DSTATE_SF_TRI_PROVOKE_SHIFT 29 |
# define GEN6_3DSTATE_SF_LINE_PROVOKE_SHIFT 27 |
# define GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT 25 |
#define GEN6_3DSTATE_WM BRW_3D(3, 0, 0x14) |
/* DW2 */ |
# define GEN6_3DSTATE_WM_SAMPLER_COUNT_SHITF 27 |
# define GEN6_3DSTATE_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT 18 |
/* DW4 */ |
# define GEN6_3DSTATE_WM_DISPATCH_START_GRF_0_SHIFT 16 |
/* DW5 */ |
# define GEN6_3DSTATE_WM_MAX_THREADS_SHIFT 25 |
# define GEN6_3DSTATE_WM_DISPATCH_ENABLE (1 << 19) |
# define GEN6_3DSTATE_WM_16_DISPATCH_ENABLE (1 << 1) |
# define GEN6_3DSTATE_WM_8_DISPATCH_ENABLE (1 << 0) |
/* DW6 */ |
# define GEN6_3DSTATE_WM_NUM_SF_OUTPUTS_SHIFT 20 |
# define GEN6_3DSTATE_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC (1 << 15) |
# define GEN6_3DSTATE_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC (1 << 14) |
# define GEN6_3DSTATE_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC (1 << 13) |
# define GEN6_3DSTATE_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC (1 << 12) |
# define GEN6_3DSTATE_WM_PERSPECTIVE_CENTROID_BARYCENTRIC (1 << 11) |
# define GEN6_3DSTATE_WM_PERSPECTIVE_PIXEL_BARYCENTRIC (1 << 10) |
#define GEN6_3DSTATE_CONSTANT_VS BRW_3D(3, 0, 0x15) |
#define GEN6_3DSTATE_CONSTANT_GS BRW_3D(3, 0, 0x16) |
#define GEN6_3DSTATE_CONSTANT_PS BRW_3D(3, 0, 0x17) |
#define GEN6_3DSTATE_SAMPLE_MASK BRW_3D(3, 0, 0x18) |
#define GEN6_3DSTATE_MULTISAMPLE BRW_3D(3, 1, 0x0d) |
/* DW1 */ |
# define GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER (0 << 4) |
# define GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_UPPER_LEFT (1 << 4) |
# define GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_1 (0 << 1) |
# define GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_4 (2 << 1) |
# define GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_8 (3 << 1) |
/* on GEN7+ */ |
/* _3DSTATE_VERTEX_BUFFERS on GEN7*/ |
/* DW1 */ |
#define GEN7_VB0_ADDRESS_MODIFYENABLE (1 << 14) |
/* _3DPRIMITIVE on GEN7 */ |
/* DW1 */ |
# define GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL (0 << 8) |
# define GEN7_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM (1 << 8) |
/* 3DSTATE_WM on GEN7 */ |
/* DW1 */ |
# define GEN7_WM_STATISTICS_ENABLE (1 << 31) |
# define GEN7_WM_DEPTH_CLEAR (1 << 30) |
# define GEN7_WM_DISPATCH_ENABLE (1 << 29) |
# define GEN6_WM_DEPTH_RESOLVE (1 << 28) |
# define GEN7_WM_HIERARCHICAL_DEPTH_RESOLVE (1 << 27) |
# define GEN7_WM_KILL_ENABLE (1 << 25) |
# define GEN7_WM_PSCDEPTH_OFF (0 << 23) |
# define GEN7_WM_PSCDEPTH_ON (1 << 23) |
# define GEN7_WM_PSCDEPTH_ON_GE (2 << 23) |
# define GEN7_WM_PSCDEPTH_ON_LE (3 << 23) |
# define GEN7_WM_USES_SOURCE_DEPTH (1 << 20) |
# define GEN7_WM_USES_SOURCE_W (1 << 19) |
# define GEN7_WM_POSITION_ZW_PIXEL (0 << 17) |
# define GEN7_WM_POSITION_ZW_CENTROID (2 << 17) |
# define GEN7_WM_POSITION_ZW_SAMPLE (3 << 17) |
# define GEN7_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC (1 << 16) |
# define GEN7_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC (1 << 15) |
# define GEN7_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC (1 << 14) |
# define GEN7_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC (1 << 13) |
# define GEN7_WM_PERSPECTIVE_CENTROID_BARYCENTRIC (1 << 12) |
# define GEN7_WM_PERSPECTIVE_PIXEL_BARYCENTRIC (1 << 11) |
# define GEN7_WM_USES_INPUT_COVERAGE_MASK (1 << 10) |
# define GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5 (0 << 8) |
# define GEN7_WM_LINE_END_CAP_AA_WIDTH_1_0 (1 << 8) |
# define GEN7_WM_LINE_END_CAP_AA_WIDTH_2_0 (2 << 8) |
# define GEN7_WM_LINE_END_CAP_AA_WIDTH_4_0 (3 << 8) |
# define GEN7_WM_LINE_AA_WIDTH_0_5 (0 << 6) |
# define GEN7_WM_LINE_AA_WIDTH_1_0 (1 << 6) |
# define GEN7_WM_LINE_AA_WIDTH_2_0 (2 << 6) |
# define GEN7_WM_LINE_AA_WIDTH_4_0 (3 << 6) |
# define GEN7_WM_POLYGON_STIPPLE_ENABLE (1 << 4) |
# define GEN7_WM_LINE_STIPPLE_ENABLE (1 << 3) |
# define GEN7_WM_POINT_RASTRULE_UPPER_RIGHT (1 << 2) |
# define GEN7_WM_MSRAST_OFF_PIXEL (0 << 0) |
# define GEN7_WM_MSRAST_OFF_PATTERN (1 << 0) |
# define GEN7_WM_MSRAST_ON_PIXEL (2 << 0) |
# define GEN7_WM_MSRAST_ON_PATTERN (3 << 0) |
/* DW2 */ |
# define GEN7_WM_MSDISPMODE_PERPIXEL (1 << 31) |
#define GEN7_3DSTATE_CLEAR_PARAMS BRW_3D(3, 0, 0x04) |
#define GEN7_3DSTATE_DEPTH_BUFFER BRW_3D(3, 0, 0x05) |
#define GEN7_3DSTATE_CONSTANT_HS BRW_3D(3, 0, 0x19) |
#define GEN7_3DSTATE_CONSTANT_DS BRW_3D(3, 0, 0x1a) |
#define GEN7_3DSTATE_HS BRW_3D(3, 0, 0x1b) |
#define GEN7_3DSTATE_TE BRW_3D(3, 0, 0x1c) |
#define GEN7_3DSTATE_DS BRW_3D(3, 0, 0x1d) |
#define GEN7_3DSTATE_STREAMOUT BRW_3D(3, 0, 0x1e) |
#define GEN7_3DSTATE_SBE BRW_3D(3, 0, 0x1f) |
/* DW1 */ |
# define GEN7_SBE_SWIZZLE_CONTROL_MODE (1 << 28) |
# define GEN7_SBE_NUM_OUTPUTS_SHIFT 22 |
# define GEN7_SBE_SWIZZLE_ENABLE (1 << 21) |
# define GEN7_SBE_POINT_SPRITE_LOWERLEFT (1 << 20) |
# define GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT 11 |
# define GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT 4 |
#define GEN7_3DSTATE_PS BRW_3D(3, 0, 0x20) |
/* DW1: kernel pointer */ |
/* DW2 */ |
# define GEN7_PS_SPF_MODE (1 << 31) |
# define GEN7_PS_VECTOR_MASK_ENABLE (1 << 30) |
# define GEN7_PS_SAMPLER_COUNT_SHIFT 27 |
# define GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT 18 |
# define GEN7_PS_FLOATING_POINT_MODE_IEEE_754 (0 << 16) |
# define GEN7_PS_FLOATING_POINT_MODE_ALT (1 << 16) |
/* DW3: scratch space */ |
/* DW4 */ |
# define GEN7_PS_MAX_THREADS_SHIFT_IVB 24 |
# define GEN7_PS_MAX_THREADS_SHIFT_HSW 23 |
# define GEN7_PS_SAMPLE_MASK_SHIFT_HSW 12 |
# define GEN7_PS_PUSH_CONSTANT_ENABLE (1 << 11) |
# define GEN7_PS_ATTRIBUTE_ENABLE (1 << 10) |
# define GEN7_PS_OMASK_TO_RENDER_TARGET (1 << 9) |
# define GEN7_PS_DUAL_SOURCE_BLEND_ENABLE (1 << 7) |
# define GEN7_PS_POSOFFSET_NONE (0 << 3) |
# define GEN7_PS_POSOFFSET_CENTROID (2 << 3) |
# define GEN7_PS_POSOFFSET_SAMPLE (3 << 3) |
# define GEN7_PS_32_DISPATCH_ENABLE (1 << 2) |
# define GEN7_PS_16_DISPATCH_ENABLE (1 << 1) |
# define GEN7_PS_8_DISPATCH_ENABLE (1 << 0) |
/* DW5 */ |
# define GEN7_PS_DISPATCH_START_GRF_SHIFT_0 16 |
# define GEN7_PS_DISPATCH_START_GRF_SHIFT_1 8 |
# define GEN7_PS_DISPATCH_START_GRF_SHIFT_2 0 |
/* DW6: kernel 1 pointer */ |
/* DW7: kernel 2 pointer */ |
#define GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CL BRW_3D(3, 0, 0x21) |
#define GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC BRW_3D(3, 0, 0x23) |
#define GEN7_3DSTATE_BLEND_STATE_POINTERS BRW_3D(3, 0, 0x24) |
#define GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS BRW_3D(3, 0, 0x25) |
#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS BRW_3D(3, 0, 0x26) |
#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS BRW_3D(3, 0, 0x27) |
#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS BRW_3D(3, 0, 0x28) |
#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS BRW_3D(3, 0, 0x29) |
#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS BRW_3D(3, 0, 0x2a) |
#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_VS BRW_3D(3, 0, 0x2b) |
#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_GS BRW_3D(3, 0, 0x2e) |
#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS BRW_3D(3, 0, 0x2f) |
#define GEN7_3DSTATE_URB_VS BRW_3D(3, 0, 0x30) |
#define GEN7_3DSTATE_URB_HS BRW_3D(3, 0, 0x31) |
#define GEN7_3DSTATE_URB_DS BRW_3D(3, 0, 0x32) |
#define GEN7_3DSTATE_URB_GS BRW_3D(3, 0, 0x33) |
/* DW1 */ |
# define GEN7_URB_ENTRY_NUMBER_SHIFT 0 |
# define GEN7_URB_ENTRY_SIZE_SHIFT 16 |
# define GEN7_URB_STARTING_ADDRESS_SHIFT 25 |
#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS BRW_3D(3, 1, 0x12) |
#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS BRW_3D(3, 1, 0x16) |
/* DW1 */ |
# define GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT 16 |
#define PIPELINE_SELECT_3D 0 |
#define PIPELINE_SELECT_MEDIA 1 |
#define UF0_CS_REALLOC (1 << 13) |
#define UF0_VFE_REALLOC (1 << 12) |
#define UF0_SF_REALLOC (1 << 11) |
#define UF0_CLIP_REALLOC (1 << 10) |
#define UF0_GS_REALLOC (1 << 9) |
#define UF0_VS_REALLOC (1 << 8) |
#define UF1_CLIP_FENCE_SHIFT 20 |
#define UF1_GS_FENCE_SHIFT 10 |
#define UF1_VS_FENCE_SHIFT 0 |
#define UF2_CS_FENCE_SHIFT 20 |
#define UF2_VFE_FENCE_SHIFT 10 |
#define UF2_SF_FENCE_SHIFT 0 |
/* for BRW_STATE_BASE_ADDRESS */ |
#define BASE_ADDRESS_MODIFY (1 << 0) |
/* for BRW_3DSTATE_PIPELINED_POINTERS */ |
#define BRW_GS_DISABLE 0 |
#define BRW_GS_ENABLE 1 |
#define BRW_CLIP_DISABLE 0 |
#define BRW_CLIP_ENABLE 1 |
/* for BRW_PIPE_CONTROL */ |
#define BRW_PIPE_CONTROL_CS_STALL (1 << 20) |
#define BRW_PIPE_CONTROL_NOWRITE (0 << 14) |
#define BRW_PIPE_CONTROL_WRITE_QWORD (1 << 14) |
#define BRW_PIPE_CONTROL_WRITE_DEPTH (2 << 14) |
#define BRW_PIPE_CONTROL_WRITE_TIME (3 << 14) |
#define BRW_PIPE_CONTROL_DEPTH_STALL (1 << 13) |
#define BRW_PIPE_CONTROL_WC_FLUSH (1 << 12) |
#define BRW_PIPE_CONTROL_IS_FLUSH (1 << 11) |
#define BRW_PIPE_CONTROL_TC_FLUSH (1 << 10) |
#define BRW_PIPE_CONTROL_NOTIFY_ENABLE (1 << 8) |
#define BRW_PIPE_CONTROL_GLOBAL_GTT (1 << 2) |
#define BRW_PIPE_CONTROL_LOCAL_PGTT (0 << 2) |
#define BRW_PIPE_CONTROL_STALL_AT_SCOREBOARD (1 << 1) |
#define BRW_PIPE_CONTROL_DEPTH_CACHE_FLUSH (1 << 0) |
/* VERTEX_BUFFER_STATE Structure */ |
#define VB0_BUFFER_INDEX_SHIFT 27 |
#define GEN6_VB0_BUFFER_INDEX_SHIFT 26 |
#define VB0_VERTEXDATA (0 << 26) |
#define VB0_INSTANCEDATA (1 << 26) |
#define GEN6_VB0_VERTEXDATA (0 << 20) |
#define GEN6_VB0_INSTANCEDATA (1 << 20) |
#define VB0_BUFFER_PITCH_SHIFT 0 |
/* VERTEX_ELEMENT_STATE Structure */ |
#define VE0_VERTEX_BUFFER_INDEX_SHIFT 27 |
#define GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT 26 /* for GEN6 */ |
#define VE0_VALID (1 << 26) |
#define GEN6_VE0_VALID (1 << 25) /* for GEN6 */ |
#define VE0_FORMAT_SHIFT 16 |
#define VE0_OFFSET_SHIFT 0 |
#define VE1_VFCOMPONENT_0_SHIFT 28 |
#define VE1_VFCOMPONENT_1_SHIFT 24 |
#define VE1_VFCOMPONENT_2_SHIFT 20 |
#define VE1_VFCOMPONENT_3_SHIFT 16 |
#define VE1_DESTINATION_ELEMENT_OFFSET_SHIFT 0 |
/* 3DPRIMITIVE bits */ |
#define BRW_3DPRIMITIVE_VERTEX_SEQUENTIAL (0 << 15) |
#define BRW_3DPRIMITIVE_VERTEX_RANDOM (1 << 15) |
/* Primitive types are in brw_defines.h */ |
#define BRW_3DPRIMITIVE_TOPOLOGY_SHIFT 10 |
#define BRW_SVG_CTL 0x7400 |
#define BRW_SVG_CTL_GS_BA (0 << 8) |
#define BRW_SVG_CTL_SS_BA (1 << 8) |
#define BRW_SVG_CTL_IO_BA (2 << 8) |
#define BRW_SVG_CTL_GS_AUB (3 << 8) |
#define BRW_SVG_CTL_IO_AUB (4 << 8) |
#define BRW_SVG_CTL_SIP (5 << 8) |
#define BRW_SVG_RDATA 0x7404 |
#define BRW_SVG_WORK_CTL 0x7408 |
#define BRW_VF_CTL 0x7500 |
#define BRW_VF_CTL_SNAPSHOT_COMPLETE (1 << 31) |
#define BRW_VF_CTL_SNAPSHOT_MUX_SELECT_THREADID (0 << 8) |
#define BRW_VF_CTL_SNAPSHOT_MUX_SELECT_VF_DEBUG (1 << 8) |
#define BRW_VF_CTL_SNAPSHOT_TYPE_VERTEX_SEQUENCE (0 << 4) |
#define BRW_VF_CTL_SNAPSHOT_TYPE_VERTEX_INDEX (1 << 4) |
#define BRW_VF_CTL_SKIP_INITIAL_PRIMITIVES (1 << 3) |
#define BRW_VF_CTL_MAX_PRIMITIVES_LIMIT_ENABLE (1 << 2) |
#define BRW_VF_CTL_VERTEX_RANGE_LIMIT_ENABLE (1 << 1) |
#define BRW_VF_CTL_SNAPSHOT_ENABLE (1 << 0) |
#define BRW_VF_STRG_VAL 0x7504 |
#define BRW_VF_STR_VL_OVR 0x7508 |
#define BRW_VF_VC_OVR 0x750c |
#define BRW_VF_STR_PSKIP 0x7510 |
#define BRW_VF_MAX_PRIM 0x7514 |
#define BRW_VF_RDATA 0x7518 |
#define BRW_VS_CTL 0x7600 |
#define BRW_VS_CTL_SNAPSHOT_COMPLETE (1 << 31) |
#define BRW_VS_CTL_SNAPSHOT_MUX_VERTEX_0 (0 << 8) |
#define BRW_VS_CTL_SNAPSHOT_MUX_VERTEX_1 (1 << 8) |
#define BRW_VS_CTL_SNAPSHOT_MUX_VALID_COUNT (2 << 8) |
#define BRW_VS_CTL_SNAPSHOT_MUX_VS_KERNEL_POINTER (3 << 8) |
#define BRW_VS_CTL_SNAPSHOT_ALL_THREADS (1 << 2) |
#define BRW_VS_CTL_THREAD_SNAPSHOT_ENABLE (1 << 1) |
#define BRW_VS_CTL_SNAPSHOT_ENABLE (1 << 0) |
#define BRW_VS_STRG_VAL 0x7604 |
#define BRW_VS_RDATA 0x7608 |
#define BRW_SF_CTL 0x7b00 |
#define BRW_SF_CTL_SNAPSHOT_COMPLETE (1 << 31) |
#define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_0_FF_ID (0 << 8) |
#define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_0_REL_COUNT (1 << 8) |
#define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_1_FF_ID (2 << 8) |
#define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_1_REL_COUNT (3 << 8) |
#define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_2_FF_ID (4 << 8) |
#define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_2_REL_COUNT (5 << 8) |
#define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_COUNT (6 << 8) |
#define BRW_SF_CTL_SNAPSHOT_MUX_SF_KERNEL_POINTER (7 << 8) |
#define BRW_SF_CTL_MIN_MAX_PRIMITIVE_RANGE_ENABLE (1 << 4) |
#define BRW_SF_CTL_DEBUG_CLIP_RECTANGLE_ENABLE (1 << 3) |
#define BRW_SF_CTL_SNAPSHOT_ALL_THREADS (1 << 2) |
#define BRW_SF_CTL_THREAD_SNAPSHOT_ENABLE (1 << 1) |
#define BRW_SF_CTL_SNAPSHOT_ENABLE (1 << 0) |
#define BRW_SF_STRG_VAL 0x7b04 |
#define BRW_SF_RDATA 0x7b18 |
#define BRW_WIZ_CTL 0x7c00 |
#define BRW_WIZ_CTL_SNAPSHOT_COMPLETE (1 << 31) |
#define BRW_WIZ_CTL_SUBSPAN_INSTANCE_SHIFT 16 |
#define BRW_WIZ_CTL_SNAPSHOT_MUX_WIZ_KERNEL_POINTER (0 << 8) |
#define BRW_WIZ_CTL_SNAPSHOT_MUX_SUBSPAN_INSTANCE (1 << 8) |
#define BRW_WIZ_CTL_SNAPSHOT_MUX_PRIMITIVE_SEQUENCE (2 << 8) |
#define BRW_WIZ_CTL_SINGLE_SUBSPAN_DISPATCH (1 << 6) |
#define BRW_WIZ_CTL_IGNORE_COLOR_SCOREBOARD_STALLS (1 << 5) |
#define BRW_WIZ_CTL_ENABLE_SUBSPAN_INSTANCE_COMPARE (1 << 4) |
#define BRW_WIZ_CTL_USE_UPSTREAM_SNAPSHOT_FLAG (1 << 3) |
#define BRW_WIZ_CTL_SNAPSHOT_ALL_THREADS (1 << 2) |
#define BRW_WIZ_CTL_THREAD_SNAPSHOT_ENABLE (1 << 1) |
#define BRW_WIZ_CTL_SNAPSHOT_ENABLE (1 << 0) |
#define BRW_WIZ_STRG_VAL 0x7c04 |
#define BRW_WIZ_RDATA 0x7c18 |
#define BRW_TS_CTL 0x7e00 |
#define BRW_TS_CTL_SNAPSHOT_COMPLETE (1 << 31) |
#define BRW_TS_CTL_SNAPSHOT_MESSAGE_ERROR (0 << 8) |
#define BRW_TS_CTL_SNAPSHOT_INTERFACE_DESCRIPTOR (3 << 8) |
#define BRW_TS_CTL_SNAPSHOT_ALL_CHILD_THREADS (1 << 2) |
#define BRW_TS_CTL_SNAPSHOT_ALL_ROOT_THREADS (1 << 1) |
#define BRW_TS_CTL_SNAPSHOT_ENABLE (1 << 0) |
#define BRW_TS_STRG_VAL 0x7e04 |
#define BRW_TS_RDATA 0x7e08 |
#define BRW_TD_CTL 0x8000 |
#define BRW_TD_CTL_MUX_SHIFT 8 |
#define BRW_TD_CTL_EXTERNAL_HALT_R0_DEBUG_MATCH (1 << 7) |
#define BRW_TD_CTL_FORCE_EXTERNAL_HALT (1 << 6) |
#define BRW_TD_CTL_EXCEPTION_MASK_OVERRIDE (1 << 5) |
#define BRW_TD_CTL_FORCE_THREAD_BREAKPOINT_ENABLE (1 << 4) |
#define BRW_TD_CTL_BREAKPOINT_ENABLE (1 << 2) |
#define BRW_TD_CTL2 0x8004 |
#define BRW_TD_CTL2_ILLEGAL_OPCODE_EXCEPTION_OVERRIDE (1 << 28) |
#define BRW_TD_CTL2_MASKSTACK_EXCEPTION_OVERRIDE (1 << 26) |
#define BRW_TD_CTL2_SOFTWARE_EXCEPTION_OVERRIDE (1 << 25) |
#define BRW_TD_CTL2_ACTIVE_THREAD_LIMIT_SHIFT 16 |
#define BRW_TD_CTL2_ACTIVE_THREAD_LIMIT_ENABLE (1 << 8) |
#define BRW_TD_CTL2_THREAD_SPAWNER_EXECUTION_MASK_ENABLE (1 << 7) |
#define BRW_TD_CTL2_WIZ_EXECUTION_MASK_ENABLE (1 << 6) |
#define BRW_TD_CTL2_SF_EXECUTION_MASK_ENABLE (1 << 5) |
#define BRW_TD_CTL2_CLIPPER_EXECUTION_MASK_ENABLE (1 << 4) |
#define BRW_TD_CTL2_GS_EXECUTION_MASK_ENABLE (1 << 3) |
#define BRW_TD_CTL2_VS_EXECUTION_MASK_ENABLE (1 << 0) |
#define BRW_TD_VF_VS_EMSK 0x8008 |
#define BRW_TD_GS_EMSK 0x800c |
#define BRW_TD_CLIP_EMSK 0x8010 |
#define BRW_TD_SF_EMSK 0x8014 |
#define BRW_TD_WIZ_EMSK 0x8018 |
#define BRW_TD_0_6_EHTRG_VAL 0x801c |
#define BRW_TD_0_7_EHTRG_VAL 0x8020 |
#define BRW_TD_0_6_EHTRG_MSK 0x8024 |
#define BRW_TD_0_7_EHTRG_MSK 0x8028 |
#define BRW_TD_RDATA 0x802c |
#define BRW_TD_TS_EMSK 0x8030 |
#define BRW_EU_CTL 0x8800 |
#define BRW_EU_CTL_SELECT_SHIFT 16 |
#define BRW_EU_CTL_DATA_MUX_SHIFT 8 |
#define BRW_EU_ATT_0 0x8810 |
#define BRW_EU_ATT_1 0x8814 |
#define BRW_EU_ATT_DATA_0 0x8820 |
#define BRW_EU_ATT_DATA_1 0x8824 |
#define BRW_EU_ATT_CLR_0 0x8830 |
#define BRW_EU_ATT_CLR_1 0x8834 |
#define BRW_EU_RDATA 0x8840 |
/* End regs for broadwater */ |
/drivers/video/Intel-2D/uxa/i965_render.c |
---|
0,0 → 1,3049 |
/* |
* Copyright © 2006,2008 Intel Corporation |
* Copyright © 2007 Red Hat, Inc. |
* |
* Permission is hereby granted, free of charge, to any person obtaining a |
* copy of this software and associated documentation files (the "Software"), |
* to deal in the Software without restriction, including without limitation |
* the rights to use, copy, modify, merge, publish, distribute, sublicense, |
* and/or sell copies of the Software, and to permit persons to whom the |
* Software is furnished to do so, subject to the following conditions: |
* |
* The above copyright notice and this permission notice (including the next |
* paragraph) shall be included in all copies or substantial portions of the |
* Software. |
* |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
* SOFTWARE. |
* |
* Authors: |
* Wang Zhenyu <zhenyu.z.wang@intel.com> |
* Eric Anholt <eric@anholt.net> |
* Carl Worth <cworth@redhat.com> |
* Keith Packard <keithp@keithp.com> |
* |
*/ |
#ifdef HAVE_CONFIG_H |
#include "config.h" |
#endif |
#include <assert.h> |
#include <stdlib.h> |
#include <memory.h> |
#include <intel_bufmgr.h> |
//#include "xf86.h" |
#include "intel.h" |
#include "i830_reg.h" |
#include "i965_reg.h" |
/* bring in brw structs */ |
#include "brw_defines.h" |
#include "brw_structs.h" |
#define intel_debug_fallback printf |
// refer vol2, 3d rasterization 3.8.1 |
/* defined in brw_defines.h */ |
static const struct blendinfo { |
Bool dst_alpha; |
Bool src_alpha; |
uint32_t src_blend; |
uint32_t dst_blend; |
} i965_blend_op[] = { |
/* Clear */ |
{0, 0, BRW_BLENDFACTOR_ZERO, BRW_BLENDFACTOR_ZERO}, |
/* Src */ |
{0, 0, BRW_BLENDFACTOR_ONE, BRW_BLENDFACTOR_ZERO}, |
/* Dst */ |
{0, 0, BRW_BLENDFACTOR_ZERO, BRW_BLENDFACTOR_ONE}, |
/* Over */ |
{0, 1, BRW_BLENDFACTOR_ONE, BRW_BLENDFACTOR_INV_SRC_ALPHA}, |
/* OverReverse */ |
{1, 0, BRW_BLENDFACTOR_INV_DST_ALPHA, BRW_BLENDFACTOR_ONE}, |
/* In */ |
{1, 0, BRW_BLENDFACTOR_DST_ALPHA, BRW_BLENDFACTOR_ZERO}, |
/* InReverse */ |
{0, 1, BRW_BLENDFACTOR_ZERO, BRW_BLENDFACTOR_SRC_ALPHA}, |
/* Out */ |
{1, 0, BRW_BLENDFACTOR_INV_DST_ALPHA, BRW_BLENDFACTOR_ZERO}, |
/* OutReverse */ |
{0, 1, BRW_BLENDFACTOR_ZERO, BRW_BLENDFACTOR_INV_SRC_ALPHA}, |
/* Atop */ |
{1, 1, BRW_BLENDFACTOR_DST_ALPHA, BRW_BLENDFACTOR_INV_SRC_ALPHA}, |
/* AtopReverse */ |
{1, 1, BRW_BLENDFACTOR_INV_DST_ALPHA, BRW_BLENDFACTOR_SRC_ALPHA}, |
/* Xor */ |
{1, 1, BRW_BLENDFACTOR_INV_DST_ALPHA, BRW_BLENDFACTOR_INV_SRC_ALPHA}, |
/* Add */ |
{0, 0, BRW_BLENDFACTOR_ONE, BRW_BLENDFACTOR_ONE}, |
}; |
/** |
* Highest-valued BLENDFACTOR used in i965_blend_op. |
* |
* This leaves out BRW_BLENDFACTOR_INV_DST_COLOR, |
* BRW_BLENDFACTOR_INV_CONST_{COLOR,ALPHA}, |
* BRW_BLENDFACTOR_INV_SRC1_{COLOR,ALPHA} |
*/ |
#define BRW_BLENDFACTOR_COUNT (BRW_BLENDFACTOR_INV_DST_ALPHA + 1) |
/* FIXME: surface format defined in brw_defines.h, shared Sampling engine |
* 1.7.2 |
*/ |
static const struct formatinfo { |
int fmt; |
uint32_t card_fmt; |
} i965_tex_formats[] = { |
{PICT_a8, BRW_SURFACEFORMAT_A8_UNORM}, |
{PICT_a8r8g8b8, BRW_SURFACEFORMAT_B8G8R8A8_UNORM}, |
{PICT_x8r8g8b8, BRW_SURFACEFORMAT_B8G8R8X8_UNORM}, |
{PICT_a8b8g8r8, BRW_SURFACEFORMAT_R8G8B8A8_UNORM}, |
{PICT_x8b8g8r8, BRW_SURFACEFORMAT_R8G8B8X8_UNORM}, |
{PICT_r8g8b8, BRW_SURFACEFORMAT_R8G8B8_UNORM}, |
{PICT_r5g6b5, BRW_SURFACEFORMAT_B5G6R5_UNORM}, |
{PICT_a1r5g5b5, BRW_SURFACEFORMAT_B5G5R5A1_UNORM}, |
#if XORG_VERSION_CURRENT >= 10699900 |
{PICT_a2r10g10b10, BRW_SURFACEFORMAT_B10G10R10A2_UNORM}, |
{PICT_x2r10g10b10, BRW_SURFACEFORMAT_B10G10R10X2_UNORM}, |
{PICT_a2b10g10r10, BRW_SURFACEFORMAT_R10G10B10A2_UNORM}, |
{PICT_x2r10g10b10, BRW_SURFACEFORMAT_B10G10R10X2_UNORM}, |
#endif |
{PICT_a4r4g4b4, BRW_SURFACEFORMAT_B4G4R4A4_UNORM}, |
}; |
static void i965_get_blend_cntl(int op, PicturePtr mask, uint32_t dst_format, |
uint32_t * sblend, uint32_t * dblend) |
{ |
*sblend = i965_blend_op[op].src_blend; |
*dblend = i965_blend_op[op].dst_blend; |
/* If there's no dst alpha channel, adjust the blend op so that we'll treat |
* it as always 1. |
*/ |
if (PICT_FORMAT_A(dst_format) == 0 && i965_blend_op[op].dst_alpha) { |
if (*sblend == BRW_BLENDFACTOR_DST_ALPHA) |
*sblend = BRW_BLENDFACTOR_ONE; |
else if (*sblend == BRW_BLENDFACTOR_INV_DST_ALPHA) |
*sblend = BRW_BLENDFACTOR_ZERO; |
} |
/* If the source alpha is being used, then we should only be in a case where |
* the source blend factor is 0, and the source blend value is the mask |
* channels multiplied by the source picture's alpha. |
*/ |
if (mask && mask->componentAlpha && PICT_FORMAT_RGB(mask->format) |
&& i965_blend_op[op].src_alpha) { |
if (*dblend == BRW_BLENDFACTOR_SRC_ALPHA) { |
*dblend = BRW_BLENDFACTOR_SRC_COLOR; |
} else if (*dblend == BRW_BLENDFACTOR_INV_SRC_ALPHA) { |
*dblend = BRW_BLENDFACTOR_INV_SRC_COLOR; |
} |
} |
} |
static uint32_t i965_get_dest_format(PicturePtr dest_picture) |
{ |
switch (dest_picture->format) { |
case PICT_a8r8g8b8: |
case PICT_x8r8g8b8: |
return BRW_SURFACEFORMAT_B8G8R8A8_UNORM; |
case PICT_a8b8g8r8: |
case PICT_x8b8g8r8: |
return BRW_SURFACEFORMAT_R8G8B8A8_UNORM; |
#if XORG_VERSION_CURRENT >= 10699900 |
case PICT_a2r10g10b10: |
case PICT_x2r10g10b10: |
return BRW_SURFACEFORMAT_B10G10R10A2_UNORM; |
#endif |
case PICT_r5g6b5: |
return BRW_SURFACEFORMAT_B5G6R5_UNORM; |
case PICT_x1r5g5b5: |
case PICT_a1r5g5b5: |
return BRW_SURFACEFORMAT_B5G5R5A1_UNORM; |
case PICT_a8: |
return BRW_SURFACEFORMAT_A8_UNORM; |
case PICT_a4r4g4b4: |
case PICT_x4r4g4b4: |
return BRW_SURFACEFORMAT_B4G4R4A4_UNORM; |
default: |
return -1; |
} |
} |
Bool |
i965_check_composite(int op, |
PicturePtr source_picture, |
PicturePtr mask_picture, |
PicturePtr dest_picture, |
int width, int height) |
{ |
/* Check for unsupported compositing operations. */ |
if (op >= sizeof(i965_blend_op) / sizeof(i965_blend_op[0])) { |
intel_debug_fallback("Unsupported Composite op 0x%x\n", op); |
return FALSE; |
} |
if (mask_picture && mask_picture->componentAlpha && |
PICT_FORMAT_RGB(mask_picture->format)) { |
/* Check if it's component alpha that relies on a source alpha and on |
* the source value. We can only get one of those into the single |
* source value that we get to blend with. |
*/ |
if (i965_blend_op[op].src_alpha && |
(i965_blend_op[op].src_blend != BRW_BLENDFACTOR_ZERO)) { |
intel_debug_fallback("Component alpha not supported " |
"with source alpha and source " |
"value blending.\n"); |
return FALSE; |
} |
} |
if (i965_get_dest_format(dest_picture) == -1) { |
intel_debug_fallback("Usupported Color buffer format 0x%x\n", |
(int)dest_picture->format); |
return FALSE; |
} |
return TRUE; |
} |
Bool |
i965_check_composite_texture(ScreenPtr screen, PicturePtr picture) |
{ |
if (picture->repeatType > RepeatReflect) { |
intel_debug_fallback("extended repeat (%d) not supported\n", |
picture->repeatType); |
return FALSE; |
} |
if (picture->filter != PictFilterNearest && |
picture->filter != PictFilterBilinear) { |
intel_debug_fallback("Unsupported filter 0x%x\n", picture->filter); |
return FALSE; |
} |
if (picture->pDrawable) { |
int w, h, i; |
w = picture->pDrawable->width; |
h = picture->pDrawable->height; |
if ((w > 8192) || (h > 8192)) { |
intel_debug_fallback( "Picture w/h too large (%dx%d)\n",w, h); |
return FALSE; |
} |
for (i = 0; |
i < sizeof(i965_tex_formats) / sizeof(i965_tex_formats[0]); |
i++) { |
if (i965_tex_formats[i].fmt == picture->format) |
break; |
} |
if (i == sizeof(i965_tex_formats) / sizeof(i965_tex_formats[0])) |
{ |
intel_debug_fallback("Unsupported picture format " |
"0x%x\n", (int)picture->format); |
return FALSE; |
} |
return TRUE; |
} |
return FALSE; |
} |
#define BRW_GRF_BLOCKS(nreg) ((nreg + 15) / 16 - 1) |
/* Set up a default static partitioning of the URB, which is supposed to |
* allow anything we would want to do, at potentially lower performance. |
*/ |
#define URB_CS_ENTRY_SIZE 0 |
#define URB_CS_ENTRIES 0 |
#define URB_VS_ENTRY_SIZE 1 // each 512-bit row |
#define URB_VS_ENTRIES 8 // we needs at least 8 entries |
#define URB_GS_ENTRY_SIZE 0 |
#define URB_GS_ENTRIES 0 |
#define URB_CLIP_ENTRY_SIZE 0 |
#define URB_CLIP_ENTRIES 0 |
#define URB_SF_ENTRY_SIZE 2 |
#define URB_SF_ENTRIES 1 |
/* |
* this program computes dA/dx and dA/dy for the texture coordinates along |
* with the base texture coordinate. It was extracted from the Mesa driver |
*/ |
#define SF_KERNEL_NUM_GRF 16 |
#define SF_MAX_THREADS 2 |
static const uint32_t sf_kernel_static[][4] = { |
#include "exa_sf.g4b" |
}; |
static const uint32_t sf_kernel_mask_static[][4] = { |
#include "exa_sf_mask.g4b" |
}; |
/* ps kernels */ |
#define PS_KERNEL_NUM_GRF 32 |
#define PS_MAX_THREADS 48 |
static const uint32_t ps_kernel_nomask_affine_static[][4] = { |
#include "exa_wm_xy.g4b" |
#include "exa_wm_src_affine.g4b" |
#include "exa_wm_src_sample_argb.g4b" |
#include "exa_wm_write.g4b" |
}; |
static const uint32_t ps_kernel_nomask_projective_static[][4] = { |
#include "exa_wm_xy.g4b" |
#include "exa_wm_src_projective.g4b" |
#include "exa_wm_src_sample_argb.g4b" |
#include "exa_wm_write.g4b" |
}; |
static const uint32_t ps_kernel_maskca_affine_static[][4] = { |
#include "exa_wm_xy.g4b" |
#include "exa_wm_src_affine.g4b" |
#include "exa_wm_src_sample_argb.g4b" |
#include "exa_wm_mask_affine.g4b" |
#include "exa_wm_mask_sample_argb.g4b" |
#include "exa_wm_ca.g4b" |
#include "exa_wm_write.g4b" |
}; |
static const uint32_t ps_kernel_maskca_projective_static[][4] = { |
#include "exa_wm_xy.g4b" |
#include "exa_wm_src_projective.g4b" |
#include "exa_wm_src_sample_argb.g4b" |
#include "exa_wm_mask_projective.g4b" |
#include "exa_wm_mask_sample_argb.g4b" |
#include "exa_wm_ca.g4b" |
#include "exa_wm_write.g4b" |
}; |
static const uint32_t ps_kernel_maskca_srcalpha_affine_static[][4] = { |
#include "exa_wm_xy.g4b" |
#include "exa_wm_src_affine.g4b" |
#include "exa_wm_src_sample_a.g4b" |
#include "exa_wm_mask_affine.g4b" |
#include "exa_wm_mask_sample_argb.g4b" |
#include "exa_wm_ca_srcalpha.g4b" |
#include "exa_wm_write.g4b" |
}; |
static const uint32_t ps_kernel_maskca_srcalpha_projective_static[][4] = { |
#include "exa_wm_xy.g4b" |
#include "exa_wm_src_projective.g4b" |
#include "exa_wm_src_sample_a.g4b" |
#include "exa_wm_mask_projective.g4b" |
#include "exa_wm_mask_sample_argb.g4b" |
#include "exa_wm_ca_srcalpha.g4b" |
#include "exa_wm_write.g4b" |
}; |
static const uint32_t ps_kernel_masknoca_affine_static[][4] = { |
#include "exa_wm_xy.g4b" |
#include "exa_wm_src_affine.g4b" |
#include "exa_wm_src_sample_argb.g4b" |
#include "exa_wm_mask_affine.g4b" |
#include "exa_wm_mask_sample_a.g4b" |
#include "exa_wm_noca.g4b" |
#include "exa_wm_write.g4b" |
}; |
static const uint32_t ps_kernel_masknoca_projective_static[][4] = { |
#include "exa_wm_xy.g4b" |
#include "exa_wm_src_projective.g4b" |
#include "exa_wm_src_sample_argb.g4b" |
#include "exa_wm_mask_projective.g4b" |
#include "exa_wm_mask_sample_a.g4b" |
#include "exa_wm_noca.g4b" |
#include "exa_wm_write.g4b" |
}; |
/* new programs for Ironlake */ |
static const uint32_t sf_kernel_static_gen5[][4] = { |
#include "exa_sf.g4b.gen5" |
}; |
static const uint32_t sf_kernel_mask_static_gen5[][4] = { |
#include "exa_sf_mask.g4b.gen5" |
}; |
static const uint32_t ps_kernel_nomask_affine_static_gen5[][4] = { |
#include "exa_wm_xy.g4b.gen5" |
#include "exa_wm_src_affine.g4b.gen5" |
#include "exa_wm_src_sample_argb.g4b.gen5" |
#include "exa_wm_write.g4b.gen5" |
}; |
static const uint32_t ps_kernel_nomask_projective_static_gen5[][4] = { |
#include "exa_wm_xy.g4b.gen5" |
#include "exa_wm_src_projective.g4b.gen5" |
#include "exa_wm_src_sample_argb.g4b.gen5" |
#include "exa_wm_write.g4b.gen5" |
}; |
static const uint32_t ps_kernel_maskca_affine_static_gen5[][4] = { |
#include "exa_wm_xy.g4b.gen5" |
#include "exa_wm_src_affine.g4b.gen5" |
#include "exa_wm_src_sample_argb.g4b.gen5" |
#include "exa_wm_mask_affine.g4b.gen5" |
#include "exa_wm_mask_sample_argb.g4b.gen5" |
#include "exa_wm_ca.g4b.gen5" |
#include "exa_wm_write.g4b.gen5" |
}; |
static const uint32_t ps_kernel_maskca_projective_static_gen5[][4] = { |
#include "exa_wm_xy.g4b.gen5" |
#include "exa_wm_src_projective.g4b.gen5" |
#include "exa_wm_src_sample_argb.g4b.gen5" |
#include "exa_wm_mask_projective.g4b.gen5" |
#include "exa_wm_mask_sample_argb.g4b.gen5" |
#include "exa_wm_ca.g4b.gen5" |
#include "exa_wm_write.g4b.gen5" |
}; |
static const uint32_t ps_kernel_maskca_srcalpha_affine_static_gen5[][4] = { |
#include "exa_wm_xy.g4b.gen5" |
#include "exa_wm_src_affine.g4b.gen5" |
#include "exa_wm_src_sample_a.g4b.gen5" |
#include "exa_wm_mask_affine.g4b.gen5" |
#include "exa_wm_mask_sample_argb.g4b.gen5" |
#include "exa_wm_ca_srcalpha.g4b.gen5" |
#include "exa_wm_write.g4b.gen5" |
}; |
static const uint32_t ps_kernel_maskca_srcalpha_projective_static_gen5[][4] = { |
#include "exa_wm_xy.g4b.gen5" |
#include "exa_wm_src_projective.g4b.gen5" |
#include "exa_wm_src_sample_a.g4b.gen5" |
#include "exa_wm_mask_projective.g4b.gen5" |
#include "exa_wm_mask_sample_argb.g4b.gen5" |
#include "exa_wm_ca_srcalpha.g4b.gen5" |
#include "exa_wm_write.g4b.gen5" |
}; |
static const uint32_t ps_kernel_masknoca_affine_static_gen5[][4] = { |
#include "exa_wm_xy.g4b.gen5" |
#include "exa_wm_src_affine.g4b.gen5" |
#include "exa_wm_src_sample_argb.g4b.gen5" |
#include "exa_wm_mask_affine.g4b.gen5" |
#include "exa_wm_mask_sample_a.g4b.gen5" |
#include "exa_wm_noca.g4b.gen5" |
#include "exa_wm_write.g4b.gen5" |
}; |
static const uint32_t ps_kernel_masknoca_projective_static_gen5[][4] = { |
#include "exa_wm_xy.g4b.gen5" |
#include "exa_wm_src_projective.g4b.gen5" |
#include "exa_wm_src_sample_argb.g4b.gen5" |
#include "exa_wm_mask_projective.g4b.gen5" |
#include "exa_wm_mask_sample_a.g4b.gen5" |
#include "exa_wm_noca.g4b.gen5" |
#include "exa_wm_write.g4b.gen5" |
}; |
/* programs for GEN6 */ |
static const uint32_t ps_kernel_nomask_affine_static_gen6[][4] = { |
#include "exa_wm_src_affine.g6b" |
#include "exa_wm_src_sample_argb.g6b" |
#include "exa_wm_write.g6b" |
}; |
static const uint32_t ps_kernel_nomask_projective_static_gen6[][4] = { |
#include "exa_wm_src_projective.g6b" |
#include "exa_wm_src_sample_argb.g6b" |
#include "exa_wm_write.g6b" |
}; |
static const uint32_t ps_kernel_maskca_affine_static_gen6[][4] = { |
#include "exa_wm_src_affine.g6b" |
#include "exa_wm_src_sample_argb.g6b" |
#include "exa_wm_mask_affine.g6b" |
#include "exa_wm_mask_sample_argb.g6b" |
#include "exa_wm_ca.g6b" |
#include "exa_wm_write.g6b" |
}; |
static const uint32_t ps_kernel_maskca_projective_static_gen6[][4] = { |
#include "exa_wm_src_projective.g6b" |
#include "exa_wm_src_sample_argb.g6b" |
#include "exa_wm_mask_projective.g6b" |
#include "exa_wm_mask_sample_argb.g6b" |
#include "exa_wm_ca.g4b.gen5" |
#include "exa_wm_write.g6b" |
}; |
static const uint32_t ps_kernel_maskca_srcalpha_affine_static_gen6[][4] = { |
#include "exa_wm_src_affine.g6b" |
#include "exa_wm_src_sample_a.g6b" |
#include "exa_wm_mask_affine.g6b" |
#include "exa_wm_mask_sample_argb.g6b" |
#include "exa_wm_ca_srcalpha.g6b" |
#include "exa_wm_write.g6b" |
}; |
static const uint32_t ps_kernel_maskca_srcalpha_projective_static_gen6[][4] = { |
#include "exa_wm_src_projective.g6b" |
#include "exa_wm_src_sample_a.g6b" |
#include "exa_wm_mask_projective.g6b" |
#include "exa_wm_mask_sample_argb.g6b" |
#include "exa_wm_ca_srcalpha.g6b" |
#include "exa_wm_write.g6b" |
}; |
static const uint32_t ps_kernel_masknoca_affine_static_gen6[][4] = { |
#include "exa_wm_src_affine.g6b" |
#include "exa_wm_src_sample_argb.g6b" |
#include "exa_wm_mask_affine.g6b" |
#include "exa_wm_mask_sample_a.g6b" |
#include "exa_wm_noca.g6b" |
#include "exa_wm_write.g6b" |
}; |
static const uint32_t ps_kernel_masknoca_projective_static_gen6[][4] = { |
#include "exa_wm_src_projective.g6b" |
#include "exa_wm_src_sample_argb.g6b" |
#include "exa_wm_mask_projective.g6b" |
#include "exa_wm_mask_sample_a.g6b" |
#include "exa_wm_noca.g6b" |
#include "exa_wm_write.g6b" |
}; |
/* programs for GEN7 */ |
static const uint32_t ps_kernel_nomask_affine_static_gen7[][4] = { |
#include "exa_wm_src_affine.g7b" |
#include "exa_wm_src_sample_argb.g7b" |
#include "exa_wm_write.g7b" |
}; |
static const uint32_t ps_kernel_nomask_projective_static_gen7[][4] = { |
#include "exa_wm_src_projective.g7b" |
#include "exa_wm_src_sample_argb.g7b" |
#include "exa_wm_write.g7b" |
}; |
static const uint32_t ps_kernel_maskca_affine_static_gen7[][4] = { |
#include "exa_wm_src_affine.g7b" |
#include "exa_wm_src_sample_argb.g7b" |
#include "exa_wm_mask_affine.g7b" |
#include "exa_wm_mask_sample_argb.g7b" |
#include "exa_wm_ca.g6b" |
#include "exa_wm_write.g7b" |
}; |
static const uint32_t ps_kernel_maskca_projective_static_gen7[][4] = { |
#include "exa_wm_src_projective.g7b" |
#include "exa_wm_src_sample_argb.g7b" |
#include "exa_wm_mask_projective.g7b" |
#include "exa_wm_mask_sample_argb.g7b" |
#include "exa_wm_ca.g4b.gen5" |
#include "exa_wm_write.g7b" |
}; |
static const uint32_t ps_kernel_maskca_srcalpha_affine_static_gen7[][4] = { |
#include "exa_wm_src_affine.g7b" |
#include "exa_wm_src_sample_a.g7b" |
#include "exa_wm_mask_affine.g7b" |
#include "exa_wm_mask_sample_argb.g7b" |
#include "exa_wm_ca_srcalpha.g6b" |
#include "exa_wm_write.g7b" |
}; |
static const uint32_t ps_kernel_maskca_srcalpha_projective_static_gen7[][4] = { |
#include "exa_wm_src_projective.g7b" |
#include "exa_wm_src_sample_a.g7b" |
#include "exa_wm_mask_projective.g7b" |
#include "exa_wm_mask_sample_argb.g7b" |
#include "exa_wm_ca_srcalpha.g6b" |
#include "exa_wm_write.g7b" |
}; |
static const uint32_t ps_kernel_masknoca_affine_static_gen7[][4] = { |
#include "exa_wm_src_affine.g7b" |
#include "exa_wm_src_sample_argb.g7b" |
#include "exa_wm_mask_affine.g7b" |
#include "exa_wm_mask_sample_a.g7b" |
#include "exa_wm_noca.g6b" |
#include "exa_wm_write.g7b" |
}; |
static const uint32_t ps_kernel_masknoca_projective_static_gen7[][4] = { |
#include "exa_wm_src_projective.g7b" |
#include "exa_wm_src_sample_argb.g7b" |
#include "exa_wm_mask_projective.g7b" |
#include "exa_wm_mask_sample_a.g7b" |
#include "exa_wm_noca.g6b" |
#include "exa_wm_write.g7b" |
}; |
typedef enum { |
SS_INVALID_FILTER = -1, |
SS_FILTER_NEAREST, |
SS_FILTER_BILINEAR, |
FILTER_COUNT, |
} sampler_state_filter_t; |
typedef enum { |
SS_INVALID_EXTEND = -1, |
SS_EXTEND_NONE, |
SS_EXTEND_REPEAT, |
SS_EXTEND_PAD, |
SS_EXTEND_REFLECT, |
EXTEND_COUNT, |
} sampler_state_extend_t; |
typedef enum { |
WM_KERNEL_NOMASK_AFFINE, |
WM_KERNEL_NOMASK_PROJECTIVE, |
WM_KERNEL_MASKCA_AFFINE, |
WM_KERNEL_MASKCA_PROJECTIVE, |
WM_KERNEL_MASKCA_SRCALPHA_AFFINE, |
WM_KERNEL_MASKCA_SRCALPHA_PROJECTIVE, |
WM_KERNEL_MASKNOCA_AFFINE, |
WM_KERNEL_MASKNOCA_PROJECTIVE, |
KERNEL_COUNT |
} wm_kernel_t; |
#define KERNEL(kernel_enum, kernel, masked) \ |
[kernel_enum] = {&kernel, sizeof(kernel), masked} |
struct wm_kernel_info { |
const void *data; |
unsigned int size; |
Bool has_mask; |
}; |
static const struct wm_kernel_info wm_kernels_gen4[] = { |
KERNEL(WM_KERNEL_NOMASK_AFFINE, |
ps_kernel_nomask_affine_static, FALSE), |
KERNEL(WM_KERNEL_NOMASK_PROJECTIVE, |
ps_kernel_nomask_projective_static, FALSE), |
KERNEL(WM_KERNEL_MASKCA_AFFINE, |
ps_kernel_maskca_affine_static, TRUE), |
KERNEL(WM_KERNEL_MASKCA_PROJECTIVE, |
ps_kernel_maskca_projective_static, TRUE), |
KERNEL(WM_KERNEL_MASKCA_SRCALPHA_AFFINE, |
ps_kernel_maskca_srcalpha_affine_static, TRUE), |
KERNEL(WM_KERNEL_MASKCA_SRCALPHA_PROJECTIVE, |
ps_kernel_maskca_srcalpha_projective_static, TRUE), |
KERNEL(WM_KERNEL_MASKNOCA_AFFINE, |
ps_kernel_masknoca_affine_static, TRUE), |
KERNEL(WM_KERNEL_MASKNOCA_PROJECTIVE, |
ps_kernel_masknoca_projective_static, TRUE), |
}; |
static const struct wm_kernel_info wm_kernels_gen5[] = { |
KERNEL(WM_KERNEL_NOMASK_AFFINE, |
ps_kernel_nomask_affine_static_gen5, FALSE), |
KERNEL(WM_KERNEL_NOMASK_PROJECTIVE, |
ps_kernel_nomask_projective_static_gen5, FALSE), |
KERNEL(WM_KERNEL_MASKCA_AFFINE, |
ps_kernel_maskca_affine_static_gen5, TRUE), |
KERNEL(WM_KERNEL_MASKCA_PROJECTIVE, |
ps_kernel_maskca_projective_static_gen5, TRUE), |
KERNEL(WM_KERNEL_MASKCA_SRCALPHA_AFFINE, |
ps_kernel_maskca_srcalpha_affine_static_gen5, TRUE), |
KERNEL(WM_KERNEL_MASKCA_SRCALPHA_PROJECTIVE, |
ps_kernel_maskca_srcalpha_projective_static_gen5, TRUE), |
KERNEL(WM_KERNEL_MASKNOCA_AFFINE, |
ps_kernel_masknoca_affine_static_gen5, TRUE), |
KERNEL(WM_KERNEL_MASKNOCA_PROJECTIVE, |
ps_kernel_masknoca_projective_static_gen5, TRUE), |
}; |
static const struct wm_kernel_info wm_kernels_gen6[] = { |
KERNEL(WM_KERNEL_NOMASK_AFFINE, |
ps_kernel_nomask_affine_static_gen6, FALSE), |
KERNEL(WM_KERNEL_NOMASK_PROJECTIVE, |
ps_kernel_nomask_projective_static_gen6, FALSE), |
KERNEL(WM_KERNEL_MASKCA_AFFINE, |
ps_kernel_maskca_affine_static_gen6, TRUE), |
KERNEL(WM_KERNEL_MASKCA_PROJECTIVE, |
ps_kernel_maskca_projective_static_gen6, TRUE), |
KERNEL(WM_KERNEL_MASKCA_SRCALPHA_AFFINE, |
ps_kernel_maskca_srcalpha_affine_static_gen6, TRUE), |
KERNEL(WM_KERNEL_MASKCA_SRCALPHA_PROJECTIVE, |
ps_kernel_maskca_srcalpha_projective_static_gen6, TRUE), |
KERNEL(WM_KERNEL_MASKNOCA_AFFINE, |
ps_kernel_masknoca_affine_static_gen6, TRUE), |
KERNEL(WM_KERNEL_MASKNOCA_PROJECTIVE, |
ps_kernel_masknoca_projective_static_gen6, TRUE), |
}; |
static const struct wm_kernel_info wm_kernels_gen7[] = { |
KERNEL(WM_KERNEL_NOMASK_AFFINE, |
ps_kernel_nomask_affine_static_gen7, FALSE), |
KERNEL(WM_KERNEL_NOMASK_PROJECTIVE, |
ps_kernel_nomask_projective_static_gen7, FALSE), |
KERNEL(WM_KERNEL_MASKCA_AFFINE, |
ps_kernel_maskca_affine_static_gen7, TRUE), |
KERNEL(WM_KERNEL_MASKCA_PROJECTIVE, |
ps_kernel_maskca_projective_static_gen7, TRUE), |
KERNEL(WM_KERNEL_MASKCA_SRCALPHA_AFFINE, |
ps_kernel_maskca_srcalpha_affine_static_gen7, TRUE), |
KERNEL(WM_KERNEL_MASKCA_SRCALPHA_PROJECTIVE, |
ps_kernel_maskca_srcalpha_projective_static_gen7, TRUE), |
KERNEL(WM_KERNEL_MASKNOCA_AFFINE, |
ps_kernel_masknoca_affine_static_gen7, TRUE), |
KERNEL(WM_KERNEL_MASKNOCA_PROJECTIVE, |
ps_kernel_masknoca_projective_static_gen7, TRUE), |
}; |
#undef KERNEL |
typedef struct _brw_cc_unit_state_padded { |
struct brw_cc_unit_state state; |
char pad[64 - sizeof(struct brw_cc_unit_state)]; |
} brw_cc_unit_state_padded; |
#ifndef MAX |
#define MAX(a, b) ((a) > (b) ? (a) : (b)) |
#endif |
#define SURFACE_STATE_PADDED_SIZE ALIGN(MAX(sizeof(struct brw_surface_state), sizeof(struct gen7_surface_state)), 32) |
struct gen4_cc_unit_state { |
/* Index by [src_blend][dst_blend] */ |
brw_cc_unit_state_padded cc_state[BRW_BLENDFACTOR_COUNT][BRW_BLENDFACTOR_COUNT]; |
}; |
typedef struct gen4_composite_op { |
int op; |
sampler_state_filter_t src_filter; |
sampler_state_filter_t mask_filter; |
sampler_state_extend_t src_extend; |
sampler_state_extend_t mask_extend; |
Bool is_affine; |
wm_kernel_t wm_kernel; |
int vertex_id; |
} gen4_composite_op; |
/** Private data for gen4 render accel implementation. */ |
struct gen4_render_state { |
drm_intel_bo *vs_state_bo; |
drm_intel_bo *sf_state_bo; |
drm_intel_bo *sf_mask_state_bo; |
drm_intel_bo *cc_state_bo; |
drm_intel_bo *wm_state_bo[KERNEL_COUNT] |
[FILTER_COUNT] [EXTEND_COUNT] |
[FILTER_COUNT] [EXTEND_COUNT]; |
drm_intel_bo *wm_kernel_bo[KERNEL_COUNT]; |
drm_intel_bo *cc_vp_bo; |
drm_intel_bo *gen6_blend_bo; |
drm_intel_bo *gen6_depth_stencil_bo; |
drm_intel_bo *ps_sampler_state_bo[FILTER_COUNT] |
[EXTEND_COUNT] |
[FILTER_COUNT] |
[EXTEND_COUNT]; |
gen4_composite_op composite_op; |
}; |
static void gen6_emit_composite_state(struct intel_screen_private *intel); |
static void gen6_render_state_init(); |
/** |
* Sets up the SF state pointing at an SF kernel. |
* |
* The SF kernel does coord interp: for each attribute, |
* calculate dA/dx and dA/dy. Hand these interpolation coefficients |
* back to SF which then hands pixels off to WM. |
*/ |
static drm_intel_bo *gen4_create_sf_state(intel_screen_private *intel, |
drm_intel_bo * kernel_bo) |
{ |
struct brw_sf_unit_state *sf_state; |
drm_intel_bo *sf_state_bo; |
int ret; |
sf_state_bo = drm_intel_bo_alloc(intel->bufmgr, "gen4 SF state", |
sizeof(*sf_state), 4096); |
assert(sf_state_bo); |
ret = drm_intel_bo_map(sf_state_bo, TRUE); |
assert(ret == 0); |
sf_state = memset(sf_state_bo->virtual, 0, sizeof(*sf_state)); |
sf_state->thread0.grf_reg_count = BRW_GRF_BLOCKS(SF_KERNEL_NUM_GRF); |
sf_state->thread0.kernel_start_pointer = |
intel_emit_reloc(sf_state_bo, |
offsetof(struct brw_sf_unit_state, thread0), |
kernel_bo, sf_state->thread0.grf_reg_count << 1, |
I915_GEM_DOMAIN_INSTRUCTION, 0) >> 6; |
sf_state->sf1.single_program_flow = 1; |
sf_state->sf1.binding_table_entry_count = 0; |
sf_state->sf1.thread_priority = 0; |
sf_state->sf1.floating_point_mode = 0; /* Mesa does this */ |
sf_state->sf1.illegal_op_exception_enable = 1; |
sf_state->sf1.mask_stack_exception_enable = 1; |
sf_state->sf1.sw_exception_enable = 1; |
sf_state->thread2.per_thread_scratch_space = 0; |
/* scratch space is not used in our kernel */ |
sf_state->thread2.scratch_space_base_pointer = 0; |
sf_state->thread3.const_urb_entry_read_length = 0; /* no const URBs */ |
sf_state->thread3.const_urb_entry_read_offset = 0; /* no const URBs */ |
sf_state->thread3.urb_entry_read_length = 1; /* 1 URB per vertex */ |
/* don't smash vertex header, read start from dw8 */ |
sf_state->thread3.urb_entry_read_offset = 1; |
sf_state->thread3.dispatch_grf_start_reg = 3; |
sf_state->thread4.max_threads = SF_MAX_THREADS - 1; |
sf_state->thread4.urb_entry_allocation_size = URB_SF_ENTRY_SIZE - 1; |
sf_state->thread4.nr_urb_entries = URB_SF_ENTRIES; |
sf_state->sf5.viewport_transform = FALSE; /* skip viewport */ |
sf_state->sf6.cull_mode = BRW_CULLMODE_NONE; |
sf_state->sf6.scissor = 0; |
sf_state->sf7.trifan_pv = 2; |
sf_state->sf6.dest_org_vbias = 0x8; |
sf_state->sf6.dest_org_hbias = 0x8; |
drm_intel_bo_unmap(sf_state_bo); |
return sf_state_bo; |
(void)ret; |
} |
static drm_intel_bo *sampler_border_color_create(intel_screen_private *intel) |
{ |
struct brw_sampler_legacy_border_color sampler_border_color; |
/* Set up the sampler border color (always transparent black) */ |
memset(&sampler_border_color, 0, sizeof(sampler_border_color)); |
sampler_border_color.color[0] = 0; /* R */ |
sampler_border_color.color[1] = 0; /* G */ |
sampler_border_color.color[2] = 0; /* B */ |
sampler_border_color.color[3] = 0; /* A */ |
return intel_bo_alloc_for_data(intel, |
&sampler_border_color, |
sizeof(sampler_border_color), |
"gen4 render sampler border color"); |
} |
static void |
gen4_sampler_state_init(drm_intel_bo * sampler_state_bo, |
struct brw_sampler_state *sampler_state, |
sampler_state_filter_t filter, |
sampler_state_extend_t extend, |
drm_intel_bo * border_color_bo) |
{ |
uint32_t sampler_state_offset; |
sampler_state_offset = (char *)sampler_state - |
(char *)sampler_state_bo->virtual; |
/* PS kernel use this sampler */ |
memset(sampler_state, 0, sizeof(*sampler_state)); |
sampler_state->ss0.lod_preclamp = 1; /* GL mode */ |
/* We use the legacy mode to get the semantics specified by |
* the Render extension. */ |
sampler_state->ss0.border_color_mode = BRW_BORDER_COLOR_MODE_LEGACY; |
switch (filter) { |
default: |
case SS_FILTER_NEAREST: |
sampler_state->ss0.min_filter = BRW_MAPFILTER_NEAREST; |
sampler_state->ss0.mag_filter = BRW_MAPFILTER_NEAREST; |
break; |
case SS_FILTER_BILINEAR: |
sampler_state->ss0.min_filter = BRW_MAPFILTER_LINEAR; |
sampler_state->ss0.mag_filter = BRW_MAPFILTER_LINEAR; |
break; |
} |
switch (extend) { |
default: |
case SS_EXTEND_NONE: |
sampler_state->ss1.r_wrap_mode = BRW_TEXCOORDMODE_CLAMP_BORDER; |
sampler_state->ss1.s_wrap_mode = BRW_TEXCOORDMODE_CLAMP_BORDER; |
sampler_state->ss1.t_wrap_mode = BRW_TEXCOORDMODE_CLAMP_BORDER; |
break; |
case SS_EXTEND_REPEAT: |
sampler_state->ss1.r_wrap_mode = BRW_TEXCOORDMODE_WRAP; |
sampler_state->ss1.s_wrap_mode = BRW_TEXCOORDMODE_WRAP; |
sampler_state->ss1.t_wrap_mode = BRW_TEXCOORDMODE_WRAP; |
break; |
case SS_EXTEND_PAD: |
sampler_state->ss1.r_wrap_mode = BRW_TEXCOORDMODE_CLAMP; |
sampler_state->ss1.s_wrap_mode = BRW_TEXCOORDMODE_CLAMP; |
sampler_state->ss1.t_wrap_mode = BRW_TEXCOORDMODE_CLAMP; |
break; |
case SS_EXTEND_REFLECT: |
sampler_state->ss1.r_wrap_mode = BRW_TEXCOORDMODE_MIRROR; |
sampler_state->ss1.s_wrap_mode = BRW_TEXCOORDMODE_MIRROR; |
sampler_state->ss1.t_wrap_mode = BRW_TEXCOORDMODE_MIRROR; |
break; |
} |
sampler_state->ss2.border_color_pointer = |
intel_emit_reloc(sampler_state_bo, sampler_state_offset + |
offsetof(struct brw_sampler_state, ss2), |
border_color_bo, 0, |
I915_GEM_DOMAIN_SAMPLER, 0) >> 5; |
sampler_state->ss3.chroma_key_enable = 0; /* disable chromakey */ |
} |
static void |
gen7_sampler_state_init(drm_intel_bo * sampler_state_bo, |
struct gen7_sampler_state *sampler_state, |
sampler_state_filter_t filter, |
sampler_state_extend_t extend, |
drm_intel_bo * border_color_bo) |
{ |
uint32_t sampler_state_offset; |
sampler_state_offset = (char *)sampler_state - |
(char *)sampler_state_bo->virtual; |
/* PS kernel use this sampler */ |
memset(sampler_state, 0, sizeof(*sampler_state)); |
sampler_state->ss0.lod_preclamp = 1; /* GL mode */ |
/* We use the legacy mode to get the semantics specified by |
* the Render extension. */ |
sampler_state->ss0.default_color_mode = BRW_BORDER_COLOR_MODE_LEGACY; |
switch (filter) { |
default: |
case SS_FILTER_NEAREST: |
sampler_state->ss0.min_filter = BRW_MAPFILTER_NEAREST; |
sampler_state->ss0.mag_filter = BRW_MAPFILTER_NEAREST; |
break; |
case SS_FILTER_BILINEAR: |
sampler_state->ss0.min_filter = BRW_MAPFILTER_LINEAR; |
sampler_state->ss0.mag_filter = BRW_MAPFILTER_LINEAR; |
break; |
} |
switch (extend) { |
default: |
case SS_EXTEND_NONE: |
sampler_state->ss3.r_wrap_mode = BRW_TEXCOORDMODE_CLAMP_BORDER; |
sampler_state->ss3.s_wrap_mode = BRW_TEXCOORDMODE_CLAMP_BORDER; |
sampler_state->ss3.t_wrap_mode = BRW_TEXCOORDMODE_CLAMP_BORDER; |
break; |
case SS_EXTEND_REPEAT: |
sampler_state->ss3.r_wrap_mode = BRW_TEXCOORDMODE_WRAP; |
sampler_state->ss3.s_wrap_mode = BRW_TEXCOORDMODE_WRAP; |
sampler_state->ss3.t_wrap_mode = BRW_TEXCOORDMODE_WRAP; |
break; |
case SS_EXTEND_PAD: |
sampler_state->ss3.r_wrap_mode = BRW_TEXCOORDMODE_CLAMP; |
sampler_state->ss3.s_wrap_mode = BRW_TEXCOORDMODE_CLAMP; |
sampler_state->ss3.t_wrap_mode = BRW_TEXCOORDMODE_CLAMP; |
break; |
case SS_EXTEND_REFLECT: |
sampler_state->ss3.r_wrap_mode = BRW_TEXCOORDMODE_MIRROR; |
sampler_state->ss3.s_wrap_mode = BRW_TEXCOORDMODE_MIRROR; |
sampler_state->ss3.t_wrap_mode = BRW_TEXCOORDMODE_MIRROR; |
break; |
} |
sampler_state->ss2.default_color_pointer = |
intel_emit_reloc(sampler_state_bo, sampler_state_offset + |
offsetof(struct gen7_sampler_state, ss2), |
border_color_bo, 0, |
I915_GEM_DOMAIN_SAMPLER, 0) >> 5; |
sampler_state->ss3.chroma_key_enable = 0; /* disable chromakey */ |
} |
static drm_intel_bo *gen4_create_sampler_state(intel_screen_private *intel, |
sampler_state_filter_t src_filter, |
sampler_state_extend_t src_extend, |
sampler_state_filter_t mask_filter, |
sampler_state_extend_t mask_extend, |
drm_intel_bo * border_color_bo) |
{ |
drm_intel_bo *sampler_state_bo; |
struct brw_sampler_state *sampler_state; |
int ret; |
sampler_state_bo = |
drm_intel_bo_alloc(intel->bufmgr, "gen4 sampler state", |
sizeof(struct brw_sampler_state) * 2, 4096); |
assert(sampler_state_bo); |
ret = drm_intel_bo_map(sampler_state_bo, TRUE); |
assert(ret == 0); |
sampler_state = sampler_state_bo->virtual; |
gen4_sampler_state_init(sampler_state_bo, |
&sampler_state[0], |
src_filter, src_extend, border_color_bo); |
gen4_sampler_state_init(sampler_state_bo, |
&sampler_state[1], |
mask_filter, mask_extend, border_color_bo); |
drm_intel_bo_unmap(sampler_state_bo); |
return sampler_state_bo; |
(void)ret; |
} |
static drm_intel_bo * |
gen7_create_sampler_state(intel_screen_private *intel, |
sampler_state_filter_t src_filter, |
sampler_state_extend_t src_extend, |
sampler_state_filter_t mask_filter, |
sampler_state_extend_t mask_extend, |
drm_intel_bo * border_color_bo) |
{ |
drm_intel_bo *sampler_state_bo; |
struct gen7_sampler_state *sampler_state; |
int ret; |
sampler_state_bo = |
drm_intel_bo_alloc(intel->bufmgr, "gen7 sampler state", |
sizeof(struct gen7_sampler_state) * 2, 4096); |
assert(sampler_state_bo); |
ret = drm_intel_bo_map(sampler_state_bo, TRUE); |
assert(ret == 0); |
sampler_state = sampler_state_bo->virtual; |
gen7_sampler_state_init(sampler_state_bo, |
&sampler_state[0], |
src_filter, src_extend, border_color_bo); |
gen7_sampler_state_init(sampler_state_bo, |
&sampler_state[1], |
mask_filter, mask_extend, border_color_bo); |
drm_intel_bo_unmap(sampler_state_bo); |
return sampler_state_bo; |
(void)ret; |
} |
static inline drm_intel_bo * |
i965_create_sampler_state(intel_screen_private *intel, |
sampler_state_filter_t src_filter, |
sampler_state_extend_t src_extend, |
sampler_state_filter_t mask_filter, |
sampler_state_extend_t mask_extend, |
drm_intel_bo * border_color_bo) |
{ |
if (INTEL_INFO(intel)->gen < 070) |
return gen4_create_sampler_state(intel, src_filter, src_extend, |
mask_filter, mask_extend, |
border_color_bo); |
return gen7_create_sampler_state(intel, src_filter, src_extend, |
mask_filter, mask_extend, |
border_color_bo); |
} |
static void |
cc_state_init(drm_intel_bo * cc_state_bo, |
uint32_t cc_state_offset, |
int src_blend, int dst_blend, drm_intel_bo * cc_vp_bo) |
{ |
struct brw_cc_unit_state *cc_state; |
cc_state = (struct brw_cc_unit_state *)((char *)cc_state_bo->virtual + |
cc_state_offset); |
memset(cc_state, 0, sizeof(*cc_state)); |
cc_state->cc0.stencil_enable = 0; /* disable stencil */ |
cc_state->cc2.depth_test = 0; /* disable depth test */ |
cc_state->cc2.logicop_enable = 0; /* disable logic op */ |
cc_state->cc3.ia_blend_enable = 0; /* blend alpha same as colors */ |
cc_state->cc3.blend_enable = 1; /* enable color blend */ |
cc_state->cc3.alpha_test = 0; /* disable alpha test */ |
cc_state->cc4.cc_viewport_state_offset = |
intel_emit_reloc(cc_state_bo, cc_state_offset + |
offsetof(struct brw_cc_unit_state, cc4), |
cc_vp_bo, 0, I915_GEM_DOMAIN_INSTRUCTION, 0) >> 5; |
cc_state->cc5.dither_enable = 0; /* disable dither */ |
cc_state->cc5.logicop_func = 0xc; /* COPY */ |
cc_state->cc5.statistics_enable = 1; |
cc_state->cc5.ia_blend_function = BRW_BLENDFUNCTION_ADD; |
/* Fill in alpha blend factors same as color, for the future. */ |
cc_state->cc5.ia_src_blend_factor = src_blend; |
cc_state->cc5.ia_dest_blend_factor = dst_blend; |
cc_state->cc6.blend_function = BRW_BLENDFUNCTION_ADD; |
cc_state->cc6.clamp_post_alpha_blend = 1; |
cc_state->cc6.clamp_pre_alpha_blend = 1; |
cc_state->cc6.clamp_range = 0; /* clamp range [0,1] */ |
cc_state->cc6.src_blend_factor = src_blend; |
cc_state->cc6.dest_blend_factor = dst_blend; |
} |
static drm_intel_bo *gen4_create_wm_state(intel_screen_private *intel, |
Bool has_mask, |
drm_intel_bo * kernel_bo, |
drm_intel_bo * sampler_bo) |
{ |
struct brw_wm_unit_state *state; |
drm_intel_bo *wm_state_bo; |
int ret; |
wm_state_bo = drm_intel_bo_alloc(intel->bufmgr, "gen4 WM state", |
sizeof(*state), 4096); |
assert(wm_state_bo); |
ret = drm_intel_bo_map(wm_state_bo, TRUE); |
assert(ret == 0); |
state = memset(wm_state_bo->virtual, 0, sizeof(*state)); |
state->thread0.grf_reg_count = BRW_GRF_BLOCKS(PS_KERNEL_NUM_GRF); |
state->thread0.kernel_start_pointer = |
intel_emit_reloc(wm_state_bo, |
offsetof(struct brw_wm_unit_state, thread0), |
kernel_bo, state->thread0.grf_reg_count << 1, |
I915_GEM_DOMAIN_INSTRUCTION, 0) >> 6; |
state->thread1.single_program_flow = 0; |
/* scratch space is not used in our kernel */ |
state->thread2.scratch_space_base_pointer = 0; |
state->thread2.per_thread_scratch_space = 0; |
state->thread3.const_urb_entry_read_length = 0; |
state->thread3.const_urb_entry_read_offset = 0; |
state->thread3.urb_entry_read_offset = 0; |
/* wm kernel use urb from 3, see wm_program in compiler module */ |
state->thread3.dispatch_grf_start_reg = 3; /* must match kernel */ |
if (IS_GEN5(intel)) |
state->wm4.sampler_count = 0; /* hardware requirement */ |
else |
state->wm4.sampler_count = 1; /* 1-4 samplers used */ |
state->wm4.sampler_state_pointer = |
intel_emit_reloc(wm_state_bo, |
offsetof(struct brw_wm_unit_state, wm4), |
sampler_bo, |
state->wm4.sampler_count << 2, |
I915_GEM_DOMAIN_INSTRUCTION, 0) >> 5; |
state->wm5.max_threads = PS_MAX_THREADS - 1; |
state->wm5.transposed_urb_read = 0; |
state->wm5.thread_dispatch_enable = 1; |
/* just use 16-pixel dispatch (4 subspans), don't need to change kernel |
* start point |
*/ |
state->wm5.enable_16_pix = 1; |
state->wm5.enable_8_pix = 0; |
state->wm5.early_depth_test = 1; |
/* Each pair of attributes (src/mask coords) is two URB entries */ |
if (has_mask) { |
state->thread1.binding_table_entry_count = 3; /* 2 tex and fb */ |
state->thread3.urb_entry_read_length = 4; |
} else { |
state->thread1.binding_table_entry_count = 2; /* 1 tex and fb */ |
state->thread3.urb_entry_read_length = 2; |
} |
/* binding table entry count is only used for prefetching, and it has to |
* be set 0 for Ironlake |
*/ |
if (IS_GEN5(intel)) |
state->thread1.binding_table_entry_count = 0; |
drm_intel_bo_unmap(wm_state_bo); |
return wm_state_bo; |
(void)ret; |
} |
static drm_intel_bo *gen4_create_cc_viewport(intel_screen_private *intel) |
{ |
drm_intel_bo *bo; |
struct brw_cc_viewport vp; |
int ret; |
vp.min_depth = -1.e35; |
vp.max_depth = 1.e35; |
bo = drm_intel_bo_alloc(intel->bufmgr, "gen4 render unit state", |
sizeof(vp), 4096); |
assert(bo); |
ret = drm_intel_bo_subdata(bo, 0, sizeof(vp), &vp); |
assert(ret == 0); |
return bo; |
(void)ret; |
} |
static drm_intel_bo *gen4_create_vs_unit_state(intel_screen_private *intel) |
{ |
struct brw_vs_unit_state vs_state; |
memset(&vs_state, 0, sizeof(vs_state)); |
/* Set up the vertex shader to be disabled (passthrough) */ |
if (IS_GEN5(intel)) |
vs_state.thread4.nr_urb_entries = URB_VS_ENTRIES >> 2; /* hardware requirement */ |
else |
vs_state.thread4.nr_urb_entries = URB_VS_ENTRIES; |
vs_state.thread4.urb_entry_allocation_size = URB_VS_ENTRY_SIZE - 1; |
vs_state.vs6.vs_enable = 0; |
vs_state.vs6.vert_cache_disable = 1; |
return intel_bo_alloc_for_data(intel, &vs_state, sizeof(vs_state), |
"gen4 render VS state"); |
} |
/** |
* Set up all combinations of cc state: each blendfactor for source and |
* dest. |
*/ |
static drm_intel_bo *gen4_create_cc_unit_state(intel_screen_private *intel) |
{ |
drm_intel_bo *cc_state_bo, *cc_vp_bo; |
int i, j, ret; |
cc_vp_bo = gen4_create_cc_viewport(intel); |
cc_state_bo = drm_intel_bo_alloc(intel->bufmgr, "gen4 CC state", |
sizeof(struct gen4_cc_unit_state), |
4096); |
assert(cc_state_bo); |
ret = drm_intel_bo_map(cc_state_bo, TRUE); |
assert(ret == 0); |
for (i = 0; i < BRW_BLENDFACTOR_COUNT; i++) { |
for (j = 0; j < BRW_BLENDFACTOR_COUNT; j++) { |
cc_state_init(cc_state_bo, |
offsetof(struct gen4_cc_unit_state, |
cc_state[i][j].state), |
i, j, cc_vp_bo); |
} |
} |
drm_intel_bo_unmap(cc_state_bo); |
drm_intel_bo_unreference(cc_vp_bo); |
return cc_state_bo; |
(void)ret; |
} |
static uint32_t i965_get_card_format(PicturePtr picture) |
{ |
int i; |
for (i = 0; i < sizeof(i965_tex_formats) / sizeof(i965_tex_formats[0]); |
i++) { |
if (i965_tex_formats[i].fmt == picture->format) |
break; |
} |
assert(i != sizeof(i965_tex_formats) / sizeof(i965_tex_formats[0])); |
return i965_tex_formats[i].card_fmt; |
} |
static sampler_state_filter_t sampler_state_filter_from_picture(int filter) |
{ |
switch (filter) { |
case PictFilterNearest: |
return SS_FILTER_NEAREST; |
case PictFilterBilinear: |
return SS_FILTER_BILINEAR; |
default: |
return SS_INVALID_FILTER; |
} |
} |
static sampler_state_extend_t sampler_state_extend_from_picture(int repeat_type) |
{ |
switch (repeat_type) { |
case RepeatNone: |
return SS_EXTEND_NONE; |
case RepeatNormal: |
return SS_EXTEND_REPEAT; |
case RepeatPad: |
return SS_EXTEND_PAD; |
case RepeatReflect: |
return SS_EXTEND_REFLECT; |
default: |
return SS_INVALID_EXTEND; |
} |
} |
/** |
* Sets up the common fields for a surface state buffer for the given |
* picture in the given surface state buffer. |
*/ |
static int |
gen4_set_picture_surface_state(intel_screen_private *intel, |
PicturePtr picture, PixmapPtr pixmap, |
Bool is_dst) |
{ |
struct intel_pixmap *priv = pixmap->private; |
struct brw_surface_state *ss; |
uint32_t write_domain, read_domains; |
int offset; |
if (is_dst) { |
write_domain = I915_GEM_DOMAIN_RENDER; |
read_domains = I915_GEM_DOMAIN_RENDER; |
} else { |
write_domain = 0; |
read_domains = I915_GEM_DOMAIN_SAMPLER; |
} |
intel_batch_mark_pixmap_domains(intel, priv, |
read_domains, write_domain); |
ss = (struct brw_surface_state *) |
(intel->surface_data + intel->surface_used); |
memset(ss, 0, sizeof(*ss)); |
ss->ss0.surface_type = BRW_SURFACE_2D; |
if (is_dst) |
ss->ss0.surface_format = i965_get_dest_format(picture); |
else |
ss->ss0.surface_format = i965_get_card_format(picture); |
ss->ss0.data_return_format = BRW_SURFACERETURNFORMAT_FLOAT32; |
ss->ss0.color_blend = 1; |
ss->ss1.base_addr = priv->bo->offset; |
ss->ss2.height = pixmap->drawable.height - 1; |
ss->ss2.width = pixmap->drawable.width - 1; |
ss->ss3.pitch = intel_pixmap_pitch(pixmap) - 1; |
ss->ss3.tile_walk = 0; /* Tiled X */ |
ss->ss3.tiled_surface = intel_pixmap_tiled(pixmap) ? 1 : 0; |
dri_bo_emit_reloc(intel->surface_bo, |
read_domains, write_domain, |
0, |
intel->surface_used + |
offsetof(struct brw_surface_state, ss1), |
priv->bo); |
offset = intel->surface_used; |
intel->surface_used += SURFACE_STATE_PADDED_SIZE; |
return offset; |
} |
static int |
gen7_set_picture_surface_state(intel_screen_private *intel, |
PicturePtr picture, PixmapPtr pixmap, |
Bool is_dst) |
{ |
struct intel_pixmap *priv = pixmap->private; |
struct gen7_surface_state *ss; |
uint32_t write_domain, read_domains; |
int offset; |
if (is_dst) { |
write_domain = I915_GEM_DOMAIN_RENDER; |
read_domains = I915_GEM_DOMAIN_RENDER; |
} else { |
write_domain = 0; |
read_domains = I915_GEM_DOMAIN_SAMPLER; |
} |
intel_batch_mark_pixmap_domains(intel, priv, |
read_domains, write_domain); |
ss = (struct gen7_surface_state *) |
(intel->surface_data + intel->surface_used); |
memset(ss, 0, sizeof(*ss)); |
ss->ss0.surface_type = BRW_SURFACE_2D; |
if (is_dst) |
ss->ss0.surface_format = i965_get_dest_format(picture); |
else |
ss->ss0.surface_format = i965_get_card_format(picture); |
ss->ss0.tile_walk = 0; /* Tiled X */ |
ss->ss0.tiled_surface = intel_pixmap_tiled(pixmap) ? 1 : 0; |
ss->ss1.base_addr = priv->bo->offset; |
ss->ss2.height = pixmap->drawable.height - 1; |
ss->ss2.width = pixmap->drawable.width - 1; |
ss->ss3.pitch = intel_pixmap_pitch(pixmap) - 1; |
if (IS_HSW(intel)) { |
ss->ss7.shader_chanel_select_r = HSW_SCS_RED; |
ss->ss7.shader_chanel_select_g = HSW_SCS_GREEN; |
ss->ss7.shader_chanel_select_b = HSW_SCS_BLUE; |
ss->ss7.shader_chanel_select_a = HSW_SCS_ALPHA; |
} |
dri_bo_emit_reloc(intel->surface_bo, |
read_domains, write_domain, |
0, |
intel->surface_used + |
offsetof(struct gen7_surface_state, ss1), |
priv->bo); |
offset = intel->surface_used; |
intel->surface_used += SURFACE_STATE_PADDED_SIZE; |
return offset; |
} |
static inline int |
i965_set_picture_surface_state(intel_screen_private *intel, |
PicturePtr picture, PixmapPtr pixmap, |
Bool is_dst) |
{ |
if (INTEL_INFO(intel)->gen < 070) |
return gen4_set_picture_surface_state(intel, picture, pixmap, is_dst); |
return gen7_set_picture_surface_state(intel, picture, pixmap, is_dst); |
} |
static void gen4_composite_vertex_elements(struct intel_screen_private *intel) |
{ |
struct gen4_render_state *render_state = intel->gen4_render_state; |
gen4_composite_op *composite_op = &render_state->composite_op; |
Bool has_mask = intel->render_mask != NULL; |
Bool is_affine = composite_op->is_affine; |
/* |
* number of extra parameters per vertex |
*/ |
int nelem = has_mask ? 2 : 1; |
/* |
* size of extra parameters: |
* 3 for homogenous (xyzw) |
* 2 for cartesian (xy) |
*/ |
int selem = is_affine ? 2 : 3; |
uint32_t w_component; |
uint32_t src_format; |
int id; |
id = has_mask << 1 | is_affine; |
if (composite_op->vertex_id == id) |
return; |
composite_op->vertex_id = id; |
if (is_affine) { |
src_format = BRW_SURFACEFORMAT_R32G32_FLOAT; |
w_component = BRW_VFCOMPONENT_STORE_1_FLT; |
} else { |
src_format = BRW_SURFACEFORMAT_R32G32B32_FLOAT; |
w_component = BRW_VFCOMPONENT_STORE_SRC; |
} |
if (IS_GEN5(intel)) { |
/* |
* The reason to add this extra vertex element in the header is that |
* Ironlake has different vertex header definition and origin method to |
* set destination element offset doesn't exist anymore, which means |
* hardware requires a predefined vertex element layout. |
* |
* haihao proposed this approach to fill the first vertex element, so |
* origin layout for Gen4 doesn't need to change, and origin shader |
* programs behavior is also kept. |
* |
* I think this is not bad. - zhenyu |
*/ |
OUT_BATCH(BRW_3DSTATE_VERTEX_ELEMENTS | |
((2 * (2 + nelem)) - 1)); |
OUT_BATCH((id << VE0_VERTEX_BUFFER_INDEX_SHIFT) | VE0_VALID | |
(BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) | |
(0 << VE0_OFFSET_SHIFT)); |
OUT_BATCH((BRW_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT) | |
(BRW_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT) | |
(BRW_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT) | |
(BRW_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT)); |
} else { |
/* Set up our vertex elements, sourced from the single vertex buffer. |
* that will be set up later. |
*/ |
OUT_BATCH(BRW_3DSTATE_VERTEX_ELEMENTS | |
((2 * (1 + nelem)) - 1)); |
} |
/* x,y */ |
OUT_BATCH((id << VE0_VERTEX_BUFFER_INDEX_SHIFT) | VE0_VALID | |
(BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) | |
(0 << VE0_OFFSET_SHIFT)); |
if (IS_GEN5(intel)) |
OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) | |
(BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) | |
(BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) | |
(BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT)); |
else |
OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) | |
(BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) | |
(BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) | |
(BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) | |
(4 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT)); |
/* u0, v0, w0 */ |
OUT_BATCH((id << VE0_VERTEX_BUFFER_INDEX_SHIFT) | VE0_VALID | |
(src_format << VE0_FORMAT_SHIFT) | |
((2 * 4) << VE0_OFFSET_SHIFT)); /* offset vb in bytes */ |
if (IS_GEN5(intel)) |
OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) | |
(BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) | |
(w_component << VE1_VFCOMPONENT_2_SHIFT) | |
(BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT)); |
else |
OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) | |
(BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) | |
(w_component << VE1_VFCOMPONENT_2_SHIFT) | |
(BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) | |
((4 + 4) << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT)); /* VUE offset in dwords */ |
/* u1, v1, w1 */ |
if (has_mask) { |
OUT_BATCH((id << VE0_VERTEX_BUFFER_INDEX_SHIFT) | VE0_VALID | |
(src_format << VE0_FORMAT_SHIFT) | |
(((2 + selem) * 4) << VE0_OFFSET_SHIFT)); /* vb offset in bytes */ |
if (IS_GEN5(intel)) |
OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) | |
(BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) | |
(w_component << VE1_VFCOMPONENT_2_SHIFT) | |
(BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT)); |
else |
OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) | |
(BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) | |
(w_component << VE1_VFCOMPONENT_2_SHIFT) | |
(BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) | |
((4 + 4 + 4) << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT)); /* VUE offset in dwords */ |
} |
} |
static void i965_emit_composite_state(struct intel_screen_private *intel) |
{ |
struct gen4_render_state *render_state = intel->gen4_render_state; |
gen4_composite_op *composite_op = &render_state->composite_op; |
int op = composite_op->op; |
PicturePtr mask_picture = intel->render_mask_picture; |
PicturePtr dest_picture = intel->render_dest_picture; |
PixmapPtr mask = intel->render_mask; |
PixmapPtr dest = intel->render_dest; |
sampler_state_filter_t src_filter = composite_op->src_filter; |
sampler_state_filter_t mask_filter = composite_op->mask_filter; |
sampler_state_extend_t src_extend = composite_op->src_extend; |
sampler_state_extend_t mask_extend = composite_op->mask_extend; |
uint32_t src_blend, dst_blend; |
intel->needs_render_state_emit = FALSE; |
/* Begin the long sequence of commands needed to set up the 3D |
* rendering pipe |
*/ |
if (intel->needs_3d_invariant) { |
if (IS_GEN5(intel)) { |
/* Ironlake errata workaround: Before disabling the clipper, |
* you have to MI_FLUSH to get the pipeline idle. |
*/ |
OUT_BATCH(MI_FLUSH | MI_INHIBIT_RENDER_CACHE_FLUSH); |
} |
/* Match Mesa driver setup */ |
if (INTEL_INFO(intel)->gen >= 045) |
OUT_BATCH(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D); |
else |
OUT_BATCH(BRW_PIPELINE_SELECT | PIPELINE_SELECT_3D); |
/* Set system instruction pointer */ |
OUT_BATCH(BRW_STATE_SIP | 0); |
OUT_BATCH(0); |
intel->needs_3d_invariant = FALSE; |
} |
if (intel->surface_reloc == 0) { |
/* Zero out the two base address registers so all offsets are |
* absolute. |
*/ |
if (IS_GEN5(intel)) { |
OUT_BATCH(BRW_STATE_BASE_ADDRESS | 6); |
OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* Generate state base address */ |
intel->surface_reloc = intel->batch_used; |
intel_batch_emit_dword(intel, |
intel->surface_bo->offset | BASE_ADDRESS_MODIFY); |
OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* media base addr, don't care */ |
OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* Instruction base address */ |
/* general state max addr, disabled */ |
OUT_BATCH(0 | BASE_ADDRESS_MODIFY); |
/* media object state max addr, disabled */ |
OUT_BATCH(0 | BASE_ADDRESS_MODIFY); |
/* Instruction max addr, disabled */ |
OUT_BATCH(0 | BASE_ADDRESS_MODIFY); |
} else { |
OUT_BATCH(BRW_STATE_BASE_ADDRESS | 4); |
OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* Generate state base address */ |
intel->surface_reloc = intel->batch_used; |
intel_batch_emit_dword(intel, |
intel->surface_bo->offset | BASE_ADDRESS_MODIFY); |
OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* media base addr, don't care */ |
/* general state max addr, disabled */ |
OUT_BATCH(0 | BASE_ADDRESS_MODIFY); |
/* media object state max addr, disabled */ |
OUT_BATCH(0 | BASE_ADDRESS_MODIFY); |
} |
} |
i965_get_blend_cntl(op, mask_picture, dest_picture->format, |
&src_blend, &dst_blend); |
/* Binding table pointers */ |
OUT_BATCH(BRW_3DSTATE_BINDING_TABLE_POINTERS | 4); |
OUT_BATCH(0); /* vs */ |
OUT_BATCH(0); /* gs */ |
OUT_BATCH(0); /* clip */ |
OUT_BATCH(0); /* sf */ |
/* Only the PS uses the binding table */ |
OUT_BATCH(intel->surface_table); |
/* The drawing rectangle clipping is always on. Set it to values that |
* shouldn't do any clipping. |
*/ |
OUT_BATCH(BRW_3DSTATE_DRAWING_RECTANGLE | 2); |
OUT_BATCH(0x00000000); /* ymin, xmin */ |
OUT_BATCH(DRAW_YMAX(dest->drawable.height - 1) | |
DRAW_XMAX(dest->drawable.width - 1)); /* ymax, xmax */ |
OUT_BATCH(0x00000000); /* yorigin, xorigin */ |
/* skip the depth buffer */ |
/* skip the polygon stipple */ |
/* skip the polygon stipple offset */ |
/* skip the line stipple */ |
/* Set the pointers to the 3d pipeline state */ |
OUT_BATCH(BRW_3DSTATE_PIPELINED_POINTERS | 5); |
OUT_RELOC(render_state->vs_state_bo, |
I915_GEM_DOMAIN_INSTRUCTION, 0, 0); |
OUT_BATCH(BRW_GS_DISABLE); /* disable GS, resulting in passthrough */ |
OUT_BATCH(BRW_CLIP_DISABLE); /* disable CLIP, resulting in passthrough */ |
if (mask) { |
OUT_RELOC(render_state->sf_mask_state_bo, |
I915_GEM_DOMAIN_INSTRUCTION, 0, 0); |
} else { |
OUT_RELOC(render_state->sf_state_bo, |
I915_GEM_DOMAIN_INSTRUCTION, 0, 0); |
} |
OUT_RELOC(render_state->wm_state_bo[composite_op->wm_kernel] |
[src_filter][src_extend] |
[mask_filter][mask_extend], |
I915_GEM_DOMAIN_INSTRUCTION, 0, 0); |
OUT_RELOC(render_state->cc_state_bo, |
I915_GEM_DOMAIN_INSTRUCTION, 0, |
offsetof(struct gen4_cc_unit_state, |
cc_state[src_blend][dst_blend])); |
{ |
int urb_vs_start, urb_vs_size; |
int urb_gs_start, urb_gs_size; |
int urb_clip_start, urb_clip_size; |
int urb_sf_start, urb_sf_size; |
int urb_cs_start, urb_cs_size; |
urb_vs_start = 0; |
urb_vs_size = URB_VS_ENTRIES * URB_VS_ENTRY_SIZE; |
urb_gs_start = urb_vs_start + urb_vs_size; |
urb_gs_size = URB_GS_ENTRIES * URB_GS_ENTRY_SIZE; |
urb_clip_start = urb_gs_start + urb_gs_size; |
urb_clip_size = URB_CLIP_ENTRIES * URB_CLIP_ENTRY_SIZE; |
urb_sf_start = urb_clip_start + urb_clip_size; |
urb_sf_size = URB_SF_ENTRIES * URB_SF_ENTRY_SIZE; |
urb_cs_start = urb_sf_start + urb_sf_size; |
urb_cs_size = URB_CS_ENTRIES * URB_CS_ENTRY_SIZE; |
/* Erratum (Vol 1a, p32): |
* URB_FENCE must not cross a cache-line (64 bytes). |
*/ |
if ((intel->batch_used & 15) > (16 - 3)) { |
int cnt = 16 - (intel->batch_used & 15); |
while (cnt--) |
OUT_BATCH(MI_NOOP); |
} |
OUT_BATCH(BRW_URB_FENCE | |
UF0_CS_REALLOC | |
UF0_SF_REALLOC | |
UF0_CLIP_REALLOC | |
UF0_GS_REALLOC | |
UF0_VS_REALLOC | |
1); |
OUT_BATCH(((urb_clip_start + urb_clip_size) << UF1_CLIP_FENCE_SHIFT) | |
((urb_gs_start + urb_gs_size) << UF1_GS_FENCE_SHIFT) | |
((urb_vs_start + urb_vs_size) << UF1_VS_FENCE_SHIFT)); |
OUT_BATCH(((urb_cs_start + urb_cs_size) << UF2_CS_FENCE_SHIFT) | |
((urb_sf_start + urb_sf_size) << UF2_SF_FENCE_SHIFT)); |
/* Constant buffer state */ |
OUT_BATCH(BRW_CS_URB_STATE | 0); |
OUT_BATCH(((URB_CS_ENTRY_SIZE - 1) << 4) | |
(URB_CS_ENTRIES << 0)); |
} |
gen4_composite_vertex_elements(intel); |
} |
/** |
* Returns whether the current set of composite state plus vertex buffer is |
* expected to fit in the aperture. |
*/ |
static Bool i965_composite_check_aperture(intel_screen_private *intel) |
{ |
struct gen4_render_state *render_state = intel->gen4_render_state; |
gen4_composite_op *composite_op = &render_state->composite_op; |
drm_intel_bo *bo_table[] = { |
intel->batch_bo, |
intel->vertex_bo, |
intel->surface_bo, |
render_state->vs_state_bo, |
render_state->sf_state_bo, |
render_state->sf_mask_state_bo, |
render_state->wm_state_bo[composite_op->wm_kernel] |
[composite_op->src_filter] |
[composite_op->src_extend] |
[composite_op->mask_filter] |
[composite_op->mask_extend], |
render_state->cc_state_bo, |
}; |
drm_intel_bo *gen6_bo_table[] = { |
intel->batch_bo, |
intel->vertex_bo, |
intel->surface_bo, |
render_state->wm_kernel_bo[composite_op->wm_kernel], |
render_state->ps_sampler_state_bo[composite_op->src_filter] |
[composite_op->src_extend] |
[composite_op->mask_filter] |
[composite_op->mask_extend], |
render_state->cc_vp_bo, |
render_state->cc_state_bo, |
render_state->gen6_blend_bo, |
render_state->gen6_depth_stencil_bo, |
}; |
if (INTEL_INFO(intel)->gen >= 060) |
return drm_intel_bufmgr_check_aperture_space(gen6_bo_table, |
ARRAY_SIZE(gen6_bo_table)) == 0; |
else |
return drm_intel_bufmgr_check_aperture_space(bo_table, |
ARRAY_SIZE(bo_table)) == 0; |
} |
static void i965_surface_flush(struct intel_screen_private *intel) |
{ |
int ret; |
ret = drm_intel_bo_subdata(intel->surface_bo, |
0, intel->surface_used, |
intel->surface_data); |
assert(ret == 0); |
intel->surface_used = 0; |
assert (intel->surface_reloc != 0); |
drm_intel_bo_emit_reloc(intel->batch_bo, |
intel->surface_reloc * 4, |
intel->surface_bo, BASE_ADDRESS_MODIFY, |
I915_GEM_DOMAIN_INSTRUCTION, 0); |
intel->surface_reloc = 0; |
drm_intel_bo_unreference(intel->surface_bo); |
intel->surface_bo = |
drm_intel_bo_alloc(intel->bufmgr, "surface data", |
sizeof(intel->surface_data), 4096); |
assert(intel->surface_bo); |
return; |
(void)ret; |
} |
static void |
i965_emit_composite_primitive_identity_source(intel_screen_private *intel, |
int srcX, int srcY, |
int maskX, int maskY, |
int dstX, int dstY, |
int w, int h) |
{ |
OUT_VERTEX(dstX + w); |
OUT_VERTEX(dstY + h); |
OUT_VERTEX((srcX + w) * intel->scale_units[0][0]); |
OUT_VERTEX((srcY + h) * intel->scale_units[0][1]); |
OUT_VERTEX(dstX); |
OUT_VERTEX(dstY + h); |
OUT_VERTEX(srcX * intel->scale_units[0][0]); |
OUT_VERTEX((srcY + h) * intel->scale_units[0][1]); |
OUT_VERTEX(dstX); |
OUT_VERTEX(dstY); |
OUT_VERTEX(srcX * intel->scale_units[0][0]); |
OUT_VERTEX(srcY * intel->scale_units[0][1]); |
} |
static void |
i965_emit_composite_primitive_affine_source(intel_screen_private *intel, |
int srcX, int srcY, |
int maskX, int maskY, |
int dstX, int dstY, |
int w, int h) |
{ |
float src_x[3], src_y[3]; |
if (!intel_get_transformed_coordinates(srcX, srcY, |
intel->transform[0], |
&src_x[0], |
&src_y[0])) |
return; |
if (!intel_get_transformed_coordinates(srcX, srcY + h, |
intel->transform[0], |
&src_x[1], |
&src_y[1])) |
return; |
if (!intel_get_transformed_coordinates(srcX + w, srcY + h, |
intel->transform[0], |
&src_x[2], |
&src_y[2])) |
return; |
OUT_VERTEX(dstX + w); |
OUT_VERTEX(dstY + h); |
OUT_VERTEX(src_x[2] * intel->scale_units[0][0]); |
OUT_VERTEX(src_y[2] * intel->scale_units[0][1]); |
OUT_VERTEX(dstX); |
OUT_VERTEX(dstY + h); |
OUT_VERTEX(src_x[1] * intel->scale_units[0][0]); |
OUT_VERTEX(src_y[1] * intel->scale_units[0][1]); |
OUT_VERTEX(dstX); |
OUT_VERTEX(dstY); |
OUT_VERTEX(src_x[0] * intel->scale_units[0][0]); |
OUT_VERTEX(src_y[0] * intel->scale_units[0][1]); |
} |
static void |
i965_emit_composite_primitive_identity_source_mask(intel_screen_private *intel, |
int srcX, int srcY, |
int maskX, int maskY, |
int dstX, int dstY, |
int w, int h) |
{ |
OUT_VERTEX(dstX + w); |
OUT_VERTEX(dstY + h); |
OUT_VERTEX((srcX + w) * intel->scale_units[0][0]); |
OUT_VERTEX((srcY + h) * intel->scale_units[0][1]); |
OUT_VERTEX((maskX + w) * intel->scale_units[1][0]); |
OUT_VERTEX((maskY + h) * intel->scale_units[1][1]); |
OUT_VERTEX(dstX); |
OUT_VERTEX(dstY + h); |
OUT_VERTEX(srcX * intel->scale_units[0][0]); |
OUT_VERTEX((srcY + h) * intel->scale_units[0][1]); |
OUT_VERTEX(maskX * intel->scale_units[1][0]); |
OUT_VERTEX((maskY + h) * intel->scale_units[1][1]); |
OUT_VERTEX(dstX); |
OUT_VERTEX(dstY); |
OUT_VERTEX(srcX * intel->scale_units[0][0]); |
OUT_VERTEX(srcY * intel->scale_units[0][1]); |
OUT_VERTEX(maskX * intel->scale_units[1][0]); |
OUT_VERTEX(maskY * intel->scale_units[1][1]); |
} |
static void |
i965_emit_composite_primitive(intel_screen_private *intel, |
int srcX, int srcY, |
int maskX, int maskY, |
int dstX, int dstY, |
int w, int h) |
{ |
float src_x[3], src_y[3], src_w[3], mask_x[3], mask_y[3], mask_w[3]; |
Bool is_affine = intel->gen4_render_state->composite_op.is_affine; |
if (is_affine) { |
if (!intel_get_transformed_coordinates(srcX, srcY, |
intel->transform[0], |
&src_x[0], |
&src_y[0])) |
return; |
if (!intel_get_transformed_coordinates(srcX, srcY + h, |
intel->transform[0], |
&src_x[1], |
&src_y[1])) |
return; |
if (!intel_get_transformed_coordinates(srcX + w, srcY + h, |
intel->transform[0], |
&src_x[2], |
&src_y[2])) |
return; |
} else { |
if (!intel_get_transformed_coordinates_3d(srcX, srcY, |
intel->transform[0], |
&src_x[0], |
&src_y[0], |
&src_w[0])) |
return; |
if (!intel_get_transformed_coordinates_3d(srcX, srcY + h, |
intel->transform[0], |
&src_x[1], |
&src_y[1], |
&src_w[1])) |
return; |
if (!intel_get_transformed_coordinates_3d(srcX + w, srcY + h, |
intel->transform[0], |
&src_x[2], |
&src_y[2], |
&src_w[2])) |
return; |
} |
if (intel->render_mask) { |
if (is_affine) { |
if (!intel_get_transformed_coordinates(maskX, maskY, |
intel->transform[1], |
&mask_x[0], |
&mask_y[0])) |
return; |
if (!intel_get_transformed_coordinates(maskX, maskY + h, |
intel->transform[1], |
&mask_x[1], |
&mask_y[1])) |
return; |
if (!intel_get_transformed_coordinates(maskX + w, maskY + h, |
intel->transform[1], |
&mask_x[2], |
&mask_y[2])) |
return; |
} else { |
if (!intel_get_transformed_coordinates_3d(maskX, maskY, |
intel->transform[1], |
&mask_x[0], |
&mask_y[0], |
&mask_w[0])) |
return; |
if (!intel_get_transformed_coordinates_3d(maskX, maskY + h, |
intel->transform[1], |
&mask_x[1], |
&mask_y[1], |
&mask_w[1])) |
return; |
if (!intel_get_transformed_coordinates_3d(maskX + w, maskY + h, |
intel->transform[1], |
&mask_x[2], |
&mask_y[2], |
&mask_w[2])) |
return; |
} |
} |
OUT_VERTEX(dstX + w); |
OUT_VERTEX(dstY + h); |
OUT_VERTEX(src_x[2] * intel->scale_units[0][0]); |
OUT_VERTEX(src_y[2] * intel->scale_units[0][1]); |
if (!is_affine) |
OUT_VERTEX(src_w[2]); |
if (intel->render_mask) { |
OUT_VERTEX(mask_x[2] * intel->scale_units[1][0]); |
OUT_VERTEX(mask_y[2] * intel->scale_units[1][1]); |
if (!is_affine) |
OUT_VERTEX(mask_w[2]); |
} |
OUT_VERTEX(dstX); |
OUT_VERTEX(dstY + h); |
OUT_VERTEX(src_x[1] * intel->scale_units[0][0]); |
OUT_VERTEX(src_y[1] * intel->scale_units[0][1]); |
if (!is_affine) |
OUT_VERTEX(src_w[1]); |
if (intel->render_mask) { |
OUT_VERTEX(mask_x[1] * intel->scale_units[1][0]); |
OUT_VERTEX(mask_y[1] * intel->scale_units[1][1]); |
if (!is_affine) |
OUT_VERTEX(mask_w[1]); |
} |
OUT_VERTEX(dstX); |
OUT_VERTEX(dstY); |
OUT_VERTEX(src_x[0] * intel->scale_units[0][0]); |
OUT_VERTEX(src_y[0] * intel->scale_units[0][1]); |
if (!is_affine) |
OUT_VERTEX(src_w[0]); |
if (intel->render_mask) { |
OUT_VERTEX(mask_x[0] * intel->scale_units[1][0]); |
OUT_VERTEX(mask_y[0] * intel->scale_units[1][1]); |
if (!is_affine) |
OUT_VERTEX(mask_w[0]); |
} |
} |
Bool |
i965_prepare_composite(int op, PicturePtr source_picture, |
PicturePtr mask_picture, PicturePtr dest_picture, |
PixmapPtr source, PixmapPtr mask, PixmapPtr dest) |
{ |
intel_screen_private *intel = intel_get_screen_private(); |
struct gen4_render_state *render_state = intel->gen4_render_state; |
gen4_composite_op *composite_op = &render_state->composite_op; |
composite_op->src_filter = |
sampler_state_filter_from_picture(source_picture->filter); |
if (composite_op->src_filter == SS_INVALID_FILTER) { |
intel_debug_fallback("Bad src filter 0x%x\n", |
source_picture->filter); |
return FALSE; |
} |
composite_op->src_extend = |
sampler_state_extend_from_picture(source_picture->repeatType); |
if (composite_op->src_extend == SS_INVALID_EXTEND) { |
intel_debug_fallback("Bad src repeat 0x%x\n", |
source_picture->repeatType); |
return FALSE; |
} |
if (mask_picture) { |
if (mask_picture->componentAlpha && |
PICT_FORMAT_RGB(mask_picture->format)) { |
/* Check if it's component alpha that relies on a source alpha and on |
* the source value. We can only get one of those into the single |
* source value that we get to blend with. |
*/ |
if (i965_blend_op[op].src_alpha && |
(i965_blend_op[op].src_blend != BRW_BLENDFACTOR_ZERO)) { |
intel_debug_fallback("Component alpha not supported " |
"with source alpha and source " |
"value blending.\n"); |
return FALSE; |
} |
} |
composite_op->mask_filter = |
sampler_state_filter_from_picture(mask_picture->filter); |
if (composite_op->mask_filter == SS_INVALID_FILTER) { |
intel_debug_fallback("Bad mask filter 0x%x\n", |
mask_picture->filter); |
return FALSE; |
} |
composite_op->mask_extend = |
sampler_state_extend_from_picture(mask_picture->repeatType); |
if (composite_op->mask_extend == SS_INVALID_EXTEND) { |
intel_debug_fallback("Bad mask repeat 0x%x\n", |
mask_picture->repeatType); |
return FALSE; |
} |
} else { |
composite_op->mask_filter = SS_FILTER_NEAREST; |
composite_op->mask_extend = SS_EXTEND_NONE; |
} |
/* Flush any pending writes prior to relocating the textures. */ |
if (intel_pixmap_is_dirty(source) || intel_pixmap_is_dirty(mask)) |
intel_batch_emit_flush(); |
composite_op->op = op; |
intel->render_source_picture = source_picture; |
intel->render_mask_picture = mask_picture; |
intel->render_dest_picture = dest_picture; |
intel->render_source = source; |
intel->render_mask = mask; |
intel->render_dest = dest; |
intel->scale_units[0][0] = 1. / source->drawable.width; |
intel->scale_units[0][1] = 1. / source->drawable.height; |
intel->transform[0] = source_picture->transform; |
composite_op->is_affine = intel_transform_is_affine(intel->transform[0]); |
if (mask_picture == NULL) { |
intel->transform[1] = NULL; |
intel->scale_units[1][0] = -1; |
intel->scale_units[1][1] = -1; |
} else { |
assert(mask != NULL); |
intel->transform[1] = mask_picture->transform; |
intel->scale_units[1][0] = 1. / mask->drawable.width; |
intel->scale_units[1][1] = 1. / mask->drawable.height; |
composite_op->is_affine &= |
intel_transform_is_affine(intel->transform[1]); |
} |
if (mask) { |
if (mask_picture->componentAlpha && |
PICT_FORMAT_RGB(mask_picture->format)) { |
if (i965_blend_op[op].src_alpha) { |
if (composite_op->is_affine) |
composite_op->wm_kernel = |
WM_KERNEL_MASKCA_SRCALPHA_AFFINE; |
else |
composite_op->wm_kernel = |
WM_KERNEL_MASKCA_SRCALPHA_PROJECTIVE; |
} else { |
if (composite_op->is_affine) |
composite_op->wm_kernel = |
WM_KERNEL_MASKCA_AFFINE; |
else |
composite_op->wm_kernel = |
WM_KERNEL_MASKCA_PROJECTIVE; |
} |
} else { |
if (composite_op->is_affine) |
composite_op->wm_kernel = |
WM_KERNEL_MASKNOCA_AFFINE; |
else |
composite_op->wm_kernel = |
WM_KERNEL_MASKNOCA_PROJECTIVE; |
} |
} else { |
if (composite_op->is_affine) |
composite_op->wm_kernel = WM_KERNEL_NOMASK_AFFINE; |
else |
composite_op->wm_kernel = WM_KERNEL_NOMASK_PROJECTIVE; |
} |
intel->prim_emit = i965_emit_composite_primitive; |
if (!mask) { |
if (intel->transform[0] == NULL) |
intel->prim_emit = i965_emit_composite_primitive_identity_source; |
else if (composite_op->is_affine) |
intel->prim_emit = i965_emit_composite_primitive_affine_source; |
} else { |
if (intel->transform[0] == NULL && intel->transform[1] == NULL) |
intel->prim_emit = i965_emit_composite_primitive_identity_source_mask; |
} |
intel->floats_per_vertex = |
2 + (mask ? 2 : 1) * (composite_op->is_affine ? 2: 3); |
if (!i965_composite_check_aperture(intel)) { |
intel_batch_submit(); |
if (!i965_composite_check_aperture(intel)) { |
intel_debug_fallback("Couldn't fit render operation " |
"in aperture\n"); |
return FALSE; |
} |
} |
if (sizeof(intel->surface_data) - intel->surface_used < |
4 * SURFACE_STATE_PADDED_SIZE) |
i965_surface_flush(intel); |
intel->needs_render_state_emit = TRUE; |
return TRUE; |
} |
static void i965_select_vertex_buffer(struct intel_screen_private *intel) |
{ |
int id = intel->gen4_render_state->composite_op.vertex_id; |
int modifyenable = 0; |
if (intel->vertex_id & (1 << id)) |
return; |
if (INTEL_INFO(intel)->gen >= 070) |
modifyenable = GEN7_VB0_ADDRESS_MODIFYENABLE; |
/* Set up the pointer to our (single) vertex buffer */ |
OUT_BATCH(BRW_3DSTATE_VERTEX_BUFFERS | 3); |
/* XXX could use multiple vbo to reduce relocations if |
* frequently switching between vertex sizes, like rgb10text. |
*/ |
if (INTEL_INFO(intel)->gen >= 060) { |
OUT_BATCH((id << GEN6_VB0_BUFFER_INDEX_SHIFT) | |
GEN6_VB0_VERTEXDATA | |
modifyenable | |
(4*intel->floats_per_vertex << VB0_BUFFER_PITCH_SHIFT)); |
} else { |
OUT_BATCH((id << VB0_BUFFER_INDEX_SHIFT) | |
VB0_VERTEXDATA | |
(4*intel->floats_per_vertex << VB0_BUFFER_PITCH_SHIFT)); |
} |
OUT_RELOC(intel->vertex_bo, I915_GEM_DOMAIN_VERTEX, 0, 0); |
if (INTEL_INFO(intel)->gen >= 050) |
OUT_RELOC(intel->vertex_bo, |
I915_GEM_DOMAIN_VERTEX, 0, |
sizeof(intel->vertex_ptr) - 1); |
else |
OUT_BATCH(0); |
OUT_BATCH(0); // ignore for VERTEXDATA, but still there |
intel->vertex_id |= 1 << id; |
} |
static void i965_bind_surfaces(struct intel_screen_private *intel) |
{ |
uint32_t *binding_table; |
assert(intel->surface_used + 4 * SURFACE_STATE_PADDED_SIZE <= sizeof(intel->surface_data)); |
binding_table = (uint32_t*) (intel->surface_data + intel->surface_used); |
intel->surface_table = intel->surface_used; |
intel->surface_used += SURFACE_STATE_PADDED_SIZE; |
binding_table[0] = |
i965_set_picture_surface_state(intel, |
intel->render_dest_picture, |
intel->render_dest, |
TRUE); |
binding_table[1] = |
i965_set_picture_surface_state(intel, |
intel->render_source_picture, |
intel->render_source, |
FALSE); |
if (intel->render_mask) { |
binding_table[2] = |
i965_set_picture_surface_state(intel, |
intel->render_mask_picture, |
intel->render_mask, |
FALSE); |
} |
} |
void |
i965_composite(PixmapPtr dest, int srcX, int srcY, int maskX, int maskY, |
int dstX, int dstY, int w, int h) |
{ |
intel_screen_private *intel = intel_get_screen_private(); |
intel_batch_start_atomic(200); |
if (intel->needs_render_state_emit) { |
i965_bind_surfaces(intel); |
if (INTEL_INFO(intel)->gen >= 060) |
gen6_emit_composite_state(intel); |
else |
i965_emit_composite_state(intel); |
} |
if (intel->floats_per_vertex != intel->last_floats_per_vertex) { |
intel->vertex_index = (intel->vertex_used + intel->floats_per_vertex - 1) / intel->floats_per_vertex; |
intel->vertex_used = intel->vertex_index * intel->floats_per_vertex; |
intel->last_floats_per_vertex = intel->floats_per_vertex; |
} |
if (intel_vertex_space(intel) < 3*4*intel->floats_per_vertex) { |
i965_vertex_flush(intel); |
intel_next_vertex(intel); |
intel->vertex_index = 0; |
} |
i965_select_vertex_buffer(intel); |
if (intel->vertex_offset == 0) { |
if (INTEL_INFO(intel)->gen >= 070) { |
OUT_BATCH(BRW_3DPRIMITIVE | (7 - 2)); |
OUT_BATCH(BRW_3DPRIMITIVE_VERTEX_SEQUENTIAL | |
_3DPRIM_RECTLIST); |
} else { |
OUT_BATCH(BRW_3DPRIMITIVE | |
BRW_3DPRIMITIVE_VERTEX_SEQUENTIAL | |
(_3DPRIM_RECTLIST << BRW_3DPRIMITIVE_TOPOLOGY_SHIFT) | |
(0 << 9) | |
4); |
} |
intel->vertex_offset = intel->batch_used; |
OUT_BATCH(0); /* vertex count, to be filled in later */ |
OUT_BATCH(intel->vertex_index); |
OUT_BATCH(1); /* single instance */ |
OUT_BATCH(0); /* start instance location */ |
OUT_BATCH(0); /* index buffer offset, ignored */ |
intel->vertex_count = intel->vertex_index; |
} |
intel->prim_emit(intel, |
srcX, srcY, |
maskX, maskY, |
dstX, dstY, |
w, h); |
intel->vertex_index += 3; |
if (INTEL_INFO(intel)->gen < 050) { |
/* XXX OMG! */ |
i965_vertex_flush(intel); |
OUT_BATCH(MI_FLUSH | MI_INHIBIT_RENDER_CACHE_FLUSH); |
} |
intel_batch_end_atomic(); |
} |
void i965_batch_commit_notify(intel_screen_private *intel) |
{ |
intel->needs_render_state_emit = TRUE; |
intel->needs_3d_invariant = TRUE; |
intel->last_floats_per_vertex = 0; |
intel->vertex_index = 0; |
intel->gen4_render_state->composite_op.vertex_id = -1; |
intel->gen6_render_state.num_sf_outputs = 0; |
intel->gen6_render_state.samplers = NULL; |
intel->gen6_render_state.blend = -1; |
intel->gen6_render_state.kernel = NULL; |
intel->gen6_render_state.drawrect = -1; |
assert(intel->surface_reloc == 0); |
} |
/** |
* Called at EnterVT so we can set up our offsets into the state buffer. |
*/ |
void gen4_render_state_init() |
{ |
ENTER(); |
intel_screen_private *intel = intel_get_screen_private(); |
struct gen4_render_state *render; |
const struct wm_kernel_info *wm_kernels; |
sampler_state_filter_t src_filter; |
sampler_state_extend_t src_extend; |
sampler_state_filter_t mask_filter; |
sampler_state_extend_t mask_extend; |
drm_intel_bo *sf_kernel_bo, *sf_kernel_mask_bo; |
drm_intel_bo *border_color_bo; |
int m; |
intel->needs_3d_invariant = TRUE; |
intel->surface_bo = |
drm_intel_bo_alloc(intel->bufmgr, "surface data", |
sizeof(intel->surface_data), 4096); |
assert(intel->surface_bo); |
intel->surface_used = 0; |
if (intel->gen4_render_state == NULL) { |
intel->gen4_render_state = calloc(1, sizeof(*render)); |
assert(intel->gen4_render_state != NULL); |
} |
if (INTEL_INFO(intel)->gen >= 060) |
return gen6_render_state_init(); |
render = intel->gen4_render_state; |
render->composite_op.vertex_id = -1; |
render->vs_state_bo = gen4_create_vs_unit_state(intel); |
/* Set up the two SF states (one for blending with a mask, one without) */ |
if (IS_GEN5(intel)) { |
sf_kernel_bo = intel_bo_alloc_for_data(intel, |
sf_kernel_static_gen5, |
sizeof |
(sf_kernel_static_gen5), |
"sf kernel gen5"); |
sf_kernel_mask_bo = |
intel_bo_alloc_for_data(intel, sf_kernel_mask_static_gen5, |
sizeof(sf_kernel_mask_static_gen5), |
"sf mask kernel"); |
} else { |
sf_kernel_bo = intel_bo_alloc_for_data(intel, |
sf_kernel_static, |
sizeof(sf_kernel_static), |
"sf kernel"); |
sf_kernel_mask_bo = intel_bo_alloc_for_data(intel, |
sf_kernel_mask_static, |
sizeof |
(sf_kernel_mask_static), |
"sf mask kernel"); |
} |
render->sf_state_bo = gen4_create_sf_state(intel, sf_kernel_bo); |
render->sf_mask_state_bo = gen4_create_sf_state(intel, sf_kernel_mask_bo); |
drm_intel_bo_unreference(sf_kernel_bo); |
drm_intel_bo_unreference(sf_kernel_mask_bo); |
wm_kernels = IS_GEN5(intel) ? wm_kernels_gen5 : wm_kernels_gen4; |
for (m = 0; m < KERNEL_COUNT; m++) { |
render->wm_kernel_bo[m] = |
intel_bo_alloc_for_data(intel, |
wm_kernels[m].data, |
wm_kernels[m].size, |
"WM kernel"); |
} |
/* Set up the WM states: each filter/extend type for source and mask, per |
* kernel. |
*/ |
border_color_bo = sampler_border_color_create(intel); |
for (src_filter = 0; src_filter < FILTER_COUNT; src_filter++) { |
for (src_extend = 0; src_extend < EXTEND_COUNT; src_extend++) { |
for (mask_filter = 0; mask_filter < FILTER_COUNT; mask_filter++) { |
for (mask_extend = 0; mask_extend < EXTEND_COUNT; mask_extend++) { |
drm_intel_bo *sampler_state_bo; |
sampler_state_bo = |
i965_create_sampler_state(intel, |
src_filter, src_extend, |
mask_filter, mask_extend, |
border_color_bo); |
for (m = 0; m < KERNEL_COUNT; m++) { |
render->wm_state_bo[m][src_filter][src_extend][mask_filter][mask_extend] = |
gen4_create_wm_state |
(intel, |
wm_kernels[m]. has_mask, |
render->wm_kernel_bo[m], |
sampler_state_bo); |
} |
drm_intel_bo_unreference(sampler_state_bo); |
} |
} |
} |
} |
drm_intel_bo_unreference(border_color_bo); |
render->cc_state_bo = gen4_create_cc_unit_state(intel); |
LEAVE(); |
} |
/** |
* Called at LeaveVT. |
*/ |
void gen4_render_state_cleanup(ScrnInfoPtr scrn) |
{ |
intel_screen_private *intel = intel_get_screen_private(scrn); |
struct gen4_render_state *render_state = intel->gen4_render_state; |
int i, j, k, l, m; |
drm_intel_bo_unreference(intel->surface_bo); |
drm_intel_bo_unreference(render_state->vs_state_bo); |
drm_intel_bo_unreference(render_state->sf_state_bo); |
drm_intel_bo_unreference(render_state->sf_mask_state_bo); |
for (i = 0; i < KERNEL_COUNT; i++) |
drm_intel_bo_unreference(render_state->wm_kernel_bo[i]); |
for (i = 0; i < FILTER_COUNT; i++) |
for (j = 0; j < EXTEND_COUNT; j++) |
for (k = 0; k < FILTER_COUNT; k++) |
for (l = 0; l < EXTEND_COUNT; l++) |
for (m = 0; m < KERNEL_COUNT; m++) |
drm_intel_bo_unreference |
(render_state-> |
wm_state_bo[m][i][j][k] |
[l]); |
for (i = 0; i < FILTER_COUNT; i++) |
for (j = 0; j < EXTEND_COUNT; j++) |
for (k = 0; k < FILTER_COUNT; k++) |
for (l = 0; l < EXTEND_COUNT; l++) |
drm_intel_bo_unreference(render_state->ps_sampler_state_bo[i][j][k][l]); |
drm_intel_bo_unreference(render_state->cc_state_bo); |
drm_intel_bo_unreference(render_state->cc_vp_bo); |
drm_intel_bo_unreference(render_state->gen6_blend_bo); |
drm_intel_bo_unreference(render_state->gen6_depth_stencil_bo); |
free(intel->gen4_render_state); |
intel->gen4_render_state = NULL; |
} |
/* |
* for GEN6+ |
*/ |
#define GEN6_BLEND_STATE_PADDED_SIZE ALIGN(sizeof(struct gen6_blend_state), 64) |
static drm_intel_bo * |
gen6_composite_create_cc_state(intel_screen_private *intel) |
{ |
struct gen6_color_calc_state *state; |
drm_intel_bo *cc_bo; |
int ret; |
cc_bo = drm_intel_bo_alloc(intel->bufmgr, |
"gen6 CC state", |
sizeof(*state), |
4096); |
assert(cc_bo); |
ret = drm_intel_bo_map(cc_bo, TRUE); |
assert(ret == 0); |
state = memset(cc_bo->virtual, 0, sizeof(*state)); |
state->constant_r = 1.0; |
state->constant_g = 0.0; |
state->constant_b = 1.0; |
state->constant_a = 1.0; |
drm_intel_bo_unmap(cc_bo); |
return cc_bo; |
(void)ret; |
} |
static drm_intel_bo * |
gen6_composite_create_blend_state(intel_screen_private *intel) |
{ |
drm_intel_bo *blend_bo; |
int src, dst, ret; |
blend_bo = drm_intel_bo_alloc(intel->bufmgr, |
"gen6 BLEND state", |
BRW_BLENDFACTOR_COUNT * BRW_BLENDFACTOR_COUNT * GEN6_BLEND_STATE_PADDED_SIZE, |
4096); |
assert(blend_bo); |
ret = drm_intel_bo_map(blend_bo, TRUE); |
assert(ret == 0); |
memset(blend_bo->virtual, 0, blend_bo->size); |
for (src = 0; src < BRW_BLENDFACTOR_COUNT; src++) { |
for (dst = 0; dst < BRW_BLENDFACTOR_COUNT; dst++) { |
uint32_t blend_state_offset = (src * BRW_BLENDFACTOR_COUNT + dst) * GEN6_BLEND_STATE_PADDED_SIZE; |
struct gen6_blend_state *blend; |
blend = (struct gen6_blend_state *)((char *)blend_bo->virtual + blend_state_offset); |
blend->blend0.dest_blend_factor = dst; |
blend->blend0.source_blend_factor = src; |
blend->blend0.blend_func = BRW_BLENDFUNCTION_ADD; |
blend->blend0.blend_enable = 1; |
blend->blend1.post_blend_clamp_enable = 1; |
blend->blend1.pre_blend_clamp_enable = 1; |
} |
} |
drm_intel_bo_unmap(blend_bo); |
return blend_bo; |
(void)ret; |
} |
static drm_intel_bo * |
gen6_composite_create_depth_stencil_state(intel_screen_private *intel) |
{ |
drm_intel_bo *depth_stencil_bo; |
int ret; |
depth_stencil_bo = |
drm_intel_bo_alloc(intel->bufmgr, |
"gen6 DEPTH_STENCIL state", |
sizeof(struct gen6_depth_stencil_state), |
4096); |
assert(depth_stencil_bo); |
ret = drm_intel_bo_map(depth_stencil_bo, TRUE); |
assert(ret == 0); |
memset(depth_stencil_bo->virtual, 0, |
sizeof(struct gen6_depth_stencil_state)); |
drm_intel_bo_unmap(depth_stencil_bo); |
return depth_stencil_bo; |
(void)ret; |
} |
static void |
gen6_composite_state_base_address(intel_screen_private *intel) |
{ |
OUT_BATCH(BRW_STATE_BASE_ADDRESS | (10 - 2)); |
OUT_BATCH(BASE_ADDRESS_MODIFY); /* General state base address */ |
intel->surface_reloc = intel->batch_used; |
intel_batch_emit_dword(intel, |
intel->surface_bo->offset | BASE_ADDRESS_MODIFY); |
OUT_BATCH(BASE_ADDRESS_MODIFY); /* Dynamic state base address */ |
OUT_BATCH(BASE_ADDRESS_MODIFY); /* Indirect object base address */ |
OUT_BATCH(BASE_ADDRESS_MODIFY); /* Instruction base address */ |
OUT_BATCH(BASE_ADDRESS_MODIFY); /* General state upper bound */ |
OUT_BATCH(BASE_ADDRESS_MODIFY); /* Dynamic state upper bound */ |
OUT_BATCH(BASE_ADDRESS_MODIFY); /* Indirect object upper bound */ |
OUT_BATCH(BASE_ADDRESS_MODIFY); /* Instruction access upper bound */ |
} |
static void |
gen6_composite_cc_state_pointers(intel_screen_private *intel, |
uint32_t blend_offset) |
{ |
struct gen4_render_state *render_state = intel->gen4_render_state; |
drm_intel_bo *cc_bo = NULL; |
drm_intel_bo *depth_stencil_bo = NULL; |
if (intel->gen6_render_state.blend == blend_offset) |
return; |
if (intel->gen6_render_state.blend == -1) { |
cc_bo = render_state->cc_state_bo; |
depth_stencil_bo = render_state->gen6_depth_stencil_bo; |
} |
if (INTEL_INFO(intel)->gen >= 070) { |
gen7_upload_cc_state_pointers(intel, render_state->gen6_blend_bo, cc_bo, depth_stencil_bo, blend_offset); |
} else { |
gen6_upload_cc_state_pointers(intel, render_state->gen6_blend_bo, cc_bo, depth_stencil_bo, blend_offset); |
} |
intel->gen6_render_state.blend = blend_offset; |
} |
static void |
gen6_composite_sampler_state_pointers(intel_screen_private *intel, |
drm_intel_bo *bo) |
{ |
if (intel->gen6_render_state.samplers == bo) |
return; |
intel->gen6_render_state.samplers = bo; |
if (INTEL_INFO(intel)->gen >= 070) |
gen7_upload_sampler_state_pointers(intel, bo); |
else |
gen6_upload_sampler_state_pointers(intel, bo); |
} |
static void |
gen6_composite_wm_constants(intel_screen_private *intel) |
{ |
Bool ivb = INTEL_INFO(intel)->gen >= 070; |
/* disable WM constant buffer */ |
OUT_BATCH(GEN6_3DSTATE_CONSTANT_PS | ((ivb ? 7 : 5) - 2)); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
if (ivb) { |
OUT_BATCH(0); |
OUT_BATCH(0); |
} |
} |
static void |
gen6_composite_sf_state(intel_screen_private *intel, |
Bool has_mask) |
{ |
int num_sf_outputs = has_mask ? 2 : 1; |
if (intel->gen6_render_state.num_sf_outputs == num_sf_outputs) |
return; |
intel->gen6_render_state.num_sf_outputs = num_sf_outputs; |
if (INTEL_INFO(intel)->gen >= 070) |
gen7_upload_sf_state(intel, num_sf_outputs, 1); |
else |
gen6_upload_sf_state(intel, num_sf_outputs, 1); |
} |
static void |
gen6_composite_wm_state(intel_screen_private *intel, |
Bool has_mask, |
drm_intel_bo *bo) |
{ |
int num_surfaces = has_mask ? 3 : 2; |
int num_sf_outputs = has_mask ? 2 : 1; |
if (intel->gen6_render_state.kernel == bo) |
return; |
intel->gen6_render_state.kernel = bo; |
OUT_BATCH(GEN6_3DSTATE_WM | (9 - 2)); |
OUT_RELOC(bo, |
I915_GEM_DOMAIN_INSTRUCTION, 0, |
0); |
OUT_BATCH((1 << GEN6_3DSTATE_WM_SAMPLER_COUNT_SHITF) | |
(num_surfaces << GEN6_3DSTATE_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT)); |
OUT_BATCH(0); |
OUT_BATCH((6 << GEN6_3DSTATE_WM_DISPATCH_START_GRF_0_SHIFT)); /* DW4 */ |
OUT_BATCH(((40 - 1) << GEN6_3DSTATE_WM_MAX_THREADS_SHIFT) | |
GEN6_3DSTATE_WM_DISPATCH_ENABLE | |
GEN6_3DSTATE_WM_16_DISPATCH_ENABLE); |
OUT_BATCH((num_sf_outputs << GEN6_3DSTATE_WM_NUM_SF_OUTPUTS_SHIFT) | |
GEN6_3DSTATE_WM_PERSPECTIVE_PIXEL_BARYCENTRIC); |
OUT_BATCH(0); |
OUT_BATCH(0); |
} |
static void |
gen7_composite_wm_state(intel_screen_private *intel, |
Bool has_mask, |
drm_intel_bo *bo) |
{ |
int num_surfaces = has_mask ? 3 : 2; |
unsigned int max_threads_shift = GEN7_PS_MAX_THREADS_SHIFT_IVB; |
unsigned int num_samples = 0; |
if (IS_HSW(intel)) { |
max_threads_shift = GEN7_PS_MAX_THREADS_SHIFT_HSW; |
num_samples = 1 << GEN7_PS_SAMPLE_MASK_SHIFT_HSW; |
} |
if (intel->gen6_render_state.kernel == bo) |
return; |
intel->gen6_render_state.kernel = bo; |
OUT_BATCH(GEN6_3DSTATE_WM | (3 - 2)); |
OUT_BATCH(GEN7_WM_DISPATCH_ENABLE | |
GEN7_WM_PERSPECTIVE_PIXEL_BARYCENTRIC); |
OUT_BATCH(0); |
OUT_BATCH(GEN7_3DSTATE_PS | (8 - 2)); |
OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); |
OUT_BATCH((1 << GEN7_PS_SAMPLER_COUNT_SHIFT) | |
(num_surfaces << GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT)); |
OUT_BATCH(0); /* scratch space base offset */ |
OUT_BATCH(((48 - 1) << max_threads_shift) | num_samples | |
GEN7_PS_ATTRIBUTE_ENABLE | |
GEN7_PS_16_DISPATCH_ENABLE); |
OUT_BATCH((6 << GEN7_PS_DISPATCH_START_GRF_SHIFT_0)); |
OUT_BATCH(0); /* kernel 1 pointer */ |
OUT_BATCH(0); /* kernel 2 pointer */ |
} |
static void |
gen6_composite_drawing_rectangle(intel_screen_private *intel, |
PixmapPtr dest) |
{ |
uint32_t dw = |
DRAW_YMAX(dest->drawable.height - 1) | |
DRAW_XMAX(dest->drawable.width - 1); |
/* XXX cacomposite depends upon the implicit non-pipelined flush */ |
if (0 && intel->gen6_render_state.drawrect == dw) |
return; |
intel->gen6_render_state.drawrect = dw; |
OUT_BATCH(BRW_3DSTATE_DRAWING_RECTANGLE | (4 - 2)); |
OUT_BATCH(0x00000000); /* ymin, xmin */ |
OUT_BATCH(dw); /* ymax, xmax */ |
OUT_BATCH(0x00000000); /* yorigin, xorigin */ |
} |
static void |
gen6_composite_vertex_element_state(intel_screen_private *intel, |
Bool has_mask, |
Bool is_affine) |
{ |
/* |
* vertex data in vertex buffer |
* position: (x, y) |
* texture coordinate 0: (u0, v0) if (is_affine is TRUE) else (u0, v0, w0) |
* texture coordinate 1 if (has_mask is TRUE): same as above |
*/ |
gen4_composite_op *composite_op = &intel->gen4_render_state->composite_op; |
int nelem = has_mask ? 2 : 1; |
int selem = is_affine ? 2 : 3; |
uint32_t w_component; |
uint32_t src_format; |
int id; |
id = has_mask << 1 | is_affine; |
if (composite_op->vertex_id == id) |
return; |
composite_op->vertex_id = id; |
if (is_affine) { |
src_format = BRW_SURFACEFORMAT_R32G32_FLOAT; |
w_component = BRW_VFCOMPONENT_STORE_1_FLT; |
} else { |
src_format = BRW_SURFACEFORMAT_R32G32B32_FLOAT; |
w_component = BRW_VFCOMPONENT_STORE_SRC; |
} |
/* The VUE layout |
* dword 0-3: pad (0.0, 0.0, 0.0. 0.0) |
* dword 4-7: position (x, y, 1.0, 1.0), |
* dword 8-11: texture coordinate 0 (u0, v0, w0, 1.0) |
* dword 12-15: texture coordinate 1 (u1, v1, w1, 1.0) |
* |
* dword 4-15 are fetched from vertex buffer |
*/ |
OUT_BATCH(BRW_3DSTATE_VERTEX_ELEMENTS | |
((2 * (2 + nelem)) + 1 - 2)); |
OUT_BATCH((id << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT) | GEN6_VE0_VALID | |
(BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) | |
(0 << VE0_OFFSET_SHIFT)); |
OUT_BATCH((BRW_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT) | |
(BRW_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT) | |
(BRW_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT) | |
(BRW_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT)); |
/* x,y */ |
OUT_BATCH((id << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT) | GEN6_VE0_VALID | |
(BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) | |
(0 << VE0_OFFSET_SHIFT)); /* offsets vb in bytes */ |
OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) | |
(BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) | |
(BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) | |
(BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT)); |
/* u0, v0, w0 */ |
OUT_BATCH((id << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT) | GEN6_VE0_VALID | |
(src_format << VE0_FORMAT_SHIFT) | |
((2 * 4) << VE0_OFFSET_SHIFT)); /* offset vb in bytes */ |
OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) | |
(BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) | |
(w_component << VE1_VFCOMPONENT_2_SHIFT) | |
(BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT)); |
/* u1, v1, w1 */ |
if (has_mask) { |
OUT_BATCH((id << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT) | |
GEN6_VE0_VALID | |
(src_format << VE0_FORMAT_SHIFT) | |
(((2 + selem) * 4) << VE0_OFFSET_SHIFT)); /* vb offset in bytes */ |
OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) | |
(BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) | |
(w_component << VE1_VFCOMPONENT_2_SHIFT) | |
(BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT)); |
} |
} |
static void |
gen6_emit_composite_state(struct intel_screen_private *intel) |
{ |
struct gen4_render_state *render = intel->gen4_render_state; |
gen4_composite_op *composite_op = &render->composite_op; |
sampler_state_filter_t src_filter = composite_op->src_filter; |
sampler_state_filter_t mask_filter = composite_op->mask_filter; |
sampler_state_extend_t src_extend = composite_op->src_extend; |
sampler_state_extend_t mask_extend = composite_op->mask_extend; |
Bool is_affine = composite_op->is_affine; |
Bool has_mask = intel->render_mask != NULL; |
Bool ivb = INTEL_INFO(intel)->gen >= 070; |
uint32_t src, dst; |
drm_intel_bo *ps_sampler_state_bo = render->ps_sampler_state_bo[src_filter][src_extend][mask_filter][mask_extend]; |
intel->needs_render_state_emit = FALSE; |
if (intel->needs_3d_invariant) { |
gen6_upload_invariant_states(intel); |
if (ivb) { |
gen7_upload_viewport_state_pointers(intel, render->cc_vp_bo); |
gen7_upload_urb(intel); |
gen7_upload_bypass_states(intel); |
gen7_upload_depth_buffer_state(intel); |
} else { |
gen6_upload_invariant_states(intel); |
gen6_upload_viewport_state_pointers(intel, render->cc_vp_bo); |
gen6_upload_urb(intel); |
gen6_upload_gs_state(intel); |
gen6_upload_depth_buffer_state(intel); |
} |
gen6_composite_wm_constants(intel); |
gen6_upload_vs_state(intel); |
gen6_upload_clip_state(intel); |
intel->needs_3d_invariant = FALSE; |
} |
i965_get_blend_cntl(composite_op->op, |
intel->render_mask_picture, |
intel->render_dest_picture->format, |
&src, &dst); |
if (intel->surface_reloc == 0) |
gen6_composite_state_base_address(intel); |
gen6_composite_cc_state_pointers(intel, |
(src * BRW_BLENDFACTOR_COUNT + dst) * GEN6_BLEND_STATE_PADDED_SIZE); |
gen6_composite_sampler_state_pointers(intel, ps_sampler_state_bo); |
gen6_composite_sf_state(intel, has_mask); |
if (ivb) { |
gen7_composite_wm_state(intel, has_mask, |
render->wm_kernel_bo[composite_op->wm_kernel]); |
gen7_upload_binding_table(intel, intel->surface_table); |
} else { |
gen6_composite_wm_state(intel, has_mask, |
render->wm_kernel_bo[composite_op->wm_kernel]); |
gen6_upload_binding_table(intel, intel->surface_table); |
} |
gen6_composite_drawing_rectangle(intel, intel->render_dest); |
gen6_composite_vertex_element_state(intel, has_mask, is_affine); |
} |
static void |
gen6_render_state_init() |
{ |
ENTER(); |
intel_screen_private *intel = intel_get_screen_private(); |
struct gen4_render_state *render; |
sampler_state_filter_t src_filter; |
sampler_state_filter_t mask_filter; |
sampler_state_extend_t src_extend; |
sampler_state_extend_t mask_extend; |
int m; |
drm_intel_bo *border_color_bo; |
const struct wm_kernel_info *wm_kernels; |
render= intel->gen4_render_state; |
render->composite_op.vertex_id = -1; |
intel->gen6_render_state.num_sf_outputs = 0; |
intel->gen6_render_state.samplers = NULL; |
intel->gen6_render_state.blend = -1; |
intel->gen6_render_state.kernel = NULL; |
intel->gen6_render_state.drawrect = -1; |
wm_kernels = IS_GEN7(intel) ? wm_kernels_gen7 : wm_kernels_gen6; |
for (m = 0; m < KERNEL_COUNT; m++) { |
render->wm_kernel_bo[m] = |
intel_bo_alloc_for_data(intel, |
wm_kernels[m].data, |
wm_kernels[m].size, |
"WM kernel gen6/7"); |
} |
border_color_bo = sampler_border_color_create(intel); |
for (src_filter = 0; src_filter < FILTER_COUNT; src_filter++) { |
for (src_extend = 0; src_extend < EXTEND_COUNT; src_extend++) { |
for (mask_filter = 0; mask_filter < FILTER_COUNT; mask_filter++) { |
for (mask_extend = 0; mask_extend < EXTEND_COUNT; mask_extend++) { |
render->ps_sampler_state_bo[src_filter][src_extend][mask_filter][mask_extend] = |
i965_create_sampler_state(intel, |
src_filter, src_extend, |
mask_filter, mask_extend, |
border_color_bo); |
} |
} |
} |
} |
drm_intel_bo_unreference(border_color_bo); |
render->cc_vp_bo = gen4_create_cc_viewport(intel); |
render->cc_state_bo = gen6_composite_create_cc_state(intel); |
render->gen6_blend_bo = gen6_composite_create_blend_state(intel); |
render->gen6_depth_stencil_bo = gen6_composite_create_depth_stencil_state(intel); |
LEAVE(); |
} |
void i965_vertex_flush(struct intel_screen_private *intel) |
{ |
if (intel->vertex_offset) { |
intel->batch_ptr[intel->vertex_offset] = |
intel->vertex_index - intel->vertex_count; |
intel->vertex_offset = 0; |
} |
} |
void i965_batch_flush(struct intel_screen_private *intel) |
{ |
if (intel->surface_used) |
i965_surface_flush(intel); |
} |
#if HAS_DEVPRIVATEKEYREC |
DevPrivateKeyRec uxa_pixmap_index; |
#else |
int uxa_pixmap_index; |
#endif |
#define xFixedToFloat(val) \ |
((float)xFixedToInt(val) + ((float)xFixedFrac(val) / 65536.0)) |
static Bool |
_intel_transform_point(PictTransformPtr transform, |
float x, float y, float result[3]) |
{ |
int j; |
for (j = 0; j < 3; j++) { |
result[j] = (xFixedToFloat(transform->matrix[j][0]) * x + |
xFixedToFloat(transform->matrix[j][1]) * y + |
xFixedToFloat(transform->matrix[j][2])); |
} |
if (!result[2]) |
return FALSE; |
return TRUE; |
} |
/** |
* Returns the floating-point coordinates transformed by the given transform. |
* |
* transform may be null. |
*/ |
Bool |
intel_get_transformed_coordinates(int x, int y, PictTransformPtr transform, |
float *x_out, float *y_out) |
{ |
if (transform == NULL) { |
*x_out = x; |
*y_out = y; |
} else { |
float result[3]; |
if (!_intel_transform_point(transform, |
x, y, |
result)) |
return FALSE; |
*x_out = result[0] / result[2]; |
*y_out = result[1] / result[2]; |
} |
return TRUE; |
} |
/** |
* Returns the un-normalized floating-point coordinates transformed by the given transform. |
* |
* transform may be null. |
*/ |
Bool |
intel_get_transformed_coordinates_3d(int x, int y, PictTransformPtr transform, |
float *x_out, float *y_out, float *w_out) |
{ |
if (transform == NULL) { |
*x_out = x; |
*y_out = y; |
*w_out = 1; |
} else { |
float result[3]; |
if (!_intel_transform_point(transform, |
x, y, |
result)) |
return FALSE; |
*x_out = result[0]; |
*y_out = result[1]; |
*w_out = result[2]; |
} |
return TRUE; |
} |
/** |
* Returns whether the provided transform is affine. |
* |
* transform may be null. |
*/ |
Bool intel_transform_is_affine(PictTransformPtr t) |
{ |
if (t == NULL) |
return TRUE; |
return t->matrix[2][0] == 0 && t->matrix[2][1] == 0; |
} |
/drivers/video/Intel-2D/uxa/intel.h |
---|
0,0 → 1,407 |
/************************************************************************** |
Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas. |
Copyright © 2002 David Dawes |
All Rights Reserved. |
Permission is hereby granted, free of charge, to any person obtaining a |
copy of this software and associated documentation files (the |
"Software"), to deal in the Software without restriction, including |
without limitation the rights to use, copy, modify, merge, publish, |
distribute, sub license, and/or sell copies of the Software, and to |
permit persons to whom the Software is furnished to do so, subject to |
the following conditions: |
The above copyright notice and this permission notice (including the |
next paragraph) shall be included in all copies or substantial portions |
of the Software. |
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR |
ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
**************************************************************************/ |
/* |
* Authors: |
* Keith Whitwell <keith@tungstengraphics.com> |
* David Dawes <dawes@xfree86.org> |
* |
*/ |
#ifdef HAVE_CONFIG_H |
#include "config.h" |
#endif |
#if 0 |
#define I830DEBUG |
#endif |
#include <stdint.h> |
#ifndef REMAP_RESERVED |
#define REMAP_RESERVED 0 |
#endif |
#include "picture.h" |
#include <pciaccess.h> |
#include "intel_bufmgr.h" |
#include "i915_drm.h" |
#include "intel_driver.h" |
#include "intel_list.h" |
# define ENTER() printf("ENTER %s\n", __FUNCTION__) |
# define LEAVE() printf("LEAVE %s\n", __FUNCTION__) |
# define FAIL() printf("FAIL %s\n", __FUNCTION__) |
typedef int ScrnInfoPtr; |
typedef int ScreenPtr; |
typedef int Bool; |
#define TRUE (Bool)(1) |
#define FALSE (Bool)(0) |
typedef struct pixman_transform PictTransform, *PictTransformPtr; |
typedef struct _Pixmap *PixmapPtr; |
typedef struct _Picture *PicturePtr; |
/* remain compatible to xorg-server 1.6 */ |
#ifndef MONITOR_EDID_COMPLETE_RAWDATA |
#define MONITOR_EDID_COMPLETE_RAWDATA EDID_COMPLETE_RAWDATA |
#endif |
#if XF86_CRTC_VERSION >= 5 |
#define INTEL_PIXMAP_SHARING 1 |
#endif |
struct intel_pixmap { |
dri_bo *bo; |
struct list batch; |
uint16_t stride; |
uint8_t tiling; |
int8_t busy :2; |
uint8_t dirty :1; |
uint8_t offscreen :1; |
uint8_t pinned :3; |
#define PIN_SCANOUT 0x1 |
#define PIN_DRI 0x2 |
#define PIN_GLAMOR 0x4 |
}; |
#if HAS_DEVPRIVATEKEYREC |
extern DevPrivateKeyRec uxa_pixmap_index; |
#else |
extern int uxa_pixmap_index; |
#endif |
/* |
static inline struct intel_pixmap *intel_get_pixmap_private(PixmapPtr pixmap) |
{ |
#if HAS_DEVPRIVATEKEYREC |
return dixGetPrivate(&pixmap->devPrivates, &uxa_pixmap_index); |
#else |
return dixLookupPrivate(&pixmap->devPrivates, &uxa_pixmap_index); |
#endif |
} |
*/ |
static inline Bool intel_pixmap_is_busy(struct intel_pixmap *priv) |
{ |
if (priv->busy == -1) |
priv->busy = drm_intel_bo_busy(priv->bo); |
return priv->busy; |
} |
static inline void intel_set_pixmap_private(PixmapPtr pixmap, struct intel_pixmap *intel) |
{ |
dixSetPrivate(&pixmap->devPrivates, &uxa_pixmap_index, intel); |
} |
static inline Bool intel_pixmap_is_dirty(PixmapPtr pixmap) |
{ |
return pixmap && pixmap->private->dirty; |
} |
static inline Bool intel_pixmap_tiled(PixmapPtr pixmap) |
{ |
return pixmap->private->tiling != I915_TILING_NONE; |
} |
dri_bo *intel_get_pixmap_bo(PixmapPtr pixmap); |
void intel_set_pixmap_bo(PixmapPtr pixmap, dri_bo * bo); |
#include "common.h" |
#define PITCH_NONE 0 |
/** enumeration of 3d consumers so some can maintain invariant state. */ |
enum last_3d { |
LAST_3D_OTHER, |
LAST_3D_VIDEO, |
LAST_3D_RENDER, |
LAST_3D_ROTATION |
}; |
enum dri_type { |
DRI_DISABLED, |
DRI_NONE, |
DRI_DRI2 |
}; |
typedef struct intel_screen_private { |
int scrn; |
int cpp; |
#define RENDER_BATCH I915_EXEC_RENDER |
#define BLT_BATCH I915_EXEC_BLT |
unsigned int current_batch; |
void *modes; |
drm_intel_bo *front_buffer, *back_buffer; |
PixmapPtr back_pixmap; |
unsigned int back_name; |
long front_pitch, front_tiling; |
dri_bufmgr *bufmgr; |
uint32_t batch_ptr[4096]; |
/** Byte offset in batch_ptr for the next dword to be emitted. */ |
unsigned int batch_used; |
/** Position in batch_ptr at the start of the current BEGIN_BATCH */ |
unsigned int batch_emit_start; |
/** Number of bytes to be emitted in the current BEGIN_BATCH. */ |
uint32_t batch_emitting; |
dri_bo *batch_bo, *last_batch_bo[2]; |
/** Whether we're in a section of code that can't tolerate flushing */ |
Bool in_batch_atomic; |
/** Ending batch_used that was verified by intel_start_batch_atomic() */ |
int batch_atomic_limit; |
struct list batch_pixmaps; |
drm_intel_bo *wa_scratch_bo; |
unsigned int tiling; |
#define INTEL_TILING_FB 0x1 |
#define INTEL_TILING_2D 0x2 |
#define INTEL_TILING_3D 0x4 |
#define INTEL_TILING_ALL (~0) |
Bool swapbuffers_wait; |
Bool has_relaxed_fencing; |
int Chipset; |
struct pci_device *PciInfo; |
const struct intel_device_info *info; |
unsigned int BR[20]; |
void (*context_switch) (struct intel_screen_private *intel, |
int new_mode); |
void (*vertex_flush) (struct intel_screen_private *intel); |
void (*batch_flush) (struct intel_screen_private *intel); |
void (*batch_commit_notify) (struct intel_screen_private *intel); |
Bool need_sync; |
int accel_pixmap_offset_alignment; |
int accel_max_x; |
int accel_max_y; |
int max_bo_size; |
int max_gtt_map_size; |
int max_tiling_size; |
struct { |
drm_intel_bo *gen4_vs_bo; |
drm_intel_bo *gen4_sf_bo; |
drm_intel_bo *gen4_wm_packed_bo; |
drm_intel_bo *gen4_wm_planar_bo; |
drm_intel_bo *gen4_cc_bo; |
drm_intel_bo *gen4_cc_vp_bo; |
drm_intel_bo *gen4_sampler_bo; |
drm_intel_bo *gen4_sip_kernel_bo; |
drm_intel_bo *wm_prog_packed_bo; |
drm_intel_bo *wm_prog_planar_bo; |
drm_intel_bo *gen6_blend_bo; |
drm_intel_bo *gen6_depth_stencil_bo; |
} video; |
/* Render accel state */ |
float scale_units[2][2]; |
/** Transform pointers for src/mask, or NULL if identity */ |
PictTransform *transform[2]; |
PixmapPtr render_source, render_mask, render_dest; |
PicturePtr render_source_picture, render_mask_picture, render_dest_picture; |
Bool needs_3d_invariant; |
Bool needs_render_state_emit; |
Bool needs_render_vertex_emit; |
/* i830 render accel state */ |
uint32_t render_dest_format; |
uint32_t cblend, ablend, s8_blendctl; |
/* i915 render accel state */ |
PixmapPtr texture[2]; |
uint32_t mapstate[6]; |
uint32_t samplerstate[6]; |
struct { |
int op; |
uint32_t dst_format; |
} i915_render_state; |
struct { |
int num_sf_outputs; |
int drawrect; |
uint32_t blend; |
dri_bo *samplers; |
dri_bo *kernel; |
} gen6_render_state; |
uint32_t prim_offset; |
void (*prim_emit)(struct intel_screen_private *intel, |
int srcX, int srcY, |
int maskX, int maskY, |
int dstX, int dstY, |
int w, int h); |
int floats_per_vertex; |
int last_floats_per_vertex; |
uint16_t vertex_offset; |
uint16_t vertex_count; |
uint16_t vertex_index; |
uint16_t vertex_used; |
uint32_t vertex_id; |
float vertex_ptr[4*1024]; |
dri_bo *vertex_bo; |
uint8_t surface_data[16*1024]; |
uint16_t surface_used; |
uint16_t surface_table; |
uint32_t surface_reloc; |
dri_bo *surface_bo; |
/* 965 render acceleration state */ |
struct gen4_render_state *gen4_render_state; |
Bool use_pageflipping; |
Bool use_triple_buffer; |
Bool force_fallback; |
Bool has_kernel_flush; |
Bool needs_flush; |
enum last_3d last_3d; |
/** |
* User option to print acceleration fallback info to the server log. |
*/ |
Bool fallback_debug; |
unsigned debug_flush; |
Bool has_prime_vmap_flush; |
} intel_screen_private; |
#define INTEL_INFO(intel) ((intel)->info) |
#define IS_GENx(intel, X) (INTEL_INFO(intel)->gen >= 8*(X) && INTEL_INFO(intel)->gen < 8*((X)+1)) |
#define IS_GEN1(intel) IS_GENx(intel, 1) |
#define IS_GEN2(intel) IS_GENx(intel, 2) |
#define IS_GEN3(intel) IS_GENx(intel, 3) |
#define IS_GEN4(intel) IS_GENx(intel, 4) |
#define IS_GEN5(intel) IS_GENx(intel, 5) |
#define IS_GEN6(intel) IS_GENx(intel, 6) |
#define IS_GEN7(intel) IS_GENx(intel, 7) |
#define IS_HSW(intel) (INTEL_INFO(intel)->gen == 075) |
/* Some chips have specific errata (or limits) that we need to workaround. */ |
#define IS_I830(intel) ((intel)->PciInfo->device_id == PCI_CHIP_I830_M) |
#define IS_845G(intel) ((intel)->PciInfo->device_id == PCI_CHIP_845_G) |
#define IS_I865G(intel) ((intel)->PciInfo->device_id == PCI_CHIP_I865_G) |
#define IS_I915G(pI810) ((intel)->PciInfo->device_id == PCI_CHIP_I915_G || (intel)->PciInfo->device_id == PCI_CHIP_E7221_G) |
#define IS_I915GM(pI810) ((intel)->PciInfo->device_id == PCI_CHIP_I915_GM) |
#define IS_965_Q(pI810) ((intel)->PciInfo->device_id == PCI_CHIP_I965_Q) |
/* supports Y tiled surfaces (pre-965 Mesa isn't ready yet) */ |
#define SUPPORTS_YTILING(pI810) (INTEL_INFO(intel)->gen >= 040) |
#define HAS_BLT(pI810) (INTEL_INFO(intel)->gen >= 060) |
#ifndef I915_PARAM_HAS_PRIME_VMAP_FLUSH |
#define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21 |
#endif |
enum { |
DEBUG_FLUSH_BATCHES = 0x1, |
DEBUG_FLUSH_CACHES = 0x2, |
DEBUG_FLUSH_WAIT = 0x4, |
}; |
extern intel_screen_private *driverPrivate; |
static inline intel_screen_private * |
intel_get_screen_private() |
{ |
return driverPrivate; |
} |
#ifndef ARRAY_SIZE |
#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0])) |
#endif |
#ifndef ALIGN |
#define ALIGN(i,m) (((i) + (m) - 1) & ~((m) - 1)) |
#endif |
#ifndef MIN |
#define MIN(a,b) ((a) < (b) ? (a) : (b)) |
#endif |
static inline unsigned long intel_pixmap_pitch(PixmapPtr pixmap) |
{ |
return (unsigned long)pixmap->devKind; |
} |
/* Batchbuffer support macros and functions */ |
#include "intel_batchbuffer.h" |
void i965_vertex_flush(intel_screen_private *intel); |
void i965_batch_flush(intel_screen_private *intel); |
void i965_batch_commit_notify(intel_screen_private *intel); |
/** |
* Little wrapper around drm_intel_bo_reloc to return the initial value you |
* should stuff into the relocation entry. |
* |
* If only we'd done this before settling on the library API. |
*/ |
static inline uint32_t |
intel_emit_reloc(drm_intel_bo * bo, uint32_t offset, |
drm_intel_bo * target_bo, uint32_t target_offset, |
uint32_t read_domains, uint32_t write_domain) |
{ |
drm_intel_bo_emit_reloc(bo, offset, target_bo, target_offset, |
read_domains, write_domain); |
return target_bo->offset + target_offset; |
} |
static inline drm_intel_bo *intel_bo_alloc_for_data(intel_screen_private *intel, |
const void *data, |
unsigned int size, |
const char *name) |
{ |
drm_intel_bo *bo; |
int ret; |
bo = drm_intel_bo_alloc(intel->bufmgr, name, size, 4096); |
assert(bo); |
ret = drm_intel_bo_subdata(bo, 0, size, data); |
assert(ret == 0); |
return bo; |
(void)ret; |
} |
/drivers/video/Intel-2D/uxa/intel_batchbuffer.c |
---|
0,0 → 1,317 |
/* -*- c-basic-offset: 4 -*- */ |
/* |
* Copyright © 2006 Intel Corporation |
* |
* Permission is hereby granted, free of charge, to any person obtaining a |
* copy of this software and associated documentation files (the "Software"), |
* to deal in the Software without restriction, including without limitation |
* the rights to use, copy, modify, merge, publish, distribute, sublicense, |
* and/or sell copies of the Software, and to permit persons to whom the |
* Software is furnished to do so, subject to the following conditions: |
* |
* The above copyright notice and this permission notice (including the next |
* paragraph) shall be included in all copies or substantial portions of the |
* Software. |
* |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
* SOFTWARE. |
* |
* Authors: |
* Eric Anholt <eric@anholt.net> |
* |
*/ |
#ifdef HAVE_CONFIG_H |
#include "config.h" |
#endif |
#include <assert.h> |
#include <stdlib.h> |
#include <errno.h> |
#include <memory.h> |
//#include "xf86.h" |
#include "intel.h" |
#include "i830_reg.h" |
#include "i915_drm.h" |
#include "i965_reg.h" |
//#include "uxa.h" |
#define DUMP_BATCHBUFFERS NULL // "/tmp/i915-batchbuffers.dump" |
static void intel_end_vertex(intel_screen_private *intel) |
{ |
if (intel->vertex_bo) { |
if (intel->vertex_used) { |
dri_bo_subdata(intel->vertex_bo, 0, intel->vertex_used*4, intel->vertex_ptr); |
intel->vertex_used = 0; |
} |
dri_bo_unreference(intel->vertex_bo); |
intel->vertex_bo = NULL; |
} |
intel->vertex_id = 0; |
} |
void intel_next_vertex(intel_screen_private *intel) |
{ |
intel_end_vertex(intel); |
intel->vertex_bo = |
dri_bo_alloc(intel->bufmgr, "vertex", sizeof (intel->vertex_ptr), 4096); |
} |
static dri_bo *bo_alloc() |
{ |
intel_screen_private *intel = intel_get_screen_private(); |
int size = 4 * 4096; |
/* The 865 has issues with larger-than-page-sized batch buffers. */ |
if (IS_I865G(intel)) |
size = 4096; |
return dri_bo_alloc(intel->bufmgr, "batch", size, 4096); |
} |
static void intel_next_batch(int mode) |
{ |
intel_screen_private *intel = intel_get_screen_private(); |
dri_bo *tmp; |
drm_intel_gem_bo_clear_relocs(intel->batch_bo, 0); |
tmp = intel->last_batch_bo[mode]; |
intel->last_batch_bo[mode] = intel->batch_bo; |
intel->batch_bo = tmp; |
intel->batch_used = 0; |
/* We don't know when another client has executed, so we have |
* to reinitialize our 3D state per batch. |
*/ |
intel->last_3d = LAST_3D_OTHER; |
} |
void intel_batch_init() |
{ |
intel_screen_private *intel = intel_get_screen_private(); |
ENTER(); |
intel->batch_emit_start = 0; |
intel->batch_emitting = 0; |
intel->vertex_id = 0; |
intel->last_batch_bo[0] = bo_alloc(); |
intel->last_batch_bo[1] = bo_alloc(); |
intel->batch_bo = bo_alloc(); |
intel->batch_used = 0; |
intel->last_3d = LAST_3D_OTHER; |
LEAVE(); |
} |
void intel_batch_teardown() |
{ |
intel_screen_private *intel = intel_get_screen_private(); |
int i; |
for (i = 0; i < ARRAY_SIZE(intel->last_batch_bo); i++) { |
if (intel->last_batch_bo[i] != NULL) { |
dri_bo_unreference(intel->last_batch_bo[i]); |
intel->last_batch_bo[i] = NULL; |
} |
} |
if (intel->batch_bo != NULL) { |
dri_bo_unreference(intel->batch_bo); |
intel->batch_bo = NULL; |
} |
if (intel->vertex_bo) { |
dri_bo_unreference(intel->vertex_bo); |
intel->vertex_bo = NULL; |
} |
while (!list_is_empty(&intel->batch_pixmaps)) |
list_del(intel->batch_pixmaps.next); |
} |
static void intel_batch_do_flush() |
{ |
intel_screen_private *intel = intel_get_screen_private(); |
struct intel_pixmap *priv; |
list_for_each_entry(priv, &intel->batch_pixmaps, batch) |
priv->dirty = 0; |
} |
static void intel_emit_post_sync_nonzero_flush() |
{ |
intel_screen_private *intel = intel_get_screen_private(); |
/* keep this entire sequence of 3 PIPE_CONTROL cmds in one batch to |
* avoid upsetting the gpu. */ |
BEGIN_BATCH(3*4); |
OUT_BATCH(BRW_PIPE_CONTROL | (4 - 2)); |
OUT_BATCH(BRW_PIPE_CONTROL_CS_STALL | |
BRW_PIPE_CONTROL_STALL_AT_SCOREBOARD); |
OUT_BATCH(0); /* address */ |
OUT_BATCH(0); /* write data */ |
OUT_BATCH(BRW_PIPE_CONTROL | (4 - 2)); |
OUT_BATCH(BRW_PIPE_CONTROL_WRITE_QWORD); |
OUT_RELOC(intel->wa_scratch_bo, |
I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0); |
OUT_BATCH(0); /* write data */ |
/* now finally the _real flush */ |
OUT_BATCH(BRW_PIPE_CONTROL | (4 - 2)); |
OUT_BATCH(BRW_PIPE_CONTROL_WC_FLUSH | |
BRW_PIPE_CONTROL_TC_FLUSH | |
BRW_PIPE_CONTROL_NOWRITE); |
OUT_BATCH(0); /* write address */ |
OUT_BATCH(0); /* write data */ |
ADVANCE_BATCH(); |
} |
void intel_batch_emit_flush() |
{ |
intel_screen_private *intel = intel_get_screen_private(); |
int flags; |
assert (!intel->in_batch_atomic); |
/* Big hammer, look to the pipelined flushes in future. */ |
if ((INTEL_INFO(intel)->gen >= 060)) { |
if (intel->current_batch == BLT_BATCH) { |
BEGIN_BATCH_BLT(4); |
OUT_BATCH(MI_FLUSH_DW | 2); |
OUT_BATCH(0); |
OUT_BATCH(0); |
OUT_BATCH(0); |
ADVANCE_BATCH(); |
} else { |
if ((INTEL_INFO(intel)->gen == 060)) { |
/* HW-Workaround for Sandybdrige */ |
intel_emit_post_sync_nonzero_flush(); |
} else { |
BEGIN_BATCH(4); |
OUT_BATCH(BRW_PIPE_CONTROL | (4 - 2)); |
OUT_BATCH(BRW_PIPE_CONTROL_WC_FLUSH | |
BRW_PIPE_CONTROL_TC_FLUSH | |
BRW_PIPE_CONTROL_NOWRITE); |
OUT_BATCH(0); /* write address */ |
OUT_BATCH(0); /* write data */ |
ADVANCE_BATCH(); |
} |
} |
} else { |
flags = MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE; |
if (INTEL_INFO(intel)->gen >= 040) |
flags = 0; |
BEGIN_BATCH(1); |
OUT_BATCH(MI_FLUSH | flags); |
ADVANCE_BATCH(); |
} |
intel_batch_do_flush(); |
} |
void intel_batch_submit() |
{ |
intel_screen_private *intel = intel_get_screen_private(); |
int ret; |
assert (!intel->in_batch_atomic); |
if (intel->vertex_flush) |
intel->vertex_flush(intel); |
intel_end_vertex(intel); |
if (intel->batch_flush) |
intel->batch_flush(intel); |
if (intel->batch_used == 0) |
return; |
/* Mark the end of the batchbuffer. */ |
OUT_BATCH(MI_BATCH_BUFFER_END); |
/* Emit a padding dword if we aren't going to be quad-word aligned. */ |
if (intel->batch_used & 1) |
OUT_BATCH(MI_NOOP); |
if (DUMP_BATCHBUFFERS) { |
FILE *file = fopen(DUMP_BATCHBUFFERS, "a"); |
if (file) { |
fwrite (intel->batch_ptr, intel->batch_used*4, 1, file); |
fclose(file); |
} |
} |
ret = dri_bo_subdata(intel->batch_bo, 0, intel->batch_used*4, intel->batch_ptr); |
if (ret == 0) { |
ret = drm_intel_bo_mrb_exec(intel->batch_bo, |
intel->batch_used*4, |
NULL, 0, 0xffffffff, |
(HAS_BLT(intel) ? |
intel->current_batch: |
I915_EXEC_DEFAULT)); |
} |
if (ret != 0) { |
static int once; |
if (!once) { |
if (ret == -EIO) { |
/* The GPU has hung and unlikely to recover by this point. */ |
printf("Detected a hung GPU, disabling acceleration.\n"); |
printf("When reporting this, please include i915_error_state from debugfs and the full dmesg.\n"); |
} else { |
/* The driver is broken. */ |
printf("Failed to submit batch buffer, expect rendering corruption\n "); |
} |
// uxa_set_force_fallback(xf86ScrnToScreen(scrn), TRUE); |
intel->force_fallback = TRUE; |
once = 1; |
} |
} |
while (!list_is_empty(&intel->batch_pixmaps)) { |
struct intel_pixmap *entry; |
entry = list_first_entry(&intel->batch_pixmaps, |
struct intel_pixmap, |
batch); |
entry->busy = -1; |
entry->dirty = 0; |
list_del(&entry->batch); |
} |
if (intel->debug_flush & DEBUG_FLUSH_WAIT) |
drm_intel_bo_wait_rendering(intel->batch_bo); |
intel_next_batch(intel->current_batch == I915_EXEC_BLT); |
if (intel->batch_commit_notify) |
intel->batch_commit_notify(intel); |
intel->current_batch = 0; |
} |
void intel_debug_flush() |
{ |
intel_screen_private *intel = intel_get_screen_private(); |
if (intel->debug_flush & DEBUG_FLUSH_CACHES) |
intel_batch_emit_flush(); |
if (intel->debug_flush & DEBUG_FLUSH_BATCHES) |
intel_batch_submit(); |
} |
/drivers/video/Intel-2D/uxa/intel_batchbuffer.h |
---|
0,0 → 1,226 |
/************************************************************************** |
Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas. |
Copyright © 2002 David Dawes |
All Rights Reserved. |
Permission is hereby granted, free of charge, to any person obtaining a |
copy of this software and associated documentation files (the |
"Software"), to deal in the Software without restriction, including |
without limitation the rights to use, copy, modify, merge, publish, |
distribute, sub license, and/or sell copies of the Software, and to |
permit persons to whom the Software is furnished to do so, subject to |
the following conditions: |
The above copyright notice and this permission notice (including the |
next paragraph) shall be included in all copies or substantial portions |
of the Software. |
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR |
ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
**************************************************************************/ |
#ifndef _INTEL_BATCHBUFFER_H |
#define _INTEL_BATCHBUFFER_H |
#define BATCH_RESERVED 16 |
void intel_batch_init(); |
void intel_batch_teardown(); |
void intel_batch_emit_flush(); |
void intel_batch_submit(); |
static inline int intel_batch_space(intel_screen_private *intel) |
{ |
return (intel->batch_bo->size - BATCH_RESERVED) - (4*intel->batch_used); |
} |
static inline int intel_vertex_space(intel_screen_private *intel) |
{ |
return intel->vertex_bo ? intel->vertex_bo->size - (4*intel->vertex_used) : 0; |
} |
static inline void |
intel_batch_require_space(intel_screen_private *intel, int sz) |
{ |
assert(sz < intel->batch_bo->size - 8); |
if (intel_batch_space(intel) < sz) |
intel_batch_submit(); |
} |
static inline void intel_batch_start_atomic(int sz) |
{ |
intel_screen_private *intel = intel_get_screen_private(); |
assert(!intel->in_batch_atomic); |
if (intel->current_batch != RENDER_BATCH) { |
if (intel->current_batch && intel->context_switch) |
intel->context_switch(intel, RENDER_BATCH); |
} |
intel_batch_require_space(intel, sz * 4); |
intel->current_batch = RENDER_BATCH; |
intel->in_batch_atomic = TRUE; |
intel->batch_atomic_limit = intel->batch_used + sz; |
} |
static inline void intel_batch_end_atomic() |
{ |
intel_screen_private *intel = intel_get_screen_private(); |
assert(intel->in_batch_atomic); |
assert(intel->batch_used <= intel->batch_atomic_limit); |
intel->in_batch_atomic = FALSE; |
} |
static inline void intel_batch_emit_dword(intel_screen_private *intel, uint32_t dword) |
{ |
intel->batch_ptr[intel->batch_used++] = dword; |
} |
static inline void intel_batch_align(intel_screen_private *intel, uint32_t align) |
{ |
uint32_t delta; |
align /= 4; |
assert(align); |
if ((delta = intel->batch_used & (align - 1))) { |
delta = align - delta; |
memset (intel->batch_ptr + intel->batch_used, 0, 4*delta); |
intel->batch_used += delta; |
} |
} |
static inline void |
intel_batch_emit_reloc(intel_screen_private *intel, |
dri_bo * bo, |
uint32_t read_domains, |
uint32_t write_domains, uint32_t delta, int needs_fence) |
{ |
if (needs_fence) |
drm_intel_bo_emit_reloc_fence(intel->batch_bo, |
intel->batch_used * 4, |
bo, delta, |
read_domains, write_domains); |
else |
drm_intel_bo_emit_reloc(intel->batch_bo, intel->batch_used * 4, |
bo, delta, |
read_domains, write_domains); |
intel_batch_emit_dword(intel, bo->offset + delta); |
} |
static inline void |
intel_batch_mark_pixmap_domains(intel_screen_private *intel, |
struct intel_pixmap *priv, |
uint32_t read_domains, uint32_t write_domain) |
{ |
assert (read_domains); |
assert (write_domain == 0 || write_domain == read_domains); |
if (list_is_empty(&priv->batch)) |
list_add(&priv->batch, &intel->batch_pixmaps); |
priv->dirty |= write_domain != 0; |
priv->busy = 1; |
intel->needs_flush |= write_domain != 0; |
} |
static inline void |
intel_batch_emit_reloc_pixmap(intel_screen_private *intel, PixmapPtr pixmap, |
uint32_t read_domains, uint32_t write_domain, |
uint32_t delta, int needs_fence) |
{ |
struct intel_pixmap *priv = pixmap->private; |
intel_batch_mark_pixmap_domains(intel, priv, read_domains, write_domain); |
intel_batch_emit_reloc(intel, priv->bo, |
read_domains, write_domain, |
delta, needs_fence); |
} |
#define ALIGN_BATCH(align) intel_batch_align(intel, align); |
#define OUT_BATCH(dword) intel_batch_emit_dword(intel, dword) |
#define OUT_RELOC(bo, read_domains, write_domains, delta) \ |
intel_batch_emit_reloc(intel, bo, read_domains, write_domains, delta, 0) |
#define OUT_RELOC_FENCED(bo, read_domains, write_domains, delta) \ |
intel_batch_emit_reloc(intel, bo, read_domains, write_domains, delta, 1) |
#define OUT_RELOC_PIXMAP(pixmap, reads, write, delta) \ |
intel_batch_emit_reloc_pixmap(intel, pixmap, reads, write, delta, 0) |
#define OUT_RELOC_PIXMAP_FENCED(pixmap, reads, write, delta) \ |
intel_batch_emit_reloc_pixmap(intel, pixmap, reads, write, delta, 1) |
union intfloat { |
float f; |
unsigned int ui; |
}; |
#define OUT_BATCH_F(x) do { \ |
union intfloat tmp; \ |
tmp.f = (float)(x); \ |
OUT_BATCH(tmp.ui); \ |
} while(0) |
#define __BEGIN_BATCH(n,batch_idx) \ |
do { \ |
if (intel->batch_emitting != 0) \ |
printf("%s: BEGIN_BATCH called without closing " \ |
"ADVANCE_BATCH\n", __FUNCTION__); \ |
assert(!intel->in_batch_atomic); \ |
if (intel->current_batch != batch_idx) { \ |
if (intel->current_batch && intel->context_switch) \ |
intel->context_switch(intel, batch_idx); \ |
} \ |
intel_batch_require_space(intel, (n) * 4); \ |
intel->current_batch = batch_idx; \ |
intel->batch_emitting = (n); \ |
intel->batch_emit_start = intel->batch_used; \ |
} while (0) |
#define BEGIN_BATCH(n) __BEGIN_BATCH(n,RENDER_BATCH) |
#define BEGIN_BATCH_BLT(n) __BEGIN_BATCH(n,BLT_BATCH) |
#define ADVANCE_BATCH() do { \ |
if (intel->batch_emitting == 0) \ |
printf("%s: ADVANCE_BATCH called with no matching " \ |
"BEGIN_BATCH\n", __FUNCTION__); \ |
if (intel->batch_used > \ |
intel->batch_emit_start + intel->batch_emitting) \ |
printf("%s: ADVANCE_BATCH: exceeded allocation %d/%d\n ", \ |
__FUNCTION__, \ |
intel->batch_used - intel->batch_emit_start, \ |
intel->batch_emitting); \ |
if (intel->batch_used < intel->batch_emit_start + \ |
intel->batch_emitting) \ |
printf("%s: ADVANCE_BATCH: under-used allocation %d/%d\n ", \ |
__FUNCTION__, \ |
intel->batch_used - intel->batch_emit_start, \ |
intel->batch_emitting); \ |
intel->batch_emitting = 0; \ |
} while (0) |
void intel_next_vertex(intel_screen_private *intel); |
static inline void intel_vertex_emit(intel_screen_private *intel, float v) |
{ |
intel->vertex_ptr[intel->vertex_used++] = v; |
} |
#define OUT_VERTEX(v) intel_vertex_emit(intel, v) |
#endif /* _INTEL_BATCHBUFFER_H */ |
/drivers/video/Intel-2D/uxa/uxa.c |
---|
0,0 → 1,570 |
#include <assert.h> |
#include <stdlib.h> |
#include <memory.h> |
#include <intel_bufmgr.h> |
//#include "xf86.h" |
#include "uxa/intel.h" |
#include "i830_reg.h" |
#include "i965_reg.h" |
/* bring in brw structs */ |
#include "brw_defines.h" |
#include "brw_structs.h" |
#include "i915_pciids.h" |
#include <pixlib2.h> |
#include <kos32sys.h> |
#define PictOpClear 0 |
#define PictOpSrc 1 |
#define PictOpDst 2 |
#define PictOpOver 3 |
#define PictOpOverReverse 4 |
#define PictOpIn 5 |
#define PictOpInReverse 6 |
#define PictOpOut 7 |
#define PictOpOutReverse 8 |
#define PictOpAtop 9 |
#define PictOpAtopReverse 10 |
#define PictOpXor 11 |
#define PictOpAdd 12 |
#define PictOpSaturate 13 |
#define PictOpMaximum 13 |
static int tls_mask; |
intel_screen_private *driverPrivate; |
__LOCK_INIT_RECURSIVE(, __uxa_lock); |
#define DBG printf |
typedef struct |
{ |
struct list entry; |
uint32_t width; |
uint32_t height; |
void *data; |
uint32_t pitch; |
drm_intel_bo *bo; |
uint32_t bo_size; |
uint32_t flags; |
}surface_t; |
#define to_surface(x) (surface_t*)((x)->handle) |
struct _Pixmap fb_pixmap; |
struct list sf_list; |
int uxa_update_fb(struct intel_screen_private *intel); |
int sna_create_mask() |
{ |
return 0; |
}; |
static void i830_done_composite(PixmapPtr dest) |
{ |
intel_screen_private *intel = intel_get_screen_private(); |
if (intel->vertex_flush) |
intel->vertex_flush(intel); |
// intel_debug_flush(scrn); |
} |
int sna_bitmap_from_handle(bitmap_t *bitmap, uint32_t handle) |
{ |
struct intel_screen_private *intel = intel_get_screen_private(); |
drm_intel_bo *bo; |
surface_t *sf; |
unsigned int size; |
bitmap->handle = 0; |
__lock_acquire_recursive(__uxa_lock); |
list_for_each_entry(sf, &sf_list, entry) |
{ |
if (sf->bo->handle == handle) |
{ |
bitmap->handle = (uint32_t)sf; |
break; |
} |
} |
__lock_release_recursive(__uxa_lock); |
if(bitmap->handle) |
return 0; |
sf = malloc(sizeof(*sf)); |
if(sf == NULL) |
goto err_1; |
size = bitmap->pitch * bitmap->height; |
bo = bo_create_from_gem_handle(intel->bufmgr, size, handle); |
sf->width = bitmap->width; |
sf->height = bitmap->height; |
sf->data = NULL; |
sf->pitch = bitmap->pitch; |
sf->bo = bo; |
sf->bo_size = size; |
sf->flags = bitmap->flags; |
bitmap->handle = (uint32_t)sf; |
return 0; |
err_1: |
return -1; |
}; |
void sna_set_bo_handle(bitmap_t *bitmap, int handle) |
{ |
sna_bitmap_from_handle(bitmap, handle); |
}; |
int sna_blit_tex(bitmap_t *bitmap, bool scale, int dst_x, int dst_y, |
int w, int h, int src_x, int src_y) |
{ |
struct _Pixmap pixSrc, pixMask; |
struct intel_pixmap privSrc; |
struct _Picture pictSrc, pictDst; |
struct intel_screen_private *intel = intel_get_screen_private(); |
surface_t *sf = to_surface(bitmap); |
int winx, winy; |
char proc_info[1024]; |
get_proc_info(proc_info); |
winx = *(uint32_t*)(proc_info+34); |
winy = *(uint32_t*)(proc_info+38); |
memset(&pixSrc, 0, sizeof(pixSrc)); |
memset(&pixMask, 0, sizeof(pixMask)); |
memset(&privSrc, 0, sizeof(pixSrc)); |
memset(&pictSrc, 0, sizeof(pictSrc)); |
memset(&pictDst, 0, sizeof(pictDst)); |
pixSrc.drawable.bitsPerPixel = 32; |
pixSrc.drawable.width = sf->width; |
pixSrc.drawable.height = sf->height; |
pixSrc.devKind = sf->pitch; |
pixSrc.private = &privSrc; |
list_init(&privSrc.batch); |
privSrc.bo = sf->bo; |
privSrc.stride = sf->pitch; |
privSrc.tiling = I915_TILING_X; |
pictSrc.format = PICT_x8r8g8b8; |
pictSrc.filter = PictFilterNearest; |
pictSrc.repeatType = RepeatNone; |
pictDst.format = PICT_a8r8g8b8; |
pictDst.filter = PictFilterNearest; |
pictDst.repeatType = RepeatNone; |
uxa_update_fb(intel); |
// pixDst.drawable.bitsPerPixel = 32; |
// pixDst.drawable.width = sna_fb.width; |
// pixDst.drawable.height = sna_fb.height; |
// pixMask.drawable.bitsPerPixel = 8; |
// pixMask.drawable.width = update.width; |
// pixMask.drawable.height = update.height; |
i965_prepare_composite(PictOpSrc, &pictSrc, NULL, &pictDst, |
&pixSrc, NULL, &fb_pixmap); |
i965_composite(&fb_pixmap, src_x, src_y, 0, 0, |
dst_x, dst_y, w, h); |
i830_done_composite(&fb_pixmap); |
intel_batch_submit(); |
return 0; |
}; |
int uxa_init_fb(struct intel_screen_private *intel) |
{ |
struct drm_i915_fb_info fb; |
static struct intel_pixmap ipix; |
int ret; |
memset(&fb, 0, sizeof(fb)); |
ret = drmIoctl(intel->scrn, SRV_FBINFO, &fb); |
if( ret != 0 ) |
return ret; |
intel->front_buffer = intel_bo_gem_create_from_name(intel->bufmgr,"frontbuffer", fb.name); |
if(intel->front_buffer == NULL) |
return -1; |
ipix.bo = intel->front_buffer; |
list_init(&ipix.batch); |
ipix.stride = fb.pitch; |
ipix.tiling = fb.tiling; |
ipix.pinned = PIN_SCANOUT; |
printf("create frontbuffer name %d bo %x\n", fb.name, ipix.bo); |
printf("size %d, offset %d handle %d\n",ipix.bo->size, ipix.bo->offset, ipix.bo->handle); |
fb_pixmap.drawable.bitsPerPixel = 32; |
fb_pixmap.drawable.width = fb.width; |
fb_pixmap.drawable.height = fb.height; |
fb_pixmap.devKind = fb.pitch; |
fb_pixmap.private = &ipix; |
return 0; |
} |
int uxa_update_fb(struct intel_screen_private *intel) |
{ |
struct drm_i915_fb_info fb; |
struct intel_pixmap *ipix; |
size_t size; |
int ret; |
ret = drmIoctl(intel->scrn, SRV_FBINFO, &fb); |
if( ret != 0 ) |
return ret; |
ipix = (struct intel_pixmap*)fb_pixmap.private; |
ipix->stride = fb.pitch; |
ipix->tiling = fb.tiling; |
fb_pixmap.drawable.width = fb.width; |
fb_pixmap.drawable.height = fb.height; |
fb_pixmap.devKind = fb.pitch; |
return 0; |
}; |
int uxa_init(uint32_t service) |
{ |
static struct pci_device device; |
struct intel_screen_private *intel = intel_get_screen_private(); |
ioctl_t io; |
int caps = 0; |
DBG("%s\n", __FUNCTION__); |
__lock_acquire_recursive(__uxa_lock); |
if(intel) |
goto done; |
io.handle = service; |
io.io_code = SRV_GET_PCI_INFO; |
io.input = &device; |
io.inp_size = sizeof(device); |
io.output = NULL; |
io.out_size = 0; |
if (call_service(&io)!=0) |
goto err1; |
intel = (intel_screen_private*)malloc(sizeof(*intel)); |
if (intel == NULL) |
goto err1; |
list_init(&sf_list); |
driverPrivate = intel; |
memset(intel, 0, sizeof(*intel)); |
// sna->cpu_features = sna_cpu_detect(); |
intel->PciInfo = &device; |
intel->info = intel_detect_chipset(intel->PciInfo); |
intel->scrn = service; |
intel->bufmgr = intel_bufmgr_gem_init(service, 8192); |
if(intel->bufmgr == NULL) |
{ |
printf("Memory manager initialization failed\n"); |
goto err1; |
}; |
if( uxa_init_fb(intel) != 0) |
goto err1; |
intel_batch_init(); |
if (INTEL_INFO(intel)->gen >= 040) |
gen4_render_state_init(); |
if (!intel_uxa_init()) { |
printf("Hardware acceleration initialization failed\n"); |
goto err1; |
} |
tls_mask = tls_alloc(); |
// printf("tls mask %x\n", tls_mask); |
done: |
// caps = sna_device->render.caps; |
err1: |
__lock_release_recursive(__uxa_lock); |
LEAVE(); |
return caps; |
} |
static void |
gen6_context_switch(intel_screen_private *intel, |
int new_mode) |
{ |
intel_batch_submit(intel->scrn); |
} |
static void |
gen5_context_switch(intel_screen_private *intel, |
int new_mode) |
{ |
/* Ironlake has a limitation that a 3D or Media command can't |
* be the first command after a BLT, unless it's |
* non-pipelined. Instead of trying to track it and emit a |
* command at the right time, we just emit a dummy |
* non-pipelined 3D instruction after each blit. |
*/ |
if (new_mode == I915_EXEC_BLT) { |
OUT_BATCH(MI_FLUSH | |
MI_STATE_INSTRUCTION_CACHE_FLUSH | |
MI_INHIBIT_RENDER_CACHE_FLUSH); |
} else { |
OUT_BATCH(CMD_POLY_STIPPLE_OFFSET << 16); |
OUT_BATCH(0); |
} |
} |
static void |
gen4_context_switch(intel_screen_private *intel, |
int new_mode) |
{ |
if (new_mode == I915_EXEC_BLT) { |
OUT_BATCH(MI_FLUSH | |
MI_STATE_INSTRUCTION_CACHE_FLUSH | |
MI_INHIBIT_RENDER_CACHE_FLUSH); |
} |
} |
static void |
intel_limits_init(intel_screen_private *intel) |
{ |
/* Limits are described in the BLT engine chapter under Graphics Data Size |
* Limitations, and the descriptions of SURFACE_STATE, 3DSTATE_BUFFER_INFO, |
* 3DSTATE_DRAWING_RECTANGLE, 3DSTATE_MAP_INFO, and 3DSTATE_MAP_INFO. |
* |
* i845 through i965 limits 2D rendering to 65536 lines and pitch of 32768. |
* |
* i965 limits 3D surface to (2*element size)-aligned offset if un-tiled. |
* i965 limits 3D surface to 4kB-aligned offset if tiled. |
* i965 limits 3D surfaces to w,h of ?,8192. |
* i965 limits 3D surface to pitch of 1B - 128kB. |
* i965 limits 3D surface pitch alignment to 1 or 2 times the element size. |
* i965 limits 3D surface pitch alignment to 512B if tiled. |
* i965 limits 3D destination drawing rect to w,h of 8192,8192. |
* |
* i915 limits 3D textures to 4B-aligned offset if un-tiled. |
* i915 limits 3D textures to ~4kB-aligned offset if tiled. |
* i915 limits 3D textures to width,height of 2048,2048. |
* i915 limits 3D textures to pitch of 16B - 8kB, in dwords. |
* i915 limits 3D destination to ~4kB-aligned offset if tiled. |
* i915 limits 3D destination to pitch of 16B - 8kB, in dwords, if un-tiled. |
* i915 limits 3D destination to pitch 64B-aligned if used with depth. |
* i915 limits 3D destination to pitch of 512B - 8kB, in tiles, if tiled. |
* i915 limits 3D destination to POT aligned pitch if tiled. |
* i915 limits 3D destination drawing rect to w,h of 2048,2048. |
* |
* i845 limits 3D textures to 4B-aligned offset if un-tiled. |
* i845 limits 3D textures to ~4kB-aligned offset if tiled. |
* i845 limits 3D textures to width,height of 2048,2048. |
* i845 limits 3D textures to pitch of 4B - 8kB, in dwords. |
* i845 limits 3D destination to 4B-aligned offset if un-tiled. |
* i845 limits 3D destination to ~4kB-aligned offset if tiled. |
* i845 limits 3D destination to pitch of 8B - 8kB, in dwords. |
* i845 limits 3D destination drawing rect to w,h of 2048,2048. |
* |
* For the tiled issues, the only tiled buffer we draw to should be |
* the front, which will have an appropriate pitch/offset already set up, |
* so UXA doesn't need to worry. |
*/ |
if (INTEL_INFO(intel)->gen >= 040) { |
intel->accel_pixmap_offset_alignment = 4 * 2; |
intel->accel_max_x = 8192; |
intel->accel_max_y = 8192; |
} else { |
intel->accel_pixmap_offset_alignment = 4; |
intel->accel_max_x = 2048; |
intel->accel_max_y = 2048; |
} |
} |
Bool intel_uxa_init() |
{ |
intel_screen_private *intel = intel_get_screen_private(); |
intel_limits_init(intel); |
intel->prim_offset = 0; |
intel->vertex_count = 0; |
intel->vertex_offset = 0; |
intel->vertex_used = 0; |
intel->floats_per_vertex = 0; |
intel->last_floats_per_vertex = 0; |
intel->vertex_bo = NULL; |
intel->surface_used = 0; |
intel->surface_reloc = 0; |
/* |
intel->uxa_driver->check_composite = i965_check_composite; |
intel->uxa_driver->check_composite_texture = i965_check_composite_texture; |
intel->uxa_driver->prepare_composite = i965_prepare_composite; |
intel->uxa_driver->composite = i965_composite; |
intel->uxa_driver->done_composite = i830_done_composite; |
*/ |
intel->vertex_flush = i965_vertex_flush; |
intel->batch_flush = i965_batch_flush; |
intel->batch_commit_notify = i965_batch_commit_notify; |
if (IS_GEN4(intel)) { |
intel->context_switch = gen4_context_switch; |
} else if (IS_GEN5(intel)) { |
intel->context_switch = gen5_context_switch; |
} else { |
intel->context_switch = gen6_context_switch; |
} |
return TRUE; |
} |
static const struct intel_device_info intel_generic_info = { |
.gen = -1, |
}; |
static const struct intel_device_info intel_i915_info = { |
.gen = 030, |
}; |
static const struct intel_device_info intel_i945_info = { |
.gen = 031, |
}; |
static const struct intel_device_info intel_g33_info = { |
.gen = 033, |
}; |
static const struct intel_device_info intel_i965_info = { |
.gen = 040, |
}; |
static const struct intel_device_info intel_g4x_info = { |
.gen = 045, |
}; |
static const struct intel_device_info intel_ironlake_info = { |
.gen = 050, |
}; |
static const struct intel_device_info intel_sandybridge_info = { |
.gen = 060, |
}; |
static const struct intel_device_info intel_ivybridge_info = { |
.gen = 070, |
}; |
static const struct intel_device_info intel_valleyview_info = { |
.gen = 071, |
}; |
static const struct intel_device_info intel_haswell_info = { |
.gen = 075, |
}; |
#define INTEL_DEVICE_MATCH(d,i) \ |
{ 0x8086, (d), PCI_MATCH_ANY, PCI_MATCH_ANY, 0x3 << 16, 0xff << 16, (intptr_t)(i) } |
static const struct pci_id_match intel_device_match[] = { |
INTEL_I915G_IDS(&intel_i915_info), |
INTEL_I915GM_IDS(&intel_i915_info), |
INTEL_I945G_IDS(&intel_i945_info), |
INTEL_I945GM_IDS(&intel_i945_info), |
INTEL_G33_IDS(&intel_g33_info), |
INTEL_PINEVIEW_IDS(&intel_g33_info), |
INTEL_I965G_IDS(&intel_i965_info), |
INTEL_I965GM_IDS(&intel_i965_info), |
INTEL_G45_IDS(&intel_g4x_info), |
INTEL_GM45_IDS(&intel_g4x_info), |
INTEL_IRONLAKE_D_IDS(&intel_ironlake_info), |
INTEL_IRONLAKE_M_IDS(&intel_ironlake_info), |
INTEL_SNB_D_IDS(&intel_sandybridge_info), |
INTEL_SNB_M_IDS(&intel_sandybridge_info), |
INTEL_IVB_D_IDS(&intel_ivybridge_info), |
INTEL_IVB_M_IDS(&intel_ivybridge_info), |
INTEL_HSW_D_IDS(&intel_haswell_info), |
INTEL_HSW_M_IDS(&intel_haswell_info), |
INTEL_VLV_D_IDS(&intel_valleyview_info), |
INTEL_VLV_M_IDS(&intel_valleyview_info), |
INTEL_VGA_DEVICE(PCI_MATCH_ANY, &intel_generic_info), |
{ 0, 0, 0 }, |
}; |
const struct pci_id_match *PciDevMatch(uint16_t dev,const struct pci_id_match *list) |
{ |
while(list->device_id) |
{ |
if(dev==list->device_id) |
return list; |
list++; |
} |
return NULL; |
} |
const struct intel_device_info * |
intel_detect_chipset(struct pci_device *pci) |
{ |
const struct pci_id_match *ent = NULL; |
ent = PciDevMatch(pci->device_id, intel_device_match); |
if(ent != NULL) |
return (const struct intel_device_info*)ent->match_data; |
else |
return &intel_generic_info; |
} |