/drivers/include/errno-base.h |
---|
File deleted |
/drivers/include/ddk.h |
---|
4,7 → 4,10 |
#define __DDK_H__ |
#include <kernel.h> |
#include <linux/errno.h> |
#include <linux/spinlock.h> |
#include <mutex.h> |
#include <linux/pci.h> |
#define OS_BASE 0x80000000 |
56,7 → 59,24 |
u32_t drvEntry(int, char *)__asm__("_drvEntry"); |
#define __WARN() dbgprintf(__FILE__, __LINE__) |
#ifndef WARN_ON |
#define WARN_ON(condition) ({ \ |
int __ret_warn_on = !!(condition); \ |
if (unlikely(__ret_warn_on)) \ |
__WARN(); \ |
unlikely(__ret_warn_on); \ |
}) |
#endif |
static inline void *kmalloc_array(size_t n, size_t size, gfp_t flags) |
{ |
// if (size != 0 && n > SIZE_MAX / size) |
// return NULL; |
return kmalloc(n * size, flags); |
} |
#endif /* DDK_H */ |
/drivers/include/drm/drmP.hh |
---|
File deleted |
/drivers/include/drm/drmP.h |
---|
36,15 → 36,22 |
#define _DRM_P_H_ |
#ifdef __KERNEL__ |
#ifdef __alpha__ |
/* add include of current.h so that "current" is defined |
* before static inline funcs in wait.h. Doing this so we |
* can build the DRM (part of PI DRI). 4/21/2000 S + B */ |
#include <asm/current.h> |
#endif /* __alpha__ */ |
#include <syscall.h> |
#include <linux/module.h> |
#include <linux/kernel.h> |
#include <linux/export.h> |
#include <linux/errno.h> |
#include <linux/kref.h> |
#include <linux/spinlock.h> |
#include <linux/wait.h> |
#include <linux/bug.h> |
//#include <linux/miscdevice.h> |
//#include <linux/fs.h> |
72,25 → 79,15 |
#define __OS_HAS_AGP (defined(CONFIG_AGP) || (defined(CONFIG_AGP_MODULE) && defined(MODULE))) |
#define __OS_HAS_MTRR (defined(CONFIG_MTRR)) |
struct module; |
#include <drm_edid.h> |
#include <drm_crtc.h> |
struct drm_file; |
struct drm_device; |
//#include "drm_os_linux.h" |
#include "drm_hashtab.h" |
#include "drm_mm.h" |
//#include <drm/drm_os_linux.h> |
#include <drm/drm_hashtab.h> |
#include <drm/drm_mm.h> |
#define DRM_UT_CORE 0x01 |
#define DRM_UT_DRIVER 0x02 |
#define DRM_UT_KMS 0x04 |
#define DRM_UT_MODE 0x08 |
#define KHZ2PICOS(a) (1000000000UL/(a)) |
/* get_scanout_position() return flags */ |
99,45 → 96,51 |
#define DRM_SCANOUTPOS_ACCURATE (1 << 2) |
extern void drm_ut_debug_printk(unsigned int request_level, |
#define DRM_UT_CORE 0x01 |
#define DRM_UT_DRIVER 0x02 |
#define DRM_UT_KMS 0x04 |
#define DRM_UT_PRIME 0x08 |
/* |
* Three debug levels are defined. |
* drm_core, drm_driver, drm_kms |
* drm_core level can be used in the generic drm code. For example: |
* drm_ioctl, drm_mm, drm_memory |
* The macro definition of DRM_DEBUG is used. |
* DRM_DEBUG(fmt, args...) |
* The debug info by using the DRM_DEBUG can be obtained by adding |
* the boot option of "drm.debug=1". |
* |
* drm_driver level can be used in the specific drm driver. It is used |
* to add the debug info related with the drm driver. For example: |
* i915_drv, i915_dma, i915_gem, radeon_drv, |
* The macro definition of DRM_DEBUG_DRIVER can be used. |
* DRM_DEBUG_DRIVER(fmt, args...) |
* The debug info by using the DRM_DEBUG_DRIVER can be obtained by |
* adding the boot option of "drm.debug=0x02" |
* |
* drm_kms level can be used in the KMS code related with specific drm driver. |
* It is used to add the debug info related with KMS mode. For example: |
* the connector/crtc , |
* The macro definition of DRM_DEBUG_KMS can be used. |
* DRM_DEBUG_KMS(fmt, args...) |
* The debug info by using the DRM_DEBUG_KMS can be obtained by |
* adding the boot option of "drm.debug=0x04" |
* |
* If we add the boot option of "drm.debug=0x06", we can get the debug info by |
* using the DRM_DEBUG_KMS and DRM_DEBUG_DRIVER. |
* If we add the boot option of "drm.debug=0x05", we can get the debug info by |
* using the DRM_DEBUG_KMS and DRM_DEBUG. |
*/ |
extern __printf(4, 5) |
void drm_ut_debug_printk(unsigned int request_level, |
const char *prefix, |
const char *function_name, |
const char *format, ...); |
extern __printf(2, 3) |
int drm_err(const char *func, const char *format, ...); |
#define DRM_DEBUG_MODE(prefix, fmt, args...) \ |
do { \ |
dbgprintf("drm debug: %s" fmt, \ |
__func__, ##args); \ |
} while (0) |
#define DRM_DEBUG(fmt, args...) \ |
do { \ |
printk("[" DRM_NAME ":%s] " fmt , __func__ , ##args); \ |
} while(0) |
#define DRM_DEBUG_KMS(fmt, args...) \ |
do { \ |
printk("[" DRM_NAME ":%s] " fmt , __func__ , ##args); \ |
} while(0) |
#define DRM_DEBUG_DRIVER(fmt, args...) \ |
do { \ |
printk("[" DRM_NAME ":%s] " fmt , __func__ , ##args); \ |
} while (0) |
#define DRM_LOG_KMS(fmt, args...) \ |
do { \ |
printk("[" DRM_NAME "]" fmt, ##args); \ |
} while (0) |
static inline int drm_sysfs_connector_add(struct drm_connector *connector) |
{ return 0; }; |
static inline void drm_sysfs_connector_remove(struct drm_connector *connector) |
{ }; |
#if 0 |
/***********************************************************************/ |
/** \name DRM template customization defaults */ |
/*@{*/ |
157,6 → 160,7 |
#define DRIVER_IRQ_VBL2 0x800 |
#define DRIVER_GEM 0x1000 |
#define DRIVER_MODESET 0x2000 |
#define DRIVER_PRIME 0x4000 |
#define DRIVER_BUS_PCI 0x1 |
#define DRIVER_BUS_PLATFORM 0x2 |
193,22 → 197,12 |
* \param fmt printf() like format string. |
* \param arg arguments |
*/ |
#define DRM_ERROR(fmt, arg...) \ |
printk(KERN_ERR "[" DRM_NAME ":%s] *ERROR* " fmt , __func__ , ##arg) |
#define DRM_ERROR(fmt, ...) \ |
drm_err(__func__, fmt, ##__VA_ARGS__) |
/** |
* Memory error output. |
* |
* \param area memory area where the error occurred. |
* \param fmt printf() like format string. |
* \param arg arguments |
*/ |
#define DRM_MEM_ERROR(area, fmt, arg...) \ |
printk(KERN_ERR "[" DRM_NAME ":%s:%s] *ERROR* " fmt , __func__, \ |
drm_mem_stats[area].name , ##arg) |
#define DRM_INFO(fmt, ...) \ |
printk(KERN_INFO "[" DRM_NAME "] " fmt, ##__VA_ARGS__) |
#define DRM_INFO(fmt, arg...) printk(KERN_INFO "[" DRM_NAME "] " fmt , ##arg) |
/** |
* Debug output. |
* |
216,45 → 210,43 |
* \param arg arguments |
*/ |
#if DRM_DEBUG_CODE |
#define DRM_DEBUG(fmt, args...) \ |
#define DRM_DEBUG(fmt, ...) \ |
do { \ |
drm_ut_debug_printk(DRM_UT_CORE, DRM_NAME, \ |
__func__, fmt, ##args); \ |
printk(KERN_INFO "[" DRM_NAME "] " fmt, ##__VA_ARGS__); \ |
} while (0) |
#define DRM_DEBUG_DRIVER(fmt, args...) \ |
#define DRM_DEBUG_DRIVER(fmt, ...) \ |
do { \ |
drm_ut_debug_printk(DRM_UT_DRIVER, DRM_NAME, \ |
__func__, fmt, ##args); \ |
printk(KERN_INFO "[" DRM_NAME "] " fmt, ##__VA_ARGS__); \ |
} while (0) |
#define DRM_DEBUG_KMS(fmt, args...) \ |
#define DRM_DEBUG_KMS(fmt, ...) \ |
do { \ |
drm_ut_debug_printk(DRM_UT_KMS, DRM_NAME, \ |
__func__, fmt, ##args); \ |
printk(KERN_INFO "[" DRM_NAME "] " fmt, ##__VA_ARGS__); \ |
} while (0) |
#define DRM_LOG(fmt, args...) \ |
#define DRM_DEBUG_PRIME(fmt, ...) \ |
do { \ |
drm_ut_debug_printk(DRM_UT_CORE, NULL, \ |
NULL, fmt, ##args); \ |
printk(KERN_INFO "[" DRM_NAME "] " fmt, ##__VA_ARGS__); \ |
} while (0) |
#define DRM_LOG_KMS(fmt, args...) \ |
#define DRM_LOG(fmt, ...) \ |
do { \ |
drm_ut_debug_printk(DRM_UT_KMS, NULL, \ |
NULL, fmt, ##args); \ |
printk(KERN_INFO "[" DRM_NAME "] " fmt, ##__VA_ARGS__); \ |
} while (0) |
#define DRM_LOG_MODE(fmt, args...) \ |
#define DRM_LOG_KMS(fmt, ...) \ |
do { \ |
drm_ut_debug_printk(DRM_UT_MODE, NULL, \ |
NULL, fmt, ##args); \ |
printk(KERN_INFO "[" DRM_NAME "] " fmt, ##__VA_ARGS__); \ |
} while (0) |
#define DRM_LOG_DRIVER(fmt, args...) \ |
#define DRM_LOG_MODE(fmt, ...) \ |
do { \ |
drm_ut_debug_printk(DRM_UT_DRIVER, NULL, \ |
NULL, fmt, ##args); \ |
printk(KERN_INFO "[" DRM_NAME "] " fmt, ##__VA_ARGS__); \ |
} while (0) |
#define DRM_LOG_DRIVER(fmt, ...) \ |
do { \ |
printk(KERN_INFO "[" DRM_NAME "] " fmt, ##__VA_ARGS__); \ |
} while (0) |
#else |
#define DRM_DEBUG_DRIVER(fmt, args...) do { } while (0) |
#define DRM_DEBUG_KMS(fmt, args...) do { } while (0) |
#define DRM_DEBUG_PRIME(fmt, args...) do { } while (0) |
#define DRM_DEBUG(fmt, arg...) do { } while (0) |
#define DRM_LOG(fmt, arg...) do { } while (0) |
#define DRM_LOG_KMS(fmt, args...) do { } while (0) |
293,6 → 285,7 |
} \ |
} while (0) |
#if 0 |
/** |
* Ioctl function type. |
* |
357,7 → 350,6 |
struct drm_buf *next; /**< Kernel-only: used for free list */ |
__volatile__ int waiting; /**< On kernel DMA queue */ |
__volatile__ int pending; /**< On hardware DMA queue */ |
wait_queue_head_t dma_wait; /**< Processes waiting */ |
struct drm_file *file_priv; /**< Private of holding file descr */ |
int context; /**< Kernel queue for this buffer */ |
int while_locked; /**< Dispatch this buffer while locked */ |
429,11 → 421,17 |
void (*destroy)(struct drm_pending_event *event); |
}; |
/* initial implementaton using a linked list - todo hashtab */ |
struct drm_prime_file_private { |
struct list_head head; |
struct mutex lock; |
}; |
/** File private data */ |
struct drm_file { |
int authenticated; |
pid_t pid; |
uid_t uid; |
struct pid *pid; |
kuid_t uid; |
drm_magic_t magic; |
unsigned long ioctl_count; |
struct list_head lhead; |
456,6 → 454,8 |
wait_queue_head_t event_wait; |
struct list_head event_list; |
int event_space; |
struct drm_prime_file_private prime; |
}; |
/** Wait queue */ |
677,7 → 677,7 |
void *driver_private; |
}; |
#include "drm_crtc.h" |
#include <drm/drm_crtc.h> |
/* per-master structure */ |
struct drm_master { |
758,11 → 758,11 |
* @dev: DRM device |
* @crtc: counter to fetch |
* |
* Driver callback for fetching a raw hardware vblank counter |
* for @crtc. If a device doesn't have a hardware counter, the |
* driver can simply return the value of drm_vblank_count and |
* make the enable_vblank() and disable_vblank() hooks into no-ops, |
* leaving interrupts enabled at all times. |
* Driver callback for fetching a raw hardware vblank counter for @crtc. |
* If a device doesn't have a hardware counter, the driver can simply |
* return the value of drm_vblank_count. The DRM core will account for |
* missed vblank events while interrupts where disabled based on system |
* timestamps. |
* |
* Wraparound handling and loss of events due to modesetting is dealt |
* with in the DRM core code. |
879,12 → 879,6 |
void (*irq_preinstall) (struct drm_device *dev); |
int (*irq_postinstall) (struct drm_device *dev); |
void (*irq_uninstall) (struct drm_device *dev); |
void (*reclaim_buffers) (struct drm_device *dev, |
struct drm_file * file_priv); |
void (*reclaim_buffers_locked) (struct drm_device *dev, |
struct drm_file *file_priv); |
void (*reclaim_buffers_idlelocked) (struct drm_device *dev, |
struct drm_file *file_priv); |
void (*set_version) (struct drm_device *dev, |
struct drm_set_version *sv); |
915,6 → 909,20 |
int (*gem_open_object) (struct drm_gem_object *, struct drm_file *); |
void (*gem_close_object) (struct drm_gem_object *, struct drm_file *); |
/* prime: */ |
/* export handle -> fd (see drm_gem_prime_handle_to_fd() helper) */ |
int (*prime_handle_to_fd)(struct drm_device *dev, struct drm_file *file_priv, |
uint32_t handle, uint32_t flags, int *prime_fd); |
/* import fd -> handle (see drm_gem_prime_fd_to_handle() helper) */ |
int (*prime_fd_to_handle)(struct drm_device *dev, struct drm_file *file_priv, |
int prime_fd, uint32_t *handle); |
/* export GEM -> dmabuf */ |
struct dma_buf * (*gem_prime_export)(struct drm_device *dev, |
struct drm_gem_object *obj, int flags); |
/* import dmabuf -> GEM */ |
struct drm_gem_object * (*gem_prime_import)(struct drm_device *dev, |
struct dma_buf *dma_buf); |
/* vga arb irq handler */ |
void (*vgaarb_irq)(struct drm_device *dev, bool state); |
930,7 → 938,7 |
uint32_t handle); |
/* Driver private ops for this object */ |
struct vm_operations_struct *gem_vm_ops; |
const struct vm_operations_struct *gem_vm_ops; |
int major; |
int minor; |
1092,12 → 1100,8 |
/*@} */ |
/** \name DMA queues (contexts) */ |
/** \name DMA support */ |
/*@{ */ |
int queue_count; /**< Number of active DMA queues */ |
int queue_reserved; /**< Number of reserved DMA queues */ |
int queue_slots; /**< Actual length of queuelist */ |
// struct drm_queue **queuelist; /**< Vector of pointers to DMA queues */ |
// struct drm_device_dma *dma; /**< Optional pointer for DMA support */ |
/*@} */ |
1182,6 → 1186,8 |
struct idr object_name_idr; |
/*@} */ |
int switch_power_state; |
atomic_t unplugged; /* device has been unplugged or gone away */ |
}; |
#define DRM_SWITCH_POWER_ON 0 |
1272,17 → 1278,12 |
/* Mapping support (drm_vm.h) */ |
extern int drm_mmap(struct file *filp, struct vm_area_struct *vma); |
extern int drm_mmap_locked(struct file *filp, struct vm_area_struct *vma); |
extern void drm_vm_open_locked(struct vm_area_struct *vma); |
extern void drm_vm_close_locked(struct vm_area_struct *vma); |
extern void drm_vm_open_locked(struct drm_device *dev, struct vm_area_struct *vma); |
extern void drm_vm_close_locked(struct drm_device *dev, struct vm_area_struct *vma); |
extern unsigned int drm_poll(struct file *filp, struct poll_table_struct *wait); |
/* Memory management support (drm_memory.h) */ |
#include "drm_memory.h" |
extern void drm_mem_init(void); |
extern int drm_mem_info(char *buf, char **start, off_t offset, |
int request, int *eof, void *data); |
extern void *drm_realloc(void *oldpt, size_t oldsize, size_t size, int area); |
#include <drm/drm_memory.h> |
extern void drm_free_agp(DRM_AGP_MEM * handle, int pages); |
extern int drm_bind_agp(DRM_AGP_MEM * handle, unsigned int start); |
extern DRM_AGP_MEM *drm_agp_bind_pages(struct drm_device *dev, |
1346,6 → 1347,8 |
/* Cache management (drm_cache.c) */ |
void drm_clflush_pages(struct page *pages[], unsigned long num_pages); |
void drm_clflush_sg(struct sg_table *st); |
void drm_clflush_virt_range(char *addr, unsigned long length); |
/* Locking IOCTL support (drm_lock.h) */ |
extern int drm_lock(struct drm_device *dev, void *data, |
1397,12 → 1400,8 |
/* IRQ support (drm_irq.h) */ |
extern int drm_control(struct drm_device *dev, void *data, |
struct drm_file *file_priv); |
extern irqreturn_t drm_irq_handler(DRM_IRQ_ARGS); |
extern int drm_irq_install(struct drm_device *dev); |
extern int drm_irq_uninstall(struct drm_device *dev); |
extern void drm_driver_irq_preinstall(struct drm_device *dev); |
extern void drm_driver_irq_postinstall(struct drm_device *dev); |
extern void drm_driver_irq_uninstall(struct drm_device *dev); |
extern int drm_vblank_init(struct drm_device *dev, int num_crtcs); |
extern int drm_wait_vblank(struct drm_device *dev, void *data, |
1478,8 → 1477,12 |
extern void drm_put_dev(struct drm_device *dev); |
extern int drm_put_minor(struct drm_minor **minor); |
extern void drm_unplug_dev(struct drm_device *dev); |
#endif |
extern unsigned int drm_debug; |
#if 0 |
extern unsigned int drm_vblank_offdelay; |
extern unsigned int drm_timestamp_precision; |
1510,7 → 1513,6 |
/* Info file support */ |
extern int drm_name_info(struct seq_file *m, void *data); |
extern int drm_vm_info(struct seq_file *m, void *data); |
extern int drm_queues_info(struct seq_file *m, void *data); |
extern int drm_bufs_info(struct seq_file *m, void *data); |
extern int drm_vblank_info(struct seq_file *m, void *data); |
extern int drm_clients_info(struct seq_file *m, void* data); |
1533,6 → 1535,7 |
struct drm_ati_pcigart_info * gart_info); |
extern int drm_ati_pcigart_cleanup(struct drm_device *dev, |
struct drm_ati_pcigart_info * gart_info); |
#endif |
extern drm_dma_handle_t *drm_pci_alloc(struct drm_device *dev, size_t size, |
size_t align); |
1539,6 → 1542,7 |
extern void __drm_pci_free(struct drm_device *dev, drm_dma_handle_t * dmah); |
extern void drm_pci_free(struct drm_device *dev, drm_dma_handle_t * dmah); |
#if 0 |
/* sysfs support (drm_sysfs.c) */ |
struct drm_sysfs_class; |
extern struct class *drm_sysfs_create(struct module *owner, char *name); |
1680,6 → 1684,7 |
} |
static __inline__ void *drm_calloc_large(size_t nmemb, size_t size) |
{ |
if (size * nmemb <= PAGE_SIZE) |
1702,7 → 1707,12 |
#endif |
#define DRM_PCIE_SPEED_25 1 |
#define DRM_PCIE_SPEED_50 2 |
#define DRM_PCIE_SPEED_80 4 |
extern int drm_pcie_get_speed_cap_mask(struct drm_device *dev, u32 *speed_mask); |
static __inline__ int drm_device_is_agp(struct drm_device *dev) |
{ |
return pci_find_capability(dev->pdev, PCI_CAP_ID_AGP); |
1713,4 → 1723,8 |
return pci_find_capability(dev->pdev, PCI_CAP_ID_EXP); |
} |
#endif /* __KERNEL__ */ |
#define drm_sysfs_connector_add(connector) |
#define drm_sysfs_connector_remove(connector) |
#endif |
/drivers/include/drm/drm_crtc.h |
---|
30,6 → 30,7 |
#include <linux/types.h> |
#include <linux/idr.h> |
#include <linux/fb.h> |
#include <drm/drm_mode.h> |
#include <drm/drm_fourcc.h> |
36,6 → 37,7 |
struct drm_device; |
struct drm_mode_set; |
struct drm_framebuffer; |
struct drm_object_properties; |
#define DRM_MODE_OBJECT_CRTC 0xcccccccc |
50,8 → 52,16 |
struct drm_mode_object { |
uint32_t id; |
uint32_t type; |
struct drm_object_properties *properties; |
}; |
#define DRM_OBJECT_MAX_PROPERTY 24 |
struct drm_object_properties { |
int count; |
uint32_t ids[DRM_OBJECT_MAX_PROPERTY]; |
uint64_t values[DRM_OBJECT_MAX_PROPERTY]; |
}; |
/* |
* Note on terminology: here, for brevity and convenience, we refer to connector |
* control chips as 'CRTCs'. They can control any type of connector, VGA, LVDS, |
109,7 → 119,8 |
.hdisplay = (hd), .hsync_start = (hss), .hsync_end = (hse), \ |
.htotal = (ht), .hskew = (hsk), .vdisplay = (vd), \ |
.vsync_start = (vss), .vsync_end = (vse), .vtotal = (vt), \ |
.vscan = (vs), .flags = (f), .vrefresh = 0 |
.vscan = (vs), .flags = (f), .vrefresh = 0, \ |
.base.type = DRM_MODE_OBJECT_MODE |
#define CRTC_INTERLACE_HALVE_V 0x1 /* halve V values for interlacing */ |
121,7 → 132,7 |
char name[DRM_DISPLAY_MODE_LEN]; |
enum drm_mode_status status; |
int type; |
unsigned int type; |
/* Proposed mode values */ |
int clock; /* in kHz */ |
157,8 → 168,6 |
int crtc_vsync_start; |
int crtc_vsync_end; |
int crtc_vtotal; |
int crtc_hadjusted; |
int crtc_vadjusted; |
/* Driver private mode info */ |
int private_size; |
207,11 → 216,10 |
u32 color_formats; |
u8 cea_rev; |
char *raw_edid; /* if any */ |
}; |
struct drm_framebuffer_funcs { |
/* note: use drm_framebuffer_remove() */ |
void (*destroy)(struct drm_framebuffer *framebuffer); |
int (*create_handle)(struct drm_framebuffer *fb, |
struct drm_file *file_priv, |
257,7 → 265,7 |
struct drm_mode_object base; |
struct list_head head; |
unsigned int length; |
void *data; |
unsigned char data[]; |
}; |
struct drm_property_enum { |
285,19 → 293,16 |
/** |
* drm_crtc_funcs - control CRTCs for a given device |
* @save: save CRTC state |
* @restore: restore CRTC state |
* @reset: reset CRTC after state has been invalidate (e.g. resume) |
* @dpms: control display power levels |
* @save: save CRTC state |
* @resore: restore CRTC state |
* @lock: lock the CRTC |
* @unlock: unlock the CRTC |
* @shadow_allocate: allocate shadow pixmap |
* @shadow_create: create shadow pixmap for rotation support |
* @shadow_destroy: free shadow pixmap |
* @mode_fixup: fixup proposed mode |
* @mode_set: set the desired mode on the CRTC |
* @cursor_set: setup the cursor |
* @cursor_move: move the cursor |
* @gamma_set: specify color ramp for CRTC |
* @destroy: deinit and free object. |
* @destroy: deinit and free object |
* @set_property: called when a property is changed |
* @set_config: apply a new CRTC configuration |
* @page_flip: initiate a page flip |
* |
* The drm_crtc_funcs structure is the central CRTC management structure |
* in the DRM. Each CRTC controls one or more connectors (note that the name |
341,6 → 346,9 |
int (*page_flip)(struct drm_crtc *crtc, |
struct drm_framebuffer *fb, |
struct drm_pending_vblank_event *event); |
int (*set_property)(struct drm_crtc *crtc, |
struct drm_property *property, uint64_t val); |
}; |
/** |
351,6 → 359,9 |
* @enabled: is this CRTC enabled? |
* @mode: current mode timings |
* @hwmode: mode timings as programmed to hw regs |
* @invert_dimensions: for purposes of error checking crtc vs fb sizes, |
* invert the width/height of the crtc. This is used if the driver |
* is performing 90 or 270 degree rotated scanout |
* @x: x position on screen |
* @y: y position on screen |
* @funcs: CRTC control functions |
360,6 → 371,7 |
* @framedur_ns: precise line timing |
* @pixeldur_ns: precise pixel timing |
* @helper_private: mid-layer private data |
* @properties: property tracking for this CRTC |
* |
* Each CRTC may have one or more connectors associated with it. This structure |
* allows the CRTC to be controlled. |
383,6 → 395,8 |
*/ |
struct drm_display_mode hwmode; |
bool invert_dimensions; |
int x, y; |
const struct drm_crtc_funcs *funcs; |
395,6 → 409,8 |
/* if you are using the helper */ |
void *helper_private; |
struct drm_object_properties properties; |
}; |
404,11 → 420,8 |
* @save: save connector state |
* @restore: restore connector state |
* @reset: reset connector after state has been invalidate (e.g. resume) |
* @mode_valid: is this mode valid on the given connector? |
* @mode_fixup: try to fixup proposed mode for this connector |
* @mode_set: set this mode |
* @detect: is this connector active? |
* @get_modes: get mode list for this connector |
* @fill_modes: fill mode list for this connector |
* @set_property: property for this connector may need update |
* @destroy: make object go away |
* @force: notify the driver the connector is forced on |
451,7 → 464,6 |
}; |
#define DRM_CONNECTOR_MAX_UMODES 16 |
#define DRM_CONNECTOR_MAX_PROPERTY 16 |
#define DRM_CONNECTOR_LEN 32 |
#define DRM_CONNECTOR_MAX_ENCODER 3 |
520,8 → 532,7 |
* @funcs: connector control functions |
* @user_modes: user added mode list |
* @edid_blob_ptr: DRM property containing EDID if present |
* @property_ids: property tracking for this connector |
* @property_values: value pointers or data for properties |
* @properties: property tracking for this connector |
* @polled: a %DRM_CONNECTOR_POLL_<foo> value for core driven polling |
* @dpms: current dpms state |
* @helper_private: mid-layer private data |
565,8 → 576,7 |
struct list_head user_modes; |
struct drm_property_blob *edid_blob_ptr; |
u32 property_ids[DRM_CONNECTOR_MAX_PROPERTY]; |
uint64_t property_values[DRM_CONNECTOR_MAX_PROPERTY]; |
struct drm_object_properties properties; |
uint8_t polled; /* DRM_CONNECTOR_POLL_* */ |
588,6 → 598,7 |
int video_latency[2]; /* [0]: progressive, [1]: interlaced */ |
int audio_latency[2]; |
int null_edid_counter; /* needed to workaround some HW bugs where we get all 0s */ |
unsigned bad_edid_counter; |
}; |
/** |
595,6 → 606,7 |
* @update_plane: update the plane configuration |
* @disable_plane: shut down the plane |
* @destroy: clean up plane resources |
* @set_property: called when a property is changed |
*/ |
struct drm_plane_funcs { |
int (*update_plane)(struct drm_plane *plane, |
605,6 → 617,9 |
uint32_t src_w, uint32_t src_h); |
int (*disable_plane)(struct drm_plane *plane); |
void (*destroy)(struct drm_plane *plane); |
int (*set_property)(struct drm_plane *plane, |
struct drm_property *property, uint64_t val); |
}; |
/** |
622,6 → 637,7 |
* @enabled: enabled flag |
* @funcs: helper functions |
* @helper_private: storage for drver layer |
* @properties: property tracking for this plane |
*/ |
struct drm_plane { |
struct drm_device *dev; |
644,6 → 660,8 |
const struct drm_plane_funcs *funcs; |
void *helper_private; |
struct drm_object_properties properties; |
}; |
/** |
663,8 → 681,6 |
* This is used to set modes. |
*/ |
struct drm_mode_set { |
struct list_head head; |
struct drm_framebuffer *fb; |
struct drm_crtc *crtc; |
struct drm_display_mode *mode; |
761,7 → 777,7 |
int min_width, min_height; |
int max_width, max_height; |
struct drm_mode_config_funcs *funcs; |
const struct drm_mode_config_funcs *funcs; |
resource_size_t fb_base; |
/* output poll support */ |
796,6 → 812,9 |
struct drm_property *scaling_mode_property; |
struct drm_property *dithering_mode_property; |
struct drm_property *dirty_info_property; |
/* dumb ioctl parameters */ |
uint32_t preferred_depth, prefer_shadow; |
}; |
#define obj_to_crtc(x) container_of(x, struct drm_crtc, base) |
807,20 → 826,26 |
#define obj_to_blob(x) container_of(x, struct drm_property_blob, base) |
#define obj_to_plane(x) container_of(x, struct drm_plane, base) |
struct drm_prop_enum_list { |
int type; |
char *name; |
}; |
extern void drm_crtc_init(struct drm_device *dev, |
extern int drm_crtc_init(struct drm_device *dev, |
struct drm_crtc *crtc, |
const struct drm_crtc_funcs *funcs); |
extern void drm_crtc_cleanup(struct drm_crtc *crtc); |
extern void drm_connector_init(struct drm_device *dev, |
extern int drm_connector_init(struct drm_device *dev, |
struct drm_connector *connector, |
const struct drm_connector_funcs *funcs, |
int connector_type); |
extern void drm_connector_cleanup(struct drm_connector *connector); |
/* helper to unplug all connectors from sysfs for device */ |
extern void drm_connector_unplug_all(struct drm_device *dev); |
extern void drm_encoder_init(struct drm_device *dev, |
extern int drm_encoder_init(struct drm_device *dev, |
struct drm_encoder *encoder, |
const struct drm_encoder_funcs *funcs, |
int encoder_type); |
843,11 → 868,13 |
extern char *drm_get_tv_select_name(int val); |
extern void drm_fb_release(struct drm_file *file_priv); |
extern int drm_mode_group_init_legacy_group(struct drm_device *dev, struct drm_mode_group *group); |
extern bool drm_probe_ddc(struct i2c_adapter *adapter); |
extern struct edid *drm_get_edid(struct drm_connector *connector, |
struct i2c_adapter *adapter); |
extern int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid); |
extern void drm_mode_probed_add(struct drm_connector *connector, struct drm_display_mode *mode); |
extern void drm_mode_remove(struct drm_connector *connector, struct drm_display_mode *mode); |
extern void drm_mode_copy(struct drm_display_mode *dst, const struct drm_display_mode *src); |
extern struct drm_display_mode *drm_mode_duplicate(struct drm_device *dev, |
const struct drm_display_mode *mode); |
extern void drm_mode_debug_printmodeline(struct drm_display_mode *mode); |
862,7 → 889,7 |
/* for us by fb module */ |
extern int drm_mode_attachmode_crtc(struct drm_device *dev, |
struct drm_crtc *crtc, |
struct drm_display_mode *mode); |
const struct drm_display_mode *mode); |
extern int drm_mode_detachmode_crtc(struct drm_device *dev, struct drm_display_mode *mode); |
extern struct drm_display_mode *drm_mode_create(struct drm_device *dev); |
888,6 → 915,12 |
extern int drm_connector_property_get_value(struct drm_connector *connector, |
struct drm_property *property, |
uint64_t *value); |
extern int drm_object_property_set_value(struct drm_mode_object *obj, |
struct drm_property *property, |
uint64_t val); |
extern int drm_object_property_get_value(struct drm_mode_object *obj, |
struct drm_property *property, |
uint64_t *value); |
extern struct drm_display_mode *drm_crtc_mode_create(struct drm_device *dev); |
extern void drm_framebuffer_set_object(struct drm_device *dev, |
unsigned long handle); |
894,6 → 927,9 |
extern int drm_framebuffer_init(struct drm_device *dev, |
struct drm_framebuffer *fb, |
const struct drm_framebuffer_funcs *funcs); |
extern void drm_framebuffer_unreference(struct drm_framebuffer *fb); |
extern void drm_framebuffer_reference(struct drm_framebuffer *fb); |
extern void drm_framebuffer_remove(struct drm_framebuffer *fb); |
extern void drm_framebuffer_cleanup(struct drm_framebuffer *fb); |
extern int drmfb_probe(struct drm_device *dev, struct drm_crtc *crtc); |
extern int drmfb_remove(struct drm_device *dev, struct drm_framebuffer *fb); |
900,10 → 936,24 |
extern void drm_crtc_probe_connector_modes(struct drm_device *dev, int maxX, int maxY); |
extern bool drm_crtc_in_use(struct drm_crtc *crtc); |
extern int drm_connector_attach_property(struct drm_connector *connector, |
extern void drm_connector_attach_property(struct drm_connector *connector, |
struct drm_property *property, uint64_t init_val); |
extern void drm_object_attach_property(struct drm_mode_object *obj, |
struct drm_property *property, |
uint64_t init_val); |
extern struct drm_property *drm_property_create(struct drm_device *dev, int flags, |
const char *name, int num_values); |
extern struct drm_property *drm_property_create_enum(struct drm_device *dev, int flags, |
const char *name, |
const struct drm_prop_enum_list *props, |
int num_values); |
struct drm_property *drm_property_create_bitmask(struct drm_device *dev, |
int flags, const char *name, |
const struct drm_prop_enum_list *props, |
int num_values); |
struct drm_property *drm_property_create_range(struct drm_device *dev, int flags, |
const char *name, |
uint64_t min, uint64_t max); |
extern void drm_property_destroy(struct drm_device *dev, struct drm_property *property); |
extern int drm_property_add_enum(struct drm_property *property, int index, |
uint64_t value, const char *name); |
919,7 → 969,7 |
struct drm_encoder *encoder); |
extern void drm_mode_connector_detach_encoder(struct drm_connector *connector, |
struct drm_encoder *encoder); |
extern bool drm_mode_crtc_set_gamma_size(struct drm_crtc *crtc, |
extern int drm_mode_crtc_set_gamma_size(struct drm_crtc *crtc, |
int gamma_size); |
extern struct drm_mode_object *drm_mode_object_find(struct drm_device *dev, |
uint32_t id, uint32_t type); |
995,7 → 1045,28 |
int hdisplay, int vdisplay); |
extern int drm_edid_header_is_valid(const u8 *raw_edid); |
extern bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid); |
extern bool drm_edid_is_valid(struct edid *edid); |
struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, |
int hsize, int vsize, int fresh); |
int hsize, int vsize, int fresh, |
bool rb); |
extern int drm_mode_create_dumb_ioctl(struct drm_device *dev, |
void *data, struct drm_file *file_priv); |
extern int drm_mode_mmap_dumb_ioctl(struct drm_device *dev, |
void *data, struct drm_file *file_priv); |
extern int drm_mode_destroy_dumb_ioctl(struct drm_device *dev, |
void *data, struct drm_file *file_priv); |
extern int drm_mode_obj_get_properties_ioctl(struct drm_device *dev, void *data, |
struct drm_file *file_priv); |
extern int drm_mode_obj_set_property_ioctl(struct drm_device *dev, void *data, |
struct drm_file *file_priv); |
extern void drm_fb_get_bpp_depth(uint32_t format, unsigned int *depth, |
int *bpp); |
extern int drm_format_num_planes(uint32_t format); |
extern int drm_format_plane_cpp(uint32_t format, int plane); |
extern int drm_format_horz_chroma_subsampling(uint32_t format); |
extern int drm_format_vert_chroma_subsampling(uint32_t format); |
#endif /* __DRM_CRTC_H__ */ |
/drivers/include/drm/drm_crtc_helper.h |
---|
44,6 → 44,13 |
ENTER_ATOMIC_MODE_SET, |
}; |
/** |
* drm_crtc_helper_funcs - helper operations for CRTCs |
* @mode_fixup: try to fixup proposed mode for this connector |
* @mode_set: set this mode |
* |
* The helper operations are called by the mid-layer CRTC helper. |
*/ |
struct drm_crtc_helper_funcs { |
/* |
* Control power levels on the CRTC. If the mode passed in is |
55,7 → 62,7 |
/* Provider can fixup or change mode timings before modeset occurs */ |
bool (*mode_fixup)(struct drm_crtc *crtc, |
struct drm_display_mode *mode, |
const struct drm_display_mode *mode, |
struct drm_display_mode *adjusted_mode); |
/* Actually set the mode */ |
int (*mode_set)(struct drm_crtc *crtc, struct drm_display_mode *mode, |
76,6 → 83,13 |
void (*disable)(struct drm_crtc *crtc); |
}; |
/** |
* drm_encoder_helper_funcs - helper operations for encoders |
* @mode_fixup: try to fixup proposed mode for this connector |
* @mode_set: set this mode |
* |
* The helper operations are called by the mid-layer CRTC helper. |
*/ |
struct drm_encoder_helper_funcs { |
void (*dpms)(struct drm_encoder *encoder, int mode); |
void (*save)(struct drm_encoder *encoder); |
82,7 → 96,7 |
void (*restore)(struct drm_encoder *encoder); |
bool (*mode_fixup)(struct drm_encoder *encoder, |
struct drm_display_mode *mode, |
const struct drm_display_mode *mode, |
struct drm_display_mode *adjusted_mode); |
void (*prepare)(struct drm_encoder *encoder); |
void (*commit)(struct drm_encoder *encoder); |
97,6 → 111,13 |
void (*disable)(struct drm_encoder *encoder); |
}; |
/** |
* drm_connector_helper_funcs - helper operations for connectors |
* @get_modes: get mode list for this connector |
* @mode_valid: is this mode valid on the given connector? |
* |
* The helper operations are called by the mid-layer CRTC helper. |
*/ |
struct drm_connector_helper_funcs { |
int (*get_modes)(struct drm_connector *connector); |
int (*mode_valid)(struct drm_connector *connector, |
145,6 → 166,4 |
extern void drm_kms_helper_poll_disable(struct drm_device *dev); |
extern void drm_kms_helper_poll_enable(struct drm_device *dev); |
extern int drm_format_num_planes(uint32_t format); |
#endif |
/drivers/include/drm/drm_dp_helper.h |
---|
26,7 → 26,19 |
#include <linux/types.h> |
#include <linux/i2c.h> |
/* From the VESA DisplayPort spec */ |
/* |
* Unless otherwise noted, all values are from the DP 1.1a spec. Note that |
* DP and DPCD versions are independent. Differences from 1.0 are not noted, |
* 1.0 devices basically don't exist in the wild. |
* |
* Abbreviations, in chronological order: |
* |
* eDP: Embedded DisplayPort version 1 |
* DPI: DisplayPort Interoperability Guideline v1.1a |
* 1.2: DisplayPort 1.2 |
* |
* 1.2 formally includes both eDP and DPI definitions. |
*/ |
#define AUX_NATIVE_WRITE 0x8 |
#define AUX_NATIVE_READ 0x9 |
53,7 → 65,7 |
#define DP_MAX_LANE_COUNT 0x002 |
# define DP_MAX_LANE_COUNT_MASK 0x1f |
# define DP_TPS3_SUPPORTED (1 << 6) |
# define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */ |
# define DP_ENHANCED_FRAME_CAP (1 << 7) |
#define DP_MAX_DOWNSPREAD 0x003 |
69,15 → 81,33 |
/* 10b = TMDS or HDMI */ |
/* 11b = Other */ |
# define DP_FORMAT_CONVERSION (1 << 3) |
# define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */ |
#define DP_MAIN_LINK_CHANNEL_CODING 0x006 |
#define DP_EDP_CONFIGURATION_CAP 0x00d |
#define DP_TRAINING_AUX_RD_INTERVAL 0x00e |
#define DP_DOWN_STREAM_PORT_COUNT 0x007 |
# define DP_PORT_COUNT_MASK 0x0f |
# define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */ |
# define DP_OUI_SUPPORT (1 << 7) |
#define DP_PSR_SUPPORT 0x070 |
#define DP_I2C_SPEED_CAP 0x00c /* DPI */ |
# define DP_I2C_SPEED_1K 0x01 |
# define DP_I2C_SPEED_5K 0x02 |
# define DP_I2C_SPEED_10K 0x04 |
# define DP_I2C_SPEED_100K 0x08 |
# define DP_I2C_SPEED_400K 0x10 |
# define DP_I2C_SPEED_1M 0x20 |
#define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */ |
#define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */ |
/* Multiple stream transport */ |
#define DP_MSTM_CAP 0x021 /* 1.2 */ |
# define DP_MST_CAP (1 << 0) |
#define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ |
# define DP_PSR_IS_SUPPORTED 1 |
#define DP_PSR_CAPS 0x071 |
#define DP_PSR_CAPS 0x071 /* XXX 1.2? */ |
# define DP_PSR_NO_TRAIN_ON_EXIT 1 |
# define DP_PSR_SETUP_TIME_330 (0 << 1) |
# define DP_PSR_SETUP_TIME_275 (1 << 1) |
89,11 → 119,36 |
# define DP_PSR_SETUP_TIME_MASK (7 << 1) |
# define DP_PSR_SETUP_TIME_SHIFT 1 |
/* |
* 0x80-0x8f describe downstream port capabilities, but there are two layouts |
* based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not, |
* each port's descriptor is one byte wide. If it was set, each port's is |
* four bytes wide, starting with the one byte from the base info. As of |
* DP interop v1.1a only VGA defines additional detail. |
*/ |
/* offset 0 */ |
#define DP_DOWNSTREAM_PORT_0 0x80 |
# define DP_DS_PORT_TYPE_MASK (7 << 0) |
# define DP_DS_PORT_TYPE_DP 0 |
# define DP_DS_PORT_TYPE_VGA 1 |
# define DP_DS_PORT_TYPE_DVI 2 |
# define DP_DS_PORT_TYPE_HDMI 3 |
# define DP_DS_PORT_TYPE_NON_EDID 4 |
# define DP_DS_PORT_HPD (1 << 3) |
/* offset 1 for VGA is maximum megapixels per second / 8 */ |
/* offset 2 */ |
# define DP_DS_VGA_MAX_BPC_MASK (3 << 0) |
# define DP_DS_VGA_8BPC 0 |
# define DP_DS_VGA_10BPC 1 |
# define DP_DS_VGA_12BPC 2 |
# define DP_DS_VGA_16BPC 3 |
/* link configuration */ |
#define DP_LINK_BW_SET 0x100 |
# define DP_LINK_BW_1_62 0x06 |
# define DP_LINK_BW_2_7 0x0a |
# define DP_LINK_BW_5_4 0x14 |
# define DP_LINK_BW_5_4 0x14 /* 1.2 */ |
#define DP_LANE_COUNT_SET 0x101 |
# define DP_LANE_COUNT_MASK 0x0f |
103,7 → 158,7 |
# define DP_TRAINING_PATTERN_DISABLE 0 |
# define DP_TRAINING_PATTERN_1 1 |
# define DP_TRAINING_PATTERN_2 2 |
# define DP_TRAINING_PATTERN_3 3 |
# define DP_TRAINING_PATTERN_3 3 /* 1.2 */ |
# define DP_TRAINING_PATTERN_MASK 0x3 |
# define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2) |
144,16 → 199,32 |
#define DP_DOWNSPREAD_CTRL 0x107 |
# define DP_SPREAD_AMP_0_5 (1 << 4) |
# define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) /* eDP */ |
#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 |
# define DP_SET_ANSI_8B10B (1 << 0) |
#define DP_PSR_EN_CFG 0x170 |
#define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */ |
/* bitmask as for DP_I2C_SPEED_CAP */ |
#define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */ |
#define DP_MSTM_CTRL 0x111 /* 1.2 */ |
# define DP_MST_EN (1 << 0) |
# define DP_UP_REQ_EN (1 << 1) |
# define DP_UPSTREAM_IS_SRC (1 << 2) |
#define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */ |
# define DP_PSR_ENABLE (1 << 0) |
# define DP_PSR_MAIN_LINK_ACTIVE (1 << 1) |
# define DP_PSR_CRC_VERIFICATION (1 << 2) |
# define DP_PSR_FRAME_CAPTURE (1 << 3) |
#define DP_SINK_COUNT 0x200 |
/* prior to 1.2 bit 7 was reserved mbz */ |
# define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f)) |
# define DP_SINK_CP_READY (1 << 6) |
#define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201 |
# define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0) |
# define DP_AUTOMATED_TEST_REQUEST (1 << 1) |
160,8 → 231,6 |
# define DP_CP_IRQ (1 << 2) |
# define DP_SINK_SPECIFIC_IRQ (1 << 6) |
#define DP_EDP_CONFIGURATION_SET 0x10a |
#define DP_LANE0_1_STATUS 0x202 |
#define DP_LANE2_3_STATUS 0x203 |
# define DP_LANE_CR_DONE (1 << 0) |
213,18 → 282,22 |
# define DP_TEST_NAK (1 << 1) |
# define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2) |
#define DP_SOURCE_OUI 0x300 |
#define DP_SINK_OUI 0x400 |
#define DP_BRANCH_OUI 0x500 |
#define DP_SET_POWER 0x600 |
# define DP_SET_POWER_D0 0x1 |
# define DP_SET_POWER_D3 0x2 |
#define DP_PSR_ERROR_STATUS 0x2006 |
#define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */ |
# define DP_PSR_LINK_CRC_ERROR (1 << 0) |
# define DP_PSR_RFB_STORAGE_ERROR (1 << 1) |
#define DP_PSR_ESI 0x2007 |
#define DP_PSR_ESI 0x2007 /* XXX 1.2? */ |
# define DP_PSR_CAPS_CHANGE (1 << 0) |
#define DP_PSR_STATUS 0x2008 |
#define DP_PSR_STATUS 0x2008 /* XXX 1.2? */ |
# define DP_PSR_SINK_INACTIVE 0 |
# define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1 |
# define DP_PSR_SINK_ACTIVE_RFB 2 |
/drivers/include/drm/drm_edid.h |
---|
90,12 → 90,26 |
u8 min_hfreq_khz; |
u8 max_hfreq_khz; |
u8 pixel_clock_mhz; /* need to multiply by 10 */ |
__le16 sec_gtf_toggle; /* A000=use above, 20=use below */ |
u8 flags; |
union { |
struct { |
u8 reserved; |
u8 hfreq_start_khz; /* need to multiply by 2 */ |
u8 c; /* need to divide by 2 */ |
__le16 m; |
u8 k; |
u8 j; /* need to divide by 2 */ |
} __attribute__((packed)) gtf2; |
struct { |
u8 version; |
u8 data1; /* high 6 bits: extra clock resolution */ |
u8 data2; /* plus low 2 of above: max hactive */ |
u8 supported_aspects; |
u8 flags; /* preferred aspect and blanking support */ |
u8 supported_scalings; |
u8 preferred_refresh; |
} __attribute__((packed)) cvt; |
} formula; |
} __attribute__((packed)); |
struct detailed_data_wpindex { |
238,5 → 252,6 |
struct drm_display_mode *mode); |
struct drm_connector *drm_select_eld(struct drm_encoder *encoder, |
struct drm_display_mode *mode); |
int drm_load_edid_firmware(struct drm_connector *connector); |
#endif /* __DRM_EDID_H__ */ |
/drivers/include/drm/drm_fb_helper.h |
---|
34,7 → 34,6 |
struct drm_fb_helper_crtc { |
uint32_t crtc_id; |
struct drm_mode_set mode_set; |
struct drm_display_mode *desired_mode; |
}; |
73,7 → 72,6 |
int connector_count; |
struct drm_fb_helper_connector **connector_info; |
struct drm_fb_helper_funcs *funcs; |
int conn_limit; |
struct fb_info *fbdev; |
u32 pseudo_palette[17]; |
struct list_head kernel_fb_list; |
/drivers/include/drm/drm_fixed.h |
---|
37,6 → 37,7 |
#define dfixed_init(A) { .full = dfixed_const((A)) } |
#define dfixed_init_half(A) { .full = dfixed_const_half((A)) } |
#define dfixed_trunc(A) ((A).full >> 12) |
#define dfixed_frac(A) ((A).full & ((1 << 12) - 1)) |
static inline u32 dfixed_floor(fixed20_12 A) |
{ |
/drivers/include/drm/drm_fourcc.h |
---|
106,9 → 106,10 |
#define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */ |
#define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */ |
#define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */ |
#define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */ |
#define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */ |
/* 2 non contiguous plane YCbCr */ |
#define DRM_FORMAT_NV12M fourcc_code('N', 'M', '1', '2') /* 2x2 subsampled Cr:Cb plane */ |
/* special NV12 tiled format */ |
#define DRM_FORMAT_NV12MT fourcc_code('T', 'M', '1', '2') /* 2x2 subsampled Cr:Cb plane 64x32 macroblocks */ |
/* |
131,7 → 132,4 |
#define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */ |
#define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */ |
/* 3 non contiguous plane YCbCr */ |
#define DRM_FORMAT_YUV420M fourcc_code('Y', 'M', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */ |
#endif /* DRM_FOURCC_H */ |
/drivers/include/drm/drm_mm.h |
---|
50,6 → 50,7 |
unsigned scanned_next_free : 1; |
unsigned scanned_preceeds_hole : 1; |
unsigned allocated : 1; |
unsigned long color; |
unsigned long start; |
unsigned long size; |
struct drm_mm *mm; |
66,6 → 67,7 |
spinlock_t unused_lock; |
unsigned int scan_check_range : 1; |
unsigned scan_alignment; |
unsigned long scan_color; |
unsigned long scan_size; |
unsigned long scan_hit_start; |
unsigned scan_hit_size; |
73,6 → 75,9 |
unsigned long scan_start; |
unsigned long scan_end; |
struct drm_mm_node *prev_scanned_node; |
void (*color_adjust)(struct drm_mm_node *node, unsigned long color, |
unsigned long *start, unsigned long *end); |
}; |
static inline bool drm_mm_node_allocated(struct drm_mm_node *node) |
100,11 → 105,13 |
extern struct drm_mm_node *drm_mm_get_block_generic(struct drm_mm_node *node, |
unsigned long size, |
unsigned alignment, |
unsigned long color, |
int atomic); |
extern struct drm_mm_node *drm_mm_get_block_range_generic( |
struct drm_mm_node *node, |
unsigned long size, |
unsigned alignment, |
unsigned long color, |
unsigned long start, |
unsigned long end, |
int atomic); |
112,13 → 119,13 |
unsigned long size, |
unsigned alignment) |
{ |
return drm_mm_get_block_generic(parent, size, alignment, 0); |
return drm_mm_get_block_generic(parent, size, alignment, 0, 0); |
} |
static inline struct drm_mm_node *drm_mm_get_block_atomic(struct drm_mm_node *parent, |
unsigned long size, |
unsigned alignment) |
{ |
return drm_mm_get_block_generic(parent, size, alignment, 1); |
return drm_mm_get_block_generic(parent, size, alignment, 0, 1); |
} |
static inline struct drm_mm_node *drm_mm_get_block_range( |
struct drm_mm_node *parent, |
127,9 → 134,20 |
unsigned long start, |
unsigned long end) |
{ |
return drm_mm_get_block_range_generic(parent, size, alignment, |
return drm_mm_get_block_range_generic(parent, size, alignment, 0, |
start, end, 0); |
} |
static inline struct drm_mm_node *drm_mm_get_color_block_range( |
struct drm_mm_node *parent, |
unsigned long size, |
unsigned alignment, |
unsigned long color, |
unsigned long start, |
unsigned long end) |
{ |
return drm_mm_get_block_range_generic(parent, size, alignment, color, |
start, end, 0); |
} |
static inline struct drm_mm_node *drm_mm_get_block_atomic_range( |
struct drm_mm_node *parent, |
unsigned long size, |
137,7 → 155,7 |
unsigned long start, |
unsigned long end) |
{ |
return drm_mm_get_block_range_generic(parent, size, alignment, |
return drm_mm_get_block_range_generic(parent, size, alignment, 0, |
start, end, 1); |
} |
extern int drm_mm_insert_node(struct drm_mm *mm, struct drm_mm_node *node, |
149,18 → 167,59 |
extern void drm_mm_put_block(struct drm_mm_node *cur); |
extern void drm_mm_remove_node(struct drm_mm_node *node); |
extern void drm_mm_replace_node(struct drm_mm_node *old, struct drm_mm_node *new); |
extern struct drm_mm_node *drm_mm_search_free(const struct drm_mm *mm, |
extern struct drm_mm_node *drm_mm_search_free_generic(const struct drm_mm *mm, |
unsigned long size, |
unsigned alignment, |
int best_match); |
extern struct drm_mm_node *drm_mm_search_free_in_range( |
unsigned long color, |
bool best_match); |
extern struct drm_mm_node *drm_mm_search_free_in_range_generic( |
const struct drm_mm *mm, |
unsigned long size, |
unsigned alignment, |
unsigned long color, |
unsigned long start, |
unsigned long end, |
int best_match); |
extern int drm_mm_init(struct drm_mm *mm, unsigned long start, |
bool best_match); |
static inline struct drm_mm_node *drm_mm_search_free(const struct drm_mm *mm, |
unsigned long size, |
unsigned alignment, |
bool best_match) |
{ |
return drm_mm_search_free_generic(mm,size, alignment, 0, best_match); |
} |
static inline struct drm_mm_node *drm_mm_search_free_in_range( |
const struct drm_mm *mm, |
unsigned long size, |
unsigned alignment, |
unsigned long start, |
unsigned long end, |
bool best_match) |
{ |
return drm_mm_search_free_in_range_generic(mm, size, alignment, 0, |
start, end, best_match); |
} |
static inline struct drm_mm_node *drm_mm_search_free_color(const struct drm_mm *mm, |
unsigned long size, |
unsigned alignment, |
unsigned long color, |
bool best_match) |
{ |
return drm_mm_search_free_generic(mm,size, alignment, color, best_match); |
} |
static inline struct drm_mm_node *drm_mm_search_free_in_range_color( |
const struct drm_mm *mm, |
unsigned long size, |
unsigned alignment, |
unsigned long color, |
unsigned long start, |
unsigned long end, |
bool best_match) |
{ |
return drm_mm_search_free_in_range_generic(mm, size, alignment, color, |
start, end, best_match); |
} |
extern int drm_mm_init(struct drm_mm *mm, |
unsigned long start, |
unsigned long size); |
extern void drm_mm_takedown(struct drm_mm *mm); |
extern int drm_mm_clean(struct drm_mm *mm); |
171,10 → 230,14 |
return block->mm; |
} |
void drm_mm_init_scan(struct drm_mm *mm, unsigned long size, |
unsigned alignment); |
void drm_mm_init_scan_with_range(struct drm_mm *mm, unsigned long size, |
void drm_mm_init_scan(struct drm_mm *mm, |
unsigned long size, |
unsigned alignment, |
unsigned long color); |
void drm_mm_init_scan_with_range(struct drm_mm *mm, |
unsigned long size, |
unsigned alignment, |
unsigned long color, |
unsigned long start, |
unsigned long end); |
int drm_mm_scan_add_block(struct drm_mm_node *node); |
/drivers/include/drm/drm_mode.h |
---|
27,6 → 27,8 |
#ifndef _DRM_MODE_H |
#define _DRM_MODE_H |
#include <linux/types.h> |
#define DRM_DISPLAY_INFO_LEN 32 |
#define DRM_CONNECTOR_NAME_LEN 32 |
#define DRM_DISPLAY_MODE_LEN 32 |
228,6 → 230,7 |
#define DRM_MODE_PROP_IMMUTABLE (1<<2) |
#define DRM_MODE_PROP_ENUM (1<<3) /* enumerated type with text strings */ |
#define DRM_MODE_PROP_BLOB (1<<4) |
#define DRM_MODE_PROP_BITMASK (1<<5) /* bitmask of enumerated types */ |
struct drm_mode_property_enum { |
__u64 value; |
252,6 → 255,21 |
__u32 connector_id; |
}; |
struct drm_mode_obj_get_properties { |
__u64 props_ptr; |
__u64 prop_values_ptr; |
__u32 count_props; |
__u32 obj_id; |
__u32 obj_type; |
}; |
struct drm_mode_obj_set_property { |
__u64 value; |
__u32 prop_id; |
__u32 obj_id; |
__u32 obj_type; |
}; |
struct drm_mode_get_blob { |
__u32 blob_id; |
__u32 length; |
341,8 → 359,9 |
struct drm_mode_modeinfo mode; |
}; |
#define DRM_MODE_CURSOR_BO (1<<0) |
#define DRM_MODE_CURSOR_MOVE (1<<1) |
#define DRM_MODE_CURSOR_BO 0x01 |
#define DRM_MODE_CURSOR_MOVE 0x02 |
#define DRM_MODE_CURSOR_FLAGS 0x03 |
/* |
* depending on the value in flags different members are used. |
/drivers/include/drm/drm_pciids.h |
---|
1,7 → 1,3 |
/* |
This file is auto-generated from the drm_pciids.txt in the DRM CVS |
Please contact dri-devel@lists.sf.net to add new cards to this list |
*/ |
#define radeon_PCI_IDS \ |
{0x1002, 0x3150, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \ |
{0x1002, 0x3151, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
181,6 → 177,7 |
{0x1002, 0x6747, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TURKS|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x6748, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TURKS|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x6749, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TURKS|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x674A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TURKS|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x6750, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TURKS|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x6751, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TURKS|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x6758, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TURKS|RADEON_NEW_MEMMAP}, \ |
198,9 → 195,64 |
{0x1002, 0x6767, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAICOS|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x6768, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAICOS|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x6770, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAICOS|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x6771, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAICOS|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x6772, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAICOS|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x6778, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAICOS|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x6779, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAICOS|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x677B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAICOS|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x6840, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TURKS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x6841, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TURKS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x6842, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TURKS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x6843, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TURKS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x6849, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TURKS|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x684C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x6850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TURKS|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x6858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TURKS|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x6859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TURKS|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x6880, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x6888, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x6889, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \ |
242,6 → 294,7 |
{0x1002, 0x68f2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x68f8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x68f9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x68fa, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x68fe, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x7100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ |
{0x1002, 0x7101, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
483,7 → 536,10 |
{0x1002, 0x9645, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SUMO2|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
{0x1002, 0x9647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SUMO|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP},\ |
{0x1002, 0x9648, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SUMO|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP},\ |
{0x1002, 0x9649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SUMO|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP},\ |
{0x1002, 0x964a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SUMO|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
{0x1002, 0x964b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SUMO|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
{0x1002, 0x964c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SUMO|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
{0x1002, 0x964e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SUMO|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP},\ |
{0x1002, 0x964f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SUMO|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP},\ |
{0x1002, 0x9710, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS880|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
498,6 → 554,33 |
{0x1002, 0x9805, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PALM|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
{0x1002, 0x9806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PALM|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
{0x1002, 0x9807, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PALM|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
{0x1002, 0x9808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PALM|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
{0x1002, 0x9809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PALM|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
{0x1002, 0x980A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PALM|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
{0x1002, 0x9900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
{0x1002, 0x9901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
{0x1002, 0x9903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
{0x1002, 0x9904, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
{0x1002, 0x9905, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
{0x1002, 0x9906, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
{0x1002, 0x9907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
{0x1002, 0x9908, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
{0x1002, 0x9909, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
{0x1002, 0x990A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
{0x1002, 0x990F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
{0x1002, 0x9910, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
{0x1002, 0x9913, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
{0x1002, 0x9917, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
{0x1002, 0x9918, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
{0x1002, 0x9919, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
{0x1002, 0x9990, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
{0x1002, 0x9991, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
{0x1002, 0x9992, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
{0x1002, 0x9993, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
{0x1002, 0x9994, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
{0x1002, 0x99A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
{0x1002, 0x99A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
{0x1002, 0x99A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
{0, 0, 0} |
/drivers/include/drm/i915_drm.h |
---|
0,0 → 1,953 |
/* |
* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
* All Rights Reserved. |
* |
* Permission is hereby granted, free of charge, to any person obtaining a |
* copy of this software and associated documentation files (the |
* "Software"), to deal in the Software without restriction, including |
* without limitation the rights to use, copy, modify, merge, publish, |
* distribute, sub license, and/or sell copies of the Software, and to |
* permit persons to whom the Software is furnished to do so, subject to |
* the following conditions: |
* |
* The above copyright notice and this permission notice (including the |
* next paragraph) shall be included in all copies or substantial portions |
* of the Software. |
* |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
* |
*/ |
#ifndef _UAPI_I915_DRM_H_ |
#define _UAPI_I915_DRM_H_ |
#include <drm/drm.h> |
/* Please note that modifications to all structs defined here are |
* subject to backwards-compatibility constraints. |
*/ |
/* For use by IPS driver */ |
extern unsigned long i915_read_mch_val(void); |
extern bool i915_gpu_raise(void); |
extern bool i915_gpu_lower(void); |
extern bool i915_gpu_busy(void); |
extern bool i915_gpu_turbo_disable(void); |
/* Each region is a minimum of 16k, and there are at most 255 of them. |
*/ |
#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use |
* of chars for next/prev indices */ |
#define I915_LOG_MIN_TEX_REGION_SIZE 14 |
typedef struct _drm_i915_init { |
enum { |
I915_INIT_DMA = 0x01, |
I915_CLEANUP_DMA = 0x02, |
I915_RESUME_DMA = 0x03 |
} func; |
unsigned int mmio_offset; |
int sarea_priv_offset; |
unsigned int ring_start; |
unsigned int ring_end; |
unsigned int ring_size; |
unsigned int front_offset; |
unsigned int back_offset; |
unsigned int depth_offset; |
unsigned int w; |
unsigned int h; |
unsigned int pitch; |
unsigned int pitch_bits; |
unsigned int back_pitch; |
unsigned int depth_pitch; |
unsigned int cpp; |
unsigned int chipset; |
} drm_i915_init_t; |
typedef struct _drm_i915_sarea { |
struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; |
int last_upload; /* last time texture was uploaded */ |
int last_enqueue; /* last time a buffer was enqueued */ |
int last_dispatch; /* age of the most recently dispatched buffer */ |
int ctxOwner; /* last context to upload state */ |
int texAge; |
int pf_enabled; /* is pageflipping allowed? */ |
int pf_active; |
int pf_current_page; /* which buffer is being displayed? */ |
int perf_boxes; /* performance boxes to be displayed */ |
int width, height; /* screen size in pixels */ |
drm_handle_t front_handle; |
int front_offset; |
int front_size; |
drm_handle_t back_handle; |
int back_offset; |
int back_size; |
drm_handle_t depth_handle; |
int depth_offset; |
int depth_size; |
drm_handle_t tex_handle; |
int tex_offset; |
int tex_size; |
int log_tex_granularity; |
int pitch; |
int rotation; /* 0, 90, 180 or 270 */ |
int rotated_offset; |
int rotated_size; |
int rotated_pitch; |
int virtualX, virtualY; |
unsigned int front_tiled; |
unsigned int back_tiled; |
unsigned int depth_tiled; |
unsigned int rotated_tiled; |
unsigned int rotated2_tiled; |
int pipeA_x; |
int pipeA_y; |
int pipeA_w; |
int pipeA_h; |
int pipeB_x; |
int pipeB_y; |
int pipeB_w; |
int pipeB_h; |
/* fill out some space for old userspace triple buffer */ |
drm_handle_t unused_handle; |
__u32 unused1, unused2, unused3; |
/* buffer object handles for static buffers. May change |
* over the lifetime of the client. |
*/ |
__u32 front_bo_handle; |
__u32 back_bo_handle; |
__u32 unused_bo_handle; |
__u32 depth_bo_handle; |
} drm_i915_sarea_t; |
/* due to userspace building against these headers we need some compat here */ |
#define planeA_x pipeA_x |
#define planeA_y pipeA_y |
#define planeA_w pipeA_w |
#define planeA_h pipeA_h |
#define planeB_x pipeB_x |
#define planeB_y pipeB_y |
#define planeB_w pipeB_w |
#define planeB_h pipeB_h |
/* Flags for perf_boxes |
*/ |
#define I915_BOX_RING_EMPTY 0x1 |
#define I915_BOX_FLIP 0x2 |
#define I915_BOX_WAIT 0x4 |
#define I915_BOX_TEXTURE_LOAD 0x8 |
#define I915_BOX_LOST_CONTEXT 0x10 |
/* I915 specific ioctls |
* The device specific ioctl range is 0x40 to 0x79. |
*/ |
#define DRM_I915_INIT 0x00 |
#define DRM_I915_FLUSH 0x01 |
#define DRM_I915_FLIP 0x02 |
#define DRM_I915_BATCHBUFFER 0x03 |
#define DRM_I915_IRQ_EMIT 0x04 |
#define DRM_I915_IRQ_WAIT 0x05 |
#define DRM_I915_GETPARAM 0x06 |
#define DRM_I915_SETPARAM 0x07 |
#define DRM_I915_ALLOC 0x08 |
#define DRM_I915_FREE 0x09 |
#define DRM_I915_INIT_HEAP 0x0a |
#define DRM_I915_CMDBUFFER 0x0b |
#define DRM_I915_DESTROY_HEAP 0x0c |
#define DRM_I915_SET_VBLANK_PIPE 0x0d |
#define DRM_I915_GET_VBLANK_PIPE 0x0e |
#define DRM_I915_VBLANK_SWAP 0x0f |
#define DRM_I915_HWS_ADDR 0x11 |
#define DRM_I915_GEM_INIT 0x13 |
#define DRM_I915_GEM_EXECBUFFER 0x14 |
#define DRM_I915_GEM_PIN 0x15 |
#define DRM_I915_GEM_UNPIN 0x16 |
#define DRM_I915_GEM_BUSY 0x17 |
#define DRM_I915_GEM_THROTTLE 0x18 |
#define DRM_I915_GEM_ENTERVT 0x19 |
#define DRM_I915_GEM_LEAVEVT 0x1a |
#define DRM_I915_GEM_CREATE 0x1b |
#define DRM_I915_GEM_PREAD 0x1c |
#define DRM_I915_GEM_PWRITE 0x1d |
#define DRM_I915_GEM_MMAP 0x1e |
#define DRM_I915_GEM_SET_DOMAIN 0x1f |
#define DRM_I915_GEM_SW_FINISH 0x20 |
#define DRM_I915_GEM_SET_TILING 0x21 |
#define DRM_I915_GEM_GET_TILING 0x22 |
#define DRM_I915_GEM_GET_APERTURE 0x23 |
#define DRM_I915_GEM_MMAP_GTT 0x24 |
#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 |
#define DRM_I915_GEM_MADVISE 0x26 |
#define DRM_I915_OVERLAY_PUT_IMAGE 0x27 |
#define DRM_I915_OVERLAY_ATTRS 0x28 |
#define DRM_I915_GEM_EXECBUFFER2 0x29 |
#define DRM_I915_GET_SPRITE_COLORKEY 0x2a |
#define DRM_I915_SET_SPRITE_COLORKEY 0x2b |
#define DRM_I915_GEM_WAIT 0x2c |
#define DRM_I915_GEM_CONTEXT_CREATE 0x2d |
#define DRM_I915_GEM_CONTEXT_DESTROY 0x2e |
#define DRM_I915_GEM_SET_CACHING 0x2f |
#define DRM_I915_GEM_GET_CACHING 0x30 |
#define DRM_I915_REG_READ 0x31 |
#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) |
#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) |
#define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP) |
#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) |
#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) |
#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) |
#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) |
#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) |
#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) |
#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) |
#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) |
#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) |
#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) |
#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) |
#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) |
#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) |
#define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init) |
#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) |
#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) |
#define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) |
#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) |
#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) |
#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) |
#define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching) |
#define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching) |
#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) |
#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) |
#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) |
#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) |
#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) |
#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) |
#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) |
#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) |
#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) |
#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) |
#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) |
#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) |
#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) |
#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) |
#define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) |
#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) |
#define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) |
#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) |
#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) |
#define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) |
#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) |
#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) |
#define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read) |
/* Allow drivers to submit batchbuffers directly to hardware, relying |
* on the security mechanisms provided by hardware. |
*/ |
typedef struct drm_i915_batchbuffer { |
int start; /* agp offset */ |
int used; /* nr bytes in use */ |
int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ |
int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ |
int num_cliprects; /* mulitpass with multiple cliprects? */ |
struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ |
} drm_i915_batchbuffer_t; |
/* As above, but pass a pointer to userspace buffer which can be |
* validated by the kernel prior to sending to hardware. |
*/ |
typedef struct _drm_i915_cmdbuffer { |
char __user *buf; /* pointer to userspace command buffer */ |
int sz; /* nr bytes in buf */ |
int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ |
int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ |
int num_cliprects; /* mulitpass with multiple cliprects? */ |
struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ |
} drm_i915_cmdbuffer_t; |
/* Userspace can request & wait on irq's: |
*/ |
typedef struct drm_i915_irq_emit { |
int __user *irq_seq; |
} drm_i915_irq_emit_t; |
typedef struct drm_i915_irq_wait { |
int irq_seq; |
} drm_i915_irq_wait_t; |
/* Ioctl to query kernel params: |
*/ |
#define I915_PARAM_IRQ_ACTIVE 1 |
#define I915_PARAM_ALLOW_BATCHBUFFER 2 |
#define I915_PARAM_LAST_DISPATCH 3 |
#define I915_PARAM_CHIPSET_ID 4 |
#define I915_PARAM_HAS_GEM 5 |
#define I915_PARAM_NUM_FENCES_AVAIL 6 |
#define I915_PARAM_HAS_OVERLAY 7 |
#define I915_PARAM_HAS_PAGEFLIPPING 8 |
#define I915_PARAM_HAS_EXECBUF2 9 |
#define I915_PARAM_HAS_BSD 10 |
#define I915_PARAM_HAS_BLT 11 |
#define I915_PARAM_HAS_RELAXED_FENCING 12 |
#define I915_PARAM_HAS_COHERENT_RINGS 13 |
#define I915_PARAM_HAS_EXEC_CONSTANTS 14 |
#define I915_PARAM_HAS_RELAXED_DELTA 15 |
#define I915_PARAM_HAS_GEN7_SOL_RESET 16 |
#define I915_PARAM_HAS_LLC 17 |
#define I915_PARAM_HAS_ALIASING_PPGTT 18 |
#define I915_PARAM_HAS_WAIT_TIMEOUT 19 |
#define I915_PARAM_HAS_SEMAPHORES 20 |
#define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21 |
#define I915_PARAM_RSVD_FOR_FUTURE_USE 22 |
typedef struct drm_i915_getparam { |
int param; |
int __user *value; |
} drm_i915_getparam_t; |
/* Ioctl to set kernel params: |
*/ |
#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 |
#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 |
#define I915_SETPARAM_ALLOW_BATCHBUFFER 3 |
#define I915_SETPARAM_NUM_USED_FENCES 4 |
typedef struct drm_i915_setparam { |
int param; |
int value; |
} drm_i915_setparam_t; |
/* A memory manager for regions of shared memory: |
*/ |
#define I915_MEM_REGION_AGP 1 |
typedef struct drm_i915_mem_alloc { |
int region; |
int alignment; |
int size; |
int __user *region_offset; /* offset from start of fb or agp */ |
} drm_i915_mem_alloc_t; |
typedef struct drm_i915_mem_free { |
int region; |
int region_offset; |
} drm_i915_mem_free_t; |
typedef struct drm_i915_mem_init_heap { |
int region; |
int size; |
int start; |
} drm_i915_mem_init_heap_t; |
/* Allow memory manager to be torn down and re-initialized (eg on |
* rotate): |
*/ |
typedef struct drm_i915_mem_destroy_heap { |
int region; |
} drm_i915_mem_destroy_heap_t; |
/* Allow X server to configure which pipes to monitor for vblank signals |
*/ |
#define DRM_I915_VBLANK_PIPE_A 1 |
#define DRM_I915_VBLANK_PIPE_B 2 |
typedef struct drm_i915_vblank_pipe { |
int pipe; |
} drm_i915_vblank_pipe_t; |
/* Schedule buffer swap at given vertical blank: |
*/ |
typedef struct drm_i915_vblank_swap { |
drm_drawable_t drawable; |
enum drm_vblank_seq_type seqtype; |
unsigned int sequence; |
} drm_i915_vblank_swap_t; |
typedef struct drm_i915_hws_addr { |
__u64 addr; |
} drm_i915_hws_addr_t; |
struct drm_i915_gem_init { |
/** |
* Beginning offset in the GTT to be managed by the DRM memory |
* manager. |
*/ |
__u64 gtt_start; |
/** |
* Ending offset in the GTT to be managed by the DRM memory |
* manager. |
*/ |
__u64 gtt_end; |
}; |
struct drm_i915_gem_create { |
/** |
* Requested size for the object. |
* |
* The (page-aligned) allocated size for the object will be returned. |
*/ |
__u64 size; |
/** |
* Returned handle for the object. |
* |
* Object handles are nonzero. |
*/ |
__u32 handle; |
__u32 pad; |
}; |
struct drm_i915_gem_pread { |
/** Handle for the object being read. */ |
__u32 handle; |
__u32 pad; |
/** Offset into the object to read from */ |
__u64 offset; |
/** Length of data to read */ |
__u64 size; |
/** |
* Pointer to write the data into. |
* |
* This is a fixed-size type for 32/64 compatibility. |
*/ |
__u64 data_ptr; |
}; |
struct drm_i915_gem_pwrite { |
/** Handle for the object being written to. */ |
__u32 handle; |
__u32 pad; |
/** Offset into the object to write to */ |
__u64 offset; |
/** Length of data to write */ |
__u64 size; |
/** |
* Pointer to read the data from. |
* |
* This is a fixed-size type for 32/64 compatibility. |
*/ |
__u64 data_ptr; |
}; |
struct drm_i915_gem_mmap { |
/** Handle for the object being mapped. */ |
__u32 handle; |
__u32 pad; |
/** Offset in the object to map. */ |
__u64 offset; |
/** |
* Length of data to map. |
* |
* The value will be page-aligned. |
*/ |
__u64 size; |
/** |
* Returned pointer the data was mapped at. |
* |
* This is a fixed-size type for 32/64 compatibility. |
*/ |
__u64 addr_ptr; |
}; |
struct drm_i915_gem_mmap_gtt { |
/** Handle for the object being mapped. */ |
__u32 handle; |
__u32 pad; |
/** |
* Fake offset to use for subsequent mmap call |
* |
* This is a fixed-size type for 32/64 compatibility. |
*/ |
__u64 offset; |
}; |
struct drm_i915_gem_set_domain { |
/** Handle for the object */ |
__u32 handle; |
/** New read domains */ |
__u32 read_domains; |
/** New write domain */ |
__u32 write_domain; |
}; |
struct drm_i915_gem_sw_finish { |
/** Handle for the object */ |
__u32 handle; |
}; |
struct drm_i915_gem_relocation_entry { |
/** |
* Handle of the buffer being pointed to by this relocation entry. |
* |
* It's appealing to make this be an index into the mm_validate_entry |
* list to refer to the buffer, but this allows the driver to create |
* a relocation list for state buffers and not re-write it per |
* exec using the buffer. |
*/ |
__u32 target_handle; |
/** |
* Value to be added to the offset of the target buffer to make up |
* the relocation entry. |
*/ |
__u32 delta; |
/** Offset in the buffer the relocation entry will be written into */ |
__u64 offset; |
/** |
* Offset value of the target buffer that the relocation entry was last |
* written as. |
* |
* If the buffer has the same offset as last time, we can skip syncing |
* and writing the relocation. This value is written back out by |
* the execbuffer ioctl when the relocation is written. |
*/ |
__u64 presumed_offset; |
/** |
* Target memory domains read by this operation. |
*/ |
__u32 read_domains; |
/** |
* Target memory domains written by this operation. |
* |
* Note that only one domain may be written by the whole |
* execbuffer operation, so that where there are conflicts, |
* the application will get -EINVAL back. |
*/ |
__u32 write_domain; |
}; |
/** @{ |
* Intel memory domains |
* |
* Most of these just align with the various caches in |
* the system and are used to flush and invalidate as |
* objects end up cached in different domains. |
*/ |
/** CPU cache */ |
#define I915_GEM_DOMAIN_CPU 0x00000001 |
/** Render cache, used by 2D and 3D drawing */ |
#define I915_GEM_DOMAIN_RENDER 0x00000002 |
/** Sampler cache, used by texture engine */ |
#define I915_GEM_DOMAIN_SAMPLER 0x00000004 |
/** Command queue, used to load batch buffers */ |
#define I915_GEM_DOMAIN_COMMAND 0x00000008 |
/** Instruction cache, used by shader programs */ |
#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 |
/** Vertex address cache */ |
#define I915_GEM_DOMAIN_VERTEX 0x00000020 |
/** GTT domain - aperture and scanout */ |
#define I915_GEM_DOMAIN_GTT 0x00000040 |
/** @} */ |
struct drm_i915_gem_exec_object { |
/** |
* User's handle for a buffer to be bound into the GTT for this |
* operation. |
*/ |
__u32 handle; |
/** Number of relocations to be performed on this buffer */ |
__u32 relocation_count; |
/** |
* Pointer to array of struct drm_i915_gem_relocation_entry containing |
* the relocations to be performed in this buffer. |
*/ |
__u64 relocs_ptr; |
/** Required alignment in graphics aperture */ |
__u64 alignment; |
/** |
* Returned value of the updated offset of the object, for future |
* presumed_offset writes. |
*/ |
__u64 offset; |
}; |
struct drm_i915_gem_execbuffer { |
/** |
* List of buffers to be validated with their relocations to be |
* performend on them. |
* |
* This is a pointer to an array of struct drm_i915_gem_validate_entry. |
* |
* These buffers must be listed in an order such that all relocations |
* a buffer is performing refer to buffers that have already appeared |
* in the validate list. |
*/ |
__u64 buffers_ptr; |
__u32 buffer_count; |
/** Offset in the batchbuffer to start execution from. */ |
__u32 batch_start_offset; |
/** Bytes used in batchbuffer from batch_start_offset */ |
__u32 batch_len; |
__u32 DR1; |
__u32 DR4; |
__u32 num_cliprects; |
/** This is a struct drm_clip_rect *cliprects */ |
__u64 cliprects_ptr; |
}; |
struct drm_i915_gem_exec_object2 { |
/** |
* User's handle for a buffer to be bound into the GTT for this |
* operation. |
*/ |
__u32 handle; |
/** Number of relocations to be performed on this buffer */ |
__u32 relocation_count; |
/** |
* Pointer to array of struct drm_i915_gem_relocation_entry containing |
* the relocations to be performed in this buffer. |
*/ |
__u64 relocs_ptr; |
/** Required alignment in graphics aperture */ |
__u64 alignment; |
/** |
* Returned value of the updated offset of the object, for future |
* presumed_offset writes. |
*/ |
__u64 offset; |
#define EXEC_OBJECT_NEEDS_FENCE (1<<0) |
__u64 flags; |
__u64 rsvd1; |
__u64 rsvd2; |
}; |
struct drm_i915_gem_execbuffer2 { |
/** |
* List of gem_exec_object2 structs |
*/ |
__u64 buffers_ptr; |
__u32 buffer_count; |
/** Offset in the batchbuffer to start execution from. */ |
__u32 batch_start_offset; |
/** Bytes used in batchbuffer from batch_start_offset */ |
__u32 batch_len; |
__u32 DR1; |
__u32 DR4; |
__u32 num_cliprects; |
/** This is a struct drm_clip_rect *cliprects */ |
__u64 cliprects_ptr; |
#define I915_EXEC_RING_MASK (7<<0) |
#define I915_EXEC_DEFAULT (0<<0) |
#define I915_EXEC_RENDER (1<<0) |
#define I915_EXEC_BSD (2<<0) |
#define I915_EXEC_BLT (3<<0) |
/* Used for switching the constants addressing mode on gen4+ RENDER ring. |
* Gen6+ only supports relative addressing to dynamic state (default) and |
* absolute addressing. |
* |
* These flags are ignored for the BSD and BLT rings. |
*/ |
#define I915_EXEC_CONSTANTS_MASK (3<<6) |
#define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */ |
#define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6) |
#define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */ |
__u64 flags; |
__u64 rsvd1; /* now used for context info */ |
__u64 rsvd2; |
}; |
/** Resets the SO write offset registers for transform feedback on gen7. */ |
#define I915_EXEC_GEN7_SOL_RESET (1<<8) |
#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) |
#define i915_execbuffer2_set_context_id(eb2, context) \ |
(eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK |
#define i915_execbuffer2_get_context_id(eb2) \ |
((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK) |
struct drm_i915_gem_pin { |
/** Handle of the buffer to be pinned. */ |
__u32 handle; |
__u32 pad; |
/** alignment required within the aperture */ |
__u64 alignment; |
/** Returned GTT offset of the buffer. */ |
__u64 offset; |
}; |
struct drm_i915_gem_unpin { |
/** Handle of the buffer to be unpinned. */ |
__u32 handle; |
__u32 pad; |
}; |
struct drm_i915_gem_busy { |
/** Handle of the buffer to check for busy */ |
__u32 handle; |
/** Return busy status (1 if busy, 0 if idle). |
* The high word is used to indicate on which rings the object |
* currently resides: |
* 16:31 - busy (r or r/w) rings (16 render, 17 bsd, 18 blt, etc) |
*/ |
__u32 busy; |
}; |
#define I915_CACHING_NONE 0 |
#define I915_CACHING_CACHED 1 |
struct drm_i915_gem_caching { |
/** |
* Handle of the buffer to set/get the caching level of. */ |
__u32 handle; |
/** |
* Cacheing level to apply or return value |
* |
* bits0-15 are for generic caching control (i.e. the above defined |
* values). bits16-31 are reserved for platform-specific variations |
* (e.g. l3$ caching on gen7). */ |
__u32 caching; |
}; |
#define I915_TILING_NONE 0 |
#define I915_TILING_X 1 |
#define I915_TILING_Y 2 |
#define I915_BIT_6_SWIZZLE_NONE 0 |
#define I915_BIT_6_SWIZZLE_9 1 |
#define I915_BIT_6_SWIZZLE_9_10 2 |
#define I915_BIT_6_SWIZZLE_9_11 3 |
#define I915_BIT_6_SWIZZLE_9_10_11 4 |
/* Not seen by userland */ |
#define I915_BIT_6_SWIZZLE_UNKNOWN 5 |
/* Seen by userland. */ |
#define I915_BIT_6_SWIZZLE_9_17 6 |
#define I915_BIT_6_SWIZZLE_9_10_17 7 |
struct drm_i915_gem_set_tiling { |
/** Handle of the buffer to have its tiling state updated */ |
__u32 handle; |
/** |
* Tiling mode for the object (I915_TILING_NONE, I915_TILING_X, |
* I915_TILING_Y). |
* |
* This value is to be set on request, and will be updated by the |
* kernel on successful return with the actual chosen tiling layout. |
* |
* The tiling mode may be demoted to I915_TILING_NONE when the system |
* has bit 6 swizzling that can't be managed correctly by GEM. |
* |
* Buffer contents become undefined when changing tiling_mode. |
*/ |
__u32 tiling_mode; |
/** |
* Stride in bytes for the object when in I915_TILING_X or |
* I915_TILING_Y. |
*/ |
__u32 stride; |
/** |
* Returned address bit 6 swizzling required for CPU access through |
* mmap mapping. |
*/ |
__u32 swizzle_mode; |
}; |
struct drm_i915_gem_get_tiling { |
/** Handle of the buffer to get tiling state for. */ |
__u32 handle; |
/** |
* Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X, |
* I915_TILING_Y). |
*/ |
__u32 tiling_mode; |
/** |
* Returned address bit 6 swizzling required for CPU access through |
* mmap mapping. |
*/ |
__u32 swizzle_mode; |
}; |
struct drm_i915_gem_get_aperture { |
/** Total size of the aperture used by i915_gem_execbuffer, in bytes */ |
__u64 aper_size; |
/** |
* Available space in the aperture used by i915_gem_execbuffer, in |
* bytes |
*/ |
__u64 aper_available_size; |
}; |
struct drm_i915_get_pipe_from_crtc_id { |
/** ID of CRTC being requested **/ |
__u32 crtc_id; |
/** pipe of requested CRTC **/ |
__u32 pipe; |
}; |
#define I915_MADV_WILLNEED 0 |
#define I915_MADV_DONTNEED 1 |
#define __I915_MADV_PURGED 2 /* internal state */ |
struct drm_i915_gem_madvise { |
/** Handle of the buffer to change the backing store advice */ |
__u32 handle; |
/* Advice: either the buffer will be needed again in the near future, |
* or wont be and could be discarded under memory pressure. |
*/ |
__u32 madv; |
/** Whether the backing store still exists. */ |
__u32 retained; |
}; |
/* flags */ |
#define I915_OVERLAY_TYPE_MASK 0xff |
#define I915_OVERLAY_YUV_PLANAR 0x01 |
#define I915_OVERLAY_YUV_PACKED 0x02 |
#define I915_OVERLAY_RGB 0x03 |
#define I915_OVERLAY_DEPTH_MASK 0xff00 |
#define I915_OVERLAY_RGB24 0x1000 |
#define I915_OVERLAY_RGB16 0x2000 |
#define I915_OVERLAY_RGB15 0x3000 |
#define I915_OVERLAY_YUV422 0x0100 |
#define I915_OVERLAY_YUV411 0x0200 |
#define I915_OVERLAY_YUV420 0x0300 |
#define I915_OVERLAY_YUV410 0x0400 |
#define I915_OVERLAY_SWAP_MASK 0xff0000 |
#define I915_OVERLAY_NO_SWAP 0x000000 |
#define I915_OVERLAY_UV_SWAP 0x010000 |
#define I915_OVERLAY_Y_SWAP 0x020000 |
#define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 |
#define I915_OVERLAY_FLAGS_MASK 0xff000000 |
#define I915_OVERLAY_ENABLE 0x01000000 |
struct drm_intel_overlay_put_image { |
/* various flags and src format description */ |
__u32 flags; |
/* source picture description */ |
__u32 bo_handle; |
/* stride values and offsets are in bytes, buffer relative */ |
__u16 stride_Y; /* stride for packed formats */ |
__u16 stride_UV; |
__u32 offset_Y; /* offset for packet formats */ |
__u32 offset_U; |
__u32 offset_V; |
/* in pixels */ |
__u16 src_width; |
__u16 src_height; |
/* to compensate the scaling factors for partially covered surfaces */ |
__u16 src_scan_width; |
__u16 src_scan_height; |
/* output crtc description */ |
__u32 crtc_id; |
__u16 dst_x; |
__u16 dst_y; |
__u16 dst_width; |
__u16 dst_height; |
}; |
/* flags */ |
#define I915_OVERLAY_UPDATE_ATTRS (1<<0) |
#define I915_OVERLAY_UPDATE_GAMMA (1<<1) |
struct drm_intel_overlay_attrs { |
__u32 flags; |
__u32 color_key; |
__s32 brightness; |
__u32 contrast; |
__u32 saturation; |
__u32 gamma0; |
__u32 gamma1; |
__u32 gamma2; |
__u32 gamma3; |
__u32 gamma4; |
__u32 gamma5; |
}; |
/* |
* Intel sprite handling |
* |
* Color keying works with a min/mask/max tuple. Both source and destination |
* color keying is allowed. |
* |
* Source keying: |
* Sprite pixels within the min & max values, masked against the color channels |
* specified in the mask field, will be transparent. All other pixels will |
* be displayed on top of the primary plane. For RGB surfaces, only the min |
* and mask fields will be used; ranged compares are not allowed. |
* |
* Destination keying: |
* Primary plane pixels that match the min value, masked against the color |
* channels specified in the mask field, will be replaced by corresponding |
* pixels from the sprite plane. |
* |
* Note that source & destination keying are exclusive; only one can be |
* active on a given plane. |
*/ |
#define I915_SET_COLORKEY_NONE (1<<0) /* disable color key matching */ |
#define I915_SET_COLORKEY_DESTINATION (1<<1) |
#define I915_SET_COLORKEY_SOURCE (1<<2) |
struct drm_intel_sprite_colorkey { |
__u32 plane_id; |
__u32 min_value; |
__u32 channel_mask; |
__u32 max_value; |
__u32 flags; |
}; |
struct drm_i915_gem_wait { |
/** Handle of BO we shall wait on */ |
__u32 bo_handle; |
__u32 flags; |
/** Number of nanoseconds to wait, Returns time remaining. */ |
__s64 timeout_ns; |
}; |
struct drm_i915_gem_context_create { |
/* output: id of new context*/ |
__u32 ctx_id; |
__u32 pad; |
}; |
struct drm_i915_gem_context_destroy { |
__u32 ctx_id; |
__u32 pad; |
}; |
struct drm_i915_reg_read { |
__u64 offset; |
__u64 val; /* Return value */ |
}; |
#endif /* _UAPI_I915_DRM_H_ */ |
/drivers/include/drm/intel-gtt.h |
---|
3,6 → 3,8 |
#ifndef _DRM_INTEL_GTT_H |
#define _DRM_INTEL_GTT_H |
struct agp_bridge_data; |
const struct intel_gtt { |
/* Size of memory reserved for graphics by the BIOS */ |
unsigned int stolen_size; |
15,19 → 17,24 |
unsigned int needs_dmar : 1; |
/* Whether we idle the gpu before mapping/unmapping */ |
unsigned int do_idle_maps : 1; |
/* Share the scratch page dma with ppgtts. */ |
dma_addr_t scratch_page_dma; |
/* for ppgtt PDE access */ |
u32 __iomem *gtt; |
/* needed for ioremap in drm/i915 */ |
phys_addr_t gma_bus_addr; |
} *intel_gtt_get(void); |
int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev, |
struct agp_bridge_data *bridge); |
void intel_gmch_remove(void); |
bool intel_enable_gtt(void); |
void intel_gtt_chipset_flush(void); |
void intel_gtt_unmap_memory(struct scatterlist *sg_list, int num_sg); |
void intel_gtt_insert_sg_entries(struct pagelist *st, unsigned int pg_start, |
unsigned int flags); |
void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries); |
int intel_gtt_map_memory(struct page **pages, unsigned int num_entries, |
struct scatterlist **sg_list, int *num_sg); |
void intel_gtt_insert_sg_entries(struct scatterlist *sg_list, |
unsigned int sg_len, |
unsigned int pg_start, |
unsigned int flags); |
void intel_gtt_insert_pages(unsigned int first_entry, unsigned int num_entries, |
struct page **pages, unsigned int flags); |
/* Special gtt memory types */ |
#define AGP_DCACHE_MEMORY 1 |
40,4 → 47,8 |
/* flag for GFDT type */ |
#define AGP_USER_CACHED_MEMORY_GFDT (1 << 3) |
#ifdef CONFIG_INTEL_IOMMU |
extern int intel_iommu_gfx_mapped; |
#endif |
#endif |
/drivers/include/drm/radeon_drm.h |
---|
33,7 → 33,7 |
#ifndef __RADEON_DRM_H__ |
#define __RADEON_DRM_H__ |
#include "drm.h" |
#include <drm/drm.h> |
/* WARNING: If you change any of these defines, make sure to change the |
* defines in the X server file (radeon_sarea.h) |
509,6 → 509,7 |
#define DRM_RADEON_GEM_SET_TILING 0x28 |
#define DRM_RADEON_GEM_GET_TILING 0x29 |
#define DRM_RADEON_GEM_BUSY 0x2a |
#define DRM_RADEON_GEM_VA 0x2b |
#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t) |
#define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START) |
807,9 → 808,19 |
#define RADEON_TILING_MICRO 0x2 |
#define RADEON_TILING_SWAP_16BIT 0x4 |
#define RADEON_TILING_SWAP_32BIT 0x8 |
#define RADEON_TILING_SURFACE 0x10 /* this object requires a surface |
* when mapped - i.e. front buffer */ |
/* this object requires a surface when mapped - i.e. front buffer */ |
#define RADEON_TILING_SURFACE 0x10 |
#define RADEON_TILING_MICRO_SQUARE 0x20 |
#define RADEON_TILING_EG_BANKW_SHIFT 8 |
#define RADEON_TILING_EG_BANKW_MASK 0xf |
#define RADEON_TILING_EG_BANKH_SHIFT 12 |
#define RADEON_TILING_EG_BANKH_MASK 0xf |
#define RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT 16 |
#define RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK 0xf |
#define RADEON_TILING_EG_TILE_SPLIT_SHIFT 24 |
#define RADEON_TILING_EG_TILE_SPLIT_MASK 0xf |
#define RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT 28 |
#define RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK 0xf |
struct drm_radeon_gem_set_tiling { |
uint32_t handle; |
897,6 → 908,7 |
#define RADEON_CHUNK_ID_RELOCS 0x01 |
#define RADEON_CHUNK_ID_IB 0x02 |
#define RADEON_CHUNK_ID_FLAGS 0x03 |
#define RADEON_CHUNK_ID_CONST_IB 0x04 |
/* The first dword of RADEON_CHUNK_ID_FLAGS is a uint32 of these flags: */ |
#define RADEON_CS_KEEP_TILING_FLAGS 0x01 |
914,7 → 926,6 |
}; |
/* drm_radeon_cs_reloc.flags */ |
#define RADEON_RELOC_DONT_SYNC 0x01 |
struct drm_radeon_cs_reloc { |
uint32_t handle; |
951,6 → 962,10 |
#define RADEON_INFO_VA_START 0x0e |
/* maximum size of ib using the virtual memory cs */ |
#define RADEON_INFO_IB_VM_MAX_SIZE 0x0f |
/* max pipes - needed for compute shaders */ |
#define RADEON_INFO_MAX_PIPES 0x10 |
/* timestamp for GL_ARB_timer_query (OpenGL), returns the current GPU clock */ |
#define RADEON_INFO_TIMESTAMP 0x11 |
struct drm_radeon_info { |
uint32_t request; |
/drivers/include/drm/ttm/ttm_bo_api.h |
---|
81,14 → 81,17 |
*/ |
struct ttm_mem_reg { |
struct drm_mm_node *mm_node; |
void *mm_node; |
unsigned long start; |
unsigned long size; |
unsigned long num_pages; |
uint32_t page_alignment; |
uint32_t mem_type; |
uint32_t placement; |
// struct ttm_bus_placement bus; |
}; |
/** |
* enum ttm_bo_type |
* |
/drivers/include/linux/asm/alternative.h |
---|
129,7 → 129,7 |
* use this macro(s) if you need more than one output parameter |
* in alternative_io |
*/ |
#define ASM_OUTPUT2(a, b) a, b |
#define ASM_OUTPUT2(a) a |
struct paravirt_patch_site; |
#ifdef CONFIG_PARAVIRT |
/drivers/include/linux/asm/atomic_32.h |
---|
266,8 → 266,8 |
u64 __aligned(8) counter; |
} atomic64_t; |
#define ATOMIC64_INIT(val) { (val) } |
extern u64 atomic64_cmpxchg(atomic64_t *ptr, u64 old_val, u64 new_val); |
/** |
278,8 → 278,22 |
* Atomically xchgs the value of @ptr to @new_val and returns |
* the old value. |
*/ |
extern u64 atomic64_xchg(atomic64_t *ptr, u64 new_val); |
static inline long long atomic64_xchg(atomic64_t *v, long long n) |
{ |
long long o; |
unsigned high = (unsigned)(n >> 32); |
unsigned low = (unsigned)n; |
asm volatile( |
"1: \n\t" |
"cmpxchg8b (%%esi) \n\t" |
"jnz 1b \n\t" |
:"=&A" (o) |
:"S" (v), "b" (low), "c" (high) |
: "memory", "cc"); |
return o; |
} |
/** |
* atomic64_set - set atomic64 variable |
* @ptr: pointer to type atomic64_t |
287,8 → 301,21 |
* |
* Atomically sets the value of @ptr to @new_val. |
*/ |
extern void atomic64_set(atomic64_t *ptr, u64 new_val); |
static inline void atomic64_set(atomic64_t *v, long long i) |
{ |
unsigned high = (unsigned)(i >> 32); |
unsigned low = (unsigned)i; |
asm volatile ( |
"1: \n\t" |
"cmpxchg8b (%%esi) \n\t" |
"jnz 1b \n\t" |
: |
:"S" (v), "b" (low), "c" (high) |
: "eax", "edx", "memory", "cc"); |
} |
/** |
* atomic64_read - read atomic64 variable |
* @ptr: pointer to type atomic64_t |
317,7 → 344,6 |
return res; |
} |
extern u64 atomic64_read(atomic64_t *ptr); |
/** |
* atomic64_add_return - add and return |
/drivers/include/linux/asm/bitops.h |
---|
15,6 → 15,8 |
#include <linux/compiler.h> |
#include <asm/alternative.h> |
#define BIT_64(n) (U64_C(1) << (n)) |
/* |
* These have to be done with inline assembly: that way the bit-setting |
* is guaranteed to be atomic. All bit operations return 0 if the bit |
262,6 → 264,13 |
* This operation is non-atomic and can be reordered. |
* If two examples of this operation race, one can appear to succeed |
* but actually fail. You must protect multiple accesses with a lock. |
* |
* Note: the operation is performed atomically with respect to |
* the local CPU, but not other CPUs. Portable code should not |
* rely on this behaviour. |
* KVM relies on this behaviour on x86 for modifying memory that is also |
* accessed from a hypervisor on the same CPU if running in a VM: don't change |
* this without also updating arch/x86/kernel/kvm.c |
*/ |
static inline int __test_and_clear_bit(int nr, volatile unsigned long *addr) |
{ |
309,7 → 318,7 |
static __always_inline int constant_test_bit(unsigned int nr, const volatile unsigned long *addr) |
{ |
return ((1UL << (nr % BITS_PER_LONG)) & |
(((unsigned long *)addr)[nr / BITS_PER_LONG])) != 0; |
(addr[nr / BITS_PER_LONG])) != 0; |
} |
static inline int variable_test_bit(int nr, volatile const unsigned long *addr) |
346,7 → 355,7 |
*/ |
static inline unsigned long __ffs(unsigned long word) |
{ |
asm("bsf %1,%0" |
asm("rep; bsf %1,%0" |
: "=r" (word) |
: "rm" (word)); |
return word; |
360,7 → 369,7 |
*/ |
static inline unsigned long ffz(unsigned long word) |
{ |
asm("bsf %1,%0" |
asm("rep; bsf %1,%0" |
: "=r" (word) |
: "r" (~word)); |
return word; |
380,6 → 389,8 |
return word; |
} |
#undef ADDR |
#ifdef __KERNEL__ |
/** |
* ffs - find first set bit in word |
398,7 → 409,7 |
#ifdef CONFIG_X86_CMOV |
asm("bsfl %1,%0\n\t" |
"cmovzl %2,%0" |
: "=r" (r) : "rm" (x), "r" (-1)); |
: "=&r" (r) : "rm" (x), "r" (-1)); |
#else |
asm("bsfl %1,%0\n\t" |
"jnz 1f\n\t" |
/drivers/include/linux/asm/cpufeature.h |
---|
6,7 → 6,7 |
#include <asm/required-features.h> |
#define NCAPINTS 9 /* N 32-bit words worth of info */ |
#define NCAPINTS 10 /* N 32-bit words worth of info */ |
/* |
* Note: If the comment begins with a quoted string, that string is used |
89,7 → 89,7 |
#define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* "" Lfence synchronizes RDTSC */ |
#define X86_FEATURE_11AP (3*32+19) /* "" Bad local APIC aka 11AP */ |
#define X86_FEATURE_NOPL (3*32+20) /* The NOPL (0F 1F) instructions */ |
#define X86_FEATURE_AMDC1E (3*32+21) /* AMD C1E detected */ |
/* 21 available, was AMD_C1E */ |
#define X86_FEATURE_XTOPOLOGY (3*32+22) /* cpu topology enum extensions */ |
#define X86_FEATURE_TSC_RELIABLE (3*32+23) /* TSC is known to be reliable */ |
#define X86_FEATURE_NONSTOP_TSC (3*32+24) /* TSC does not stop in C states */ |
97,6 → 97,7 |
#define X86_FEATURE_EXTD_APICID (3*32+26) /* has extended APICID (8 bits) */ |
#define X86_FEATURE_AMD_DCM (3*32+27) /* multi-node processor */ |
#define X86_FEATURE_APERFMPERF (3*32+28) /* APERFMPERF */ |
#define X86_FEATURE_EAGER_FPU (3*32+29) /* "eagerfpu" Non lazy FPU restore */ |
/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ |
#define X86_FEATURE_XMM3 (4*32+ 0) /* "pni" SSE-3 */ |
114,6 → 115,7 |
#define X86_FEATURE_CX16 (4*32+13) /* CMPXCHG16B */ |
#define X86_FEATURE_XTPR (4*32+14) /* Send Task Priority Messages */ |
#define X86_FEATURE_PDCM (4*32+15) /* Performance Capabilities */ |
#define X86_FEATURE_PCID (4*32+17) /* Process Context Identifiers */ |
#define X86_FEATURE_DCA (4*32+18) /* Direct Cache Access */ |
#define X86_FEATURE_XMM4_1 (4*32+19) /* "sse4_1" SSE-4.1 */ |
#define X86_FEATURE_XMM4_2 (4*32+20) /* "sse4_2" SSE-4.2 */ |
120,10 → 122,13 |
#define X86_FEATURE_X2APIC (4*32+21) /* x2APIC */ |
#define X86_FEATURE_MOVBE (4*32+22) /* MOVBE instruction */ |
#define X86_FEATURE_POPCNT (4*32+23) /* POPCNT instruction */ |
#define X86_FEATURE_TSC_DEADLINE_TIMER (4*32+24) /* Tsc deadline timer */ |
#define X86_FEATURE_AES (4*32+25) /* AES instructions */ |
#define X86_FEATURE_XSAVE (4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */ |
#define X86_FEATURE_OSXSAVE (4*32+27) /* "" XSAVE enabled in the OS */ |
#define X86_FEATURE_AVX (4*32+28) /* Advanced Vector Extensions */ |
#define X86_FEATURE_F16C (4*32+29) /* 16-bit fp conversions */ |
#define X86_FEATURE_RDRAND (4*32+30) /* The RDRAND instruction */ |
#define X86_FEATURE_HYPERVISOR (4*32+31) /* Running on a hypervisor */ |
/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */ |
150,24 → 155,63 |
#define X86_FEATURE_3DNOWPREFETCH (6*32+ 8) /* 3DNow prefetch instructions */ |
#define X86_FEATURE_OSVW (6*32+ 9) /* OS Visible Workaround */ |
#define X86_FEATURE_IBS (6*32+10) /* Instruction Based Sampling */ |
#define X86_FEATURE_SSE5 (6*32+11) /* SSE-5 */ |
#define X86_FEATURE_XOP (6*32+11) /* extended AVX instructions */ |
#define X86_FEATURE_SKINIT (6*32+12) /* SKINIT/STGI instructions */ |
#define X86_FEATURE_WDT (6*32+13) /* Watchdog timer */ |
#define X86_FEATURE_LWP (6*32+15) /* Light Weight Profiling */ |
#define X86_FEATURE_FMA4 (6*32+16) /* 4 operands MAC instructions */ |
#define X86_FEATURE_TCE (6*32+17) /* translation cache extension */ |
#define X86_FEATURE_NODEID_MSR (6*32+19) /* NodeId MSR */ |
#define X86_FEATURE_TBM (6*32+21) /* trailing bit manipulations */ |
#define X86_FEATURE_TOPOEXT (6*32+22) /* topology extensions CPUID leafs */ |
#define X86_FEATURE_PERFCTR_CORE (6*32+23) /* core performance counter extensions */ |
/* |
* Auxiliary flags: Linux defined - For features scattered in various |
* CPUID levels like 0x6, 0xA etc |
* CPUID levels like 0x6, 0xA etc, word 7 |
*/ |
#define X86_FEATURE_IDA (7*32+ 0) /* Intel Dynamic Acceleration */ |
#define X86_FEATURE_ARAT (7*32+ 1) /* Always Running APIC Timer */ |
#define X86_FEATURE_CPB (7*32+ 2) /* AMD Core Performance Boost */ |
#define X86_FEATURE_EPB (7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */ |
#define X86_FEATURE_XSAVEOPT (7*32+ 4) /* Optimized Xsave */ |
#define X86_FEATURE_PLN (7*32+ 5) /* Intel Power Limit Notification */ |
#define X86_FEATURE_PTS (7*32+ 6) /* Intel Package Thermal Status */ |
#define X86_FEATURE_DTHERM (7*32+ 7) /* Digital Thermal Sensor */ |
#define X86_FEATURE_HW_PSTATE (7*32+ 8) /* AMD HW-PState */ |
/* Virtualization flags: Linux defined */ |
/* Virtualization flags: Linux defined, word 8 */ |
#define X86_FEATURE_TPR_SHADOW (8*32+ 0) /* Intel TPR Shadow */ |
#define X86_FEATURE_VNMI (8*32+ 1) /* Intel Virtual NMI */ |
#define X86_FEATURE_FLEXPRIORITY (8*32+ 2) /* Intel FlexPriority */ |
#define X86_FEATURE_EPT (8*32+ 3) /* Intel Extended Page Table */ |
#define X86_FEATURE_VPID (8*32+ 4) /* Intel Virtual Processor ID */ |
#define X86_FEATURE_NPT (8*32+ 5) /* AMD Nested Page Table support */ |
#define X86_FEATURE_LBRV (8*32+ 6) /* AMD LBR Virtualization support */ |
#define X86_FEATURE_SVML (8*32+ 7) /* "svm_lock" AMD SVM locking MSR */ |
#define X86_FEATURE_NRIPS (8*32+ 8) /* "nrip_save" AMD SVM next_rip save */ |
#define X86_FEATURE_TSCRATEMSR (8*32+ 9) /* "tsc_scale" AMD TSC scaling support */ |
#define X86_FEATURE_VMCBCLEAN (8*32+10) /* "vmcb_clean" AMD VMCB clean bits support */ |
#define X86_FEATURE_FLUSHBYASID (8*32+11) /* AMD flush-by-ASID support */ |
#define X86_FEATURE_DECODEASSISTS (8*32+12) /* AMD Decode Assists support */ |
#define X86_FEATURE_PAUSEFILTER (8*32+13) /* AMD filtered pause intercept */ |
#define X86_FEATURE_PFTHRESHOLD (8*32+14) /* AMD pause filter threshold */ |
/* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 9 */ |
#define X86_FEATURE_FSGSBASE (9*32+ 0) /* {RD/WR}{FS/GS}BASE instructions*/ |
#define X86_FEATURE_BMI1 (9*32+ 3) /* 1st group bit manipulation extensions */ |
#define X86_FEATURE_HLE (9*32+ 4) /* Hardware Lock Elision */ |
#define X86_FEATURE_AVX2 (9*32+ 5) /* AVX2 instructions */ |
#define X86_FEATURE_SMEP (9*32+ 7) /* Supervisor Mode Execution Protection */ |
#define X86_FEATURE_BMI2 (9*32+ 8) /* 2nd group bit manipulation extensions */ |
#define X86_FEATURE_ERMS (9*32+ 9) /* Enhanced REP MOVSB/STOSB */ |
#define X86_FEATURE_INVPCID (9*32+10) /* Invalidate Processor Context ID */ |
#define X86_FEATURE_RTM (9*32+11) /* Restricted Transactional Memory */ |
#define X86_FEATURE_RDSEED (9*32+18) /* The RDSEED instruction */ |
#define X86_FEATURE_ADX (9*32+19) /* The ADCX and ADOX instructions */ |
#define X86_FEATURE_SMAP (9*32+20) /* Supervisor Mode Access Prevention */ |
#if defined(__KERNEL__) && !defined(__ASSEMBLY__) |
#include <linux/bitops.h> |
178,8 → 222,7 |
#define test_cpu_cap(c, bit) \ |
test_bit(bit, (unsigned long *)((c)->x86_capability)) |
#define cpu_has(c, bit) \ |
(__builtin_constant_p(bit) && \ |
#define REQUIRED_MASK_BIT_SET(bit) \ |
( (((bit)>>5)==0 && (1UL<<((bit)&31) & REQUIRED_MASK0)) || \ |
(((bit)>>5)==1 && (1UL<<((bit)&31) & REQUIRED_MASK1)) || \ |
(((bit)>>5)==2 && (1UL<<((bit)&31) & REQUIRED_MASK2)) || \ |
187,10 → 230,18 |
(((bit)>>5)==4 && (1UL<<((bit)&31) & REQUIRED_MASK4)) || \ |
(((bit)>>5)==5 && (1UL<<((bit)&31) & REQUIRED_MASK5)) || \ |
(((bit)>>5)==6 && (1UL<<((bit)&31) & REQUIRED_MASK6)) || \ |
(((bit)>>5)==7 && (1UL<<((bit)&31) & REQUIRED_MASK7)) ) \ |
? 1 : \ |
(((bit)>>5)==7 && (1UL<<((bit)&31) & REQUIRED_MASK7)) || \ |
(((bit)>>5)==8 && (1UL<<((bit)&31) & REQUIRED_MASK8)) || \ |
(((bit)>>5)==9 && (1UL<<((bit)&31) & REQUIRED_MASK9)) ) |
#define cpu_has(c, bit) \ |
(__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \ |
test_cpu_cap(c, bit)) |
#define this_cpu_has(bit) \ |
(__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \ |
x86_this_cpu_test_bit(bit, (unsigned long *)&cpu_info.x86_capability)) |
#define boot_cpu_has(bit) cpu_has(&boot_cpu_data, bit) |
#define set_cpu_cap(c, bit) set_bit(bit, (unsigned long *)((c)->x86_capability)) |
219,7 → 270,9 |
#define cpu_has_xmm boot_cpu_has(X86_FEATURE_XMM) |
#define cpu_has_xmm2 boot_cpu_has(X86_FEATURE_XMM2) |
#define cpu_has_xmm3 boot_cpu_has(X86_FEATURE_XMM3) |
#define cpu_has_ssse3 boot_cpu_has(X86_FEATURE_SSSE3) |
#define cpu_has_aes boot_cpu_has(X86_FEATURE_AES) |
#define cpu_has_avx boot_cpu_has(X86_FEATURE_AVX) |
#define cpu_has_ht boot_cpu_has(X86_FEATURE_HT) |
#define cpu_has_mp boot_cpu_has(X86_FEATURE_MP) |
#define cpu_has_nx boot_cpu_has(X86_FEATURE_NX) |
247,8 → 300,14 |
#define cpu_has_xmm4_2 boot_cpu_has(X86_FEATURE_XMM4_2) |
#define cpu_has_x2apic boot_cpu_has(X86_FEATURE_X2APIC) |
#define cpu_has_xsave boot_cpu_has(X86_FEATURE_XSAVE) |
#define cpu_has_xsaveopt boot_cpu_has(X86_FEATURE_XSAVEOPT) |
#define cpu_has_osxsave boot_cpu_has(X86_FEATURE_OSXSAVE) |
#define cpu_has_hypervisor boot_cpu_has(X86_FEATURE_HYPERVISOR) |
#define cpu_has_pclmulqdq boot_cpu_has(X86_FEATURE_PCLMULQDQ) |
#define cpu_has_perfctr_core boot_cpu_has(X86_FEATURE_PERFCTR_CORE) |
#define cpu_has_cx8 boot_cpu_has(X86_FEATURE_CX8) |
#define cpu_has_cx16 boot_cpu_has(X86_FEATURE_CX16) |
#define cpu_has_eager_fpu boot_cpu_has(X86_FEATURE_EAGER_FPU) |
#if defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_64) |
# define cpu_has_invlpg 1 |
/drivers/include/linux/asm/div64.h |
---|
4,6 → 4,7 |
#ifdef CONFIG_X86_32 |
#include <linux/types.h> |
#include <linux/log2.h> |
/* |
* do_div() is NOT a C function. It wants to return |
21,6 → 22,10 |
({ \ |
unsigned long __upper, __low, __high, __mod, __base; \ |
__base = (base); \ |
if (__builtin_constant_p(__base) && is_power_of_2(__base)) { \ |
__mod = n & (__base - 1); \ |
n >>= ilog2(__base); \ |
} else { \ |
asm("":"=a" (__low), "=d" (__high) : "A" (n)); \ |
__upper = __high; \ |
if (__high) { \ |
30,6 → 35,7 |
asm("divl %2":"=a" (__low), "=d" (__mod) \ |
: "rm" (__base), "0" (__low), "1" (__upper)); \ |
asm("":"=A" (n) : "a" (__low), "d" (__high)); \ |
} \ |
__mod; \ |
}) |
/drivers/include/linux/asm/required-features.h |
---|
84,5 → 84,7 |
#define REQUIRED_MASK5 0 |
#define REQUIRED_MASK6 0 |
#define REQUIRED_MASK7 0 |
#define REQUIRED_MASK8 0 |
#define REQUIRED_MASK9 0 |
#endif /* _ASM_X86_REQUIRED_FEATURES_H */ |
/drivers/include/linux/backlight.h |
---|
--- linux/bitops.h (revision 3030) |
+++ linux/bitops.h (revision 3031) |
@@ -26,6 +26,23 @@ |
(bit) < (size); \ |
(bit) = find_next_bit((addr), (size), (bit) + 1)) |
+/* same as for_each_set_bit() but use bit as value to start with */ |
+#define for_each_set_bit_from(bit, addr, size) \ |
+ for ((bit) = find_next_bit((addr), (size), (bit)); \ |
+ (bit) < (size); \ |
+ (bit) = find_next_bit((addr), (size), (bit) + 1)) |
+ |
+#define for_each_clear_bit(bit, addr, size) \ |
+ for ((bit) = find_first_zero_bit((addr), (size)); \ |
+ (bit) < (size); \ |
+ (bit) = find_next_zero_bit((addr), (size), (bit) + 1)) |
+ |
+/* same as for_each_clear_bit() but use bit as value to start with */ |
+#define for_each_clear_bit_from(bit, addr, size) \ |
+ for ((bit) = find_next_zero_bit((addr), (size), (bit)); \ |
+ (bit) < (size); \ |
+ (bit) = find_next_zero_bit((addr), (size), (bit) + 1)) |
+ |
static __inline__ int get_bitmask_order(unsigned int count) |
{ |
int order; |
@@ -50,6 +67,26 @@ |
} |
/** |
+ * rol64 - rotate a 64-bit value left |
+ * @word: value to rotate |
+ * @shift: bits to roll |
+ */ |
+static inline __u64 rol64(__u64 word, unsigned int shift) |
+{ |
+ return (word << shift) | (word >> (64 - shift)); |
+} |
+ |
+/** |
+ * ror64 - rotate a 64-bit value right |
+ * @word: value to rotate |
+ * @shift: bits to roll |
+ */ |
+static inline __u64 ror64(__u64 word, unsigned int shift) |
+{ |
+ return (word >> shift) | (word << (64 - shift)); |
+} |
+ |
+/** |
* rol32 - rotate a 32-bit value left |
* @word: value to rotate |
* @shift: bits to roll |
/drivers/include/linux/bug.h |
---|
0,0 → 1,12 |
#ifndef _ASM_GENERIC_BUG_H |
#define _ASM_GENERIC_BUG_H |
#define WARN(condition, format...) ({ \ |
int __ret_warn_on = !!(condition); \ |
unlikely(__ret_warn_on); \ |
}) |
#endif |
/drivers/include/linux/compiler-gcc.h |
---|
83,6 → 83,7 |
#define __pure __attribute__((pure)) |
#define __aligned(x) __attribute__((aligned(x))) |
#define __printf(a,b) __attribute__((format(printf,a,b))) |
#define __scanf(a, b) __attribute__((format(scanf, a, b))) |
#define noinline __attribute__((noinline)) |
#define __attribute_const__ __attribute__((__const__)) |
#define __maybe_unused __attribute__((unused)) |
/drivers/include/linux/compiler-gcc4.h |
---|
29,6 → 29,7 |
the kernel context */ |
#define __cold __attribute__((__cold__)) |
#define __linktime_error(message) __attribute__((__error__(message))) |
#if __GNUC_MINOR__ >= 5 |
/* |
48,10 → 49,17 |
#endif |
#endif |
#if __GNUC_MINOR__ >= 6 |
/* |
* Tell the optimizer that something else uses this function or variable. |
*/ |
#define __visible __attribute__((externally_visible)) |
#endif |
#if __GNUC_MINOR__ > 0 |
#define __compiletime_object_size(obj) __builtin_object_size(obj, 0) |
#endif |
#if __GNUC_MINOR__ >= 4 && !defined(__CHECKER__) |
#if __GNUC_MINOR__ >= 3 && !defined(__CHECKER__) |
#define __compiletime_warning(message) __attribute__((warning(message))) |
#define __compiletime_error(message) __attribute__((error(message))) |
#endif |
/drivers/include/linux/compiler.h |
---|
236,7 → 236,7 |
/* |
* Rather then using noinline to prevent stack consumption, use |
* noinline_for_stack instead. For documentaiton reasons. |
* noinline_for_stack instead. For documentation reasons. |
*/ |
#define noinline_for_stack noinline |
278,6 → 278,10 |
# define __section(S) __attribute__ ((__section__(#S))) |
#endif |
#ifndef __visible |
#define __visible |
#endif |
/* Are two types/vars the same type (ignoring qualifiers)? */ |
#ifndef __same_type |
# define __same_type(a, b) __builtin_types_compatible_p(typeof(a), typeof(b)) |
293,7 → 297,9 |
#ifndef __compiletime_error |
# define __compiletime_error(message) |
#endif |
#ifndef __linktime_error |
# define __linktime_error(message) |
#endif |
/* |
* Prevent the compiler from merging or refetching accesses. The compiler |
* is also forbidden from reordering successive instances of ACCESS_ONCE(), |
/drivers/include/linux/delay.h |
---|
--- linux/dmapool.h (revision 3030) |
+++ linux/dmapool.h (revision 3031) |
@@ -21,6 +21,12 @@ |
void dma_pool_free(struct dma_pool *pool, void *vaddr, dma_addr_t addr); |
+/* |
+ * Managed DMA pool |
+ */ |
+struct dma_pool *dmam_pool_create(const char *name, struct device *dev, |
+ size_t size, size_t align, size_t allocation); |
+void dmam_pool_destroy(struct dma_pool *pool); |
#endif |
/drivers/include/linux/errno-base.h |
---|
0,0 → 1,39 |
#ifndef _ASM_GENERIC_ERRNO_BASE_H |
#define _ASM_GENERIC_ERRNO_BASE_H |
#define EPERM 1 /* Operation not permitted */ |
#define ENOENT 2 /* No such file or directory */ |
#define ESRCH 3 /* No such process */ |
#define EINTR 4 /* Interrupted system call */ |
#define EIO 5 /* I/O error */ |
#define ENXIO 6 /* No such device or address */ |
#define E2BIG 7 /* Argument list too long */ |
#define ENOEXEC 8 /* Exec format error */ |
#define EBADF 9 /* Bad file number */ |
#define ECHILD 10 /* No child processes */ |
#define EAGAIN 11 /* Try again */ |
#define ENOMEM 12 /* Out of memory */ |
#define EACCES 13 /* Permission denied */ |
#define EFAULT 14 /* Bad address */ |
#define ENOTBLK 15 /* Block device required */ |
#define EBUSY 16 /* Device or resource busy */ |
#define EEXIST 17 /* File exists */ |
#define EXDEV 18 /* Cross-device link */ |
#define ENODEV 19 /* No such device */ |
#define ENOTDIR 20 /* Not a directory */ |
#define EISDIR 21 /* Is a directory */ |
#define EINVAL 22 /* Invalid argument */ |
#define ENFILE 23 /* File table overflow */ |
#define EMFILE 24 /* Too many open files */ |
#define ENOTTY 25 /* Not a typewriter */ |
#define ETXTBSY 26 /* Text file busy */ |
#define EFBIG 27 /* File too large */ |
#define ENOSPC 28 /* No space left on device */ |
#define ESPIPE 29 /* Illegal seek */ |
#define EROFS 30 /* Read-only file system */ |
#define EMLINK 31 /* Too many links */ |
#define EPIPE 32 /* Broken pipe */ |
#define EDOM 33 /* Math argument out of domain of func */ |
#define ERANGE 34 /* Math result not representable */ |
#endif |
/drivers/include/linux/export.h |
---|
0,0 → 1,19 |
#ifndef _LINUX_EXPORT_H |
#define _LINUX_EXPORT_H |
/* |
* Export symbols from the kernel to modules. Forked from module.h |
* to reduce the amount of pointless cruft we feed to gcc when only |
* exporting a simple symbol or two. |
* |
* If you feel the need to add #include <linux/foo.h> to this file |
* then you are doing something wrong and should go away silently. |
*/ |
#define EXPORT_SYMBOL(sym) |
#define EXPORT_SYMBOL_GPL(sym) |
#define EXPORT_SYMBOL_GPL_FUTURE(sym) |
#define EXPORT_UNUSED_SYMBOL(sym) |
#define EXPORT_UNUSED_SYMBOL_GPL(sym) |
#define THIS_MODULE ((struct module *)0) |
#endif /* _LINUX_EXPORT_H */ |
/drivers/include/linux/fb.h |
---|
549,6 → 549,10 |
#define FB_EVENT_FB_UNBIND 0x0E |
/* CONSOLE-SPECIFIC: remap all consoles to new fb - for vga switcheroo */ |
#define FB_EVENT_REMAP_ALL_CONSOLE 0x0F |
/* A hardware display blank early change occured */ |
#define FB_EARLY_EVENT_BLANK 0x10 |
/* A hardware display blank revert early change occured */ |
#define FB_R_EARLY_EVENT_BLANK 0x11 |
struct fb_event { |
struct fb_info *info; |
599,6 → 603,7 |
struct mutex lock; /* mutex that protects the page list */ |
struct list_head pagelist; /* list of touched pages */ |
/* callback */ |
void (*first_io)(struct fb_info *info); |
void (*deferred_io)(struct fb_info *info, struct list_head *pagelist); |
}; |
#endif |
990,6 → 995,7 |
/* drivers/video/fbmem.c */ |
extern int register_framebuffer(struct fb_info *fb_info); |
extern int unregister_framebuffer(struct fb_info *fb_info); |
extern int unlink_framebuffer(struct fb_info *fb_info); |
extern void remove_conflicting_framebuffers(struct apertures_struct *a, |
const char *name, bool primary); |
extern int fb_prepare_logo(struct fb_info *fb_info, int rotate); |
1112,6 → 1118,7 |
/* drivers/video/fbcmap.c */ |
extern int fb_alloc_cmap(struct fb_cmap *cmap, int len, int transp); |
extern int fb_alloc_cmap_gfp(struct fb_cmap *cmap, int len, int transp, gfp_t flags); |
extern void fb_dealloc_cmap(struct fb_cmap *cmap); |
extern int fb_copy_cmap(const struct fb_cmap *from, struct fb_cmap *to); |
extern int fb_cmap_to_user(const struct fb_cmap *from, struct fb_cmap_user *to); |
1139,6 → 1146,7 |
extern const char *fb_mode_option; |
extern const struct fb_videomode vesa_modes[]; |
extern const struct fb_videomode cea_modes[64]; |
struct fb_modelist { |
struct list_head list; |
/drivers/include/linux/i2c-algo-bit.h |
---|
15,7 → 15,8 |
You should have received a copy of the GNU General Public License |
along with this program; if not, write to the Free Software |
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ |
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, |
MA 02110-1301 USA. */ |
/* ------------------------------------------------------------------------- */ |
/* With some changes from Kyösti Mälkki <kmalkki@cc.hut.fi> and even |
49,5 → 50,6 |
int i2c_bit_add_bus(struct i2c_adapter *); |
int i2c_bit_add_numbered_bus(struct i2c_adapter *); |
extern const struct i2c_algorithm i2c_bit_algo; |
#endif /* _LINUX_I2C_ALGO_BIT_H */ |
/drivers/include/linux/i2c.h |
---|
17,12 → 17,12 |
You should have received a copy of the GNU General Public License |
along with this program; if not, write to the Free Software |
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ |
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, |
MA 02110-1301 USA. */ |
/* ------------------------------------------------------------------------- */ |
/* With some changes from Kyösti Mälkki <kmalkki@cc.hut.fi> and |
Frodo Looijaard <frodol@dds.nl> */ |
#ifndef _LINUX_I2C_H |
#define _LINUX_I2C_H |
32,6 → 32,8 |
#include <linux/i2c-id.h> |
#include <linux/mod_devicetable.h> |
extern struct bus_type i2c_bus_type; |
extern struct device_type i2c_adapter_type; |
/* --- General options ------------------------------------------------ */ |
70,7 → 72,7 |
* The driver.owner field should be set to the module owner of this driver. |
* The driver.name field should be set to the name of this driver. |
* |
* For automatic device detection, both @detect and @address_data must |
* For automatic device detection, both @detect and @address_list must |
* be defined. @class should also be set, otherwise only devices forced |
* with module parameters will be created. The detect function must |
* fill at least the name field of the i2c_board_info structure it is |
271,6 → 273,8 |
#define I2C_CLIENT_TEN 0x10 /* we have a ten bit chip address */ |
/* Must equal I2C_M_TEN below */ |
#define I2C_CLIENT_WAKE 0x80 /* for board_info; true iff can wake */ |
#define I2C_CLIENT_SCCB 0x9000 /* Use Omnivision SCCB protocol */ |
/* Must match I2C_M_STOP|IGNORE_NAK */ |
/* i2c adapter classes (bitmask) */ |
#define I2C_CLASS_HWMON (1<<0) /* lm_sensors, ... */ |
/drivers/include/linux/ioport.h |
---|
35,8 → 35,9 |
#define IORESOURCE_BITS 0x000000ff /* Bus-specific bits */ |
#define IORESOURCE_TYPE_BITS 0x00001f00 /* Resource type */ |
#define IORESOURCE_IO 0x00000100 |
#define IORESOURCE_IO 0x00000100 /* PCI/ISA I/O ports */ |
#define IORESOURCE_MEM 0x00000200 |
#define IORESOURCE_REG 0x00000300 /* Register offsets */ |
#define IORESOURCE_IRQ 0x00000400 |
#define IORESOURCE_DMA 0x00000800 |
#define IORESOURCE_BUS 0x00001000 |
/drivers/include/linux/jiffies.h |
---|
71,16 → 71,10 |
/* a value TUSEC for TICK_USEC (can be set bij adjtimex) */ |
#define TICK_USEC_TO_NSEC(TUSEC) (SH_DIV (TUSEC * USER_HZ * 1000, ACTHZ, 8)) |
#define jiffies GetTimerTicks() |
#if (BITS_PER_LONG < 64) |
u64 get_jiffies_64(void); |
#else |
static inline u64 get_jiffies_64(void) |
{ |
return (u64)jiffies; |
return (u64)GetTimerTicks(); |
} |
#endif |
/* |
* These inlines deal with timer wrapping correctly. You are |
295,7 → 289,13 |
extern unsigned long timeval_to_jiffies(const struct timeval *value); |
extern void jiffies_to_timeval(const unsigned long jiffies, |
struct timeval *value); |
extern clock_t jiffies_to_clock_t(unsigned long x); |
static inline clock_t jiffies_delta_to_clock_t(long delta) |
{ |
return jiffies_to_clock_t(max(0L, delta)); |
} |
extern unsigned long clock_t_to_jiffies(unsigned long x); |
extern u64 jiffies_64_to_clock_t(u64 x); |
extern u64 nsec_to_clock_t(u64 x); |
/drivers/include/linux/kernel.h |
---|
29,6 → 29,7 |
#define LLONG_MAX ((long long)(~0ULL>>1)) |
#define LLONG_MIN (-LLONG_MAX - 1) |
#define ULLONG_MAX (~0ULL) |
#define SIZE_MAX (~(size_t)0) |
#define ALIGN(x,a) __ALIGN_MASK(x,(typeof(x))(a)-1) |
#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask)) |
306,7 → 307,10 |
writel(val >> 32, addr+4); |
} |
#define swap(a, b) \ |
do { typeof(a) __tmp = (a); (a) = (b); (b) = __tmp; } while (0) |
#define mmiowb() barrier() |
#define dev_err(dev, format, arg...) \ |
329,6 → 333,34 |
unsigned int dma_length; |
}; |
struct sg_table { |
struct scatterlist *sgl; /* the list */ |
unsigned int nents; /* number of mapped entries */ |
unsigned int orig_nents; /* original size of list */ |
}; |
#define SG_MAX_SINGLE_ALLOC (4096 / sizeof(struct scatterlist)) |
struct scatterlist *sg_next(struct scatterlist *sg); |
#define sg_dma_address(sg) ((sg)->dma_address) |
#define sg_dma_len(sg) ((sg)->length) |
#define sg_is_chain(sg) ((sg)->page_link & 0x01) |
#define sg_is_last(sg) ((sg)->page_link & 0x02) |
#define sg_chain_ptr(sg) \ |
((struct scatterlist *) ((sg)->page_link & ~0x03)) |
static inline addr_t sg_page(struct scatterlist *sg) |
{ |
return (addr_t)((sg)->page_link & ~0x3); |
} |
#define for_each_sg(sglist, sg, nr, __i) \ |
for (__i = 0, sg = (sglist); __i < (nr); __i++, sg = sg_next(sg)) |
struct page |
{ |
unsigned int addr; |
347,6 → 379,10 |
*/ |
}; |
struct pagelist { |
dma_addr_t *page; |
unsigned int nents; |
}; |
#endif |
/drivers/include/linux/log2.h |
---|
0,0 → 1,208 |
/* Integer base 2 logarithm calculation |
* |
* Copyright (C) 2006 Red Hat, Inc. All Rights Reserved. |
* Written by David Howells (dhowells@redhat.com) |
* |
* This program is free software; you can redistribute it and/or |
* modify it under the terms of the GNU General Public License |
* as published by the Free Software Foundation; either version |
* 2 of the License, or (at your option) any later version. |
*/ |
#ifndef _LINUX_LOG2_H |
#define _LINUX_LOG2_H |
#include <linux/types.h> |
#include <linux/bitops.h> |
/* |
* deal with unrepresentable constant logarithms |
*/ |
extern __attribute__((const, noreturn)) |
int ____ilog2_NaN(void); |
/* |
* non-constant log of base 2 calculators |
* - the arch may override these in asm/bitops.h if they can be implemented |
* more efficiently than using fls() and fls64() |
* - the arch is not required to handle n==0 if implementing the fallback |
*/ |
#ifndef CONFIG_ARCH_HAS_ILOG2_U32 |
static inline __attribute__((const)) |
int __ilog2_u32(u32 n) |
{ |
return fls(n) - 1; |
} |
#endif |
#ifndef CONFIG_ARCH_HAS_ILOG2_U64 |
static inline __attribute__((const)) |
int __ilog2_u64(u64 n) |
{ |
return fls64(n) - 1; |
} |
#endif |
/* |
* Determine whether some value is a power of two, where zero is |
* *not* considered a power of two. |
*/ |
static inline __attribute__((const)) |
bool is_power_of_2(unsigned long n) |
{ |
return (n != 0 && ((n & (n - 1)) == 0)); |
} |
/* |
* round up to nearest power of two |
*/ |
static inline __attribute__((const)) |
unsigned long __roundup_pow_of_two(unsigned long n) |
{ |
return 1UL << fls_long(n - 1); |
} |
/* |
* round down to nearest power of two |
*/ |
static inline __attribute__((const)) |
unsigned long __rounddown_pow_of_two(unsigned long n) |
{ |
return 1UL << (fls_long(n) - 1); |
} |
/** |
* ilog2 - log of base 2 of 32-bit or a 64-bit unsigned value |
* @n - parameter |
* |
* constant-capable log of base 2 calculation |
* - this can be used to initialise global variables from constant data, hence |
* the massive ternary operator construction |
* |
* selects the appropriately-sized optimised version depending on sizeof(n) |
*/ |
#define ilog2(n) \ |
( \ |
__builtin_constant_p(n) ? ( \ |
(n) < 1 ? ____ilog2_NaN() : \ |
(n) & (1ULL << 63) ? 63 : \ |
(n) & (1ULL << 62) ? 62 : \ |
(n) & (1ULL << 61) ? 61 : \ |
(n) & (1ULL << 60) ? 60 : \ |
(n) & (1ULL << 59) ? 59 : \ |
(n) & (1ULL << 58) ? 58 : \ |
(n) & (1ULL << 57) ? 57 : \ |
(n) & (1ULL << 56) ? 56 : \ |
(n) & (1ULL << 55) ? 55 : \ |
(n) & (1ULL << 54) ? 54 : \ |
(n) & (1ULL << 53) ? 53 : \ |
(n) & (1ULL << 52) ? 52 : \ |
(n) & (1ULL << 51) ? 51 : \ |
(n) & (1ULL << 50) ? 50 : \ |
(n) & (1ULL << 49) ? 49 : \ |
(n) & (1ULL << 48) ? 48 : \ |
(n) & (1ULL << 47) ? 47 : \ |
(n) & (1ULL << 46) ? 46 : \ |
(n) & (1ULL << 45) ? 45 : \ |
(n) & (1ULL << 44) ? 44 : \ |
(n) & (1ULL << 43) ? 43 : \ |
(n) & (1ULL << 42) ? 42 : \ |
(n) & (1ULL << 41) ? 41 : \ |
(n) & (1ULL << 40) ? 40 : \ |
(n) & (1ULL << 39) ? 39 : \ |
(n) & (1ULL << 38) ? 38 : \ |
(n) & (1ULL << 37) ? 37 : \ |
(n) & (1ULL << 36) ? 36 : \ |
(n) & (1ULL << 35) ? 35 : \ |
(n) & (1ULL << 34) ? 34 : \ |
(n) & (1ULL << 33) ? 33 : \ |
(n) & (1ULL << 32) ? 32 : \ |
(n) & (1ULL << 31) ? 31 : \ |
(n) & (1ULL << 30) ? 30 : \ |
(n) & (1ULL << 29) ? 29 : \ |
(n) & (1ULL << 28) ? 28 : \ |
(n) & (1ULL << 27) ? 27 : \ |
(n) & (1ULL << 26) ? 26 : \ |
(n) & (1ULL << 25) ? 25 : \ |
(n) & (1ULL << 24) ? 24 : \ |
(n) & (1ULL << 23) ? 23 : \ |
(n) & (1ULL << 22) ? 22 : \ |
(n) & (1ULL << 21) ? 21 : \ |
(n) & (1ULL << 20) ? 20 : \ |
(n) & (1ULL << 19) ? 19 : \ |
(n) & (1ULL << 18) ? 18 : \ |
(n) & (1ULL << 17) ? 17 : \ |
(n) & (1ULL << 16) ? 16 : \ |
(n) & (1ULL << 15) ? 15 : \ |
(n) & (1ULL << 14) ? 14 : \ |
(n) & (1ULL << 13) ? 13 : \ |
(n) & (1ULL << 12) ? 12 : \ |
(n) & (1ULL << 11) ? 11 : \ |
(n) & (1ULL << 10) ? 10 : \ |
(n) & (1ULL << 9) ? 9 : \ |
(n) & (1ULL << 8) ? 8 : \ |
(n) & (1ULL << 7) ? 7 : \ |
(n) & (1ULL << 6) ? 6 : \ |
(n) & (1ULL << 5) ? 5 : \ |
(n) & (1ULL << 4) ? 4 : \ |
(n) & (1ULL << 3) ? 3 : \ |
(n) & (1ULL << 2) ? 2 : \ |
(n) & (1ULL << 1) ? 1 : \ |
(n) & (1ULL << 0) ? 0 : \ |
____ilog2_NaN() \ |
) : \ |
(sizeof(n) <= 4) ? \ |
__ilog2_u32(n) : \ |
__ilog2_u64(n) \ |
) |
/** |
* roundup_pow_of_two - round the given value up to nearest power of two |
* @n - parameter |
* |
* round the given value up to the nearest power of two |
* - the result is undefined when n == 0 |
* - this can be used to initialise global variables from constant data |
*/ |
#define roundup_pow_of_two(n) \ |
( \ |
__builtin_constant_p(n) ? ( \ |
(n == 1) ? 1 : \ |
(1UL << (ilog2((n) - 1) + 1)) \ |
) : \ |
__roundup_pow_of_two(n) \ |
) |
/** |
* rounddown_pow_of_two - round the given value down to nearest power of two |
* @n - parameter |
* |
* round the given value down to the nearest power of two |
* - the result is undefined when n == 0 |
* - this can be used to initialise global variables from constant data |
*/ |
#define rounddown_pow_of_two(n) \ |
( \ |
__builtin_constant_p(n) ? ( \ |
(1UL << ilog2(n))) : \ |
__rounddown_pow_of_two(n) \ |
) |
/** |
* order_base_2 - calculate the (rounded up) base 2 order of the argument |
* @n: parameter |
* |
* The first few values calculated by this routine: |
* ob2(0) = 0 |
* ob2(1) = 0 |
* ob2(2) = 1 |
* ob2(3) = 2 |
* ob2(4) = 2 |
* ob2(5) = 3 |
* ... and so on. |
*/ |
#define order_base_2(n) ilog2(roundup_pow_of_two(n)) |
#endif /* _LINUX_LOG2_H */ |
/drivers/include/linux/math64.h |
---|
0,0 → 1,121 |
#ifndef _LINUX_MATH64_H |
#define _LINUX_MATH64_H |
#include <linux/types.h> |
#include <asm/div64.h> |
#if BITS_PER_LONG == 64 |
#define div64_long(x,y) div64_s64((x),(y)) |
/** |
* div_u64_rem - unsigned 64bit divide with 32bit divisor with remainder |
* |
* This is commonly provided by 32bit archs to provide an optimized 64bit |
* divide. |
*/ |
static inline u64 div_u64_rem(u64 dividend, u32 divisor, u32 *remainder) |
{ |
*remainder = dividend % divisor; |
return dividend / divisor; |
} |
/** |
* div_s64_rem - signed 64bit divide with 32bit divisor with remainder |
*/ |
static inline s64 div_s64_rem(s64 dividend, s32 divisor, s32 *remainder) |
{ |
*remainder = dividend % divisor; |
return dividend / divisor; |
} |
/** |
* div64_u64 - unsigned 64bit divide with 64bit divisor |
*/ |
static inline u64 div64_u64(u64 dividend, u64 divisor) |
{ |
return dividend / divisor; |
} |
/** |
* div64_s64 - signed 64bit divide with 64bit divisor |
*/ |
static inline s64 div64_s64(s64 dividend, s64 divisor) |
{ |
return dividend / divisor; |
} |
#elif BITS_PER_LONG == 32 |
#define div64_long(x,y) div_s64((x),(y)) |
#ifndef div_u64_rem |
static inline u64 div_u64_rem(u64 dividend, u32 divisor, u32 *remainder) |
{ |
*remainder = do_div(dividend, divisor); |
return dividend; |
} |
#endif |
#ifndef div_s64_rem |
extern s64 div_s64_rem(s64 dividend, s32 divisor, s32 *remainder); |
#endif |
#ifndef div64_u64 |
extern u64 div64_u64(u64 dividend, u64 divisor); |
#endif |
#ifndef div64_s64 |
extern s64 div64_s64(s64 dividend, s64 divisor); |
#endif |
#endif /* BITS_PER_LONG */ |
/** |
* div_u64 - unsigned 64bit divide with 32bit divisor |
* |
* This is the most common 64bit divide and should be used if possible, |
* as many 32bit archs can optimize this variant better than a full 64bit |
* divide. |
*/ |
#ifndef div_u64 |
static inline u64 div_u64(u64 dividend, u32 divisor) |
{ |
u32 remainder; |
return div_u64_rem(dividend, divisor, &remainder); |
} |
#endif |
/** |
* div_s64 - signed 64bit divide with 32bit divisor |
*/ |
#ifndef div_s64 |
static inline s64 div_s64(s64 dividend, s32 divisor) |
{ |
s32 remainder; |
return div_s64_rem(dividend, divisor, &remainder); |
} |
#endif |
u32 iter_div_u64_rem(u64 dividend, u32 divisor, u64 *remainder); |
static __always_inline u32 |
__iter_div_u64_rem(u64 dividend, u32 divisor, u64 *remainder) |
{ |
u32 ret = 0; |
while (dividend >= divisor) { |
/* The following asm() prevents the compiler from |
optimising this loop into a modulo operation. */ |
asm("" : "+rm"(dividend)); |
dividend -= divisor; |
ret++; |
} |
*remainder = dividend; |
return ret; |
} |
#endif /* _LINUX_MATH64_H */ |
/drivers/include/linux/mod_devicetable.h |
---|
78,6 → 78,9 |
* of a given interface; other interfaces may support other classes. |
* @bInterfaceSubClass: Subclass of interface; associated with bInterfaceClass. |
* @bInterfaceProtocol: Protocol of interface; associated with bInterfaceClass. |
* @bInterfaceNumber: Number of interface; composite devices may use |
* fixed interface numbers to differentiate between vendor-specific |
* interfaces. |
* @driver_info: Holds information used by the driver. Usually it holds |
* a pointer to a descriptor understood by the driver, or perhaps |
* device flags. |
130,12 → 133,15 |
#define USB_DEVICE_ID_MATCH_INT_CLASS 0x0080 |
#define USB_DEVICE_ID_MATCH_INT_SUBCLASS 0x0100 |
#define USB_DEVICE_ID_MATCH_INT_PROTOCOL 0x0200 |
#define USB_DEVICE_ID_MATCH_INT_NUMBER 0x0400 |
#define HID_ANY_ID (~0) |
#define HID_BUS_ANY 0xffff |
#define HID_GROUP_ANY 0x0000 |
struct hid_device_id { |
__u16 bus; |
__u16 pad1; |
__u16 group; |
__u32 vendor; |
__u32 product; |
kernel_ulong_t driver_data |
222,7 → 228,7 |
char type[32]; |
char compatible[128]; |
#ifdef __KERNEL__ |
void *data; |
const void *data; |
#else |
kernel_ulong_t data; |
#endif |
/drivers/include/linux/module.h |
---|
11,15 → 11,14 |
#include <linux/kernel.h> |
#define EXPORT_SYMBOL(x) |
#define MODULE_FIRMWARE(x) |
#define MODULE_AUTHOR(x); |
#define MODULE_DESCRIPTION(x); |
#define MODULE_LICENSE(x); |
#define MODULE_PARM_DESC(_parm, desc) |
#define MODULE_AUTHOR(x) |
#define MODULE_DESCRIPTION(x) |
#define MODULE_LICENSE(x) |
struct module {}; |
#endif /* _LINUX_MODULE_H */ |
/drivers/include/linux/moduleparam.h |
---|
0,0 → 1,3 |
#define MODULE_PARM_DESC(_parm, desc) |
#define module_param_named(name, value, type, perm) |
/drivers/include/linux/pci.h |
---|
13,11 → 13,10 |
* PCI to PCI Bridge Specification |
* PCI System Design Guide |
*/ |
#ifndef LINUX_PCI_H |
#define LINUX_PCI_H |
#include <types.h> |
#include <linux/types.h> |
#include <list.h> |
#include <linux/pci_regs.h> /* The pci register defines */ |
#include <ioport.h> |
276,6 → 275,20 |
#define PCI_D3cold ((pci_power_t __force) 4) |
#define PCI_UNKNOWN ((pci_power_t __force) 5) |
#define PCI_POWER_ERROR ((pci_power_t __force) -1) |
/* Remember to update this when the list above changes! */ |
extern const char *pci_power_names[]; |
static inline const char *pci_power_name(pci_power_t state) |
{ |
return pci_power_names[1 + (int) state]; |
} |
#define PCI_PM_D2_DELAY 200 |
#define PCI_PM_D3_WAIT 10 |
#define PCI_PM_D3COLD_WAIT 100 |
#define PCI_PM_BUS_WAIT 50 |
/** The pci_channel state describes connectivity between the CPU and |
* the pci device. If some PCI bus between here and the pci device |
* has crashed or locked up, this info is reflected here. |
346,9 → 359,10 |
u8 revision; /* PCI revision, low byte of class word */ |
u8 hdr_type; /* PCI header type (`multi' flag masked out) */ |
u8 pcie_cap; /* PCI-E capability offset */ |
u8 pcie_type; /* PCI-E device/port type */ |
u8 pcie_mpss:3; /* PCI-E Max Payload Size Supported */ |
u8 rom_base_reg; /* which config register controls the ROM */ |
u8 pin; /* which interrupt pin this device uses */ |
u16 pcie_flags_reg; /* cached PCI-E Capabilities Register */ |
// struct pci_driver *driver; /* which driver has allocated this device */ |
uint64_t dma_mask; /* Mask of the bits of bus address this |
367,14 → 381,25 |
unsigned int pme_support:5; /* Bitmask of states from which PME# |
can be generated */ |
unsigned int pme_interrupt:1; |
unsigned int pme_poll:1; /* Poll device's PME status bit */ |
unsigned int d1_support:1; /* Low power state D1 is supported */ |
unsigned int d2_support:1; /* Low power state D2 is supported */ |
unsigned int no_d1d2:1; /* Only allow D0 and D3 */ |
unsigned int no_d1d2:1; /* D1 and D2 are forbidden */ |
unsigned int no_d3cold:1; /* D3cold is forbidden */ |
unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ |
unsigned int mmio_always_on:1; /* disallow turning off io/mem |
decoding during bar sizing */ |
unsigned int wakeup_prepared:1; |
unsigned int runtime_d3cold:1; /* whether go through runtime |
D3cold, not set for devices |
powered on/off by the |
corresponding bridge */ |
unsigned int d3_delay; /* D3->D0 transition time in ms */ |
unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */ |
#ifdef CONFIG_PCIEASPM |
struct pcie_link_state *link_state; /* ASPM link state. */ |
#endif |
pci_channel_state_t error_state; /* current connectivity state */ |
struct device dev; /* Generic device interface */ |
387,7 → 412,6 |
*/ |
unsigned int irq; |
struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ |
resource_size_t fw_addr[DEVICE_COUNT_RESOURCE]; /* FW-assigned addr */ |
/* These fields are used by common fixups */ |
unsigned int transparent:1; /* Transparent PCI bridge */ |
396,7 → 420,7 |
unsigned int is_added:1; |
unsigned int is_busmaster:1; /* device is busmaster */ |
unsigned int no_msi:1; /* device may not use msi */ |
unsigned int block_ucfg_access:1; /* userspace config space access is blocked */ |
unsigned int block_cfg_access:1; /* config space access is blocked */ |
unsigned int broken_parity_status:1; /* Device generates false positive parity */ |
unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */ |
unsigned int msi_enabled:1; |
411,15 → 435,15 |
unsigned int is_virtfn:1; |
unsigned int reset_fn:1; |
unsigned int is_hotplug_bridge:1; |
unsigned int __aer_firmware_first_valid:1; |
unsigned int __aer_firmware_first:1; |
unsigned int broken_intx_masking:1; |
unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */ |
// pci_dev_flags_t dev_flags; |
// atomic_t enable_cnt; /* pci_enable_device has been called */ |
atomic_t enable_cnt; /* pci_enable_device has been called */ |
// u32 saved_config_space[16]; /* config space saved at suspend time */ |
// struct hlist_head saved_cap_space; |
// struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */ |
// int rom_attr_enabled; /* has display of the rom attribute been enabled? */ |
// struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ |
// struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ |
}; |
#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) |
443,6 → 467,7 |
struct list_head slots; /* list of slots on this bus */ |
struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; |
struct list_head resources; /* address space routed to this bus */ |
struct resource busn_res; /* bus numbers routed to this bus */ |
struct pci_ops *ops; /* configuration access functions */ |
void *sysdata; /* hook for sys-specific extension */ |
450,8 → 475,6 |
unsigned char number; /* bus number */ |
unsigned char primary; /* number of primary bridge */ |
unsigned char secondary; /* number of secondary bridge */ |
unsigned char subordinate; /* max number of subordinate buses */ |
unsigned char max_bus_speed; /* enum pci_bus_speed */ |
unsigned char cur_bus_speed; /* enum pci_bus_speed */ |
571,6 → 594,16 |
return !!pci_pcie_cap(dev); |
} |
/** |
* pci_pcie_type - get the PCIe device/port type |
* @dev: PCI device |
*/ |
static inline int pci_pcie_type(const struct pci_dev *dev) |
{ |
return (dev->pcie_flags_reg & PCI_EXP_FLAGS_TYPE) >> 4; |
} |
static inline int pci_iov_init(struct pci_dev *dev) |
{ |
return -ENODEV; |
/drivers/include/linux/pci_regs.h |
---|
26,6 → 26,7 |
* Under PCI, each device has 256 bytes of configuration address space, |
* of which the first 64 bytes are standardized as follows: |
*/ |
#define PCI_STD_HEADER_SIZEOF 64 |
#define PCI_VENDOR_ID 0x00 /* 16 bits */ |
#define PCI_DEVICE_ID 0x02 /* 16 bits */ |
#define PCI_COMMAND 0x04 /* 16 bits */ |
125,7 → 126,8 |
#define PCI_IO_RANGE_TYPE_MASK 0x0fUL /* I/O bridging type */ |
#define PCI_IO_RANGE_TYPE_16 0x00 |
#define PCI_IO_RANGE_TYPE_32 0x01 |
#define PCI_IO_RANGE_MASK (~0x0fUL) |
#define PCI_IO_RANGE_MASK (~0x0fUL) /* Standard 4K I/O windows */ |
#define PCI_IO_1K_RANGE_MASK (~0x03UL) /* Intel 1K I/O windows */ |
#define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */ |
#define PCI_MEMORY_BASE 0x20 /* Memory range behind */ |
#define PCI_MEMORY_LIMIT 0x22 |
209,9 → 211,12 |
#define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */ |
#define PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */ |
#define PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */ |
#define PCI_CAP_ID_SECDEV 0x0F /* Secure Device */ |
#define PCI_CAP_ID_EXP 0x10 /* PCI Express */ |
#define PCI_CAP_ID_MSIX 0x11 /* MSI-X */ |
#define PCI_CAP_ID_SATA 0x12 /* SATA Data/Index Conf. */ |
#define PCI_CAP_ID_AF 0x13 /* PCI Advanced Features */ |
#define PCI_CAP_ID_MAX PCI_CAP_ID_AF |
#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ |
#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */ |
#define PCI_CAP_SIZEOF 4 |
276,6 → 281,7 |
#define PCI_VPD_ADDR_MASK 0x7fff /* Address mask */ |
#define PCI_VPD_ADDR_F 0x8000 /* Write 0, 1 indicates completion */ |
#define PCI_VPD_DATA 4 /* 32-bits of data returned here */ |
#define PCI_CAP_VPD_SIZEOF 8 |
/* Slot Identification */ |
297,8 → 303,10 |
#define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */ |
#define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */ |
#define PCI_MSI_MASK_32 12 /* Mask bits register for 32-bit devices */ |
#define PCI_MSI_PENDING_32 16 /* Pending intrs for 32-bit devices */ |
#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */ |
#define PCI_MSI_MASK_64 16 /* Mask bits register for 64-bit devices */ |
#define PCI_MSI_PENDING_64 20 /* Pending intrs for 64-bit devices */ |
/* MSI-X registers */ |
#define PCI_MSIX_FLAGS 2 |
308,6 → 316,7 |
#define PCI_MSIX_TABLE 4 |
#define PCI_MSIX_PBA 8 |
#define PCI_MSIX_FLAGS_BIRMASK (7 << 0) |
#define PCI_CAP_MSIX_SIZEOF 12 /* size of MSIX registers */ |
/* MSI-X entry's format */ |
#define PCI_MSIX_ENTRY_SIZE 16 |
338,6 → 347,7 |
#define PCI_AF_CTRL_FLR 0x01 |
#define PCI_AF_STATUS 5 |
#define PCI_AF_STATUS_TP 0x01 |
#define PCI_CAP_AF_SIZEOF 6 /* size of AF registers */ |
/* PCI-X registers */ |
374,6 → 384,10 |
#define PCI_X_STATUS_SPL_ERR 0x20000000 /* Rcvd Split Completion Error Msg */ |
#define PCI_X_STATUS_266MHZ 0x40000000 /* 266 MHz capable */ |
#define PCI_X_STATUS_533MHZ 0x80000000 /* 533 MHz capable */ |
#define PCI_X_ECC_CSR 8 /* ECC control and status */ |
#define PCI_CAP_PCIX_SIZEOF_V0 8 /* size of registers for Version 0 */ |
#define PCI_CAP_PCIX_SIZEOF_V1 24 /* size for Version 1 */ |
#define PCI_CAP_PCIX_SIZEOF_V2 PCI_CAP_PCIX_SIZEOF_V1 /* Same for v2 */ |
/* PCI Bridge Subsystem ID registers */ |
391,8 → 405,9 |
#define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */ |
#define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */ |
#define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */ |
#define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIE Bridge */ |
#define PCI_EXP_TYPE_RC_END 0x9 /* Root Complex Integrated Endpoint */ |
#define PCI_EXP_TYPE_RC_EC 0x10 /* Root Complex Event Collector */ |
#define PCI_EXP_TYPE_RC_EC 0xa /* Root Complex Event Collector */ |
#define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */ |
#define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */ |
#define PCI_EXP_DEVCAP 4 /* Device capabilities */ |
461,6 → 476,7 |
#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ |
#define PCI_EXP_LNKSTA_LBMS 0x4000 /* Link Bandwidth Management Status */ |
#define PCI_EXP_LNKSTA_LABS 0x8000 /* Link Autonomous Bandwidth Status */ |
#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V1 20 /* v1 endpoints end here */ |
#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ |
#define PCI_EXP_SLTCAP_ABP 0x00000001 /* Attention Button Present */ |
#define PCI_EXP_SLTCAP_PCP 0x00000002 /* Power Controller Present */ |
506,6 → 522,12 |
#define PCI_EXP_RTSTA 32 /* Root Status */ |
#define PCI_EXP_RTSTA_PME 0x10000 /* PME status */ |
#define PCI_EXP_RTSTA_PENDING 0x20000 /* PME pending */ |
/* |
* Note that the following PCI Express 'Capability Structure' registers |
* were introduced with 'Capability Version' 0x2 (v2). These registers |
* do not exist on devices with Capability Version 1. Use pci_pcie_cap2() |
* to use these fields safely. |
*/ |
#define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */ |
#define PCI_EXP_DEVCAP2_ARI 0x20 /* Alternative Routing-ID */ |
#define PCI_EXP_DEVCAP2_LTR 0x800 /* Latency tolerance reporting */ |
520,7 → 542,14 |
#define PCI_EXP_OBFF_MSGA_EN 0x2000 /* OBFF enable with Message type A */ |
#define PCI_EXP_OBFF_MSGB_EN 0x4000 /* OBFF enable with Message type B */ |
#define PCI_EXP_OBFF_WAKE_EN 0x6000 /* OBFF using WAKE# signaling */ |
#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 44 /* v2 endpoints end here */ |
#define PCI_EXP_LNKCAP2 44 /* Link Capability 2 */ |
#define PCI_EXP_LNKCAP2_SLS_2_5GB 0x01 /* Current Link Speed 2.5GT/s */ |
#define PCI_EXP_LNKCAP2_SLS_5_0GB 0x02 /* Current Link Speed 5.0GT/s */ |
#define PCI_EXP_LNKCAP2_SLS_8_0GB 0x04 /* Current Link Speed 8.0GT/s */ |
#define PCI_EXP_LNKCAP2_CROSSLINK 0x100 /* Crosslink supported */ |
#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ |
#define PCI_EXP_LNKSTA2 50 /* Link Status 2 */ |
#define PCI_EXP_SLTCTL2 56 /* Slot Control 2 */ |
/* Extended Capabilities (PCI-X 2.0 and Express) */ |
528,21 → 557,43 |
#define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf) |
#define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc) |
#define PCI_EXT_CAP_ID_ERR 1 |
#define PCI_EXT_CAP_ID_VC 2 |
#define PCI_EXT_CAP_ID_DSN 3 |
#define PCI_EXT_CAP_ID_PWR 4 |
#define PCI_EXT_CAP_ID_VNDR 11 |
#define PCI_EXT_CAP_ID_ACS 13 |
#define PCI_EXT_CAP_ID_ARI 14 |
#define PCI_EXT_CAP_ID_ATS 15 |
#define PCI_EXT_CAP_ID_SRIOV 16 |
#define PCI_EXT_CAP_ID_LTR 24 |
#define PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */ |
#define PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel Capability */ |
#define PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */ |
#define PCI_EXT_CAP_ID_PWR 0x04 /* Power Budgeting */ |
#define PCI_EXT_CAP_ID_RCLD 0x05 /* Root Complex Link Declaration */ |
#define PCI_EXT_CAP_ID_RCILC 0x06 /* Root Complex Internal Link Control */ |
#define PCI_EXT_CAP_ID_RCEC 0x07 /* Root Complex Event Collector */ |
#define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function VC Capability */ |
#define PCI_EXT_CAP_ID_VC9 0x09 /* same as _VC */ |
#define PCI_EXT_CAP_ID_RCRB 0x0A /* Root Complex RB? */ |
#define PCI_EXT_CAP_ID_VNDR 0x0B /* Vendor Specific */ |
#define PCI_EXT_CAP_ID_CAC 0x0C /* Config Access - obsolete */ |
#define PCI_EXT_CAP_ID_ACS 0x0D /* Access Control Services */ |
#define PCI_EXT_CAP_ID_ARI 0x0E /* Alternate Routing ID */ |
#define PCI_EXT_CAP_ID_ATS 0x0F /* Address Translation Services */ |
#define PCI_EXT_CAP_ID_SRIOV 0x10 /* Single Root I/O Virtualization */ |
#define PCI_EXT_CAP_ID_MRIOV 0x11 /* Multi Root I/O Virtualization */ |
#define PCI_EXT_CAP_ID_MCAST 0x12 /* Multicast */ |
#define PCI_EXT_CAP_ID_PRI 0x13 /* Page Request Interface */ |
#define PCI_EXT_CAP_ID_AMD_XXX 0x14 /* reserved for AMD */ |
#define PCI_EXT_CAP_ID_REBAR 0x15 /* resizable BAR */ |
#define PCI_EXT_CAP_ID_DPA 0x16 /* dynamic power alloc */ |
#define PCI_EXT_CAP_ID_TPH 0x17 /* TPH request */ |
#define PCI_EXT_CAP_ID_LTR 0x18 /* latency tolerance reporting */ |
#define PCI_EXT_CAP_ID_SECPCI 0x19 /* Secondary PCIe */ |
#define PCI_EXT_CAP_ID_PMUX 0x1A /* Protocol Multiplexing */ |
#define PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */ |
#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PASID |
#define PCI_EXT_CAP_DSN_SIZEOF 12 |
#define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40 |
/* Advanced Error Reporting */ |
#define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */ |
#define PCI_ERR_UNC_TRAIN 0x00000001 /* Training */ |
#define PCI_ERR_UNC_DLP 0x00000010 /* Data Link Protocol */ |
#define PCI_ERR_UNC_SURPDN 0x00000020 /* Surprise Down */ |
#define PCI_ERR_UNC_POISON_TLP 0x00001000 /* Poisoned TLP */ |
#define PCI_ERR_UNC_FCP 0x00002000 /* Flow Control Protocol */ |
#define PCI_ERR_UNC_COMP_TIME 0x00004000 /* Completion Timeout */ |
552,6 → 603,11 |
#define PCI_ERR_UNC_MALF_TLP 0x00040000 /* Malformed TLP */ |
#define PCI_ERR_UNC_ECRC 0x00080000 /* ECRC Error Status */ |
#define PCI_ERR_UNC_UNSUP 0x00100000 /* Unsupported Request */ |
#define PCI_ERR_UNC_ACSV 0x00200000 /* ACS Violation */ |
#define PCI_ERR_UNC_INTN 0x00400000 /* internal error */ |
#define PCI_ERR_UNC_MCBTLP 0x00800000 /* MC blocked TLP */ |
#define PCI_ERR_UNC_ATOMEG 0x01000000 /* Atomic egress blocked */ |
#define PCI_ERR_UNC_TLPPRE 0x02000000 /* TLP prefix blocked */ |
#define PCI_ERR_UNCOR_MASK 8 /* Uncorrectable Error Mask */ |
/* Same bits as above */ |
#define PCI_ERR_UNCOR_SEVER 12 /* Uncorrectable Error Severity */ |
562,6 → 618,9 |
#define PCI_ERR_COR_BAD_DLLP 0x00000080 /* Bad DLLP Status */ |
#define PCI_ERR_COR_REP_ROLL 0x00000100 /* REPLAY_NUM Rollover */ |
#define PCI_ERR_COR_REP_TIMER 0x00001000 /* Replay Timer Timeout */ |
#define PCI_ERR_COR_ADV_NFAT 0x00002000 /* Advisory Non-Fatal */ |
#define PCI_ERR_COR_INTERNAL 0x00004000 /* Corrected Internal */ |
#define PCI_ERR_COR_LOG_OVER 0x00008000 /* Header Log Overflow */ |
#define PCI_ERR_COR_MASK 20 /* Correctable Error Mask */ |
/* Same bits as above */ |
#define PCI_ERR_CAP 24 /* Advanced Error Capabilities */ |
593,12 → 652,18 |
/* Virtual Channel */ |
#define PCI_VC_PORT_REG1 4 |
#define PCI_VC_REG1_EVCC 0x7 /* extended vc count */ |
#define PCI_VC_PORT_REG2 8 |
#define PCI_VC_REG2_32_PHASE 0x2 |
#define PCI_VC_REG2_64_PHASE 0x4 |
#define PCI_VC_REG2_128_PHASE 0x8 |
#define PCI_VC_PORT_CTRL 12 |
#define PCI_VC_PORT_STATUS 14 |
#define PCI_VC_RES_CAP 16 |
#define PCI_VC_RES_CTRL 20 |
#define PCI_VC_RES_STATUS 26 |
#define PCI_CAP_VC_BASE_SIZEOF 0x10 |
#define PCI_CAP_VC_PER_VC_SIZEOF 0x0C |
/* Power Budgeting */ |
#define PCI_PWR_DSR 4 /* Data Select Register */ |
611,7 → 676,14 |
#define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) /* Power Rail */ |
#define PCI_PWR_CAP 12 /* Capability */ |
#define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */ |
#define PCI_EXT_CAP_PWR_SIZEOF 16 |
/* Vendor-Specific (VSEC, PCI_EXT_CAP_ID_VNDR) */ |
#define PCI_VNDR_HEADER 4 /* Vendor-Specific Header */ |
#define PCI_VNDR_HEADER_ID(x) ((x) & 0xffff) |
#define PCI_VNDR_HEADER_REV(x) (((x) >> 16) & 0xf) |
#define PCI_VNDR_HEADER_LEN(x) (((x) >> 20) & 0xfff) |
/* |
* Hypertransport sub capability types |
* |
643,6 → 715,8 |
#define HT_CAPTYPE_ERROR_RETRY 0xC0 /* Retry on error configuration */ |
#define HT_CAPTYPE_GEN3 0xD0 /* Generation 3 hypertransport configuration */ |
#define HT_CAPTYPE_PM 0xE0 /* Hypertransport powermanagement configuration */ |
#define HT_CAP_SIZEOF_LONG 28 /* slave & primary */ |
#define HT_CAP_SIZEOF_SHORT 24 /* host & secondary */ |
/* Alternative Routing-ID Interpretation */ |
#define PCI_ARI_CAP 0x04 /* ARI Capability Register */ |
653,6 → 727,7 |
#define PCI_ARI_CTRL_MFVC 0x0001 /* MFVC Function Groups Enable */ |
#define PCI_ARI_CTRL_ACS 0x0002 /* ACS Function Groups Enable */ |
#define PCI_ARI_CTRL_FG(x) (((x) >> 4) & 7) /* Function Group */ |
#define PCI_EXT_CAP_ARI_SIZEOF 8 |
/* Address Translation Service */ |
#define PCI_ATS_CAP 0x04 /* ATS Capability Register */ |
662,26 → 737,29 |
#define PCI_ATS_CTRL_ENABLE 0x8000 /* ATS Enable */ |
#define PCI_ATS_CTRL_STU(x) ((x) & 0x1f) /* Smallest Translation Unit */ |
#define PCI_ATS_MIN_STU 12 /* shift of minimum STU block */ |
#define PCI_EXT_CAP_ATS_SIZEOF 8 |
/* Page Request Interface */ |
#define PCI_PRI_CAP 0x13 /* PRI capability ID */ |
#define PCI_PRI_CONTROL_OFF 0x04 /* Offset of control register */ |
#define PCI_PRI_STATUS_OFF 0x06 /* Offset of status register */ |
#define PCI_PRI_ENABLE 0x0001 /* Enable mask */ |
#define PCI_PRI_RESET 0x0002 /* Reset bit mask */ |
#define PCI_PRI_STATUS_RF 0x0001 /* Request Failure */ |
#define PCI_PRI_STATUS_UPRGI 0x0002 /* Unexpected PRG index */ |
#define PCI_PRI_STATUS_STOPPED 0x0100 /* PRI Stopped */ |
#define PCI_PRI_MAX_REQ_OFF 0x08 /* Cap offset for max reqs supported */ |
#define PCI_PRI_ALLOC_REQ_OFF 0x0c /* Cap offset for max reqs allowed */ |
#define PCI_PRI_CTRL 0x04 /* PRI control register */ |
#define PCI_PRI_CTRL_ENABLE 0x01 /* Enable */ |
#define PCI_PRI_CTRL_RESET 0x02 /* Reset */ |
#define PCI_PRI_STATUS 0x06 /* PRI status register */ |
#define PCI_PRI_STATUS_RF 0x001 /* Response Failure */ |
#define PCI_PRI_STATUS_UPRGI 0x002 /* Unexpected PRG index */ |
#define PCI_PRI_STATUS_STOPPED 0x100 /* PRI Stopped */ |
#define PCI_PRI_MAX_REQ 0x08 /* PRI max reqs supported */ |
#define PCI_PRI_ALLOC_REQ 0x0c /* PRI max reqs allowed */ |
#define PCI_EXT_CAP_PRI_SIZEOF 16 |
/* PASID capability */ |
#define PCI_PASID_CAP 0x1b /* PASID capability ID */ |
#define PCI_PASID_CAP_OFF 0x04 /* PASID feature register */ |
#define PCI_PASID_CONTROL_OFF 0x06 /* PASID control register */ |
#define PCI_PASID_ENABLE 0x01 /* Enable/Supported bit */ |
#define PCI_PASID_EXEC 0x02 /* Exec permissions Enable/Supported */ |
#define PCI_PASID_PRIV 0x04 /* Priviledge Mode Enable/Support */ |
#define PCI_PASID_CAP 0x04 /* PASID feature register */ |
#define PCI_PASID_CAP_EXEC 0x02 /* Exec permissions Supported */ |
#define PCI_PASID_CAP_PRIV 0x04 /* Priviledge Mode Supported */ |
#define PCI_PASID_CTRL 0x06 /* PASID control register */ |
#define PCI_PASID_CTRL_ENABLE 0x01 /* Enable bit */ |
#define PCI_PASID_CTRL_EXEC 0x02 /* Exec permissions Enable */ |
#define PCI_PASID_CTRL_PRIV 0x04 /* Priviledge Mode Enable */ |
#define PCI_EXT_CAP_PASID_SIZEOF 8 |
/* Single Root I/O Virtualization */ |
#define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */ |
713,6 → 791,7 |
#define PCI_SRIOV_VFM_MI 0x1 /* Dormant.MigrateIn */ |
#define PCI_SRIOV_VFM_MO 0x2 /* Active.MigrateOut */ |
#define PCI_SRIOV_VFM_AV 0x3 /* Active.Available */ |
#define PCI_EXT_CAP_SRIOV_SIZEOF 64 |
#define PCI_LTR_MAX_SNOOP_LAT 0x4 |
#define PCI_LTR_MAX_NOSNOOP_LAT 0x6 |
719,6 → 798,7 |
#define PCI_LTR_VALUE_MASK 0x000003ff |
#define PCI_LTR_SCALE_MASK 0x00001c00 |
#define PCI_LTR_SCALE_SHIFT 10 |
#define PCI_EXT_CAP_LTR_SIZEOF 8 |
/* Access Control Service */ |
#define PCI_ACS_CAP 0x04 /* ACS Capability Register */ |
729,7 → 809,38 |
#define PCI_ACS_UF 0x10 /* Upstream Forwarding */ |
#define PCI_ACS_EC 0x20 /* P2P Egress Control */ |
#define PCI_ACS_DT 0x40 /* Direct Translated P2P */ |
#define PCI_ACS_EGRESS_BITS 0x05 /* ACS Egress Control Vector Size */ |
#define PCI_ACS_CTRL 0x06 /* ACS Control Register */ |
#define PCI_ACS_EGRESS_CTL_V 0x08 /* ACS Egress Control Vector */ |
#define PCI_VSEC_HDR 4 /* extended cap - vendor specific */ |
#define PCI_VSEC_HDR_LEN_SHIFT 20 /* shift for length field */ |
/* sata capability */ |
#define PCI_SATA_REGS 4 /* SATA REGs specifier */ |
#define PCI_SATA_REGS_MASK 0xF /* location - BAR#/inline */ |
#define PCI_SATA_REGS_INLINE 0xF /* REGS in config space */ |
#define PCI_SATA_SIZEOF_SHORT 8 |
#define PCI_SATA_SIZEOF_LONG 16 |
/* resizable BARs */ |
#define PCI_REBAR_CTRL 8 /* control register */ |
#define PCI_REBAR_CTRL_NBAR_MASK (7 << 5) /* mask for # bars */ |
#define PCI_REBAR_CTRL_NBAR_SHIFT 5 /* shift for # bars */ |
/* dynamic power allocation */ |
#define PCI_DPA_CAP 4 /* capability register */ |
#define PCI_DPA_CAP_SUBSTATE_MASK 0x1F /* # substates - 1 */ |
#define PCI_DPA_BASE_SIZEOF 16 /* size with 0 substates */ |
/* TPH Requester */ |
#define PCI_TPH_CAP 4 /* capability register */ |
#define PCI_TPH_CAP_LOC_MASK 0x600 /* location mask */ |
#define PCI_TPH_LOC_NONE 0x000 /* no location */ |
#define PCI_TPH_LOC_CAP 0x200 /* in capability */ |
#define PCI_TPH_LOC_MSIX 0x400 /* in MSI-X */ |
#define PCI_TPH_CAP_ST_MASK 0x07FF0000 /* st table mask */ |
#define PCI_TPH_CAP_ST_SHIFT 16 /* st table shift */ |
#define PCI_TPH_BASE_SIZEOF 12 /* size with no st table */ |
#endif /* LINUX_PCI_REGS_H */ |
/drivers/include/linux/poison.h |
---|
40,12 → 40,6 |
#define RED_INACTIVE 0x09F911029D74E35BULL /* when obj is inactive */ |
#define RED_ACTIVE 0xD84156C5635688C0ULL /* when obj is active */ |
#ifdef CONFIG_PHYS_ADDR_T_64BIT |
#define MEMBLOCK_INACTIVE 0x3a84fb0144c9e71bULL |
#else |
#define MEMBLOCK_INACTIVE 0x44c9e71bUL |
#endif |
#define SLUB_RED_INACTIVE 0xbb |
#define SLUB_RED_ACTIVE 0xcc |
/drivers/include/linux/spinlock.h |
---|
344,4 → 344,10 |
# include <linux/spinlock_api_up.h> |
#endif |
struct rw_semaphore { |
signed long count; |
spinlock_t wait_lock; |
struct list_head wait_list; |
}; |
#endif /* __LINUX_SPINLOCK_H */ |
/drivers/include/linux/spinlock_api_up.h |
---|
31,7 → 31,7 |
do { local_bh_disable(); __LOCK(lock); } while (0) |
#define __LOCK_IRQ(lock) \ |
do { local_irq_disable(); __LOCK(lock); } while (0) |
do { asm volatile ("cli \n"); __LOCK(lock); } while (0) |
#define __LOCK_IRQSAVE(lock, flags) \ |
do { \ |
51,7 → 51,7 |
__release(lock); (void)(lock); } while (0) |
#define __UNLOCK_IRQ(lock) \ |
do { local_irq_enable(); __UNLOCK(lock); } while (0) |
do { asm volatile ("sti \n"); __UNLOCK(lock); } while (0) |
#define __UNLOCK_IRQRESTORE(lock, flags) \ |
do { \ |
/drivers/include/linux/types.h |
---|
24,7 → 24,8 |
typedef __kernel_dev_t dev_t; |
typedef __kernel_ino_t ino_t; |
typedef __kernel_mode_t mode_t; |
typedef __kernel_nlink_t nlink_t; |
typedef unsigned short umode_t; |
typedef __u32 nlink_t; |
typedef __kernel_off_t off_t; |
typedef __kernel_pid_t pid_t; |
typedef __kernel_daddr_t daddr_t; |
252,9 → 253,7 |
typedef unsigned int addr_t; |
typedef unsigned int count_t; |
# define WARN(condition, format...) |
#define false 0 |
#define true 1 |
267,14 → 266,6 |
#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d)) |
#define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */ |
#define DRM_INFO(fmt, arg...) dbgprintf("DRM: "fmt , ##arg) |
#define DRM_ERROR(fmt, arg...) \ |
printk(KERN_ERR "[" DRM_NAME ":%s] *ERROR* " fmt , __func__ , ##arg) |
#define BUILD_BUG_ON_ZERO(e) (sizeof(char[1 - 2 * !!(e)]) - 1) |
345,24 → 336,7 |
#define PAGE_MASK (~(PAGE_SIZE-1)) |
#define do_div(n, base) \ |
({ \ |
unsigned long __upper, __low, __high, __mod, __base; \ |
__base = (base); \ |
asm("":"=a" (__low), "=d" (__high) : "A" (n)); \ |
__upper = __high; \ |
if (__high) { \ |
__upper = __high % (__base); \ |
__high = __high / (__base); \ |
} \ |
asm("divl %2":"=a" (__low), "=d" (__mod) \ |
: "rm" (__base), "0" (__low), "1" (__upper)); \ |
asm("":"=A" (n) : "a" (__low), "d" (__high)); \ |
__mod; \ |
}) |
#define ENTER() dbgprintf("enter %s\n",__FUNCTION__) |
#define LEAVE() dbgprintf("leave %s\n",__FUNCTION__) |
375,4 → 349,9 |
#define PCI_DEVICE_ID_ATI_RADEON_QY 0x5159 |
#ifndef __read_mostly |
#define __read_mostly |
#endif |
#endif /* _LINUX_TYPES_H */ |
/drivers/include/linux/wait.h |
---|
36,6 → 36,40 |
} while (0) |
#define wait_event_timeout(wq, condition, timeout) \ |
({ \ |
long __ret = timeout; \ |
do{ \ |
wait_queue_t __wait = { \ |
.task_list = LIST_HEAD_INIT(__wait.task_list), \ |
.evnt = CreateEvent(NULL, MANUAL_DESTROY), \ |
}; \ |
u32 flags; \ |
\ |
spin_lock_irqsave(&wq.lock, flags); \ |
if (list_empty(&__wait.task_list)) \ |
__add_wait_queue(&wq, &__wait); \ |
spin_unlock_irqrestore(&wq.lock, flags); \ |
\ |
for(;;){ \ |
if (condition) \ |
break; \ |
WaitEvent(__wait.evnt); \ |
}; \ |
if (!list_empty_careful(&__wait.task_list)) { \ |
spin_lock_irqsave(&wq.lock, flags); \ |
list_del_init(&__wait.task_list); \ |
spin_unlock_irqrestore(&wq.lock, flags); \ |
}; \ |
DestroyEvent(__wait.evnt); \ |
} while (0); \ |
__ret; \ |
}) |
#define wait_event(wq, condition) \ |
do{ \ |
wait_queue_t __wait = { \ |
63,6 → 97,8 |
} while (0) |
static inline |
void wake_up_all(wait_queue_head_t *q) |
{ |
127,10 → 163,13 |
struct work_struct work; |
}; |
struct workqueue_struct *alloc_workqueue_key(const char *fmt, |
unsigned int flags, int max_active); |
#define alloc_ordered_workqueue(fmt, flags, args...) \ |
alloc_workqueue(fmt, WQ_UNBOUND | (flags), 1, ##args) |
int queue_delayed_work(struct workqueue_struct *wq, |
struct delayed_work *dwork, unsigned long delay); |
140,5 → 179,12 |
(_work)->work.func = _func; \ |
} while (0) |
struct completion { |
unsigned int done; |
wait_queue_head_t wait; |
}; |
#endif |
/drivers/include/syscall.h |
---|
39,6 → 39,7 |
addr_t STDCALL AllocPages(count_t count)__asm__("AllocPages"); |
void IMPORT __attribute__((regparm(1))) |
FreePage(addr_t page)__asm__("FreePage"); |
void STDCALL MapPage(void *vaddr, addr_t paddr, u32_t flags)__asm__("MapPage"); |
void* STDCALL CreateRingBuffer(size_t size, u32_t map)__asm__("CreateRingBuffer"); |
91,6 → 92,48 |
#define pciWriteLong(tag, reg, val) \ |
PciWrite32(PCI_BUS_FROM_TAG(tag),PCI_DFN_FROM_TAG(tag),(reg),(val)) |
static inline int pci_read_config_byte(struct pci_dev *dev, int where, |
u8 *val) |
{ |
*val = PciRead8(dev->busnr, dev->devfn, where); |
return 1; |
} |
static inline int pci_read_config_word(struct pci_dev *dev, int where, |
u16 *val) |
{ |
*val = PciRead16(dev->busnr, dev->devfn, where); |
return 1; |
} |
static inline int pci_read_config_dword(struct pci_dev *dev, int where, |
u32 *val) |
{ |
*val = PciRead32(dev->busnr, dev->devfn, where); |
return 1; |
} |
static inline int pci_write_config_byte(struct pci_dev *dev, int where, |
u8 val) |
{ |
PciWrite8(dev->busnr, dev->devfn, where, val); |
return 1; |
} |
static inline int pci_write_config_word(struct pci_dev *dev, int where, |
u16 val) |
{ |
PciWrite16(dev->busnr, dev->devfn, where, val); |
return 1; |
} |
static inline int pci_write_config_dword(struct pci_dev *dev, int where, |
u32 val) |
{ |
PciWrite32(dev->busnr, dev->devfn, where, val); |
return 1; |
} |
/////////////////////////////////////////////////////////////////////////////// |
int dbg_open(char *path); |
447,4 → 490,37 |
#define rmb() asm volatile("lfence":::"memory") |
static inline void *vzalloc(unsigned long size) |
{ |
void *mem; |
mem = KernelAlloc(size); |
if(mem) |
memset(mem, 0, size); |
return mem; |
}; |
static inline void vfree(void *addr) |
{ |
KernelFree(addr); |
} |
static inline int power_supply_is_system_supplied(void) { return -1; } |
#define RWSEM_UNLOCKED_VALUE 0x00000000 |
#define RWSEM_ACTIVE_BIAS 0x00000001 |
#define RWSEM_ACTIVE_MASK 0x0000ffff |
#define RWSEM_WAITING_BIAS (-0x00010000) |
#define RWSEM_ACTIVE_READ_BIAS RWSEM_ACTIVE_BIAS |
#define RWSEM_ACTIVE_WRITE_BIAS (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS) |
static void init_rwsem(struct rw_semaphore *sem) |
{ |
sem->count = RWSEM_UNLOCKED_VALUE; |
spin_lock_init(&sem->wait_lock); |
INIT_LIST_HEAD(&sem->wait_list); |
} |
#endif |