| /drivers/old/ati2d/accel_2d.h |
|---|
| 0,0 → 1,165 |
| #define PX_CREATE 1 |
| #define PX_DESTROY 2 |
| #define PX_CLEAR 3 |
| #define PX_DRAW_RECT 4 |
| #define PX_FILL_RECT 5 |
| #define PX_LINE 6 |
| #define PX_BLIT 7 |
| #define PX_BLIT_TRANSPARENT 8 |
| #define PX_BLIT_ALPHA 9 |
| typedef unsigned int color_t; |
| typedef struct |
| { |
| int x; |
| int y; |
| }pt_t; |
| /*********** Clipping **********/ |
| typedef struct |
| { |
| int xmin; |
| int ymin; |
| int xmax; |
| int ymax; |
| }clip_t, *PTRclip; |
| #define CLIP_TOP 1 |
| #define CLIP_BOTTOM 2 |
| #define CLIP_RIGHT 4 |
| #define CLIP_LEFT 8 |
| int LineClip ( clip_t *clip, int *x1, int *y1, int *x2, int *y2 ); |
| int BlockClip( clip_t *clip, int *x1, int *y1, int *x2, int* y2 ); |
| typedef struct |
| { |
| unsigned width; |
| unsigned height; |
| u32_t format; |
| u32_t flags; |
| size_t pitch; |
| void *mapped; |
| u32_t handle; |
| }pixmap_t; |
| typedef struct |
| { |
| unsigned width; |
| unsigned height; |
| u32_t format; |
| u32_t flags; |
| size_t pitch; |
| void *mapped; |
| unsigned pitch_offset; |
| addr_t local; |
| }local_pixmap_t; |
| #define PX_MEM_SYSTEM 0 |
| #define PX_MEM_LOCAL 1 |
| #define PX_MEM_GART 2 |
| #define PX_MEM_MASK 3 |
| #define PX_LOCK 1 |
| typedef struct |
| { |
| local_pixmap_t *dstpix; |
| color_t color; |
| }io_clear_t; |
| typedef struct |
| { |
| local_pixmap_t *dstpix; |
| struct |
| { |
| int x0; |
| int y0; |
| }; |
| union |
| { |
| struct |
| { |
| int x1; |
| int y1; |
| }; |
| struct |
| { |
| int w; |
| int h; |
| }; |
| }; |
| color_t color; |
| color_t border; |
| }io_draw_t; |
| typedef struct |
| { |
| local_pixmap_t *dstpix; |
| int x; |
| int y; |
| int w; |
| int h; |
| color_t bkcolor; |
| color_t fcolor; |
| u32_t bmp0; |
| u32_t bmp1; |
| color_t border; |
| }io_fill_t; |
| typedef struct |
| { |
| local_pixmap_t *dstpix; |
| int dst_x; |
| int dst_y; |
| local_pixmap_t *srcpix; |
| int src_x; |
| int src_y; |
| int w; |
| int h; |
| union { |
| color_t key; |
| color_t alpha; |
| }; |
| }io_blit_t; |
| static addr_t bind_pixmap(local_pixmap_t *pixmap); |
| int CreatePixmap(pixmap_t *io); |
| int DestroyPixmap(pixmap_t *io); |
| int ClearPixmap(io_clear_t *io); |
| int Line(io_draw_t *draw); |
| int DrawRect(io_draw_t * draw); |
| int FillRect(io_fill_t * fill); |
| int Blit(io_blit_t* blit); |
| int BlitTransparent(io_blit_t* blit); |
| /drivers/old/ati2d/accel_2d.inc |
|---|
| 0,0 → 1,889 |
| int ClearPixmap(io_clear_t *io) |
| { |
| u32_t *ring; |
| local_pixmap_t *dstpixmap; |
| dstpixmap = (io->dstpix == (void*)-1) ? &scr_pixmap : io->dstpix ; |
| lock_device(); |
| #if R300_PIO |
| FIFOWait(6); |
| OUTREG(R5XX_DP_GUI_MASTER_CNTL, |
| RADEON_GMC_DST_PITCH_OFFSET_CNTL | |
| RADEON_GMC_BRUSH_SOLID_COLOR | |
| RADEON_GMC_DST_32BPP | |
| RADEON_GMC_SRC_DATATYPE_COLOR | |
| R5XX_GMC_CLR_CMP_CNTL_DIS | |
| R5XX_GMC_WR_MSK_DIS | |
| R5XX_ROP3_P |
| ); |
| OUTREG(R5XX_DP_BRUSH_FRGD_CLR, io->color); |
| OUTREG(R5XX_DP_CNTL, R5XX_DST_X_LEFT_TO_RIGHT | R5XX_DST_Y_TOP_TO_BOTTOM); |
| OUTREG(R5XX_DST_PITCH_OFFSET, dstpixmap->pitch_offset); |
| OUTREG(R5XX_DST_Y_X, 0); |
| OUTREG(R5XX_DST_WIDTH_HEIGHT,(dstpixmap->width<<16)|dstpixmap->height); |
| #else |
| BEGIN_RING(6); |
| OUT_RING(CP_PACKET3(RADEON_CNTL_PAINT_MULTI, 4)); |
| OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL | |
| RADEON_GMC_BRUSH_SOLID_COLOR | |
| RADEON_GMC_DST_32BPP | |
| RADEON_GMC_SRC_DATATYPE_COLOR | |
| R5XX_GMC_CLR_CMP_CNTL_DIS | |
| R5XX_GMC_WR_MSK_DIS | |
| R5XX_ROP3_P |
| ); |
| OUT_RING(dstpixmap->pitch_offset); |
| OUT_RING(io->color); |
| OUT_RING( 0 ); |
| OUT_RING((dstpixmap->width<<16)|dstpixmap->height); |
| COMMIT_RING(); |
| #endif |
| unlock_device(); |
| return ERR_OK; |
| } |
| int Line(io_draw_t *draw) |
| { |
| local_pixmap_t *dstpixmap; |
| clip_t clip; |
| int x0, y0, x1, y1; |
| dstpixmap = (draw->dstpix == (void*)-1) ? &scr_pixmap : draw->dstpix ; |
| x0 = draw->x0; |
| y0 = draw->y0; |
| x1 = draw->x1; |
| y1 = draw->y1; |
| clip.xmin = 0; |
| clip.ymin = 0; |
| clip.xmax = dstpixmap->width-1; |
| clip.ymax = dstpixmap->height-1; |
| if ( !LineClip(&clip, &x0, &y0, &x1, &y1 )) |
| { |
| u32_t *ring, write; |
| lock_device(); |
| #if R300_PIO |
| FIFOWait(6); |
| OUTREG(R5XX_DP_GUI_MASTER_CNTL, |
| RADEON_GMC_DST_PITCH_OFFSET_CNTL | |
| RADEON_GMC_BRUSH_SOLID_COLOR | |
| RADEON_GMC_DST_32BPP | |
| RADEON_GMC_SRC_DATATYPE_COLOR | |
| R5XX_GMC_CLR_CMP_CNTL_DIS | |
| R5XX_GMC_WR_MSK_DIS | |
| R5XX_ROP3_P |
| ); |
| OUTREG(R5XX_DST_LINE_PATCOUNT, 0x55 << R5XX_BRES_CNTL_SHIFT); |
| OUTREG(R5XX_DP_BRUSH_FRGD_CLR, draw->color); |
| OUTREG(R5XX_DST_PITCH_OFFSET, dstpixmap->pitch_offset); |
| OUTREG(R5XX_DST_LINE_START,(y0<<16)|x0); |
| OUTREG(R5XX_DST_LINE_END,(y1<<16)|x1); |
| #else |
| BEGIN_RING(6); |
| OUT_RING(CP_PACKET3(RADEON_CNTL_PAINT_POLYLINE, 4)); |
| OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL | |
| RADEON_GMC_BRUSH_SOLID_COLOR | |
| RADEON_GMC_DST_32BPP | |
| RADEON_GMC_SRC_DATATYPE_COLOR | |
| R5XX_GMC_CLR_CMP_CNTL_DIS | |
| R5XX_GMC_WR_MSK_DIS | |
| R5XX_ROP3_P); |
| OUT_RING(dstpixmap->pitch_offset); |
| OUT_RING(draw->color); |
| OUT_RING((y0<<16)|x0); |
| OUT_RING((y1<<16)|x1); |
| COMMIT_RING(); |
| #endif |
| unlock_device(); |
| }; |
| return ERR_OK; |
| } |
| int DrawRect(io_draw_t* draw) |
| { |
| int x0, y0, x1, y1, xend, yend; |
| local_pixmap_t *dstpixmap; |
| clip_t dst_clip; |
| dstpixmap = (draw->dstpix == (void*)-1) ? &scr_pixmap : draw->dstpix ; |
| x0 = draw->x0; |
| y0 = draw->y0; |
| x1 = xend = x0 + draw->w - 1; |
| y1 = yend = y0 + draw->h - 1; |
| dst_clip.xmin = 0; |
| dst_clip.ymin = 0; |
| dst_clip.xmax = dstpixmap->width-1; |
| dst_clip.ymax = dstpixmap->height-1; |
| // dbgprintf("draw rect x0:%d, y0:%d, x1:%d, y1:%d, color: %x\n", |
| // x0, y0, x1, y1, draw->color); |
| if( ! BlockClip( &dst_clip, &x0, &y0, &x1, &y1)) |
| { |
| u32_t *ring; |
| int w, h; |
| w = x1 - x0 + 1; |
| h = y1 - y0 + 1; |
| lock_device(); |
| #if R300_PIO |
| FIFOWait(7); |
| OUTREG(R5XX_DP_GUI_MASTER_CNTL, |
| RADEON_GMC_DST_PITCH_OFFSET_CNTL | |
| RADEON_GMC_BRUSH_SOLID_COLOR | |
| RADEON_GMC_DST_32BPP | |
| RADEON_GMC_SRC_DATATYPE_COLOR | |
| R5XX_GMC_CLR_CMP_CNTL_DIS | |
| R5XX_GMC_WR_MSK_DIS | |
| R5XX_ROP3_P |
| ); |
| OUTREG(R5XX_DP_BRUSH_FRGD_CLR, draw->color); |
| OUTREG(R5XX_DP_CNTL, R5XX_DST_X_LEFT_TO_RIGHT | R5XX_DST_Y_TOP_TO_BOTTOM); |
| OUTREG(R5XX_DST_PITCH_OFFSET, dstpixmap->pitch_offset); |
| OUTREG(R5XX_DST_Y_X,(y0<<16)|x0); |
| OUTREG(R5XX_DST_WIDTH_HEIGHT,(w<<16)|h); |
| if( draw->color != draw->border) |
| { |
| OUTREG(R5XX_DP_BRUSH_FRGD_CLR, draw->border); |
| if( y0 == draw->y0) |
| { |
| FIFOWait(2); |
| OUTREG(R5XX_DST_Y_X,(y0<<16)|x0); |
| OUTREG(R5XX_DST_WIDTH_HEIGHT,(w<<16)|1); |
| y0++; |
| h--; |
| } |
| if( y1 == yend ) |
| { |
| FIFOWait(2); |
| OUTREG(R5XX_DST_Y_X,(y1<<16)|x0); |
| OUTREG(R5XX_DST_WIDTH_HEIGHT,(w<<16)|1); |
| h--; |
| } |
| if( (h > 0) && (x0 == draw->x0)) |
| { |
| FIFOWait(2); |
| OUTREG(R5XX_DST_Y_X,(y0<<16)|x0); |
| OUTREG(R5XX_DST_WIDTH_HEIGHT,(1<<16)|h); |
| } |
| if( (h > 0) && (x1 == xend)) |
| { |
| FIFOWait(2); |
| OUTREG(R5XX_DST_Y_X,(y0<<16)|x1); |
| OUTREG(R5XX_DST_WIDTH_HEIGHT,(1<<16)|h); |
| } |
| }; |
| #else |
| BEGIN_RING(64); |
| OUT_RING(CP_PACKET3(RADEON_CNTL_PAINT_MULTI, 4)); |
| OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL | |
| RADEON_GMC_BRUSH_SOLID_COLOR | |
| RADEON_GMC_DST_32BPP | |
| RADEON_GMC_SRC_DATATYPE_COLOR | |
| R5XX_GMC_CLR_CMP_CNTL_DIS | |
| R5XX_GMC_WR_MSK_DIS | |
| R5XX_ROP3_P |
| ); |
| OUT_RING(dstpixmap->pitch_offset); |
| OUT_RING(draw->color); |
| OUT_RING((x0<<16)|y0); |
| OUT_RING((w<<16)|h); |
| OUT_RING(CP_PACKET2()); |
| OUT_RING(CP_PACKET2()); |
| if( draw->color != draw->border) |
| { |
| if( y0 == draw->y0) { |
| OUT_RING(CP_PACKET3(RADEON_CNTL_PAINT_MULTI, 4)); |
| OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL | |
| RADEON_GMC_BRUSH_SOLID_COLOR | |
| RADEON_GMC_DST_32BPP | |
| RADEON_GMC_SRC_DATATYPE_COLOR | |
| R5XX_GMC_CLR_CMP_CNTL_DIS | |
| R5XX_GMC_WR_MSK_DIS | |
| R5XX_ROP3_P |
| ); |
| OUT_RING(dstpixmap->pitch_offset); |
| OUT_RING(draw->border); |
| OUT_RING((x0<<16)|y0); |
| OUT_RING((w<<16)|1); |
| OUT_RING(CP_PACKET2()); |
| OUT_RING(CP_PACKET2()); |
| // y0++; |
| // h--; |
| } |
| if( y1 == yend ) { |
| OUT_RING(CP_PACKET3(RADEON_CNTL_PAINT_MULTI, 4)); |
| OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL | |
| RADEON_GMC_BRUSH_SOLID_COLOR | |
| RADEON_GMC_DST_32BPP | |
| RADEON_GMC_SRC_DATATYPE_COLOR | |
| R5XX_GMC_CLR_CMP_CNTL_DIS | |
| R5XX_GMC_WR_MSK_DIS | |
| R5XX_ROP3_P |
| ); |
| OUT_RING(dstpixmap->pitch_offset); |
| OUT_RING(draw->border); |
| OUT_RING((x0<<16)|y1); |
| OUT_RING((w<<16)|1); |
| OUT_RING(CP_PACKET2()); |
| OUT_RING(CP_PACKET2()); |
| // h--; |
| } |
| if( (h > 0) && (x0 == draw->x0)) { |
| OUT_RING(CP_PACKET3(RADEON_CNTL_PAINT_MULTI, 4)); |
| OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL | |
| RADEON_GMC_BRUSH_SOLID_COLOR | |
| RADEON_GMC_DST_32BPP | |
| RADEON_GMC_SRC_DATATYPE_COLOR | |
| R5XX_GMC_CLR_CMP_CNTL_DIS | |
| R5XX_GMC_WR_MSK_DIS | |
| R5XX_ROP3_P |
| ); |
| OUT_RING(dstpixmap->pitch_offset); |
| OUT_RING(draw->border); |
| OUT_RING((x0<<16)|y0); |
| OUT_RING((1<<16)|h); |
| OUT_RING(CP_PACKET2()); |
| OUT_RING(CP_PACKET2()); |
| } |
| if( (h > 0) && (x1 == xend)) { |
| OUT_RING(CP_PACKET3(RADEON_CNTL_PAINT_MULTI, 4)); |
| OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL | |
| RADEON_GMC_BRUSH_SOLID_COLOR | |
| RADEON_GMC_DST_32BPP | |
| RADEON_GMC_SRC_DATATYPE_COLOR | |
| R5XX_GMC_CLR_CMP_CNTL_DIS | |
| R5XX_GMC_WR_MSK_DIS | |
| R5XX_ROP3_P |
| ); |
| OUT_RING(dstpixmap->pitch_offset); |
| OUT_RING(draw->border); |
| OUT_RING((x1<<16)|y0); |
| OUT_RING((1<<16)|h); |
| OUT_RING(CP_PACKET2()); |
| OUT_RING(CP_PACKET2()); |
| } |
| }; |
| /* |
| CP_REG(R5XX_DP_GUI_MASTER_CNTL, |
| RADEON_GMC_DST_PITCH_OFFSET_CNTL | |
| RADEON_GMC_BRUSH_SOLID_COLOR | |
| RADEON_GMC_DST_32BPP | |
| RADEON_GMC_SRC_DATATYPE_COLOR | |
| R5XX_GMC_CLR_CMP_CNTL_DIS | |
| R5XX_GMC_WR_MSK_DIS | |
| R5XX_ROP3_P |
| ); |
| CP_REG(R5XX_DP_BRUSH_FRGD_CLR, draw->color); |
| CP_REG(R5XX_DP_CNTL, R5XX_DST_X_LEFT_TO_RIGHT | R5XX_DST_Y_TOP_TO_BOTTOM); |
| CP_REG(R5XX_DST_PITCH_OFFSET, dstpixmap->pitch_offset); |
| CP_REG(R5XX_DST_Y_X,(y0<<16)|x0); |
| CP_REG(R5XX_DST_WIDTH_HEIGHT,(w<<16)|h); |
| if( draw->color != draw->border) |
| { |
| CP_REG(R5XX_DP_GUI_MASTER_CNTL, |
| RADEON_GMC_DST_PITCH_OFFSET_CNTL | |
| RADEON_GMC_BRUSH_SOLID_COLOR | |
| RADEON_GMC_DST_32BPP | |
| RADEON_GMC_SRC_DATATYPE_COLOR | |
| R5XX_GMC_CLR_CMP_CNTL_DIS | |
| R5XX_GMC_WR_MSK_DIS | |
| R5XX_ROP3_P |
| ); |
| CP_REG(R5XX_DP_BRUSH_FRGD_CLR, draw->border); |
| CP_REG(R5XX_DP_CNTL, R5XX_DST_X_LEFT_TO_RIGHT | R5XX_DST_Y_TOP_TO_BOTTOM); |
| CP_REG(R5XX_DST_PITCH_OFFSET, dstpixmap->pitch_offset); |
| if( y0 == draw->y0) { |
| CP_REG(R5XX_DST_Y_X,(y0<<16)|x0); |
| CP_REG(R5XX_DST_WIDTH_HEIGHT,(w<<16)|1); |
| y0++; |
| h--; |
| } |
| if( y1 == yend ) { |
| CP_REG(R5XX_DST_Y_X,(y1<<16)|x0); |
| CP_REG(R5XX_DST_WIDTH_HEIGHT,(w<<16)|1); |
| h--; |
| } |
| if( (h > 0) && (x0 == draw->x0)) { |
| CP_REG(R5XX_DST_Y_X,(y0<<16)|x0); |
| CP_REG(R5XX_DST_WIDTH_HEIGHT,(1<<16)|h); |
| } |
| if( (h > 0) && (x1 == xend)) { |
| CP_REG(R5XX_DST_Y_X,(y0<<16)|x1); |
| CP_REG(R5XX_DST_WIDTH_HEIGHT,(1<<16)|h); |
| } |
| }; |
| */ |
| COMMIT_RING(); |
| #endif |
| unlock_device(); |
| }; |
| return ERR_OK; |
| } |
| int FillRect(io_fill_t *fill) |
| { |
| local_pixmap_t *dstpixmap; |
| clip_t dst_clip; |
| int x0, y0, x1, y1, xend, yend; |
| dstpixmap = (fill->dstpix == (void*)-1) ? &scr_pixmap : fill->dstpix ; |
| x0 = fill->x; |
| y0 = fill->y; |
| xend = x1 = x0 + fill->w - 1; |
| yend = y1 = y0 + fill->h - 1; |
| dst_clip.xmin = 0; |
| dst_clip.ymin = 0; |
| dst_clip.xmax = dstpixmap->width-1; |
| dst_clip.ymax = dstpixmap->height-1; |
| // dbgprintf("fill rect x0:%d, y0:%d, x1:%d, y1:%d\n", |
| // x0, y0, x1, y1); |
| if( ! BlockClip(&dst_clip, &x0, &y0, &x1, &y1)) |
| { |
| u32_t *ring, write; |
| int w = x1 - x0 + 1; |
| int h = y1 - y0 + 1; |
| lock_device(); |
| #if R300_PIO |
| FIFOWait(9); |
| OUTREG(R5XX_DP_GUI_MASTER_CNTL, |
| RADEON_GMC_DST_PITCH_OFFSET_CNTL | |
| R5XX_GMC_BRUSH_8X8_MONO_FG_BG | |
| RADEON_GMC_DST_32BPP | |
| R5XX_GMC_SRC_DATATYPE_COLOR | |
| R5XX_GMC_CLR_CMP_CNTL_DIS | |
| R5XX_GMC_WR_MSK_DIS | |
| R5XX_ROP3_P |
| ); |
| OUTREG(R5XX_DP_BRUSH_BKGD_CLR, fill->bkcolor); |
| OUTREG(R5XX_DP_BRUSH_FRGD_CLR, fill->fcolor); |
| OUTREG(R5XX_BRUSH_DATA0, fill->bmp0); |
| OUTREG(R5XX_BRUSH_DATA1, fill->bmp1); |
| OUTREG(R5XX_DP_CNTL, R5XX_DST_X_LEFT_TO_RIGHT | R5XX_DST_Y_TOP_TO_BOTTOM); |
| OUTREG(R5XX_DST_PITCH_OFFSET, dstpixmap->pitch_offset); |
| OUTREG(R5XX_DST_Y_X,(y0<<16)|x0); |
| OUTREG(R5XX_DST_HEIGHT_WIDTH,(h<<16)|w); |
| if( (fill->border & 0xFF000000) != 0) |
| { |
| FIFOWait(2); |
| OUTREG(R5XX_DP_GUI_MASTER_CNTL, |
| RADEON_GMC_DST_PITCH_OFFSET_CNTL | |
| RADEON_GMC_BRUSH_SOLID_COLOR | |
| RADEON_GMC_DST_32BPP | |
| RADEON_GMC_SRC_DATATYPE_COLOR | |
| R5XX_GMC_CLR_CMP_CNTL_DIS | |
| R5XX_GMC_WR_MSK_DIS | |
| R5XX_ROP3_P |
| ); |
| OUTREG(R5XX_DP_BRUSH_FRGD_CLR, fill->border); |
| if( y0 == fill->y) |
| { |
| FIFOWait(2); |
| OUTREG(R5XX_DST_Y_X,(y0<<16)|x0); |
| OUTREG(R5XX_DST_WIDTH_HEIGHT,(w<<16)|1); |
| y0++; |
| h--; |
| } |
| if( y1 == yend ) |
| { |
| FIFOWait(2); |
| OUTREG(R5XX_DST_Y_X,(y1<<16)|x0); |
| OUTREG(R5XX_DST_WIDTH_HEIGHT,(w<<16)|1); |
| h--; |
| } |
| if( (h > 0) && (x0 == fill->x)) |
| { |
| FIFOWait(2); |
| OUTREG(R5XX_DST_Y_X,(y0<<16)|x0); |
| OUTREG(R5XX_DST_WIDTH_HEIGHT,(1<<16)|h); |
| } |
| if( (h > 0) && (x1 == xend)) |
| { |
| FIFOWait(2); |
| OUTREG(R5XX_DST_Y_X,(y0<<16)|x1); |
| OUTREG(R5XX_DST_WIDTH_HEIGHT,(1<<16)|h); |
| } |
| }; |
| #else |
| BEGIN_RING(9+10*2); |
| OUT_RING(CP_PACKET3(RADEON_CNTL_PAINT, 7)); |
| OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL | |
| R5XX_GMC_BRUSH_8X8_MONO_FG_BG | |
| RADEON_GMC_DST_32BPP | |
| RADEON_GMC_SRC_DATATYPE_COLOR | |
| R5XX_GMC_CLR_CMP_CNTL_DIS | |
| R5XX_GMC_WR_MSK_DIS | |
| R5XX_ROP3_P |
| ); |
| OUT_RING(dstpixmap->pitch_offset); |
| OUT_RING(fill->bkcolor); |
| OUT_RING(fill->fcolor); |
| OUT_RING(fill->bmp0); |
| OUT_RING(fill->bmp1); |
| OUT_RING((y0<<16)|x0); |
| OUT_RING((y1<<16)|x1); |
| if( (fill->border & 0xFF000000) != 0) |
| { |
| CP_REG(R5XX_DP_GUI_MASTER_CNTL, |
| RADEON_GMC_DST_PITCH_OFFSET_CNTL | |
| RADEON_GMC_BRUSH_SOLID_COLOR | |
| RADEON_GMC_DST_32BPP | |
| RADEON_GMC_SRC_DATATYPE_COLOR | |
| R5XX_GMC_CLR_CMP_CNTL_DIS | |
| R5XX_GMC_WR_MSK_DIS | |
| R5XX_ROP3_P |
| ); |
| CP_REG(R5XX_DP_BRUSH_FRGD_CLR, fill->border); |
| if( y0 == fill->y) |
| { |
| CP_REG(R5XX_DST_Y_X,(y0<<16)|x0); |
| CP_REG(R5XX_DST_WIDTH_HEIGHT,(w<<16)|1); |
| y0++; |
| h--; |
| } |
| if( y1 == yend ) |
| { |
| CP_REG(R5XX_DST_Y_X,(y1<<16)|x0); |
| CP_REG(R5XX_DST_WIDTH_HEIGHT,(w<<16)|1); |
| h--; |
| } |
| if( (h > 0) && (x0 == fill->x)) |
| { |
| CP_REG(R5XX_DST_Y_X,(y0<<16)|x0); |
| CP_REG(R5XX_DST_WIDTH_HEIGHT,(1<<16)|h); |
| } |
| if( (h > 0) && (x1 == xend)) |
| { |
| CP_REG(R5XX_DST_Y_X,(y0<<16)|x1); |
| CP_REG(R5XX_DST_WIDTH_HEIGHT,(1<<16)|h); |
| } |
| }; |
| COMMIT_RING(); |
| #endif |
| unlock_device(); |
| }; |
| return ERR_OK; |
| }; |
| #define ADDRREG(addr) ((volatile u32_t *)(rhd.MMIOBase + (addr))) |
| static int blit_host(u32_t dstpitch, int dstx, int dsty, |
| u32_t src, int srcx, int srcy, |
| int w, int h, int srcpitch, Bool trans, color_t key) |
| { |
| u32_t dp_cntl; |
| color_t *src_addr; |
| lock_device(); |
| #if R300_PIO |
| dp_cntl = RADEON_GMC_DST_PITCH_OFFSET_CNTL | |
| RADEON_GMC_BRUSH_NONE | |
| RADEON_GMC_DST_32BPP | |
| RADEON_GMC_SRC_DATATYPE_COLOR | |
| RADEON_DP_SRC_SOURCE_HOST_DATA | |
| R5XX_GMC_WR_MSK_DIS | |
| R5XX_ROP3_S; |
| if( trans == FALSE ) |
| { |
| dp_cntl|= R5XX_GMC_CLR_CMP_CNTL_DIS; |
| FIFOWait(5); |
| } |
| else |
| FIFOWait(8); |
| OUTREG(R5XX_DP_GUI_MASTER_CNTL, dp_cntl); |
| OUTREG(R5XX_DP_CNTL, R5XX_DST_X_LEFT_TO_RIGHT | |
| R5XX_DST_Y_TOP_TO_BOTTOM); |
| OUTREG(R5XX_DST_PITCH_OFFSET, dstpitch); |
| if( trans ) |
| { |
| OUTREG(R5XX_CLR_CMP_CLR_SRC, key); |
| OUTREG(R5XX_CLR_CMP_MASK, R5XX_CLR_CMP_MSK); |
| OUTREG(R5XX_CLR_CMP_CNTL, R5XX_SRC_CMP_EQ_COLOR | |
| R5XX_CLR_CMP_SRC_SOURCE); |
| }; |
| OUTREG(RADEON_DST_Y_X, (dsty << 16) | (dstx & 0xffff)); |
| OUTREG(RADEON_DST_HEIGHT_WIDTH, (h << 16) | w); |
| src_addr = &((color_t*)src)[srcpitch*srcy/4+srcx]; |
| while ( h-- ) |
| { |
| color_t *tmp_src = src_addr; |
| src_addr += srcpitch/4; |
| int left = w; |
| while( left ) |
| { |
| volatile u32_t *d; |
| if( left > 8 ) |
| { |
| int i; |
| R5xxFIFOWait(8); |
| d = ADDRREG(RADEON_HOST_DATA0); |
| /* Unrolling doesn't improve performance */ |
| for ( i = 0; i < 8; i++) |
| *d++ = *tmp_src++; |
| left -= 8; |
| } |
| else |
| { |
| R5xxFIFOWait(left); |
| if( h ) |
| d = ADDRREG(RADEON_HOST_DATA7) - (left - 1); |
| else |
| d = ADDRREG(RADEON_HOST_DATA_LAST) - (left - 1); |
| for ( ; left; --left) |
| *d++ = *tmp_src++; |
| left = 0; |
| }; |
| }; |
| }; |
| #endif |
| unlock_device(); |
| return ERR_OK; |
| } |
| int Blit(io_blit_t *blit) |
| { |
| clip_t src_clip, dst_clip; |
| local_pixmap_t *srcpixmap; |
| local_pixmap_t *dstpixmap; |
| u32_t srcpitchoffset; |
| Bool need_sync = FALSE; |
| dstpixmap = (blit->dstpix == (void*)-1) ? &scr_pixmap : blit->dstpix ; |
| srcpixmap = (blit->srcpix == (void*)-1) ? &scr_pixmap : blit->srcpix ; |
| src_clip.xmin = 0; |
| src_clip.ymin = 0; |
| src_clip.xmax = srcpixmap->width-1; |
| src_clip.ymax = srcpixmap->height-1; |
| dst_clip.xmin = 0; |
| dst_clip.ymin = 0; |
| dst_clip.xmax = dstpixmap->width-1; |
| dst_clip.ymax = dstpixmap->height-1; |
| if( !blit_clip(&dst_clip, &blit->dst_x, &blit->dst_y, |
| &src_clip, &blit->src_x, &blit->src_y, |
| &blit->w, &blit->h) ) |
| { |
| u32_t *ring, write; |
| /* |
| if( (srcpixmap->flags & PX_MEM_MASK)==PX_MEM_SYSTEM) |
| return blit_host(dstpixmap->pitch_offset, |
| blit->dst_x, blit->dst_y, |
| srcpixmap->mapped, |
| blit->src_x, blit->src_y, |
| blit->w, blit->h, |
| srcpixmap->pitch, |
| FALSE, 0 ); |
| */ |
| // if( (srcpixmap->flags & PX_MEM_MASK)==PX_MEM_SYSTEM) |
| // { |
| // srcpitchoffset = bind_pixmap(srcpixmap); |
| // need_sync = TRUE; |
| // } |
| // else |
| srcpitchoffset = srcpixmap->pitch_offset; |
| lock_device(); |
| #if R300_PIO |
| FIFOWait(7); |
| OUTREG(R5XX_DP_GUI_MASTER_CNTL, |
| RADEON_GMC_SRC_PITCH_OFFSET_CNTL | |
| RADEON_GMC_DST_PITCH_OFFSET_CNTL | |
| RADEON_GMC_BRUSH_NONE | |
| RADEON_GMC_DST_32BPP | |
| RADEON_GMC_SRC_DATATYPE_COLOR | |
| RADEON_DP_SRC_SOURCE_MEMORY | |
| R5XX_GMC_CLR_CMP_CNTL_DIS | |
| R5XX_GMC_WR_MSK_DIS | |
| R5XX_ROP3_S |
| ); |
| OUTREG(R5XX_DP_CNTL, R5XX_DST_X_LEFT_TO_RIGHT | R5XX_DST_Y_TOP_TO_BOTTOM); |
| OUTREG(R5XX_DST_PITCH_OFFSET, dstpixmap->pitch_offset); |
| OUTREG(R5XX_SRC_PITCH_OFFSET, srcpitchoffset); |
| OUTREG(R5XX_SRC_Y_X,(blit->src_y<<16)|blit->src_x); |
| OUTREG(R5XX_DST_Y_X,(blit->dst_y<<16)|blit->dst_x); |
| OUTREG(R5XX_DST_HEIGHT_WIDTH,(blit->h<<16)|blit->w); |
| #else |
| BEGIN_RING(7); |
| OUT_RING(CP_PACKET3(RADEON_CNTL_BITBLT, 5)); |
| OUT_RING(RADEON_GMC_SRC_PITCH_OFFSET_CNTL | |
| RADEON_GMC_DST_PITCH_OFFSET_CNTL | |
| RADEON_GMC_BRUSH_NONE | |
| RADEON_GMC_DST_32BPP | |
| RADEON_GMC_SRC_DATATYPE_COLOR | |
| RADEON_DP_SRC_SOURCE_MEMORY | |
| R5XX_GMC_CLR_CMP_CNTL_DIS | |
| R5XX_GMC_WR_MSK_DIS | |
| R5XX_ROP3_S |
| ); |
| OUT_RING(srcpitchoffset); |
| OUT_RING(dstpixmap->pitch_offset); |
| OUT_RING((blit->src_x<<16)|blit->src_y); |
| OUT_RING((blit->dst_x<<16)|blit->dst_y); |
| OUT_RING((blit->w<<16)|blit->h); |
| COMMIT_RING(); |
| #endif |
| if( need_sync == TRUE ) |
| R5xx2DIdleLocal(); |
| unlock_device(); |
| }; |
| return ERR_OK; |
| }; |
| int BlitTransparent(io_blit_t *blit) |
| { |
| clip_t src_clip, dst_clip; |
| local_pixmap_t *srcpixmap; |
| local_pixmap_t *dstpixmap; |
| u32_t srcpitchoffset; |
| Bool need_sync = FALSE; |
| // dbgprintf("Transblit src: %x dst: %x\n",blit->srcpix, blit->dstpix); |
| dstpixmap = (blit->dstpix == (void*)-1) ? &scr_pixmap : blit->dstpix ; |
| srcpixmap = (blit->srcpix == (void*)-1) ? &scr_pixmap : blit->srcpix ; |
| //dbgprintf("srcpixmap: %x dstpixmap: %x\n",srcpixmap, dstpixmap); |
| //dbgprintf("dst.width: %d dst.height: %d\n", dstpixmap->width,dstpixmap->height); |
| //dbgprintf("src.width: %d src.height: %d\n", srcpixmap->width,srcpixmap->height); |
| //dbgprintf("srcpitch: %x dstpitch: %x\n", |
| // srcpixmap->pitch_offset,dstpixmap->pitch_offset); |
| src_clip.xmin = 0; |
| src_clip.ymin = 0; |
| src_clip.xmax = srcpixmap->width-1; |
| src_clip.ymax = srcpixmap->height-1; |
| dst_clip.xmin = 0; |
| dst_clip.ymin = 0; |
| dst_clip.xmax = dstpixmap->width-1; |
| dst_clip.ymax = dstpixmap->height-1; |
| if( !blit_clip(&dst_clip, &blit->dst_x, &blit->dst_y, |
| &src_clip, &blit->src_x, &blit->src_y, |
| &blit->w, &blit->h) ) |
| { |
| u32_t *ring, write; |
| // if( (srcpixmap->flags & PX_MEM_MASK)==PX_MEM_SYSTEM) |
| // { |
| // srcpitchoffset = bind_pixmap(srcpixmap); |
| // need_sync = TRUE; |
| // } |
| // else |
| srcpitchoffset = srcpixmap->pitch_offset; |
| lock_device(); |
| #if R300_PIO |
| FIFOWait(10); |
| OUTREG(R5XX_DP_GUI_MASTER_CNTL, |
| RADEON_GMC_SRC_PITCH_OFFSET_CNTL | |
| RADEON_GMC_DST_PITCH_OFFSET_CNTL | |
| RADEON_GMC_BRUSH_NONE | |
| RADEON_GMC_DST_32BPP | |
| RADEON_GMC_SRC_DATATYPE_COLOR | |
| RADEON_DP_SRC_SOURCE_MEMORY | |
| R5XX_GMC_WR_MSK_DIS | |
| R5XX_ROP3_S |
| ); |
| OUTREG(R5XX_DP_CNTL, R5XX_DST_X_LEFT_TO_RIGHT | R5XX_DST_Y_TOP_TO_BOTTOM); |
| OUTREG(R5XX_CLR_CMP_CLR_SRC, blit->key); |
| OUTREG(R5XX_CLR_CMP_MASK, R5XX_CLR_CMP_MSK); |
| OUTREG(R5XX_CLR_CMP_CNTL, R5XX_SRC_CMP_EQ_COLOR | R5XX_CLR_CMP_SRC_SOURCE); |
| OUTREG(R5XX_DST_PITCH_OFFSET, dstpixmap->pitch_offset); |
| OUTREG(R5XX_SRC_PITCH_OFFSET, srcpitchoffset); |
| OUTREG(R5XX_SRC_Y_X,(blit->src_y<<16)|blit->src_x); |
| OUTREG(R5XX_DST_Y_X,(blit->dst_y<<16)|blit->dst_x); |
| OUTREG(R5XX_DST_HEIGHT_WIDTH,(blit->h<<16)|blit->w); |
| #else |
| BEGIN_RING(10); |
| OUT_RING(CP_PACKET3(RADEON_CNTL_TRANBLT, 8)); |
| OUT_RING(RADEON_GMC_SRC_PITCH_OFFSET_CNTL | |
| RADEON_GMC_DST_PITCH_OFFSET_CNTL | |
| RADEON_GMC_BRUSH_NONE | |
| RADEON_GMC_DST_32BPP | |
| RADEON_GMC_SRC_DATATYPE_COLOR | |
| RADEON_DP_SRC_SOURCE_MEMORY | |
| R5XX_GMC_WR_MSK_DIS | |
| R5XX_ROP3_S |
| ); |
| OUT_RING(srcpitchoffset); |
| OUT_RING(dstpixmap->pitch_offset); |
| OUT_RING(R5XX_CLR_CMP_SRC_SOURCE | R5XX_SRC_CMP_EQ_COLOR); |
| OUT_RING(blit->key); |
| OUT_RING(0xFFFFFFFF); |
| OUT_RING((blit->src_x<<16)|blit->src_y); |
| OUT_RING((blit->dst_x<<16)|blit->dst_y); |
| OUT_RING((blit->w<<16)|blit->h); |
| COMMIT_RING(); |
| #endif |
| if( need_sync == TRUE ) |
| R5xx2DIdleLocal(); |
| unlock_device(); |
| }; |
| return ERR_OK; |
| } |
| /drivers/old/ati2d/accel_3d.inc |
|---|
| 0,0 → 1,1218 |
| #define BEGIN_ACCEL(n) BEGIN_RING(2*(n)) |
| //#define FINISH_ACCEL() ADVANCE_RING() |
| #define FINISH_ACCEL() COMMIT_RING() |
| #define OUT_ACCEL_REG(reg, val) OUT_RING_REG(reg, val) |
| #define RADEON_SWITCH_TO_3D() \ |
| do { \ |
| u32_t wait_until = 0; \ |
| BEGIN_ACCEL(1); \ |
| wait_until |= RADEON_WAIT_HOST_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN; \ |
| OUT_ACCEL_REG(RADEON_WAIT_UNTIL, wait_until); \ |
| FINISH_ACCEL(); \ |
| } while (0); |
| struct blendinfo { |
| Bool dst_alpha; |
| Bool src_alpha; |
| u32_t blend_cntl; |
| }; |
| static struct blendinfo RadeonBlendOp[] = { |
| /* 0 - Clear */ |
| {0, 0, RADEON_SRC_BLEND_GL_ZERO | RADEON_DST_BLEND_GL_ZERO}, |
| /* 1 - Src */ |
| {0, 0, RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO}, |
| /* 2 - Dst */ |
| {0, 0, RADEON_SRC_BLEND_GL_ZERO | RADEON_DST_BLEND_GL_ONE}, |
| /* 3 - Over */ |
| {0, 1, RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA}, |
| /* 4 - OverReverse */ |
| {1, 0, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | RADEON_DST_BLEND_GL_ONE}, |
| /* 5 - In */ |
| {1, 0, RADEON_SRC_BLEND_GL_DST_ALPHA | RADEON_DST_BLEND_GL_ZERO}, |
| /* 6 - InReverse */ |
| {0, 1, RADEON_SRC_BLEND_GL_ZERO | RADEON_DST_BLEND_GL_SRC_ALPHA}, |
| /* 7 - Out */ |
| {1, 0, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | RADEON_DST_BLEND_GL_ZERO}, |
| /* 8 - OutReverse */ |
| {0, 1, RADEON_SRC_BLEND_GL_ZERO | RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA}, |
| /* 9 - Atop */ |
| {1, 1, RADEON_SRC_BLEND_GL_DST_ALPHA | RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA}, |
| /* 10- AtopReverse */ |
| {1, 1, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | RADEON_DST_BLEND_GL_SRC_ALPHA}, |
| /* 11 - Xor */ |
| {1, 1, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA}, |
| /* 12 - Add */ |
| {0, 0, RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ONE}, |
| }; |
| static void Init3DEngine(RHDPtr rhdPtr) |
| { |
| // RADEONInfoPtr info = RADEONPTR(pScrn); |
| u32_t gb_tile_config, su_reg_dest, vap_cntl; |
| // ACCEL_PREAMBLE(); |
| u32_t *ring, write; |
| // info->texW[0] = info->texH[0] = info->texW[1] = info->texH[1] = 1; |
| if (IS_R300_3D || IS_R500_3D) |
| { |
| BEGIN_ACCEL(3); |
| OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); |
| OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); |
| OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); |
| FINISH_ACCEL(); |
| if ( IS_R500_3D) |
| { |
| u32_t gb_pipe_sel = INREG(R400_GB_PIPE_SELECT); |
| rhdPtr->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1; |
| RADEONOUTPLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4)); |
| } |
| dbgprintf("Pipes count %d\n", rhdPtr->num_gb_pipes ); |
| gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 | R300_SUBPIXEL_1_16); |
| switch(rhdPtr->num_gb_pipes) { |
| case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break; |
| case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break; |
| case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break; |
| default: |
| case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break; |
| } |
| BEGIN_ACCEL(5); |
| OUT_ACCEL_REG(R300_GB_TILE_CONFIG, gb_tile_config); |
| OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); |
| OUT_ACCEL_REG(R300_DST_PIPE_CONFIG, R300_PIPE_AUTO_CONFIG); |
| OUT_ACCEL_REG(R300_GB_SELECT, 0); |
| OUT_ACCEL_REG(R300_GB_ENABLE, 0); |
| FINISH_ACCEL(); |
| if (IS_R500_3D) { |
| su_reg_dest = ((1 << rhdPtr->num_gb_pipes) - 1); |
| BEGIN_ACCEL(2); |
| OUT_ACCEL_REG(R500_SU_REG_DEST, su_reg_dest); |
| OUT_ACCEL_REG(R500_VAP_INDEX_OFFSET, 0); |
| FINISH_ACCEL(); |
| } |
| BEGIN_ACCEL(3); |
| OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); |
| OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); |
| OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); |
| FINISH_ACCEL(); |
| BEGIN_ACCEL(5); |
| OUT_ACCEL_REG(R300_GB_AA_CONFIG, 0); |
| OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); |
| OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); |
| OUT_ACCEL_REG(R300_GB_MSPOS0, ((8 << R300_MS_X0_SHIFT) | |
| (8 << R300_MS_Y0_SHIFT) | |
| (8 << R300_MS_X1_SHIFT) | |
| (8 << R300_MS_Y1_SHIFT) | |
| (8 << R300_MS_X2_SHIFT) | |
| (8 << R300_MS_Y2_SHIFT) | |
| (8 << R300_MSBD0_Y_SHIFT) | |
| (7 << R300_MSBD0_X_SHIFT))); |
| OUT_ACCEL_REG(R300_GB_MSPOS1, ((8 << R300_MS_X3_SHIFT) | |
| (8 << R300_MS_Y3_SHIFT) | |
| (8 << R300_MS_X4_SHIFT) | |
| (8 << R300_MS_Y4_SHIFT) | |
| (8 << R300_MS_X5_SHIFT) | |
| (8 << R300_MS_Y5_SHIFT) | |
| (8 << R300_MSBD1_SHIFT))); |
| FINISH_ACCEL(); |
| BEGIN_ACCEL(5); |
| OUT_ACCEL_REG(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL); |
| OUT_ACCEL_REG(R300_GA_POLY_MODE, R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE); |
| OUT_ACCEL_REG(R300_GA_ROUND_MODE, (R300_GEOMETRY_ROUND_NEAREST | |
| R300_COLOR_ROUND_NEAREST)); |
| OUT_ACCEL_REG(R300_GA_COLOR_CONTROL, (R300_RGB0_SHADING_GOURAUD | |
| R300_ALPHA0_SHADING_GOURAUD | |
| R300_RGB1_SHADING_GOURAUD | |
| R300_ALPHA1_SHADING_GOURAUD | |
| R300_RGB2_SHADING_GOURAUD | |
| R300_ALPHA2_SHADING_GOURAUD | |
| R300_RGB3_SHADING_GOURAUD | |
| R300_ALPHA3_SHADING_GOURAUD)); |
| OUT_ACCEL_REG(R300_GA_OFFSET, 0); |
| FINISH_ACCEL(); |
| BEGIN_ACCEL(5); |
| OUT_ACCEL_REG(R300_SU_TEX_WRAP, 0); |
| OUT_ACCEL_REG(R300_SU_POLY_OFFSET_ENABLE, 0); |
| OUT_ACCEL_REG(R300_SU_CULL_MODE, R300_FACE_NEG); |
| OUT_ACCEL_REG(R300_SU_DEPTH_SCALE, 0x4b7fffff); |
| OUT_ACCEL_REG(R300_SU_DEPTH_OFFSET, 0); |
| FINISH_ACCEL(); |
| /* setup the VAP */ |
| if (rhdPtr->has_tcl) |
| vap_cntl = ((5 << R300_PVS_NUM_SLOTS_SHIFT) | |
| (5 << R300_PVS_NUM_CNTLRS_SHIFT) | |
| (9 << R300_VF_MAX_VTX_NUM_SHIFT)); |
| else |
| vap_cntl = ((10 << R300_PVS_NUM_SLOTS_SHIFT) | |
| (5 << R300_PVS_NUM_CNTLRS_SHIFT) | |
| (5 << R300_VF_MAX_VTX_NUM_SHIFT)); |
| if (rhdPtr->ChipSet == RHD_FAMILY_RV515) |
| vap_cntl |= (2 << R300_PVS_NUM_FPUS_SHIFT); |
| else if ((rhdPtr->ChipSet == RHD_FAMILY_RV530) || |
| (rhdPtr->ChipSet == RHD_FAMILY_RV560)) |
| vap_cntl |= (5 << R300_PVS_NUM_FPUS_SHIFT); |
| else if (rhdPtr->ChipSet == RHD_FAMILY_R420) |
| vap_cntl |= (6 << R300_PVS_NUM_FPUS_SHIFT); |
| else if ((rhdPtr->ChipSet == RHD_FAMILY_R520) || |
| (rhdPtr->ChipSet == RHD_FAMILY_R580) || |
| (rhdPtr->ChipSet == RHD_FAMILY_RV570)) |
| vap_cntl |= (8 << R300_PVS_NUM_FPUS_SHIFT); |
| else |
| vap_cntl |= (4 << R300_PVS_NUM_FPUS_SHIFT); |
| if (rhdPtr->has_tcl) |
| BEGIN_ACCEL(15); |
| else |
| BEGIN_ACCEL(9); |
| OUT_ACCEL_REG(R300_VAP_VTX_STATE_CNTL, 0); |
| OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0); |
| if (rhdPtr->has_tcl) |
| OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, 0); |
| else |
| OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, R300_PVS_BYPASS); |
| OUT_ACCEL_REG(R300_VAP_CNTL, vap_cntl); |
| OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0); |
| OUT_ACCEL_REG(R300_VAP_VTE_CNTL, R300_VTX_XY_FMT | R300_VTX_Z_FMT); |
| OUT_ACCEL_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0); |
| OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0, |
| ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) | |
| (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) | |
| (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_0_SHIFT) | |
| (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_0_SHIFT) | |
| ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) |
| << R300_WRITE_ENA_0_SHIFT) | |
| (R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) | |
| (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) | |
| (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_1_SHIFT) | |
| (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_1_SHIFT) | |
| ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) |
| << R300_WRITE_ENA_1_SHIFT))); |
| OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_1, |
| ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_2_SHIFT) | |
| (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_2_SHIFT) | |
| (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_2_SHIFT) | |
| (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_2_SHIFT) | |
| ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) |
| << R300_WRITE_ENA_2_SHIFT))); |
| if (rhdPtr->has_tcl) { |
| OUT_ACCEL_REG(R300_VAP_PVS_FLOW_CNTL_OPC, 0); |
| OUT_ACCEL_REG(R300_VAP_GB_VERT_CLIP_ADJ, 0x3f800000); |
| OUT_ACCEL_REG(R300_VAP_GB_VERT_DISC_ADJ, 0x3f800000); |
| OUT_ACCEL_REG(R300_VAP_GB_HORZ_CLIP_ADJ, 0x3f800000); |
| OUT_ACCEL_REG(R300_VAP_GB_HORZ_DISC_ADJ, 0x3f800000); |
| OUT_ACCEL_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE); |
| } |
| FINISH_ACCEL(); |
| /* pre-load the vertex shaders */ |
| if (rhdPtr->has_tcl) { |
| /* exa mask shader program */ |
| BEGIN_ACCEL(13); |
| OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0); |
| /* PVS inst 0 */ |
| OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
| (R300_PVS_DST_OPCODE(R300_VE_ADD) | |
| R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
| R300_PVS_DST_OFFSET(0) | |
| R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
| R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
| OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
| (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
| R300_PVS_SRC_OFFSET(0) | |
| R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
| R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
| R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
| R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
| OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
| (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
| R300_PVS_SRC_OFFSET(0) | |
| R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
| OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
| (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
| R300_PVS_SRC_OFFSET(0) | |
| R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
| /* PVS inst 1 */ |
| OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
| (R300_PVS_DST_OPCODE(R300_VE_ADD) | |
| R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
| R300_PVS_DST_OFFSET(1) | |
| R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
| R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
| OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
| (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
| R300_PVS_SRC_OFFSET(6) | |
| R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
| R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
| R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
| R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
| OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
| (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
| R300_PVS_SRC_OFFSET(6) | |
| R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
| OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
| (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
| R300_PVS_SRC_OFFSET(6) | |
| R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
| /* PVS inst 2 */ |
| OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
| (R300_PVS_DST_OPCODE(R300_VE_ADD) | |
| R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
| R300_PVS_DST_OFFSET(2) | |
| R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
| R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
| OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
| (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
| R300_PVS_SRC_OFFSET(7) | |
| R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
| R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
| R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
| R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
| OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
| (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
| R300_PVS_SRC_OFFSET(7) | |
| R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
| OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
| (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
| R300_PVS_SRC_OFFSET(7) | |
| R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
| FINISH_ACCEL(); |
| BEGIN_ACCEL(9); |
| /* exa no mask instruction */ |
| OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 3); |
| /* PVS inst 0 */ |
| OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
| (R300_PVS_DST_OPCODE(R300_VE_ADD) | |
| R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
| R300_PVS_DST_OFFSET(0) | |
| R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
| R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
| OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
| (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
| R300_PVS_SRC_OFFSET(0) | |
| R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
| R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
| R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
| R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
| OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
| (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
| R300_PVS_SRC_OFFSET(0) | |
| R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
| OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
| (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
| R300_PVS_SRC_OFFSET(0) | |
| R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
| /* PVS inst 1 */ |
| OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
| (R300_PVS_DST_OPCODE(R300_VE_ADD) | |
| R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
| R300_PVS_DST_OFFSET(1) | |
| R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
| R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
| OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
| (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
| R300_PVS_SRC_OFFSET(6) | |
| R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
| R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
| R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
| R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
| OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
| (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
| R300_PVS_SRC_OFFSET(6) | |
| R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
| OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
| (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
| R300_PVS_SRC_OFFSET(6) | |
| R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
| FINISH_ACCEL(); |
| /* Xv shader program */ |
| BEGIN_ACCEL(9); |
| OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 5); |
| OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
| (R300_PVS_DST_OPCODE(R300_VE_ADD) | |
| R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
| R300_PVS_DST_OFFSET(0) | |
| R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
| R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
| OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
| (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
| R300_PVS_SRC_OFFSET(0) | |
| R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
| R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
| R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
| R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
| OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
| (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
| R300_PVS_SRC_OFFSET(0) | |
| R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
| OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
| (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
| R300_PVS_SRC_OFFSET(0) | |
| R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
| OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
| (R300_PVS_DST_OPCODE(R300_VE_ADD) | |
| R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
| R300_PVS_DST_OFFSET(1) | |
| R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
| R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
| OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
| (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
| R300_PVS_SRC_OFFSET(6) | |
| R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
| R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
| R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
| R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
| OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
| (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
| R300_PVS_SRC_OFFSET(6) | |
| R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
| OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
| (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
| R300_PVS_SRC_OFFSET(6) | |
| R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
| FINISH_ACCEL(); |
| } |
| /* pre-load the RS instructions */ |
| BEGIN_ACCEL(4); |
| if (IS_R300_3D) { |
| /* rasterizer source table |
| * R300_RS_TEX_PTR is the offset into the input RS stream |
| * 0,1 are tex0 |
| * 2,3 are tex1 |
| */ |
| OUT_ACCEL_REG(R300_RS_IP_0, |
| (R300_RS_TEX_PTR(0) | |
| R300_RS_SEL_S(R300_RS_SEL_C0) | |
| R300_RS_SEL_T(R300_RS_SEL_C1) | |
| R300_RS_SEL_R(R300_RS_SEL_K0) | |
| R300_RS_SEL_Q(R300_RS_SEL_K1))); |
| OUT_ACCEL_REG(R300_RS_IP_1, |
| (R300_RS_TEX_PTR(2) | |
| R300_RS_SEL_S(R300_RS_SEL_C0) | |
| R300_RS_SEL_T(R300_RS_SEL_C1) | |
| R300_RS_SEL_R(R300_RS_SEL_K0) | |
| R300_RS_SEL_Q(R300_RS_SEL_K1))); |
| /* src tex */ |
| /* R300_INST_TEX_ID - select the RS source table entry |
| * R300_INST_TEX_ADDR - the FS temp register for the texture data |
| */ |
| OUT_ACCEL_REG(R300_RS_INST_0, (R300_INST_TEX_ID(0) | |
| R300_RS_INST_TEX_CN_WRITE | |
| R300_INST_TEX_ADDR(0))); |
| /* mask tex */ |
| OUT_ACCEL_REG(R300_RS_INST_1, (R300_INST_TEX_ID(1) | |
| R300_RS_INST_TEX_CN_WRITE | |
| R300_INST_TEX_ADDR(1))); |
| } else { |
| /* rasterizer source table |
| * R300_RS_TEX_PTR is the offset into the input RS stream |
| * 0,1 are tex0 |
| * 2,3 are tex1 |
| */ |
| OUT_ACCEL_REG(R500_RS_IP_0, ((0 << R500_RS_IP_TEX_PTR_S_SHIFT) | |
| (1 << R500_RS_IP_TEX_PTR_T_SHIFT) | |
| (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | |
| (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT))); |
| OUT_ACCEL_REG(R500_RS_IP_1, ((2 << R500_RS_IP_TEX_PTR_S_SHIFT) | |
| (3 << R500_RS_IP_TEX_PTR_T_SHIFT) | |
| (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | |
| (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT))); |
| /* src tex */ |
| /* R500_RS_INST_TEX_ID_SHIFT - select the RS source table entry |
| * R500_RS_INST_TEX_ADDR_SHIFT - the FS temp register for the texture data |
| */ |
| OUT_ACCEL_REG(R500_RS_INST_0, ((0 << R500_RS_INST_TEX_ID_SHIFT) | |
| R500_RS_INST_TEX_CN_WRITE | |
| (0 << R500_RS_INST_TEX_ADDR_SHIFT))); |
| /* mask tex */ |
| OUT_ACCEL_REG(R500_RS_INST_1, ((1 << R500_RS_INST_TEX_ID_SHIFT) | |
| R500_RS_INST_TEX_CN_WRITE | |
| (1 << R500_RS_INST_TEX_ADDR_SHIFT))); |
| } |
| FINISH_ACCEL(); |
| /* pre-load FS tex instructions */ |
| if (IS_R300_3D) { |
| BEGIN_ACCEL(2); |
| /* tex inst for src texture */ |
| OUT_ACCEL_REG(R300_US_TEX_INST_0, |
| (R300_TEX_SRC_ADDR(0) | |
| R300_TEX_DST_ADDR(0) | |
| R300_TEX_ID(0) | |
| R300_TEX_INST(R300_TEX_INST_LD))); |
| /* tex inst for mask texture */ |
| OUT_ACCEL_REG(R300_US_TEX_INST_1, |
| (R300_TEX_SRC_ADDR(1) | |
| R300_TEX_DST_ADDR(1) | |
| R300_TEX_ID(1) | |
| R300_TEX_INST(R300_TEX_INST_LD))); |
| FINISH_ACCEL(); |
| } |
| if (IS_R300_3D) { |
| BEGIN_ACCEL(9); |
| OUT_ACCEL_REG(R300_US_CONFIG, (0 << R300_NLEVEL_SHIFT) | R300_FIRST_TEX); |
| OUT_ACCEL_REG(R300_US_PIXSIZE, 1); /* highest temp used */ |
| OUT_ACCEL_REG(R300_US_CODE_ADDR_0, |
| (R300_ALU_START(0) | |
| R300_ALU_SIZE(0) | |
| R300_TEX_START(0) | |
| R300_TEX_SIZE(0))); |
| OUT_ACCEL_REG(R300_US_CODE_ADDR_1, |
| (R300_ALU_START(0) | |
| R300_ALU_SIZE(0) | |
| R300_TEX_START(0) | |
| R300_TEX_SIZE(0))); |
| OUT_ACCEL_REG(R300_US_CODE_ADDR_2, |
| (R300_ALU_START(0) | |
| R300_ALU_SIZE(0) | |
| R300_TEX_START(0) | |
| R300_TEX_SIZE(0))); |
| } else { |
| BEGIN_ACCEL(7); |
| OUT_ACCEL_REG(R300_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO); |
| OUT_ACCEL_REG(R300_US_PIXSIZE, 1); /* highest temp used */ |
| OUT_ACCEL_REG(R500_US_FC_CTRL, 0); |
| } |
| OUT_ACCEL_REG(R300_US_W_FMT, 0); |
| OUT_ACCEL_REG(R300_US_OUT_FMT_1, (R300_OUT_FMT_UNUSED | |
| R300_OUT_FMT_C0_SEL_BLUE | |
| R300_OUT_FMT_C1_SEL_GREEN | |
| R300_OUT_FMT_C2_SEL_RED | |
| R300_OUT_FMT_C3_SEL_ALPHA)); |
| OUT_ACCEL_REG(R300_US_OUT_FMT_2, (R300_OUT_FMT_UNUSED | |
| R300_OUT_FMT_C0_SEL_BLUE | |
| R300_OUT_FMT_C1_SEL_GREEN | |
| R300_OUT_FMT_C2_SEL_RED | |
| R300_OUT_FMT_C3_SEL_ALPHA)); |
| OUT_ACCEL_REG(R300_US_OUT_FMT_3, (R300_OUT_FMT_UNUSED | |
| R300_OUT_FMT_C0_SEL_BLUE | |
| R300_OUT_FMT_C1_SEL_GREEN | |
| R300_OUT_FMT_C2_SEL_RED | |
| R300_OUT_FMT_C3_SEL_ALPHA)); |
| FINISH_ACCEL(); |
| BEGIN_ACCEL(3); |
| OUT_ACCEL_REG(R300_FG_DEPTH_SRC, 0); |
| OUT_ACCEL_REG(R300_FG_FOG_BLEND, 0); |
| OUT_ACCEL_REG(R300_FG_ALPHA_FUNC, 0); |
| FINISH_ACCEL(); |
| BEGIN_ACCEL(13); |
| OUT_ACCEL_REG(R300_RB3D_ABLENDCNTL, 0); |
| OUT_ACCEL_REG(R300_RB3D_ZSTENCILCNTL, 0); |
| OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); |
| OUT_ACCEL_REG(R300_RB3D_BW_CNTL, 0); |
| OUT_ACCEL_REG(R300_RB3D_ZCNTL, 0); |
| OUT_ACCEL_REG(R300_RB3D_ZTOP, 0); |
| OUT_ACCEL_REG(R300_RB3D_ROPCNTL, 0); |
| OUT_ACCEL_REG(R300_RB3D_AARESOLVE_CTL, 0); |
| OUT_ACCEL_REG(R300_RB3D_COLOR_CHANNEL_MASK, (R300_BLUE_MASK_EN | |
| R300_GREEN_MASK_EN | |
| R300_RED_MASK_EN | |
| R300_ALPHA_MASK_EN)); |
| OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); |
| OUT_ACCEL_REG(R300_RB3D_CCTL, 0); |
| OUT_ACCEL_REG(R300_RB3D_DITHER_CTL, 0); |
| OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); |
| FINISH_ACCEL(); |
| BEGIN_ACCEL(7); |
| OUT_ACCEL_REG(R300_SC_EDGERULE, 0xA5294A5); |
| OUT_ACCEL_REG(R300_SC_SCISSOR0, ((0 << R300_SCISSOR_X_SHIFT) | |
| (0 << R300_SCISSOR_Y_SHIFT))); |
| OUT_ACCEL_REG(R300_SC_SCISSOR1, ((8191 << R300_SCISSOR_X_SHIFT) | |
| (8191 << R300_SCISSOR_Y_SHIFT))); |
| if (IS_R300_3D) { |
| /* clip has offset 1440 */ |
| OUT_ACCEL_REG(R300_SC_CLIP_0_A, ((1088 << R300_CLIP_X_SHIFT) | |
| (1088 << R300_CLIP_Y_SHIFT))); |
| OUT_ACCEL_REG(R300_SC_CLIP_0_B, (((1080 + 2920) << R300_CLIP_X_SHIFT) | |
| ((1080 + 2920) << R300_CLIP_Y_SHIFT))); |
| } else { |
| OUT_ACCEL_REG(R300_SC_CLIP_0_A, ((0 << R300_CLIP_X_SHIFT) | |
| (0 << R300_CLIP_Y_SHIFT))); |
| OUT_ACCEL_REG(R300_SC_CLIP_0_B, ((4080 << R300_CLIP_X_SHIFT) | |
| (4080 << R300_CLIP_Y_SHIFT))); |
| } |
| OUT_ACCEL_REG(R300_SC_CLIP_RULE, 0xAAAA); |
| OUT_ACCEL_REG(R300_SC_SCREENDOOR, 0xffffff); |
| FINISH_ACCEL(); |
| } else if ((rhdPtr->ChipSet == RHD_FAMILY_RV250) || |
| (rhdPtr->ChipSet == RHD_FAMILY_RV280) || |
| (rhdPtr->ChipSet == RHD_FAMILY_RS300) || |
| (rhdPtr->ChipSet == RHD_FAMILY_R200)) { |
| BEGIN_ACCEL(7); |
| if (rhdPtr->ChipSet == RHD_FAMILY_RS300) { |
| OUT_ACCEL_REG(R200_SE_VAP_CNTL_STATUS, RADEON_TCL_BYPASS); |
| } else { |
| OUT_ACCEL_REG(R200_SE_VAP_CNTL_STATUS, 0); |
| } |
| OUT_ACCEL_REG(R200_PP_CNTL_X, 0); |
| OUT_ACCEL_REG(R200_PP_TXMULTI_CTL_0, 0); |
| OUT_ACCEL_REG(R200_SE_VTX_STATE_CNTL, 0); |
| OUT_ACCEL_REG(R200_RE_CNTL, 0x0); |
| OUT_ACCEL_REG(R200_SE_VTE_CNTL, 0); |
| OUT_ACCEL_REG(R200_SE_VAP_CNTL, R200_VAP_FORCE_W_TO_ONE | |
| R200_VAP_VF_MAX_VTX_NUM); |
| FINISH_ACCEL(); |
| BEGIN_ACCEL(5); |
| OUT_ACCEL_REG(RADEON_RE_TOP_LEFT, 0); |
| OUT_ACCEL_REG(RADEON_RE_WIDTH_HEIGHT, 0x07ff07ff); |
| OUT_ACCEL_REG(RADEON_AUX_SC_CNTL, 0); |
| OUT_ACCEL_REG(RADEON_RB3D_PLANEMASK, 0xffffffff); |
| OUT_ACCEL_REG(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD | |
| RADEON_BFACE_SOLID | |
| RADEON_FFACE_SOLID | |
| RADEON_VTX_PIX_CENTER_OGL | |
| RADEON_ROUND_MODE_ROUND | |
| RADEON_ROUND_PREC_4TH_PIX)); |
| FINISH_ACCEL(); |
| } else { |
| BEGIN_ACCEL(2); |
| if ((rhdPtr->ChipSet == RHD_FAMILY_RADEON) || |
| (rhdPtr->ChipSet == RHD_FAMILY_RV200)) |
| OUT_ACCEL_REG(RADEON_SE_CNTL_STATUS, 0); |
| else |
| OUT_ACCEL_REG(RADEON_SE_CNTL_STATUS, RADEON_TCL_BYPASS); |
| OUT_ACCEL_REG(RADEON_SE_COORD_FMT, |
| RADEON_VTX_XY_PRE_MULT_1_OVER_W0 | |
| RADEON_VTX_ST0_NONPARAMETRIC | |
| RADEON_VTX_ST1_NONPARAMETRIC | |
| RADEON_TEX1_W_ROUTING_USE_W0); |
| FINISH_ACCEL(); |
| BEGIN_ACCEL(5); |
| OUT_ACCEL_REG(RADEON_RE_TOP_LEFT, 0); |
| OUT_ACCEL_REG(RADEON_RE_WIDTH_HEIGHT, 0x07ff07ff); |
| OUT_ACCEL_REG(RADEON_AUX_SC_CNTL, 0); |
| OUT_ACCEL_REG(RADEON_RB3D_PLANEMASK, 0xffffffff); |
| OUT_ACCEL_REG(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD | |
| RADEON_BFACE_SOLID | |
| RADEON_FFACE_SOLID | |
| RADEON_VTX_PIX_CENTER_OGL | |
| RADEON_ROUND_MODE_ROUND | |
| RADEON_ROUND_PREC_4TH_PIX)); |
| FINISH_ACCEL(); |
| } |
| } |
| static Bool R300TextureSetup(int w, int h, int unit) |
| { |
| //RINFO_FROM_SCREEN(pPix->drawable.pScreen); |
| u32_t txfilter, txformat0, txformat1, txoffset, txpitch; |
| // int w = pPict->pDrawable->width; |
| // int h = pPict->pDrawable->height; |
| int i, pixel_shift; |
| //ACCEL_PREAMBLE(); |
| //TRACE; |
| //txpitch = exaGetPixmapPitch(pPix); |
| txpitch = rhd.displayWidth * 4; |
| // txoffset = exaGetPixmapOffset(pPix) + info->fbLocation + pScrn->fbOffset; |
| txoffset = rhd.FbIntAddress + rhd.FbScanoutStart; |
| if ((txoffset & 0x1f) != 0) |
| dbgprintf("Bad texture offset 0x%x\n", (int)txoffset); |
| if ((txpitch & 0x1f) != 0) |
| dbgprintf("Bad texture pitch 0x%x\n", (int)txpitch); |
| /* TXPITCH = pixels (texels) per line - 1 */ |
| pixel_shift = 32 >> 4; |
| txpitch >>= pixel_shift; |
| txpitch -= 1; |
| // if (RADEONPixmapIsColortiled(pPix)) |
| // txoffset |= R300_MACRO_TILE; |
| // for (i = 0; i < sizeof(R300TexFormats) / sizeof(R300TexFormats[0]); i++) |
| // { |
| // if (R300TexFormats[i].fmt == pPict->format) |
| // break; |
| // } |
| //txformat1 = R300TexFormats[i].card_fmt; |
| txformat1 = R300_EASY_TX_FORMAT(X, Y, Z, W, W8Z8Y8X8); |
| txformat0 = ((((w - 1) & 0x7ff) << R300_TXWIDTH_SHIFT) | |
| (((h - 1) & 0x7ff) << R300_TXHEIGHT_SHIFT)); |
| if (IS_R500_3D && ((w - 1) & 0x800)) |
| txpitch |= R500_TXWIDTH_11; |
| if (IS_R500_3D && ((h - 1) & 0x800)) |
| txpitch |= R500_TXHEIGHT_11; |
| /* Use TXPITCH instead of TXWIDTH for address computations: we could |
| * omit this if there is no padding, but there is no apparent advantage |
| * in doing so. |
| */ |
| txformat0 |= R300_TXPITCH_EN; |
| // info->texW[unit] = w; |
| // info->texH[unit] = h; |
| // if (pPict->repeat && !(unit == 0 && need_src_tile_x)) |
| // txfilter = R300_TX_CLAMP_S(R300_TX_CLAMP_WRAP); |
| // else |
| txfilter = R300_TX_CLAMP_S(R300_TX_CLAMP_CLAMP_GL); |
| // if (pPict->repeat && !(unit == 0 && need_src_tile_y)) |
| // txfilter |= R300_TX_CLAMP_T(R300_TX_CLAMP_WRAP); |
| // else |
| txfilter |= R300_TX_CLAMP_T(R300_TX_CLAMP_CLAMP_GL); |
| txfilter |= (unit << R300_TX_ID_SHIFT); |
| // switch (pPict->filter) { |
| // case PictFilterNearest: |
| txfilter |= (R300_TX_MAG_FILTER_NEAREST | R300_TX_MIN_FILTER_NEAREST); |
| // break; |
| // case PictFilterBilinear: |
| // txfilter |= (R300_TX_MAG_FILTER_LINEAR | R300_TX_MIN_FILTER_LINEAR); |
| // break; |
| // default: |
| // RADEON_FALLBACK(("Bad filter 0x%x\n", pPict->filter)); |
| // } |
| { |
| u32_t *ring, write; |
| BEGIN_ACCEL(7); |
| OUT_ACCEL_REG(R300_TX_FILTER0_0 + (unit * 4), txfilter); |
| OUT_ACCEL_REG(R300_TX_FILTER1_0 + (unit * 4), 0); |
| OUT_ACCEL_REG(R300_TX_FORMAT0_0 + (unit * 4), txformat0); |
| OUT_ACCEL_REG(R300_TX_FORMAT1_0 + (unit * 4), txformat1); |
| OUT_ACCEL_REG(R300_TX_FORMAT2_0 + (unit * 4), txpitch); |
| OUT_ACCEL_REG(R300_TX_OFFSET_0 + (unit * 4), txoffset); |
| // if (!pPict->repeat) |
| OUT_ACCEL_REG(R300_TX_BORDER_COLOR_0 + (unit * 4), 0); |
| FINISH_ACCEL(); |
| } |
| // if (pPict->transform != 0) { |
| // is_transform[unit] = TRUE; |
| // transform[unit] = pPict->transform; |
| // } else { |
| // is_transform[unit] = FALSE; |
| // } |
| return TRUE; |
| } |
| static u32_t RADEONGetBlendCntl(int op, u32_t dst_format) |
| { |
| u32_t sblend, dblend; |
| sblend = RadeonBlendOp[op].blend_cntl & RADEON_SRC_BLEND_MASK; |
| dblend = RadeonBlendOp[op].blend_cntl & RADEON_DST_BLEND_MASK; |
| /* If there's no dst alpha channel, adjust the blend op so that we'll treat |
| * it as always 1. |
| */ |
| if (PICT_FORMAT_A(dst_format) == 0 && RadeonBlendOp[op].dst_alpha) { |
| if (sblend == RADEON_SRC_BLEND_GL_DST_ALPHA) |
| sblend = RADEON_SRC_BLEND_GL_ONE; |
| else if (sblend == RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA) |
| sblend = RADEON_SRC_BLEND_GL_ZERO; |
| } |
| return sblend | dblend; |
| } |
| static Bool R300PrepareComposite(int op, int srcX, int srcY, |
| int dstX, int dstY, |
| int w, int h) |
| { |
| // RINFO_FROM_SCREEN(pDst->drawable.pScreen); |
| u32_t dst_format, dst_offset, dst_pitch; |
| u32_t txenable, colorpitch; |
| u32_t blendcntl; |
| int pixel_shift; |
| u32_t *ring, write; |
| //ACCEL_PREAMBLE(); |
| //TRACE; |
| //if (!info->XInited3D) |
| // RADEONInit3DEngine(pScrn); |
| //if (!R300GetDestFormat(pDstPicture, &dst_format)) |
| // return FALSE; |
| dst_format = R300_COLORFORMAT_ARGB8888; |
| pixel_shift = 32 >> 4; |
| //dst_offset = exaGetPixmapOffset(pDst) + info->fbLocation + pScrn->fbOffset; |
| dst_offset = rhd.FbIntAddress + rhd.FbScanoutStart; |
| //dst_pitch = exaGetPixmapPitch(pDst); |
| dst_pitch = rhd.displayWidth * 4; |
| colorpitch = dst_pitch >> pixel_shift; |
| // if (RADEONPixmapIsColortiled(pDst)) |
| // colorpitch |= R300_COLORTILE; |
| colorpitch |= dst_format; |
| if ((dst_offset & 0x0f) != 0) |
| dbgprintf("Bad destination offset 0x%x\n", (int)dst_offset); |
| if (((dst_pitch >> pixel_shift) & 0x7) != 0) |
| dbgprintf("Bad destination pitch 0x%x\n", (int)dst_pitch); |
| // if (!RADEONSetupSourceTile(pSrcPicture, pSrc, TRUE, FALSE)) |
| // return FALSE; |
| if (!R300TextureSetup(w, h, 0)) |
| return FALSE; |
| txenable = R300_TEX_0_ENABLE; |
| // RADEON_SWITCH_TO_3D(); |
| /* setup the VAP */ |
| BEGIN_ACCEL(7); |
| /* These registers define the number, type, and location of data submitted |
| * to the PVS unit of GA input (when PVS is disabled) |
| * DST_VEC_LOC is the slot in the PVS input vector memory when PVS/TCL is |
| * enabled. This memory provides the imputs to the vertex shader program |
| * and ordering is not important. When PVS/TCL is disabled, this field maps |
| * directly to the GA input memory and the order is signifigant. In |
| * PVS_BYPASS mode the order is as follows: |
| * Position |
| * Point Size |
| * Color 0-3 |
| * Textures 0-7 |
| * Fog |
| */ |
| OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_0, |
| ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) | |
| (0 << R300_SKIP_DWORDS_0_SHIFT) | |
| (0 << R300_DST_VEC_LOC_0_SHIFT) | |
| R300_SIGNED_0 | |
| (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) | |
| (0 << R300_SKIP_DWORDS_1_SHIFT) | |
| (6 << R300_DST_VEC_LOC_1_SHIFT) | |
| R300_LAST_VEC_1 | |
| R300_SIGNED_1)); |
| /* load the vertex shader |
| * We pre-load vertex programs in RADEONInit3DEngine(): |
| * - exa no mask |
| * - exa mask |
| * - Xv |
| * Here we select the offset of the vertex program we want to use |
| */ |
| OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_0, |
| ((3 << R300_PVS_FIRST_INST_SHIFT) | |
| (4 << R300_PVS_XYZW_VALID_INST_SHIFT) | |
| (4 << R300_PVS_LAST_INST_SHIFT))); |
| OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_1, |
| (4 << R300_PVS_LAST_VTX_SRC_INST_SHIFT)); |
| /* Position and one or two sets of 2 texture coordinates */ |
| OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_0, R300_VTX_POS_PRESENT); |
| OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_1, (2 << R300_TEX_0_COMP_CNT_SHIFT)); |
| OUT_ACCEL_REG(R300_TX_INVALTAGS, 0x0); |
| OUT_ACCEL_REG(R300_TX_ENABLE, txenable); |
| FINISH_ACCEL(); |
| /* setup pixel shader */ |
| if (IS_R300_3D) { |
| } else { |
| u32_t output_fmt; |
| u32_t src_color, src_alpha; |
| u32_t mask_color, mask_alpha; |
| if (PICT_FORMAT_RGB(PICT_a8r8g8b8) == 0) |
| src_color = (R500_ALU_RGB_R_SWIZ_A_0 | |
| R500_ALU_RGB_G_SWIZ_A_0 | |
| R500_ALU_RGB_B_SWIZ_A_0); |
| else |
| src_color = (R500_ALU_RGB_R_SWIZ_A_R | |
| R500_ALU_RGB_G_SWIZ_A_G | |
| R500_ALU_RGB_B_SWIZ_A_B); |
| if (PICT_FORMAT_A(PICT_a8r8g8b8) == 0) |
| src_alpha = R500_ALPHA_SWIZ_A_1; |
| else |
| src_alpha = R500_ALPHA_SWIZ_A_A; |
| mask_color = (R500_ALU_RGB_R_SWIZ_B_1 | |
| R500_ALU_RGB_G_SWIZ_B_1 | |
| R500_ALU_RGB_B_SWIZ_B_1); |
| mask_alpha = R500_ALPHA_SWIZ_B_1; |
| /* shader output swizzling */ |
| output_fmt = (R300_OUT_FMT_C4_8 | |
| R300_OUT_FMT_C0_SEL_BLUE | |
| R300_OUT_FMT_C1_SEL_GREEN | |
| R300_OUT_FMT_C2_SEL_RED | |
| R300_OUT_FMT_C3_SEL_ALPHA); |
| BEGIN_ACCEL(6); |
| OUT_ACCEL_REG(R300_RS_COUNT, |
| ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) | |
| R300_RS_COUNT_HIRES_EN)); |
| OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0) | R300_TX_OFFSET_RS(6)); |
| OUT_ACCEL_REG(R500_US_CODE_ADDR, (R500_US_CODE_START_ADDR(0) | |
| R500_US_CODE_END_ADDR(1))); |
| OUT_ACCEL_REG(R500_US_CODE_RANGE, (R500_US_CODE_RANGE_ADDR(0) | |
| R500_US_CODE_RANGE_SIZE(1))); |
| OUT_ACCEL_REG(R500_US_CODE_OFFSET, 0); |
| OUT_ACCEL_REG(R300_US_OUT_FMT_0, output_fmt); |
| FINISH_ACCEL(); |
| BEGIN_ACCEL(13); |
| OUT_ACCEL_REG(R500_GA_US_VECTOR_INDEX, 0); |
| /* tex inst for src texture */ |
| OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX | |
| R500_INST_TEX_SEM_WAIT | |
| R500_INST_RGB_WMASK_R | |
| R500_INST_RGB_WMASK_G | |
| R500_INST_RGB_WMASK_B | |
| R500_INST_ALPHA_WMASK | |
| R500_INST_RGB_CLAMP | |
| R500_INST_ALPHA_CLAMP)); |
| OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) | |
| R500_TEX_INST_LD | |
| R500_TEX_SEM_ACQUIRE | |
| R500_TEX_IGNORE_UNCOVERED)); |
| OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) | |
| R500_TEX_SRC_S_SWIZ_R | |
| R500_TEX_SRC_T_SWIZ_G | |
| R500_TEX_DST_ADDR(0) | |
| R500_TEX_DST_R_SWIZ_R | |
| R500_TEX_DST_G_SWIZ_G | |
| R500_TEX_DST_B_SWIZ_B | |
| R500_TEX_DST_A_SWIZ_A)); |
| OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_DX_ADDR(0) | |
| R500_DX_S_SWIZ_R | |
| R500_DX_T_SWIZ_R | |
| R500_DX_R_SWIZ_R | |
| R500_DX_Q_SWIZ_R | |
| R500_DY_ADDR(0) | |
| R500_DY_S_SWIZ_R | |
| R500_DY_T_SWIZ_R | |
| R500_DY_R_SWIZ_R | |
| R500_DY_Q_SWIZ_R)); |
| OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); |
| OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); |
| /* ALU inst */ |
| /* *_OMASK* - output component write mask */ |
| OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_OUT | |
| R500_INST_TEX_SEM_WAIT | |
| R500_INST_LAST | |
| R500_INST_RGB_OMASK_R | |
| R500_INST_RGB_OMASK_G | |
| R500_INST_RGB_OMASK_B | |
| R500_INST_ALPHA_OMASK | |
| R500_INST_RGB_CLAMP | |
| R500_INST_ALPHA_CLAMP)); |
| /* ALU inst |
| * temp addresses for texture inputs |
| * RGB_ADDR0 is src tex (temp 0) |
| * RGB_ADDR1 is mask tex (temp 1) |
| */ |
| OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) | |
| R500_RGB_ADDR1(1) | |
| R500_RGB_ADDR2(0))); |
| /* ALU inst |
| * temp addresses for texture inputs |
| * ALPHA_ADDR0 is src tex (temp 0) |
| * ALPHA_ADDR1 is mask tex (temp 1) |
| */ |
| OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) | |
| R500_ALPHA_ADDR1(1) | |
| R500_ALPHA_ADDR2(0))); |
| /* R500_ALU_RGB_TARGET - RGB render target */ |
| OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 | |
| src_color | |
| R500_ALU_RGB_SEL_B_SRC1 | |
| mask_color | |
| R500_ALU_RGB_TARGET(0))); |
| /* R500_ALPHA_RGB_TARGET - alpha render target */ |
| OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_OP_MAD | |
| R500_ALPHA_ADDRD(0) | |
| R500_ALPHA_SEL_A_SRC0 | |
| src_alpha | |
| R500_ALPHA_SEL_B_SRC1 | |
| mask_alpha | |
| R500_ALPHA_TARGET(0))); |
| OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_OP_MAD | |
| R500_ALU_RGBA_ADDRD(0) | |
| R500_ALU_RGBA_R_SWIZ_0 | |
| R500_ALU_RGBA_G_SWIZ_0 | |
| R500_ALU_RGBA_B_SWIZ_0 | |
| R500_ALU_RGBA_A_SWIZ_0)); |
| FINISH_ACCEL(); |
| } |
| BEGIN_ACCEL(3); |
| OUT_ACCEL_REG(R300_RB3D_COLOROFFSET0, dst_offset); |
| OUT_ACCEL_REG(R300_RB3D_COLORPITCH0, colorpitch); |
| blendcntl = RADEONGetBlendCntl(op, PICT_a8r8g8b8); |
| OUT_ACCEL_REG(R300_RB3D_BLENDCNTL, blendcntl | R300_ALPHA_BLEND_ENABLE | R300_READ_ENABLE); |
| FINISH_ACCEL(); |
| return TRUE; |
| } |
| static void RadeonCompositeTile(int srcX, int srcY, |
| int dstX, int dstY, |
| int w, int h) |
| { |
| // RINFO_FROM_SCREEN(pDst->drawable.pScreen); |
| int vtx_count; |
| xPointFixed srcTopLeft, srcTopRight, srcBottomLeft, srcBottomRight; |
| xPointFixed maskTopLeft, maskTopRight, maskBottomLeft, maskBottomRight; |
| u32_t *ring, write; |
| // ACCEL_PREAMBLE(); |
| // ENTER_DRAW(0); |
| /* ErrorF("RadeonComposite (%d,%d) (%d,%d) (%d,%d) (%d,%d)\n", |
| srcX, srcY, maskX, maskY,dstX, dstY, w, h); */ |
| srcTopLeft.x = IntToxFixed(srcX); |
| srcTopLeft.y = IntToxFixed(srcY); |
| srcTopRight.x = IntToxFixed(srcX + w); |
| srcTopRight.y = IntToxFixed(srcY); |
| srcBottomLeft.x = IntToxFixed(srcX); |
| srcBottomLeft.y = IntToxFixed(srcY + h); |
| srcBottomRight.x = IntToxFixed(srcX + w); |
| srcBottomRight.y = IntToxFixed(srcY + h); |
| /* |
| if (is_transform[0]) { |
| transformPoint(transform[0], &srcTopLeft); |
| transformPoint(transform[0], &srcTopRight); |
| transformPoint(transform[0], &srcBottomLeft); |
| transformPoint(transform[0], &srcBottomRight); |
| } |
| if (is_transform[1]) { |
| transformPoint(transform[1], &maskTopLeft); |
| transformPoint(transform[1], &maskTopRight); |
| transformPoint(transform[1], &maskBottomLeft); |
| transformPoint(transform[1], &maskBottomRight); |
| } |
| */ |
| vtx_count = VTX_COUNT; |
| BEGIN_ACCEL(1); |
| OUT_ACCEL_REG(R300_VAP_VTX_SIZE, vtx_count); |
| FINISH_ACCEL(); |
| BEGIN_RING(4 * vtx_count + 4); |
| OUT_RING(CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2, |
| 4 * vtx_count)); |
| OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN | |
| RADEON_CP_VC_CNTL_PRIM_WALK_RING | |
| (4 << RADEON_CP_VC_CNTL_NUM_SHIFT)); |
| VTX_OUT((float)dstX, (float)dstY, |
| xFixedToFloat(srcTopLeft.x) / w, // info->texW[0], |
| xFixedToFloat(srcTopLeft.y) / h); // info->texH[0]); |
| VTX_OUT((float)dstX, (float)(dstY + h), |
| xFixedToFloat(srcBottomLeft.x) / w, // info->texW[0], |
| xFixedToFloat(srcBottomLeft.y) / h); // info->texH[0]); |
| VTX_OUT((float)(dstX + w), (float)(dstY + h), |
| xFixedToFloat(srcBottomRight.x) / w, // info->texW[0], |
| xFixedToFloat(srcBottomRight.y) / h); // info->texH[0]); |
| VTX_OUT((float)(dstX + w), (float)dstY, |
| xFixedToFloat(srcTopRight.x) / w, // info->texW[0], |
| xFixedToFloat(srcTopRight.y) / h); // info->texH[0]); |
| /* flushing is pipelined, free/finish is not */ |
| OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D); |
| // OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN); |
| COMMIT_RING(); |
| // LEAVE_DRAW(0); |
| } |
| #undef VTX_OUT |
| #undef VTX_OUT_MASK |
| #if 0 |
| int RadeonComposite( blit_t *blit) |
| { |
| int tileSrcY, tileMaskY, tileDstY; |
| int remainingHeight; |
| R300PrepareComposite(3, blit->src_x, blit->src_y, |
| blit->dst_x, blit->dst_y, |
| blit->w, blit->h); |
| // if (!need_src_tile_x && !need_src_tile_y) { |
| RadeonCompositeTile( blit->src_x, blit->src_y, |
| blit->dst_x, blit->dst_y, |
| blit->w, blit->h); |
| return 0; |
| // } |
| /* Tiling logic borrowed from exaFillRegionTiled */ |
| #if 0 |
| modulus(srcY, src_tile_height, tileSrcY); |
| tileMaskY = maskY; |
| tileDstY = dstY; |
| remainingHeight = height; |
| while (remainingHeight > 0) { |
| int remainingWidth = width; |
| int tileSrcX, tileMaskX, tileDstX; |
| int h = src_tile_height - tileSrcY; |
| if (h > remainingHeight) |
| h = remainingHeight; |
| remainingHeight -= h; |
| modulus(srcX, src_tile_width, tileSrcX); |
| tileMaskX = maskX; |
| tileDstX = dstX; |
| while (remainingWidth > 0) { |
| int w = src_tile_width - tileSrcX; |
| if (w > remainingWidth) |
| w = remainingWidth; |
| remainingWidth -= w; |
| FUNC_NAME(RadeonCompositeTile)(pDst, |
| tileSrcX, tileSrcY, |
| tileMaskX, tileMaskY, |
| tileDstX, tileDstY, |
| w, h); |
| tileSrcX = 0; |
| tileMaskX += w; |
| tileDstX += w; |
| } |
| tileSrcY = 0; |
| tileMaskY += h; |
| tileDstY += h; |
| } |
| #endif |
| } |
| #endif |
| /drivers/old/ati2d/ati2d.c |
|---|
| 0,0 → 1,181 |
| #define R300_PIO 0 |
| #define API_VERSION 0x01000100 |
| #define SRV_GETVERSION 0 |
| #include "types.h" |
| #include <stdio.h> |
| #include <malloc.h> |
| #include <memory.h> |
| #include "pci.h" |
| #include "syscall.h" |
| #include "radeon_reg.h" |
| #include "atihw.h" |
| #include "accel_2d.h" |
| RHD_t rhd __attribute__ ((aligned (128))); /* reduce cache lock */ |
| static clip_t clip; |
| static local_pixmap_t scr_pixmap; |
| int __stdcall srv_2d(ioctl_t *io); |
| u32_t __stdcall drvEntry(int action) |
| { |
| RHDPtr rhdPtr; |
| u32_t retval; |
| int i; |
| if(action != 1) |
| return 0; |
| if(!dbg_open("/bd0/2/ati2d.log")) |
| { |
| printf("Can't open /rd/1/drivers/ati2d.log\nExit\n"); |
| return 0; |
| } |
| if( GetScreenBpp() != 32) |
| { |
| dbgprintf("32 bpp dispaly mode required !\nExit\t"); |
| return 0; |
| } |
| if((rhdPtr=FindPciDevice())==NULL) |
| { |
| dbgprintf("Device not found\n"); |
| return 0; |
| }; |
| dbgprintf("detect %s GART\n", |
| rhd.gart_type == RADEON_IS_PCIE ? "PCIE":"PCI"); |
| for(i=0;i<6;i++) |
| { |
| if(rhd.memBase[i]) |
| dbgprintf("Memory base_%d 0x%x size 0x%x\n", |
| i,rhd.memBase[i],(1<<rhd.memsize[i])); |
| }; |
| for(i=0;i<6;i++) |
| { |
| if(rhd.ioBase[i]) |
| dbgprintf("Io base_%d 0x%x size 0x%x\n", |
| i,rhd.ioBase[i],(1<<rhd.memsize[i])); |
| }; |
| if(!RHDPreInit()) |
| return 0; |
| R5xx2DInit(); |
| Init3DEngine(&rhd); |
| retval = RegService("HDRAW", srv_2d); |
| dbgprintf("reg service %s as: %x\n", "HDRAW", retval); |
| return retval; |
| }; |
| int __stdcall srv_2d(ioctl_t *io) |
| { |
| u32_t *inp; |
| u32_t *outp; |
| inp = io->input; |
| outp = io->output; |
| switch(io->io_code) |
| { |
| case SRV_GETVERSION: |
| if(io->out_size==4) |
| { |
| *outp = API_VERSION; |
| return 0; |
| } |
| break; |
| case PX_CREATE: |
| if(io->inp_size==7) |
| return CreatePixmap((pixmap_t*)inp); |
| break; |
| case PX_DESTROY: |
| if(io->inp_size==7) |
| return DestroyPixmap((pixmap_t*)inp); |
| break; |
| case PX_CLEAR: |
| if(io->inp_size==2) |
| return ClearPixmap((io_clear_t*)inp); |
| break; |
| case PX_DRAW_RECT: |
| if(io->inp_size==7) |
| return DrawRect((io_draw_t*)inp); |
| break; |
| case PX_FILL_RECT: |
| if(io->inp_size==10) |
| return FillRect((io_fill_t*)inp); |
| break; |
| case PX_LINE: |
| if(io->inp_size==6) |
| return Line((io_draw_t*)inp); |
| break; |
| case PX_BLIT: |
| if(io->inp_size==8) |
| return Blit((io_blit_t*)inp); |
| break; |
| case PX_BLIT_TRANSPARENT: |
| if(io->inp_size==9) |
| return BlitTransparent((io_blit_t*)inp); |
| break; |
| case PX_BLIT_ALPHA: |
| if(io->inp_size==9) |
| return RadeonComposite((io_blit_t*)inp); |
| break; |
| default: |
| return ERR_PARAM; |
| }; |
| return ERR_PARAM; |
| } |
| #include "init.c" |
| #include "pci.c" |
| #include "ati_mem.c" |
| #include "r500.inc" |
| #include "clip.inc" |
| #include "pixmap.inc" |
| #include "accel_2d.inc" |
| #include "init_3d.inc" |
| #include "blend.inc" |
| #if !R300_PIO |
| #include "init_cp.c" |
| #endif |
| /drivers/old/ati2d/ati2d.lk |
|---|
| 0,0 → 1,26 |
| IMP |
| _KernelAlloc core.KernelAlloc, |
| _KernelFree core.KernelFree, |
| _UserAlloc core.UserAlloc, |
| _UserFree core.UserFree, |
| _AllocPages core.AllocPages, |
| _CommitPages core.CommitPages, |
| _UnmapPages core.UnmapPages, |
| _MapIoMem core.MapIoMem, |
| _GetPgAddr core.GetPgAddr, |
| _CreateRingBuffer core.CreateRingBuffer, |
| _PciApi core.PciApi, |
| _PciRead8 core.PciRead8, |
| _PciRead16 core.PciRead16, |
| _PciRead32 core.PciRead32, |
| _PciWrite32 core.PciWrite32, |
| _RegService core.RegService, |
| _WaitMutex core.WaitMutex, |
| _Delay core.Delay, |
| _ChangeTask core.ChangeTask, |
| _SysMsgBoardStr core.SysMsgBoardStr |
| FIL ati2d.obj, |
| vsprintf.obj, |
| icompute.obj |
| /drivers/old/ati2d/ati_mem.c |
|---|
| 0,0 → 1,225 |
| /* radeon_mem.c -- Simple GART/fb memory manager for radeon -*- linux-c -*- */ |
| /* |
| * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. |
| * |
| * The Weather Channel (TM) funded Tungsten Graphics to develop the |
| * initial release of the Radeon 8500 driver under the XFree86 license. |
| * This notice must be preserved. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice (including the next |
| * paragraph) shall be included in all copies or substantial portions of the |
| * Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| * DEALINGS IN THE SOFTWARE. |
| * |
| * Authors: |
| * Keith Whitwell <keith@tungstengraphics.com> |
| */ |
| #define USED_BLOCK 1 |
| #define list_for_each(entry, head) \ |
| for (entry = (head)->next; entry != head; entry = (entry)->next) |
| /* Very simple allocator for GART memory, working on a static range |
| * already mapped into each client's address space. |
| */ |
| struct mem_block |
| { |
| struct mem_block *next; |
| struct mem_block *prev; |
| addr_t start; |
| size_t size; |
| }; |
| /* Initialize. How to check for an uninitialized heap? |
| */ |
| static int init_heap(struct mem_block **heap, int start, int size) |
| { |
| struct mem_block *blocks = malloc(sizeof(*blocks)); |
| if (!blocks) |
| return -1; //-ENOMEM; |
| *heap = malloc(sizeof(**heap)); |
| if (!*heap) |
| { |
| free(blocks); |
| return -1; //-ENOMEM; |
| } |
| blocks->start = start; |
| blocks->size = size; |
| blocks->next = blocks->prev = *heap; |
| __clear(*heap,sizeof(**heap)); |
| (*heap)->next = (*heap)->prev = blocks; |
| (*heap)->start |= USED_BLOCK; |
| return 0; |
| } |
| static struct mem_block **get_heap(RHDPtr rhdPtr, int region) |
| { |
| switch (region) |
| { |
| case RHD_MEM_GART: |
| return &rhdPtr->gart_heap; |
| case RHD_MEM_FB: |
| return &rhdPtr->fb_heap; |
| default: |
| return NULL; |
| } |
| } |
| static struct mem_block *split_block(struct mem_block *p, int size) |
| { |
| /* Maybe cut off the end of an existing block */ |
| if (size < p->size) |
| { |
| struct mem_block *newblock = malloc(sizeof(*newblock)); |
| if (!newblock) |
| goto out; |
| newblock->start = p->start + size; |
| newblock->size = p->size - size; |
| newblock->next = p->next; |
| newblock->prev = p; |
| p->next->prev = newblock; |
| p->next = newblock; |
| p->size = size; |
| p->start|=USED_BLOCK; |
| } |
| out: |
| return p; |
| } |
| static struct mem_block *alloc_block(struct mem_block *heap, int size) |
| { |
| struct mem_block *p; |
| list_for_each(p, heap) |
| { |
| if ( !(p->start & USED_BLOCK) && size <= p->size) |
| return split_block(p, size); |
| } |
| return NULL; |
| } |
| static struct mem_block *find_block(struct mem_block *heap, int start) |
| { |
| struct mem_block *p; |
| list_for_each(p, heap) |
| if ((p->start & ~USED_BLOCK) == start) |
| return p; |
| return NULL; |
| } |
| static void free_block(struct mem_block *p) |
| { |
| /* Assumes a single contiguous range. Needs a special file_priv in |
| * 'heap' to stop it being subsumed. |
| */ |
| p->start &= ~USED_BLOCK; |
| if ( !(p->next->start & USED_BLOCK)) |
| { |
| struct mem_block *q = p->next; |
| p->size += q->size; |
| p->next = q->next; |
| p->next->prev = p; |
| free(q); |
| } |
| if ( !(p->prev->start & USED_BLOCK)) |
| { |
| struct mem_block *q = p->prev; |
| q->size += p->size; |
| q->next = p->next; |
| q->next->prev = q; |
| free(p); |
| } |
| } |
| int rhdInitHeap(RHDPtr rhdPtr) |
| { |
| int base = rhdPtr->FbFreeStart; |
| return init_heap(&rhdPtr->fb_heap, base, rhdPtr->FbFreeSize); |
| }; |
| addr_t rhd_mem_alloc(RHDPtr rhdPtr,int region, int size) |
| { |
| struct mem_block *block, **heap; |
| heap = get_heap(rhdPtr, region); |
| if (!heap || !*heap) |
| return 0; |
| /* Make things easier on ourselves: all allocations at least |
| * 4k aligned. |
| */ |
| size = (size+4095) & ~4095; |
| block = alloc_block(*heap, size); |
| if (!block) |
| return 0; |
| return (block->start & ~USED_BLOCK); |
| } |
| int rhd_mem_free(RHDPtr rhdPtr, int region, addr_t offset) |
| { |
| struct mem_block *block, **heap; |
| heap = get_heap(rhdPtr, region); |
| if (!heap || !*heap) |
| return -1; |
| block = find_block(*heap, (int)offset); |
| if (!block) |
| return -1; |
| if ( !(block->start & USED_BLOCK)) |
| return -1; |
| free_block(block); |
| return 0; |
| } |
| void dump_mem() |
| { |
| struct mem_block *p; |
| struct mem_block **heap; |
| heap = &rhd.fb_heap; |
| list_for_each(p, *heap) |
| { |
| dbgprintf("block: %x next: %x prev: %x start: %x size:%x\n", |
| p,p->next,p->prev,p->start,p->size); |
| } |
| } |
| /drivers/old/ati2d/ati_pciids_gen.h |
|---|
| 0,0 → 1,385 |
| #define PCI_CHIP_RV380_3150 0x3150 |
| #define PCI_CHIP_RV380_3151 0x3151 |
| #define PCI_CHIP_RV380_3152 0x3152 |
| #define PCI_CHIP_RV380_3154 0x3154 |
| #define PCI_CHIP_RV380_3E50 0x3E50 |
| #define PCI_CHIP_RV380_3E54 0x3E54 |
| #define PCI_CHIP_RS100_4136 0x4136 |
| #define PCI_CHIP_RS200_4137 0x4137 |
| #define PCI_CHIP_R300_AD 0x4144 |
| #define PCI_CHIP_R300_AE 0x4145 |
| #define PCI_CHIP_R300_AF 0x4146 |
| #define PCI_CHIP_R300_AG 0x4147 |
| #define PCI_CHIP_R350_AH 0x4148 |
| #define PCI_CHIP_R350_AI 0x4149 |
| #define PCI_CHIP_R350_AJ 0x414A |
| #define PCI_CHIP_R350_AK 0x414B |
| #define PCI_CHIP_RV350_AP 0x4150 |
| #define PCI_CHIP_RV350_AQ 0x4151 |
| #define PCI_CHIP_RV360_AR 0x4152 |
| #define PCI_CHIP_RV350_AS 0x4153 |
| #define PCI_CHIP_RV350_AT 0x4154 |
| #define PCI_CHIP_RV350_4155 0x4155 |
| #define PCI_CHIP_RV350_AV 0x4156 |
| #define PCI_CHIP_MACH32 0x4158 |
| #define PCI_CHIP_RS250_4237 0x4237 |
| #define PCI_CHIP_R200_BB 0x4242 |
| #define PCI_CHIP_R200_BC 0x4243 |
| #define PCI_CHIP_RS100_4336 0x4336 |
| #define PCI_CHIP_RS200_4337 0x4337 |
| #define PCI_CHIP_MACH64CT 0x4354 |
| #define PCI_CHIP_MACH64CX 0x4358 |
| #define PCI_CHIP_RS250_4437 0x4437 |
| #define PCI_CHIP_MACH64ET 0x4554 |
| #define PCI_CHIP_MACH64GB 0x4742 |
| #define PCI_CHIP_MACH64GD 0x4744 |
| #define PCI_CHIP_MACH64GI 0x4749 |
| #define PCI_CHIP_MACH64GL 0x474C |
| #define PCI_CHIP_MACH64GM 0x474D |
| #define PCI_CHIP_MACH64GN 0x474E |
| #define PCI_CHIP_MACH64GO 0x474F |
| #define PCI_CHIP_MACH64GP 0x4750 |
| #define PCI_CHIP_MACH64GQ 0x4751 |
| #define PCI_CHIP_MACH64GR 0x4752 |
| #define PCI_CHIP_MACH64GS 0x4753 |
| #define PCI_CHIP_MACH64GT 0x4754 |
| #define PCI_CHIP_MACH64GU 0x4755 |
| #define PCI_CHIP_MACH64GV 0x4756 |
| #define PCI_CHIP_MACH64GW 0x4757 |
| #define PCI_CHIP_MACH64GX 0x4758 |
| #define PCI_CHIP_MACH64GY 0x4759 |
| #define PCI_CHIP_MACH64GZ 0x475A |
| #define PCI_CHIP_RV250_If 0x4966 |
| #define PCI_CHIP_RV250_Ig 0x4967 |
| #define PCI_CHIP_R420_JH 0x4A48 |
| #define PCI_CHIP_R420_JI 0x4A49 |
| #define PCI_CHIP_R420_JJ 0x4A4A |
| #define PCI_CHIP_R420_JK 0x4A4B |
| #define PCI_CHIP_R420_JL 0x4A4C |
| #define PCI_CHIP_R420_JM 0x4A4D |
| #define PCI_CHIP_R420_JN 0x4A4E |
| #define PCI_CHIP_R420_4A4F 0x4A4F |
| #define PCI_CHIP_R420_JP 0x4A50 |
| #define PCI_CHIP_R481_4B49 0x4B49 |
| #define PCI_CHIP_R481_4B4A 0x4B4A |
| #define PCI_CHIP_R481_4B4B 0x4B4B |
| #define PCI_CHIP_R481_4B4C 0x4B4C |
| #define PCI_CHIP_MACH64LB 0x4C42 |
| #define PCI_CHIP_MACH64LD 0x4C44 |
| #define PCI_CHIP_RAGE128LE 0x4C45 |
| #define PCI_CHIP_RAGE128LF 0x4C46 |
| #define PCI_CHIP_MACH64LG 0x4C47 |
| #define PCI_CHIP_MACH64LI 0x4C49 |
| #define PCI_CHIP_MACH64LM 0x4C4D |
| #define PCI_CHIP_MACH64LN 0x4C4E |
| #define PCI_CHIP_MACH64LP 0x4C50 |
| #define PCI_CHIP_MACH64LQ 0x4C51 |
| #define PCI_CHIP_MACH64LR 0x4C52 |
| #define PCI_CHIP_MACH64LS 0x4C53 |
| #define PCI_CHIP_RADEON_LW 0x4C57 |
| #define PCI_CHIP_RADEON_LX 0x4C58 |
| #define PCI_CHIP_RADEON_LY 0x4C59 |
| #define PCI_CHIP_RADEON_LZ 0x4C5A |
| #define PCI_CHIP_RV250_Ld 0x4C64 |
| #define PCI_CHIP_RV250_Lf 0x4C66 |
| #define PCI_CHIP_RV250_Lg 0x4C67 |
| #define PCI_CHIP_RAGE128MF 0x4D46 |
| #define PCI_CHIP_RAGE128ML 0x4D4C |
| #define PCI_CHIP_R300_ND 0x4E44 |
| #define PCI_CHIP_R300_NE 0x4E45 |
| #define PCI_CHIP_R300_NF 0x4E46 |
| #define PCI_CHIP_R300_NG 0x4E47 |
| #define PCI_CHIP_R350_NH 0x4E48 |
| #define PCI_CHIP_R350_NI 0x4E49 |
| #define PCI_CHIP_R360_NJ 0x4E4A |
| #define PCI_CHIP_R350_NK 0x4E4B |
| #define PCI_CHIP_RV350_NP 0x4E50 |
| #define PCI_CHIP_RV350_NQ 0x4E51 |
| #define PCI_CHIP_RV350_NR 0x4E52 |
| #define PCI_CHIP_RV350_NS 0x4E53 |
| #define PCI_CHIP_RV350_NT 0x4E54 |
| #define PCI_CHIP_RV350_NV 0x4E56 |
| #define PCI_CHIP_RAGE128PA 0x5041 |
| #define PCI_CHIP_RAGE128PB 0x5042 |
| #define PCI_CHIP_RAGE128PC 0x5043 |
| #define PCI_CHIP_RAGE128PD 0x5044 |
| #define PCI_CHIP_RAGE128PE 0x5045 |
| #define PCI_CHIP_RAGE128PF 0x5046 |
| #define PCI_CHIP_RAGE128PG 0x5047 |
| #define PCI_CHIP_RAGE128PH 0x5048 |
| #define PCI_CHIP_RAGE128PI 0x5049 |
| #define PCI_CHIP_RAGE128PJ 0x504A |
| #define PCI_CHIP_RAGE128PK 0x504B |
| #define PCI_CHIP_RAGE128PL 0x504C |
| #define PCI_CHIP_RAGE128PM 0x504D |
| #define PCI_CHIP_RAGE128PN 0x504E |
| #define PCI_CHIP_RAGE128PO 0x504F |
| #define PCI_CHIP_RAGE128PP 0x5050 |
| #define PCI_CHIP_RAGE128PQ 0x5051 |
| #define PCI_CHIP_RAGE128PR 0x5052 |
| #define PCI_CHIP_RAGE128PS 0x5053 |
| #define PCI_CHIP_RAGE128PT 0x5054 |
| #define PCI_CHIP_RAGE128PU 0x5055 |
| #define PCI_CHIP_RAGE128PV 0x5056 |
| #define PCI_CHIP_RAGE128PW 0x5057 |
| #define PCI_CHIP_RAGE128PX 0x5058 |
| #define PCI_CHIP_RADEON_QD 0x5144 |
| #define PCI_CHIP_RADEON_QE 0x5145 |
| #define PCI_CHIP_RADEON_QF 0x5146 |
| #define PCI_CHIP_RADEON_QG 0x5147 |
| #define PCI_CHIP_R200_QH 0x5148 |
| #define PCI_CHIP_R200_QL 0x514C |
| #define PCI_CHIP_R200_QM 0x514D |
| #define PCI_CHIP_RV200_QW 0x5157 |
| #define PCI_CHIP_RV200_QX 0x5158 |
| #define PCI_CHIP_RV100_QY 0x5159 |
| #define PCI_CHIP_RV100_QZ 0x515A |
| #define PCI_CHIP_RN50_515E 0x515E |
| #define PCI_CHIP_RAGE128RE 0x5245 |
| #define PCI_CHIP_RAGE128RF 0x5246 |
| #define PCI_CHIP_RAGE128RG 0x5247 |
| #define PCI_CHIP_RAGE128RK 0x524B |
| #define PCI_CHIP_RAGE128RL 0x524C |
| #define PCI_CHIP_RAGE128SE 0x5345 |
| #define PCI_CHIP_RAGE128SF 0x5346 |
| #define PCI_CHIP_RAGE128SG 0x5347 |
| #define PCI_CHIP_RAGE128SH 0x5348 |
| #define PCI_CHIP_RAGE128SK 0x534B |
| #define PCI_CHIP_RAGE128SL 0x534C |
| #define PCI_CHIP_RAGE128SM 0x534D |
| #define PCI_CHIP_RAGE128SN 0x534E |
| #define PCI_CHIP_RAGE128TF 0x5446 |
| #define PCI_CHIP_RAGE128TL 0x544C |
| #define PCI_CHIP_RAGE128TR 0x5452 |
| #define PCI_CHIP_RAGE128TS 0x5453 |
| #define PCI_CHIP_RAGE128TT 0x5454 |
| #define PCI_CHIP_RAGE128TU 0x5455 |
| #define PCI_CHIP_RV370_5460 0x5460 |
| #define PCI_CHIP_RV370_5462 0x5462 |
| #define PCI_CHIP_RV370_5464 0x5464 |
| #define PCI_CHIP_R423_UH 0x5548 |
| #define PCI_CHIP_R423_UI 0x5549 |
| #define PCI_CHIP_R423_UJ 0x554A |
| #define PCI_CHIP_R423_UK 0x554B |
| #define PCI_CHIP_R430_554C 0x554C |
| #define PCI_CHIP_R430_554D 0x554D |
| #define PCI_CHIP_R430_554E 0x554E |
| #define PCI_CHIP_R430_554F 0x554F |
| #define PCI_CHIP_R423_5550 0x5550 |
| #define PCI_CHIP_R423_UQ 0x5551 |
| #define PCI_CHIP_R423_UR 0x5552 |
| #define PCI_CHIP_R423_UT 0x5554 |
| #define PCI_CHIP_RV410_564A 0x564A |
| #define PCI_CHIP_RV410_564B 0x564B |
| #define PCI_CHIP_RV410_564F 0x564F |
| #define PCI_CHIP_RV410_5652 0x5652 |
| #define PCI_CHIP_RV410_5653 0x5653 |
| #define PCI_CHIP_RV410_5657 0x5657 |
| #define PCI_CHIP_MACH64VT 0x5654 |
| #define PCI_CHIP_MACH64VU 0x5655 |
| #define PCI_CHIP_MACH64VV 0x5656 |
| #define PCI_CHIP_RS300_5834 0x5834 |
| #define PCI_CHIP_RS300_5835 0x5835 |
| #define PCI_CHIP_RS480_5954 0x5954 |
| #define PCI_CHIP_RS480_5955 0x5955 |
| #define PCI_CHIP_RV280_5960 0x5960 |
| #define PCI_CHIP_RV280_5961 0x5961 |
| #define PCI_CHIP_RV280_5962 0x5962 |
| #define PCI_CHIP_RV280_5964 0x5964 |
| #define PCI_CHIP_RV280_5965 0x5965 |
| #define PCI_CHIP_RN50_5969 0x5969 |
| #define PCI_CHIP_RS482_5974 0x5974 |
| #define PCI_CHIP_RS485_5975 0x5975 |
| #define PCI_CHIP_RS400_5A41 0x5A41 |
| #define PCI_CHIP_RS400_5A42 0x5A42 |
| #define PCI_CHIP_RC410_5A61 0x5A61 |
| #define PCI_CHIP_RC410_5A62 0x5A62 |
| #define PCI_CHIP_RV370_5B60 0x5B60 |
| #define PCI_CHIP_RV370_5B62 0x5B62 |
| #define PCI_CHIP_RV370_5B63 0x5B63 |
| #define PCI_CHIP_RV370_5B64 0x5B64 |
| #define PCI_CHIP_RV370_5B65 0x5B65 |
| #define PCI_CHIP_RV280_5C61 0x5C61 |
| #define PCI_CHIP_RV280_5C63 0x5C63 |
| #define PCI_CHIP_R430_5D48 0x5D48 |
| #define PCI_CHIP_R430_5D49 0x5D49 |
| #define PCI_CHIP_R430_5D4A 0x5D4A |
| #define PCI_CHIP_R480_5D4C 0x5D4C |
| #define PCI_CHIP_R480_5D4D 0x5D4D |
| #define PCI_CHIP_R480_5D4E 0x5D4E |
| #define PCI_CHIP_R480_5D4F 0x5D4F |
| #define PCI_CHIP_R480_5D50 0x5D50 |
| #define PCI_CHIP_R480_5D52 0x5D52 |
| #define PCI_CHIP_R423_5D57 0x5D57 |
| #define PCI_CHIP_RV410_5E48 0x5E48 |
| #define PCI_CHIP_RV410_5E4A 0x5E4A |
| #define PCI_CHIP_RV410_5E4B 0x5E4B |
| #define PCI_CHIP_RV410_5E4C 0x5E4C |
| #define PCI_CHIP_RV410_5E4D 0x5E4D |
| #define PCI_CHIP_RV410_5E4F 0x5E4F |
| #define PCI_CHIP_R520_7100 0x7100 |
| #define PCI_CHIP_R520_7101 0x7101 |
| #define PCI_CHIP_R520_7102 0x7102 |
| #define PCI_CHIP_R520_7103 0x7103 |
| #define PCI_CHIP_R520_7104 0x7104 |
| #define PCI_CHIP_R520_7105 0x7105 |
| #define PCI_CHIP_R520_7106 0x7106 |
| #define PCI_CHIP_R520_7108 0x7108 |
| #define PCI_CHIP_R520_7109 0x7109 |
| #define PCI_CHIP_R520_710A 0x710A |
| #define PCI_CHIP_R520_710B 0x710B |
| #define PCI_CHIP_R520_710C 0x710C |
| #define PCI_CHIP_R520_710E 0x710E |
| #define PCI_CHIP_R520_710F 0x710F |
| #define PCI_CHIP_RV515_7140 0x7140 |
| #define PCI_CHIP_RV515_7141 0x7141 |
| #define PCI_CHIP_RV515_7142 0x7142 |
| #define PCI_CHIP_RV515_7143 0x7143 |
| #define PCI_CHIP_RV515_7144 0x7144 |
| #define PCI_CHIP_RV515_7145 0x7145 |
| #define PCI_CHIP_RV515_7146 0x7146 |
| #define PCI_CHIP_RV515_7147 0x7147 |
| #define PCI_CHIP_RV515_7149 0x7149 |
| #define PCI_CHIP_RV515_714A 0x714A |
| #define PCI_CHIP_RV515_714B 0x714B |
| #define PCI_CHIP_RV515_714C 0x714C |
| #define PCI_CHIP_RV515_714D 0x714D |
| #define PCI_CHIP_RV515_714E 0x714E |
| #define PCI_CHIP_RV515_714F 0x714F |
| #define PCI_CHIP_RV515_7151 0x7151 |
| #define PCI_CHIP_RV515_7152 0x7152 |
| #define PCI_CHIP_RV515_7153 0x7153 |
| #define PCI_CHIP_RV515_715E 0x715E |
| #define PCI_CHIP_RV515_715F 0x715F |
| #define PCI_CHIP_RV515_7180 0x7180 |
| #define PCI_CHIP_RV515_7181 0x7181 |
| #define PCI_CHIP_RV515_7183 0x7183 |
| #define PCI_CHIP_RV515_7186 0x7186 |
| #define PCI_CHIP_RV515_7187 0x7187 |
| #define PCI_CHIP_RV515_7188 0x7188 |
| #define PCI_CHIP_RV515_718A 0x718A |
| #define PCI_CHIP_RV515_718B 0x718B |
| #define PCI_CHIP_RV515_718C 0x718C |
| #define PCI_CHIP_RV515_718D 0x718D |
| #define PCI_CHIP_RV515_718F 0x718F |
| #define PCI_CHIP_RV515_7193 0x7193 |
| #define PCI_CHIP_RV515_7196 0x7196 |
| #define PCI_CHIP_RV515_719B 0x719B |
| #define PCI_CHIP_RV515_719F 0x719F |
| #define PCI_CHIP_RV530_71C0 0x71C0 |
| #define PCI_CHIP_RV530_71C1 0x71C1 |
| #define PCI_CHIP_RV530_71C2 0x71C2 |
| #define PCI_CHIP_RV530_71C3 0x71C3 |
| #define PCI_CHIP_RV530_71C4 0x71C4 |
| #define PCI_CHIP_RV530_71C5 0x71C5 |
| #define PCI_CHIP_RV530_71C6 0x71C6 |
| #define PCI_CHIP_RV530_71C7 0x71C7 |
| #define PCI_CHIP_RV530_71CD 0x71CD |
| #define PCI_CHIP_RV530_71CE 0x71CE |
| #define PCI_CHIP_RV530_71D2 0x71D2 |
| #define PCI_CHIP_RV530_71D4 0x71D4 |
| #define PCI_CHIP_RV530_71D5 0x71D5 |
| #define PCI_CHIP_RV530_71D6 0x71D6 |
| #define PCI_CHIP_RV530_71DA 0x71DA |
| #define PCI_CHIP_RV530_71DE 0x71DE |
| #define PCI_CHIP_RV515_7200 0x7200 |
| #define PCI_CHIP_RV515_7210 0x7210 |
| #define PCI_CHIP_RV515_7211 0x7211 |
| #define PCI_CHIP_R580_7240 0x7240 |
| #define PCI_CHIP_R580_7243 0x7243 |
| #define PCI_CHIP_R580_7244 0x7244 |
| #define PCI_CHIP_R580_7245 0x7245 |
| #define PCI_CHIP_R580_7246 0x7246 |
| #define PCI_CHIP_R580_7247 0x7247 |
| #define PCI_CHIP_R580_7248 0x7248 |
| #define PCI_CHIP_R580_7249 0x7249 |
| #define PCI_CHIP_R580_724A 0x724A |
| #define PCI_CHIP_R580_724B 0x724B |
| #define PCI_CHIP_R580_724C 0x724C |
| #define PCI_CHIP_R580_724D 0x724D |
| #define PCI_CHIP_R580_724E 0x724E |
| #define PCI_CHIP_R580_724F 0x724F |
| #define PCI_CHIP_RV570_7280 0x7280 |
| #define PCI_CHIP_RV560_7281 0x7281 |
| #define PCI_CHIP_RV560_7283 0x7283 |
| #define PCI_CHIP_R580_7284 0x7284 |
| #define PCI_CHIP_RV560_7287 0x7287 |
| #define PCI_CHIP_RV570_7288 0x7288 |
| #define PCI_CHIP_RV570_7289 0x7289 |
| #define PCI_CHIP_RV570_728B 0x728B |
| #define PCI_CHIP_RV570_728C 0x728C |
| #define PCI_CHIP_RV560_7290 0x7290 |
| #define PCI_CHIP_RV560_7291 0x7291 |
| #define PCI_CHIP_RV560_7293 0x7293 |
| #define PCI_CHIP_RV560_7297 0x7297 |
| #define PCI_CHIP_RS350_7834 0x7834 |
| #define PCI_CHIP_RS350_7835 0x7835 |
| #define PCI_CHIP_RS690_791E 0x791E |
| #define PCI_CHIP_RS690_791F 0x791F |
| #define PCI_CHIP_RS600_793F 0x793F |
| #define PCI_CHIP_RS600_7941 0x7941 |
| #define PCI_CHIP_RS600_7942 0x7942 |
| #define PCI_CHIP_RS740_796C 0x796C |
| #define PCI_CHIP_RS740_796D 0x796D |
| #define PCI_CHIP_RS740_796E 0x796E |
| #define PCI_CHIP_RS740_796F 0x796F |
| #define PCI_CHIP_R600_9400 0x9400 |
| #define PCI_CHIP_R600_9401 0x9401 |
| #define PCI_CHIP_R600_9402 0x9402 |
| #define PCI_CHIP_R600_9403 0x9403 |
| #define PCI_CHIP_R600_9405 0x9405 |
| #define PCI_CHIP_R600_940A 0x940A |
| #define PCI_CHIP_R600_940B 0x940B |
| #define PCI_CHIP_R600_940F 0x940F |
| #define PCI_CHIP_RV770_9440 0x9440 |
| #define PCI_CHIP_RV770_9441 0x9441 |
| #define PCI_CHIP_RV770_9442 0x9442 |
| #define PCI_CHIP_RV610_94C0 0x94C0 |
| #define PCI_CHIP_RV610_94C1 0x94C1 |
| #define PCI_CHIP_RV610_94C3 0x94C3 |
| #define PCI_CHIP_RV610_94C4 0x94C4 |
| #define PCI_CHIP_RV610_94C5 0x94C5 |
| #define PCI_CHIP_RV610_94C6 0x94C6 |
| #define PCI_CHIP_RV610_94C7 0x94C7 |
| #define PCI_CHIP_RV610_94C8 0x94C8 |
| #define PCI_CHIP_RV610_94C9 0x94C9 |
| #define PCI_CHIP_RV610_94CB 0x94CB |
| #define PCI_CHIP_RV610_94CC 0x94CC |
| #define PCI_CHIP_RV670_9500 0x9500 |
| #define PCI_CHIP_RV670_9501 0x9501 |
| #define PCI_CHIP_RV670_9505 0x9505 |
| #define PCI_CHIP_RV670_9507 0x9507 |
| #define PCI_CHIP_RV670_950F 0x950F |
| #define PCI_CHIP_RV670_9511 0x9511 |
| #define PCI_CHIP_RV670_9515 0x9515 |
| #define PCI_CHIP_RV630_9580 0x9580 |
| #define PCI_CHIP_RV630_9581 0x9581 |
| #define PCI_CHIP_RV630_9583 0x9583 |
| #define PCI_CHIP_RV630_9586 0x9586 |
| #define PCI_CHIP_RV630_9587 0x9587 |
| #define PCI_CHIP_RV630_9588 0x9588 |
| #define PCI_CHIP_RV630_9589 0x9589 |
| #define PCI_CHIP_RV630_958A 0x958A |
| #define PCI_CHIP_RV630_958B 0x958B |
| #define PCI_CHIP_RV630_958C 0x958C |
| #define PCI_CHIP_RV630_958D 0x958D |
| #define PCI_CHIP_RV630_958E 0x958E |
| #define PCI_CHIP_RV620_95C0 0x95C0 |
| #define PCI_CHIP_RV620_95C5 0x95C5 |
| #define PCI_CHIP_RV620_95C7 0x95C7 |
| #define PCI_CHIP_RV620_95C2 0x95C2 |
| #define PCI_CHIP_RV620_95C4 0x95C4 |
| #define PCI_CHIP_RV620_95CD 0x95CD |
| #define PCI_CHIP_RV620_95CE 0x95CE |
| #define PCI_CHIP_RV620_95CF 0x95CF |
| #define PCI_CHIP_RV635_9590 0x9590 |
| #define PCI_CHIP_RV635_9596 0x9596 |
| #define PCI_CHIP_RV635_9597 0x9597 |
| #define PCI_CHIP_RV635_9598 0x9598 |
| #define PCI_CHIP_RV635_9599 0x9599 |
| #define PCI_CHIP_RV635_9591 0x9591 |
| #define PCI_CHIP_RV635_9593 0x9593 |
| #define PCI_CHIP_RS780_9610 0x9610 |
| #define PCI_CHIP_RS780_9611 0x9611 |
| #define PCI_CHIP_RS780_9612 0x9612 |
| #define PCI_CHIP_RS780_9613 0x9613 |
| /drivers/old/ati2d/atihw.h |
|---|
| 0,0 → 1,569 |
| typedef void *pointer; |
| typedef unsigned int memType; |
| typedef struct { float hi, lo; } range; |
| typedef enum |
| { |
| CHIP_FAMILY_UNKNOW, |
| CHIP_FAMILY_LEGACY, |
| CHIP_FAMILY_RADEON, |
| CHIP_FAMILY_RV100, |
| CHIP_FAMILY_RS100, /* U1 (IGP320M) or A3 (IGP320)*/ |
| CHIP_FAMILY_RV200, |
| CHIP_FAMILY_RS200, /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350), RS250 (IGP 7000) */ |
| CHIP_FAMILY_R200, |
| CHIP_FAMILY_RV250, |
| CHIP_FAMILY_RS300, /* RS300/RS350 */ |
| CHIP_FAMILY_RV280, |
| CHIP_FAMILY_R300, |
| CHIP_FAMILY_R350, |
| CHIP_FAMILY_RV350, |
| CHIP_FAMILY_RV380, /* RV370/RV380/M22/M24 */ |
| CHIP_FAMILY_R420, /* R420/R423/M18 */ |
| CHIP_FAMILY_RV410, /* RV410, M26 */ |
| CHIP_FAMILY_RS400, /* xpress 200, 200m (RS400) Intel */ |
| CHIP_FAMILY_RS480, /* xpress 200, 200m (RS410/480/482/485) AMD */ |
| CHIP_FAMILY_RV515, /* rv515 */ |
| CHIP_FAMILY_R520, /* r520 */ |
| CHIP_FAMILY_RV530, /* rv530 */ |
| CHIP_FAMILY_R580, /* r580 */ |
| CHIP_FAMILY_RV560, /* rv560 */ |
| CHIP_FAMILY_RV570, /* rv570 */ |
| CHIP_FAMILY_RS600, |
| CHIP_FAMILY_RS690, |
| CHIP_FAMILY_RS740, |
| CHIP_FAMILY_R600, /* r600 */ |
| CHIP_FAMILY_R630, |
| CHIP_FAMILY_RV610, |
| CHIP_FAMILY_RV630, |
| CHIP_FAMILY_RV670, |
| CHIP_FAMILY_RV620, |
| CHIP_FAMILY_RV635, |
| CHIP_FAMILY_RS780, |
| CHIP_FAMILY_RV770, |
| CHIP_FAMILY_LAST |
| } RADEONChipFamily; |
| #define IS_RV100_VARIANT ((rhdPtr->ChipFamily == CHIP_FAMILY_RV100) || \ |
| (rhdPtr->ChipFamily == CHIP_FAMILY_RV200) || \ |
| (rhdPtr->ChipFamily == CHIP_FAMILY_RS100) || \ |
| (rhdPtr->ChipFamily == CHIP_FAMILY_RS200) || \ |
| (rhdPtr->ChipFamily == CHIP_FAMILY_RV250) || \ |
| (rhdPtr->ChipFamily == CHIP_FAMILY_RV280) || \ |
| (rhdPtr->ChipFamily == CHIP_FAMILY_RS300)) |
| #define IS_R300_VARIANT ((info->ChipFamily == CHIP_FAMILY_R300) || \ |
| (info->ChipFamily == CHIP_FAMILY_RV350) || \ |
| (info->ChipFamily == CHIP_FAMILY_R350) || \ |
| (info->ChipFamily == CHIP_FAMILY_RV380) || \ |
| (info->ChipFamily == CHIP_FAMILY_R420) || \ |
| (info->ChipFamily == CHIP_FAMILY_RV410) || \ |
| (info->ChipFamily == CHIP_FAMILY_RS400) || \ |
| (info->ChipFamily == CHIP_FAMILY_RS480)) |
| #define IS_AVIVO_VARIANT ((info->ChipFamily >= CHIP_FAMILY_RV515)) |
| #define IS_DCE3_VARIANT ((info->ChipFamily >= CHIP_FAMILY_RV620)) |
| #define IS_R500_3D ((info->ChipFamily == CHIP_FAMILY_RV515) || \ |
| (info->ChipFamily == CHIP_FAMILY_R520) || \ |
| (info->ChipFamily == CHIP_FAMILY_RV530) || \ |
| (info->ChipFamily == CHIP_FAMILY_R580) || \ |
| (info->ChipFamily == CHIP_FAMILY_RV560) || \ |
| (info->ChipFamily == CHIP_FAMILY_RV570)) |
| #define IS_R300_3D ((info->ChipFamily == CHIP_FAMILY_R300) || \ |
| (info->ChipFamily == CHIP_FAMILY_RV350) || \ |
| (info->ChipFamily == CHIP_FAMILY_R350) || \ |
| (info->ChipFamily == CHIP_FAMILY_RV380) || \ |
| (info->ChipFamily == CHIP_FAMILY_R420) || \ |
| (info->ChipFamily == CHIP_FAMILY_RV410) || \ |
| (info->ChipFamily == CHIP_FAMILY_RS690) || \ |
| (info->ChipFamily == CHIP_FAMILY_RS600) || \ |
| (info->ChipFamily == CHIP_FAMILY_RS740) || \ |
| (info->ChipFamily == CHIP_FAMILY_RS400) || \ |
| (info->ChipFamily == CHIP_FAMILY_RS480)) |
| typedef enum { |
| CARD_PCI, |
| CARD_AGP, |
| CARD_PCIE |
| } RADEONCardType; |
| enum radeon_chip_flags { |
| RADEON_FAMILY_MASK = 0x0000ffffUL, |
| RADEON_FLAGS_MASK = 0xffff0000UL, |
| RADEON_IS_MOBILITY = 0x00010000UL, |
| RADEON_IS_IGP = 0x00020000UL, |
| RADEON_SINGLE_CRTC = 0x00040000UL, |
| RADEON_IS_AGP = 0x00080000UL, |
| RADEON_HAS_HIERZ = 0x00100000UL, |
| RADEON_IS_PCIE = 0x00200000UL, |
| RADEON_NEW_MEMMAP = 0x00400000UL, |
| RADEON_IS_PCI = 0x00800000UL, |
| RADEON_IS_IGPGART = 0x01000000UL, |
| }; |
| /* |
| * Errata workarounds |
| */ |
| typedef enum { |
| CHIP_ERRATA_R300_CG = 0x00000001, |
| CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, |
| CHIP_ERRATA_PLL_DELAY = 0x00000004 |
| } RADEONErrata; |
| typedef struct |
| { |
| u32_t pci_device_id; |
| RADEONChipFamily chip_family; |
| int mobility; |
| int igp; |
| int nocrtc2; |
| int nointtvout; |
| int singledac; |
| } RADEONCardInfo; |
| #define RHD_FB_BAR 0 |
| #define RHD_MMIO_BAR 2 |
| #define RHD_MEM_GART 1 |
| #define RHD_MEM_FB 2 |
| #define RADEON_DEFAULT_GART_SIZE 8 /* MB (must be 2^n and > 4MB) */ |
| #define R300_DEFAULT_GART_SIZE 32 /* MB (for R300 and above) */ |
| #define RADEON_DEFAULT_RING_SIZE 1 /* MB (must be page aligned) */ |
| #define RADEON_DEFAULT_BUFFER_SIZE 2 /* MB (must be page aligned) */ |
| #define RADEON_DEFAULT_GART_TEX_SIZE 1 /* MB (must be page aligned) */ |
| #define RADEON_DEFAULT_CP_TIMEOUT 100000 /* usecs */ |
| #define RADEON_DEFAULT_PCI_APER_SIZE 32 /* in MB */ |
| #define RADEON_PCIGART_TABLE_SIZE (32*1024) |
| #define RADEON_IDLE_RETRY 16 /* Fall out of idle loops after this count */ |
| #define RADEON_TIMEOUT 4000000 /* Fall out of wait loops after this count */ |
| typedef struct RHDRec |
| { |
| addr_t MMIOBase; |
| size_t MMIOMapSize; |
| u32_t lock; |
| addr_t FbFreeStart; |
| addr_t FbFreeSize; |
| /* visible part of the framebuffer */ |
| // unsigned int FbScanoutStart; |
| // unsigned int FbScanoutSize; |
| // u32_t LinearAddr; /* Frame buffer physical address */ |
| addr_t fbLocation; /* Frame buffer physical address */ |
| u32_t mc_fb_location; |
| u32_t mc_agp_location; |
| u32_t mc_agp_location_hi; |
| size_t videoRam; |
| u32_t MemCntl; |
| u32_t BusCntl; |
| unsigned long FbMapSize; /* Size of frame buffer, in bytes */ |
| unsigned long FbSecureSize; /* Size of secured fb area at end of |
| framebuffer */ |
| RADEONChipFamily ChipFamily; |
| RADEONErrata ChipErrata; |
| char *chipset; |
| Bool IsIGP; |
| Bool IsMobility; |
| Bool HasCRTC2; |
| u32_t bus; |
| u32_t devfn; |
| PCITAG PciTag; |
| u16_t PciDeviceID; |
| u16_t subvendor_id; |
| u16_t subdevice_id; |
| RADEONCardType cardType; /* Current card is a PCI card */ |
| u32_t memBase[6]; |
| u32_t ioBase[6]; |
| u32_t memtype[6]; |
| u32_t memsize[6]; |
| struct mem_block *fb_heap; |
| struct mem_block *gart_heap; |
| u32_t displayWidth; |
| u32_t displayHeight; |
| u32_t gart_type; |
| u32_t *gart_table; |
| addr_t gart_table_dma; |
| addr_t gart_vm_start; |
| size_t gart_size; |
| u32_t* ringBase; |
| u32_t ring_rp; |
| u32_t ring_wp; |
| u32_t ringSize; |
| u32_t ring_avail; |
| u32_t bufSize; |
| u32_t pciAperSize; |
| u32_t CPusecTimeout; |
| int __xmin; |
| int __ymin; |
| int __xmax; |
| int __ymax; |
| u32_t gui_control; |
| u32_t dst_pitch_offset; |
| u32_t surface_cntl; |
| volatile u32_t host_rp __attribute__ ((aligned (128))); |
| volatile u32_t scratch0 __attribute__ ((aligned (128))); |
| volatile u32_t scratch1; |
| volatile u32_t scratch2; |
| volatile u32_t scratch3; |
| volatile u32_t scratch4; |
| volatile u32_t scratch5; |
| volatile u32_t scratch6; |
| volatile u32_t scratch7; |
| int RamWidth __attribute__ ((aligned (128))); |
| Bool IsDDR; |
| int num_gb_pipes; |
| int has_tcl; |
| }RHD_t, *RHDPtr; |
| extern RHD_t rhd; |
| #define RADEON_CP_PACKET0 0x00000000 |
| #define RADEON_CP_PACKET1 0x40000000 |
| #define RADEON_CP_PACKET2 0x80000000 |
| #define RADEON_CP_PACKET3 0xC0000000 |
| # define RADEON_CNTL_PAINT 0x00009100 |
| # define RADEON_CNTL_BITBLT 0x00009200 |
| # define RADEON_CNTL_TRANBLT 0x00009C00 |
| # define RADEON_CNTL_PAINT_POLYLINE 0x00009500 |
| # define RADEON_CNTL_PAINT_MULTI 0x00009A00 |
| #if R300_PIO |
| #define BEGIN_ACCEL(n) FIFOWait(n) |
| #define FINISH_ACCEL() |
| #define COMMIT_RING() |
| #define OUT_ACCEL_REG(reg, val) OUTREG(reg, val) |
| #else |
| #define CP_PACKET0(reg, n) \ |
| (RADEON_CP_PACKET0 | ((n - 1 ) << 16) | ((reg) >> 2)) |
| #define CP_PACKET1(reg0, reg1) \ |
| (RADEON_CP_PACKET1 | (((reg1) >> 2) << 11) | ((reg0) >> 2)) |
| #define CP_PACKET2() \ |
| (RADEON_CP_PACKET2) |
| #define CP_PACKET3( pkt, n ) \ |
| (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) |
| #define BEGIN_RING( req ) do { \ |
| int avail = rhd.ring_rp-rhd.ring_wp; \ |
| if (avail <=0 ) avail+= 0x4000; \ |
| if( (req)+128 > avail) \ |
| { \ |
| rhd.ring_rp = INREG(RADEON_CP_RB_RPTR); \ |
| avail = rhd.ring_rp-rhd.ring_wp; \ |
| if (avail <= 0) avail+= 0x4000; \ |
| if( (req)+128 > avail){ \ |
| unlock_device(); \ |
| return 0; \ |
| }; \ |
| } \ |
| ring = &rhd.ringBase[rhd.ring_wp]; \ |
| }while(0) |
| #define ADVANCE_RING() |
| #define OUT_RING( x ) *ring++ = (x) |
| #define CP_REG(reg, val) \ |
| do { \ |
| ring[0] = CP_PACKET0((reg), 1); \ |
| ring[1] = (val); \ |
| ring+= 2; \ |
| } while (0) |
| #define DRM_MEMORYBARRIER() __asm__ volatile("lock; addl $0,0(%%esp)" : : : "memory"); |
| #define COMMIT_RING() do { \ |
| rhd.ring_wp = (ring - rhd.ringBase) & 0x3FFF; \ |
| /* Flush writes to ring */ \ |
| DRM_MEMORYBARRIER(); \ |
| /*GET_RING_HEAD( dev_priv ); */ \ |
| OUTREG( RADEON_CP_RB_WPTR, rhd.ring_wp); \ |
| /* read from PCI bus to ensure correct posting */ \ |
| /* INREG( RADEON_CP_RB_RPTR ); */ \ |
| } while (0) |
| #define BEGIN_ACCEL(n) BEGIN_RING(2*(n)) |
| #define FINISH_ACCEL() COMMIT_RING() |
| #define OUT_ACCEL_REG(reg, val) CP_REG((reg), (val)) |
| #endif |
| typedef struct { |
| int token; /* id of the token */ |
| const char * name; /* token name */ |
| } SymTabRec, *SymTabPtr; |
| extern inline void lock_device() |
| { |
| __asm__ __volatile__ ( |
| "call *__imp__WaitMutex" |
| ::"b" (&rhd.lock)); |
| }; |
| extern inline void unlock_device() |
| { |
| rhd.lock = 0; |
| } |
| extern inline void |
| OUTREG8(u16_t offset, u8_t value) |
| { |
| *(volatile u8_t *)((u8_t *)(rhd.MMIOBase + offset)) = value; |
| } |
| extern inline u32_t INREG(u16_t offset) |
| { |
| return *(volatile u32_t *)((u8_t*)(rhd.MMIOBase + offset)); |
| } |
| extern inline void OUTREG(u16_t offset, u32_t value) |
| { |
| *(volatile u32_t *)((u8_t *)(rhd.MMIOBase + offset)) = value; |
| } |
| //#define OUTREG( offset, value) \ |
| // *(volatile u32_t *)((u8_t *)(rhd.MMIOBase + (u32_t)(offset))) = (u32_t)value |
| extern inline u32_t _RHDRegRead(RHDPtr rhdPtr, u16_t offset) |
| { |
| return *(volatile u32_t *)((u8_t*)(rhdPtr->MMIOBase + offset)); |
| } |
| extern inline void |
| MASKREG(u16_t offset, u32_t value, u32_t mask) |
| { |
| u32_t tmp; |
| tmp = INREG(offset); |
| tmp &= ~mask; |
| tmp |= (value & mask); |
| OUTREG(offset, tmp); |
| }; |
| #define INPLL( addr) RADEONINPLL( addr) |
| #define OUTPLL( addr, val) RADEONOUTPLL( addr, val) |
| extern inline void |
| _RHDRegWrite(RHDPtr rhdPtr, u16_t offset, u32_t value) |
| { |
| *(volatile u32_t *)((u8_t *)(rhdPtr->MMIOBase + offset)) = value; |
| } |
| extern inline void |
| _RHDRegMask(RHDPtr rhdPtr, u16_t offset, u32_t value, u32_t mask) |
| { |
| u32_t tmp; |
| tmp = _RHDRegRead(rhdPtr, offset); |
| tmp &= ~mask; |
| tmp |= (value & mask); |
| _RHDRegWrite(rhdPtr, offset, tmp); |
| }; |
| #define RHDRegRead(ptr, offset) _RHDRegRead((ptr)->rhdPtr, (offset)) |
| #define RHDRegWrite(ptr, offset, value) _RHDRegWrite((ptr)->rhdPtr, (offset), (value)) |
| #define RHDRegMask(ptr, offset, value, mask) _RHDRegMask((ptr)->rhdPtr, (offset), (value), (mask)) |
| #define RHDFUNC(ptr) |
| #define DBG(x) x |
| // #define DBG(x) |
| #pragma pack (push,1) |
| typedef struct s_cursor |
| { |
| u32_t magic; // 'CURS' |
| void (*destroy)(struct s_cursor*); // destructor |
| u32_t fd; // next object in list |
| u32_t bk; // prev object in list |
| u32_t pid; // owner id |
| void *base; // allocated memory |
| u32_t hot_x; // hotspot coords |
| u32_t hot_y; |
| }cursor_t; |
| #pragma pack (pop) |
| #define LOAD_FROM_FILE 0 |
| #define LOAD_FROM_MEM 1 |
| #define LOAD_INDIRECT 2 |
| cursor_t *create_cursor(u32_t pid, void *src, u32_t flags); |
| void __stdcall copy_cursor(void *img, void *src); |
| void destroy_cursor(cursor_t *cursor); |
| void __destroy_cursor(cursor_t *cursor); // wrap |
| void __stdcall r500_SelectCursor(cursor_t *cursor); |
| void __stdcall r500_SetCursor(cursor_t *cursor, int x, int y); |
| void __stdcall r500_CursorRestore(int x, int y); |
| typedef struct { |
| u32_t x ; |
| u32_t y ; |
| } xPointFixed; |
| typedef u32_t xFixed_16_16; |
| typedef xFixed_16_16 xFixed; |
| #define XFIXED_BITS 16 |
| #define xFixedToInt(f) (int) ((f) >> XFIXED_BITS) |
| #define IntToxFixed(i) ((xFixed) (i) << XFIXED_BITS) |
| #define xFixedToFloat(f) (((float) (f)) / 65536) |
| #define PICT_FORMAT(bpp,type,a,r,g,b) (((bpp) << 24) | \ |
| ((type) << 16) | \ |
| ((a) << 12) | \ |
| ((r) << 8) | \ |
| ((g) << 4) | \ |
| ((b))) |
| #define PICT_FORMAT_A(f) (((f) >> 12) & 0x0f) |
| #define PICT_FORMAT_RGB(f) (((f) ) & 0xfff) |
| #define PICT_TYPE_OTHER 0 |
| #define PICT_TYPE_A 1 |
| #define PICT_TYPE_ARGB 2 |
| #define PICT_TYPE_ABGR 3 |
| #define PICT_TYPE_COLOR 4 |
| #define PICT_TYPE_GRAY 5 |
| typedef enum _PictFormatShort { |
| PICT_a8r8g8b8 = PICT_FORMAT(32,PICT_TYPE_ARGB,8,8,8,8), |
| PICT_x8r8g8b8 = PICT_FORMAT(32,PICT_TYPE_ARGB,0,8,8,8), |
| PICT_a8b8g8r8 = PICT_FORMAT(32,PICT_TYPE_ABGR,8,8,8,8), |
| PICT_x8b8g8r8 = PICT_FORMAT(32,PICT_TYPE_ABGR,0,8,8,8), |
| /* 24bpp formats */ |
| PICT_r8g8b8 = PICT_FORMAT(24,PICT_TYPE_ARGB,0,8,8,8), |
| PICT_b8g8r8 = PICT_FORMAT(24,PICT_TYPE_ABGR,0,8,8,8), |
| /* 16bpp formats */ |
| PICT_r5g6b5 = PICT_FORMAT(16,PICT_TYPE_ARGB,0,5,6,5), |
| PICT_b5g6r5 = PICT_FORMAT(16,PICT_TYPE_ABGR,0,5,6,5), |
| PICT_a1r5g5b5 = PICT_FORMAT(16,PICT_TYPE_ARGB,1,5,5,5), |
| PICT_x1r5g5b5 = PICT_FORMAT(16,PICT_TYPE_ARGB,0,5,5,5), |
| PICT_a1b5g5r5 = PICT_FORMAT(16,PICT_TYPE_ABGR,1,5,5,5), |
| PICT_x1b5g5r5 = PICT_FORMAT(16,PICT_TYPE_ABGR,0,5,5,5), |
| PICT_a4r4g4b4 = PICT_FORMAT(16,PICT_TYPE_ARGB,4,4,4,4), |
| PICT_x4r4g4b4 = PICT_FORMAT(16,PICT_TYPE_ARGB,0,4,4,4), |
| PICT_a4b4g4r4 = PICT_FORMAT(16,PICT_TYPE_ABGR,4,4,4,4), |
| PICT_x4b4g4r4 = PICT_FORMAT(16,PICT_TYPE_ABGR,0,4,4,4), |
| /* 8bpp formats */ |
| PICT_a8 = PICT_FORMAT(8,PICT_TYPE_A,8,0,0,0), |
| PICT_r3g3b2 = PICT_FORMAT(8,PICT_TYPE_ARGB,0,3,3,2), |
| PICT_b2g3r3 = PICT_FORMAT(8,PICT_TYPE_ABGR,0,3,3,2), |
| PICT_a2r2g2b2 = PICT_FORMAT(8,PICT_TYPE_ARGB,2,2,2,2), |
| PICT_a2b2g2r2 = PICT_FORMAT(8,PICT_TYPE_ABGR,2,2,2,2), |
| PICT_c8 = PICT_FORMAT(8,PICT_TYPE_COLOR,0,0,0,0), |
| PICT_g8 = PICT_FORMAT(8,PICT_TYPE_GRAY,0,0,0,0), |
| PICT_x4a4 = PICT_FORMAT(8,PICT_TYPE_A,4,0,0,0), |
| PICT_x4c4 = PICT_FORMAT(8,PICT_TYPE_COLOR,0,0,0,0), |
| PICT_x4g4 = PICT_FORMAT(8,PICT_TYPE_GRAY,0,0,0,0), |
| /* 4bpp formats */ |
| PICT_a4 = PICT_FORMAT(4,PICT_TYPE_A,4,0,0,0), |
| PICT_r1g2b1 = PICT_FORMAT(4,PICT_TYPE_ARGB,0,1,2,1), |
| PICT_b1g2r1 = PICT_FORMAT(4,PICT_TYPE_ABGR,0,1,2,1), |
| PICT_a1r1g1b1 = PICT_FORMAT(4,PICT_TYPE_ARGB,1,1,1,1), |
| PICT_a1b1g1r1 = PICT_FORMAT(4,PICT_TYPE_ABGR,1,1,1,1), |
| PICT_c4 = PICT_FORMAT(4,PICT_TYPE_COLOR,0,0,0,0), |
| PICT_g4 = PICT_FORMAT(4,PICT_TYPE_GRAY,0,0,0,0), |
| /* 1bpp formats */ |
| PICT_a1 = PICT_FORMAT(1,PICT_TYPE_A,1,0,0,0), |
| PICT_g1 = PICT_FORMAT(1,PICT_TYPE_GRAY,0,0,0,0), |
| } PictFormatShort; |
| void dump_mem(); |
| RHDPtr FindPciDevice(); |
| static __inline__ int drm_device_is_pcie(PCITAG pciTag); |
| static void init_pipes(RHDPtr info); |
| Bool init_cp(RHDPtr info); |
| Bool RHDPreInit(); |
| void R5xx2DInit(); |
| int Init3DEngine(RHDPtr info); |
| void init_gart(RHDPtr info); |
| int rhdInitHeap(RHDPtr rhdPtr); |
| /drivers/old/ati2d/blend.inc |
|---|
| 0,0 → 1,677 |
| struct blendinfo { |
| Bool dst_alpha; |
| Bool src_alpha; |
| u32_t blend_cntl; |
| }; |
| static struct blendinfo RadeonBlendOp[] = { |
| /* 0 - Clear */ |
| {0, 0, RADEON_SRC_BLEND_GL_ZERO | RADEON_DST_BLEND_GL_ZERO}, |
| /* 1 - Src */ |
| {0, 0, RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO}, |
| /* 2 - Dst */ |
| {0, 0, RADEON_SRC_BLEND_GL_ZERO | RADEON_DST_BLEND_GL_ONE}, |
| /* 3 - Over */ |
| {0, 1, RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA}, |
| /* 4 - OverReverse */ |
| {1, 0, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | RADEON_DST_BLEND_GL_ONE}, |
| /* 5 - In */ |
| {1, 0, RADEON_SRC_BLEND_GL_DST_ALPHA | RADEON_DST_BLEND_GL_ZERO}, |
| /* 6 - InReverse */ |
| {0, 1, RADEON_SRC_BLEND_GL_ZERO | RADEON_DST_BLEND_GL_SRC_ALPHA}, |
| /* 7 - Out */ |
| {1, 0, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | RADEON_DST_BLEND_GL_ZERO}, |
| /* 8 - OutReverse */ |
| {0, 1, RADEON_SRC_BLEND_GL_ZERO | RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA}, |
| /* 9 - Atop */ |
| {1, 1, RADEON_SRC_BLEND_GL_DST_ALPHA | RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA}, |
| /* 10- AtopReverse */ |
| {1, 1, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | RADEON_DST_BLEND_GL_SRC_ALPHA}, |
| /* 11 - Xor */ |
| {1, 1, RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA | RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA}, |
| /* 12 - Add */ |
| {0, 0, RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ONE}, |
| }; |
| static Bool R300TextureSetup(RHDPtr info,local_pixmap_t *srcpix, int w, int h, int unit) |
| { |
| u32_t txfilter, txformat0, txformat1, txoffset, txpitch; |
| int i, pixel_shift; |
| txpitch = srcpix->pitch; |
| txoffset = (u32_t)srcpix->local; |
| if ((txoffset & 0x1f) != 0) |
| dbgprintf("Bad texture offset 0x%x\n", (int)txoffset); |
| if ((txpitch & 0x1f) != 0) |
| dbgprintf("Bad texture pitch 0x%x\n", (int)txpitch); |
| /* TXPITCH = pixels (texels) per line - 1 */ |
| pixel_shift = 32 >> 4; |
| txpitch >>= pixel_shift; |
| txpitch -= 1; |
| txformat1 = R300_TX_FORMAT_A8R8G8B8; |
| txformat0 = ((((w - 1) & 0x7ff) << R300_TXWIDTH_SHIFT) | |
| (((h - 1) & 0x7ff) << R300_TXHEIGHT_SHIFT)); |
| if (IS_R500_3D && ((w - 1) & 0x800)) |
| txpitch |= R500_TXWIDTH_11; |
| if (IS_R500_3D && ((h - 1) & 0x800)) |
| txpitch |= R500_TXHEIGHT_11; |
| /* Use TXPITCH instead of TXWIDTH for address computations: we could |
| * omit this if there is no padding, but there is no apparent advantage |
| * in doing so. |
| */ |
| txformat0 |= R300_TXPITCH_EN; |
| txfilter = R300_TX_CLAMP_S(R300_TX_CLAMP_CLAMP_GL); |
| txfilter |= R300_TX_CLAMP_T(R300_TX_CLAMP_CLAMP_GL); |
| txfilter |= (unit << R300_TX_ID_SHIFT); |
| txfilter |= (R300_TX_MAG_FILTER_NEAREST | R300_TX_MIN_FILTER_NEAREST); |
| { |
| u32_t *ring; |
| BEGIN_ACCEL(7); |
| OUT_ACCEL_REG(R300_TX_FILTER0_0 + (unit * 4), txfilter); |
| OUT_ACCEL_REG(R300_TX_FILTER1_0 + (unit * 4), 0); |
| OUT_ACCEL_REG(R300_TX_FORMAT0_0 + (unit * 4), txformat0); |
| OUT_ACCEL_REG(R300_TX_FORMAT1_0 + (unit * 4), txformat1); |
| OUT_ACCEL_REG(R300_TX_FORMAT2_0 + (unit * 4), txpitch); |
| OUT_ACCEL_REG(R300_TX_OFFSET_0 + (unit * 4), txoffset); |
| // if (!pPict->repeat) |
| OUT_ACCEL_REG(R300_TX_BORDER_COLOR_0 + (unit * 4), 0); |
| COMMIT_RING(); |
| } |
| return TRUE; |
| } |
| static u32_t RADEONGetBlendCntl(int op, u32_t dst_format) |
| { |
| u32_t sblend, dblend; |
| return RADEON_SRC_BLEND_GL_SRC_ALPHA | RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA; |
| } |
| Bool R300PrepareComposite(local_pixmap_t *dstpix, int dstX, int dstY, |
| local_pixmap_t *srcpix, int srcX, int srcY, |
| int w, int h, int op) |
| { |
| u32_t dst_format, dst_offset, dst_pitch; |
| u32_t txenable, colorpitch; |
| u32_t blendcntl; |
| int pixel_shift; |
| u32_t *ring; |
| RHDPtr info = &rhd; |
| dst_format = R300_COLORFORMAT_ARGB8888; |
| dst_offset = (u32_t)dstpix->local; |
| dst_pitch = dstpix->pitch; |
| pixel_shift = 32 >> 4; |
| colorpitch = dst_pitch >> pixel_shift; |
| colorpitch |= dst_format; |
| if ((dst_offset & 0x0f) != 0) |
| dbgprintf("Bad destination offset 0x%x\n", (int)dst_offset); |
| if (((dst_pitch >> pixel_shift) & 0x7) != 0) |
| dbgprintf("Bad destination pitch 0x%x\n", (int)dst_pitch); |
| if (!R300TextureSetup(&rhd, srcpix, w, h, 0)) |
| return FALSE; |
| txenable = R300_TEX_0_ENABLE; |
| // RADEON_SWITCH_TO_3D(); |
| /* setup the VAP */ |
| BEGIN_ACCEL(7); |
| /* These registers define the number, type, and location of data submitted |
| * to the PVS unit of GA input (when PVS is disabled) |
| * DST_VEC_LOC is the slot in the PVS input vector memory when PVS/TCL is |
| * enabled. This memory provides the imputs to the vertex shader program |
| * and ordering is not important. When PVS/TCL is disabled, this field maps |
| * directly to the GA input memory and the order is signifigant. In |
| * PVS_BYPASS mode the order is as follows: |
| * 0 Position |
| * 1 Point Size |
| * 2 Color 0 |
| * 3 Color 1 |
| * 4 Color 2 |
| * 5 Color 3 |
| * 6 Textures 0 |
| * 7 Textures 1 |
| * 8 Textures 2 |
| * 9 Textures 3 - 7 |
| * 14 Fog |
| */ |
| OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_0, |
| ((R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_0_SHIFT) | |
| (0 << R300_SKIP_DWORDS_0_SHIFT) | |
| (0 << R300_DST_VEC_LOC_0_SHIFT) | |
| R300_SIGNED_0 | |
| (R300_DATA_TYPE_FLOAT_2 << R300_DATA_TYPE_1_SHIFT) | |
| (0 << R300_SKIP_DWORDS_1_SHIFT) | |
| (6 << R300_DST_VEC_LOC_1_SHIFT) | |
| R300_LAST_VEC_1 | |
| R300_SIGNED_1)); |
| /* load the vertex shader |
| * We pre-load vertex programs in RADEONInit3DEngine(): |
| * - exa no mask |
| * - exa mask |
| * - Xv |
| * Here we select the offset of the vertex program we want to use |
| */ |
| if (info->has_tcl) { |
| OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_0, |
| ((3 << R300_PVS_FIRST_INST_SHIFT) | |
| (4 << R300_PVS_XYZW_VALID_INST_SHIFT) | |
| (4 << R300_PVS_LAST_INST_SHIFT))); |
| OUT_ACCEL_REG(R300_VAP_PVS_CODE_CNTL_1, |
| (4 << R300_PVS_LAST_VTX_SRC_INST_SHIFT)); |
| } |
| /* Position and one or two sets of 2 texture coordinates */ |
| OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_0, R300_VTX_POS_PRESENT); //VTX_COLOR_0_PRESENT |
| OUT_ACCEL_REG(R300_VAP_OUT_VTX_FMT_1, (2 << R300_TEX_0_COMP_CNT_SHIFT)); |
| OUT_ACCEL_REG(R300_TX_INVALTAGS, 0x0); |
| OUT_ACCEL_REG(R300_TX_ENABLE, txenable); |
| FINISH_ACCEL(); |
| /* setup pixel shader */ |
| /* setup pixel shader */ |
| if (IS_R300_3D) |
| { |
| u32_t output_fmt; |
| int src_color, src_alpha; |
| int mask_color, mask_alpha; |
| src_color = R300_ALU_RGB_SRC0_RGB; |
| src_alpha = R300_ALU_ALPHA_SRC0_A; |
| mask_color = R300_ALU_RGB_1_0; |
| mask_alpha = R300_ALU_ALPHA_1_0; |
| /* shader output swizzling */ |
| output_fmt = (R300_OUT_FMT_C4_8 | |
| R300_OUT_FMT_C0_SEL_BLUE | |
| R300_OUT_FMT_C1_SEL_GREEN | |
| R300_OUT_FMT_C2_SEL_RED | |
| R300_OUT_FMT_C3_SEL_ALPHA); |
| /* setup the rasterizer, load FS */ |
| BEGIN_ACCEL(10); |
| /* 2 components: 2 for tex0 */ |
| OUT_ACCEL_REG(R300_RS_COUNT, |
| ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) | |
| R300_RS_COUNT_HIRES_EN)); |
| OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0) | R300_TX_OFFSET_RS(6)); |
| OUT_ACCEL_REG(R300_US_CODE_OFFSET, (R300_ALU_CODE_OFFSET(0) | |
| R300_ALU_CODE_SIZE(0) | |
| R300_TEX_CODE_OFFSET(0) | |
| R300_TEX_CODE_SIZE(0))); |
| OUT_ACCEL_REG(R300_US_CODE_ADDR_3, |
| (R300_ALU_START(0) | |
| R300_ALU_SIZE(0) | |
| R300_TEX_START(0) | |
| R300_TEX_SIZE(0) | |
| R300_RGBA_OUT)); |
| // OUT_ACCEL_REG(R300_US_PIXSIZE, 1); /* highest temp used */ |
| /* shader output swizzling */ |
| OUT_ACCEL_REG(R300_US_OUT_FMT_0, output_fmt); |
| /* tex inst for src texture is pre-loaded in RADEONInit3DEngine() */ |
| /* tex inst for mask texture is pre-loaded in RADEONInit3DEngine() */ |
| /* RGB inst |
| * temp addresses for texture inputs |
| * ALU_RGB_ADDR0 is src tex (temp 0) |
| * ALU_RGB_ADDR1 is mask tex (temp 1) |
| * R300_ALU_RGB_OMASK - output components to write |
| * R300_ALU_RGB_TARGET_A - render target |
| */ |
| OUT_ACCEL_REG(R300_US_ALU_RGB_ADDR(0), |
| (R300_ALU_RGB_ADDR0(0) | |
| R300_ALU_RGB_ADDR1(1) | |
| R300_ALU_RGB_ADDR2(0) | |
| R300_ALU_RGB_ADDRD(0) | |
| R300_ALU_RGB_OMASK((R300_ALU_RGB_MASK_R | |
| R300_ALU_RGB_MASK_G | |
| R300_ALU_RGB_MASK_B)) | |
| R300_ALU_RGB_TARGET_A)); |
| /* RGB inst |
| * ALU operation |
| */ |
| OUT_ACCEL_REG(R300_US_ALU_RGB_INST(0), |
| (R300_ALU_RGB_SEL_A(src_color) | |
| R300_ALU_RGB_MOD_A(R300_ALU_RGB_MOD_NOP) | |
| R300_ALU_RGB_SEL_B(mask_color) | |
| R300_ALU_RGB_MOD_B(R300_ALU_RGB_MOD_NOP) | |
| R300_ALU_RGB_SEL_C(R300_ALU_RGB_0_0) | |
| R300_ALU_RGB_MOD_C(R300_ALU_RGB_MOD_NOP) | |
| R300_ALU_RGB_OP(R300_ALU_RGB_OP_MAD) | |
| R300_ALU_RGB_OMOD(R300_ALU_RGB_OMOD_NONE) | |
| R300_ALU_RGB_CLAMP)); |
| /* Alpha inst |
| * temp addresses for texture inputs |
| * ALU_ALPHA_ADDR0 is src tex (0) |
| * ALU_ALPHA_ADDR1 is mask tex (1) |
| * R300_ALU_ALPHA_OMASK - output components to write |
| * R300_ALU_ALPHA_TARGET_A - render target |
| */ |
| OUT_ACCEL_REG(R300_US_ALU_ALPHA_ADDR(0), |
| (R300_ALU_ALPHA_ADDR0(0) | |
| R300_ALU_ALPHA_ADDR1(1) | |
| R300_ALU_ALPHA_ADDR2(0) | |
| R300_ALU_ALPHA_ADDRD(0) | |
| R300_ALU_ALPHA_OMASK(R300_ALU_ALPHA_MASK_A) | |
| R300_ALU_ALPHA_TARGET_A | |
| R300_ALU_ALPHA_OMASK_W(R300_ALU_ALPHA_MASK_NONE))); |
| /* Alpha inst |
| * ALU operation |
| */ |
| OUT_ACCEL_REG(R300_US_ALU_ALPHA_INST(0), |
| (R300_ALU_ALPHA_SEL_A(src_alpha) | |
| R300_ALU_ALPHA_MOD_A(R300_ALU_ALPHA_MOD_NOP) | |
| R300_ALU_ALPHA_SEL_B(mask_alpha) | |
| R300_ALU_ALPHA_MOD_B(R300_ALU_ALPHA_MOD_NOP) | |
| R300_ALU_ALPHA_SEL_C(R300_ALU_ALPHA_0_0) | |
| R300_ALU_ALPHA_MOD_C(R300_ALU_ALPHA_MOD_NOP) | |
| R300_ALU_ALPHA_OP(R300_ALU_ALPHA_OP_MAD) | |
| R300_ALU_ALPHA_OMOD(R300_ALU_ALPHA_OMOD_NONE) | |
| R300_ALU_ALPHA_CLAMP)); |
| FINISH_ACCEL(); |
| } |
| else |
| { |
| u32_t output_fmt; |
| u32_t src_color, src_alpha; |
| u32_t mask_color, mask_alpha; |
| src_color = (R500_ALU_RGB_R_SWIZ_A_R | |
| R500_ALU_RGB_G_SWIZ_A_G | |
| R500_ALU_RGB_B_SWIZ_A_B); |
| src_alpha = R500_ALPHA_SWIZ_A_A; |
| mask_color = (R500_ALU_RGB_R_SWIZ_B_1 | |
| R500_ALU_RGB_G_SWIZ_B_1 | |
| R500_ALU_RGB_B_SWIZ_B_1); |
| mask_alpha = R500_ALPHA_SWIZ_B_1; |
| /* shader output swizzling */ |
| output_fmt = (R300_OUT_FMT_C4_8 | |
| R300_OUT_FMT_C0_SEL_BLUE | |
| R300_OUT_FMT_C1_SEL_GREEN | |
| R300_OUT_FMT_C2_SEL_RED | |
| R300_OUT_FMT_C3_SEL_ALPHA); |
| BEGIN_ACCEL(6); |
| OUT_ACCEL_REG(R300_RS_COUNT, |
| ((2 << R300_RS_COUNT_IT_COUNT_SHIFT) | |
| R300_RS_COUNT_HIRES_EN)); |
| OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0) | R300_TX_OFFSET_RS(6)); |
| OUT_ACCEL_REG(R500_US_CODE_ADDR, (R500_US_CODE_START_ADDR(0) | |
| R500_US_CODE_END_ADDR(1))); |
| OUT_ACCEL_REG(R500_US_CODE_RANGE, (R500_US_CODE_RANGE_ADDR(0) | |
| R500_US_CODE_RANGE_SIZE(1))); |
| OUT_ACCEL_REG(R500_US_CODE_OFFSET, 0); |
| OUT_ACCEL_REG(R300_US_OUT_FMT_0, output_fmt); |
| COMMIT_RING(); |
| BEGIN_ACCEL(13); |
| OUT_ACCEL_REG(R500_GA_US_VECTOR_INDEX, 0); |
| /* tex inst for src texture */ |
| OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_TEX | |
| R500_INST_TEX_SEM_WAIT | |
| R500_INST_RGB_WMASK_R | |
| R500_INST_RGB_WMASK_G | |
| R500_INST_RGB_WMASK_B | |
| R500_INST_ALPHA_WMASK | |
| R500_INST_RGB_CLAMP | |
| R500_INST_ALPHA_CLAMP)); |
| OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_ID(0) | |
| R500_TEX_INST_LD | |
| R500_TEX_SEM_ACQUIRE | |
| R500_TEX_IGNORE_UNCOVERED)); |
| OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_TEX_SRC_ADDR(0) | |
| R500_TEX_SRC_S_SWIZ_R | |
| R500_TEX_SRC_T_SWIZ_G | |
| R500_TEX_DST_ADDR(0) | |
| R500_TEX_DST_R_SWIZ_R | |
| R500_TEX_DST_G_SWIZ_G | |
| R500_TEX_DST_B_SWIZ_B | |
| R500_TEX_DST_A_SWIZ_A)); |
| OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_DX_ADDR(0) | |
| R500_DX_S_SWIZ_R | |
| R500_DX_T_SWIZ_R | |
| R500_DX_R_SWIZ_R | |
| R500_DX_Q_SWIZ_R | |
| R500_DY_ADDR(0) | |
| R500_DY_S_SWIZ_R | |
| R500_DY_T_SWIZ_R | |
| R500_DY_R_SWIZ_R | |
| R500_DY_Q_SWIZ_R)); |
| OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); |
| OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, 0x00000000); |
| /* ALU inst */ |
| /* *_OMASK* - output component write mask */ |
| OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_INST_TYPE_OUT | |
| R500_INST_TEX_SEM_WAIT | |
| R500_INST_LAST | |
| R500_INST_RGB_OMASK_R | |
| R500_INST_RGB_OMASK_G | |
| R500_INST_RGB_OMASK_B | |
| R500_INST_ALPHA_OMASK | |
| R500_INST_RGB_CLAMP | |
| R500_INST_ALPHA_CLAMP)); |
| /* ALU inst |
| * temp addresses for texture inputs |
| * RGB_ADDR0 is src tex (temp 0) |
| * RGB_ADDR1 is mask tex (temp 1) |
| */ |
| OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_RGB_ADDR0(0) | |
| R500_RGB_ADDR1(1) | |
| R500_RGB_ADDR2(0))); |
| /* ALU inst |
| * temp addresses for texture inputs |
| * ALPHA_ADDR0 is src tex (temp 0) |
| * ALPHA_ADDR1 is mask tex (temp 1) |
| */ |
| OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_ADDR0(0) | |
| R500_ALPHA_ADDR1(1) | |
| R500_ALPHA_ADDR2(0))); |
| /* R500_ALU_RGB_TARGET - RGB render target */ |
| OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGB_SEL_A_SRC0 | |
| src_color | |
| R500_ALU_RGB_SEL_B_SRC1 | |
| mask_color | |
| R500_ALU_RGB_TARGET(0))); |
| /* R500_ALPHA_RGB_TARGET - alpha render target */ |
| OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALPHA_OP_MAD | |
| R500_ALPHA_ADDRD(0) | |
| R500_ALPHA_SEL_A_SRC0 | |
| src_alpha | |
| R500_ALPHA_SEL_B_SRC1 | |
| mask_alpha | |
| R500_ALPHA_TARGET(0))); |
| OUT_ACCEL_REG(R500_GA_US_VECTOR_DATA, (R500_ALU_RGBA_OP_MAD | |
| R500_ALU_RGBA_ADDRD(0) | |
| R500_ALU_RGBA_R_SWIZ_0 | |
| R500_ALU_RGBA_G_SWIZ_0 | |
| R500_ALU_RGBA_B_SWIZ_0 | |
| R500_ALU_RGBA_A_SWIZ_0)); |
| FINISH_ACCEL(); |
| } |
| BEGIN_ACCEL(3); |
| OUT_ACCEL_REG(R300_RB3D_COLOROFFSET0, dst_offset); |
| OUT_ACCEL_REG(R300_RB3D_COLORPITCH0, colorpitch); |
| blendcntl = RADEONGetBlendCntl(op, PICT_a8r8g8b8); |
| OUT_ACCEL_REG(R300_RB3D_BLENDCNTL, blendcntl | R300_ALPHA_BLEND_ENABLE | |
| R300_READ_ENABLE); |
| FINISH_ACCEL(); |
| return TRUE; |
| } |
| #define VTX_COUNT 4 |
| static __inline__ u32_t F_TO_DW(float val) |
| { |
| union { |
| float f; |
| u32_t l; |
| }tmp; |
| tmp.f = val; |
| return tmp.l; |
| } |
| #if R300_PIO |
| #define OUT_ACCEL_REG_F(reg, val) OUTREG(reg, F_TO_DW(val)) |
| #define VTX_OUT(_dstX, _dstY, _srcX, _srcY) \ |
| do { \ |
| OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _dstX); \ |
| OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _dstY); \ |
| OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _srcX); \ |
| OUT_ACCEL_REG_F(RADEON_SE_PORT_DATA0, _srcY); \ |
| } while (0) |
| #else |
| #define OUT_RING_F(x) OUT_RING(F_TO_DW(x)) |
| #define VTX_OUT(_dstX, _dstY, _srcX, _srcY) \ |
| do { \ |
| OUT_RING_F(_dstX); \ |
| OUT_RING_F(_dstY); \ |
| OUT_RING_F(_srcX); \ |
| OUT_RING_F(_srcY); \ |
| } while (0) |
| #endif |
| static int R300CompositeTile(int srcX, int srcY, |
| int dstX, int dstY, |
| int w, int h) |
| { |
| int vtx_count; |
| xPointFixed srcTopLeft, srcTopRight, srcBottomLeft, srcBottomRight; |
| xPointFixed maskTopLeft, maskTopRight, maskBottomLeft, maskBottomRight; |
| RHDPtr info = &rhd; |
| u32_t *ring; |
| srcTopLeft.x = IntToxFixed(srcX); |
| srcTopLeft.y = IntToxFixed(srcY); |
| srcTopRight.x = IntToxFixed(srcX + w); |
| srcTopRight.y = IntToxFixed(srcY); |
| srcBottomLeft.x = IntToxFixed(srcX); |
| srcBottomLeft.y = IntToxFixed(srcY + h); |
| srcBottomRight.x = IntToxFixed(srcX + w); |
| srcBottomRight.y = IntToxFixed(srcY + h); |
| vtx_count = VTX_COUNT; |
| #if R300_PIO |
| BEGIN_ACCEL(6 + vtx_count * 4); |
| OUT_ACCEL_REG(R300_VAP_VTX_SIZE, vtx_count); |
| OUT_ACCEL_REG(RADEON_SE_VF_CNTL, |
| (RADEON_VF_PRIM_TYPE_QUAD_LIST | |
| RADEON_VF_PRIM_WALK_DATA | |
| (4 << RADEON_VF_NUM_VERTICES_SHIFT))); |
| #else |
| BEGIN_ACCEL(7 + 4 * vtx_count); |
| OUT_ACCEL_REG(R300_VAP_VTX_SIZE, vtx_count); |
| OUT_RING(CP_PACKET3(R200_CP_PACKET3_3D_DRAW_IMMD_2, |
| 4 * vtx_count)); |
| OUT_RING(RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN | |
| RADEON_CP_VC_CNTL_PRIM_WALK_RING | |
| (4 << RADEON_CP_VC_CNTL_NUM_SHIFT)); |
| #endif |
| VTX_OUT((float)dstX, (float)dstY, |
| xFixedToFloat(srcTopLeft.x) / w, // info->texW[0], |
| xFixedToFloat(srcTopLeft.y) / h); // info->texH[0]); |
| VTX_OUT((float)dstX, (float)(dstY + h), |
| xFixedToFloat(srcBottomLeft.x) / w, // info->texW[0], |
| xFixedToFloat(srcBottomLeft.y) / h); // info->texH[0]); |
| VTX_OUT((float)(dstX + w), (float)(dstY + h), |
| xFixedToFloat(srcBottomRight.x) / w, // info->texW[0], |
| xFixedToFloat(srcBottomRight.y) / h); // info->texH[0]); |
| VTX_OUT((float)(dstX + w), (float)dstY, |
| xFixedToFloat(srcTopRight.x) / w, // info->texW[0], |
| xFixedToFloat(srcTopRight.y) / h); // info->texH[0]); |
| /* flushing is pipelined, free/finish is not */ |
| OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D); |
| OUT_ACCEL_REG(R300_SC_CLIP_RULE, 0xAAAA); |
| OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_RB3D_DC_FLUSH_ALL); |
| OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_3D_IDLECLEAN); |
| COMMIT_RING(); |
| } |
| #undef VTX_OUT |
| #undef VTX_OUT_MASK |
| int RadeonComposite( io_blit_t *blit) |
| { |
| int tileSrcY, tileMaskY, tileDstY; |
| int remainingHeight; |
| local_pixmap_t *srcpixmap; |
| local_pixmap_t *dstpixmap; |
| dbgprintf("Blit Alpha src: %x dst: %x\n",blit->srcpix, blit->dstpix); |
| dstpixmap = (blit->dstpix == (void*)-1) ? &scr_pixmap : blit->dstpix ; |
| srcpixmap = (blit->srcpix == (void*)-1) ? &scr_pixmap : blit->srcpix ; |
| lock_device(); |
| { |
| u32_t *ring; |
| #if R300_PIO |
| FIFOWait(10); |
| OUTREG(R5XX_DP_GUI_MASTER_CNTL, |
| RADEON_GMC_DST_PITCH_OFFSET_CNTL | |
| RADEON_GMC_BRUSH_SOLID_COLOR | |
| RADEON_GMC_DST_32BPP | |
| RADEON_GMC_SRC_DATATYPE_COLOR | |
| R5XX_GMC_CLR_CMP_CNTL_DIS | |
| R5XX_ROP3_P |
| ); |
| OUTREG(R5XX_DST_PITCH_OFFSET, srcpixmap->pitch_offset); |
| OUTREG(R5XX_DP_BRUSH_FRGD_CLR, blit->alpha<<24); |
| OUTREG(R5XX_DP_WRITE_MASK, 0xFF000000); |
| OUTREG(R5XX_DP_CNTL, R5XX_DST_X_LEFT_TO_RIGHT | R5XX_DST_Y_TOP_TO_BOTTOM); |
| OUTREG(R5XX_DST_Y_X, 0); |
| OUTREG(R5XX_DST_WIDTH_HEIGHT,(srcpixmap->width<<16)|srcpixmap->height); |
| OUTREG( RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN |
| | RADEON_WAIT_HOST_IDLECLEAN ); |
| OUTREG(R5XX_DP_WRITE_MASK, 0xFFFFFFFF); |
| OUTREG(RADEON_WAIT_UNTIL, RADEON_WAIT_HOST_IDLECLEAN | |
| RADEON_WAIT_2D_IDLECLEAN); |
| #else |
| BEGIN_RING(2 + 6); |
| CP_REG(R5XX_DP_WRITE_MASK, 0xFF000000); |
| OUT_RING(CP_PACKET3(RADEON_CNTL_PAINT_MULTI, 4)); |
| OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL | |
| RADEON_GMC_BRUSH_SOLID_COLOR | |
| RADEON_GMC_DST_32BPP | |
| RADEON_GMC_SRC_DATATYPE_COLOR | |
| R5XX_GMC_CLR_CMP_CNTL_DIS | |
| R5XX_ROP3_P |
| ); |
| OUT_RING(srcpixmap->pitch_offset); |
| OUT_RING(blit->alpha<<24); |
| OUT_RING( 0 ); |
| OUT_RING((srcpixmap->width<<16)|srcpixmap->height); |
| COMMIT_RING(); |
| #endif |
| RHDPtr info = &rhd; |
| FIFOWait(64); |
| delay(2); |
| if( IS_R300_3D || IS_R500_3D ) |
| { |
| R300PrepareComposite(dstpixmap, blit->dst_x, blit->dst_y, |
| srcpixmap, blit->src_x, blit->src_y, |
| blit->w, blit->h, 3); |
| R300CompositeTile( blit->src_x, blit->src_y, |
| blit->dst_x, blit->dst_y, |
| blit->w, blit->h); |
| } |
| else if ((info->ChipFamily == CHIP_FAMILY_RV250) || |
| (info->ChipFamily == CHIP_FAMILY_RV280) || |
| (info->ChipFamily == CHIP_FAMILY_RS300) || |
| (info->ChipFamily == CHIP_FAMILY_R200)) |
| { |
| }; |
| }; |
| FIFOWait(64); |
| delay(2); |
| unlock_device(); |
| return 0; |
| }; |
| /drivers/old/ati2d/clip.inc |
|---|
| 0,0 → 1,181 |
| #define CLIP_TOP 1 |
| #define CLIP_BOTTOM 2 |
| #define CLIP_RIGHT 4 |
| #define CLIP_LEFT 8 |
| static int _L1OutCode( clip_t *clip, int x, int y ) |
| /*================================= |
| Verify that a point is inside or outside the active viewport. */ |
| { |
| int flag; |
| flag = 0; |
| if( x < clip->xmin ) { |
| flag |= CLIP_LEFT; |
| } else if( x > clip->xmax ) { |
| flag |= CLIP_RIGHT; |
| } |
| if( y < clip->ymin ) { |
| flag |= CLIP_TOP; |
| } else if( y > clip->ymax ) { |
| flag |= CLIP_BOTTOM; |
| } |
| return( flag ); |
| } |
| static void line_inter( int * x1, int* y1, int x2, int y2, int x ) |
| /*=========================================================================== |
| Find the intersection of a line with a boundary of the viewport. |
| (x1, y1) is outside and ( x2, y2 ) is inside the viewport. |
| NOTE : the signs of denom and ( x - *x1 ) cancel out during division |
| so make both of them positive before rounding. */ |
| { |
| int numer; |
| int denom; |
| denom = abs( x2 - *x1 ); |
| numer = 2L * (long)( y2 - *y1 ) * abs( x - *x1 ); |
| if( numer > 0 ) { |
| numer += denom; /* round to closest pixel */ |
| } else { |
| numer -= denom; |
| } |
| *y1 += numer / ( denom << 1 ); |
| *x1 = x; |
| } |
| int LineClip( clip_t *clip, int *x1, int *y1, int *x2, int *y2 ) |
| /*============================================================= |
| Clips the line with end points (x1,y1) and (x2,y2) to the active |
| viewport using the Cohen-Sutherland clipping algorithm. Return the |
| clipped coordinates and a decision drawing flag. */ |
| { |
| int flag1; |
| int flag2; |
| flag1 = _L1OutCode( clip, *x1, *y1 ); |
| flag2 = _L1OutCode( clip, *x2, *y2 ); |
| for( ;; ) { |
| if( flag1 & flag2 ) break; /* trivially outside */ |
| if( flag1 == flag2 ) break; /* completely inside */ |
| if( flag1 == 0 ) { /* first point inside */ |
| if( flag2 & CLIP_TOP ) { |
| line_inter( y2, x2, *y1, *x1, clip->ymin ); |
| } else if( flag2 & CLIP_BOTTOM ) { |
| line_inter( y2, x2, *y1, *x1, clip->ymax ); |
| } else if( flag2 & CLIP_RIGHT ) { |
| line_inter( x2, y2, *x1, *y1, clip->xmax ); |
| } else if( flag2 & CLIP_LEFT ) { |
| line_inter( x2, y2, *x1, *y1, clip->xmin ); |
| } |
| flag2 = _L1OutCode( clip, *x2, *y2 ); |
| } else { /* second point inside */ |
| if( flag1 & CLIP_TOP ) { |
| line_inter( y1, x1, *y2, *x2, clip->ymin ); |
| } else if( flag1 & CLIP_BOTTOM ) { |
| line_inter( y1, x1, *y2, *x2, clip->ymax ); |
| } else if( flag1 & CLIP_RIGHT ) { |
| line_inter( x1, y1, *x2, *y2, clip->xmax ); |
| } else if( flag1 & CLIP_LEFT ) { |
| line_inter( x1, y1, *x2, *y2, clip->xmin ); |
| } |
| flag1 = _L1OutCode( clip, *x1, *y1 ); |
| } |
| } |
| return( flag1 & flag2 ); |
| } |
| static void block_inter( clip_t *clip, int *x, int *y, int flag ) |
| /*====================================================== |
| Find the intersection of a block with a boundary of the viewport. */ |
| { |
| if( flag & CLIP_TOP ) { |
| *y = clip->ymin; |
| } else if( flag & CLIP_BOTTOM ) { |
| *y = clip->ymax; |
| } else if( flag & CLIP_RIGHT ) { |
| *x = clip->xmax; |
| } else if( flag & CLIP_LEFT ) { |
| *x = clip->xmin; |
| } |
| } |
| int BlockClip(clip_t *clip, int *x1, int *y1, int *x2, int* y2 ) |
| /*============================================================== |
| Clip a block with opposite corners (x1,y1) and (x2,y2) to the |
| active viewport based on the Cohen-Sutherland algorithm for line |
| clipping. Return the clipped coordinates and a decision drawing |
| flag ( 0 draw : 1 don't draw ). */ |
| { |
| int flag1; |
| int flag2; |
| flag1 = _L1OutCode( clip, *x1, *y1 ); |
| flag2 = _L1OutCode( clip, *x2, *y2 ); |
| for( ;; ) { |
| if( flag1 & flag2 ) break; /* trivially outside */ |
| if( flag1 == flag2 ) break; /* completely inside */ |
| if( flag1 == 0 ) { |
| block_inter( clip, x2, y2, flag2 ); |
| flag2 = _L1OutCode( clip, *x2, *y2 ); |
| } else { |
| block_inter( clip, x1, y1, flag1 ); |
| flag1 = _L1OutCode( clip, *x1, *y1 ); |
| } |
| } |
| return( flag1 & flag2 ); |
| } |
| int blit_clip(clip_t *dst_clip,int *dst_x,int *dst_y, |
| clip_t *src_clip,int *src_x, int *src_y, |
| int *w, int *h) |
| { |
| int sx0, sy0, sx1, sy1; |
| sx0 = *src_x; |
| sy0 = *src_y; |
| sx1 = sx0 + *w - 1; |
| sy1 = sy0 + *h - 1; |
| if( ! BlockClip( src_clip, &sx0, &sy0, &sx1, &sy1)) |
| { |
| int dx0, dy0, dx1, dy1; |
| dx0 = *dst_x + sx0 - *src_x; |
| dy0 = *dst_y + sy0 - *src_y; |
| dx1 = dx0 + sx1 - sx0; |
| dy1 = dy0 + sy1 - sy0; |
| if( ! BlockClip( dst_clip, &dx0, &dy0, &dx1, &dy1)) |
| { |
| *w = dx1 - dx0 + 1; |
| *h = dy1 - dy0 + 1; |
| *src_x += dx0 - *dst_x; |
| *src_y += dy0 - *dst_y; |
| *dst_x = dx0; |
| *dst_y = dy0; |
| return 0; |
| }; |
| return 1; |
| } |
| return 1; |
| }; |
| /drivers/old/ati2d/init.c |
|---|
| 0,0 → 1,1269 |
| static Bool rhdMapMMIO(RHDPtr rhdPtr) |
| { |
| rhdPtr->MMIOMapSize = 1 << rhdPtr->memsize[RHD_MMIO_BAR]; |
| rhdPtr->MMIOBase = MapIoMem(rhdPtr->memBase[RHD_MMIO_BAR], |
| rhdPtr->MMIOMapSize,PG_SW+PG_NOCACHE); |
| if( rhdPtr->MMIOBase==0) |
| return 0; |
| DBG(dbgprintf("Mapped IO at %x (size %x)\n", rhdPtr->MMIOBase, rhdPtr->MMIOMapSize)); |
| return 1; |
| } |
| /* Read MC register */ |
| unsigned INMC(RHDPtr info, int addr) |
| { |
| u32_t data; |
| if ((info->ChipFamily == CHIP_FAMILY_RS690) || |
| (info->ChipFamily == CHIP_FAMILY_RS740)) { |
| OUTREG(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK)); |
| data = INREG(RS690_MC_DATA); |
| } else if (info->ChipFamily == CHIP_FAMILY_RS600) { |
| OUTREG(RS600_MC_INDEX, (addr & RS600_MC_INDEX_MASK)); |
| data = INREG(RS600_MC_DATA); |
| } else if (IS_AVIVO_VARIANT) { |
| OUTREG(AVIVO_MC_INDEX, (addr & 0xff) | 0x7f0000); |
| (void)INREG(AVIVO_MC_INDEX); |
| data = INREG(AVIVO_MC_DATA); |
| OUTREG(AVIVO_MC_INDEX, 0); |
| (void)INREG(AVIVO_MC_INDEX); |
| } else { |
| OUTREG(R300_MC_IND_INDEX, addr & 0x3f); |
| (void)INREG(R300_MC_IND_INDEX); |
| data = INREG(R300_MC_IND_DATA); |
| OUTREG(R300_MC_IND_INDEX, 0); |
| (void)INREG(R300_MC_IND_INDEX); |
| } |
| return data; |
| } |
| /* Write MC information */ |
| void OUTMC(RHDPtr info, int addr, u32_t data) |
| { |
| if ((info->ChipFamily == CHIP_FAMILY_RS690) || |
| (info->ChipFamily == CHIP_FAMILY_RS740)) { |
| OUTREG(RS690_MC_INDEX, ((addr & RS690_MC_INDEX_MASK) | RS690_MC_INDEX_WR_EN)); |
| OUTREG(RS690_MC_DATA, data); |
| OUTREG(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); |
| } |
| else if (info->ChipFamily == CHIP_FAMILY_RS600) { |
| OUTREG(RS600_MC_INDEX, ((addr & RS600_MC_INDEX_MASK) | RS600_MC_INDEX_WR_EN)); |
| OUTREG(RS600_MC_DATA, data); |
| OUTREG(RS600_MC_INDEX, RS600_MC_INDEX_WR_ACK); |
| } |
| else if (IS_AVIVO_VARIANT) { |
| OUTREG(AVIVO_MC_INDEX, (addr & 0xff) | 0xff0000); |
| (void)INREG(AVIVO_MC_INDEX); |
| OUTREG(AVIVO_MC_DATA, data); |
| OUTREG(AVIVO_MC_INDEX, 0); |
| (void)INREG(AVIVO_MC_INDEX); |
| } |
| else { |
| OUTREG(R300_MC_IND_INDEX, (((addr) & 0x3f) | R300_MC_IND_WR_EN)); |
| (void)INREG(R300_MC_IND_INDEX); |
| OUTREG(R300_MC_IND_DATA, data); |
| OUTREG(R300_MC_IND_INDEX, 0); |
| (void)INREG(R300_MC_IND_INDEX); |
| } |
| } |
| static Bool avivo_get_mc_idle(RHDPtr info) |
| { |
| if (info->ChipFamily >= CHIP_FAMILY_R600) { |
| /* no idea where this is on r600 yet */ |
| return TRUE; |
| } |
| else if (info->ChipFamily == CHIP_FAMILY_RV515) { |
| if (INMC(info, RV515_MC_STATUS) & RV515_MC_STATUS_IDLE) |
| return TRUE; |
| else |
| return FALSE; |
| } |
| else if (info->ChipFamily == CHIP_FAMILY_RS600) |
| { |
| if (INMC(info, RS600_MC_STATUS) & RS600_MC_STATUS_IDLE) |
| return TRUE; |
| else |
| return FALSE; |
| } |
| else if ((info->ChipFamily == CHIP_FAMILY_RS690) || |
| (info->ChipFamily == CHIP_FAMILY_RS740)) { |
| if (INMC(info, RS690_MC_STATUS) & RS690_MC_STATUS_IDLE) |
| return TRUE; |
| else |
| return FALSE; |
| } |
| else { |
| if (INMC(info, R520_MC_STATUS) & R520_MC_STATUS_IDLE) |
| return TRUE; |
| else |
| return FALSE; |
| } |
| } |
| #define LOC_FB 0x1 |
| #define LOC_AGP 0x2 |
| static void radeon_read_mc_fb_agp_location(RHDPtr info, int mask, |
| u32_t *fb_loc, u32_t *agp_loc, u32_t *agp_loc_hi) |
| { |
| if (info->ChipFamily >= CHIP_FAMILY_RV770) |
| { |
| if (mask & LOC_FB) |
| *fb_loc = INREG(R700_MC_VM_FB_LOCATION); |
| if (mask & LOC_AGP) { |
| *agp_loc = INREG(R600_MC_VM_AGP_BOT); |
| *agp_loc_hi = INREG(R600_MC_VM_AGP_TOP); |
| } |
| } |
| else if (info->ChipFamily >= CHIP_FAMILY_R600) |
| { |
| if (mask & LOC_FB) |
| *fb_loc = INREG(R600_MC_VM_FB_LOCATION); |
| if (mask & LOC_AGP) { |
| *agp_loc = INREG(R600_MC_VM_AGP_BOT); |
| *agp_loc_hi = INREG(R600_MC_VM_AGP_TOP); |
| } |
| } |
| else if (info->ChipFamily == CHIP_FAMILY_RV515) |
| { |
| if (mask & LOC_FB) |
| *fb_loc = INMC(info, RV515_MC_FB_LOCATION); |
| if (mask & LOC_AGP) { |
| *agp_loc = INMC(info, RV515_MC_AGP_LOCATION); |
| *agp_loc_hi = 0; |
| } |
| } |
| else if (info->ChipFamily == CHIP_FAMILY_RS600) |
| { |
| if (mask & LOC_FB) |
| *fb_loc = INMC(info, RS600_MC_FB_LOCATION); |
| if (mask & LOC_AGP) { |
| *agp_loc = 0;//INMC(pScrn, RS600_MC_AGP_LOCATION); |
| *agp_loc_hi = 0; |
| } |
| } |
| else if ((info->ChipFamily == CHIP_FAMILY_RS690) || |
| (info->ChipFamily == CHIP_FAMILY_RS740)) |
| { |
| if (mask & LOC_FB) |
| *fb_loc = INMC(info, RS690_MC_FB_LOCATION); |
| if (mask & LOC_AGP) { |
| *agp_loc = INMC(info, RS690_MC_AGP_LOCATION); |
| *agp_loc_hi = 0; |
| } |
| } |
| else if (info->ChipFamily >= CHIP_FAMILY_R520) |
| { |
| if (mask & LOC_FB) |
| *fb_loc = INMC(info, R520_MC_FB_LOCATION); |
| if (mask & LOC_AGP) { |
| *agp_loc = INMC(info, R520_MC_AGP_LOCATION); |
| *agp_loc_hi = 0; |
| } |
| } |
| else |
| { |
| if (mask & LOC_FB) |
| *fb_loc = INREG(RADEON_MC_FB_LOCATION); |
| if (mask & LOC_AGP) |
| *agp_loc = INREG(RADEON_MC_AGP_LOCATION); |
| } |
| } |
| static void radeon_write_mc_fb_agp_location(RHDPtr info, int mask, u32_t fb_loc, |
| u32_t agp_loc, u32_t agp_loc_hi) |
| { |
| if (info->ChipFamily >= CHIP_FAMILY_RV770) { |
| if (mask & LOC_FB) |
| OUTREG(R700_MC_VM_FB_LOCATION, fb_loc); |
| if (mask & LOC_AGP) { |
| OUTREG(R600_MC_VM_AGP_BOT, agp_loc); |
| OUTREG(R600_MC_VM_AGP_TOP, agp_loc_hi); |
| } |
| } |
| else if (info->ChipFamily >= CHIP_FAMILY_R600) |
| { |
| if (mask & LOC_FB) |
| OUTREG(R600_MC_VM_FB_LOCATION, fb_loc); |
| if (mask & LOC_AGP) { |
| OUTREG(R600_MC_VM_AGP_BOT, agp_loc); |
| OUTREG(R600_MC_VM_AGP_TOP, agp_loc_hi); |
| } |
| } |
| else if (info->ChipFamily == CHIP_FAMILY_RV515) |
| { |
| if (mask & LOC_FB) |
| OUTMC(info, RV515_MC_FB_LOCATION, fb_loc); |
| if (mask & LOC_AGP) |
| OUTMC(info, RV515_MC_AGP_LOCATION, agp_loc); |
| (void)INMC(info, RV515_MC_AGP_LOCATION); |
| } |
| else if (info->ChipFamily == CHIP_FAMILY_RS600) |
| { |
| if (mask & LOC_FB) |
| OUTMC(info, RS600_MC_FB_LOCATION, fb_loc); |
| /* if (mask & LOC_AGP) |
| OUTMC(pScrn, RS600_MC_AGP_LOCATION, agp_loc);*/ |
| } |
| else if ((info->ChipFamily == CHIP_FAMILY_RS690) || |
| (info->ChipFamily == CHIP_FAMILY_RS740)) |
| { |
| if (mask & LOC_FB) |
| OUTMC(info, RS690_MC_FB_LOCATION, fb_loc); |
| if (mask & LOC_AGP) |
| OUTMC(info, RS690_MC_AGP_LOCATION, agp_loc); |
| } |
| else if (info->ChipFamily >= CHIP_FAMILY_R520) |
| { |
| if (mask & LOC_FB) |
| OUTMC(info, R520_MC_FB_LOCATION, fb_loc); |
| if (mask & LOC_AGP) |
| OUTMC(info, R520_MC_AGP_LOCATION, agp_loc); |
| (void)INMC(info, R520_MC_FB_LOCATION); |
| } |
| else { |
| if (mask & LOC_FB) |
| OUTREG(RADEON_MC_FB_LOCATION, fb_loc); |
| if (mask & LOC_AGP) |
| OUTREG(RADEON_MC_AGP_LOCATION, agp_loc); |
| } |
| } |
| static void RADEONUpdateMemMapRegisters(RHDPtr info) |
| { |
| u32_t timeout; |
| u32_t mc_fb_loc, mc_agp_loc, mc_agp_loc_hi; |
| radeon_read_mc_fb_agp_location(info, LOC_FB | LOC_AGP, &mc_fb_loc, |
| &mc_agp_loc, &mc_agp_loc_hi); |
| if (IS_AVIVO_VARIANT) |
| { |
| if (mc_fb_loc != info->mc_fb_location || |
| mc_agp_loc != info->mc_agp_location) |
| { |
| u32_t d1crtc, d2crtc; |
| u32_t tmp; |
| // RADEONWaitForIdleMMIO(pScrn); |
| OUTREG(AVIVO_D1VGA_CONTROL, INREG(AVIVO_D1VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE); |
| OUTREG(AVIVO_D2VGA_CONTROL, INREG(AVIVO_D2VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE); |
| /* Stop display & memory access */ |
| d1crtc = INREG(AVIVO_D1CRTC_CONTROL); |
| OUTREG(AVIVO_D1CRTC_CONTROL, d1crtc & ~AVIVO_CRTC_EN); |
| d2crtc = INREG(AVIVO_D2CRTC_CONTROL); |
| OUTREG(AVIVO_D2CRTC_CONTROL, d2crtc & ~AVIVO_CRTC_EN); |
| tmp = INREG(AVIVO_D2CRTC_CONTROL); |
| usleep(1000); |
| timeout = 0; |
| while (!(avivo_get_mc_idle(info))) |
| { |
| if (++timeout > 1000000) |
| { |
| dbgprintf("Timeout trying to update memory controller settings !\n"); |
| dbgprintf("You will probably crash now ... \n"); |
| /* Nothing we can do except maybe try to kill the server, |
| * let's wait 2 seconds to leave the above message a chance |
| * to maybe hit the disk and continue trying to setup despite |
| * the MC being non-idle |
| */ |
| usleep(20000); |
| } |
| usleep(10); |
| } |
| radeon_write_mc_fb_agp_location(info, LOC_FB | LOC_AGP, |
| info->mc_fb_location, |
| info->mc_agp_location, |
| info->mc_agp_location_hi); |
| if (info->ChipFamily < CHIP_FAMILY_R600) { |
| OUTREG(AVIVO_HDP_FB_LOCATION, info->mc_fb_location); |
| } |
| else { |
| OUTREG(R600_HDP_NONSURFACE_BASE, (info->mc_fb_location << 16) & 0xff0000); |
| } |
| OUTREG(AVIVO_D1CRTC_CONTROL, d1crtc ); |
| OUTREG(AVIVO_D2CRTC_CONTROL, d2crtc ); |
| tmp = INREG(AVIVO_D2CRTC_CONTROL); |
| /* Reset the engine and HDP */ |
| // RADEONEngineReset(pScrn); |
| } |
| } |
| else |
| { |
| /* Write memory mapping registers only if their value change |
| * since we must ensure no access is done while they are |
| * reprogrammed |
| */ |
| if ( mc_fb_loc != info->mc_fb_location || |
| mc_agp_loc != info->mc_agp_location) |
| { |
| u32_t crtc_ext_cntl, crtc_gen_cntl, crtc2_gen_cntl=0, ov0_scale_cntl; |
| u32_t old_mc_status, status_idle; |
| dbgprintf(" Map Changed ! Applying ...\n"); |
| /* Make sure engine is idle. We assume the CCE is stopped |
| * at this point |
| */ |
| // RADEONWaitForIdleMMIO(info); |
| if (info->IsIGP) |
| goto igp_no_mcfb; |
| /* Capture MC_STATUS in case things go wrong ... */ |
| old_mc_status = INREG(RADEON_MC_STATUS); |
| /* Stop display & memory access */ |
| ov0_scale_cntl = INREG(RADEON_OV0_SCALE_CNTL); |
| OUTREG(RADEON_OV0_SCALE_CNTL, ov0_scale_cntl & ~RADEON_SCALER_ENABLE); |
| crtc_ext_cntl = INREG(RADEON_CRTC_EXT_CNTL); |
| OUTREG(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl | RADEON_CRTC_DISPLAY_DIS); |
| crtc_gen_cntl = INREG(RADEON_CRTC_GEN_CNTL); |
| // RADEONWaitForVerticalSync(pScrn); |
| OUTREG(RADEON_CRTC_GEN_CNTL, |
| (crtc_gen_cntl & ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_ICON_EN)) |
| | RADEON_CRTC_DISP_REQ_EN_B | RADEON_CRTC_EXT_DISP_EN); |
| if (info->HasCRTC2) |
| { |
| crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL); |
| // RADEONWaitForVerticalSync2(pScrn); |
| OUTREG(RADEON_CRTC2_GEN_CNTL, (crtc2_gen_cntl |
| & ~(RADEON_CRTC2_CUR_EN | RADEON_CRTC2_ICON_EN)) |
| | RADEON_CRTC2_DISP_REQ_EN_B); |
| } |
| /* Make sure the chip settles down (paranoid !) */ |
| usleep(1000); |
| /* Wait for MC idle */ |
| if (IS_R300_VARIANT) |
| status_idle = R300_MC_IDLE; |
| else |
| status_idle = RADEON_MC_IDLE; |
| timeout = 0; |
| while (!(INREG(RADEON_MC_STATUS) & status_idle)) |
| { |
| if (++timeout > 1000000) |
| { |
| dbgprintf("Timeout trying to update memory controller settings !\n"); |
| dbgprintf("MC_STATUS = 0x%08x (on entry = 0x%08x)\n", |
| INREG(RADEON_MC_STATUS), old_mc_status); |
| dbgprintf("You will probably crash now ... \n"); |
| /* Nothing we can do except maybe try to kill the server, |
| * let's wait 2 seconds to leave the above message a chance |
| * to maybe hit the disk and continue trying to setup despite |
| * the MC being non-idle |
| */ |
| usleep(20000); |
| } |
| usleep(10); |
| } |
| /* Update maps, first clearing out AGP to make sure we don't get |
| * a temporary overlap |
| */ |
| OUTREG(RADEON_MC_AGP_LOCATION, 0xfffffffc); |
| OUTREG(RADEON_MC_FB_LOCATION, info->mc_fb_location); |
| radeon_write_mc_fb_agp_location(info, LOC_FB | LOC_AGP, info->mc_fb_location, |
| 0xfffffffc, 0); |
| OUTREG(RADEON_CRTC_GEN_CNTL,crtc_gen_cntl ); |
| OUTREG(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); |
| OUTREG(RADEON_OV0_SCALE_CNTL, ov0_scale_cntl ); |
| igp_no_mcfb: |
| radeon_write_mc_fb_agp_location(info, LOC_AGP, 0, |
| info->mc_agp_location, 0); |
| /* Make sure map fully reached the chip */ |
| (void)INREG(RADEON_MC_FB_LOCATION); |
| dbgprintf(" Map applied, resetting engine ...\n"); |
| /* Reset the engine and HDP */ |
| // RADEONEngineReset(pScrn); |
| /* Make sure we have sane offsets before re-enabling the CRTCs, disable |
| * stereo, clear offsets, and wait for offsets to catch up with hw |
| */ |
| OUTREG(RADEON_CRTC_OFFSET_CNTL, RADEON_CRTC_OFFSET_FLIP_CNTL); |
| OUTREG(RADEON_CRTC_OFFSET, 0); |
| OUTREG(RADEON_CUR_OFFSET, 0); |
| timeout = 0; |
| while(INREG(RADEON_CRTC_OFFSET) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET) |
| { |
| if (timeout++ > 1000000) { |
| dbgprintf("Timeout waiting for CRTC offset to update !\n"); |
| break; |
| } |
| usleep(1000); |
| } |
| if (info->HasCRTC2) |
| { |
| OUTREG(RADEON_CRTC2_OFFSET_CNTL, RADEON_CRTC2_OFFSET_FLIP_CNTL); |
| OUTREG(RADEON_CRTC2_OFFSET, 0); |
| OUTREG(RADEON_CUR2_OFFSET, 0); |
| timeout = 0; |
| while(INREG(RADEON_CRTC2_OFFSET) & RADEON_CRTC2_OFFSET__GUI_TRIG_OFFSET) |
| { |
| if (timeout++ > 1000000) { |
| dbgprintf("Timeout waiting for CRTC2 offset to update !\n"); |
| break; |
| } |
| usleep(1000); |
| } |
| } |
| } |
| dbgprintf("Updating display base addresses...\n"); |
| OUTREG(RADEON_DISPLAY_BASE_ADDR, info->fbLocation); |
| if (info->HasCRTC2) |
| OUTREG(RADEON_DISPLAY2_BASE_ADDR, info->fbLocation); |
| OUTREG(RADEON_OV0_BASE_ADDR, info->fbLocation); |
| (void)INREG(RADEON_OV0_BASE_ADDR); |
| /* More paranoia delays, wait 100ms */ |
| usleep(1000); |
| dbgprintf("Memory map updated.\n"); |
| }; |
| }; |
| static void RADEONInitMemoryMap(RHDPtr info) |
| { |
| u32_t mem_size; |
| u32_t aper_size; |
| radeon_read_mc_fb_agp_location(info, LOC_FB | LOC_AGP, &info->mc_fb_location, |
| &info->mc_agp_location, &info->mc_agp_location_hi); |
| dbgprintf(" MC_FB_LOCATION : 0x%08x\n", (unsigned)info->mc_fb_location); |
| dbgprintf(" MC_AGP_LOCATION : 0x%08x\n", (unsigned)info->mc_agp_location); |
| /* We shouldn't use info->videoRam here which might have been clipped |
| * but the real video RAM instead |
| */ |
| if (info->ChipFamily >= CHIP_FAMILY_R600){ |
| mem_size = INREG(R600_CONFIG_MEMSIZE); |
| aper_size = INREG(R600_CONFIG_APER_SIZE); |
| } |
| else { |
| mem_size = INREG(RADEON_CONFIG_MEMSIZE); |
| aper_size = INREG(RADEON_CONFIG_APER_SIZE); |
| } |
| if (mem_size == 0) |
| mem_size = 0x800000; |
| /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM - |
| Novell bug 204882 + along with lots of ubuntu ones */ |
| if (aper_size > mem_size) |
| mem_size = aper_size; |
| if ( (info->ChipFamily != CHIP_FAMILY_RS600) && |
| (info->ChipFamily != CHIP_FAMILY_RS690) && |
| (info->ChipFamily != CHIP_FAMILY_RS740)) |
| { |
| if (info->IsIGP) |
| info->mc_fb_location = INREG(RADEON_NB_TOM); |
| else |
| { |
| u32_t aper0_base; |
| if (info->ChipFamily >= CHIP_FAMILY_R600) { |
| aper0_base = INREG(R600_CONFIG_F0_BASE); |
| } |
| else { |
| aper0_base = INREG(RADEON_CONFIG_APER_0_BASE); |
| } |
| dbgprintf("aper0 base %x\n", aper0_base ); |
| /* Recent chips have an "issue" with the memory controller, the |
| * location must be aligned to the size. We just align it down, |
| * too bad if we walk over the top of system memory, we don't |
| * use DMA without a remapped anyway. |
| * Affected chips are rv280, all r3xx, and all r4xx, but not IGP |
| */ |
| if ( info->ChipFamily == CHIP_FAMILY_RV280 || |
| info->ChipFamily == CHIP_FAMILY_R300 || |
| info->ChipFamily == CHIP_FAMILY_R350 || |
| info->ChipFamily == CHIP_FAMILY_RV350 || |
| info->ChipFamily == CHIP_FAMILY_RV380 || |
| info->ChipFamily == CHIP_FAMILY_R420 || |
| info->ChipFamily == CHIP_FAMILY_RV410) |
| aper0_base &= ~(mem_size - 1); |
| if ( info->ChipFamily >= CHIP_FAMILY_R600) { |
| info->mc_fb_location = (aper0_base >> 24) | |
| (((aper0_base + mem_size - 1) & 0xff000000U) >> 8); |
| dbgprintf("mc fb loc is %08x\n", (unsigned int)info->mc_fb_location); |
| } |
| else { |
| info->mc_fb_location = (aper0_base >> 16) | |
| ((aper0_base + mem_size - 1) & 0xffff0000U); |
| dbgprintf("mc fb loc is %08x\n", (unsigned int)info->mc_fb_location); |
| } |
| } |
| } |
| if (info->ChipFamily >= CHIP_FAMILY_R600) { |
| info->fbLocation = (info->mc_fb_location & 0xffff) << 24; |
| } |
| else { |
| info->fbLocation = (info->mc_fb_location & 0xffff) << 16; |
| } |
| /* Just disable the damn AGP apertures for now, it may be |
| * re-enabled later by the DRM |
| */ |
| if (IS_AVIVO_VARIANT) { |
| if (info->ChipFamily >= CHIP_FAMILY_R600) { |
| OUTREG(R600_HDP_NONSURFACE_BASE, (info->mc_fb_location << 16) & 0xff0000); |
| } |
| else { |
| OUTREG(AVIVO_HDP_FB_LOCATION, info->mc_fb_location); |
| } |
| info->mc_agp_location = 0x003f0000; |
| } |
| else |
| info->mc_agp_location = 0xffffffc0; |
| dbgprintf("RADEONInitMemoryMap() : \n"); |
| dbgprintf(" mem_size : 0x%08x\n", (u32_t)mem_size); |
| dbgprintf(" MC_FB_LOCATION : 0x%08x\n", (unsigned)info->mc_fb_location); |
| dbgprintf(" MC_AGP_LOCATION : 0x%08x\n", (unsigned)info->mc_agp_location); |
| dbgprintf(" FB_LOCATION : 0x%08x\n", (unsigned)info->fbLocation); |
| RADEONUpdateMemMapRegisters(info); |
| } |
| static void RADEONGetVRamType(RHDPtr info) |
| { |
| u32_t tmp; |
| if (info->IsIGP || (info->ChipFamily >= CHIP_FAMILY_R300)) |
| info->IsDDR = TRUE; |
| else if (INREG(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR) |
| info->IsDDR = TRUE; |
| else |
| info->IsDDR = FALSE; |
| if ( (info->ChipFamily >= CHIP_FAMILY_R600) && |
| (info->ChipFamily <= CHIP_FAMILY_RV635)) |
| { |
| int chansize; |
| /* r6xx */ |
| tmp = INREG(R600_RAMCFG); |
| if (tmp & R600_CHANSIZE_OVERRIDE) |
| chansize = 16; |
| else if (tmp & R600_CHANSIZE) |
| chansize = 64; |
| else |
| chansize = 32; |
| if (info->ChipFamily == CHIP_FAMILY_R600) |
| info->RamWidth = 8 * chansize; |
| else if (info->ChipFamily == CHIP_FAMILY_RV670) |
| info->RamWidth = 4 * chansize; |
| else if ((info->ChipFamily == CHIP_FAMILY_RV610) || |
| (info->ChipFamily == CHIP_FAMILY_RV620)) |
| info->RamWidth = chansize; |
| else if ((info->ChipFamily == CHIP_FAMILY_RV630) || |
| (info->ChipFamily == CHIP_FAMILY_RV635)) |
| info->RamWidth = 2 * chansize; |
| } |
| else if (info->ChipFamily == CHIP_FAMILY_RV515) { |
| /* rv515/rv550 */ |
| tmp = INMC(info, RV515_MC_CNTL); |
| tmp &= RV515_MEM_NUM_CHANNELS_MASK; |
| switch (tmp) { |
| case 0: info->RamWidth = 64; break; |
| case 1: info->RamWidth = 128; break; |
| default: info->RamWidth = 128; break; |
| } |
| } |
| else if ((info->ChipFamily >= CHIP_FAMILY_R520) && |
| (info->ChipFamily <= CHIP_FAMILY_RV570)){ |
| /* r520/rv530/rv560/rv570/r580 */ |
| tmp = INMC(info, R520_MC_CNTL0); |
| switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) { |
| case 0: info->RamWidth = 32; break; |
| case 1: info->RamWidth = 64; break; |
| case 2: info->RamWidth = 128; break; |
| case 3: info->RamWidth = 256; break; |
| default: info->RamWidth = 64; break; |
| } |
| if (tmp & R520_MC_CHANNEL_SIZE) { |
| info->RamWidth *= 2; |
| } |
| } |
| else if ((info->ChipFamily >= CHIP_FAMILY_R300) && |
| (info->ChipFamily <= CHIP_FAMILY_RV410)) { |
| /* r3xx, r4xx */ |
| tmp = INREG(RADEON_MEM_CNTL); |
| tmp &= R300_MEM_NUM_CHANNELS_MASK; |
| switch (tmp) { |
| case 0: info->RamWidth = 64; break; |
| case 1: info->RamWidth = 128; break; |
| case 2: info->RamWidth = 256; break; |
| default: info->RamWidth = 128; break; |
| } |
| } |
| else if ((info->ChipFamily == CHIP_FAMILY_RV100) || |
| (info->ChipFamily == CHIP_FAMILY_RS100) || |
| (info->ChipFamily == CHIP_FAMILY_RS200)){ |
| tmp = INREG(RADEON_MEM_CNTL); |
| if (tmp & RV100_HALF_MODE) |
| info->RamWidth = 32; |
| else |
| info->RamWidth = 64; |
| if (!info->HasCRTC2) { |
| info->RamWidth /= 4; |
| info->IsDDR = TRUE; |
| } |
| } |
| else if (info->ChipFamily <= CHIP_FAMILY_RV280) { |
| tmp = INREG(RADEON_MEM_CNTL); |
| if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) |
| info->RamWidth = 128; |
| else |
| info->RamWidth = 64; |
| } else { |
| /* newer IGPs */ |
| info->RamWidth = 128; |
| } |
| /* This may not be correct, as some cards can have half of channel disabled |
| * ToDo: identify these cases |
| */ |
| } |
| /* |
| * Depending on card genertation, chipset bugs, etc... the amount of vram |
| * accessible to the CPU can vary. This function is our best shot at figuring |
| * it out. Returns a value in KB. |
| */ |
| static u32_t RADEONGetAccessibleVRAM(RHDPtr info) |
| { |
| u32_t aper_size; |
| unsigned char byte; |
| if (info->ChipFamily >= CHIP_FAMILY_R600) |
| aper_size = INREG(R600_CONFIG_APER_SIZE) / 1024; |
| else |
| aper_size = INREG(RADEON_CONFIG_APER_SIZE) / 1024; |
| /* Set HDP_APER_CNTL only on cards that are known not to be broken, |
| * that is has the 2nd generation multifunction PCI interface |
| */ |
| if (info->ChipFamily == CHIP_FAMILY_RV280 || |
| info->ChipFamily == CHIP_FAMILY_RV350 || |
| info->ChipFamily == CHIP_FAMILY_RV380 || |
| info->ChipFamily == CHIP_FAMILY_R420 || |
| info->ChipFamily == CHIP_FAMILY_RV410 || |
| IS_AVIVO_VARIANT) { |
| MASKREG (RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL, |
| ~RADEON_HDP_APER_CNTL); |
| dbgprintf("Generation 2 PCI interface, using max accessible memory\n"); |
| return aper_size * 2; |
| } |
| /* Older cards have all sorts of funny issues to deal with. First |
| * check if it's a multifunction card by reading the PCI config |
| * header type... Limit those to one aperture size |
| */ |
| byte = pciReadByte(info->PciTag, 0xe); |
| if (byte & 0x80) { |
| dbgprintf("Generation 1 PCI interface in multifunction mode, " |
| "accessible memory limited to one aperture\n"); |
| return aper_size; |
| } |
| /* Single function older card. We read HDP_APER_CNTL to see how the BIOS |
| * have set it up. We don't write this as it's broken on some ASICs but |
| * we expect the BIOS to have done the right thing (might be too optimistic...) |
| */ |
| if (INREG(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL) |
| return aper_size * 2; |
| return aper_size; |
| } |
| int RADEONDRIGetPciAperTableSize(RHDPtr info) |
| { |
| int ret_size; |
| int num_pages; |
| num_pages = (info->pciAperSize * 1024 * 1024) / 4096; |
| ret_size = num_pages * sizeof(unsigned int); |
| return ret_size; |
| } |
| static Bool RADEONPreInitVRAM(RHDPtr info) |
| { |
| u32_t accessible, bar_size; |
| if ((!IS_AVIVO_VARIANT) && info->IsIGP) |
| { |
| u32_t tom = INREG(RADEON_NB_TOM); |
| info->videoRam = (((tom >> 16) - |
| (tom & 0xffff) + 1) << 6); |
| OUTREG(RADEON_CONFIG_MEMSIZE, info->videoRam * 1024); |
| } |
| else |
| { |
| if (info->ChipFamily >= CHIP_FAMILY_R600) |
| info->videoRam = INREG(R600_CONFIG_MEMSIZE) / 1024; |
| else |
| { |
| /* Read VRAM size from card */ |
| info->videoRam = INREG(RADEON_CONFIG_MEMSIZE) / 1024; |
| /* Some production boards of m6 will return 0 if it's 8 MB */ |
| if (info->videoRam == 0) |
| { |
| info->videoRam = 8192; |
| OUTREG(RADEON_CONFIG_MEMSIZE, 0x800000); |
| } |
| } |
| } |
| RADEONGetVRamType(info); |
| /* Get accessible memory */ |
| accessible = RADEONGetAccessibleVRAM(info); |
| /* Crop it to the size of the PCI BAR */ |
| // bar_size = PCI_REGION_SIZE(info->PciInfo, 0) / 1024; |
| bar_size = 1 << (info->memsize[RHD_FB_BAR] - 10); |
| if (bar_size == 0) |
| bar_size = 0x20000; |
| if (accessible > bar_size) |
| accessible = bar_size; |
| dbgprintf("Detected total video RAM=%dK width=%dbit," |
| "accessible=%uK (PCI BAR=%uK)\n", |
| info->videoRam, info->RamWidth, |
| (unsigned)accessible, (unsigned)bar_size); |
| if (info->videoRam > accessible) |
| info->videoRam = accessible; |
| if (!IS_AVIVO_VARIANT) |
| info->MemCntl = INREG(RADEON_SDRAM_MODE_REG); |
| info->BusCntl = INREG(RADEON_BUS_CNTL); |
| info->videoRam &= ~1023; |
| info->FbMapSize = info->videoRam * 1024; |
| // info->gartSize = RADEON_DEFAULT_GART_SIZE; |
| info->ringSize = RADEON_DEFAULT_RING_SIZE; |
| info->bufSize = RADEON_DEFAULT_BUFFER_SIZE; |
| // info->gartTexSize = info->gartSize - (info->ringSize + info->bufSize); |
| info->pciAperSize = RADEON_DEFAULT_PCI_APER_SIZE; |
| info->CPusecTimeout = RADEON_DEFAULT_CP_TIMEOUT; |
| /* if the card is PCI Express reserve the last 32k for the gart table */ |
| // if (info->cardType == CARD_PCIE ) |
| // /* work out the size of pcie aperture */ |
| // info->FbSecureSize = RADEONDRIGetPciAperTableSize(info); |
| // else |
| // info->FbSecureSize = 0; |
| return TRUE; |
| } |
| static Bool RADEONPreInitChipType(RHDPtr rhdPtr) |
| { |
| u32_t cmd_stat; |
| rhdPtr->ChipErrata = 0; |
| if ( (rhdPtr->ChipFamily == CHIP_FAMILY_R300) && |
| ((_RHDRegRead(rhdPtr,RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) |
| == RADEON_CFG_ATI_REV_A11)) |
| rhdPtr->ChipErrata |= CHIP_ERRATA_R300_CG; |
| if ( (rhdPtr->ChipFamily == CHIP_FAMILY_RV200) || |
| (rhdPtr->ChipFamily == CHIP_FAMILY_RS200) ) |
| rhdPtr->ChipErrata |= CHIP_ERRATA_PLL_DUMMYREADS; |
| if ( (rhdPtr->ChipFamily == CHIP_FAMILY_RV100) || |
| (rhdPtr->ChipFamily == CHIP_FAMILY_RS100) || |
| (rhdPtr->ChipFamily == CHIP_FAMILY_RS200) ) |
| rhdPtr->ChipErrata |= CHIP_ERRATA_PLL_DELAY; |
| rhdPtr->cardType = CARD_PCI; |
| cmd_stat = pciReadLong(rhdPtr->PciTag, PCI_CMD_STAT_REG); |
| if (cmd_stat & RADEON_CAP_LIST) |
| { |
| u32_t cap_ptr, cap_id; |
| cap_ptr = pciReadLong(rhdPtr->PciTag, RADEON_CAPABILITIES_PTR_PCI_CONFIG); |
| cap_ptr &= RADEON_CAP_PTR_MASK; |
| while(cap_ptr != RADEON_CAP_ID_NULL) |
| { |
| cap_id = pciReadLong(rhdPtr->PciTag, cap_ptr); |
| if ((cap_id & 0xff)== RADEON_CAP_ID_AGP) { |
| rhdPtr->cardType = CARD_AGP; |
| break; |
| } |
| if ((cap_id & 0xff)== RADEON_CAP_ID_EXP) { |
| rhdPtr->cardType = CARD_PCIE; |
| break; |
| } |
| cap_ptr = (cap_id >> 8) & RADEON_CAP_PTR_MASK; |
| } |
| } |
| dbgprintf("%s card detected\n",(rhdPtr->cardType==CARD_PCI) ? "PCI" : |
| (rhdPtr->cardType==CARD_PCIE) ? "PCIE" : "AGP"); |
| /* treat PCIE IGP cards as PCI */ |
| if (rhdPtr->cardType == CARD_PCIE && rhdPtr->IsIGP) |
| rhdPtr->cardType = CARD_PCI; |
| if ( (rhdPtr->ChipFamily == CHIP_FAMILY_RS100) || |
| (rhdPtr->ChipFamily == CHIP_FAMILY_RS200) || |
| (rhdPtr->ChipFamily == CHIP_FAMILY_RS300) || |
| (rhdPtr->ChipFamily == CHIP_FAMILY_RS400) || |
| (rhdPtr->ChipFamily == CHIP_FAMILY_RS480) || |
| (rhdPtr->ChipFamily == CHIP_FAMILY_RS600) || |
| (rhdPtr->ChipFamily == CHIP_FAMILY_RS690) || |
| (rhdPtr->ChipFamily == CHIP_FAMILY_RS740)) |
| rhdPtr->has_tcl = FALSE; |
| else { |
| rhdPtr->has_tcl = TRUE; |
| } |
| // rhdPtr->LinearAddr = rhdPtr->memBase[RHD_FB_BAR]; |
| return TRUE; |
| } |
| #if 0 |
| static Bool RADEONSetAgpMode(RADEONInfoPtr info, ScreenPtr pScreen) |
| { |
| unsigned char *RADEONMMIO = info->MMIO; |
| // unsigned long mode = drmAgpGetMode(info->dri->drmFD); /* Default mode */ |
| // unsigned int vendor = drmAgpVendorId(info->dri->drmFD); |
| // unsigned int device = drmAgpDeviceId(info->dri->drmFD); |
| /* ignore agp 3.0 mode bit from the chip as it's buggy on some cards with |
| pcie-agp rialto bridge chip - use the one from bridge which must match */ |
| uint32_t agp_status = (INREG(RADEON_AGP_STATUS) ); // & RADEON_AGP_MODE_MASK; |
| Bool is_v3 = (agp_status & RADEON_AGPv3_MODE); |
| unsigned int defaultMode; |
| if (is_v3) { |
| defaultMode = (agp_status & RADEON_AGPv3_8X_MODE) ? 8 : 4; |
| } else { |
| if (agp_status & RADEON_AGP_4X_MODE) defaultMode = 4; |
| else if (agp_status & RADEON_AGP_2X_MODE) defaultMode = 2; |
| else defaultMode = 1; |
| } |
| // agpMode = defaultMode; |
| dbgprintf(pScreen->myNum, from, "Using AGP %dx\n", dbgprintf); |
| mode &= ~RADEON_AGP_MODE_MASK; |
| if (is_v3) { |
| /* only set one mode bit for AGPv3 */ |
| switch (defaultMode) { |
| case 8: mode |= RADEON_AGPv3_8X_MODE; break; |
| case 4: default: mode |= RADEON_AGPv3_4X_MODE; |
| } |
| /*TODO: need to take care of other bits valid for v3 mode |
| * currently these bits are not used in all tested cards. |
| */ |
| } else { |
| switch (defaultMode) { |
| case 4: mode |= RADEON_AGP_4X_MODE; |
| case 2: mode |= RADEON_AGP_2X_MODE; |
| case 1: default: mode |= RADEON_AGP_1X_MODE; |
| } |
| } |
| /* AGP Fast Writes. |
| * TODO: take into account that certain agp modes don't support fast |
| * writes at all */ |
| mode &= ~RADEON_AGP_FW_MODE; /* Disable per default */ |
| dbgprintf("AGP Mode 0x%08lx\n", mode); |
| if (drmAgpEnable(info->dri->drmFD, mode) < 0) { |
| xf86DrvMsg(pScreen->myNum, X_ERROR, "[agp] AGP not enabled\n"); |
| drmAgpRelease(info->dri->drmFD); |
| return FALSE; |
| } |
| /* Workaround for some hardware bugs */ |
| if (info->ChipFamily < CHIP_FAMILY_R200) |
| OUTREG(RADEON_AGP_CNTL, INREG(RADEON_AGP_CNTL) | 0x000e0000); |
| /* Modify the mode if the default mode |
| * is not appropriate for this |
| * particular combination of graphics |
| * card and AGP chipset. |
| */ |
| return TRUE; |
| } |
| #endif |
| Bool RHDPreInit() |
| { |
| RHDPtr info; |
| /* We need access to IO space already */ |
| if ( !rhdMapMMIO(&rhd) ) { |
| dbgprintf("Failed to map MMIO.\n"); |
| return FALSE; |
| }; |
| if( !RADEONPreInitChipType(&rhd)) |
| return FALSE; |
| if (!RADEONPreInitVRAM(&rhd)) |
| return FALSE; |
| RADEONInitMemoryMap(&rhd); |
| if (!rhd.videoRam) |
| { |
| dbgprintf("No Video RAM detected.\n"); |
| goto error1; |
| } |
| dbgprintf("VideoRAM: %d kByte\n",rhd.videoRam); |
| /* setup the raster pipes */ |
| init_pipes(&rhd); |
| init_gart(&rhd); |
| rhd.FbFreeSize = rhd.videoRam << 10; |
| rhd.FbFreeStart = 10*1024*1024; |
| rhd.FbFreeSize = rhd.FbMapSize - rhd.FbFreeStart - rhd.FbSecureSize; |
| rhdInitHeap(&rhd); |
| info = &rhd; |
| return TRUE; |
| error1: |
| return FALSE; |
| }; |
| static void RADEONPllErrataAfterIndex() |
| { |
| if (!(rhd.ChipErrata & CHIP_ERRATA_PLL_DUMMYREADS)) |
| return; |
| /* This workaround is necessary on rv200 and RS200 or PLL |
| * reads may return garbage (among others...) |
| */ |
| (void)INREG(RADEON_CLOCK_CNTL_DATA); |
| (void)INREG(RADEON_CRTC_GEN_CNTL); |
| } |
| static void RADEONPllErrataAfterData() |
| { |
| /* This function is required to workaround a hardware bug in some (all?) |
| * revisions of the R300. This workaround should be called after every |
| * CLOCK_CNTL_INDEX register access. If not, register reads afterward |
| * may not be correct. |
| */ |
| if (rhd.ChipFamily <= CHIP_FAMILY_RV380) |
| { |
| u32_t save, tmp; |
| save = INREG(RADEON_CLOCK_CNTL_INDEX); |
| tmp = save & ~(0x3f | RADEON_PLL_WR_EN); |
| OUTREG(RADEON_CLOCK_CNTL_INDEX, tmp); |
| tmp = INREG(RADEON_CLOCK_CNTL_DATA); |
| OUTREG(RADEON_CLOCK_CNTL_INDEX, save); |
| } |
| } |
| /* Read PLL register */ |
| static u32_t RADEONINPLL(int addr) |
| { |
| u32_t data; |
| OUTREG8(RADEON_CLOCK_CNTL_INDEX, addr & 0x3f); |
| RADEONPllErrataAfterIndex(); |
| data = INREG(RADEON_CLOCK_CNTL_DATA); |
| RADEONPllErrataAfterData(); |
| return data; |
| }; |
| /* Write PLL information */ |
| static void RADEONOUTPLL(int addr, u32_t data) |
| { |
| OUTREG8(RADEON_CLOCK_CNTL_INDEX, (((addr) & 0x3f) | |
| RADEON_PLL_WR_EN)); |
| RADEONPllErrataAfterIndex(); |
| OUTREG(RADEON_CLOCK_CNTL_DATA, data); |
| RADEONPllErrataAfterData(); |
| } |
| static void init_pipes(RHDPtr info) |
| { |
| u32_t gb_tile_config = 0; |
| if ( (info->ChipFamily == CHIP_FAMILY_RV410) || |
| (info->ChipFamily == CHIP_FAMILY_R420) || |
| (info->ChipFamily == CHIP_FAMILY_RS600) || |
| (info->ChipFamily == CHIP_FAMILY_RS690) || |
| (info->ChipFamily == CHIP_FAMILY_RS740) || |
| (info->ChipFamily == CHIP_FAMILY_RS400) || |
| (info->ChipFamily == CHIP_FAMILY_RS480) || IS_R500_3D) |
| { |
| u32_t gb_pipe_sel = INREG(R400_GB_PIPE_SELECT); |
| info->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1; |
| if (IS_R500_3D) |
| OUTPLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4)); |
| } |
| else |
| { |
| if ((info->ChipFamily == CHIP_FAMILY_R300) || |
| (info->ChipFamily == CHIP_FAMILY_R350)) |
| { |
| /* R3xx chips */ |
| info->num_gb_pipes = 2; |
| } |
| else { |
| /* RV3xx chips */ |
| info->num_gb_pipes = 1; |
| } |
| } |
| if (IS_R300_3D || IS_R500_3D) |
| { |
| dbgprintf("num quad-pipes is %d\n", info->num_gb_pipes); |
| switch(info->num_gb_pipes) { |
| case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break; |
| case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break; |
| case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break; |
| default: |
| case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break; |
| } |
| OUTREG(R300_GB_TILE_CONFIG, gb_tile_config); |
| OUTREG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); |
| OUTREG(R300_DST_PIPE_CONFIG, INREG(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG); |
| OUTREG(R300_RB2D_DSTCACHE_MODE, (INREG(R300_RB2D_DSTCACHE_MODE) | |
| R300_DC_AUTOFLUSH_ENABLE | |
| R300_DC_DC_DISABLE_IGNORE_PE)); |
| } |
| else |
| OUTREG(RADEON_RB3D_CNTL, 0); |
| }; |
| #define RADEON_AIC_PT_BASE 0x01d8 |
| #define RADEON_AIC_LO_ADDR 0x01dc |
| #define RADEON_AIC_HI_ADDR 0x01e0 |
| #define RADEON_AIC_TLB_ADDR 0x01e4 |
| #define RADEON_AIC_TLB_DATA 0x01e8 |
| #define RADEON_PCIE_INDEX 0x0030 |
| #define RADEON_PCIE_DATA 0x0034 |
| #define RADEON_PCIE_TX_GART_CNTL 0x10 |
| # define RADEON_PCIE_TX_GART_EN (1 << 0) |
| # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1) |
| # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1 << 1) |
| # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3 << 1) |
| # define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0 << 3) |
| # define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1 << 3) |
| # define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1 << 5) |
| # define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1 << 8) |
| #define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11 |
| #define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12 |
| #define RADEON_PCIE_TX_GART_BASE 0x13 |
| #define RADEON_PCIE_TX_GART_START_LO 0x14 |
| #define RADEON_PCIE_TX_GART_START_HI 0x15 |
| #define RADEON_PCIE_TX_GART_END_LO 0x16 |
| #define RADEON_PCIE_TX_GART_END_HI 0x17 |
| #define RADEON_WRITE8(offset, val) \ |
| *(volatile u8_t*)((addr_t)rhd.MMIOBase + (offset)) = val |
| #define RADEON_WRITE_PCIE( addr, val ) \ |
| do { \ |
| RADEON_WRITE8( RADEON_PCIE_INDEX, \ |
| ((addr) & 0xff)); \ |
| OUTREG( RADEON_PCIE_DATA, (val) ); \ |
| } while (0) |
| static u32_t RADEON_READ_PCIE(int addr) |
| { |
| RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff); |
| return INREG(RADEON_PCIE_DATA); |
| } |
| static void radeon_set_pciegart(RHDPtr info, int on) |
| { |
| u32_t tmp = RADEON_READ_PCIE(RADEON_PCIE_TX_GART_CNTL); |
| if (on) |
| { |
| RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, |
| info->gart_vm_start); |
| RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE, |
| info->gart_table_dma); |
| RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO, |
| info->gart_vm_start); |
| RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO, |
| info->gart_vm_start + info->gart_size - 1); |
| // radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */ |
| OUTREG(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */ |
| RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, |
| RADEON_PCIE_TX_GART_EN); |
| } else { |
| RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, |
| tmp & ~RADEON_PCIE_TX_GART_EN); |
| } |
| } |
| static void radeon_set_pcigart(RHDPtr info, int on) |
| { |
| u32_t tmp; |
| tmp = INREG(RADEON_AIC_CNTL); |
| if( on ) |
| { |
| OUTREG(RADEON_AIC_CNTL, tmp | RADEON_PCIGART_TRANSLATE_EN); |
| /* set PCI GART page-table base address |
| */ |
| OUTREG(RADEON_AIC_PT_BASE, info->gart_table_dma); |
| /* set address range for PCI address translate |
| */ |
| OUTREG(RADEON_AIC_LO_ADDR, info->gart_vm_start); |
| OUTREG(RADEON_AIC_HI_ADDR, info->gart_vm_start |
| + info->gart_size - 1); |
| /* Turn off AGP aperture -- is this required for PCI GART? |
| */ |
| // radeon_write_agp_location(dev_priv, 0xffffffc0); |
| OUTREG(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */ |
| } |
| else OUTREG(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN); |
| } |
| void init_gart(RHDPtr info) |
| { |
| u32_t *pci_gart; |
| count_t pages; |
| info->gart_size = 16*1024*1024; |
| info->gart_vm_start = info->fbLocation + (info->videoRam << 10); |
| if( info->gart_type == RADEON_IS_PCIE) |
| info->gart_table_dma = info->gart_vm_start |
| - RADEON_PCIGART_TABLE_SIZE; |
| else |
| info->gart_table_dma = AllocPages(RADEON_PCIGART_TABLE_SIZE >> 12); |
| if ( ! info->gart_table_dma) { |
| dbgprintf("cannot allocate PCI GART page!\n"); |
| return; |
| } |
| info->gart_table = (u32_t*)MapIoMem(info->gart_table_dma, |
| RADEON_PCIGART_TABLE_SIZE, |
| PG_SW | PG_NOCACHE); |
| if ( ! info->gart_table) { |
| dbgprintf("cannot map PCI GART page!\n"); |
| return; |
| } |
| pci_gart = info->gart_table; |
| memset(pci_gart, 0, RADEON_PCIGART_TABLE_SIZE); |
| __asm__ __volatile( |
| "wbinvd" |
| :::"memory"); |
| if( info->gart_type == RADEON_IS_PCIE) |
| radeon_set_pciegart(info, 1); |
| else |
| radeon_set_pcigart(info, 1); |
| dbgprintf("gart size 0x%x\n", info->gart_size); |
| dbgprintf("gart base 0x%x\n", info->gart_vm_start); |
| dbgprintf("gart table 0x%x\n", info->gart_table); |
| dbgprintf("gart table dma 0x%x\n", info->gart_table_dma); |
| } |
| /drivers/old/ati2d/init_3d.inc |
|---|
| 0,0 → 1,631 |
| /* |
| * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and |
| * VA Linux Systems Inc., Fremont, California. |
| * |
| * All Rights Reserved. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining |
| * a copy of this software and associated documentation files (the |
| * "Software"), to deal in the Software without restriction, including |
| * without limitation on the rights to use, copy, modify, merge, |
| * publish, distribute, sublicense, and/or sell copies of the Software, |
| * and to permit persons to whom the Software is furnished to do so, |
| * subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice (including the |
| * next paragraph) shall be included in all copies or substantial |
| * portions of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR |
| * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
| * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| * DEALINGS IN THE SOFTWARE. |
| */ |
| int Init3DEngine(RHDPtr info) |
| { |
| u32_t gb_tile_config, su_reg_dest, vap_cntl; |
| u32_t *ring; |
| u32_t ifl; |
| // info->texW[0] = info->texH[0] = info->texW[1] = info->texH[1] = 1; |
| ifl = safe_cli(); |
| FIFOWait(64); |
| delay(2); |
| if (IS_R300_3D || IS_R500_3D) { |
| BEGIN_ACCEL(3); |
| OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); |
| OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); |
| OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); |
| FINISH_ACCEL(); |
| gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 | R300_SUBPIXEL_1_16); |
| switch(info->num_gb_pipes) |
| { |
| case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break; |
| case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break; |
| case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break; |
| default: |
| case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break; |
| } |
| BEGIN_ACCEL(5); |
| OUT_ACCEL_REG(R300_GB_TILE_CONFIG, gb_tile_config); |
| OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); |
| OUT_ACCEL_REG(R300_DST_PIPE_CONFIG, R300_PIPE_AUTO_CONFIG); |
| OUT_ACCEL_REG(R300_GB_SELECT, 0); |
| OUT_ACCEL_REG(R300_GB_ENABLE, 0); |
| FINISH_ACCEL(); |
| if (IS_R500_3D) { |
| su_reg_dest = ((1 << info->num_gb_pipes) - 1); |
| BEGIN_ACCEL(2); |
| OUT_ACCEL_REG(R500_SU_REG_DEST, su_reg_dest); |
| OUT_ACCEL_REG(R500_VAP_INDEX_OFFSET, 0); |
| FINISH_ACCEL(); |
| } |
| BEGIN_ACCEL(3); |
| OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); |
| OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); |
| OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); |
| FINISH_ACCEL(); |
| BEGIN_ACCEL(5); |
| OUT_ACCEL_REG(R300_GB_AA_CONFIG, 0); |
| OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); |
| OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); |
| OUT_ACCEL_REG(R300_GB_MSPOS0, ((8 << R300_MS_X0_SHIFT) | |
| (8 << R300_MS_Y0_SHIFT) | |
| (8 << R300_MS_X1_SHIFT) | |
| (8 << R300_MS_Y1_SHIFT) | |
| (8 << R300_MS_X2_SHIFT) | |
| (8 << R300_MS_Y2_SHIFT) | |
| (8 << R300_MSBD0_Y_SHIFT) | |
| (7 << R300_MSBD0_X_SHIFT))); |
| OUT_ACCEL_REG(R300_GB_MSPOS1, ((8 << R300_MS_X3_SHIFT) | |
| (8 << R300_MS_Y3_SHIFT) | |
| (8 << R300_MS_X4_SHIFT) | |
| (8 << R300_MS_Y4_SHIFT) | |
| (8 << R300_MS_X5_SHIFT) | |
| (8 << R300_MS_Y5_SHIFT) | |
| (8 << R300_MSBD1_SHIFT))); |
| FINISH_ACCEL(); |
| BEGIN_ACCEL(5); |
| OUT_ACCEL_REG(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL); |
| OUT_ACCEL_REG(R300_GA_POLY_MODE, R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE); |
| OUT_ACCEL_REG(R300_GA_ROUND_MODE, (R300_GEOMETRY_ROUND_NEAREST | |
| R300_COLOR_ROUND_NEAREST)); |
| OUT_ACCEL_REG(R300_GA_COLOR_CONTROL, (R300_RGB0_SHADING_GOURAUD | |
| R300_ALPHA0_SHADING_GOURAUD | |
| R300_RGB1_SHADING_GOURAUD | |
| R300_ALPHA1_SHADING_GOURAUD | |
| R300_RGB2_SHADING_GOURAUD | |
| R300_ALPHA2_SHADING_GOURAUD | |
| R300_RGB3_SHADING_GOURAUD | |
| R300_ALPHA3_SHADING_GOURAUD)); |
| OUT_ACCEL_REG(R300_GA_OFFSET, 0); |
| FINISH_ACCEL(); |
| BEGIN_ACCEL(5); |
| OUT_ACCEL_REG(R300_SU_TEX_WRAP, 0); |
| OUT_ACCEL_REG(R300_SU_POLY_OFFSET_ENABLE, 0); |
| OUT_ACCEL_REG(R300_SU_CULL_MODE, R300_FACE_NEG); |
| OUT_ACCEL_REG(R300_SU_DEPTH_SCALE, 0x4b7fffff); |
| OUT_ACCEL_REG(R300_SU_DEPTH_OFFSET, 0); |
| FINISH_ACCEL(); |
| /* setup the VAP */ |
| if (info->has_tcl) |
| vap_cntl = ((5 << R300_PVS_NUM_SLOTS_SHIFT) | |
| (5 << R300_PVS_NUM_CNTLRS_SHIFT) | |
| (9 << R300_VF_MAX_VTX_NUM_SHIFT)); |
| else |
| vap_cntl = ((10 << R300_PVS_NUM_SLOTS_SHIFT) | |
| (5 << R300_PVS_NUM_CNTLRS_SHIFT) | |
| (5 << R300_VF_MAX_VTX_NUM_SHIFT)); |
| if (info->ChipFamily == CHIP_FAMILY_RV515) |
| vap_cntl |= (2 << R300_PVS_NUM_FPUS_SHIFT); |
| else if ((info->ChipFamily == CHIP_FAMILY_RV530) || |
| (info->ChipFamily == CHIP_FAMILY_RV560) || |
| (info->ChipFamily == CHIP_FAMILY_RV570)) |
| vap_cntl |= (5 << R300_PVS_NUM_FPUS_SHIFT); |
| else if ((info->ChipFamily == CHIP_FAMILY_RV410) || |
| (info->ChipFamily == CHIP_FAMILY_R420)) |
| vap_cntl |= (6 << R300_PVS_NUM_FPUS_SHIFT); |
| else if ((info->ChipFamily == CHIP_FAMILY_R520) || |
| (info->ChipFamily == CHIP_FAMILY_R580)) |
| vap_cntl |= (8 << R300_PVS_NUM_FPUS_SHIFT); |
| else |
| vap_cntl |= (4 << R300_PVS_NUM_FPUS_SHIFT); |
| if (info->has_tcl) |
| BEGIN_ACCEL(15); |
| else |
| BEGIN_ACCEL(9); |
| OUT_ACCEL_REG(R300_VAP_VTX_STATE_CNTL, 0); |
| OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0); |
| if (info->has_tcl) |
| OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, 0); |
| else |
| OUT_ACCEL_REG(R300_VAP_CNTL_STATUS, R300_PVS_BYPASS); |
| OUT_ACCEL_REG(R300_VAP_CNTL, vap_cntl); |
| OUT_ACCEL_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0); |
| OUT_ACCEL_REG(R300_VAP_VTE_CNTL, R300_VTX_XY_FMT | R300_VTX_Z_FMT); |
| OUT_ACCEL_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0); |
| OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0, |
| ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) | |
| (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) | |
| (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_0_SHIFT) | |
| (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_0_SHIFT) | |
| ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) |
| << R300_WRITE_ENA_0_SHIFT) | |
| (R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) | |
| (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) | |
| (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_1_SHIFT) | |
| (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_1_SHIFT) | |
| ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) |
| << R300_WRITE_ENA_1_SHIFT))); |
| OUT_ACCEL_REG(R300_VAP_PROG_STREAM_CNTL_EXT_1, |
| ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_2_SHIFT) | |
| (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_2_SHIFT) | |
| (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_2_SHIFT) | |
| (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_2_SHIFT) | |
| ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) |
| << R300_WRITE_ENA_2_SHIFT))); |
| if (info->has_tcl) { |
| OUT_ACCEL_REG(R300_VAP_PVS_FLOW_CNTL_OPC, 0); |
| OUT_ACCEL_REG(R300_VAP_GB_VERT_CLIP_ADJ, 0x3f800000); |
| OUT_ACCEL_REG(R300_VAP_GB_VERT_DISC_ADJ, 0x3f800000); |
| OUT_ACCEL_REG(R300_VAP_GB_HORZ_CLIP_ADJ, 0x3f800000); |
| OUT_ACCEL_REG(R300_VAP_GB_HORZ_DISC_ADJ, 0x3f800000); |
| OUT_ACCEL_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE); |
| } |
| FINISH_ACCEL(); |
| /* pre-load the vertex shaders */ |
| if (info->has_tcl) { |
| /* exa mask/Xv bicubic shader program |
| dcl_position v0 |
| dcl_texcoord v1 |
| dcl_texcoord1 v2 |
| mov oPos, v0 |
| mov oT0, v1 |
| mov oT1, v2 */ |
| BEGIN_ACCEL(13); |
| OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 0); |
| /* PVS inst 0 */ |
| OUT_ACCEL_REG (R300_VAP_PVS_VECTOR_DATA_REG, |
| (R300_PVS_DST_OPCODE(R300_VE_ADD) | |
| R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
| R300_PVS_DST_OFFSET(0) | |
| R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
| R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
| OUT_ACCEL_REG (R300_VAP_PVS_VECTOR_DATA_REG, |
| (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
| R300_PVS_SRC_OFFSET(0) | |
| R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
| R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
| R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
| R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
| OUT_ACCEL_REG (R300_VAP_PVS_VECTOR_DATA_REG, |
| (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
| R300_PVS_SRC_OFFSET(0) | |
| R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
| OUT_ACCEL_REG (R300_VAP_PVS_VECTOR_DATA_REG, |
| (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
| R300_PVS_SRC_OFFSET(0) | |
| R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
| /* PVS inst 1 */ |
| OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
| (R300_PVS_DST_OPCODE(R300_VE_ADD) | |
| R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
| R300_PVS_DST_OFFSET(1) | |
| R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
| R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
| OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
| (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
| R300_PVS_SRC_OFFSET(6) | |
| R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
| R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
| R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
| R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
| OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
| (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
| R300_PVS_SRC_OFFSET(6) | |
| R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
| OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
| (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
| R300_PVS_SRC_OFFSET(6) | |
| R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
| /* PVS inst 2 */ |
| OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
| (R300_PVS_DST_OPCODE(R300_VE_ADD) | |
| R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
| R300_PVS_DST_OFFSET(2) | |
| R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
| R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
| OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
| (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
| R300_PVS_SRC_OFFSET(7) | |
| R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
| R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
| R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
| R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
| OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
| (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
| R300_PVS_SRC_OFFSET(7) | |
| R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
| OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
| (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
| R300_PVS_SRC_OFFSET(7) | |
| R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
| FINISH_ACCEL(); |
| BEGIN_ACCEL(9); |
| /* exa no mask instruction |
| dcl_position v0 |
| dcl_texcoord v1 |
| mov oPos, v0 |
| mov oT0, v1 */ |
| OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 3); |
| /* PVS inst 0 */ |
| OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
| (R300_PVS_DST_OPCODE(R300_VE_ADD) | |
| R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
| R300_PVS_DST_OFFSET(0) | |
| R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
| R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
| OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
| (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
| R300_PVS_SRC_OFFSET(0) | |
| R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
| R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
| R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
| R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
| OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
| (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
| R300_PVS_SRC_OFFSET(0) | |
| R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
| OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
| (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
| R300_PVS_SRC_OFFSET(0) | |
| R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
| /* PVS inst 1 */ |
| OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
| (R300_PVS_DST_OPCODE(R300_VE_ADD) | |
| R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
| R300_PVS_DST_OFFSET(1) | |
| R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
| R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
| OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
| (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
| R300_PVS_SRC_OFFSET(6) | |
| R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
| R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
| R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
| R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
| OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
| (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
| R300_PVS_SRC_OFFSET(6) | |
| R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
| OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
| (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
| R300_PVS_SRC_OFFSET(6) | |
| R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
| FINISH_ACCEL(); |
| /* Xv shader program */ |
| BEGIN_ACCEL(9); |
| OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_INDX_REG, 5); |
| OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
| (R300_PVS_DST_OPCODE(R300_VE_ADD) | |
| R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
| R300_PVS_DST_OFFSET(0) | |
| R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
| R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
| OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
| (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
| R300_PVS_SRC_OFFSET(0) | |
| R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
| R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
| R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
| R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
| OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
| (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
| R300_PVS_SRC_OFFSET(0) | |
| R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
| OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
| (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
| R300_PVS_SRC_OFFSET(0) | |
| R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
| OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
| (R300_PVS_DST_OPCODE(R300_VE_ADD) | |
| R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | |
| R300_PVS_DST_OFFSET(1) | |
| R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | |
| R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); |
| OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
| (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
| R300_PVS_SRC_OFFSET(6) | |
| R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | |
| R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | |
| R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | |
| R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_W))); |
| OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
| (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
| R300_PVS_SRC_OFFSET(6) | |
| R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
| OUT_ACCEL_REG(R300_VAP_PVS_VECTOR_DATA_REG, |
| (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | |
| R300_PVS_SRC_OFFSET(6) | |
| R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | |
| R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); |
| FINISH_ACCEL(); |
| } |
| /* pre-load the RS instructions */ |
| BEGIN_ACCEL(4); |
| if (IS_R300_3D) { |
| /* rasterizer source table |
| * R300_RS_TEX_PTR is the offset into the input RS stream |
| * 0,1 are tex0 |
| * 2,3 are tex1 |
| */ |
| OUT_ACCEL_REG(R300_RS_IP_0, |
| (R300_RS_TEX_PTR(0) | |
| R300_RS_SEL_S(R300_RS_SEL_C0) | |
| R300_RS_SEL_T(R300_RS_SEL_C1) | |
| R300_RS_SEL_R(R300_RS_SEL_K0) | |
| R300_RS_SEL_Q(R300_RS_SEL_K1))); |
| OUT_ACCEL_REG(R300_RS_IP_1, |
| (R300_RS_TEX_PTR(2) | |
| R300_RS_SEL_S(R300_RS_SEL_C0) | |
| R300_RS_SEL_T(R300_RS_SEL_C1) | |
| R300_RS_SEL_R(R300_RS_SEL_K0) | |
| R300_RS_SEL_Q(R300_RS_SEL_K1))); |
| /* src tex */ |
| /* R300_INST_TEX_ID - select the RS source table entry |
| * R300_INST_TEX_ADDR - the FS temp register for the texture data |
| */ |
| OUT_ACCEL_REG(R300_RS_INST_0, (R300_INST_TEX_ID(0) | |
| R300_RS_INST_TEX_CN_WRITE | |
| R300_INST_TEX_ADDR(0))); |
| /* mask tex */ |
| OUT_ACCEL_REG(R300_RS_INST_1, (R300_INST_TEX_ID(1) | |
| R300_RS_INST_TEX_CN_WRITE | |
| R300_INST_TEX_ADDR(1))); |
| } else { |
| /* rasterizer source table |
| * R300_RS_TEX_PTR is the offset into the input RS stream |
| * 0,1 are tex0 |
| * 2,3 are tex1 |
| */ |
| OUT_ACCEL_REG(R500_RS_IP_0, ((0 << R500_RS_IP_TEX_PTR_S_SHIFT) | |
| (1 << R500_RS_IP_TEX_PTR_T_SHIFT) | |
| (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | |
| (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT))); |
| OUT_ACCEL_REG(R500_RS_IP_1, ((2 << R500_RS_IP_TEX_PTR_S_SHIFT) | |
| (3 << R500_RS_IP_TEX_PTR_T_SHIFT) | |
| (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | |
| (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT))); |
| /* src tex */ |
| /* R500_RS_INST_TEX_ID_SHIFT - select the RS source table entry |
| * R500_RS_INST_TEX_ADDR_SHIFT - the FS temp register for the texture data |
| */ |
| OUT_ACCEL_REG(R500_RS_INST_0, ((0 << R500_RS_INST_TEX_ID_SHIFT) | |
| R500_RS_INST_TEX_CN_WRITE | |
| (0 << R500_RS_INST_TEX_ADDR_SHIFT))); |
| /* mask tex */ |
| OUT_ACCEL_REG(R500_RS_INST_1, ((1 << R500_RS_INST_TEX_ID_SHIFT) | |
| R500_RS_INST_TEX_CN_WRITE | |
| (1 << R500_RS_INST_TEX_ADDR_SHIFT))); |
| } |
| FINISH_ACCEL(); |
| if (IS_R300_3D) |
| BEGIN_ACCEL(4); |
| else { |
| BEGIN_ACCEL(6); |
| OUT_ACCEL_REG(R300_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO); |
| OUT_ACCEL_REG(R500_US_FC_CTRL, 0); |
| } |
| OUT_ACCEL_REG(R300_US_W_FMT, 0); |
| OUT_ACCEL_REG(R300_US_OUT_FMT_1, (R300_OUT_FMT_UNUSED | |
| R300_OUT_FMT_C0_SEL_BLUE | |
| R300_OUT_FMT_C1_SEL_GREEN | |
| R300_OUT_FMT_C2_SEL_RED | |
| R300_OUT_FMT_C3_SEL_ALPHA)); |
| OUT_ACCEL_REG(R300_US_OUT_FMT_2, (R300_OUT_FMT_UNUSED | |
| R300_OUT_FMT_C0_SEL_BLUE | |
| R300_OUT_FMT_C1_SEL_GREEN | |
| R300_OUT_FMT_C2_SEL_RED | |
| R300_OUT_FMT_C3_SEL_ALPHA)); |
| OUT_ACCEL_REG(R300_US_OUT_FMT_3, (R300_OUT_FMT_UNUSED | |
| R300_OUT_FMT_C0_SEL_BLUE | |
| R300_OUT_FMT_C1_SEL_GREEN | |
| R300_OUT_FMT_C2_SEL_RED | |
| R300_OUT_FMT_C3_SEL_ALPHA)); |
| FINISH_ACCEL(); |
| BEGIN_ACCEL(3); |
| OUT_ACCEL_REG(R300_FG_DEPTH_SRC, 0); |
| OUT_ACCEL_REG(R300_FG_FOG_BLEND, 0); |
| OUT_ACCEL_REG(R300_FG_ALPHA_FUNC, 0); |
| FINISH_ACCEL(); |
| BEGIN_ACCEL(13); |
| OUT_ACCEL_REG(R300_RB3D_ABLENDCNTL, 0); |
| OUT_ACCEL_REG(R300_RB3D_ZSTENCILCNTL, 0); |
| OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); |
| OUT_ACCEL_REG(R300_RB3D_BW_CNTL, 0); |
| OUT_ACCEL_REG(R300_RB3D_ZCNTL, 0); |
| OUT_ACCEL_REG(R300_RB3D_ZTOP, 0); |
| OUT_ACCEL_REG(R300_RB3D_ROPCNTL, 0); |
| OUT_ACCEL_REG(R300_RB3D_AARESOLVE_CTL, 0); |
| OUT_ACCEL_REG(R300_RB3D_COLOR_CHANNEL_MASK, (R300_BLUE_MASK_EN | |
| R300_GREEN_MASK_EN | |
| R300_RED_MASK_EN | |
| R300_ALPHA_MASK_EN)); |
| OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); |
| OUT_ACCEL_REG(R300_RB3D_CCTL, 0); |
| OUT_ACCEL_REG(R300_RB3D_DITHER_CTL, 0); |
| OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); |
| FINISH_ACCEL(); |
| BEGIN_ACCEL(5); |
| OUT_ACCEL_REG(R300_SC_EDGERULE, 0xA5294A5); |
| if (IS_R300_3D) { |
| /* clip has offset 1440 */ |
| OUT_ACCEL_REG(R300_SC_CLIP_0_A, ((1088 << R300_CLIP_X_SHIFT) | |
| (1088 << R300_CLIP_Y_SHIFT))); |
| OUT_ACCEL_REG(R300_SC_CLIP_0_B, (((1080 + 2920) << R300_CLIP_X_SHIFT) | |
| ((1080 + 2920) << R300_CLIP_Y_SHIFT))); |
| } else { |
| OUT_ACCEL_REG(R300_SC_CLIP_0_A, ((0 << R300_CLIP_X_SHIFT) | |
| (0 << R300_CLIP_Y_SHIFT))); |
| OUT_ACCEL_REG(R300_SC_CLIP_0_B, ((4080 << R300_CLIP_X_SHIFT) | |
| (4080 << R300_CLIP_Y_SHIFT))); |
| } |
| OUT_ACCEL_REG(R300_SC_CLIP_RULE, 0xAAAA); |
| OUT_ACCEL_REG(R300_SC_SCREENDOOR, 0xffffff); |
| FINISH_ACCEL(); |
| } else if ((info->ChipFamily == CHIP_FAMILY_RV250) || |
| (info->ChipFamily == CHIP_FAMILY_RV280) || |
| (info->ChipFamily == CHIP_FAMILY_RS300) || |
| (info->ChipFamily == CHIP_FAMILY_R200)) { |
| BEGIN_ACCEL(6); |
| if (info->ChipFamily == CHIP_FAMILY_RS300) { |
| OUT_ACCEL_REG(R200_SE_VAP_CNTL_STATUS, RADEON_TCL_BYPASS); |
| } else { |
| OUT_ACCEL_REG(R200_SE_VAP_CNTL_STATUS, 0); |
| } |
| OUT_ACCEL_REG(R200_PP_CNTL_X, 0); |
| OUT_ACCEL_REG(R200_PP_TXMULTI_CTL_0, 0); |
| OUT_ACCEL_REG(R200_SE_VTX_STATE_CNTL, 0); |
| OUT_ACCEL_REG(R200_SE_VTE_CNTL, 0); |
| OUT_ACCEL_REG(R200_SE_VAP_CNTL, R200_VAP_FORCE_W_TO_ONE | |
| R200_VAP_VF_MAX_VTX_NUM); |
| FINISH_ACCEL(); |
| BEGIN_ACCEL(5); |
| OUT_ACCEL_REG(RADEON_RE_TOP_LEFT, 0); |
| OUT_ACCEL_REG(RADEON_RE_WIDTH_HEIGHT, 0x07ff07ff); |
| OUT_ACCEL_REG(RADEON_AUX_SC_CNTL, 0); |
| OUT_ACCEL_REG(RADEON_RB3D_PLANEMASK, 0xffffffff); |
| OUT_ACCEL_REG(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD | |
| RADEON_BFACE_SOLID | |
| RADEON_FFACE_SOLID | |
| RADEON_VTX_PIX_CENTER_OGL | |
| RADEON_ROUND_MODE_ROUND | |
| RADEON_ROUND_PREC_4TH_PIX)); |
| FINISH_ACCEL(); |
| } else { |
| BEGIN_ACCEL(2); |
| if ((info->ChipFamily == CHIP_FAMILY_RADEON) || |
| (info->ChipFamily == CHIP_FAMILY_RV200)) |
| OUT_ACCEL_REG(RADEON_SE_CNTL_STATUS, 0); |
| else |
| OUT_ACCEL_REG(RADEON_SE_CNTL_STATUS, RADEON_TCL_BYPASS); |
| OUT_ACCEL_REG(RADEON_SE_COORD_FMT, |
| RADEON_VTX_XY_PRE_MULT_1_OVER_W0 | |
| RADEON_VTX_ST0_NONPARAMETRIC | |
| RADEON_VTX_ST1_NONPARAMETRIC | |
| RADEON_TEX1_W_ROUTING_USE_W0); |
| FINISH_ACCEL(); |
| BEGIN_ACCEL(5); |
| OUT_ACCEL_REG(RADEON_RE_TOP_LEFT, 0); |
| OUT_ACCEL_REG(RADEON_RE_WIDTH_HEIGHT, 0x07ff07ff); |
| OUT_ACCEL_REG(RADEON_AUX_SC_CNTL, 0); |
| OUT_ACCEL_REG(RADEON_RB3D_PLANEMASK, 0xffffffff); |
| OUT_ACCEL_REG(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD | |
| RADEON_BFACE_SOLID | |
| RADEON_FFACE_SOLID | |
| RADEON_VTX_PIX_CENTER_OGL | |
| RADEON_ROUND_MODE_ROUND | |
| RADEON_ROUND_PREC_4TH_PIX)); |
| FINISH_ACCEL(); |
| } |
| safe_sti(ifl); |
| FIFOWait(64); |
| delay(2); |
| } |
| /drivers/old/ati2d/init_cp.c |
|---|
| 0,0 → 1,328 |
| #define RADEON_SCRATCH_REG0 0x15e0 |
| #define RADEON_SCRATCH_REG1 0x15e4 |
| #define RADEON_SCRATCH_REG2 0x15e8 |
| #define RADEON_SCRATCH_REG3 0x15ec |
| #define RADEON_SCRATCH_REG4 0x15f0 |
| #define RADEON_SCRATCH_REG5 0x15f4 |
| #define RADEON_SCRATCH_UMSK 0x0770 |
| #define RADEON_SCRATCH_ADDR 0x0774 |
| # define RS400_BUS_MASTER_DIS (1 << 14) |
| //# define RADEON_BUS_MASTER_DIS (1 << 6) |
| #define RADEON_ISYNC_CNTL 0x1724 |
| # define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0) |
| # define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1) |
| # define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2) |
| # define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3) |
| # define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4) |
| # define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5) |
| void RADEONEngineFlush(RHDPtr info) |
| { |
| int i; |
| if (info->ChipFamily <= CHIP_FAMILY_RV280) |
| { |
| MASKREG(RADEON_RB3D_DSTCACHE_CTLSTAT,RADEON_RB3D_DC_FLUSH_ALL, |
| ~RADEON_RB3D_DC_FLUSH_ALL); |
| for (i = 0; i < RADEON_TIMEOUT; i++) { |
| if (!(INREG(RADEON_RB3D_DSTCACHE_CTLSTAT) & RADEON_RB3D_DC_BUSY)) |
| break; |
| } |
| if (i == RADEON_TIMEOUT) { |
| dbgprintf("DC flush timeout: %x\n", |
| (u32_t)INREG(RADEON_RB3D_DSTCACHE_CTLSTAT)); |
| } |
| } |
| else |
| { |
| // MASKREG(R300_DSTCACHE_CTLSTAT,R300_RB2D_DC_FLUSH_ALL, |
| // ~R300_RB2D_DC_FLUSH_ALL); |
| // for (i = 0; i < RADEON_TIMEOUT; i++) { |
| // if (!(INREG(R300_DSTCACHE_CTLSTAT) & R300_RB2D_DC_BUSY)) |
| // break; |
| // } |
| // if (i == RADEON_TIMEOUT) { |
| // dbgprintf("DC flush timeout: %x\n", |
| // (u32_t)INREG(R300_DSTCACHE_CTLSTAT)); |
| // } |
| } |
| } |
| static int radeon_do_wait_for_idle() |
| { |
| int i, ret; |
| ret = R5xxFIFOWaitLocal(64); |
| if (ret) |
| return ret; |
| for (i = 0; i < RADEON_TIMEOUT; i++) |
| { |
| if (!(INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)) { |
| RADEONEngineFlush(&rhd); |
| return 0; |
| } |
| usleep(1); |
| } |
| dbgprintf("wait idle failed status : 0x%08X 0x%08X\n", |
| INREG(RADEON_RBBM_STATUS), |
| INREG(R300_VAP_CNTL_STATUS)); |
| return 1; |
| } |
| /* ================================================================ |
| * CP control, initialization |
| */ |
| /* Load the microcode for the CP */ |
| #include "radeon_microcode.h" |
| static void load_microcode(RHDPtr info) |
| { |
| int i; |
| const u32_t (*microcode)[2]; |
| OUTREG(RADEON_CP_ME_RAM_ADDR, 0); |
| if ( (info->ChipFamily == CHIP_FAMILY_LEGACY ) || |
| (info->ChipFamily == CHIP_FAMILY_RADEON ) || |
| (info->ChipFamily == CHIP_FAMILY_RV100 ) || |
| (info->ChipFamily == CHIP_FAMILY_RV200 ) || |
| (info->ChipFamily == CHIP_FAMILY_RS100 ) || |
| (info->ChipFamily == CHIP_FAMILY_RS200 )) |
| { |
| microcode = R100_cp_microcode; |
| dbgprintf("Loading R100 Microcode\n"); |
| } |
| else if ((info->ChipFamily == CHIP_FAMILY_R200 ) || |
| (info->ChipFamily == CHIP_FAMILY_RV250) || |
| (info->ChipFamily == CHIP_FAMILY_RV280) || |
| (info->ChipFamily == CHIP_FAMILY_RS300)) |
| { |
| microcode = R200_cp_microcode; |
| dbgprintf("Loading R200 Microcode\n"); |
| } |
| else if ((info->ChipFamily == CHIP_FAMILY_R300) || |
| (info->ChipFamily == CHIP_FAMILY_R350) || |
| (info->ChipFamily == CHIP_FAMILY_RV350) || |
| (info->ChipFamily == CHIP_FAMILY_RV380) || |
| (info->ChipFamily == CHIP_FAMILY_RS400) || |
| (info->ChipFamily == CHIP_FAMILY_RS480)) |
| { |
| dbgprintf("Loading R300 Microcode\n"); |
| microcode = R300_cp_microcode; |
| } |
| else if ((info->ChipFamily == CHIP_FAMILY_R420) || |
| (info->ChipFamily == CHIP_FAMILY_RV410)) |
| { |
| dbgprintf("Loading R400 Microcode\n"); |
| microcode = R420_cp_microcode; |
| } |
| else if ((info->ChipFamily == CHIP_FAMILY_RS600) || |
| (info->ChipFamily == CHIP_FAMILY_RS690) || |
| (info->ChipFamily == CHIP_FAMILY_RS740)) |
| { |
| dbgprintf("Loading RS690/RS740 Microcode\n"); |
| microcode = RS690_cp_microcode; |
| } |
| else if ((info->ChipFamily == CHIP_FAMILY_RV515) || |
| (info->ChipFamily == CHIP_FAMILY_R520) || |
| (info->ChipFamily == CHIP_FAMILY_RV530) || |
| (info->ChipFamily == CHIP_FAMILY_R580) || |
| (info->ChipFamily == CHIP_FAMILY_RV560) || |
| (info->ChipFamily == CHIP_FAMILY_RV570)) |
| { |
| dbgprintf("Loading R500 Microcode\n"); |
| microcode = R520_cp_microcode; |
| } |
| for (i = 0; i < 256; i++) { |
| OUTREG(RADEON_CP_ME_RAM_DATAH, microcode[i][1]); |
| OUTREG(RADEON_CP_ME_RAM_DATAL, microcode[i][0]); |
| } |
| } |
| void init_ring_buffer(RHDPtr info) |
| { |
| u32_t ring_base; |
| u32_t tmp; |
| info->ringBase = CreateRingBuffer( 64*1024, PG_SW); |
| dbgprintf("create cp ring buffer %x\n", rhd.ringBase); |
| ring_base = GetPgAddr(rhd.ringBase); |
| dbgprintf("ring base %x\n", ring_base); |
| OUTREG(RADEON_CP_RB_BASE, ring_base); |
| info->ring_avail = 64*1024/4 ; |
| /* Set the write pointer delay */ |
| OUTREG(RADEON_CP_RB_WPTR_DELAY, 0); |
| /* Initialize the ring buffer's read and write pointers */ |
| rhd.ring_rp = rhd.ring_wp = INREG(RADEON_CP_RB_RPTR); |
| rhd.host_rp = rhd.ring_rp; |
| OUTREG(RADEON_CP_RB_WPTR,rhd.ring_rp); |
| tmp = (((u32_t)&rhd.host_rp) & 4095) + GetPgAddr((void*)&rhd.host_rp); |
| OUTREG(RADEON_CP_RB_RPTR_ADDR, tmp); // ring buffer read pointer |
| /* Set ring buffer size */ |
| OUTREG(RADEON_CP_RB_CNTL, (1<<27)|(0<<18)|(10<<8)|13); |
| /* Initialize the scratch register pointer. This will cause |
| * the scratch register values to be written out to memory |
| * whenever they are updated. |
| * |
| * We simply put this behind the ring read pointer, this works |
| * with PCI GART as well as (whatever kind of) AGP GART |
| */ |
| tmp = (((u32_t)&rhd.scratch0) & 4095) + GetPgAddr((void*)&rhd.scratch0); |
| OUTREG(RADEON_SCRATCH_ADDR, tmp); |
| OUTREG(RADEON_SCRATCH_UMSK, 0x0); |
| //OUTREG(0x778, 1); |
| /* Turn on bus mastering */ |
| if ( (info->ChipFamily == CHIP_FAMILY_RS400) || |
| (info->ChipFamily == CHIP_FAMILY_RS690) || |
| (info->ChipFamily == CHIP_FAMILY_RS740) ) |
| { |
| /* rs400, rs690/rs740 */ |
| tmp = INREG(RADEON_BUS_CNTL) & ~RS400_BUS_MASTER_DIS; |
| OUTREG(RADEON_BUS_CNTL, tmp); |
| } |
| else if (!((info->ChipFamily == CHIP_FAMILY_RV380) || |
| (info->ChipFamily >= CHIP_FAMILY_R420))) |
| { |
| /* r1xx, r2xx, r300, r(v)350, r420/r481, rs480 */ |
| tmp = INREG(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; |
| OUTREG(RADEON_BUS_CNTL, tmp); |
| } /* PCIE cards appears to not need this */ |
| tmp = INREG(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; |
| OUTREG(RADEON_BUS_CNTL, tmp); |
| radeon_do_wait_for_idle(); |
| /* Sync everything up */ |
| OUTREG(RADEON_ISYNC_CNTL, |
| (RADEON_ISYNC_ANY2D_IDLE3D | |
| RADEON_ISYNC_ANY3D_IDLE2D | |
| RADEON_ISYNC_WAIT_IDLEGUI | |
| RADEON_ISYNC_CPSCRATCH_IDLEGUI)); |
| } |
| #define RADEON_WAIT_UNTIL_IDLE() do { \ |
| OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 1 ) ); \ |
| OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ |
| RADEON_WAIT_3D_IDLECLEAN | \ |
| RADEON_WAIT_HOST_IDLECLEAN) ); \ |
| } while (0) |
| #define R300_ZB_ZCACHE_CTLSTAT 0x4f18 |
| # define RADEON_RB3D_ZC_FLUSH (1 << 0) |
| # define RADEON_RB3D_ZC_FREE (1 << 2) |
| # define RADEON_RB3D_ZC_FLUSH_ALL 0x5 |
| # define RADEON_RB3D_ZC_BUSY (1 << 31) |
| # define R300_ZC_FLUSH (1 << 0) |
| # define R300_ZC_FREE (1 << 1) |
| # define R300_ZC_BUSY (1 << 31) |
| # define RADEON_RB3D_DC_FLUSH (3 << 0) |
| # define RADEON_RB3D_DC_FREE (3 << 2) |
| # define RADEON_RB3D_DC_FLUSH_ALL 0xf |
| # define RADEON_RB3D_DC_BUSY (1 << 31) |
| # define R300_RB3D_DC_FLUSH (2 << 0) |
| # define R300_RB3D_DC_FREE (2 << 2) |
| # |
| #define RADEON_PURGE_CACHE() do { \ |
| if ( rhd.ChipFamily <= CHIP_FAMILY_RV280) { \ |
| OUT_RING(CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 1)); \ |
| OUT_RING(RADEON_RB3D_DC_FLUSH | RADEON_RB3D_DC_FREE); \ |
| } else { \ |
| OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 1)); \ |
| OUT_RING(R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE ); \ |
| } \ |
| } while (0) |
| #define RADEON_FLUSH_ZCACHE() do { \ |
| if ( rhd.ChipFamily <= CHIP_FAMILY_RV280) { \ |
| OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 1 ) ); \ |
| OUT_RING( RADEON_RB3D_ZC_FLUSH ); \ |
| } else { \ |
| OUT_RING( CP_PACKET0( R300_ZB_ZCACHE_CTLSTAT, 1 ) ); \ |
| OUT_RING( R300_ZC_FLUSH ); \ |
| } \ |
| } while (0) |
| #define RADEON_PURGE_ZCACHE() do { \ |
| if (rhd.ChipFamily <= CHIP_FAMILY_RV280) { \ |
| OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 1)); \ |
| OUT_RING(RADEON_RB3D_ZC_FLUSH | RADEON_RB3D_ZC_FREE); \ |
| } else { \ |
| OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 1)); \ |
| OUT_RING(R300_ZC_FLUSH | R300_ZC_FREE); \ |
| } \ |
| } while (0) |
| static int radeon_cp_start(RHDPtr info) |
| { |
| u32_t *ring, write; |
| u32_t ifl; |
| radeon_do_wait_for_idle(64); |
| OUTREG(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM); |
| ifl = safe_cli(); |
| BEGIN_RING(8); |
| /* isync can only be written through cp on r5xx write it here */ |
| OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 1)); |
| OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D | |
| RADEON_ISYNC_ANY3D_IDLE2D | |
| RADEON_ISYNC_WAIT_IDLEGUI | |
| RADEON_ISYNC_CPSCRATCH_IDLEGUI); |
| RADEON_PURGE_CACHE(); |
| RADEON_PURGE_ZCACHE(); |
| RADEON_WAIT_UNTIL_IDLE(); |
| ADVANCE_RING(); |
| COMMIT_RING(); |
| safe_sti(ifl); |
| radeon_do_wait_for_idle(); |
| }; |
| Bool init_cp(RHDPtr info) |
| { |
| load_microcode(&rhd); |
| init_ring_buffer(&rhd); |
| radeon_engine_reset(&rhd); |
| rhd.ring_rp = rhd.ring_wp = INREG(RADEON_CP_RB_RPTR); |
| OUTREG(RADEON_CP_RB_WPTR, rhd.ring_rp); |
| radeon_cp_start(&rhd); |
| return TRUE; |
| }; |
| /drivers/old/ati2d/makefile |
|---|
| 0,0 → 1,56 |
| CC = gcc |
| FASM = e:/fasm/fasm.exe |
| CFLAGS = -c -O2 -fomit-frame-pointer -fno-builtin-printf |
| LDRHD = -shared -T ld.x -s --file-alignment 32 |
| INCLUDES = -I ../../include |
| HFILES:= ../../include/types.h \ |
| ../../include/syscall.h \ |
| ../../include/pci.h \ |
| atihw.h \ |
| accel_2d.h \ |
| r5xx_regs.h \ |
| radeon_microcode.h |
| SRC_DEP:= init.c \ |
| pci.c \ |
| ati_mem.c \ |
| init_cp.c \ |
| init_3d.inc \ |
| blend.inc \ |
| r500.inc \ |
| pixmap.inc \ |
| accel_2d.inc |
| ATI_SRC:= ati2d.c |
| ATI_OBJ:= ati2d.obj |
| ATI_OBJ = $(patsubst %.s, %.obj, $(patsubst %.asm, %.obj,\ |
| $(patsubst %.c, %.obj, $(ATI_SRC)))) |
| ATI2D = ati2d.dll |
| all: $(ATI2D) |
| $(ATI2D): $(ATI_OBJ) $(SRC_DEP) $(HFILES) Makefile |
| wlink name ati2d.dll SYS nt_dll lib libdrv op offset=0 op nod op maxe=25 op el op STUB=stub.exe op START=_drvEntry @ati2d.lk |
| kpack.exe ati2d.dll ati2d.drv |
| ati2d.obj : ati2d.c $(SRC_DEP) $(HFILES) Makefile |
| $(CC) $(INCLUDES) $(CFLAGS) -o ati2d.obj ati2d.c |
| curhelp.obj : curhelp.asm |
| $(FASM) curhelp.asm |
| %.obj : %.c $(HFILES) |
| $(CC) $(CFLAGS) -o $@ $< |
| %.obj: %.asm |
| as -o $@ $< |
| /drivers/old/ati2d/pci.c |
|---|
| 0,0 → 1,288 |
| #include "ati_pciids_gen.h" |
| #include "radeon_chipset_gen.h" |
| #include "radeon_chipinfo_gen.h" |
| const char * |
| xf86TokenToString(SymTabPtr table, int token) |
| { |
| int i; |
| for (i = 0; table[i].token >= 0 && table[i].token != token; i++){}; |
| if (table[i].token < 0) |
| return NULL; |
| else |
| return(table[i].name); |
| } |
| const RADEONCardInfo *RadeonDevMatch(u16_t dev,const RADEONCardInfo *list) |
| { |
| while(list->pci_device_id) |
| { |
| if(dev == list->pci_device_id) |
| return list; |
| list++; |
| } |
| return 0; |
| } |
| RHDPtr FindPciDevice() |
| { |
| const RADEONCardInfo *dev; |
| u32_t bus, last_bus; |
| if( (last_bus = PciApi(1))==-1) |
| return 0; |
| for(bus=0;bus<=last_bus;bus++) |
| { |
| u32_t devfn; |
| for(devfn=0;devfn<256;devfn++) |
| { |
| u32_t id; |
| id = PciRead32(bus,devfn, 0); |
| if( (u16_t)id != VENDOR_ATI) |
| continue; |
| rhd.PciDeviceID = (id>>16); |
| if( (dev = RadeonDevMatch(rhd.PciDeviceID, RADEONCards))!=NULL) |
| { |
| u32_t reg2C; |
| int i; |
| rhd.chipset = (char*)xf86TokenToString(RADEONChipsets, rhd.PciDeviceID); |
| if (!rhd.chipset){ |
| dbgprintf("ChipID 0x%04x is not recognized\n", rhd.PciDeviceID); |
| return FALSE; |
| } |
| dbgprintf("Chipset: \"%s\" (ChipID = 0x%04x)\n", |
| rhd.chipset,rhd.PciDeviceID); |
| rhd.bus = bus; |
| rhd.devfn = devfn; |
| rhd.PciTag = pciTag(bus,(devfn>>3)&0x1F,devfn&0x7); |
| rhd.ChipFamily = dev->chip_family; |
| rhd.IsMobility = dev->mobility; |
| rhd.IsIGP = dev->igp; |
| rhd.HasCRTC2 = !dev->nocrtc2; |
| reg2C = PciRead32(bus,devfn, 0x2C); |
| rhd.subvendor_id = reg2C & 0xFFFF;; |
| rhd.subdevice_id = reg2C >> 16; |
| if (rhd.ChipFamily >= CHIP_FAMILY_R600) |
| dbgprintf("R600 unsupported yet.\nExit\n"); |
| if( rhd.ChipFamily >= CHIP_FAMILY_R420) |
| rhd.gart_type = RADEON_IS_PCIE; |
| else |
| rhd.gart_type = RADEON_IS_PCI; |
| for (i = 0; i < 6; i++) |
| { |
| u32_t base; |
| Bool validSize; |
| base = PciRead32(bus,devfn, PCI_MAP_REG_START + (i << 2)); |
| if(base) |
| { |
| if (base & PCI_MAP_IO){ |
| rhd.ioBase[i] = (u32_t)PCIGETIO(base); |
| rhd.memtype[i] = base & PCI_MAP_IO_ATTR_MASK; |
| } |
| else{ |
| rhd.memBase[i] = (u32_t)PCIGETMEMORY(base); |
| rhd.memtype[i] = base & PCI_MAP_MEMORY_ATTR_MASK; |
| } |
| } |
| rhd.memsize[i] = pciGetBaseSize(bus,devfn, i, TRUE, &validSize); |
| } |
| return &rhd; |
| } |
| } |
| }; |
| return NULL; |
| } |
| u32_t pciGetBaseSize(int bus, int devfn, int index, Bool destructive, Bool *min) |
| { |
| int offset; |
| u32_t addr1; |
| u32_t addr2; |
| u32_t mask1; |
| u32_t mask2; |
| int bits = 0; |
| /* |
| * silently ignore bogus index values. Valid values are 0-6. 0-5 are |
| * the 6 base address registers, and 6 is the ROM base address register. |
| */ |
| if (index < 0 || index > 6) |
| return 0; |
| if (min) |
| *min = destructive; |
| /* Get the PCI offset */ |
| if (index == 6) |
| offset = PCI_MAP_ROM_REG; |
| else |
| offset = PCI_MAP_REG_START + (index << 2); |
| addr1 = PciRead32(bus, devfn, offset); |
| /* |
| * Check if this is the second part of a 64 bit address. |
| * XXX need to check how endianness affects 64 bit addresses. |
| */ |
| if (index > 0 && index < 6) { |
| addr2 = PciRead32(bus, devfn, offset - 4); |
| if (PCI_MAP_IS_MEM(addr2) && PCI_MAP_IS64BITMEM(addr2)) |
| return 0; |
| } |
| if (destructive) { |
| PciWrite32(bus, devfn, offset, 0xffffffff); |
| mask1 = PciRead32(bus, devfn, offset); |
| PciWrite32(bus, devfn, offset, addr1); |
| } else { |
| mask1 = addr1; |
| } |
| /* Check if this is the first part of a 64 bit address. */ |
| if (index < 5 && PCI_MAP_IS_MEM(mask1) && PCI_MAP_IS64BITMEM(mask1)) |
| { |
| if (PCIGETMEMORY(mask1) == 0) |
| { |
| addr2 = PciRead32(bus, devfn, offset + 4); |
| if (destructive) |
| { |
| PciWrite32(bus, devfn, offset + 4, 0xffffffff); |
| mask2 = PciRead32(bus, devfn, offset + 4); |
| PciWrite32(bus, devfn, offset + 4, addr2); |
| } |
| else |
| { |
| mask2 = addr2; |
| } |
| if (mask2 == 0) |
| return 0; |
| bits = 32; |
| while ((mask2 & 1) == 0) |
| { |
| bits++; |
| mask2 >>= 1; |
| } |
| if (bits > 32) |
| return bits; |
| } |
| } |
| if (index < 6) |
| if (PCI_MAP_IS_MEM(mask1)) |
| mask1 = PCIGETMEMORY(mask1); |
| else |
| mask1 = PCIGETIO(mask1); |
| else |
| mask1 = PCIGETROM(mask1); |
| if (mask1 == 0) |
| return 0; |
| bits = 0; |
| while ((mask1 & 1) == 0) { |
| bits++; |
| mask1 >>= 1; |
| } |
| /* I/O maps can be no larger than 8 bits */ |
| if ((index < 6) && PCI_MAP_IS_IO(addr1) && bits > 8) |
| bits = 8; |
| /* ROM maps can be no larger than 24 bits */ |
| if (index == 6 && bits > 24) |
| bits = 24; |
| return bits; |
| } |
| #define PCI_FIND_CAP_TTL 48 |
| static int __pci_find_next_cap_ttl(PCITAG pciTag, u8_t pos, |
| int cap, int *ttl) |
| { |
| u8_t id; |
| while ((*ttl)--) |
| { |
| pos = pciReadByte(pciTag, pos); |
| if (pos < 0x40) |
| break; |
| pos &= ~3; |
| id = pciReadByte(pciTag, pos + PCI_CAP_LIST_ID); |
| if (id == 0xff) |
| break; |
| if (id == cap) |
| return pos; |
| pos += PCI_CAP_LIST_NEXT; |
| } |
| return 0; |
| } |
| static int __pci_find_next_cap(PCITAG pciTag, u8_t pos, int cap) |
| { |
| int ttl = PCI_FIND_CAP_TTL; |
| return __pci_find_next_cap_ttl(pciTag, pos, cap, &ttl); |
| } |
| static int __pci_bus_find_cap_start(PCITAG pciTag) |
| { |
| u16_t status; |
| u8_t hdr_type; |
| status = pciReadWord(pciTag, PCI_STATUS); |
| if (!(status & PCI_STATUS_CAP_LIST)) |
| return 0; |
| hdr_type = pciReadByte(pciTag, 0x0E); |
| switch (hdr_type) |
| { |
| case PCI_HEADER_TYPE_NORMAL: |
| case PCI_HEADER_TYPE_BRIDGE: |
| return PCI_CAPABILITY_LIST; |
| case PCI_HEADER_TYPE_CARDBUS: |
| return PCI_CB_CAPABILITY_LIST; |
| default: |
| return 0; |
| } |
| return 0; |
| } |
| int pci_find_capability(PCITAG pciTag, int cap) |
| { |
| int pos; |
| pos = __pci_bus_find_cap_start(pciTag); |
| if (pos) |
| pos = __pci_find_next_cap(pciTag, pos, cap); |
| return pos; |
| } |
| static __inline__ int drm_device_is_pcie(PCITAG pciTag) |
| { |
| return pci_find_capability(pciTag, PCI_CAP_ID_EXP); |
| } |
| /drivers/old/ati2d/pixmap.inc |
|---|
| 0,0 → 1,258 |
| int CreatePixmap(pixmap_t *io) |
| { |
| local_pixmap_t *pixmap; |
| unsigned pitch; |
| size_t size; |
| addr_t mem_local = 0; |
| addr_t mem_dma = 0; |
| void *mapped; |
| if( (io->width == 0) || (io->width > 2048)|| |
| (io->height == 0)|| (io->height > 2048)) |
| { |
| dbgprintf("Invalid pixmap size w:%d h:%d\n", io->width,io->height); |
| return ERR_PARAM; |
| }; |
| pixmap = malloc(sizeof(local_pixmap_t)); |
| if(!pixmap) |
| return ERR_PARAM; |
| pitch = ((io->width+15)&~15)*4; |
| size = pitch*io->height; |
| dbgprintf("pitch = %d\n", pitch); |
| if( (io->flags & PX_MEM_MASK) == PX_MEM_LOCAL ) { |
| mem_local = rhd_mem_alloc(&rhd,RHD_MEM_FB,size); |
| mem_dma = mem_local + rhd.fbLocation; |
| } |
| else |
| mem_local = mem_dma = AllocPages( size >> 12 ); |
| if ( !mem_local) { |
| dbgprintf("Not enough memory for pixmap\n"); |
| free(pixmap); |
| return ERR_PARAM; |
| }; |
| pixmap->pitch_offset = ((pitch/64)<<22)| (mem_dma>>10); |
| pixmap->local = mem_dma; |
| size = (size+4095) & ~ 4095; |
| if (mapped = UserAlloc(size)) |
| { |
| CommitPages(mapped, mem_dma|7|(1<<9), size); |
| io->mapped = mapped; |
| io->pitch = pitch; |
| io->handle = (u32_t)pixmap; |
| pixmap->width = io->width; |
| pixmap->height = io->height; |
| pixmap->format = PICT_a8r8g8b8; |
| pixmap->flags = io->flags; |
| pixmap->pitch = pitch; |
| pixmap->mapped = mapped; |
| dbgprintf("pixmap.pitch_offset: %x\n", pixmap->pitch_offset); |
| dbgprintf("width: %d height: %d\n",pixmap->width,pixmap->height ); |
| dbgprintf("map at %x\n", pixmap->mapped); |
| return ERR_OK; |
| }; |
| rhd_mem_free(&rhd, RHD_MEM_FB, mem_local); |
| free(pixmap); |
| return ERR_PARAM; |
| }; |
| int DestroyPixmap( pixmap_t *io ) |
| { |
| local_pixmap_t *pixmap; |
| size_t size; |
| dbgprintf("Destroy pixmap %x\n", io->handle); |
| if(io->handle == -1) |
| return ERR_PARAM; |
| else |
| pixmap = (local_pixmap_t*)io->handle; |
| size = (pixmap->pitch*pixmap->height+4095) & ~ 4095; |
| UnmapPages(pixmap->mapped, size); |
| UserFree(pixmap->mapped); |
| if( (io->flags & PX_MEM_MASK) == PX_MEM_LOCAL ) |
| { |
| rhd_mem_free(&rhd,RHD_MEM_FB,pixmap->local-rhd.fbLocation); |
| } |
| else |
| { |
| count_t pages = size >> 12; |
| addr_t base = pixmap->local; |
| while( pages--) |
| { |
| addr_t tmp; |
| // __asm__ __volatile__( |
| // "call *__imp__PageFree" |
| // :"=eax" (tmp):"a" (base) ); |
| // base+= 4096; |
| }; |
| } |
| free(pixmap); |
| io->format = 0; |
| io->pitch = 0; |
| io->mapped = NULL; |
| io->handle = 0; |
| return ERR_OK; |
| }; |
| # define ATI_PCIGART_PAGE_SIZE 4096 /**< PCI GART page size */ |
| # define ATI_PCIGART_PAGE_MASK (~(ATI_PCIGART_PAGE_SIZE-1)) |
| #define ATI_PCIE_WRITE 0x4 |
| #define ATI_PCIE_READ 0x8 |
| #define upper_32_bits(n) ((u32_t)(((n) >> 16) >> 16)) |
| static void bind_pcie(u32_t *gart, addr_t base, count_t pages) |
| { |
| addr_t page_base; |
| while(pages--) |
| { |
| page_base = base & ATI_PCIGART_PAGE_MASK; |
| page_base >>= 8; |
| page_base |= (upper_32_bits(base) & 0xff) << 24; |
| page_base |= ATI_PCIE_READ | ATI_PCIE_WRITE; |
| *gart = page_base; |
| base+= 4096; |
| gart++; |
| } |
| __asm__ __volatile("sfence":::"memory"); |
| RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, |
| RADEON_PCIE_TX_GART_EN |
| | RADEON_PCIE_TX_GART_INVALIDATE_TLB); |
| } |
| static void bind_pci(u32_t *gart, addr_t base, count_t pages) |
| { |
| u32_t tmp; |
| tmp = INREG(RADEON_AIC_CNTL); |
| OUTREG(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN); |
| while(pages--) |
| { |
| *gart = base & ATI_PCIGART_PAGE_MASK; |
| base+= 4096; |
| gart++; |
| } |
| __asm__ __volatile("sfence":::"memory"); |
| OUTREG(RADEON_AIC_CNTL, tmp | RADEON_PCIGART_TRANSLATE_EN); |
| OUTREG(RADEON_AIC_PT_BASE, rhd.gart_table_dma); |
| } |
| static addr_t bind_pixmap(local_pixmap_t *pixmap) |
| { |
| u32_t *gart = rhd.gart_table; |
| count_t pages = ((pixmap->height * pixmap->pitch+4095)&~4095)>>12; |
| addr_t base = pixmap->local; |
| if( rhd.gart_type == RADEON_IS_PCIE) |
| bind_pcie(gart, base, pages); |
| else |
| bind_pci(gart, base, pages); |
| return ((pixmap->pitch / 64) << 22) | (rhd.gart_vm_start >> 10); |
| } |
| #if 0 |
| int LockPixmap(userpixmap_t *io) |
| { |
| pixmap_t *pixmap; |
| size_t size; |
| void *usermap; |
| dbgprintf("Lock pixmap %x\n", io->pixmap); |
| if(io->pixmap == (pixmap_t*)-1) |
| return ERR_PARAM; |
| else |
| pixmap = io->pixmap; |
| if( (pixmap->flags & 1) == PX_LOCK ) |
| return ERR_PARAM; |
| size = (pixmap->pitch*pixmap->width+4095) & ~ 4095; |
| if (usermap = UserAlloc(size)) |
| { |
| CommitPages(usermap, ((u32_t)pixmap->raw+rhd.PhisBase)|7|(1<<9), size); |
| pixmap->flags |= PX_LOCK; |
| pixmap->usermap = usermap; |
| io->usermap = usermap; |
| io->pitch = pixmap->pitch; |
| dbgprintf("map at %x\n", io->usermap); |
| return ERR_OK; |
| } |
| else |
| return ERR_PARAM; |
| }; |
| int UnlockPixmap(userpixmap_t *io) |
| { |
| pixmap_t *pixmap; |
| size_t size; |
| dbgprintf("Unlock pixmap %x\n", io->pixmap); |
| if(io->pixmap == (pixmap_t*)-1) |
| return ERR_PARAM; |
| else |
| pixmap = io->pixmap; |
| if( (pixmap->flags & 1) != PX_LOCK ) |
| return ERR_PARAM; |
| /* Sanity checks */ |
| if( (pixmap->usermap == 0)|| |
| ((u32_t)pixmap->usermap >= 0x80000000) || |
| ((u32_t)pixmap->usermap & 4095) |
| ) |
| return ERR_PARAM; |
| size = (pixmap->pitch*pixmap->width+4095) & ~ 4095; |
| UnmapPages(pixmap->usermap, size); |
| UserFree(pixmap->usermap); |
| pixmap->usermap = NULL; |
| pixmap->flags &= ~PX_LOCK; |
| io->usermap = NULL; |
| io->pitch = 0; |
| return ERR_OK; |
| }; |
| #endif |
| /drivers/old/ati2d/r500.inc |
|---|
| 0,0 → 1,273 |
| #define R300_TEST |
| #include "r5xx_regs.h" |
| #define R5XX_LOOP_COUNT 2000000 |
| #define RADEON_CLOCK_CNTL_DATA 0x000c |
| #define RADEON_CLOCK_CNTL_INDEX 0x0008 |
| # define RADEON_PLL_WR_EN (1 << 7) |
| # define RADEON_PLL_DIV_SEL (3 << 8) |
| # define RADEON_PLL2_DIV_SEL_MASK ~(3 << 8) |
| #define RADEON_MCLK_CNTL 0x0012 /* PLL */ |
| # define RADEON_FORCEON_MCLKA (1 << 16) |
| # define RADEON_FORCEON_MCLKB (1 << 17) |
| # define RADEON_FORCEON_YCLKA (1 << 18) |
| # define RADEON_FORCEON_YCLKB (1 << 19) |
| # define RADEON_FORCEON_MC (1 << 20) |
| # define RADEON_FORCEON_AIC (1 << 21) |
| # define R300_DISABLE_MC_MCLKA (1 << 21) |
| # define R300_DISABLE_MC_MCLKB (1 << 21) |
| void radeon_engine_reset(RHDPtr info) |
| { |
| u32_t clock_cntl_index; |
| u32_t mclk_cntl; |
| u32_t rbbm_soft_reset; |
| u32_t host_path_cntl; |
| if (info->ChipFamily <= CHIP_FAMILY_RV410) |
| { |
| /* may need something similar for newer chips */ |
| clock_cntl_index = INREG(RADEON_CLOCK_CNTL_INDEX); |
| mclk_cntl = INPLL( RADEON_MCLK_CNTL); |
| OUTPLL(RADEON_MCLK_CNTL, (mclk_cntl | |
| RADEON_FORCEON_MCLKA | |
| RADEON_FORCEON_MCLKB | |
| RADEON_FORCEON_YCLKA | |
| RADEON_FORCEON_YCLKB | |
| RADEON_FORCEON_MC | |
| RADEON_FORCEON_AIC)); |
| } |
| rbbm_soft_reset = INREG(RADEON_RBBM_SOFT_RESET); |
| OUTREG(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset | |
| RADEON_SOFT_RESET_CP | |
| RADEON_SOFT_RESET_HI | |
| RADEON_SOFT_RESET_SE | |
| RADEON_SOFT_RESET_RE | |
| RADEON_SOFT_RESET_PP | |
| RADEON_SOFT_RESET_E2 | |
| RADEON_SOFT_RESET_RB)); |
| INREG(RADEON_RBBM_SOFT_RESET); |
| OUTREG(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset & |
| ~(RADEON_SOFT_RESET_CP | |
| RADEON_SOFT_RESET_HI | |
| RADEON_SOFT_RESET_SE | |
| RADEON_SOFT_RESET_RE | |
| RADEON_SOFT_RESET_PP | |
| RADEON_SOFT_RESET_E2 | |
| RADEON_SOFT_RESET_RB))); |
| INREG(RADEON_RBBM_SOFT_RESET); |
| if (info->ChipFamily <= CHIP_FAMILY_RV410) { |
| OUTPLL(RADEON_MCLK_CNTL, mclk_cntl); |
| OUTREG(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index); |
| OUTREG(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset); |
| } |
| }; |
| static Bool R5xxFIFOWaitLocal(u32_t required) //R100-R500 |
| { |
| int i; |
| for (i = 0; i < RADEON_TIMEOUT; i++) |
| if (required <= (INREG(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK)) |
| return TRUE; |
| dbgprintf("%s: Timeout 0x%08X.\n", __func__, (u32_t) INREG(RADEON_RBBM_STATUS)); |
| return FALSE; |
| } |
| void FIFOWait(u32_t required) |
| { |
| int i; |
| for (i = 0; i < 200; i++) |
| { |
| if (required <= (INREG(RADEON_RBBM_STATUS) & |
| RADEON_RBBM_FIFOCNT_MASK)) |
| return ; |
| delay(2); |
| }; |
| }; |
| /* |
| * Flush all dirty data in the Pixel Cache to memory. |
| */ |
| static Bool |
| R5xx2DFlush() |
| { |
| int i; |
| MASKREG(R5XX_DSTCACHE_CTLSTAT, |
| R5XX_DSTCACHE_FLUSH_ALL, R5XX_DSTCACHE_FLUSH_ALL); |
| for (i = 0; i < R5XX_LOOP_COUNT; i++) |
| if (!(INREG(R5XX_DSTCACHE_CTLSTAT) & R5XX_DSTCACHE_BUSY)) |
| return TRUE; |
| dbgprintf("%s: Timeout 0x%08x.\n", __func__, |
| (unsigned int)INREG(R5XX_DSTCACHE_CTLSTAT)); |
| return FALSE; |
| } |
| static Bool |
| R5xx2DIdleLocal() //R100-R500 |
| { |
| int i; |
| /* wait for fifo to clear */ |
| for (i = 0; i < R5XX_LOOP_COUNT; i++) |
| if (64 == (INREG(R5XX_RBBM_STATUS) & R5XX_RBBM_FIFOCNT_MASK)) |
| break; |
| if (i == R5XX_LOOP_COUNT) { |
| dbgprintf("%s: FIFO Timeout 0x%08X.\n", __func__,INREG(R5XX_RBBM_STATUS)); |
| return FALSE; |
| } |
| /* wait for engine to go idle */ |
| for (i = 0; i < R5XX_LOOP_COUNT; i++) { |
| if (!(INREG(R5XX_RBBM_STATUS) & R5XX_RBBM_ACTIVE)) { |
| R5xx2DFlush(); |
| return TRUE; |
| } |
| } |
| dbgprintf("%s: Idle Timeout 0x%08X.\n", __func__,INREG(R5XX_RBBM_STATUS)); |
| return FALSE; |
| } |
| void |
| R5xx2DSetup() |
| { |
| /* Setup engine location. This shouldn't be necessary since we |
| * set them appropriately before any accel ops, but let's avoid |
| * random bogus DMA in case we inadvertently trigger the engine |
| * in the wrong place (happened). */ |
| R5xxFIFOWaitLocal(2); |
| OUTREG(R5XX_DST_PITCH_OFFSET,rhd.dst_pitch_offset); |
| OUTREG(R5XX_SRC_PITCH_OFFSET,rhd.dst_pitch_offset); |
| R5xxFIFOWaitLocal(1); |
| MASKREG(R5XX_DP_DATATYPE, 0, R5XX_HOST_BIG_ENDIAN_EN); |
| OUTREG(R5XX_SURFACE_CNTL, rhd.surface_cntl); |
| R5xxFIFOWaitLocal(3); |
| OUTREG(R5XX_SC_TOP_LEFT, 0); |
| OUTREG(R5XX_SC_BOTTOM_RIGHT, |
| RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); |
| OUTREG(R5XX_DEFAULT_SC_BOTTOM_RIGHT, |
| RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); |
| R5xxFIFOWaitLocal(1); |
| // OUTREG(R5XX_DP_GUI_MASTER_CNTL, rhd.gui_control | |
| // R5XX_GMC_BRUSH_SOLID_COLOR | R5XX_GMC_SRC_DATATYPE_COLOR); |
| OUTREG(R5XX_DP_CNTL, R5XX_DST_X_LEFT_TO_RIGHT | R5XX_DST_Y_TOP_TO_BOTTOM); |
| R5xxFIFOWaitLocal(5); |
| OUTREG(R5XX_DP_BRUSH_FRGD_CLR, 0xFFFFFFFF); |
| OUTREG(R5XX_DP_BRUSH_BKGD_CLR, 0x00000000); |
| OUTREG(R5XX_DP_SRC_FRGD_CLR, 0xFFFFFFFF); |
| OUTREG(R5XX_DP_SRC_BKGD_CLR, 0x00000000); |
| OUTREG(R5XX_DP_WRITE_MASK, 0xFFFFFFFF); |
| R5xx2DIdleLocal(); |
| } |
| void R5xxFIFOWait(u32_t required) |
| { |
| if (!R5xxFIFOWaitLocal(required)) { |
| radeon_engine_reset(&rhd); |
| R5xx2DSetup(); |
| } |
| } |
| void R5xx2DIdle() |
| { |
| if (!R5xx2DIdleLocal()) { |
| // R5xx2DReset(); |
| R5xx2DSetup(); |
| } |
| } |
| void R5xx2DInit() |
| { |
| u32_t base; |
| int screensize; |
| int screenpitch; |
| screensize = GetScreenSize(); |
| screenpitch = GetScreenPitch(); |
| rhd.displayWidth = screensize >> 16; |
| rhd.displayHeight = screensize & 0xFFFF; |
| rhd.__xmin = 0; |
| rhd.__ymin = 0; |
| rhd.__xmax = rhd.displayWidth - 1; |
| rhd.__ymax = rhd.displayHeight - 1; |
| clip.xmin = 0; |
| clip.ymin = 0; |
| clip.xmax = rhd.displayWidth - 1; |
| clip.ymax = rhd.displayHeight - 1; |
| dbgprintf("screen width %d height %d\n", |
| rhd.displayWidth, rhd.displayHeight); |
| rhd.gui_control = ((6 << RADEON_GMC_DST_DATATYPE_SHIFT) |
| | RADEON_GMC_CLR_CMP_CNTL_DIS |
| | RADEON_GMC_DST_PITCH_OFFSET_CNTL); |
| dbgprintf("gui_control %x \n", rhd.gui_control); |
| rhd.surface_cntl = 0; |
| rhd.dst_pitch_offset = (((rhd.displayWidth * 4 / 64)<< 22) | |
| (rhd.fbLocation >> 10)); |
| dbgprintf("dst_pitch_offset %x \n", rhd.dst_pitch_offset); |
| scr_pixmap.width = rhd.displayWidth; |
| scr_pixmap.height = rhd.displayHeight; |
| scr_pixmap.format = PICT_a8r8g8b8; |
| scr_pixmap.flags = PX_MEM_LOCAL; |
| scr_pixmap.pitch = rhd.displayWidth * 4 ;//screenpitch; |
| scr_pixmap.local = rhd.fbLocation; |
| scr_pixmap.pitch_offset = rhd.dst_pitch_offset; |
| scr_pixmap.mapped = 0; |
| R5xxFIFOWaitLocal(2); |
| OUTREG(R5XX_DST_PITCH_OFFSET,rhd.dst_pitch_offset); |
| OUTREG(R5XX_SRC_PITCH_OFFSET,rhd.dst_pitch_offset); |
| R5xxFIFOWaitLocal(1); |
| MASKREG(R5XX_DP_DATATYPE, 0, R5XX_HOST_BIG_ENDIAN_EN); |
| OUTREG(R5XX_SURFACE_CNTL, rhd.surface_cntl); |
| #if !R300_PIO |
| init_cp(&rhd); |
| #endif |
| R5xx2DSetup(); |
| } |
| /drivers/old/ati2d/r5xx_2dregs.h |
|---|
| 0,0 → 1,288 |
| /* |
| * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and |
| * VA Linux Systems Inc., Fremont, California. |
| * |
| * All Rights Reserved. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining |
| * a copy of this software and associated documentation files (the |
| * "Software"), to deal in the Software without restriction, including |
| * without limitation on the rights to use, copy, modify, merge, |
| * publish, distribute, sublicense, and/or sell copies of the Software, |
| * and to permit persons to whom the Software is furnished to do so, |
| * subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice (including the |
| * next paragraph) shall be included in all copies or substantial |
| * portions of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR |
| * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
| * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| * DEALINGS IN THE SOFTWARE. |
| */ |
| /* WARNING: the above is not a standard MIT license. */ |
| /* |
| * Authors: |
| * Kevin E. Martin <martin@xfree86.org> |
| * Rickard E. Faith <faith@valinux.com> |
| * Alan Hourihane <alanh@fairlite.demon.co.uk> |
| */ |
| #ifndef _R5XX_2DREGS_H |
| # define _R5XX_2DREGS_H |
| #define R5XX_DATATYPE_VQ 0 |
| #define R5XX_DATATYPE_CI4 1 |
| #define R5XX_DATATYPE_CI8 2 |
| #define R5XX_DATATYPE_ARGB1555 3 |
| #define R5XX_DATATYPE_RGB565 4 |
| #define R5XX_DATATYPE_RGB888 5 |
| #define R5XX_DATATYPE_ARGB8888 6 |
| #define R5XX_DATATYPE_RGB332 7 |
| #define R5XX_DATATYPE_Y8 8 |
| #define R5XX_DATATYPE_RGB8 9 |
| #define R5XX_DATATYPE_CI16 10 |
| #define R5XX_DATATYPE_VYUY_422 11 |
| #define R5XX_DATATYPE_YVYU_422 12 |
| #define R5XX_DATATYPE_AYUV_444 14 |
| #define R5XX_DATATYPE_ARGB4444 15 |
| #define R5XX_RBBM_SOFT_RESET 0x00f0 |
| # define R5XX_SOFT_RESET_CP (1 << 0) |
| # define R5XX_SOFT_RESET_HI (1 << 1) |
| # define R5XX_SOFT_RESET_SE (1 << 2) |
| # define R5XX_SOFT_RESET_RE (1 << 3) |
| # define R5XX_SOFT_RESET_PP (1 << 4) |
| # define R5XX_SOFT_RESET_E2 (1 << 5) |
| # define R5XX_SOFT_RESET_RB (1 << 6) |
| # define R5XX_SOFT_RESET_HDP (1 << 7) |
| #define R5XX_HOST_PATH_CNTL 0x0130 |
| # define R5XX_HDP_SOFT_RESET (1 << 26) |
| # define R5XX_HDP_APER_CNTL (1 << 23) |
| #define R5XX_SURFACE_CNTL 0x0b00 |
| # define R5XX_SURF_TRANSLATION_DIS (1 << 8) |
| # define R5XX_NONSURF_AP0_SWP_16BPP (1 << 20) |
| # define R5XX_NONSURF_AP0_SWP_32BPP (1 << 21) |
| # define R5XX_NONSURF_AP1_SWP_16BPP (1 << 22) |
| # define R5XX_NONSURF_AP1_SWP_32BPP (1 << 23) |
| #define R5XX_SURFACE0_INFO 0x0b0c |
| # define R5XX_SURF_TILE_COLOR_MACRO (0 << 16) |
| # define R5XX_SURF_TILE_COLOR_BOTH (1 << 16) |
| # define R5XX_SURF_TILE_DEPTH_32BPP (2 << 16) |
| # define R5XX_SURF_TILE_DEPTH_16BPP (3 << 16) |
| # define R5XX_SURF_AP0_SWP_16BPP (1 << 20) |
| # define R5XX_SURF_AP0_SWP_32BPP (1 << 21) |
| # define R5XX_SURF_AP1_SWP_16BPP (1 << 22) |
| # define R5XX_SURF_AP1_SWP_32BPP (1 << 23) |
| #define R5XX_SURFACE0_LOWER_BOUND 0x0b04 |
| #define R5XX_SURFACE0_UPPER_BOUND 0x0b08 |
| #define R5XX_RBBM_STATUS 0x0e40 |
| # define R5XX_RBBM_FIFOCNT_MASK 0x007f |
| # define R5XX_RBBM_ACTIVE (1 << 31) |
| #define R5XX_SRC_PITCH_OFFSET 0x1428 |
| #define R5XX_DST_PITCH_OFFSET 0x142c |
| #define R5XX_SRC_Y_X 0x1434 |
| #define R5XX_DST_Y_X 0x1438 |
| #define R5XX_DST_HEIGHT_WIDTH 0x143c |
| #define R5XX_DP_GUI_MASTER_CNTL 0x146c |
| # define R5XX_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) |
| # define R5XX_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) |
| # define R5XX_GMC_SRC_CLIPPING (1 << 2) |
| # define R5XX_GMC_DST_CLIPPING (1 << 3) |
| # define R5XX_GMC_BRUSH_DATATYPE_MASK (0x0f << 4) |
| # define R5XX_GMC_BRUSH_8X8_MONO_FG_BG (0 << 4) |
| # define R5XX_GMC_BRUSH_8X8_MONO_FG_LA (1 << 4) |
| # define R5XX_GMC_BRUSH_1X8_MONO_FG_BG (4 << 4) |
| # define R5XX_GMC_BRUSH_1X8_MONO_FG_LA (5 << 4) |
| # define R5XX_GMC_BRUSH_32x1_MONO_FG_BG (6 << 4) |
| # define R5XX_GMC_BRUSH_32x1_MONO_FG_LA (7 << 4) |
| # define R5XX_GMC_BRUSH_32x32_MONO_FG_BG (8 << 4) |
| # define R5XX_GMC_BRUSH_32x32_MONO_FG_LA (9 << 4) |
| # define R5XX_GMC_BRUSH_8x8_COLOR (10 << 4) |
| # define R5XX_GMC_BRUSH_1X8_COLOR (12 << 4) |
| # define R5XX_GMC_BRUSH_SOLID_COLOR (13 << 4) |
| # define R5XX_GMC_BRUSH_NONE (15 << 4) |
| # define R5XX_GMC_DST_8BPP_CI (2 << 8) |
| # define R5XX_GMC_DST_15BPP (3 << 8) |
| # define R5XX_GMC_DST_16BPP (4 << 8) |
| # define R5XX_GMC_DST_24BPP (5 << 8) |
| # define R5XX_GMC_DST_32BPP (6 << 8) |
| # define R5XX_GMC_DST_8BPP_RGB (7 << 8) |
| # define R5XX_GMC_DST_Y8 (8 << 8) |
| # define R5XX_GMC_DST_RGB8 (9 << 8) |
| # define R5XX_GMC_DST_VYUY (11 << 8) |
| # define R5XX_GMC_DST_YVYU (12 << 8) |
| # define R5XX_GMC_DST_AYUV444 (14 << 8) |
| # define R5XX_GMC_DST_ARGB4444 (15 << 8) |
| # define R5XX_GMC_DST_DATATYPE_MASK (0x0f << 8) |
| # define R5XX_GMC_DST_DATATYPE_SHIFT 8 |
| # define R5XX_GMC_SRC_DATATYPE_MASK (3 << 12) |
| # define R5XX_GMC_SRC_DATATYPE_MONO_FG_BG (0 << 12) |
| # define R5XX_GMC_SRC_DATATYPE_MONO_FG_LA (1 << 12) |
| # define R5XX_GMC_SRC_DATATYPE_COLOR (3 << 12) |
| # define R5XX_GMC_BYTE_PIX_ORDER (1 << 14) |
| # define R5XX_GMC_BYTE_MSB_TO_LSB (0 << 14) |
| # define R5XX_GMC_BYTE_LSB_TO_MSB (1 << 14) |
| # define R5XX_GMC_CONVERSION_TEMP (1 << 15) |
| # define R5XX_GMC_CONVERSION_TEMP_6500 (0 << 15) |
| # define R5XX_GMC_CONVERSION_TEMP_9300 (1 << 15) |
| # define R5XX_GMC_ROP3_MASK (0xff << 16) |
| # define R5XX_DP_SRC_SOURCE_MASK (7 << 24) |
| # define R5XX_DP_SRC_SOURCE_MEMORY (2 << 24) |
| # define R5XX_DP_SRC_SOURCE_HOST_DATA (3 << 24) |
| # define R5XX_GMC_3D_FCN_EN (1 << 27) |
| # define R5XX_GMC_CLR_CMP_CNTL_DIS (1 << 28) |
| # define R5XX_GMC_AUX_CLIP_DIS (1 << 29) |
| # define R5XX_GMC_WR_MSK_DIS (1 << 30) |
| # define R5XX_GMC_LD_BRUSH_Y_X (1 << 31) |
| # define R5XX_ROP3_ZERO 0x00000000 |
| # define R5XX_ROP3_DSa 0x00880000 |
| # define R5XX_ROP3_SDna 0x00440000 |
| # define R5XX_ROP3_S 0x00cc0000 |
| # define R5XX_ROP3_DSna 0x00220000 |
| # define R5XX_ROP3_D 0x00aa0000 |
| # define R5XX_ROP3_DSx 0x00660000 |
| # define R5XX_ROP3_DSo 0x00ee0000 |
| # define R5XX_ROP3_DSon 0x00110000 |
| # define R5XX_ROP3_DSxn 0x00990000 |
| # define R5XX_ROP3_Dn 0x00550000 |
| # define R5XX_ROP3_SDno 0x00dd0000 |
| # define R5XX_ROP3_Sn 0x00330000 |
| # define R5XX_ROP3_DSno 0x00bb0000 |
| # define R5XX_ROP3_DSan 0x00770000 |
| # define R5XX_ROP3_ONE 0x00ff0000 |
| # define R5XX_ROP3_DPa 0x00a00000 |
| # define R5XX_ROP3_PDna 0x00500000 |
| # define R5XX_ROP3_P 0x00f00000 |
| # define R5XX_ROP3_DPna 0x000a0000 |
| # define R5XX_ROP3_D 0x00aa0000 |
| # define R5XX_ROP3_DPx 0x005a0000 |
| # define R5XX_ROP3_DPo 0x00fa0000 |
| # define R5XX_ROP3_DPon 0x00050000 |
| # define R5XX_ROP3_PDxn 0x00a50000 |
| # define R5XX_ROP3_PDno 0x00f50000 |
| # define R5XX_ROP3_Pn 0x000f0000 |
| # define R5XX_ROP3_DPno 0x00af0000 |
| # define R5XX_ROP3_DPan 0x005f0000 |
| #define R5XX_BRUSH_Y_X 0x1474 |
| #define R5XX_DP_BRUSH_BKGD_CLR 0x1478 |
| #define R5XX_DP_BRUSH_FRGD_CLR 0x147c |
| #define R5XX_BRUSH_DATA0 0x1480 |
| #define R5XX_BRUSH_DATA1 0x1484 |
| #define R5XX_DST_WIDTH_HEIGHT 0x1598 |
| #define R5XX_CLR_CMP_CNTL 0x15c0 |
| # define R5XX_SRC_CMP_EQ_COLOR (4 << 0) |
| # define R5XX_SRC_CMP_NEQ_COLOR (5 << 0) |
| # define R5XX_CLR_CMP_SRC_SOURCE (1 << 24) |
| #define R5XX_CLR_CMP_CLR_SRC 0x15c4 |
| #define R5XX_CLR_CMP_MASK 0x15cc |
| # define R5XX_CLR_CMP_MSK 0xffffffff |
| #define R5XX_DP_SRC_BKGD_CLR 0x15dc |
| #define R5XX_DP_SRC_FRGD_CLR 0x15d8 |
| #define R5XX_DST_LINE_START 0x1600 |
| #define R5XX_DST_LINE_END 0x1604 |
| #define R5XX_DST_LINE_PATCOUNT 0x1608 |
| # define R5XX_BRES_CNTL_SHIFT 8 |
| #define R5XX_DP_CNTL 0x16c0 |
| # define R5XX_DST_X_LEFT_TO_RIGHT (1 << 0) |
| # define R5XX_DST_Y_TOP_TO_BOTTOM (1 << 1) |
| # define R5XX_DP_DST_TILE_LINEAR (0 << 3) |
| # define R5XX_DP_DST_TILE_MACRO (1 << 3) |
| # define R5XX_DP_DST_TILE_MICRO (2 << 3) |
| # define R5XX_DP_DST_TILE_BOTH (3 << 3) |
| #define R5XX_DP_DATATYPE 0x16c4 |
| # define R5XX_HOST_BIG_ENDIAN_EN (1 << 29) |
| #define R5XX_DP_WRITE_MASK 0x16cc |
| #define R5XX_DEFAULT_SC_BOTTOM_RIGHT 0x16e8 |
| # define R5XX_DEFAULT_SC_RIGHT_MAX (0x1fff << 0) |
| # define R5XX_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16) |
| #define R5XX_SC_TOP_LEFT 0x16ec |
| #define R5XX_SC_BOTTOM_RIGHT 0x16f0 |
| # define R5XX_SC_SIGN_MASK_LO 0x8000 |
| # define R5XX_SC_SIGN_MASK_HI 0x80000000 |
| #define R5XX_RBBM_GUICNTL 0x172c |
| # define R5XX_HOST_DATA_SWAP_NONE (0 << 0) |
| # define R5XX_HOST_DATA_SWAP_16BIT (1 << 0) |
| # define R5XX_HOST_DATA_SWAP_32BIT (2 << 0) |
| # define R5XX_HOST_DATA_SWAP_HDW (3 << 0) |
| #define R5XX_HOST_DATA0 0x17c0 |
| #define R5XX_HOST_DATA1 0x17c4 |
| #define R5XX_HOST_DATA2 0x17c8 |
| #define R5XX_HOST_DATA3 0x17cc |
| #define R5XX_HOST_DATA4 0x17d0 |
| #define R5XX_HOST_DATA5 0x17d4 |
| #define R5XX_HOST_DATA6 0x17d8 |
| #define R5XX_HOST_DATA7 0x17dc |
| #define R5XX_HOST_DATA_LAST 0x17e0 |
| #define R5XX_RB3D_CNTL 0x1c3c |
| # define R5XX_ALPHA_BLEND_ENABLE (1 << 0) |
| # define R5XX_PLANE_MASK_ENABLE (1 << 1) |
| # define R5XX_DITHER_ENABLE (1 << 2) |
| # define R5XX_ROUND_ENABLE (1 << 3) |
| # define R5XX_SCALE_DITHER_ENABLE (1 << 4) |
| # define R5XX_DITHER_INIT (1 << 5) |
| # define R5XX_ROP_ENABLE (1 << 6) |
| # define R5XX_STENCIL_ENABLE (1 << 7) |
| # define R5XX_Z_ENABLE (1 << 8) |
| # define R5XX_DEPTH_XZ_OFFEST_ENABLE (1 << 9) |
| # define R5XX_COLOR_FORMAT_ARGB1555 (3 << 10) |
| # define R5XX_COLOR_FORMAT_RGB565 (4 << 10) |
| # define R5XX_COLOR_FORMAT_ARGB8888 (6 << 10) |
| # define R5XX_COLOR_FORMAT_RGB332 (7 << 10) |
| # define R5XX_COLOR_FORMAT_Y8 (8 << 10) |
| # define R5XX_COLOR_FORMAT_RGB8 (9 << 10) |
| # define R5XX_COLOR_FORMAT_YUV422_VYUY (11 << 10) |
| # define R5XX_COLOR_FORMAT_YUV422_YVYU (12 << 10) |
| # define R5XX_COLOR_FORMAT_aYUV444 (14 << 10) |
| # define R5XX_COLOR_FORMAT_ARGB4444 (15 << 10) |
| # define R5XX_CLRCMP_FLIP_ENABLE (1 << 14) |
| #define R5XX_RB3D_DSTCACHE_CTLSTAT 0x325C |
| # define R5XX_RB3D_DC_FLUSH (3 << 0) |
| # define R5XX_RB3D_DC_FREE (3 << 2) |
| # define R5XX_RB3D_DC_FLUSH_ALL 0xf |
| # define R5XX_RB3D_DC_BUSY (1 << 31) |
| #define R5XX_RB3D_DSTCACHE_MODE 0x3258 |
| # define R5XX_RB3D_DC_CACHE_ENABLE (0) |
| # define R5XX_RB3D_DC_2D_CACHE_DISABLE (1) |
| # define R5XX_RB3D_DC_3D_CACHE_DISABLE (2) |
| # define R5XX_RB3D_DC_CACHE_DISABLE (3) |
| # define R5XX_RB3D_DC_2D_CACHE_LINESIZE_128 (1 << 2) |
| # define R5XX_RB3D_DC_3D_CACHE_LINESIZE_128 (2 << 2) |
| # define R5XX_RB3D_DC_2D_CACHE_AUTOFLUSH (1 << 8) |
| # define R5XX_RB3D_DC_3D_CACHE_AUTOFLUSH (2 << 8) |
| # define R200_RB3D_DC_2D_CACHE_AUTOFREE (1 << 10) |
| # define R200_RB3D_DC_3D_CACHE_AUTOFREE (2 << 10) |
| # define R5XX_RB3D_DC_FORCE_RMW (1 << 16) |
| # define R5XX_RB3D_DC_DISABLE_RI_FILL (1 << 24) |
| # define R5XX_RB3D_DC_DISABLE_RI_READ (1 << 25) |
| #endif /* _R5XX_2DREGS_H */ |
| /drivers/old/ati2d/r5xx_regs.h |
|---|
| 0,0 → 1,273 |
| /* |
| * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and |
| * VA Linux Systems Inc., Fremont, California. |
| * |
| * All Rights Reserved. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining |
| * a copy of this software and associated documentation files (the |
| * "Software"), to deal in the Software without restriction, including |
| * without limitation on the rights to use, copy, modify, merge, |
| * publish, distribute, sublicense, and/or sell copies of the Software, |
| * and to permit persons to whom the Software is furnished to do so, |
| * subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice (including the |
| * next paragraph) shall be included in all copies or substantial |
| * portions of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR |
| * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
| * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| * DEALINGS IN THE SOFTWARE. |
| */ |
| /* WARNING: the above is not a standard MIT license. */ |
| /* |
| * Authors: |
| * Kevin E. Martin <martin@xfree86.org> |
| * Rickard E. Faith <faith@valinux.com> |
| * Alan Hourihane <alanh@fairlite.demon.co.uk> |
| */ |
| #ifndef _R5XX_2DREGS_H |
| # define _R5XX_2DREGS_H |
| #define R5XX_DATATYPE_VQ 0 |
| #define R5XX_DATATYPE_CI4 1 |
| #define R5XX_DATATYPE_CI8 2 |
| #define R5XX_DATATYPE_ARGB1555 3 |
| #define R5XX_DATATYPE_RGB565 4 |
| #define R5XX_DATATYPE_RGB888 5 |
| #define R5XX_DATATYPE_ARGB8888 6 |
| #define R5XX_DATATYPE_RGB332 7 |
| #define R5XX_DATATYPE_Y8 8 |
| #define R5XX_DATATYPE_RGB8 9 |
| #define R5XX_DATATYPE_CI16 10 |
| #define R5XX_DATATYPE_VYUY_422 11 |
| #define R5XX_DATATYPE_YVYU_422 12 |
| #define R5XX_DATATYPE_AYUV_444 14 |
| #define R5XX_DATATYPE_ARGB4444 15 |
| #define R5XX_RBBM_SOFT_RESET 0x00f0 |
| # define R5XX_SOFT_RESET_CP (1 << 0) |
| # define R5XX_SOFT_RESET_HI (1 << 1) |
| # define R5XX_SOFT_RESET_SE (1 << 2) |
| # define R5XX_SOFT_RESET_RE (1 << 3) |
| # define R5XX_SOFT_RESET_PP (1 << 4) |
| # define R5XX_SOFT_RESET_E2 (1 << 5) |
| # define R5XX_SOFT_RESET_RB (1 << 6) |
| # define R5XX_SOFT_RESET_HDP (1 << 7) |
| #define R5XX_HOST_PATH_CNTL 0x0130 |
| # define R5XX_HDP_SOFT_RESET (1 << 26) |
| # define R5XX_HDP_APER_CNTL (1 << 23) |
| #define R5XX_SURFACE_CNTL 0x0b00 |
| # define R5XX_SURF_TRANSLATION_DIS (1 << 8) |
| # define R5XX_NONSURF_AP0_SWP_16BPP (1 << 20) |
| # define R5XX_NONSURF_AP0_SWP_32BPP (1 << 21) |
| # define R5XX_NONSURF_AP1_SWP_16BPP (1 << 22) |
| # define R5XX_NONSURF_AP1_SWP_32BPP (1 << 23) |
| #define R5XX_SURFACE0_INFO 0x0b0c |
| # define R5XX_SURF_TILE_COLOR_MACRO (0 << 16) |
| # define R5XX_SURF_TILE_COLOR_BOTH (1 << 16) |
| # define R5XX_SURF_TILE_DEPTH_32BPP (2 << 16) |
| # define R5XX_SURF_TILE_DEPTH_16BPP (3 << 16) |
| # define R5XX_SURF_AP0_SWP_16BPP (1 << 20) |
| # define R5XX_SURF_AP0_SWP_32BPP (1 << 21) |
| # define R5XX_SURF_AP1_SWP_16BPP (1 << 22) |
| # define R5XX_SURF_AP1_SWP_32BPP (1 << 23) |
| #define R5XX_SURFACE0_LOWER_BOUND 0x0b04 |
| #define R5XX_SURFACE0_UPPER_BOUND 0x0b08 |
| #define R5XX_RBBM_STATUS 0x0e40 |
| # define R5XX_RBBM_FIFOCNT_MASK 0x007f |
| # define R5XX_RBBM_ACTIVE (1 << 31) |
| #define R5XX_SRC_PITCH_OFFSET 0x1428 |
| #define R5XX_DST_PITCH_OFFSET 0x142c |
| #define R5XX_SRC_Y_X 0x1434 |
| #define R5XX_DST_Y_X 0x1438 |
| #define R5XX_DST_HEIGHT_WIDTH 0x143c |
| #define R5XX_DP_GUI_MASTER_CNTL 0x146c |
| # define R5XX_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) |
| # define R5XX_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) |
| # define R5XX_GMC_SRC_CLIPPING (1 << 2) |
| # define R5XX_GMC_DST_CLIPPING (1 << 3) |
| # define R5XX_GMC_BRUSH_DATATYPE_MASK (0x0f << 4) |
| # define R5XX_GMC_BRUSH_8X8_MONO_FG_BG (0 << 4) |
| # define R5XX_GMC_BRUSH_8X8_MONO_FG_LA (1 << 4) |
| # define R5XX_GMC_BRUSH_1X8_MONO_FG_BG (4 << 4) |
| # define R5XX_GMC_BRUSH_1X8_MONO_FG_LA (5 << 4) |
| # define R5XX_GMC_BRUSH_32x1_MONO_FG_BG (6 << 4) |
| # define R5XX_GMC_BRUSH_32x1_MONO_FG_LA (7 << 4) |
| # define R5XX_GMC_BRUSH_32x32_MONO_FG_BG (8 << 4) |
| # define R5XX_GMC_BRUSH_32x32_MONO_FG_LA (9 << 4) |
| # define R5XX_GMC_BRUSH_8x8_COLOR (10 << 4) |
| # define R5XX_GMC_BRUSH_1X8_COLOR (12 << 4) |
| # define R5XX_GMC_BRUSH_SOLID_COLOR (13 << 4) |
| # define R5XX_GMC_BRUSH_NONE (15 << 4) |
| # define R5XX_GMC_DST_8BPP_CI (2 << 8) |
| # define R5XX_GMC_DST_15BPP (3 << 8) |
| # define R5XX_GMC_DST_16BPP (4 << 8) |
| # define R5XX_GMC_DST_24BPP (5 << 8) |
| # define R5XX_GMC_DST_32BPP (6 << 8) |
| # define R5XX_GMC_DST_8BPP_RGB (7 << 8) |
| # define R5XX_GMC_DST_Y8 (8 << 8) |
| # define R5XX_GMC_DST_RGB8 (9 << 8) |
| # define R5XX_GMC_DST_VYUY (11 << 8) |
| # define R5XX_GMC_DST_YVYU (12 << 8) |
| # define R5XX_GMC_DST_AYUV444 (14 << 8) |
| # define R5XX_GMC_DST_ARGB4444 (15 << 8) |
| # define R5XX_GMC_DST_DATATYPE_MASK (0x0f << 8) |
| # define R5XX_GMC_DST_DATATYPE_SHIFT 8 |
| # define R5XX_GMC_SRC_DATATYPE_MASK (3 << 12) |
| # define R5XX_GMC_SRC_DATATYPE_MONO_FG_BG (0 << 12) |
| # define R5XX_GMC_SRC_DATATYPE_MONO_FG_LA (1 << 12) |
| # define R5XX_GMC_SRC_DATATYPE_COLOR (3 << 12) |
| # define R5XX_GMC_BYTE_PIX_ORDER (1 << 14) |
| # define R5XX_GMC_BYTE_MSB_TO_LSB (0 << 14) |
| # define R5XX_GMC_BYTE_LSB_TO_MSB (1 << 14) |
| # define R5XX_GMC_CONVERSION_TEMP (1 << 15) |
| # define R5XX_GMC_CONVERSION_TEMP_6500 (0 << 15) |
| # define R5XX_GMC_CONVERSION_TEMP_9300 (1 << 15) |
| # define R5XX_GMC_ROP3_MASK (0xff << 16) |
| # define R5XX_DP_SRC_SOURCE_MASK (7 << 24) |
| # define R5XX_DP_SRC_SOURCE_MEMORY (2 << 24) |
| # define R5XX_DP_SRC_SOURCE_HOST_DATA (3 << 24) |
| # define R5XX_GMC_3D_FCN_EN (1 << 27) |
| # define R5XX_GMC_CLR_CMP_CNTL_DIS (1 << 28) |
| # define R5XX_GMC_AUX_CLIP_DIS (1 << 29) |
| # define R5XX_GMC_WR_MSK_DIS (1 << 30) |
| # define R5XX_GMC_LD_BRUSH_Y_X (1 << 31) |
| # define R5XX_ROP3_ZERO 0x00000000 |
| # define R5XX_ROP3_DSa 0x00880000 |
| # define R5XX_ROP3_SDna 0x00440000 |
| # define R5XX_ROP3_S 0x00cc0000 |
| # define R5XX_ROP3_DSna 0x00220000 |
| # define R5XX_ROP3_D 0x00aa0000 |
| # define R5XX_ROP3_DSx 0x00660000 |
| # define R5XX_ROP3_DSo 0x00ee0000 |
| # define R5XX_ROP3_DSon 0x00110000 |
| # define R5XX_ROP3_DSxn 0x00990000 |
| # define R5XX_ROP3_Dn 0x00550000 |
| # define R5XX_ROP3_SDno 0x00dd0000 |
| # define R5XX_ROP3_Sn 0x00330000 |
| # define R5XX_ROP3_DSno 0x00bb0000 |
| # define R5XX_ROP3_DSan 0x00770000 |
| # define R5XX_ROP3_ONE 0x00ff0000 |
| # define R5XX_ROP3_DPa 0x00a00000 |
| # define R5XX_ROP3_PDna 0x00500000 |
| # define R5XX_ROP3_P 0x00f00000 |
| # define R5XX_ROP3_DPna 0x000a0000 |
| # define R5XX_ROP3_D 0x00aa0000 |
| # define R5XX_ROP3_DPx 0x005a0000 |
| # define R5XX_ROP3_DPo 0x00fa0000 |
| # define R5XX_ROP3_DPon 0x00050000 |
| # define R5XX_ROP3_PDxn 0x00a50000 |
| # define R5XX_ROP3_PDno 0x00f50000 |
| # define R5XX_ROP3_Pn 0x000f0000 |
| # define R5XX_ROP3_DPno 0x00af0000 |
| # define R5XX_ROP3_DPan 0x005f0000 |
| #define R5XX_BRUSH_Y_X 0x1474 |
| #define R5XX_DP_BRUSH_BKGD_CLR 0x1478 |
| #define R5XX_DP_BRUSH_FRGD_CLR 0x147c |
| #define R5XX_BRUSH_DATA0 0x1480 |
| #define R5XX_BRUSH_DATA1 0x1484 |
| #define R5XX_DST_WIDTH_HEIGHT 0x1598 |
| #define R5XX_CLR_CMP_CNTL 0x15c0 |
| # define R5XX_SRC_CMP_EQ_COLOR (4 << 0) |
| # define R5XX_SRC_CMP_NEQ_COLOR (5 << 0) |
| # define R5XX_CLR_CMP_SRC_SOURCE (1 << 24) |
| #define R5XX_CLR_CMP_CLR_SRC 0x15c4 |
| #define R5XX_CLR_CMP_MASK 0x15cc |
| # define R5XX_CLR_CMP_MSK 0xffffffff |
| #define R5XX_DP_SRC_BKGD_CLR 0x15dc |
| #define R5XX_DP_SRC_FRGD_CLR 0x15d8 |
| #define R5XX_DST_LINE_START 0x1600 |
| #define R5XX_DST_LINE_END 0x1604 |
| #define R5XX_DST_LINE_PATCOUNT 0x1608 |
| # define R5XX_BRES_CNTL_SHIFT 8 |
| #define R5XX_DP_CNTL 0x16c0 |
| # define R5XX_DST_X_LEFT_TO_RIGHT (1 << 0) |
| # define R5XX_DST_Y_TOP_TO_BOTTOM (1 << 1) |
| # define R5XX_DP_DST_TILE_LINEAR (0 << 3) |
| # define R5XX_DP_DST_TILE_MACRO (1 << 3) |
| # define R5XX_DP_DST_TILE_MICRO (2 << 3) |
| # define R5XX_DP_DST_TILE_BOTH (3 << 3) |
| #define R5XX_DP_DATATYPE 0x16c4 |
| # define R5XX_HOST_BIG_ENDIAN_EN (1 << 29) |
| #define R5XX_DP_WRITE_MASK 0x16cc |
| #define R5XX_DEFAULT_SC_BOTTOM_RIGHT 0x16e8 |
| # define R5XX_DEFAULT_SC_RIGHT_MAX (0x1fff << 0) |
| # define R5XX_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16) |
| #define R5XX_SC_TOP_LEFT 0x16ec |
| #define R5XX_SC_BOTTOM_RIGHT 0x16f0 |
| # define R5XX_SC_SIGN_MASK_LO 0x8000 |
| # define R5XX_SC_SIGN_MASK_HI 0x80000000 |
| #define R5XX_DST_PIPE_CONFIG 0x170c |
| # define R5XX_PIPE_AUTO_CONFIG (1 << 31) |
| #define R5XX_DSTCACHE_CTLSTAT 0x1714 |
| # define R5XX_DSTCACHE_FLUSH_2D (1 << 0) |
| # define R5XX_DSTCACHE_FREE_2D (1 << 2) |
| # define R5XX_DSTCACHE_FLUSH_ALL (R5XX_DSTCACHE_FLUSH_2D | R5XX_DSTCACHE_FREE_2D) |
| # define R5XX_DSTCACHE_BUSY (1 << 31) |
| #define R5XX_WAIT_UNTIL 0x1720 |
| # define R5XX_WAIT_2D_IDLECLEAN (1 << 16) |
| # define R5XX_WAIT_3D_IDLECLEAN (1 << 17) |
| #define R5XX_RBBM_GUICNTL 0x172c |
| # define R5XX_HOST_DATA_SWAP_NONE (0 << 0) |
| # define R5XX_HOST_DATA_SWAP_16BIT (1 << 0) |
| # define R5XX_HOST_DATA_SWAP_32BIT (2 << 0) |
| # define R5XX_HOST_DATA_SWAP_HDW (3 << 0) |
| #define R5XX_HOST_DATA0 0x17c0 |
| #define R5XX_HOST_DATA1 0x17c4 |
| #define R5XX_HOST_DATA2 0x17c8 |
| #define R5XX_HOST_DATA3 0x17cc |
| #define R5XX_HOST_DATA4 0x17d0 |
| #define R5XX_HOST_DATA5 0x17d4 |
| #define R5XX_HOST_DATA6 0x17d8 |
| #define R5XX_HOST_DATA7 0x17dc |
| #define R5XX_HOST_DATA_LAST 0x17e0 |
| #define R5XX_RB2D_DSTCACHE_MODE 0x3428 |
| # define R5XX_RB2D_DC_AUTOFLUSH_ENABLE (1 << 8) |
| # define R5XX_RB2D_DC_DISABLE_IGNORE_PE (1 << 17) |
| #define R5XX_GB_TILE_CONFIG 0x4018 |
| # define R5XX_ENABLE_TILING (1 << 0) |
| # define R5XX_PIPE_COUNT_RV350 (0 << 1) |
| # define R5XX_PIPE_COUNT_R300 (3 << 1) |
| # define R5XX_PIPE_COUNT_R420_3P (6 << 1) |
| # define R5XX_PIPE_COUNT_R420 (7 << 1) |
| # define R5XX_TILE_SIZE_8 (0 << 4) |
| # define R5XX_TILE_SIZE_16 (1 << 4) |
| # define R5XX_TILE_SIZE_32 (2 << 4) |
| # define R5XX_SUBPIXEL_1_12 (0 << 16) |
| # define R5XX_SUBPIXEL_1_16 (1 << 16) |
| #endif /* _R5XX_2DREGS_H */ |
| /drivers/old/ati2d/radeon_chipinfo_gen.h |
|---|
| 0,0 → 1,306 |
| /* This file is autogenerated please do not edit */ |
| RADEONCardInfo RADEONCards[] = { |
| { 0x3150, CHIP_FAMILY_RV380, 1, 0, 0, 0, 0 }, |
| { 0x3151, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 }, |
| { 0x3152, CHIP_FAMILY_RV380, 1, 0, 0, 0, 0 }, |
| { 0x3154, CHIP_FAMILY_RV380, 1, 0, 0, 0, 0 }, |
| { 0x3E50, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 }, |
| { 0x3E54, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 }, |
| { 0x4136, CHIP_FAMILY_RS100, 0, 1, 0, 0, 1 }, |
| { 0x4137, CHIP_FAMILY_RS200, 0, 1, 0, 0, 1 }, |
| { 0x4144, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 }, |
| { 0x4145, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 }, |
| { 0x4146, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 }, |
| { 0x4147, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 }, |
| { 0x4148, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 }, |
| { 0x4149, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 }, |
| { 0x414A, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 }, |
| { 0x414B, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 }, |
| { 0x4150, CHIP_FAMILY_RV350, 0, 0, 0, 0, 0 }, |
| { 0x4151, CHIP_FAMILY_RV350, 0, 0, 0, 0, 0 }, |
| { 0x4152, CHIP_FAMILY_RV350, 0, 0, 0, 0, 0 }, |
| { 0x4153, CHIP_FAMILY_RV350, 0, 0, 0, 0, 0 }, |
| { 0x4154, CHIP_FAMILY_RV350, 0, 0, 0, 0, 0 }, |
| { 0x4155, CHIP_FAMILY_RV350, 0, 0, 0, 0, 0 }, |
| { 0x4156, CHIP_FAMILY_RV350, 0, 0, 0, 0, 0 }, |
| { 0x4237, CHIP_FAMILY_RS200, 0, 1, 0, 0, 1 }, |
| { 0x4242, CHIP_FAMILY_R200, 0, 0, 0, 1, 0 }, |
| { 0x4243, CHIP_FAMILY_R200, 0, 0, 0, 1, 0 }, |
| { 0x4336, CHIP_FAMILY_RS100, 1, 1, 0, 0, 1 }, |
| { 0x4337, CHIP_FAMILY_RS200, 1, 1, 0, 0, 1 }, |
| { 0x4437, CHIP_FAMILY_RS200, 1, 1, 0, 0, 1 }, |
| { 0x4966, CHIP_FAMILY_RV250, 0, 0, 0, 0, 0 }, |
| { 0x4967, CHIP_FAMILY_RV250, 0, 0, 0, 0, 0 }, |
| { 0x4A48, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, |
| { 0x4A49, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, |
| { 0x4A4A, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, |
| { 0x4A4B, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, |
| { 0x4A4C, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, |
| { 0x4A4D, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, |
| { 0x4A4E, CHIP_FAMILY_R420, 1, 0, 0, 0, 0 }, |
| { 0x4A4F, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, |
| { 0x4A50, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, |
| { 0x4B49, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, |
| { 0x4B4A, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, |
| { 0x4B4B, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, |
| { 0x4B4C, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, |
| { 0x4C57, CHIP_FAMILY_RV200, 1, 0, 0, 0, 0 }, |
| { 0x4C58, CHIP_FAMILY_RV200, 1, 0, 0, 0, 0 }, |
| { 0x4C59, CHIP_FAMILY_RV100, 1, 0, 0, 0, 0 }, |
| { 0x4C5A, CHIP_FAMILY_RV100, 1, 0, 0, 0, 0 }, |
| { 0x4C64, CHIP_FAMILY_RV250, 1, 0, 0, 0, 0 }, |
| { 0x4C66, CHIP_FAMILY_RV250, 1, 0, 0, 0, 0 }, |
| { 0x4C67, CHIP_FAMILY_RV250, 1, 0, 0, 0, 0 }, |
| { 0x4E44, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 }, |
| { 0x4E45, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 }, |
| { 0x4E46, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 }, |
| { 0x4E47, CHIP_FAMILY_R300, 0, 0, 0, 0, 0 }, |
| { 0x4E48, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 }, |
| { 0x4E49, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 }, |
| { 0x4E4A, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 }, |
| { 0x4E4B, CHIP_FAMILY_R350, 0, 0, 0, 0, 0 }, |
| { 0x4E50, CHIP_FAMILY_RV350, 1, 0, 0, 0, 0 }, |
| { 0x4E51, CHIP_FAMILY_RV350, 1, 0, 0, 0, 0 }, |
| { 0x4E52, CHIP_FAMILY_RV350, 1, 0, 0, 0, 0 }, |
| { 0x4E53, CHIP_FAMILY_RV350, 1, 0, 0, 0, 0 }, |
| { 0x4E54, CHIP_FAMILY_RV350, 1, 0, 0, 0, 0 }, |
| { 0x4E56, CHIP_FAMILY_RV350, 1, 0, 0, 0, 0 }, |
| { 0x5144, CHIP_FAMILY_RADEON, 0, 0, 1, 1, 0 }, |
| { 0x5145, CHIP_FAMILY_RADEON, 0, 0, 1, 1, 0 }, |
| { 0x5146, CHIP_FAMILY_RADEON, 0, 0, 1, 1, 0 }, |
| { 0x5147, CHIP_FAMILY_RADEON, 0, 0, 1, 1, 0 }, |
| { 0x5148, CHIP_FAMILY_R200, 0, 0, 0, 1, 0 }, |
| { 0x514C, CHIP_FAMILY_R200, 0, 0, 0, 1, 0 }, |
| { 0x514D, CHIP_FAMILY_R200, 0, 0, 0, 1, 0 }, |
| { 0x5157, CHIP_FAMILY_RV200, 0, 0, 0, 0, 0 }, |
| { 0x5158, CHIP_FAMILY_RV200, 0, 0, 0, 0, 0 }, |
| { 0x5159, CHIP_FAMILY_RV100, 0, 0, 0, 0, 0 }, |
| { 0x515A, CHIP_FAMILY_RV100, 0, 0, 0, 0, 0 }, |
| { 0x515E, CHIP_FAMILY_RV100, 0, 0, 1, 0, 0 }, |
| { 0x5460, CHIP_FAMILY_RV380, 1, 0, 0, 0, 0 }, |
| { 0x5462, CHIP_FAMILY_RV380, 1, 0, 0, 0, 0 }, |
| { 0x5464, CHIP_FAMILY_RV380, 1, 0, 0, 0, 0 }, |
| { 0x5548, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, |
| { 0x5549, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, |
| { 0x554A, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, |
| { 0x554B, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, |
| { 0x554C, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, |
| { 0x554D, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, |
| { 0x554E, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, |
| { 0x554F, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, |
| { 0x5550, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, |
| { 0x5551, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, |
| { 0x5552, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, |
| { 0x5554, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, |
| { 0x564A, CHIP_FAMILY_RV410, 1, 0, 0, 0, 0 }, |
| { 0x564B, CHIP_FAMILY_RV410, 1, 0, 0, 0, 0 }, |
| { 0x564F, CHIP_FAMILY_RV410, 1, 0, 0, 0, 0 }, |
| { 0x5652, CHIP_FAMILY_RV410, 1, 0, 0, 0, 0 }, |
| { 0x5653, CHIP_FAMILY_RV410, 1, 0, 0, 0, 0 }, |
| { 0x5657, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 }, |
| { 0x5834, CHIP_FAMILY_RS300, 0, 1, 0, 0, 1 }, |
| { 0x5835, CHIP_FAMILY_RS300, 1, 1, 0, 0, 1 }, |
| { 0x5954, CHIP_FAMILY_RS480, 0, 1, 0, 0, 1 }, |
| { 0x5955, CHIP_FAMILY_RS480, 1, 1, 0, 0, 1 }, |
| { 0x5960, CHIP_FAMILY_RV280, 0, 0, 0, 0, 0 }, |
| { 0x5961, CHIP_FAMILY_RV280, 0, 0, 0, 0, 0 }, |
| { 0x5962, CHIP_FAMILY_RV280, 0, 0, 0, 0, 0 }, |
| { 0x5964, CHIP_FAMILY_RV280, 0, 0, 0, 0, 0 }, |
| { 0x5965, CHIP_FAMILY_RV280, 0, 0, 0, 0, 0 }, |
| { 0x5969, CHIP_FAMILY_RV100, 0, 0, 1, 0, 0 }, |
| { 0x5974, CHIP_FAMILY_RS480, 1, 1, 0, 0, 1 }, |
| { 0x5975, CHIP_FAMILY_RS480, 1, 1, 0, 0, 1 }, |
| { 0x5A41, CHIP_FAMILY_RS400, 0, 1, 0, 0, 1 }, |
| { 0x5A42, CHIP_FAMILY_RS400, 1, 1, 0, 0, 1 }, |
| { 0x5A61, CHIP_FAMILY_RS400, 0, 1, 0, 0, 1 }, |
| { 0x5A62, CHIP_FAMILY_RS400, 1, 1, 0, 0, 1 }, |
| { 0x5B60, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 }, |
| { 0x5B62, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 }, |
| { 0x5B63, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 }, |
| { 0x5B64, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 }, |
| { 0x5B65, CHIP_FAMILY_RV380, 0, 0, 0, 0, 0 }, |
| { 0x5C61, CHIP_FAMILY_RV280, 1, 0, 0, 0, 0 }, |
| { 0x5C63, CHIP_FAMILY_RV280, 1, 0, 0, 0, 0 }, |
| { 0x5D48, CHIP_FAMILY_R420, 1, 0, 0, 0, 0 }, |
| { 0x5D49, CHIP_FAMILY_R420, 1, 0, 0, 0, 0 }, |
| { 0x5D4A, CHIP_FAMILY_R420, 1, 0, 0, 0, 0 }, |
| { 0x5D4C, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, |
| { 0x5D4D, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, |
| { 0x5D4E, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, |
| { 0x5D4F, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, |
| { 0x5D50, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, |
| { 0x5D52, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, |
| { 0x5D57, CHIP_FAMILY_R420, 0, 0, 0, 0, 0 }, |
| { 0x5E48, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 }, |
| { 0x5E4A, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 }, |
| { 0x5E4B, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 }, |
| { 0x5E4C, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 }, |
| { 0x5E4D, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 }, |
| { 0x5E4F, CHIP_FAMILY_RV410, 0, 0, 0, 0, 0 }, |
| { 0x7100, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 }, |
| { 0x7101, CHIP_FAMILY_R520, 1, 0, 0, 0, 0 }, |
| { 0x7102, CHIP_FAMILY_R520, 1, 0, 0, 0, 0 }, |
| { 0x7103, CHIP_FAMILY_R520, 1, 0, 0, 0, 0 }, |
| { 0x7104, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 }, |
| { 0x7105, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 }, |
| { 0x7106, CHIP_FAMILY_R520, 1, 0, 0, 0, 0 }, |
| { 0x7108, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 }, |
| { 0x7109, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 }, |
| { 0x710A, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 }, |
| { 0x710B, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 }, |
| { 0x710C, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 }, |
| { 0x710E, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 }, |
| { 0x710F, CHIP_FAMILY_R520, 0, 0, 0, 0, 0 }, |
| { 0x7140, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, |
| { 0x7141, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, |
| { 0x7142, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, |
| { 0x7143, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, |
| { 0x7144, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 }, |
| { 0x7145, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 }, |
| { 0x7146, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, |
| { 0x7147, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, |
| { 0x7149, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 }, |
| { 0x714A, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 }, |
| { 0x714B, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 }, |
| { 0x714C, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 }, |
| { 0x714D, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, |
| { 0x714E, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, |
| { 0x714F, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, |
| { 0x7151, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, |
| { 0x7152, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, |
| { 0x7153, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, |
| { 0x715E, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, |
| { 0x715F, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, |
| { 0x7180, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, |
| { 0x7181, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, |
| { 0x7183, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, |
| { 0x7186, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 }, |
| { 0x7187, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, |
| { 0x7188, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 }, |
| { 0x718A, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 }, |
| { 0x718B, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 }, |
| { 0x718C, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 }, |
| { 0x718D, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 }, |
| { 0x718F, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, |
| { 0x7193, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, |
| { 0x7196, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 }, |
| { 0x719B, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, |
| { 0x719F, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, |
| { 0x71C0, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 }, |
| { 0x71C1, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 }, |
| { 0x71C2, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 }, |
| { 0x71C3, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 }, |
| { 0x71C4, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 }, |
| { 0x71C5, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 }, |
| { 0x71C6, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 }, |
| { 0x71C7, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 }, |
| { 0x71CD, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 }, |
| { 0x71CE, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 }, |
| { 0x71D2, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 }, |
| { 0x71D4, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 }, |
| { 0x71D5, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 }, |
| { 0x71D6, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 }, |
| { 0x71DA, CHIP_FAMILY_RV530, 0, 0, 0, 0, 0 }, |
| { 0x71DE, CHIP_FAMILY_RV530, 1, 0, 0, 0, 0 }, |
| { 0x7200, CHIP_FAMILY_RV515, 0, 0, 0, 0, 0 }, |
| { 0x7210, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 }, |
| { 0x7211, CHIP_FAMILY_RV515, 1, 0, 0, 0, 0 }, |
| { 0x7240, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, |
| { 0x7243, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, |
| { 0x7244, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, |
| { 0x7245, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, |
| { 0x7246, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, |
| { 0x7247, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, |
| { 0x7248, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, |
| { 0x7249, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, |
| { 0x724A, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, |
| { 0x724B, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, |
| { 0x724C, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, |
| { 0x724D, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, |
| { 0x724E, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, |
| { 0x724F, CHIP_FAMILY_R580, 0, 0, 0, 0, 0 }, |
| { 0x7280, CHIP_FAMILY_RV570, 0, 0, 0, 0, 0 }, |
| { 0x7281, CHIP_FAMILY_RV560, 0, 0, 0, 0, 0 }, |
| { 0x7283, CHIP_FAMILY_RV560, 0, 0, 0, 0, 0 }, |
| { 0x7284, CHIP_FAMILY_R580, 1, 0, 0, 0, 0 }, |
| { 0x7287, CHIP_FAMILY_RV560, 0, 0, 0, 0, 0 }, |
| { 0x7288, CHIP_FAMILY_RV570, 0, 0, 0, 0, 0 }, |
| { 0x7289, CHIP_FAMILY_RV570, 0, 0, 0, 0, 0 }, |
| { 0x728B, CHIP_FAMILY_RV570, 0, 0, 0, 0, 0 }, |
| { 0x728C, CHIP_FAMILY_RV570, 0, 0, 0, 0, 0 }, |
| { 0x7290, CHIP_FAMILY_RV560, 0, 0, 0, 0, 0 }, |
| { 0x7291, CHIP_FAMILY_RV560, 0, 0, 0, 0, 0 }, |
| { 0x7293, CHIP_FAMILY_RV560, 0, 0, 0, 0, 0 }, |
| { 0x7297, CHIP_FAMILY_RV560, 0, 0, 0, 0, 0 }, |
| { 0x7834, CHIP_FAMILY_RS300, 0, 1, 0, 0, 1 }, |
| { 0x7835, CHIP_FAMILY_RS300, 1, 1, 0, 0, 1 }, |
| { 0x791E, CHIP_FAMILY_RS690, 0, 1, 0, 0, 1 }, |
| { 0x791F, CHIP_FAMILY_RS690, 0, 1, 0, 0, 1 }, |
| { 0x793F, CHIP_FAMILY_RS600, 0, 1, 0, 0, 1 }, |
| { 0x7941, CHIP_FAMILY_RS600, 0, 1, 0, 0, 1 }, |
| { 0x7942, CHIP_FAMILY_RS600, 0, 1, 0, 0, 1 }, |
| { 0x796C, CHIP_FAMILY_RS740, 0, 1, 0, 0, 1 }, |
| { 0x796D, CHIP_FAMILY_RS740, 0, 1, 0, 0, 1 }, |
| { 0x796E, CHIP_FAMILY_RS740, 0, 1, 0, 0, 1 }, |
| { 0x796F, CHIP_FAMILY_RS740, 0, 1, 0, 0, 1 }, |
| { 0x9400, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 }, |
| { 0x9401, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 }, |
| { 0x9402, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 }, |
| { 0x9403, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 }, |
| { 0x9405, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 }, |
| { 0x940A, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 }, |
| { 0x940B, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 }, |
| { 0x940F, CHIP_FAMILY_R600, 0, 0, 0, 0, 0 }, |
| { 0x9440, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 }, |
| { 0x9441, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 }, |
| { 0x9442, CHIP_FAMILY_RV770, 0, 0, 0, 0, 0 }, |
| { 0x94C0, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 }, |
| { 0x94C1, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 }, |
| { 0x94C3, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 }, |
| { 0x94C4, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 }, |
| { 0x94C5, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 }, |
| { 0x94C6, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 }, |
| { 0x94C7, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 }, |
| { 0x94C8, CHIP_FAMILY_RV610, 1, 0, 0, 0, 0 }, |
| { 0x94C9, CHIP_FAMILY_RV610, 1, 0, 0, 0, 0 }, |
| { 0x94CB, CHIP_FAMILY_RV610, 1, 0, 0, 0, 0 }, |
| { 0x94CC, CHIP_FAMILY_RV610, 0, 0, 0, 0, 0 }, |
| { 0x9500, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 }, |
| { 0x9501, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 }, |
| { 0x9505, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 }, |
| { 0x9507, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 }, |
| { 0x950F, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 }, |
| { 0x9511, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 }, |
| { 0x9515, CHIP_FAMILY_RV670, 0, 0, 0, 0, 0 }, |
| { 0x9580, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 }, |
| { 0x9581, CHIP_FAMILY_RV630, 1, 0, 0, 0, 0 }, |
| { 0x9583, CHIP_FAMILY_RV630, 1, 0, 0, 0, 0 }, |
| { 0x9586, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 }, |
| { 0x9587, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 }, |
| { 0x9588, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 }, |
| { 0x9589, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 }, |
| { 0x958A, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 }, |
| { 0x958B, CHIP_FAMILY_RV630, 1, 0, 0, 0, 0 }, |
| { 0x958C, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 }, |
| { 0x958D, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 }, |
| { 0x958E, CHIP_FAMILY_RV630, 0, 0, 0, 0, 0 }, |
| { 0x95C0, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 }, |
| { 0x95C5, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 }, |
| { 0x95C7, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 }, |
| { 0x95C2, CHIP_FAMILY_RV620, 1, 0, 0, 0, 0 }, |
| { 0x95C4, CHIP_FAMILY_RV620, 1, 0, 0, 0, 0 }, |
| { 0x95CD, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 }, |
| { 0x95CE, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 }, |
| { 0x95CF, CHIP_FAMILY_RV620, 0, 0, 0, 0, 0 }, |
| { 0x9590, CHIP_FAMILY_RV635, 0, 0, 0, 0, 0 }, |
| { 0x9596, CHIP_FAMILY_RV635, 0, 0, 0, 0, 0 }, |
| { 0x9597, CHIP_FAMILY_RV635, 0, 0, 0, 0, 0 }, |
| { 0x9598, CHIP_FAMILY_RV635, 0, 0, 0, 0, 0 }, |
| { 0x9599, CHIP_FAMILY_RV635, 0, 0, 0, 0, 0 }, |
| { 0x9591, CHIP_FAMILY_RV635, 1, 0, 0, 0, 0 }, |
| { 0x9593, CHIP_FAMILY_RV635, 1, 0, 0, 0, 0 }, |
| { 0x9610, CHIP_FAMILY_RS780, 0, 1, 0, 0, 1 }, |
| { 0x9611, CHIP_FAMILY_RS780, 0, 1, 0, 0, 1 }, |
| { 0x9612, CHIP_FAMILY_RS780, 0, 1, 0, 0, 1 }, |
| { 0x9613, CHIP_FAMILY_RS780, 0, 1, 0, 0, 1 }, |
| }; |
| /drivers/old/ati2d/radeon_chipset_gen.h |
|---|
| 0,0 → 1,307 |
| /* This file is autogenerated please do not edit */ |
| static SymTabRec RADEONChipsets[] = { |
| { PCI_CHIP_RV380_3150, "ATI Radeon Mobility X600 (M24) 3150 (PCIE)" }, |
| { PCI_CHIP_RV380_3151, "ATI FireMV 2400 (PCI)" }, |
| { PCI_CHIP_RV380_3152, "ATI Radeon Mobility X300 (M24) 3152 (PCIE)" }, |
| { PCI_CHIP_RV380_3154, "ATI FireGL M24 GL 3154 (PCIE)" }, |
| { PCI_CHIP_RV380_3E50, "ATI Radeon X600 (RV380) 3E50 (PCIE)" }, |
| { PCI_CHIP_RV380_3E54, "ATI FireGL V3200 (RV380) 3E54 (PCIE)" }, |
| { PCI_CHIP_RS100_4136, "ATI Radeon IGP320 (A3) 4136" }, |
| { PCI_CHIP_RS200_4137, "ATI Radeon IGP330/340/350 (A4) 4137" }, |
| { PCI_CHIP_R300_AD, "ATI Radeon 9500 AD (AGP)" }, |
| { PCI_CHIP_R300_AE, "ATI Radeon 9500 AE (AGP)" }, |
| { PCI_CHIP_R300_AF, "ATI Radeon 9600TX AF (AGP)" }, |
| { PCI_CHIP_R300_AG, "ATI FireGL Z1 AG (AGP)" }, |
| { PCI_CHIP_R350_AH, "ATI Radeon 9800SE AH (AGP)" }, |
| { PCI_CHIP_R350_AI, "ATI Radeon 9800 AI (AGP)" }, |
| { PCI_CHIP_R350_AJ, "ATI Radeon 9800 AJ (AGP)" }, |
| { PCI_CHIP_R350_AK, "ATI FireGL X2 AK (AGP)" }, |
| { PCI_CHIP_RV350_AP, "ATI Radeon 9600 AP (AGP)" }, |
| { PCI_CHIP_RV350_AQ, "ATI Radeon 9600SE AQ (AGP)" }, |
| { PCI_CHIP_RV360_AR, "ATI Radeon 9600XT AR (AGP)" }, |
| { PCI_CHIP_RV350_AS, "ATI Radeon 9600 AS (AGP)" }, |
| { PCI_CHIP_RV350_AT, "ATI FireGL T2 AT (AGP)" }, |
| { PCI_CHIP_RV350_4155, "ATI Radeon 9650" }, |
| { PCI_CHIP_RV350_AV, "ATI FireGL RV360 AV (AGP)" }, |
| { PCI_CHIP_RS250_4237, "ATI Radeon 7000 IGP (A4+) 4237" }, |
| { PCI_CHIP_R200_BB, "ATI Radeon 8500 AIW BB (AGP)" }, |
| { PCI_CHIP_R200_BC, "ATI Radeon 8500 AIW BC (AGP)" }, |
| { PCI_CHIP_RS100_4336, "ATI Radeon IGP320M (U1) 4336" }, |
| { PCI_CHIP_RS200_4337, "ATI Radeon IGP330M/340M/350M (U2) 4337" }, |
| { PCI_CHIP_RS250_4437, "ATI Radeon Mobility 7000 IGP 4437" }, |
| { PCI_CHIP_RV250_If, "ATI Radeon 9000/PRO If (AGP/PCI)" }, |
| { PCI_CHIP_RV250_Ig, "ATI Radeon 9000 Ig (AGP/PCI)" }, |
| { PCI_CHIP_R420_JH, "ATI Radeon X800 (R420) JH (AGP)" }, |
| { PCI_CHIP_R420_JI, "ATI Radeon X800PRO (R420) JI (AGP)" }, |
| { PCI_CHIP_R420_JJ, "ATI Radeon X800SE (R420) JJ (AGP)" }, |
| { PCI_CHIP_R420_JK, "ATI Radeon X800 (R420) JK (AGP)" }, |
| { PCI_CHIP_R420_JL, "ATI Radeon X800 (R420) JL (AGP)" }, |
| { PCI_CHIP_R420_JM, "ATI FireGL X3 (R420) JM (AGP)" }, |
| { PCI_CHIP_R420_JN, "ATI Radeon Mobility 9800 (M18) JN (AGP)" }, |
| { PCI_CHIP_R420_4A4F, "ATI Radeon X800 SE (R420) (AGP)" }, |
| { PCI_CHIP_R420_JP, "ATI Radeon X800XT (R420) JP (AGP)" }, |
| { PCI_CHIP_R481_4B49, "ATI Radeon X850 XT (R480) (AGP)" }, |
| { PCI_CHIP_R481_4B4A, "ATI Radeon X850 SE (R480) (AGP)" }, |
| { PCI_CHIP_R481_4B4B, "ATI Radeon X850 PRO (R480) (AGP)" }, |
| { PCI_CHIP_R481_4B4C, "ATI Radeon X850 XT PE (R480) (AGP)" }, |
| { PCI_CHIP_RADEON_LW, "ATI Radeon Mobility M7 LW (AGP)" }, |
| { PCI_CHIP_RADEON_LX, "ATI Mobility FireGL 7800 M7 LX (AGP)" }, |
| { PCI_CHIP_RADEON_LY, "ATI Radeon Mobility M6 LY (AGP)" }, |
| { PCI_CHIP_RADEON_LZ, "ATI Radeon Mobility M6 LZ (AGP)" }, |
| { PCI_CHIP_RV250_Ld, "ATI FireGL Mobility 9000 (M9) Ld (AGP)" }, |
| { PCI_CHIP_RV250_Lf, "ATI Radeon Mobility 9000 (M9) Lf (AGP)" }, |
| { PCI_CHIP_RV250_Lg, "ATI Radeon Mobility 9000 (M9) Lg (AGP)" }, |
| { PCI_CHIP_R300_ND, "ATI Radeon 9700 Pro ND (AGP)" }, |
| { PCI_CHIP_R300_NE, "ATI Radeon 9700/9500Pro NE (AGP)" }, |
| { PCI_CHIP_R300_NF, "ATI Radeon 9600TX NF (AGP)" }, |
| { PCI_CHIP_R300_NG, "ATI FireGL X1 NG (AGP)" }, |
| { PCI_CHIP_R350_NH, "ATI Radeon 9800PRO NH (AGP)" }, |
| { PCI_CHIP_R350_NI, "ATI Radeon 9800 NI (AGP)" }, |
| { PCI_CHIP_R360_NJ, "ATI FireGL X2 NK (AGP)" }, |
| { PCI_CHIP_R350_NK, "ATI Radeon 9800XT NJ (AGP)" }, |
| { PCI_CHIP_RV350_NP, "ATI Radeon Mobility 9600/9700 (M10/M11) NP (AGP)" }, |
| { PCI_CHIP_RV350_NQ, "ATI Radeon Mobility 9600 (M10) NQ (AGP)" }, |
| { PCI_CHIP_RV350_NR, "ATI Radeon Mobility 9600 (M11) NR (AGP)" }, |
| { PCI_CHIP_RV350_NS, "ATI Radeon Mobility 9600 (M10) NS (AGP)" }, |
| { PCI_CHIP_RV350_NT, "ATI FireGL Mobility T2 (M10) NT (AGP)" }, |
| { PCI_CHIP_RV350_NV, "ATI FireGL Mobility T2e (M11) NV (AGP)" }, |
| { PCI_CHIP_RADEON_QD, "ATI Radeon QD (AGP)" }, |
| { PCI_CHIP_RADEON_QE, "ATI Radeon QE (AGP)" }, |
| { PCI_CHIP_RADEON_QF, "ATI Radeon QF (AGP)" }, |
| { PCI_CHIP_RADEON_QG, "ATI Radeon QG (AGP)" }, |
| { PCI_CHIP_R200_QH, "ATI FireGL 8700/8800 QH (AGP)" }, |
| { PCI_CHIP_R200_QL, "ATI Radeon 8500 QL (AGP)" }, |
| { PCI_CHIP_R200_QM, "ATI Radeon 9100 QM (AGP)" }, |
| { PCI_CHIP_RV200_QW, "ATI Radeon 7500 QW (AGP/PCI)" }, |
| { PCI_CHIP_RV200_QX, "ATI Radeon 7500 QX (AGP/PCI)" }, |
| { PCI_CHIP_RV100_QY, "ATI Radeon VE/7000 QY (AGP/PCI)" }, |
| { PCI_CHIP_RV100_QZ, "ATI Radeon VE/7000 QZ (AGP/PCI)" }, |
| { PCI_CHIP_RN50_515E, "ATI ES1000 515E (PCI)" }, |
| { PCI_CHIP_RV370_5460, "ATI Radeon Mobility X300 (M22) 5460 (PCIE)" }, |
| { PCI_CHIP_RV370_5462, "ATI Radeon Mobility X600 SE (M24C) 5462 (PCIE)" }, |
| { PCI_CHIP_RV370_5464, "ATI FireGL M22 GL 5464 (PCIE)" }, |
| { PCI_CHIP_R423_UH, "ATI Radeon X800 (R423) UH (PCIE)" }, |
| { PCI_CHIP_R423_UI, "ATI Radeon X800PRO (R423) UI (PCIE)" }, |
| { PCI_CHIP_R423_UJ, "ATI Radeon X800LE (R423) UJ (PCIE)" }, |
| { PCI_CHIP_R423_UK, "ATI Radeon X800SE (R423) UK (PCIE)" }, |
| { PCI_CHIP_R430_554C, "ATI Radeon X800 XTP (R430) (PCIE)" }, |
| { PCI_CHIP_R430_554D, "ATI Radeon X800 XL (R430) (PCIE)" }, |
| { PCI_CHIP_R430_554E, "ATI Radeon X800 SE (R430) (PCIE)" }, |
| { PCI_CHIP_R430_554F, "ATI Radeon X800 (R430) (PCIE)" }, |
| { PCI_CHIP_R423_5550, "ATI FireGL V7100 (R423) (PCIE)" }, |
| { PCI_CHIP_R423_UQ, "ATI FireGL V5100 (R423) UQ (PCIE)" }, |
| { PCI_CHIP_R423_UR, "ATI FireGL unknown (R423) UR (PCIE)" }, |
| { PCI_CHIP_R423_UT, "ATI FireGL unknown (R423) UT (PCIE)" }, |
| { PCI_CHIP_RV410_564A, "ATI Mobility FireGL V5000 (M26) (PCIE)" }, |
| { PCI_CHIP_RV410_564B, "ATI Mobility FireGL V5000 (M26) (PCIE)" }, |
| { PCI_CHIP_RV410_564F, "ATI Mobility Radeon X700 XL (M26) (PCIE)" }, |
| { PCI_CHIP_RV410_5652, "ATI Mobility Radeon X700 (M26) (PCIE)" }, |
| { PCI_CHIP_RV410_5653, "ATI Mobility Radeon X700 (M26) (PCIE)" }, |
| { PCI_CHIP_RV410_5657, "ATI Radeon X550XTX 5657 (PCIE)" }, |
| { PCI_CHIP_RS300_5834, "ATI Radeon 9100 IGP (A5) 5834" }, |
| { PCI_CHIP_RS300_5835, "ATI Radeon Mobility 9100 IGP (U3) 5835" }, |
| { PCI_CHIP_RS480_5954, "ATI Radeon XPRESS 200 5954 (PCIE)" }, |
| { PCI_CHIP_RS480_5955, "ATI Radeon XPRESS 200M 5955 (PCIE)" }, |
| { PCI_CHIP_RV280_5960, "ATI Radeon 9250 5960 (AGP)" }, |
| { PCI_CHIP_RV280_5961, "ATI Radeon 9200 5961 (AGP)" }, |
| { PCI_CHIP_RV280_5962, "ATI Radeon 9200 5962 (AGP)" }, |
| { PCI_CHIP_RV280_5964, "ATI Radeon 9200SE 5964 (AGP)" }, |
| { PCI_CHIP_RV280_5965, "ATI FireMV 2200 (PCI)" }, |
| { PCI_CHIP_RN50_5969, "ATI ES1000 5969 (PCI)" }, |
| { PCI_CHIP_RS482_5974, "ATI Radeon XPRESS 200 5974 (PCIE)" }, |
| { PCI_CHIP_RS485_5975, "ATI Radeon XPRESS 200M 5975 (PCIE)" }, |
| { PCI_CHIP_RS400_5A41, "ATI Radeon XPRESS 200 5A41 (PCIE)" }, |
| { PCI_CHIP_RS400_5A42, "ATI Radeon XPRESS 200M 5A42 (PCIE)" }, |
| { PCI_CHIP_RC410_5A61, "ATI Radeon XPRESS 200 5A61 (PCIE)" }, |
| { PCI_CHIP_RC410_5A62, "ATI Radeon XPRESS 200M 5A62 (PCIE)" }, |
| { PCI_CHIP_RV370_5B60, "ATI Radeon X300 (RV370) 5B60 (PCIE)" }, |
| { PCI_CHIP_RV370_5B62, "ATI Radeon X600 (RV370) 5B62 (PCIE)" }, |
| { PCI_CHIP_RV370_5B63, "ATI Radeon X550 (RV370) 5B63 (PCIE)" }, |
| { PCI_CHIP_RV370_5B64, "ATI FireGL V3100 (RV370) 5B64 (PCIE)" }, |
| { PCI_CHIP_RV370_5B65, "ATI FireMV 2200 PCIE (RV370) 5B65 (PCIE)" }, |
| { PCI_CHIP_RV280_5C61, "ATI Radeon Mobility 9200 (M9+) 5C61 (AGP)" }, |
| { PCI_CHIP_RV280_5C63, "ATI Radeon Mobility 9200 (M9+) 5C63 (AGP)" }, |
| { PCI_CHIP_R430_5D48, "ATI Mobility Radeon X800 XT (M28) (PCIE)" }, |
| { PCI_CHIP_R430_5D49, "ATI Mobility FireGL V5100 (M28) (PCIE)" }, |
| { PCI_CHIP_R430_5D4A, "ATI Mobility Radeon X800 (M28) (PCIE)" }, |
| { PCI_CHIP_R480_5D4C, "ATI Radeon X850 5D4C (PCIE)" }, |
| { PCI_CHIP_R480_5D4D, "ATI Radeon X850 XT PE (R480) (PCIE)" }, |
| { PCI_CHIP_R480_5D4E, "ATI Radeon X850 SE (R480) (PCIE)" }, |
| { PCI_CHIP_R480_5D4F, "ATI Radeon X850 PRO (R480) (PCIE)" }, |
| { PCI_CHIP_R480_5D50, "ATI unknown Radeon / FireGL (R480) 5D50 (PCIE)" }, |
| { PCI_CHIP_R480_5D52, "ATI Radeon X850 XT (R480) (PCIE)" }, |
| { PCI_CHIP_R423_5D57, "ATI Radeon X800XT (R423) 5D57 (PCIE)" }, |
| { PCI_CHIP_RV410_5E48, "ATI FireGL V5000 (RV410) (PCIE)" }, |
| { PCI_CHIP_RV410_5E4A, "ATI Radeon X700 XT (RV410) (PCIE)" }, |
| { PCI_CHIP_RV410_5E4B, "ATI Radeon X700 PRO (RV410) (PCIE)" }, |
| { PCI_CHIP_RV410_5E4C, "ATI Radeon X700 SE (RV410) (PCIE)" }, |
| { PCI_CHIP_RV410_5E4D, "ATI Radeon X700 (RV410) (PCIE)" }, |
| { PCI_CHIP_RV410_5E4F, "ATI Radeon X700 SE (RV410) (PCIE)" }, |
| { PCI_CHIP_R520_7100, "ATI Radeon X1800" }, |
| { PCI_CHIP_R520_7101, "ATI Mobility Radeon X1800 XT" }, |
| { PCI_CHIP_R520_7102, "ATI Mobility Radeon X1800" }, |
| { PCI_CHIP_R520_7103, "ATI Mobility FireGL V7200" }, |
| { PCI_CHIP_R520_7104, "ATI FireGL V7200" }, |
| { PCI_CHIP_R520_7105, "ATI FireGL V5300" }, |
| { PCI_CHIP_R520_7106, "ATI Mobility FireGL V7100" }, |
| { PCI_CHIP_R520_7108, "ATI Radeon X1800" }, |
| { PCI_CHIP_R520_7109, "ATI Radeon X1800" }, |
| { PCI_CHIP_R520_710A, "ATI Radeon X1800" }, |
| { PCI_CHIP_R520_710B, "ATI Radeon X1800" }, |
| { PCI_CHIP_R520_710C, "ATI Radeon X1800" }, |
| { PCI_CHIP_R520_710E, "ATI FireGL V7300" }, |
| { PCI_CHIP_R520_710F, "ATI FireGL V7350" }, |
| { PCI_CHIP_RV515_7140, "ATI Radeon X1600" }, |
| { PCI_CHIP_RV515_7141, "ATI RV505" }, |
| { PCI_CHIP_RV515_7142, "ATI Radeon X1300/X1550" }, |
| { PCI_CHIP_RV515_7143, "ATI Radeon X1550" }, |
| { PCI_CHIP_RV515_7144, "ATI M54-GL" }, |
| { PCI_CHIP_RV515_7145, "ATI Mobility Radeon X1400" }, |
| { PCI_CHIP_RV515_7146, "ATI Radeon X1300/X1550" }, |
| { PCI_CHIP_RV515_7147, "ATI Radeon X1550 64-bit" }, |
| { PCI_CHIP_RV515_7149, "ATI Mobility Radeon X1300" }, |
| { PCI_CHIP_RV515_714A, "ATI Mobility Radeon X1300" }, |
| { PCI_CHIP_RV515_714B, "ATI Mobility Radeon X1300" }, |
| { PCI_CHIP_RV515_714C, "ATI Mobility Radeon X1300" }, |
| { PCI_CHIP_RV515_714D, "ATI Radeon X1300" }, |
| { PCI_CHIP_RV515_714E, "ATI Radeon X1300" }, |
| { PCI_CHIP_RV515_714F, "ATI RV505" }, |
| { PCI_CHIP_RV515_7151, "ATI RV505" }, |
| { PCI_CHIP_RV515_7152, "ATI FireGL V3300" }, |
| { PCI_CHIP_RV515_7153, "ATI FireGL V3350" }, |
| { PCI_CHIP_RV515_715E, "ATI Radeon X1300" }, |
| { PCI_CHIP_RV515_715F, "ATI Radeon X1550 64-bit" }, |
| { PCI_CHIP_RV515_7180, "ATI Radeon X1300/X1550" }, |
| { PCI_CHIP_RV515_7181, "ATI Radeon X1600" }, |
| { PCI_CHIP_RV515_7183, "ATI Radeon X1300/X1550" }, |
| { PCI_CHIP_RV515_7186, "ATI Mobility Radeon X1450" }, |
| { PCI_CHIP_RV515_7187, "ATI Radeon X1300/X1550" }, |
| { PCI_CHIP_RV515_7188, "ATI Mobility Radeon X2300" }, |
| { PCI_CHIP_RV515_718A, "ATI Mobility Radeon X2300" }, |
| { PCI_CHIP_RV515_718B, "ATI Mobility Radeon X1350" }, |
| { PCI_CHIP_RV515_718C, "ATI Mobility Radeon X1350" }, |
| { PCI_CHIP_RV515_718D, "ATI Mobility Radeon X1450" }, |
| { PCI_CHIP_RV515_718F, "ATI Radeon X1300" }, |
| { PCI_CHIP_RV515_7193, "ATI Radeon X1550" }, |
| { PCI_CHIP_RV515_7196, "ATI Mobility Radeon X1350" }, |
| { PCI_CHIP_RV515_719B, "ATI FireMV 2250" }, |
| { PCI_CHIP_RV515_719F, "ATI Radeon X1550 64-bit" }, |
| { PCI_CHIP_RV530_71C0, "ATI Radeon X1600" }, |
| { PCI_CHIP_RV530_71C1, "ATI Radeon X1650" }, |
| { PCI_CHIP_RV530_71C2, "ATI Radeon X1600" }, |
| { PCI_CHIP_RV530_71C3, "ATI Radeon X1600" }, |
| { PCI_CHIP_RV530_71C4, "ATI Mobility FireGL V5200" }, |
| { PCI_CHIP_RV530_71C5, "ATI Mobility Radeon X1600" }, |
| { PCI_CHIP_RV530_71C6, "ATI Radeon X1650" }, |
| { PCI_CHIP_RV530_71C7, "ATI Radeon X1650" }, |
| { PCI_CHIP_RV530_71CD, "ATI Radeon X1600" }, |
| { PCI_CHIP_RV530_71CE, "ATI Radeon X1300 XT/X1600 Pro" }, |
| { PCI_CHIP_RV530_71D2, "ATI FireGL V3400" }, |
| { PCI_CHIP_RV530_71D4, "ATI Mobility FireGL V5250" }, |
| { PCI_CHIP_RV530_71D5, "ATI Mobility Radeon X1700" }, |
| { PCI_CHIP_RV530_71D6, "ATI Mobility Radeon X1700 XT" }, |
| { PCI_CHIP_RV530_71DA, "ATI FireGL V5200" }, |
| { PCI_CHIP_RV530_71DE, "ATI Mobility Radeon X1700" }, |
| { PCI_CHIP_RV515_7200, "ATI Radeon X2300HD" }, |
| { PCI_CHIP_RV515_7210, "ATI Mobility Radeon HD 2300" }, |
| { PCI_CHIP_RV515_7211, "ATI Mobility Radeon HD 2300" }, |
| { PCI_CHIP_R580_7240, "ATI Radeon X1950" }, |
| { PCI_CHIP_R580_7243, "ATI Radeon X1900" }, |
| { PCI_CHIP_R580_7244, "ATI Radeon X1950" }, |
| { PCI_CHIP_R580_7245, "ATI Radeon X1900" }, |
| { PCI_CHIP_R580_7246, "ATI Radeon X1900" }, |
| { PCI_CHIP_R580_7247, "ATI Radeon X1900" }, |
| { PCI_CHIP_R580_7248, "ATI Radeon X1900" }, |
| { PCI_CHIP_R580_7249, "ATI Radeon X1900" }, |
| { PCI_CHIP_R580_724A, "ATI Radeon X1900" }, |
| { PCI_CHIP_R580_724B, "ATI Radeon X1900" }, |
| { PCI_CHIP_R580_724C, "ATI Radeon X1900" }, |
| { PCI_CHIP_R580_724D, "ATI Radeon X1900" }, |
| { PCI_CHIP_R580_724E, "ATI AMD Stream Processor" }, |
| { PCI_CHIP_R580_724F, "ATI Radeon X1900" }, |
| { PCI_CHIP_RV570_7280, "ATI Radeon X1950" }, |
| { PCI_CHIP_RV560_7281, "ATI RV560" }, |
| { PCI_CHIP_RV560_7283, "ATI RV560" }, |
| { PCI_CHIP_R580_7284, "ATI Mobility Radeon X1900" }, |
| { PCI_CHIP_RV560_7287, "ATI RV560" }, |
| { PCI_CHIP_RV570_7288, "ATI Radeon X1950 GT" }, |
| { PCI_CHIP_RV570_7289, "ATI RV570" }, |
| { PCI_CHIP_RV570_728B, "ATI RV570" }, |
| { PCI_CHIP_RV570_728C, "ATI ATI FireGL V7400" }, |
| { PCI_CHIP_RV560_7290, "ATI RV560" }, |
| { PCI_CHIP_RV560_7291, "ATI Radeon X1650" }, |
| { PCI_CHIP_RV560_7293, "ATI Radeon X1650" }, |
| { PCI_CHIP_RV560_7297, "ATI RV560" }, |
| { PCI_CHIP_RS350_7834, "ATI Radeon 9100 PRO IGP 7834" }, |
| { PCI_CHIP_RS350_7835, "ATI Radeon Mobility 9200 IGP 7835" }, |
| { PCI_CHIP_RS690_791E, "ATI Radeon X1200" }, |
| { PCI_CHIP_RS690_791F, "ATI Radeon X1200" }, |
| { PCI_CHIP_RS600_793F, "ATI Radeon X1200" }, |
| { PCI_CHIP_RS600_7941, "ATI Radeon X1200" }, |
| { PCI_CHIP_RS600_7942, "ATI Radeon X1200" }, |
| { PCI_CHIP_RS740_796C, "ATI RS740" }, |
| { PCI_CHIP_RS740_796D, "ATI RS740M" }, |
| { PCI_CHIP_RS740_796E, "ATI RS740" }, |
| { PCI_CHIP_RS740_796F, "ATI RS740M" }, |
| { PCI_CHIP_R600_9400, "ATI Radeon HD 2900 XT" }, |
| { PCI_CHIP_R600_9401, "ATI Radeon HD 2900 XT" }, |
| { PCI_CHIP_R600_9402, "ATI Radeon HD 2900 XT" }, |
| { PCI_CHIP_R600_9403, "ATI Radeon HD 2900 Pro" }, |
| { PCI_CHIP_R600_9405, "ATI Radeon HD 2900 GT" }, |
| { PCI_CHIP_R600_940A, "ATI FireGL V8650" }, |
| { PCI_CHIP_R600_940B, "ATI FireGL V8600" }, |
| { PCI_CHIP_R600_940F, "ATI FireGL V7600" }, |
| { PCI_CHIP_RV770_9440, "ATI Radeon 4800 Series" }, |
| { PCI_CHIP_RV770_9441, "ATI Radeon HD 4870 x2" }, |
| { PCI_CHIP_RV770_9442, "ATI Radeon 4800 Series" }, |
| { PCI_CHIP_RV610_94C0, "ATI RV610" }, |
| { PCI_CHIP_RV610_94C1, "ATI Radeon HD 2400 XT" }, |
| { PCI_CHIP_RV610_94C3, "ATI Radeon HD 2400 Pro" }, |
| { PCI_CHIP_RV610_94C4, "ATI Radeon HD 2400 PRO AGP" }, |
| { PCI_CHIP_RV610_94C5, "ATI FireGL V4000" }, |
| { PCI_CHIP_RV610_94C6, "ATI RV610" }, |
| { PCI_CHIP_RV610_94C7, "ATI ATI Radeon HD 2350" }, |
| { PCI_CHIP_RV610_94C8, "ATI Mobility Radeon HD 2400 XT" }, |
| { PCI_CHIP_RV610_94C9, "ATI Mobility Radeon HD 2400" }, |
| { PCI_CHIP_RV610_94CB, "ATI RADEON E2400" }, |
| { PCI_CHIP_RV610_94CC, "ATI RV610" }, |
| { PCI_CHIP_RV670_9500, "ATI RV670" }, |
| { PCI_CHIP_RV670_9501, "ATI Radeon HD3870" }, |
| { PCI_CHIP_RV670_9505, "ATI Radeon HD3850" }, |
| { PCI_CHIP_RV670_9507, "ATI RV670" }, |
| { PCI_CHIP_RV670_950F, "ATI Radeon HD3870 X2" }, |
| { PCI_CHIP_RV670_9511, "ATI FireGL V7700" }, |
| { PCI_CHIP_RV670_9515, "ATI Radeon HD3850" }, |
| { PCI_CHIP_RV630_9580, "ATI RV630" }, |
| { PCI_CHIP_RV630_9581, "ATI Mobility Radeon HD 2600" }, |
| { PCI_CHIP_RV630_9583, "ATI Mobility Radeon HD 2600 XT" }, |
| { PCI_CHIP_RV630_9586, "ATI Radeon HD 2600 XT AGP" }, |
| { PCI_CHIP_RV630_9587, "ATI Radeon HD 2600 Pro AGP" }, |
| { PCI_CHIP_RV630_9588, "ATI Radeon HD 2600 XT" }, |
| { PCI_CHIP_RV630_9589, "ATI Radeon HD 2600 Pro" }, |
| { PCI_CHIP_RV630_958A, "ATI Gemini RV630" }, |
| { PCI_CHIP_RV630_958B, "ATI Gemini Mobility Radeon HD 2600 XT" }, |
| { PCI_CHIP_RV630_958C, "ATI FireGL V5600" }, |
| { PCI_CHIP_RV630_958D, "ATI FireGL V3600" }, |
| { PCI_CHIP_RV630_958E, "ATI Radeon HD 2600 LE" }, |
| { PCI_CHIP_RV620_95C0, "ATI Radeon HD 3470" }, |
| { PCI_CHIP_RV620_95C5, "ATI Radeon HD 3450" }, |
| { PCI_CHIP_RV620_95C7, "ATI Radeon HD 3430" }, |
| { PCI_CHIP_RV620_95C2, "ATI Mobility Radeon HD 3430" }, |
| { PCI_CHIP_RV620_95C4, "ATI Mobility Radeon HD 3400 Series" }, |
| { PCI_CHIP_RV620_95CD, "ATI FireMV 2450" }, |
| { PCI_CHIP_RV620_95CE, "ATI FireMV 2260" }, |
| { PCI_CHIP_RV620_95CF, "ATI FireMV 2260" }, |
| { PCI_CHIP_RV635_9590, "ATI ATI Radeon HD 3600 Series" }, |
| { PCI_CHIP_RV635_9596, "ATI ATI Radeon HD 3650 AGP" }, |
| { PCI_CHIP_RV635_9597, "ATI ATI Radeon HD 3600 PRO" }, |
| { PCI_CHIP_RV635_9598, "ATI ATI Radeon HD 3600 XT" }, |
| { PCI_CHIP_RV635_9599, "ATI ATI Radeon HD 3600 PRO" }, |
| { PCI_CHIP_RV635_9591, "ATI Mobility Radeon HD 3650" }, |
| { PCI_CHIP_RV635_9593, "ATI Mobility Radeon HD 3670" }, |
| { PCI_CHIP_RS780_9610, "ATI Radeon HD 3200 Graphics" }, |
| { PCI_CHIP_RS780_9611, "ATI Radeon 3100 Graphics" }, |
| { PCI_CHIP_RS780_9612, "ATI Radeon HD 3200 Graphics" }, |
| { PCI_CHIP_RS780_9613, "ATI Radeon 3100 Graphics" }, |
| { -1, NULL } |
| }; |
| /drivers/old/ati2d/radeon_microcode.h |
|---|
| 0,0 → 1,1844 |
| /* |
| * Copyright 2007 Advanced Micro Devices, Inc. |
| * All Rights Reserved. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice (including the next |
| * paragraph) shall be included in all copies or substantial portions of the |
| * Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE |
| * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION |
| * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION |
| * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| * |
| */ |
| #ifndef RADEON_MICROCODE_H |
| #define RADEON_MICROCODE_H |
| /* production radeon ucode r1xx-r6xx */ |
| static const u32_t R100_cp_microcode[][2]={ |
| { 0x21007000, 0000000000 }, |
| { 0x20007000, 0000000000 }, |
| { 0x000000b4, 0x00000004 }, |
| { 0x000000b8, 0x00000004 }, |
| { 0x6f5b4d4c, 0000000000 }, |
| { 0x4c4c427f, 0000000000 }, |
| { 0x5b568a92, 0000000000 }, |
| { 0x4ca09c6d, 0000000000 }, |
| { 0xad4c4c4c, 0000000000 }, |
| { 0x4ce1af3d, 0000000000 }, |
| { 0xd8afafaf, 0000000000 }, |
| { 0xd64c4cdc, 0000000000 }, |
| { 0x4cd10d10, 0000000000 }, |
| { 0x000f0000, 0x00000016 }, |
| { 0x362f242d, 0000000000 }, |
| { 0x00000012, 0x00000004 }, |
| { 0x000f0000, 0x00000016 }, |
| { 0x362f282d, 0000000000 }, |
| { 0x000380e7, 0x00000002 }, |
| { 0x04002c97, 0x00000002 }, |
| { 0x000f0001, 0x00000016 }, |
| { 0x333a3730, 0000000000 }, |
| { 0x000077ef, 0x00000002 }, |
| { 0x00061000, 0x00000002 }, |
| { 0x00000021, 0x0000001a }, |
| { 0x00004000, 0x0000001e }, |
| { 0x00061000, 0x00000002 }, |
| { 0x00000021, 0x0000001a }, |
| { 0x00004000, 0x0000001e }, |
| { 0x00061000, 0x00000002 }, |
| { 0x00000021, 0x0000001a }, |
| { 0x00004000, 0x0000001e }, |
| { 0x00000017, 0x00000004 }, |
| { 0x0003802b, 0x00000002 }, |
| { 0x040067e0, 0x00000002 }, |
| { 0x00000017, 0x00000004 }, |
| { 0x000077e0, 0x00000002 }, |
| { 0x00065000, 0x00000002 }, |
| { 0x000037e1, 0x00000002 }, |
| { 0x040067e1, 0x00000006 }, |
| { 0x000077e0, 0x00000002 }, |
| { 0x000077e1, 0x00000002 }, |
| { 0x000077e1, 0x00000006 }, |
| { 0xffffffff, 0000000000 }, |
| { 0x10000000, 0000000000 }, |
| { 0x0003802b, 0x00000002 }, |
| { 0x040067e0, 0x00000006 }, |
| { 0x00007675, 0x00000002 }, |
| { 0x00007676, 0x00000002 }, |
| { 0x00007677, 0x00000002 }, |
| { 0x00007678, 0x00000006 }, |
| { 0x0003802c, 0x00000002 }, |
| { 0x04002676, 0x00000002 }, |
| { 0x00007677, 0x00000002 }, |
| { 0x00007678, 0x00000006 }, |
| { 0x0000002f, 0x00000018 }, |
| { 0x0000002f, 0x00000018 }, |
| { 0000000000, 0x00000006 }, |
| { 0x00000030, 0x00000018 }, |
| { 0x00000030, 0x00000018 }, |
| { 0000000000, 0x00000006 }, |
| { 0x01605000, 0x00000002 }, |
| { 0x00065000, 0x00000002 }, |
| { 0x00098000, 0x00000002 }, |
| { 0x00061000, 0x00000002 }, |
| { 0x64c0603e, 0x00000004 }, |
| { 0x000380e6, 0x00000002 }, |
| { 0x040025c5, 0x00000002 }, |
| { 0x00080000, 0x00000016 }, |
| { 0000000000, 0000000000 }, |
| { 0x0400251d, 0x00000002 }, |
| { 0x00007580, 0x00000002 }, |
| { 0x00067581, 0x00000002 }, |
| { 0x04002580, 0x00000002 }, |
| { 0x00067581, 0x00000002 }, |
| { 0x00000049, 0x00000004 }, |
| { 0x00005000, 0000000000 }, |
| { 0x000380e6, 0x00000002 }, |
| { 0x040025c5, 0x00000002 }, |
| { 0x00061000, 0x00000002 }, |
| { 0x0000750e, 0x00000002 }, |
| { 0x00019000, 0x00000002 }, |
| { 0x00011055, 0x00000014 }, |
| { 0x00000055, 0x00000012 }, |
| { 0x0400250f, 0x00000002 }, |
| { 0x0000504f, 0x00000004 }, |
| { 0x000380e6, 0x00000002 }, |
| { 0x040025c5, 0x00000002 }, |
| { 0x00007565, 0x00000002 }, |
| { 0x00007566, 0x00000002 }, |
| { 0x00000058, 0x00000004 }, |
| { 0x000380e6, 0x00000002 }, |
| { 0x040025c5, 0x00000002 }, |
| { 0x01e655b4, 0x00000002 }, |
| { 0x4401b0e4, 0x00000002 }, |
| { 0x01c110e4, 0x00000002 }, |
| { 0x26667066, 0x00000018 }, |
| { 0x040c2565, 0x00000002 }, |
| { 0x00000066, 0x00000018 }, |
| { 0x04002564, 0x00000002 }, |
| { 0x00007566, 0x00000002 }, |
| { 0x0000005d, 0x00000004 }, |
| { 0x00401069, 0x00000008 }, |
| { 0x00101000, 0x00000002 }, |
| { 0x000d80ff, 0x00000002 }, |
| { 0x0080006c, 0x00000008 }, |
| { 0x000f9000, 0x00000002 }, |
| { 0x000e00ff, 0x00000002 }, |
| { 0000000000, 0x00000006 }, |
| { 0x0000008f, 0x00000018 }, |
| { 0x0000005b, 0x00000004 }, |
| { 0x000380e6, 0x00000002 }, |
| { 0x040025c5, 0x00000002 }, |
| { 0x00007576, 0x00000002 }, |
| { 0x00065000, 0x00000002 }, |
| { 0x00009000, 0x00000002 }, |
| { 0x00041000, 0x00000002 }, |
| { 0x0c00350e, 0x00000002 }, |
| { 0x00049000, 0x00000002 }, |
| { 0x00051000, 0x00000002 }, |
| { 0x01e785f8, 0x00000002 }, |
| { 0x00200000, 0x00000002 }, |
| { 0x0060007e, 0x0000000c }, |
| { 0x00007563, 0x00000002 }, |
| { 0x006075f0, 0x00000021 }, |
| { 0x20007073, 0x00000004 }, |
| { 0x00005073, 0x00000004 }, |
| { 0x000380e6, 0x00000002 }, |
| { 0x040025c5, 0x00000002 }, |
| { 0x00007576, 0x00000002 }, |
| { 0x00007577, 0x00000002 }, |
| { 0x0000750e, 0x00000002 }, |
| { 0x0000750f, 0x00000002 }, |
| { 0x00a05000, 0x00000002 }, |
| { 0x00600083, 0x0000000c }, |
| { 0x006075f0, 0x00000021 }, |
| { 0x000075f8, 0x00000002 }, |
| { 0x00000083, 0x00000004 }, |
| { 0x000a750e, 0x00000002 }, |
| { 0x000380e6, 0x00000002 }, |
| { 0x040025c5, 0x00000002 }, |
| { 0x0020750f, 0x00000002 }, |
| { 0x00600086, 0x00000004 }, |
| { 0x00007570, 0x00000002 }, |
| { 0x00007571, 0x00000002 }, |
| { 0x00007572, 0x00000006 }, |
| { 0x000380e6, 0x00000002 }, |
| { 0x040025c5, 0x00000002 }, |
| { 0x00005000, 0x00000002 }, |
| { 0x00a05000, 0x00000002 }, |
| { 0x00007568, 0x00000002 }, |
| { 0x00061000, 0x00000002 }, |
| { 0x00000095, 0x0000000c }, |
| { 0x00058000, 0x00000002 }, |
| { 0x0c607562, 0x00000002 }, |
| { 0x00000097, 0x00000004 }, |
| { 0x000380e6, 0x00000002 }, |
| { 0x040025c5, 0x00000002 }, |
| { 0x00600096, 0x00000004 }, |
| { 0x400070e5, 0000000000 }, |
| { 0x000380e6, 0x00000002 }, |
| { 0x040025c5, 0x00000002 }, |
| { 0x000380e5, 0x00000002 }, |
| { 0x000000a8, 0x0000001c }, |
| { 0x000650aa, 0x00000018 }, |
| { 0x040025bb, 0x00000002 }, |
| { 0x000610ab, 0x00000018 }, |
| { 0x040075bc, 0000000000 }, |
| { 0x000075bb, 0x00000002 }, |
| { 0x000075bc, 0000000000 }, |
| { 0x00090000, 0x00000006 }, |
| { 0x00090000, 0x00000002 }, |
| { 0x000d8002, 0x00000006 }, |
| { 0x00007832, 0x00000002 }, |
| { 0x00005000, 0x00000002 }, |
| { 0x000380e7, 0x00000002 }, |
| { 0x04002c97, 0x00000002 }, |
| { 0x00007820, 0x00000002 }, |
| { 0x00007821, 0x00000002 }, |
| { 0x00007800, 0000000000 }, |
| { 0x01200000, 0x00000002 }, |
| { 0x20077000, 0x00000002 }, |
| { 0x01200000, 0x00000002 }, |
| { 0x20007000, 0x00000002 }, |
| { 0x00061000, 0x00000002 }, |
| { 0x0120751b, 0x00000002 }, |
| { 0x8040750a, 0x00000002 }, |
| { 0x8040750b, 0x00000002 }, |
| { 0x00110000, 0x00000002 }, |
| { 0x000380e5, 0x00000002 }, |
| { 0x000000c6, 0x0000001c }, |
| { 0x000610ab, 0x00000018 }, |
| { 0x844075bd, 0x00000002 }, |
| { 0x000610aa, 0x00000018 }, |
| { 0x840075bb, 0x00000002 }, |
| { 0x000610ab, 0x00000018 }, |
| { 0x844075bc, 0x00000002 }, |
| { 0x000000c9, 0x00000004 }, |
| { 0x804075bd, 0x00000002 }, |
| { 0x800075bb, 0x00000002 }, |
| { 0x804075bc, 0x00000002 }, |
| { 0x00108000, 0x00000002 }, |
| { 0x01400000, 0x00000002 }, |
| { 0x006000cd, 0x0000000c }, |
| { 0x20c07000, 0x00000020 }, |
| { 0x000000cf, 0x00000012 }, |
| { 0x00800000, 0x00000006 }, |
| { 0x0080751d, 0x00000006 }, |
| { 0000000000, 0000000000 }, |
| { 0x0000775c, 0x00000002 }, |
| { 0x00a05000, 0x00000002 }, |
| { 0x00661000, 0x00000002 }, |
| { 0x0460275d, 0x00000020 }, |
| { 0x00004000, 0000000000 }, |
| { 0x01e00830, 0x00000002 }, |
| { 0x21007000, 0000000000 }, |
| { 0x6464614d, 0000000000 }, |
| { 0x69687420, 0000000000 }, |
| { 0x00000073, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0x00005000, 0x00000002 }, |
| { 0x000380d0, 0x00000002 }, |
| { 0x040025e0, 0x00000002 }, |
| { 0x000075e1, 0000000000 }, |
| { 0x00000001, 0000000000 }, |
| { 0x000380e0, 0x00000002 }, |
| { 0x04002394, 0x00000002 }, |
| { 0x00005000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0x00000008, 0000000000 }, |
| { 0x00000004, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| }; |
| static const u32_t R200_cp_microcode[][2]={ |
| { 0x21007000, 0000000000 }, |
| { 0x20007000, 0000000000 }, |
| { 0x000000bf, 0x00000004 }, |
| { 0x000000c3, 0x00000004 }, |
| { 0x7a685e5d, 0000000000 }, |
| { 0x5d5d5588, 0000000000 }, |
| { 0x68659197, 0000000000 }, |
| { 0x5da19f78, 0000000000 }, |
| { 0x5d5d5d5d, 0000000000 }, |
| { 0x5dee5d50, 0000000000 }, |
| { 0xf2acacac, 0000000000 }, |
| { 0xe75df9e9, 0000000000 }, |
| { 0xb1dd0e11, 0000000000 }, |
| { 0xe2afafaf, 0000000000 }, |
| { 0x000f0000, 0x00000016 }, |
| { 0x452f232d, 0000000000 }, |
| { 0x00000013, 0x00000004 }, |
| { 0x000f0000, 0x00000016 }, |
| { 0x452f272d, 0000000000 }, |
| { 0x000f0001, 0x00000016 }, |
| { 0x3e4d4a37, 0000000000 }, |
| { 0x000077ef, 0x00000002 }, |
| { 0x00061000, 0x00000002 }, |
| { 0x00000020, 0x0000001a }, |
| { 0x00004000, 0x0000001e }, |
| { 0x00061000, 0x00000002 }, |
| { 0x00000020, 0x0000001a }, |
| { 0x00004000, 0x0000001e }, |
| { 0x00061000, 0x00000002 }, |
| { 0x00000020, 0x0000001a }, |
| { 0x00004000, 0x0000001e }, |
| { 0x00000016, 0x00000004 }, |
| { 0x0003802a, 0x00000002 }, |
| { 0x040067e0, 0x00000002 }, |
| { 0x00000016, 0x00000004 }, |
| { 0x000077e0, 0x00000002 }, |
| { 0x00065000, 0x00000002 }, |
| { 0x000037e1, 0x00000002 }, |
| { 0x040067e1, 0x00000006 }, |
| { 0x000077e0, 0x00000002 }, |
| { 0x000077e1, 0x00000002 }, |
| { 0x000077e1, 0x00000006 }, |
| { 0xffffffff, 0000000000 }, |
| { 0x10000000, 0000000000 }, |
| { 0x07f007f0, 0000000000 }, |
| { 0x0003802a, 0x00000002 }, |
| { 0x040067e0, 0x00000006 }, |
| { 0x0003802c, 0x00000002 }, |
| { 0x04002741, 0x00000002 }, |
| { 0x04002741, 0x00000002 }, |
| { 0x04002743, 0x00000002 }, |
| { 0x00007675, 0x00000002 }, |
| { 0x00007676, 0x00000002 }, |
| { 0x00007677, 0x00000002 }, |
| { 0x00007678, 0x00000006 }, |
| { 0x0003802c, 0x00000002 }, |
| { 0x04002741, 0x00000002 }, |
| { 0x04002741, 0x00000002 }, |
| { 0x04002743, 0x00000002 }, |
| { 0x00007676, 0x00000002 }, |
| { 0x00007677, 0x00000002 }, |
| { 0x00007678, 0x00000006 }, |
| { 0x0003802b, 0x00000002 }, |
| { 0x04002676, 0x00000002 }, |
| { 0x00007677, 0x00000002 }, |
| { 0x0003802c, 0x00000002 }, |
| { 0x04002741, 0x00000002 }, |
| { 0x04002743, 0x00000002 }, |
| { 0x00007678, 0x00000006 }, |
| { 0x0003802c, 0x00000002 }, |
| { 0x04002741, 0x00000002 }, |
| { 0x04002741, 0x00000002 }, |
| { 0x04002743, 0x00000002 }, |
| { 0x00007678, 0x00000006 }, |
| { 0x0000002f, 0x00000018 }, |
| { 0x0000002f, 0x00000018 }, |
| { 0000000000, 0x00000006 }, |
| { 0x00000037, 0x00000018 }, |
| { 0x00000037, 0x00000018 }, |
| { 0000000000, 0x00000006 }, |
| { 0x01605000, 0x00000002 }, |
| { 0x00065000, 0x00000002 }, |
| { 0x00098000, 0x00000002 }, |
| { 0x00061000, 0x00000002 }, |
| { 0x64c06051, 0x00000004 }, |
| { 0x00080000, 0x00000016 }, |
| { 0000000000, 0000000000 }, |
| { 0x0400251d, 0x00000002 }, |
| { 0x00007580, 0x00000002 }, |
| { 0x00067581, 0x00000002 }, |
| { 0x04002580, 0x00000002 }, |
| { 0x00067581, 0x00000002 }, |
| { 0x0000005a, 0x00000004 }, |
| { 0x00005000, 0000000000 }, |
| { 0x00061000, 0x00000002 }, |
| { 0x0000750e, 0x00000002 }, |
| { 0x00019000, 0x00000002 }, |
| { 0x00011064, 0x00000014 }, |
| { 0x00000064, 0x00000012 }, |
| { 0x0400250f, 0x00000002 }, |
| { 0x0000505e, 0x00000004 }, |
| { 0x00007565, 0x00000002 }, |
| { 0x00007566, 0x00000002 }, |
| { 0x00000065, 0x00000004 }, |
| { 0x01e655b4, 0x00000002 }, |
| { 0x4401b0f0, 0x00000002 }, |
| { 0x01c110f0, 0x00000002 }, |
| { 0x26667071, 0x00000018 }, |
| { 0x040c2565, 0x00000002 }, |
| { 0x00000071, 0x00000018 }, |
| { 0x04002564, 0x00000002 }, |
| { 0x00007566, 0x00000002 }, |
| { 0x00000068, 0x00000004 }, |
| { 0x00401074, 0x00000008 }, |
| { 0x00101000, 0x00000002 }, |
| { 0x000d80ff, 0x00000002 }, |
| { 0x00800077, 0x00000008 }, |
| { 0x000f9000, 0x00000002 }, |
| { 0x000e00ff, 0x00000002 }, |
| { 0000000000, 0x00000006 }, |
| { 0x00000094, 0x00000018 }, |
| { 0x00000068, 0x00000004 }, |
| { 0x00007576, 0x00000002 }, |
| { 0x00065000, 0x00000002 }, |
| { 0x00009000, 0x00000002 }, |
| { 0x00041000, 0x00000002 }, |
| { 0x0c00350e, 0x00000002 }, |
| { 0x00049000, 0x00000002 }, |
| { 0x00051000, 0x00000002 }, |
| { 0x01e785f8, 0x00000002 }, |
| { 0x00200000, 0x00000002 }, |
| { 0x00600087, 0x0000000c }, |
| { 0x00007563, 0x00000002 }, |
| { 0x006075f0, 0x00000021 }, |
| { 0x2000707c, 0x00000004 }, |
| { 0x0000507c, 0x00000004 }, |
| { 0x00007576, 0x00000002 }, |
| { 0x00007577, 0x00000002 }, |
| { 0x0000750e, 0x00000002 }, |
| { 0x0000750f, 0x00000002 }, |
| { 0x00a05000, 0x00000002 }, |
| { 0x0060008a, 0x0000000c }, |
| { 0x006075f0, 0x00000021 }, |
| { 0x000075f8, 0x00000002 }, |
| { 0x0000008a, 0x00000004 }, |
| { 0x000a750e, 0x00000002 }, |
| { 0x0020750f, 0x00000002 }, |
| { 0x0060008d, 0x00000004 }, |
| { 0x00007570, 0x00000002 }, |
| { 0x00007571, 0x00000002 }, |
| { 0x00007572, 0x00000006 }, |
| { 0x00005000, 0x00000002 }, |
| { 0x00a05000, 0x00000002 }, |
| { 0x00007568, 0x00000002 }, |
| { 0x00061000, 0x00000002 }, |
| { 0x00000098, 0x0000000c }, |
| { 0x00058000, 0x00000002 }, |
| { 0x0c607562, 0x00000002 }, |
| { 0x0000009a, 0x00000004 }, |
| { 0x00600099, 0x00000004 }, |
| { 0x400070f1, 0000000000 }, |
| { 0x000380f1, 0x00000002 }, |
| { 0x000000a7, 0x0000001c }, |
| { 0x000650a9, 0x00000018 }, |
| { 0x040025bb, 0x00000002 }, |
| { 0x000610aa, 0x00000018 }, |
| { 0x040075bc, 0000000000 }, |
| { 0x000075bb, 0x00000002 }, |
| { 0x000075bc, 0000000000 }, |
| { 0x00090000, 0x00000006 }, |
| { 0x00090000, 0x00000002 }, |
| { 0x000d8002, 0x00000006 }, |
| { 0x00005000, 0x00000002 }, |
| { 0x00007821, 0x00000002 }, |
| { 0x00007800, 0000000000 }, |
| { 0x00007821, 0x00000002 }, |
| { 0x00007800, 0000000000 }, |
| { 0x01665000, 0x00000002 }, |
| { 0x000a0000, 0x00000002 }, |
| { 0x000671cc, 0x00000002 }, |
| { 0x0286f1cd, 0x00000002 }, |
| { 0x000000b7, 0x00000010 }, |
| { 0x21007000, 0000000000 }, |
| { 0x000000be, 0x0000001c }, |
| { 0x00065000, 0x00000002 }, |
| { 0x000a0000, 0x00000002 }, |
| { 0x00061000, 0x00000002 }, |
| { 0x000b0000, 0x00000002 }, |
| { 0x38067000, 0x00000002 }, |
| { 0x000a00ba, 0x00000004 }, |
| { 0x20007000, 0000000000 }, |
| { 0x01200000, 0x00000002 }, |
| { 0x20077000, 0x00000002 }, |
| { 0x01200000, 0x00000002 }, |
| { 0x20007000, 0000000000 }, |
| { 0x00061000, 0x00000002 }, |
| { 0x0120751b, 0x00000002 }, |
| { 0x8040750a, 0x00000002 }, |
| { 0x8040750b, 0x00000002 }, |
| { 0x00110000, 0x00000002 }, |
| { 0x000380f1, 0x00000002 }, |
| { 0x000000d1, 0x0000001c }, |
| { 0x000610aa, 0x00000018 }, |
| { 0x844075bd, 0x00000002 }, |
| { 0x000610a9, 0x00000018 }, |
| { 0x840075bb, 0x00000002 }, |
| { 0x000610aa, 0x00000018 }, |
| { 0x844075bc, 0x00000002 }, |
| { 0x000000d4, 0x00000004 }, |
| { 0x804075bd, 0x00000002 }, |
| { 0x800075bb, 0x00000002 }, |
| { 0x804075bc, 0x00000002 }, |
| { 0x00108000, 0x00000002 }, |
| { 0x01400000, 0x00000002 }, |
| { 0x006000d8, 0x0000000c }, |
| { 0x20c07000, 0x00000020 }, |
| { 0x000000da, 0x00000012 }, |
| { 0x00800000, 0x00000006 }, |
| { 0x0080751d, 0x00000006 }, |
| { 0x000025bb, 0x00000002 }, |
| { 0x000040d4, 0x00000004 }, |
| { 0x0000775c, 0x00000002 }, |
| { 0x00a05000, 0x00000002 }, |
| { 0x00661000, 0x00000002 }, |
| { 0x0460275d, 0x00000020 }, |
| { 0x00004000, 0000000000 }, |
| { 0x00007999, 0x00000002 }, |
| { 0x00a05000, 0x00000002 }, |
| { 0x00661000, 0x00000002 }, |
| { 0x0460299b, 0x00000020 }, |
| { 0x00004000, 0000000000 }, |
| { 0x01e00830, 0x00000002 }, |
| { 0x21007000, 0000000000 }, |
| { 0x00005000, 0x00000002 }, |
| { 0x00038056, 0x00000002 }, |
| { 0x040025e0, 0x00000002 }, |
| { 0x000075e1, 0000000000 }, |
| { 0x00000001, 0000000000 }, |
| { 0x000380ed, 0x00000002 }, |
| { 0x04007394, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0x000078c4, 0x00000002 }, |
| { 0x000078c5, 0x00000002 }, |
| { 0x000078c6, 0x00000002 }, |
| { 0x00007924, 0x00000002 }, |
| { 0x00007925, 0x00000002 }, |
| { 0x00007926, 0x00000002 }, |
| { 0x000000f2, 0x00000004 }, |
| { 0x00007924, 0x00000002 }, |
| { 0x00007925, 0x00000002 }, |
| { 0x00007926, 0x00000002 }, |
| { 0x000000f9, 0x00000004 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| }; |
| static const u32_t R300_cp_microcode[][2]={ |
| { 0x4200e000, 0000000000 }, |
| { 0x4000e000, 0000000000 }, |
| { 0x000000ae, 0x00000008 }, |
| { 0x000000b2, 0x00000008 }, |
| { 0x67554b4a, 0000000000 }, |
| { 0x4a4a4475, 0000000000 }, |
| { 0x55527d83, 0000000000 }, |
| { 0x4a8c8b65, 0000000000 }, |
| { 0x4aef4af6, 0000000000 }, |
| { 0x4ae14a4a, 0000000000 }, |
| { 0xe4979797, 0000000000 }, |
| { 0xdb4aebdd, 0000000000 }, |
| { 0x9ccc4a4a, 0000000000 }, |
| { 0xd1989898, 0000000000 }, |
| { 0x4a0f9ad6, 0000000000 }, |
| { 0x000ca000, 0x00000004 }, |
| { 0x000d0012, 0x00000038 }, |
| { 0x0000e8b4, 0x00000004 }, |
| { 0x000d0014, 0x00000038 }, |
| { 0x0000e8b6, 0x00000004 }, |
| { 0x000d0016, 0x00000038 }, |
| { 0x0000e854, 0x00000004 }, |
| { 0x000d0018, 0x00000038 }, |
| { 0x0000e855, 0x00000004 }, |
| { 0x000d001a, 0x00000038 }, |
| { 0x0000e856, 0x00000004 }, |
| { 0x000d001c, 0x00000038 }, |
| { 0x0000e857, 0x00000004 }, |
| { 0x000d001e, 0x00000038 }, |
| { 0x0000e824, 0x00000004 }, |
| { 0x000d0020, 0x00000038 }, |
| { 0x0000e825, 0x00000004 }, |
| { 0x000d0022, 0x00000038 }, |
| { 0x0000e830, 0x00000004 }, |
| { 0x000d0024, 0x00000038 }, |
| { 0x0000f0c0, 0x00000004 }, |
| { 0x000d0026, 0x00000038 }, |
| { 0x0000f0c1, 0x00000004 }, |
| { 0x000d0028, 0x00000038 }, |
| { 0x0000f041, 0x00000004 }, |
| { 0x000d002a, 0x00000038 }, |
| { 0x0000f184, 0x00000004 }, |
| { 0x000d002c, 0x00000038 }, |
| { 0x0000f185, 0x00000004 }, |
| { 0x000d002e, 0x00000038 }, |
| { 0x0000f186, 0x00000004 }, |
| { 0x000d0030, 0x00000038 }, |
| { 0x0000f187, 0x00000004 }, |
| { 0x000d0032, 0x00000038 }, |
| { 0x0000f180, 0x00000004 }, |
| { 0x000d0034, 0x00000038 }, |
| { 0x0000f393, 0x00000004 }, |
| { 0x000d0036, 0x00000038 }, |
| { 0x0000f38a, 0x00000004 }, |
| { 0x000d0038, 0x00000038 }, |
| { 0x0000f38e, 0x00000004 }, |
| { 0x0000e821, 0x00000004 }, |
| { 0x0140a000, 0x00000004 }, |
| { 0x00000043, 0x00000018 }, |
| { 0x00cce800, 0x00000004 }, |
| { 0x001b0001, 0x00000004 }, |
| { 0x08004800, 0x00000004 }, |
| { 0x001b0001, 0x00000004 }, |
| { 0x08004800, 0x00000004 }, |
| { 0x001b0001, 0x00000004 }, |
| { 0x08004800, 0x00000004 }, |
| { 0x0000003a, 0x00000008 }, |
| { 0x0000a000, 0000000000 }, |
| { 0x2000451d, 0x00000004 }, |
| { 0x0000e580, 0x00000004 }, |
| { 0x000ce581, 0x00000004 }, |
| { 0x08004580, 0x00000004 }, |
| { 0x000ce581, 0x00000004 }, |
| { 0x00000047, 0x00000008 }, |
| { 0x0000a000, 0000000000 }, |
| { 0x000c2000, 0x00000004 }, |
| { 0x0000e50e, 0x00000004 }, |
| { 0x00032000, 0x00000004 }, |
| { 0x00022051, 0x00000028 }, |
| { 0x00000051, 0x00000024 }, |
| { 0x0800450f, 0x00000004 }, |
| { 0x0000a04b, 0x00000008 }, |
| { 0x0000e565, 0x00000004 }, |
| { 0x0000e566, 0x00000004 }, |
| { 0x00000052, 0x00000008 }, |
| { 0x03cca5b4, 0x00000004 }, |
| { 0x05432000, 0x00000004 }, |
| { 0x00022000, 0x00000004 }, |
| { 0x4ccce05e, 0x00000030 }, |
| { 0x08274565, 0x00000004 }, |
| { 0x0000005e, 0x00000030 }, |
| { 0x08004564, 0x00000004 }, |
| { 0x0000e566, 0x00000004 }, |
| { 0x00000055, 0x00000008 }, |
| { 0x00802061, 0x00000010 }, |
| { 0x00202000, 0x00000004 }, |
| { 0x001b00ff, 0x00000004 }, |
| { 0x01000064, 0x00000010 }, |
| { 0x001f2000, 0x00000004 }, |
| { 0x001c00ff, 0x00000004 }, |
| { 0000000000, 0x0000000c }, |
| { 0x00000080, 0x00000030 }, |
| { 0x00000055, 0x00000008 }, |
| { 0x0000e576, 0x00000004 }, |
| { 0x000ca000, 0x00000004 }, |
| { 0x00012000, 0x00000004 }, |
| { 0x00082000, 0x00000004 }, |
| { 0x1800650e, 0x00000004 }, |
| { 0x00092000, 0x00000004 }, |
| { 0x000a2000, 0x00000004 }, |
| { 0x000f0000, 0x00000004 }, |
| { 0x00400000, 0x00000004 }, |
| { 0x00000074, 0x00000018 }, |
| { 0x0000e563, 0x00000004 }, |
| { 0x00c0e5f9, 0x000000c2 }, |
| { 0x00000069, 0x00000008 }, |
| { 0x0000a069, 0x00000008 }, |
| { 0x0000e576, 0x00000004 }, |
| { 0x0000e577, 0x00000004 }, |
| { 0x0000e50e, 0x00000004 }, |
| { 0x0000e50f, 0x00000004 }, |
| { 0x0140a000, 0x00000004 }, |
| { 0x00000077, 0x00000018 }, |
| { 0x00c0e5f9, 0x000000c2 }, |
| { 0x00000077, 0x00000008 }, |
| { 0x0014e50e, 0x00000004 }, |
| { 0x0040e50f, 0x00000004 }, |
| { 0x00c0007a, 0x00000008 }, |
| { 0x0000e570, 0x00000004 }, |
| { 0x0000e571, 0x00000004 }, |
| { 0x0000e572, 0x0000000c }, |
| { 0x0000a000, 0x00000004 }, |
| { 0x0140a000, 0x00000004 }, |
| { 0x0000e568, 0x00000004 }, |
| { 0x000c2000, 0x00000004 }, |
| { 0x00000084, 0x00000018 }, |
| { 0x000b0000, 0x00000004 }, |
| { 0x18c0e562, 0x00000004 }, |
| { 0x00000086, 0x00000008 }, |
| { 0x00c00085, 0x00000008 }, |
| { 0x000700e3, 0x00000004 }, |
| { 0x00000092, 0x00000038 }, |
| { 0x000ca094, 0x00000030 }, |
| { 0x080045bb, 0x00000004 }, |
| { 0x000c2095, 0x00000030 }, |
| { 0x0800e5bc, 0000000000 }, |
| { 0x0000e5bb, 0x00000004 }, |
| { 0x0000e5bc, 0000000000 }, |
| { 0x00120000, 0x0000000c }, |
| { 0x00120000, 0x00000004 }, |
| { 0x001b0002, 0x0000000c }, |
| { 0x0000a000, 0x00000004 }, |
| { 0x0000e821, 0x00000004 }, |
| { 0x0000e800, 0000000000 }, |
| { 0x0000e821, 0x00000004 }, |
| { 0x0000e82e, 0000000000 }, |
| { 0x02cca000, 0x00000004 }, |
| { 0x00140000, 0x00000004 }, |
| { 0x000ce1cc, 0x00000004 }, |
| { 0x050de1cd, 0x00000004 }, |
| { 0x00400000, 0x00000004 }, |
| { 0x000000a4, 0x00000018 }, |
| { 0x00c0a000, 0x00000004 }, |
| { 0x000000a1, 0x00000008 }, |
| { 0x000000a6, 0x00000020 }, |
| { 0x4200e000, 0000000000 }, |
| { 0x000000ad, 0x00000038 }, |
| { 0x000ca000, 0x00000004 }, |
| { 0x00140000, 0x00000004 }, |
| { 0x000c2000, 0x00000004 }, |
| { 0x00160000, 0x00000004 }, |
| { 0x700ce000, 0x00000004 }, |
| { 0x001400a9, 0x00000008 }, |
| { 0x4000e000, 0000000000 }, |
| { 0x02400000, 0x00000004 }, |
| { 0x400ee000, 0x00000004 }, |
| { 0x02400000, 0x00000004 }, |
| { 0x4000e000, 0000000000 }, |
| { 0x000c2000, 0x00000004 }, |
| { 0x0240e51b, 0x00000004 }, |
| { 0x0080e50a, 0x00000005 }, |
| { 0x0080e50b, 0x00000005 }, |
| { 0x00220000, 0x00000004 }, |
| { 0x000700e3, 0x00000004 }, |
| { 0x000000c0, 0x00000038 }, |
| { 0x000c2095, 0x00000030 }, |
| { 0x0880e5bd, 0x00000005 }, |
| { 0x000c2094, 0x00000030 }, |
| { 0x0800e5bb, 0x00000005 }, |
| { 0x000c2095, 0x00000030 }, |
| { 0x0880e5bc, 0x00000005 }, |
| { 0x000000c3, 0x00000008 }, |
| { 0x0080e5bd, 0x00000005 }, |
| { 0x0000e5bb, 0x00000005 }, |
| { 0x0080e5bc, 0x00000005 }, |
| { 0x00210000, 0x00000004 }, |
| { 0x02800000, 0x00000004 }, |
| { 0x00c000c7, 0x00000018 }, |
| { 0x4180e000, 0x00000040 }, |
| { 0x000000c9, 0x00000024 }, |
| { 0x01000000, 0x0000000c }, |
| { 0x0100e51d, 0x0000000c }, |
| { 0x000045bb, 0x00000004 }, |
| { 0x000080c3, 0x00000008 }, |
| { 0x0000f3ce, 0x00000004 }, |
| { 0x0140a000, 0x00000004 }, |
| { 0x00cc2000, 0x00000004 }, |
| { 0x08c053cf, 0x00000040 }, |
| { 0x00008000, 0000000000 }, |
| { 0x0000f3d2, 0x00000004 }, |
| { 0x0140a000, 0x00000004 }, |
| { 0x00cc2000, 0x00000004 }, |
| { 0x08c053d3, 0x00000040 }, |
| { 0x00008000, 0000000000 }, |
| { 0x0000f39d, 0x00000004 }, |
| { 0x0140a000, 0x00000004 }, |
| { 0x00cc2000, 0x00000004 }, |
| { 0x08c0539e, 0x00000040 }, |
| { 0x00008000, 0000000000 }, |
| { 0x03c00830, 0x00000004 }, |
| { 0x4200e000, 0000000000 }, |
| { 0x0000a000, 0x00000004 }, |
| { 0x200045e0, 0x00000004 }, |
| { 0x0000e5e1, 0000000000 }, |
| { 0x00000001, 0000000000 }, |
| { 0x000700e0, 0x00000004 }, |
| { 0x0800e394, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0x0000e8c4, 0x00000004 }, |
| { 0x0000e8c5, 0x00000004 }, |
| { 0x0000e8c6, 0x00000004 }, |
| { 0x0000e928, 0x00000004 }, |
| { 0x0000e929, 0x00000004 }, |
| { 0x0000e92a, 0x00000004 }, |
| { 0x000000e4, 0x00000008 }, |
| { 0x0000e928, 0x00000004 }, |
| { 0x0000e929, 0x00000004 }, |
| { 0x0000e92a, 0x00000004 }, |
| { 0x000000eb, 0x00000008 }, |
| { 0x02c02000, 0x00000004 }, |
| { 0x00060000, 0x00000004 }, |
| { 0x000000f3, 0x00000034 }, |
| { 0x000000f0, 0x00000008 }, |
| { 0x00008000, 0x00000004 }, |
| { 0xc000e000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0x000c2000, 0x00000004 }, |
| { 0x001d0018, 0x00000004 }, |
| { 0x001a0001, 0x00000004 }, |
| { 0x000000fb, 0x00000034 }, |
| { 0x0000004a, 0x00000008 }, |
| { 0x0500a04a, 0x00000008 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| }; |
| static const u32_t R420_cp_microcode[][2]={ |
| { 0x4200e000, 0000000000 }, |
| { 0x4000e000, 0000000000 }, |
| { 0x00000099, 0x00000008 }, |
| { 0x0000009d, 0x00000008 }, |
| { 0x4a554b4a, 0000000000 }, |
| { 0x4a4a4467, 0000000000 }, |
| { 0x55526f75, 0000000000 }, |
| { 0x4a7e7d65, 0000000000 }, |
| { 0xd9d3dff6, 0000000000 }, |
| { 0x4ac54a4a, 0000000000 }, |
| { 0xc8828282, 0000000000 }, |
| { 0xbf4acfc1, 0000000000 }, |
| { 0x87b04a4a, 0000000000 }, |
| { 0xb5838383, 0000000000 }, |
| { 0x4a0f85ba, 0000000000 }, |
| { 0x000ca000, 0x00000004 }, |
| { 0x000d0012, 0x00000038 }, |
| { 0x0000e8b4, 0x00000004 }, |
| { 0x000d0014, 0x00000038 }, |
| { 0x0000e8b6, 0x00000004 }, |
| { 0x000d0016, 0x00000038 }, |
| { 0x0000e854, 0x00000004 }, |
| { 0x000d0018, 0x00000038 }, |
| { 0x0000e855, 0x00000004 }, |
| { 0x000d001a, 0x00000038 }, |
| { 0x0000e856, 0x00000004 }, |
| { 0x000d001c, 0x00000038 }, |
| { 0x0000e857, 0x00000004 }, |
| { 0x000d001e, 0x00000038 }, |
| { 0x0000e824, 0x00000004 }, |
| { 0x000d0020, 0x00000038 }, |
| { 0x0000e825, 0x00000004 }, |
| { 0x000d0022, 0x00000038 }, |
| { 0x0000e830, 0x00000004 }, |
| { 0x000d0024, 0x00000038 }, |
| { 0x0000f0c0, 0x00000004 }, |
| { 0x000d0026, 0x00000038 }, |
| { 0x0000f0c1, 0x00000004 }, |
| { 0x000d0028, 0x00000038 }, |
| { 0x0000f041, 0x00000004 }, |
| { 0x000d002a, 0x00000038 }, |
| { 0x0000f184, 0x00000004 }, |
| { 0x000d002c, 0x00000038 }, |
| { 0x0000f185, 0x00000004 }, |
| { 0x000d002e, 0x00000038 }, |
| { 0x0000f186, 0x00000004 }, |
| { 0x000d0030, 0x00000038 }, |
| { 0x0000f187, 0x00000004 }, |
| { 0x000d0032, 0x00000038 }, |
| { 0x0000f180, 0x00000004 }, |
| { 0x000d0034, 0x00000038 }, |
| { 0x0000f393, 0x00000004 }, |
| { 0x000d0036, 0x00000038 }, |
| { 0x0000f38a, 0x00000004 }, |
| { 0x000d0038, 0x00000038 }, |
| { 0x0000f38e, 0x00000004 }, |
| { 0x0000e821, 0x00000004 }, |
| { 0x0140a000, 0x00000004 }, |
| { 0x00000043, 0x00000018 }, |
| { 0x00cce800, 0x00000004 }, |
| { 0x001b0001, 0x00000004 }, |
| { 0x08004800, 0x00000004 }, |
| { 0x001b0001, 0x00000004 }, |
| { 0x08004800, 0x00000004 }, |
| { 0x001b0001, 0x00000004 }, |
| { 0x08004800, 0x00000004 }, |
| { 0x0000003a, 0x00000008 }, |
| { 0x0000a000, 0000000000 }, |
| { 0x2000451d, 0x00000004 }, |
| { 0x0000e580, 0x00000004 }, |
| { 0x000ce581, 0x00000004 }, |
| { 0x08004580, 0x00000004 }, |
| { 0x000ce581, 0x00000004 }, |
| { 0x00000047, 0x00000008 }, |
| { 0x0000a000, 0000000000 }, |
| { 0x000c2000, 0x00000004 }, |
| { 0x0000e50e, 0x00000004 }, |
| { 0x00032000, 0x00000004 }, |
| { 0x00022051, 0x00000028 }, |
| { 0x00000051, 0x00000024 }, |
| { 0x0800450f, 0x00000004 }, |
| { 0x0000a04b, 0x00000008 }, |
| { 0x0000e565, 0x00000004 }, |
| { 0x0000e566, 0x00000004 }, |
| { 0x00000052, 0x00000008 }, |
| { 0x03cca5b4, 0x00000004 }, |
| { 0x05432000, 0x00000004 }, |
| { 0x00022000, 0x00000004 }, |
| { 0x4ccce05e, 0x00000030 }, |
| { 0x08274565, 0x00000004 }, |
| { 0x0000005e, 0x00000030 }, |
| { 0x08004564, 0x00000004 }, |
| { 0x0000e566, 0x00000004 }, |
| { 0x00000055, 0x00000008 }, |
| { 0x00802061, 0x00000010 }, |
| { 0x00202000, 0x00000004 }, |
| { 0x001b00ff, 0x00000004 }, |
| { 0x01000064, 0x00000010 }, |
| { 0x001f2000, 0x00000004 }, |
| { 0x001c00ff, 0x00000004 }, |
| { 0000000000, 0x0000000c }, |
| { 0x00000072, 0x00000030 }, |
| { 0x00000055, 0x00000008 }, |
| { 0x0000e576, 0x00000004 }, |
| { 0x0000e577, 0x00000004 }, |
| { 0x0000e50e, 0x00000004 }, |
| { 0x0000e50f, 0x00000004 }, |
| { 0x0140a000, 0x00000004 }, |
| { 0x00000069, 0x00000018 }, |
| { 0x00c0e5f9, 0x000000c2 }, |
| { 0x00000069, 0x00000008 }, |
| { 0x0014e50e, 0x00000004 }, |
| { 0x0040e50f, 0x00000004 }, |
| { 0x00c0006c, 0x00000008 }, |
| { 0x0000e570, 0x00000004 }, |
| { 0x0000e571, 0x00000004 }, |
| { 0x0000e572, 0x0000000c }, |
| { 0x0000a000, 0x00000004 }, |
| { 0x0140a000, 0x00000004 }, |
| { 0x0000e568, 0x00000004 }, |
| { 0x000c2000, 0x00000004 }, |
| { 0x00000076, 0x00000018 }, |
| { 0x000b0000, 0x00000004 }, |
| { 0x18c0e562, 0x00000004 }, |
| { 0x00000078, 0x00000008 }, |
| { 0x00c00077, 0x00000008 }, |
| { 0x000700c7, 0x00000004 }, |
| { 0x00000080, 0x00000038 }, |
| { 0x0000e5bb, 0x00000004 }, |
| { 0x0000e5bc, 0000000000 }, |
| { 0x0000a000, 0x00000004 }, |
| { 0x0000e821, 0x00000004 }, |
| { 0x0000e800, 0000000000 }, |
| { 0x0000e821, 0x00000004 }, |
| { 0x0000e82e, 0000000000 }, |
| { 0x02cca000, 0x00000004 }, |
| { 0x00140000, 0x00000004 }, |
| { 0x000ce1cc, 0x00000004 }, |
| { 0x050de1cd, 0x00000004 }, |
| { 0x00400000, 0x00000004 }, |
| { 0x0000008f, 0x00000018 }, |
| { 0x00c0a000, 0x00000004 }, |
| { 0x0000008c, 0x00000008 }, |
| { 0x00000091, 0x00000020 }, |
| { 0x4200e000, 0000000000 }, |
| { 0x00000098, 0x00000038 }, |
| { 0x000ca000, 0x00000004 }, |
| { 0x00140000, 0x00000004 }, |
| { 0x000c2000, 0x00000004 }, |
| { 0x00160000, 0x00000004 }, |
| { 0x700ce000, 0x00000004 }, |
| { 0x00140094, 0x00000008 }, |
| { 0x4000e000, 0000000000 }, |
| { 0x02400000, 0x00000004 }, |
| { 0x400ee000, 0x00000004 }, |
| { 0x02400000, 0x00000004 }, |
| { 0x4000e000, 0000000000 }, |
| { 0x000c2000, 0x00000004 }, |
| { 0x0240e51b, 0x00000004 }, |
| { 0x0080e50a, 0x00000005 }, |
| { 0x0080e50b, 0x00000005 }, |
| { 0x00220000, 0x00000004 }, |
| { 0x000700c7, 0x00000004 }, |
| { 0x000000a4, 0x00000038 }, |
| { 0x0080e5bd, 0x00000005 }, |
| { 0x0000e5bb, 0x00000005 }, |
| { 0x0080e5bc, 0x00000005 }, |
| { 0x00210000, 0x00000004 }, |
| { 0x02800000, 0x00000004 }, |
| { 0x00c000ab, 0x00000018 }, |
| { 0x4180e000, 0x00000040 }, |
| { 0x000000ad, 0x00000024 }, |
| { 0x01000000, 0x0000000c }, |
| { 0x0100e51d, 0x0000000c }, |
| { 0x000045bb, 0x00000004 }, |
| { 0x000080a7, 0x00000008 }, |
| { 0x0000f3ce, 0x00000004 }, |
| { 0x0140a000, 0x00000004 }, |
| { 0x00cc2000, 0x00000004 }, |
| { 0x08c053cf, 0x00000040 }, |
| { 0x00008000, 0000000000 }, |
| { 0x0000f3d2, 0x00000004 }, |
| { 0x0140a000, 0x00000004 }, |
| { 0x00cc2000, 0x00000004 }, |
| { 0x08c053d3, 0x00000040 }, |
| { 0x00008000, 0000000000 }, |
| { 0x0000f39d, 0x00000004 }, |
| { 0x0140a000, 0x00000004 }, |
| { 0x00cc2000, 0x00000004 }, |
| { 0x08c0539e, 0x00000040 }, |
| { 0x00008000, 0000000000 }, |
| { 0x03c00830, 0x00000004 }, |
| { 0x4200e000, 0000000000 }, |
| { 0x0000a000, 0x00000004 }, |
| { 0x200045e0, 0x00000004 }, |
| { 0x0000e5e1, 0000000000 }, |
| { 0x00000001, 0000000000 }, |
| { 0x000700c4, 0x00000004 }, |
| { 0x0800e394, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0x0000e8c4, 0x00000004 }, |
| { 0x0000e8c5, 0x00000004 }, |
| { 0x0000e8c6, 0x00000004 }, |
| { 0x0000e928, 0x00000004 }, |
| { 0x0000e929, 0x00000004 }, |
| { 0x0000e92a, 0x00000004 }, |
| { 0x000000c8, 0x00000008 }, |
| { 0x0000e928, 0x00000004 }, |
| { 0x0000e929, 0x00000004 }, |
| { 0x0000e92a, 0x00000004 }, |
| { 0x000000cf, 0x00000008 }, |
| { 0x02c02000, 0x00000004 }, |
| { 0x00060000, 0x00000004 }, |
| { 0x000000d7, 0x00000034 }, |
| { 0x000000d4, 0x00000008 }, |
| { 0x00008000, 0x00000004 }, |
| { 0xc000e000, 0000000000 }, |
| { 0x0000e1cc, 0x00000004 }, |
| { 0x0500e1cd, 0x00000004 }, |
| { 0x000ca000, 0x00000004 }, |
| { 0x000000de, 0x00000034 }, |
| { 0x000000da, 0x00000008 }, |
| { 0x0000a000, 0000000000 }, |
| { 0x0019e1cc, 0x00000004 }, |
| { 0x001b0001, 0x00000004 }, |
| { 0x0500a000, 0x00000004 }, |
| { 0x080041cd, 0x00000004 }, |
| { 0x000ca000, 0x00000004 }, |
| { 0x000000fb, 0x00000034 }, |
| { 0x0000004a, 0x00000008 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0x000c2000, 0x00000004 }, |
| { 0x001d0018, 0x00000004 }, |
| { 0x001a0001, 0x00000004 }, |
| { 0x000000fb, 0x00000034 }, |
| { 0x0000004a, 0x00000008 }, |
| { 0x0500a04a, 0x00000008 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| }; |
| static const u32_t RS600_cp_microcode[][2]={ |
| { 0x4200e000, 0000000000 }, |
| { 0x4000e000, 0000000000 }, |
| { 0x000000a0, 0x00000008 }, |
| { 0x000000a4, 0x00000008 }, |
| { 0x4a554b4a, 0000000000 }, |
| { 0x4a4a4467, 0000000000 }, |
| { 0x55526f75, 0000000000 }, |
| { 0x4a7e7d65, 0000000000 }, |
| { 0x4ae74af6, 0000000000 }, |
| { 0x4ad34a4a, 0000000000 }, |
| { 0xd6898989, 0000000000 }, |
| { 0xcd4addcf, 0000000000 }, |
| { 0x8ebe4ae2, 0000000000 }, |
| { 0xc38a8a8a, 0000000000 }, |
| { 0x4a0f8cc8, 0000000000 }, |
| { 0x000ca000, 0x00000004 }, |
| { 0x000d0012, 0x00000038 }, |
| { 0x0000e8b4, 0x00000004 }, |
| { 0x000d0014, 0x00000038 }, |
| { 0x0000e8b6, 0x00000004 }, |
| { 0x000d0016, 0x00000038 }, |
| { 0x0000e854, 0x00000004 }, |
| { 0x000d0018, 0x00000038 }, |
| { 0x0000e855, 0x00000004 }, |
| { 0x000d001a, 0x00000038 }, |
| { 0x0000e856, 0x00000004 }, |
| { 0x000d001c, 0x00000038 }, |
| { 0x0000e857, 0x00000004 }, |
| { 0x000d001e, 0x00000038 }, |
| { 0x0000e824, 0x00000004 }, |
| { 0x000d0020, 0x00000038 }, |
| { 0x0000e825, 0x00000004 }, |
| { 0x000d0022, 0x00000038 }, |
| { 0x0000e830, 0x00000004 }, |
| { 0x000d0024, 0x00000038 }, |
| { 0x0000f0c0, 0x00000004 }, |
| { 0x000d0026, 0x00000038 }, |
| { 0x0000f0c1, 0x00000004 }, |
| { 0x000d0028, 0x00000038 }, |
| { 0x0000f041, 0x00000004 }, |
| { 0x000d002a, 0x00000038 }, |
| { 0x0000f184, 0x00000004 }, |
| { 0x000d002c, 0x00000038 }, |
| { 0x0000f185, 0x00000004 }, |
| { 0x000d002e, 0x00000038 }, |
| { 0x0000f186, 0x00000004 }, |
| { 0x000d0030, 0x00000038 }, |
| { 0x0000f187, 0x00000004 }, |
| { 0x000d0032, 0x00000038 }, |
| { 0x0000f180, 0x00000004 }, |
| { 0x000d0034, 0x00000038 }, |
| { 0x0000f393, 0x00000004 }, |
| { 0x000d0036, 0x00000038 }, |
| { 0x0000f38a, 0x00000004 }, |
| { 0x000d0038, 0x00000038 }, |
| { 0x0000f38e, 0x00000004 }, |
| { 0x0000e821, 0x00000004 }, |
| { 0x0140a000, 0x00000004 }, |
| { 0x00000043, 0x00000018 }, |
| { 0x00cce800, 0x00000004 }, |
| { 0x001b0001, 0x00000004 }, |
| { 0x08004800, 0x00000004 }, |
| { 0x001b0001, 0x00000004 }, |
| { 0x08004800, 0x00000004 }, |
| { 0x001b0001, 0x00000004 }, |
| { 0x08004800, 0x00000004 }, |
| { 0x0000003a, 0x00000008 }, |
| { 0x0000a000, 0000000000 }, |
| { 0x2000451d, 0x00000004 }, |
| { 0x0000e580, 0x00000004 }, |
| { 0x000ce581, 0x00000004 }, |
| { 0x08004580, 0x00000004 }, |
| { 0x000ce581, 0x00000004 }, |
| { 0x00000047, 0x00000008 }, |
| { 0x0000a000, 0000000000 }, |
| { 0x000c2000, 0x00000004 }, |
| { 0x0000e50e, 0x00000004 }, |
| { 0x00032000, 0x00000004 }, |
| { 0x00022051, 0x00000028 }, |
| { 0x00000051, 0x00000024 }, |
| { 0x0800450f, 0x00000004 }, |
| { 0x0000a04b, 0x00000008 }, |
| { 0x0000e565, 0x00000004 }, |
| { 0x0000e566, 0x00000004 }, |
| { 0x00000052, 0x00000008 }, |
| { 0x03cca5b4, 0x00000004 }, |
| { 0x05432000, 0x00000004 }, |
| { 0x00022000, 0x00000004 }, |
| { 0x4ccce05e, 0x00000030 }, |
| { 0x08274565, 0x00000004 }, |
| { 0x0000005e, 0x00000030 }, |
| { 0x08004564, 0x00000004 }, |
| { 0x0000e566, 0x00000004 }, |
| { 0x00000055, 0x00000008 }, |
| { 0x00802061, 0x00000010 }, |
| { 0x00202000, 0x00000004 }, |
| { 0x001b00ff, 0x00000004 }, |
| { 0x01000064, 0x00000010 }, |
| { 0x001f2000, 0x00000004 }, |
| { 0x001c00ff, 0x00000004 }, |
| { 0000000000, 0x0000000c }, |
| { 0x00000072, 0x00000030 }, |
| { 0x00000055, 0x00000008 }, |
| { 0x0000e576, 0x00000004 }, |
| { 0x0000e577, 0x00000004 }, |
| { 0x0000e50e, 0x00000004 }, |
| { 0x0000e50f, 0x00000004 }, |
| { 0x0140a000, 0x00000004 }, |
| { 0x00000069, 0x00000018 }, |
| { 0x00c0e5f9, 0x000000c2 }, |
| { 0x00000069, 0x00000008 }, |
| { 0x0014e50e, 0x00000004 }, |
| { 0x0040e50f, 0x00000004 }, |
| { 0x00c0006c, 0x00000008 }, |
| { 0x0000e570, 0x00000004 }, |
| { 0x0000e571, 0x00000004 }, |
| { 0x0000e572, 0x0000000c }, |
| { 0x0000a000, 0x00000004 }, |
| { 0x0140a000, 0x00000004 }, |
| { 0x0000e568, 0x00000004 }, |
| { 0x000c2000, 0x00000004 }, |
| { 0x00000076, 0x00000018 }, |
| { 0x000b0000, 0x00000004 }, |
| { 0x18c0e562, 0x00000004 }, |
| { 0x00000078, 0x00000008 }, |
| { 0x00c00077, 0x00000008 }, |
| { 0x000700d5, 0x00000004 }, |
| { 0x00000084, 0x00000038 }, |
| { 0x000ca086, 0x00000030 }, |
| { 0x080045bb, 0x00000004 }, |
| { 0x000c2087, 0x00000030 }, |
| { 0x0800e5bc, 0000000000 }, |
| { 0x0000e5bb, 0x00000004 }, |
| { 0x0000e5bc, 0000000000 }, |
| { 0x00120000, 0x0000000c }, |
| { 0x00120000, 0x00000004 }, |
| { 0x001b0002, 0x0000000c }, |
| { 0x0000a000, 0x00000004 }, |
| { 0x0000e821, 0x00000004 }, |
| { 0x0000e800, 0000000000 }, |
| { 0x0000e821, 0x00000004 }, |
| { 0x0000e82e, 0000000000 }, |
| { 0x02cca000, 0x00000004 }, |
| { 0x00140000, 0x00000004 }, |
| { 0x000ce1cc, 0x00000004 }, |
| { 0x050de1cd, 0x00000004 }, |
| { 0x00400000, 0x00000004 }, |
| { 0x00000096, 0x00000018 }, |
| { 0x00c0a000, 0x00000004 }, |
| { 0x00000093, 0x00000008 }, |
| { 0x00000098, 0x00000020 }, |
| { 0x4200e000, 0000000000 }, |
| { 0x0000009f, 0x00000038 }, |
| { 0x000ca000, 0x00000004 }, |
| { 0x00140000, 0x00000004 }, |
| { 0x000c2000, 0x00000004 }, |
| { 0x00160000, 0x00000004 }, |
| { 0x700ce000, 0x00000004 }, |
| { 0x0014009b, 0x00000008 }, |
| { 0x4000e000, 0000000000 }, |
| { 0x02400000, 0x00000004 }, |
| { 0x400ee000, 0x00000004 }, |
| { 0x02400000, 0x00000004 }, |
| { 0x4000e000, 0000000000 }, |
| { 0x000c2000, 0x00000004 }, |
| { 0x0240e51b, 0x00000004 }, |
| { 0x0080e50a, 0x00000005 }, |
| { 0x0080e50b, 0x00000005 }, |
| { 0x00220000, 0x00000004 }, |
| { 0x000700d5, 0x00000004 }, |
| { 0x000000b2, 0x00000038 }, |
| { 0x000c2087, 0x00000030 }, |
| { 0x0880e5bd, 0x00000005 }, |
| { 0x000c2086, 0x00000030 }, |
| { 0x0800e5bb, 0x00000005 }, |
| { 0x000c2087, 0x00000030 }, |
| { 0x0880e5bc, 0x00000005 }, |
| { 0x000000b5, 0x00000008 }, |
| { 0x0080e5bd, 0x00000005 }, |
| { 0x0000e5bb, 0x00000005 }, |
| { 0x0080e5bc, 0x00000005 }, |
| { 0x00210000, 0x00000004 }, |
| { 0x02800000, 0x00000004 }, |
| { 0x00c000b9, 0x00000018 }, |
| { 0x4180e000, 0x00000040 }, |
| { 0x000000bb, 0x00000024 }, |
| { 0x01000000, 0x0000000c }, |
| { 0x0100e51d, 0x0000000c }, |
| { 0x000045bb, 0x00000004 }, |
| { 0x000080b5, 0x00000008 }, |
| { 0x0000f3ce, 0x00000004 }, |
| { 0x0140a000, 0x00000004 }, |
| { 0x00cc2000, 0x00000004 }, |
| { 0x08c053cf, 0x00000040 }, |
| { 0x00008000, 0000000000 }, |
| { 0x0000f3d2, 0x00000004 }, |
| { 0x0140a000, 0x00000004 }, |
| { 0x00cc2000, 0x00000004 }, |
| { 0x08c053d3, 0x00000040 }, |
| { 0x00008000, 0000000000 }, |
| { 0x0000f39d, 0x00000004 }, |
| { 0x0140a000, 0x00000004 }, |
| { 0x00cc2000, 0x00000004 }, |
| { 0x08c0539e, 0x00000040 }, |
| { 0x00008000, 0000000000 }, |
| { 0x03c00830, 0x00000004 }, |
| { 0x4200e000, 0000000000 }, |
| { 0x0000a000, 0x00000004 }, |
| { 0x200045e0, 0x00000004 }, |
| { 0x0000e5e1, 0000000000 }, |
| { 0x00000001, 0000000000 }, |
| { 0x000700d2, 0x00000004 }, |
| { 0x0800e394, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0x0000e8c4, 0x00000004 }, |
| { 0x0000e8c5, 0x00000004 }, |
| { 0x0000e8c6, 0x00000004 }, |
| { 0x0000e928, 0x00000004 }, |
| { 0x0000e929, 0x00000004 }, |
| { 0x0000e92a, 0x00000004 }, |
| { 0x000000d6, 0x00000008 }, |
| { 0x0000e928, 0x00000004 }, |
| { 0x0000e929, 0x00000004 }, |
| { 0x0000e92a, 0x00000004 }, |
| { 0x000000dd, 0x00000008 }, |
| { 0x00e00116, 0000000000 }, |
| { 0x000700e1, 0x00000004 }, |
| { 0x0800401c, 0x00000004 }, |
| { 0x200050e7, 0x00000004 }, |
| { 0x0000e01d, 0x00000004 }, |
| { 0x000000e4, 0x00000008 }, |
| { 0x02c02000, 0x00000004 }, |
| { 0x00060000, 0x00000004 }, |
| { 0x000000eb, 0x00000034 }, |
| { 0x000000e8, 0x00000008 }, |
| { 0x00008000, 0x00000004 }, |
| { 0xc000e000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0x000c2000, 0x00000004 }, |
| { 0x001d0018, 0x00000004 }, |
| { 0x001a0001, 0x00000004 }, |
| { 0x000000fb, 0x00000034 }, |
| { 0x0000004a, 0x00000008 }, |
| { 0x0500a04a, 0x00000008 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| }; |
| static const u32_t RS690_cp_microcode[][2]={ |
| { 0x000000dd, 0x00000008 }, |
| { 0x000000df, 0x00000008 }, |
| { 0x000000a0, 0x00000008 }, |
| { 0x000000a4, 0x00000008 }, |
| { 0x4a554b4a, 0000000000 }, |
| { 0x4a4a4467, 0000000000 }, |
| { 0x55526f75, 0000000000 }, |
| { 0x4a7e7d65, 0000000000 }, |
| { 0x4ad74af6, 0000000000 }, |
| { 0x4ac94a4a, 0000000000 }, |
| { 0xcc898989, 0000000000 }, |
| { 0xc34ad3c5, 0000000000 }, |
| { 0x8e4a4a4a, 0000000000 }, |
| { 0x4a8a8a8a, 0000000000 }, |
| { 0x4a0f8c4a, 0000000000 }, |
| { 0x000ca000, 0x00000004 }, |
| { 0x000d0012, 0x00000038 }, |
| { 0x0000e8b4, 0x00000004 }, |
| { 0x000d0014, 0x00000038 }, |
| { 0x0000e8b6, 0x00000004 }, |
| { 0x000d0016, 0x00000038 }, |
| { 0x0000e854, 0x00000004 }, |
| { 0x000d0018, 0x00000038 }, |
| { 0x0000e855, 0x00000004 }, |
| { 0x000d001a, 0x00000038 }, |
| { 0x0000e856, 0x00000004 }, |
| { 0x000d001c, 0x00000038 }, |
| { 0x0000e857, 0x00000004 }, |
| { 0x000d001e, 0x00000038 }, |
| { 0x0000e824, 0x00000004 }, |
| { 0x000d0020, 0x00000038 }, |
| { 0x0000e825, 0x00000004 }, |
| { 0x000d0022, 0x00000038 }, |
| { 0x0000e830, 0x00000004 }, |
| { 0x000d0024, 0x00000038 }, |
| { 0x0000f0c0, 0x00000004 }, |
| { 0x000d0026, 0x00000038 }, |
| { 0x0000f0c1, 0x00000004 }, |
| { 0x000d0028, 0x00000038 }, |
| { 0x0000f041, 0x00000004 }, |
| { 0x000d002a, 0x00000038 }, |
| { 0x0000f184, 0x00000004 }, |
| { 0x000d002c, 0x00000038 }, |
| { 0x0000f185, 0x00000004 }, |
| { 0x000d002e, 0x00000038 }, |
| { 0x0000f186, 0x00000004 }, |
| { 0x000d0030, 0x00000038 }, |
| { 0x0000f187, 0x00000004 }, |
| { 0x000d0032, 0x00000038 }, |
| { 0x0000f180, 0x00000004 }, |
| { 0x000d0034, 0x00000038 }, |
| { 0x0000f393, 0x00000004 }, |
| { 0x000d0036, 0x00000038 }, |
| { 0x0000f38a, 0x00000004 }, |
| { 0x000d0038, 0x00000038 }, |
| { 0x0000f38e, 0x00000004 }, |
| { 0x0000e821, 0x00000004 }, |
| { 0x0140a000, 0x00000004 }, |
| { 0x00000043, 0x00000018 }, |
| { 0x00cce800, 0x00000004 }, |
| { 0x001b0001, 0x00000004 }, |
| { 0x08004800, 0x00000004 }, |
| { 0x001b0001, 0x00000004 }, |
| { 0x08004800, 0x00000004 }, |
| { 0x001b0001, 0x00000004 }, |
| { 0x08004800, 0x00000004 }, |
| { 0x0000003a, 0x00000008 }, |
| { 0x0000a000, 0000000000 }, |
| { 0x2000451d, 0x00000004 }, |
| { 0x0000e580, 0x00000004 }, |
| { 0x000ce581, 0x00000004 }, |
| { 0x08004580, 0x00000004 }, |
| { 0x000ce581, 0x00000004 }, |
| { 0x00000047, 0x00000008 }, |
| { 0x0000a000, 0000000000 }, |
| { 0x000c2000, 0x00000004 }, |
| { 0x0000e50e, 0x00000004 }, |
| { 0x00032000, 0x00000004 }, |
| { 0x00022051, 0x00000028 }, |
| { 0x00000051, 0x00000024 }, |
| { 0x0800450f, 0x00000004 }, |
| { 0x0000a04b, 0x00000008 }, |
| { 0x0000e565, 0x00000004 }, |
| { 0x0000e566, 0x00000004 }, |
| { 0x00000052, 0x00000008 }, |
| { 0x03cca5b4, 0x00000004 }, |
| { 0x05432000, 0x00000004 }, |
| { 0x00022000, 0x00000004 }, |
| { 0x4ccce05e, 0x00000030 }, |
| { 0x08274565, 0x00000004 }, |
| { 0x0000005e, 0x00000030 }, |
| { 0x08004564, 0x00000004 }, |
| { 0x0000e566, 0x00000004 }, |
| { 0x00000055, 0x00000008 }, |
| { 0x00802061, 0x00000010 }, |
| { 0x00202000, 0x00000004 }, |
| { 0x001b00ff, 0x00000004 }, |
| { 0x01000064, 0x00000010 }, |
| { 0x001f2000, 0x00000004 }, |
| { 0x001c00ff, 0x00000004 }, |
| { 0000000000, 0x0000000c }, |
| { 0x00000072, 0x00000030 }, |
| { 0x00000055, 0x00000008 }, |
| { 0x0000e576, 0x00000004 }, |
| { 0x0000e577, 0x00000004 }, |
| { 0x0000e50e, 0x00000004 }, |
| { 0x0000e50f, 0x00000004 }, |
| { 0x0140a000, 0x00000004 }, |
| { 0x00000069, 0x00000018 }, |
| { 0x00c0e5f9, 0x000000c2 }, |
| { 0x00000069, 0x00000008 }, |
| { 0x0014e50e, 0x00000004 }, |
| { 0x0040e50f, 0x00000004 }, |
| { 0x00c0006c, 0x00000008 }, |
| { 0x0000e570, 0x00000004 }, |
| { 0x0000e571, 0x00000004 }, |
| { 0x0000e572, 0x0000000c }, |
| { 0x0000a000, 0x00000004 }, |
| { 0x0140a000, 0x00000004 }, |
| { 0x0000e568, 0x00000004 }, |
| { 0x000c2000, 0x00000004 }, |
| { 0x00000076, 0x00000018 }, |
| { 0x000b0000, 0x00000004 }, |
| { 0x18c0e562, 0x00000004 }, |
| { 0x00000078, 0x00000008 }, |
| { 0x00c00077, 0x00000008 }, |
| { 0x000700cb, 0x00000004 }, |
| { 0x00000084, 0x00000038 }, |
| { 0x000ca086, 0x00000030 }, |
| { 0x080045bb, 0x00000004 }, |
| { 0x000c2087, 0x00000030 }, |
| { 0x0800e5bc, 0000000000 }, |
| { 0x0000e5bb, 0x00000004 }, |
| { 0x0000e5bc, 0000000000 }, |
| { 0x00120000, 0x0000000c }, |
| { 0x00120000, 0x00000004 }, |
| { 0x001b0002, 0x0000000c }, |
| { 0x0000a000, 0x00000004 }, |
| { 0x0000e821, 0x00000004 }, |
| { 0x0000e800, 0000000000 }, |
| { 0x0000e821, 0x00000004 }, |
| { 0x0000e82e, 0000000000 }, |
| { 0x02cca000, 0x00000004 }, |
| { 0x00140000, 0x00000004 }, |
| { 0x000ce1cc, 0x00000004 }, |
| { 0x050de1cd, 0x00000004 }, |
| { 0x00400000, 0x00000004 }, |
| { 0x00000096, 0x00000018 }, |
| { 0x00c0a000, 0x00000004 }, |
| { 0x00000093, 0x00000008 }, |
| { 0x00000098, 0x00000020 }, |
| { 0x4200e000, 0000000000 }, |
| { 0x0000009f, 0x00000038 }, |
| { 0x000ca000, 0x00000004 }, |
| { 0x00140000, 0x00000004 }, |
| { 0x000c2000, 0x00000004 }, |
| { 0x00160000, 0x00000004 }, |
| { 0x700ce000, 0x00000004 }, |
| { 0x0014009b, 0x00000008 }, |
| { 0x4000e000, 0000000000 }, |
| { 0x02400000, 0x00000004 }, |
| { 0x400ee000, 0x00000004 }, |
| { 0x02400000, 0x00000004 }, |
| { 0x4000e000, 0000000000 }, |
| { 0x00100000, 0x0000002c }, |
| { 0x00004000, 0000000000 }, |
| { 0x080045c8, 0x00000004 }, |
| { 0x00240005, 0x00000004 }, |
| { 0x08004d0b, 0x00000004 }, |
| { 0x000c2000, 0x00000004 }, |
| { 0x0240e51b, 0x00000004 }, |
| { 0x0080e50a, 0x00000005 }, |
| { 0x0080e50b, 0x00000005 }, |
| { 0x00220000, 0x00000004 }, |
| { 0x000700cb, 0x00000004 }, |
| { 0x000000b7, 0x00000038 }, |
| { 0x000c2087, 0x00000030 }, |
| { 0x0880e5bd, 0x00000005 }, |
| { 0x000c2086, 0x00000030 }, |
| { 0x0800e5bb, 0x00000005 }, |
| { 0x000c2087, 0x00000030 }, |
| { 0x0880e5bc, 0x00000005 }, |
| { 0x000000ba, 0x00000008 }, |
| { 0x0080e5bd, 0x00000005 }, |
| { 0x0000e5bb, 0x00000005 }, |
| { 0x0080e5bc, 0x00000005 }, |
| { 0x00210000, 0x00000004 }, |
| { 0x02800000, 0x00000004 }, |
| { 0x00c000be, 0x00000018 }, |
| { 0x4180e000, 0x00000040 }, |
| { 0x000000c0, 0x00000024 }, |
| { 0x01000000, 0x0000000c }, |
| { 0x0100e51d, 0x0000000c }, |
| { 0x000045bb, 0x00000004 }, |
| { 0x000080ba, 0x00000008 }, |
| { 0x03c00830, 0x00000004 }, |
| { 0x4200e000, 0000000000 }, |
| { 0x0000a000, 0x00000004 }, |
| { 0x200045e0, 0x00000004 }, |
| { 0x0000e5e1, 0000000000 }, |
| { 0x00000001, 0000000000 }, |
| { 0x000700c8, 0x00000004 }, |
| { 0x0800e394, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0x0000e8c4, 0x00000004 }, |
| { 0x0000e8c5, 0x00000004 }, |
| { 0x0000e8c6, 0x00000004 }, |
| { 0x0000e928, 0x00000004 }, |
| { 0x0000e929, 0x00000004 }, |
| { 0x0000e92a, 0x00000004 }, |
| { 0x000000cc, 0x00000008 }, |
| { 0x0000e928, 0x00000004 }, |
| { 0x0000e929, 0x00000004 }, |
| { 0x0000e92a, 0x00000004 }, |
| { 0x000000d3, 0x00000008 }, |
| { 0x02c02000, 0x00000004 }, |
| { 0x00060000, 0x00000004 }, |
| { 0x000000db, 0x00000034 }, |
| { 0x000000d8, 0x00000008 }, |
| { 0x00008000, 0x00000004 }, |
| { 0xc000e000, 0000000000 }, |
| { 0x000000e1, 0x00000030 }, |
| { 0x4200e000, 0000000000 }, |
| { 0x000000e1, 0x00000030 }, |
| { 0x4000e000, 0000000000 }, |
| { 0x0025001b, 0x00000004 }, |
| { 0x00230000, 0x00000004 }, |
| { 0x00250005, 0x00000004 }, |
| { 0x000000e6, 0x00000034 }, |
| { 0000000000, 0x0000000c }, |
| { 0x00244000, 0x00000004 }, |
| { 0x080045c8, 0x00000004 }, |
| { 0x00240005, 0x00000004 }, |
| { 0x08004d0b, 0x0000000c }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0x000c2000, 0x00000004 }, |
| { 0x001d0018, 0x00000004 }, |
| { 0x001a0001, 0x00000004 }, |
| { 0x000000fb, 0x00000034 }, |
| { 0x0000004a, 0x00000008 }, |
| { 0x0500a04a, 0x00000008 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| }; |
| static const u32_t R520_cp_microcode[][2]={ |
| { 0x4200e000, 0000000000 }, |
| { 0x4000e000, 0000000000 }, |
| { 0x00000099, 0x00000008 }, |
| { 0x0000009d, 0x00000008 }, |
| { 0x4a554b4a, 0000000000 }, |
| { 0x4a4a4467, 0000000000 }, |
| { 0x55526f75, 0000000000 }, |
| { 0x4a7e7d65, 0000000000 }, |
| { 0xe0dae6f6, 0000000000 }, |
| { 0x4ac54a4a, 0000000000 }, |
| { 0xc8828282, 0000000000 }, |
| { 0xbf4acfc1, 0000000000 }, |
| { 0x87b04ad5, 0000000000 }, |
| { 0xb5838383, 0000000000 }, |
| { 0x4a0f85ba, 0000000000 }, |
| { 0x000ca000, 0x00000004 }, |
| { 0x000d0012, 0x00000038 }, |
| { 0x0000e8b4, 0x00000004 }, |
| { 0x000d0014, 0x00000038 }, |
| { 0x0000e8b6, 0x00000004 }, |
| { 0x000d0016, 0x00000038 }, |
| { 0x0000e854, 0x00000004 }, |
| { 0x000d0018, 0x00000038 }, |
| { 0x0000e855, 0x00000004 }, |
| { 0x000d001a, 0x00000038 }, |
| { 0x0000e856, 0x00000004 }, |
| { 0x000d001c, 0x00000038 }, |
| { 0x0000e857, 0x00000004 }, |
| { 0x000d001e, 0x00000038 }, |
| { 0x0000e824, 0x00000004 }, |
| { 0x000d0020, 0x00000038 }, |
| { 0x0000e825, 0x00000004 }, |
| { 0x000d0022, 0x00000038 }, |
| { 0x0000e830, 0x00000004 }, |
| { 0x000d0024, 0x00000038 }, |
| { 0x0000f0c0, 0x00000004 }, |
| { 0x000d0026, 0x00000038 }, |
| { 0x0000f0c1, 0x00000004 }, |
| { 0x000d0028, 0x00000038 }, |
| { 0x0000e000, 0x00000004 }, |
| { 0x000d002a, 0x00000038 }, |
| { 0x0000e000, 0x00000004 }, |
| { 0x000d002c, 0x00000038 }, |
| { 0x0000e000, 0x00000004 }, |
| { 0x000d002e, 0x00000038 }, |
| { 0x0000e000, 0x00000004 }, |
| { 0x000d0030, 0x00000038 }, |
| { 0x0000e000, 0x00000004 }, |
| { 0x000d0032, 0x00000038 }, |
| { 0x0000f180, 0x00000004 }, |
| { 0x000d0034, 0x00000038 }, |
| { 0x0000f393, 0x00000004 }, |
| { 0x000d0036, 0x00000038 }, |
| { 0x0000f38a, 0x00000004 }, |
| { 0x000d0038, 0x00000038 }, |
| { 0x0000f38e, 0x00000004 }, |
| { 0x0000e821, 0x00000004 }, |
| { 0x0140a000, 0x00000004 }, |
| { 0x00000043, 0x00000018 }, |
| { 0x00cce800, 0x00000004 }, |
| { 0x001b0001, 0x00000004 }, |
| { 0x08004800, 0x00000004 }, |
| { 0x001b0001, 0x00000004 }, |
| { 0x08004800, 0x00000004 }, |
| { 0x001b0001, 0x00000004 }, |
| { 0x08004800, 0x00000004 }, |
| { 0x0000003a, 0x00000008 }, |
| { 0x0000a000, 0000000000 }, |
| { 0x2000451d, 0x00000004 }, |
| { 0x0000e580, 0x00000004 }, |
| { 0x000ce581, 0x00000004 }, |
| { 0x08004580, 0x00000004 }, |
| { 0x000ce581, 0x00000004 }, |
| { 0x00000047, 0x00000008 }, |
| { 0x0000a000, 0000000000 }, |
| { 0x000c2000, 0x00000004 }, |
| { 0x0000e50e, 0x00000004 }, |
| { 0x00032000, 0x00000004 }, |
| { 0x00022051, 0x00000028 }, |
| { 0x00000051, 0x00000024 }, |
| { 0x0800450f, 0x00000004 }, |
| { 0x0000a04b, 0x00000008 }, |
| { 0x0000e565, 0x00000004 }, |
| { 0x0000e566, 0x00000004 }, |
| { 0x00000052, 0x00000008 }, |
| { 0x03cca5b4, 0x00000004 }, |
| { 0x05432000, 0x00000004 }, |
| { 0x00022000, 0x00000004 }, |
| { 0x4ccce05e, 0x00000030 }, |
| { 0x08274565, 0x00000004 }, |
| { 0x0000005e, 0x00000030 }, |
| { 0x08004564, 0x00000004 }, |
| { 0x0000e566, 0x00000004 }, |
| { 0x00000055, 0x00000008 }, |
| { 0x00802061, 0x00000010 }, |
| { 0x00202000, 0x00000004 }, |
| { 0x001b00ff, 0x00000004 }, |
| { 0x01000064, 0x00000010 }, |
| { 0x001f2000, 0x00000004 }, |
| { 0x001c00ff, 0x00000004 }, |
| { 0000000000, 0x0000000c }, |
| { 0x00000072, 0x00000030 }, |
| { 0x00000055, 0x00000008 }, |
| { 0x0000e576, 0x00000004 }, |
| { 0x0000e577, 0x00000004 }, |
| { 0x0000e50e, 0x00000004 }, |
| { 0x0000e50f, 0x00000004 }, |
| { 0x0140a000, 0x00000004 }, |
| { 0x00000069, 0x00000018 }, |
| { 0x00c0e5f9, 0x000000c2 }, |
| { 0x00000069, 0x00000008 }, |
| { 0x0014e50e, 0x00000004 }, |
| { 0x0040e50f, 0x00000004 }, |
| { 0x00c0006c, 0x00000008 }, |
| { 0x0000e570, 0x00000004 }, |
| { 0x0000e571, 0x00000004 }, |
| { 0x0000e572, 0x0000000c }, |
| { 0x0000a000, 0x00000004 }, |
| { 0x0140a000, 0x00000004 }, |
| { 0x0000e568, 0x00000004 }, |
| { 0x000c2000, 0x00000004 }, |
| { 0x00000076, 0x00000018 }, |
| { 0x000b0000, 0x00000004 }, |
| { 0x18c0e562, 0x00000004 }, |
| { 0x00000078, 0x00000008 }, |
| { 0x00c00077, 0x00000008 }, |
| { 0x000700c7, 0x00000004 }, |
| { 0x00000080, 0x00000038 }, |
| { 0x0000e5bb, 0x00000004 }, |
| { 0x0000e5bc, 0000000000 }, |
| { 0x0000a000, 0x00000004 }, |
| { 0x0000e821, 0x00000004 }, |
| { 0x0000e800, 0000000000 }, |
| { 0x0000e821, 0x00000004 }, |
| { 0x0000e82e, 0000000000 }, |
| { 0x02cca000, 0x00000004 }, |
| { 0x00140000, 0x00000004 }, |
| { 0x000ce1cc, 0x00000004 }, |
| { 0x050de1cd, 0x00000004 }, |
| { 0x00400000, 0x00000004 }, |
| { 0x0000008f, 0x00000018 }, |
| { 0x00c0a000, 0x00000004 }, |
| { 0x0000008c, 0x00000008 }, |
| { 0x00000091, 0x00000020 }, |
| { 0x4200e000, 0000000000 }, |
| { 0x00000098, 0x00000038 }, |
| { 0x000ca000, 0x00000004 }, |
| { 0x00140000, 0x00000004 }, |
| { 0x000c2000, 0x00000004 }, |
| { 0x00160000, 0x00000004 }, |
| { 0x700ce000, 0x00000004 }, |
| { 0x00140094, 0x00000008 }, |
| { 0x4000e000, 0000000000 }, |
| { 0x02400000, 0x00000004 }, |
| { 0x400ee000, 0x00000004 }, |
| { 0x02400000, 0x00000004 }, |
| { 0x4000e000, 0000000000 }, |
| { 0x000c2000, 0x00000004 }, |
| { 0x0240e51b, 0x00000004 }, |
| { 0x0080e50a, 0x00000005 }, |
| { 0x0080e50b, 0x00000005 }, |
| { 0x00220000, 0x00000004 }, |
| { 0x000700c7, 0x00000004 }, |
| { 0x000000a4, 0x00000038 }, |
| { 0x0080e5bd, 0x00000005 }, |
| { 0x0000e5bb, 0x00000005 }, |
| { 0x0080e5bc, 0x00000005 }, |
| { 0x00210000, 0x00000004 }, |
| { 0x02800000, 0x00000004 }, |
| { 0x00c000ab, 0x00000018 }, |
| { 0x4180e000, 0x00000040 }, |
| { 0x000000ad, 0x00000024 }, |
| { 0x01000000, 0x0000000c }, |
| { 0x0100e51d, 0x0000000c }, |
| { 0x000045bb, 0x00000004 }, |
| { 0x000080a7, 0x00000008 }, |
| { 0x0000f3ce, 0x00000004 }, |
| { 0x0140a000, 0x00000004 }, |
| { 0x00cc2000, 0x00000004 }, |
| { 0x08c053cf, 0x00000040 }, |
| { 0x00008000, 0000000000 }, |
| { 0x0000f3d2, 0x00000004 }, |
| { 0x0140a000, 0x00000004 }, |
| { 0x00cc2000, 0x00000004 }, |
| { 0x08c053d3, 0x00000040 }, |
| { 0x00008000, 0000000000 }, |
| { 0x0000f39d, 0x00000004 }, |
| { 0x0140a000, 0x00000004 }, |
| { 0x00cc2000, 0x00000004 }, |
| { 0x08c0539e, 0x00000040 }, |
| { 0x00008000, 0000000000 }, |
| { 0x03c00830, 0x00000004 }, |
| { 0x4200e000, 0000000000 }, |
| { 0x0000a000, 0x00000004 }, |
| { 0x200045e0, 0x00000004 }, |
| { 0x0000e5e1, 0000000000 }, |
| { 0x00000001, 0000000000 }, |
| { 0x000700c4, 0x00000004 }, |
| { 0x0800e394, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0x0000e8c4, 0x00000004 }, |
| { 0x0000e8c5, 0x00000004 }, |
| { 0x0000e8c6, 0x00000004 }, |
| { 0x0000e928, 0x00000004 }, |
| { 0x0000e929, 0x00000004 }, |
| { 0x0000e92a, 0x00000004 }, |
| { 0x000000c8, 0x00000008 }, |
| { 0x0000e928, 0x00000004 }, |
| { 0x0000e929, 0x00000004 }, |
| { 0x0000e92a, 0x00000004 }, |
| { 0x000000cf, 0x00000008 }, |
| { 0xdeadbeef, 0000000000 }, |
| { 0x00000116, 0000000000 }, |
| { 0x000700d3, 0x00000004 }, |
| { 0x080050e7, 0x00000004 }, |
| { 0x000700d4, 0x00000004 }, |
| { 0x0800401c, 0x00000004 }, |
| { 0x0000e01d, 0000000000 }, |
| { 0x02c02000, 0x00000004 }, |
| { 0x00060000, 0x00000004 }, |
| { 0x000000de, 0x00000034 }, |
| { 0x000000db, 0x00000008 }, |
| { 0x00008000, 0x00000004 }, |
| { 0xc000e000, 0000000000 }, |
| { 0x0000e1cc, 0x00000004 }, |
| { 0x0500e1cd, 0x00000004 }, |
| { 0x000ca000, 0x00000004 }, |
| { 0x000000e5, 0x00000034 }, |
| { 0x000000e1, 0x00000008 }, |
| { 0x0000a000, 0000000000 }, |
| { 0x0019e1cc, 0x00000004 }, |
| { 0x001b0001, 0x00000004 }, |
| { 0x0500a000, 0x00000004 }, |
| { 0x080041cd, 0x00000004 }, |
| { 0x000ca000, 0x00000004 }, |
| { 0x000000fb, 0x00000034 }, |
| { 0x0000004a, 0x00000008 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0x000c2000, 0x00000004 }, |
| { 0x001d0018, 0x00000004 }, |
| { 0x001a0001, 0x00000004 }, |
| { 0x000000fb, 0x00000034 }, |
| { 0x0000004a, 0x00000008 }, |
| { 0x0500a04a, 0x00000008 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| }; |
| #endif |
| /drivers/old/ati2d/radeon_reg.h |
|---|
| 0,0 → 1,5322 |
| /* |
| * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and |
| * VA Linux Systems Inc., Fremont, California. |
| * |
| * All Rights Reserved. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining |
| * a copy of this software and associated documentation files (the |
| * "Software"), to deal in the Software without restriction, including |
| * without limitation on the rights to use, copy, modify, merge, |
| * publish, distribute, sublicense, and/or sell copies of the Software, |
| * and to permit persons to whom the Software is furnished to do so, |
| * subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice (including the |
| * next paragraph) shall be included in all copies or substantial |
| * portions of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR |
| * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
| * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| * DEALINGS IN THE SOFTWARE. |
| */ |
| /* |
| * Authors: |
| * Kevin E. Martin <martin@xfree86.org> |
| * Rickard E. Faith <faith@valinux.com> |
| * Alan Hourihane <alanh@fairlite.demon.co.uk> |
| * |
| * References: |
| * |
| * !!!! FIXME !!!! |
| * RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical |
| * Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April |
| * 1999. |
| * |
| * !!!! FIXME !!!! |
| * RAGE 128 Software Development Manual (Technical Reference Manual P/N |
| * SDK-G04000 Rev. 0.01), ATI Technologies: June 1999. |
| * |
| */ |
| /* !!!! FIXME !!!! NOTE: THIS FILE HAS BEEN CONVERTED FROM r128_reg.h |
| * AND CONTAINS REGISTERS AND REGISTER DEFINITIONS THAT ARE NOT CORRECT |
| * ON THE RADEON. A FULL AUDIT OF THIS CODE IS NEEDED! */ |
| #ifndef _RADEON_REG_H_ |
| #define _RADEON_REG_H_ |
| #define ATI_DATATYPE_VQ 0 |
| #define ATI_DATATYPE_CI4 1 |
| #define ATI_DATATYPE_CI8 2 |
| #define ATI_DATATYPE_ARGB1555 3 |
| #define ATI_DATATYPE_RGB565 4 |
| #define ATI_DATATYPE_RGB888 5 |
| #define ATI_DATATYPE_ARGB8888 6 |
| #define ATI_DATATYPE_RGB332 7 |
| #define ATI_DATATYPE_Y8 8 |
| #define ATI_DATATYPE_RGB8 9 |
| #define ATI_DATATYPE_CI16 10 |
| #define ATI_DATATYPE_VYUY_422 11 |
| #define ATI_DATATYPE_YVYU_422 12 |
| #define ATI_DATATYPE_AYUV_444 14 |
| #define ATI_DATATYPE_ARGB4444 15 |
| /* Registers for 2D/Video/Overlay */ |
| #define RADEON_ADAPTER_ID 0x0f2c /* PCI */ |
| #define RADEON_AGP_BASE 0x0170 |
| #define RADEON_AGP_CNTL 0x0174 |
| # define RADEON_AGP_APER_SIZE_256MB (0x00 << 0) |
| # define RADEON_AGP_APER_SIZE_128MB (0x20 << 0) |
| # define RADEON_AGP_APER_SIZE_64MB (0x30 << 0) |
| # define RADEON_AGP_APER_SIZE_32MB (0x38 << 0) |
| # define RADEON_AGP_APER_SIZE_16MB (0x3c << 0) |
| # define RADEON_AGP_APER_SIZE_8MB (0x3e << 0) |
| # define RADEON_AGP_APER_SIZE_4MB (0x3f << 0) |
| # define RADEON_AGP_APER_SIZE_MASK (0x3f << 0) |
| #define RADEON_STATUS_PCI_CONFIG 0x06 |
| # define RADEON_CAP_LIST 0x100000 |
| #define RADEON_CAPABILITIES_PTR_PCI_CONFIG 0x34 /* offset in PCI config*/ |
| # define RADEON_CAP_PTR_MASK 0xfc /* mask off reserved bits of CAP_PTR */ |
| # define RADEON_CAP_ID_NULL 0x00 /* End of capability list */ |
| # define RADEON_CAP_ID_AGP 0x02 /* AGP capability ID */ |
| # define RADEON_CAP_ID_EXP 0x10 /* PCI Express */ |
| #define RADEON_AGP_COMMAND 0x0f60 /* PCI */ |
| #define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config*/ |
| # define RADEON_AGP_ENABLE (1<<8) |
| #define RADEON_AGP_PLL_CNTL 0x000b /* PLL */ |
| #define RADEON_AGP_STATUS 0x0f5c /* PCI */ |
| # define RADEON_AGP_1X_MODE 0x01 |
| # define RADEON_AGP_2X_MODE 0x02 |
| # define RADEON_AGP_4X_MODE 0x04 |
| # define RADEON_AGP_FW_MODE 0x10 |
| # define RADEON_AGP_MODE_MASK 0x17 |
| # define RADEON_AGPv3_MODE 0x08 |
| # define RADEON_AGPv3_4X_MODE 0x01 |
| # define RADEON_AGPv3_8X_MODE 0x02 |
| #define RADEON_ATTRDR 0x03c1 /* VGA */ |
| #define RADEON_ATTRDW 0x03c0 /* VGA */ |
| #define RADEON_ATTRX 0x03c0 /* VGA */ |
| #define RADEON_AUX_SC_CNTL 0x1660 |
| # define RADEON_AUX1_SC_EN (1 << 0) |
| # define RADEON_AUX1_SC_MODE_OR (0 << 1) |
| # define RADEON_AUX1_SC_MODE_NAND (1 << 1) |
| # define RADEON_AUX2_SC_EN (1 << 2) |
| # define RADEON_AUX2_SC_MODE_OR (0 << 3) |
| # define RADEON_AUX2_SC_MODE_NAND (1 << 3) |
| # define RADEON_AUX3_SC_EN (1 << 4) |
| # define RADEON_AUX3_SC_MODE_OR (0 << 5) |
| # define RADEON_AUX3_SC_MODE_NAND (1 << 5) |
| #define RADEON_AUX1_SC_BOTTOM 0x1670 |
| #define RADEON_AUX1_SC_LEFT 0x1664 |
| #define RADEON_AUX1_SC_RIGHT 0x1668 |
| #define RADEON_AUX1_SC_TOP 0x166c |
| #define RADEON_AUX2_SC_BOTTOM 0x1680 |
| #define RADEON_AUX2_SC_LEFT 0x1674 |
| #define RADEON_AUX2_SC_RIGHT 0x1678 |
| #define RADEON_AUX2_SC_TOP 0x167c |
| #define RADEON_AUX3_SC_BOTTOM 0x1690 |
| #define RADEON_AUX3_SC_LEFT 0x1684 |
| #define RADEON_AUX3_SC_RIGHT 0x1688 |
| #define RADEON_AUX3_SC_TOP 0x168c |
| #define RADEON_AUX_WINDOW_HORZ_CNTL 0x02d8 |
| #define RADEON_AUX_WINDOW_VERT_CNTL 0x02dc |
| #define RADEON_BASE_CODE 0x0f0b |
| #define RADEON_BIOS_0_SCRATCH 0x0010 |
| # define RADEON_FP_PANEL_SCALABLE (1 << 16) |
| # define RADEON_FP_PANEL_SCALE_EN (1 << 17) |
| # define RADEON_FP_CHIP_SCALE_EN (1 << 18) |
| # define RADEON_DRIVER_BRIGHTNESS_EN (1 << 26) |
| # define RADEON_DISPLAY_ROT_MASK (3 << 28) |
| # define RADEON_DISPLAY_ROT_00 (0 << 28) |
| # define RADEON_DISPLAY_ROT_90 (1 << 28) |
| # define RADEON_DISPLAY_ROT_180 (2 << 28) |
| # define RADEON_DISPLAY_ROT_270 (3 << 28) |
| #define RADEON_BIOS_1_SCRATCH 0x0014 |
| #define RADEON_BIOS_2_SCRATCH 0x0018 |
| #define RADEON_BIOS_3_SCRATCH 0x001c |
| #define RADEON_BIOS_4_SCRATCH 0x0020 |
| # define RADEON_CRT1_ATTACHED_MASK (3 << 0) |
| # define RADEON_CRT1_ATTACHED_MONO (1 << 0) |
| # define RADEON_CRT1_ATTACHED_COLOR (2 << 0) |
| # define RADEON_LCD1_ATTACHED (1 << 2) |
| # define RADEON_DFP1_ATTACHED (1 << 3) |
| # define RADEON_TV1_ATTACHED_MASK (3 << 4) |
| # define RADEON_TV1_ATTACHED_COMP (1 << 4) |
| # define RADEON_TV1_ATTACHED_SVIDEO (2 << 4) |
| # define RADEON_CRT2_ATTACHED_MASK (3 << 8) |
| # define RADEON_CRT2_ATTACHED_MONO (1 << 8) |
| # define RADEON_CRT2_ATTACHED_COLOR (2 << 8) |
| # define RADEON_DFP2_ATTACHED (1 << 11) |
| #define RADEON_BIOS_5_SCRATCH 0x0024 |
| # define RADEON_LCD1_ON (1 << 0) |
| # define RADEON_CRT1_ON (1 << 1) |
| # define RADEON_TV1_ON (1 << 2) |
| # define RADEON_DFP1_ON (1 << 3) |
| # define RADEON_CRT2_ON (1 << 5) |
| # define RADEON_CV1_ON (1 << 6) |
| # define RADEON_DFP2_ON (1 << 7) |
| # define RADEON_LCD1_CRTC_MASK (1 << 8) |
| # define RADEON_LCD1_CRTC_SHIFT 8 |
| # define RADEON_CRT1_CRTC_MASK (1 << 9) |
| # define RADEON_CRT1_CRTC_SHIFT 9 |
| # define RADEON_TV1_CRTC_MASK (1 << 10) |
| # define RADEON_TV1_CRTC_SHIFT 10 |
| # define RADEON_DFP1_CRTC_MASK (1 << 11) |
| # define RADEON_DFP1_CRTC_SHIFT 11 |
| # define RADEON_CRT2_CRTC_MASK (1 << 12) |
| # define RADEON_CRT2_CRTC_SHIFT 12 |
| # define RADEON_CV1_CRTC_MASK (1 << 13) |
| # define RADEON_CV1_CRTC_SHIFT 13 |
| # define RADEON_DFP2_CRTC_MASK (1 << 14) |
| # define RADEON_DFP2_CRTC_SHIFT 14 |
| #define RADEON_BIOS_6_SCRATCH 0x0028 |
| # define RADEON_ACC_MODE_CHANGE (1 << 2) |
| # define RADEON_EXT_DESKTOP_MODE (1 << 3) |
| # define RADEON_LCD_DPMS_ON (1 << 20) |
| # define RADEON_CRT_DPMS_ON (1 << 21) |
| # define RADEON_TV_DPMS_ON (1 << 22) |
| # define RADEON_DFP_DPMS_ON (1 << 23) |
| # define RADEON_DPMS_MASK (3 << 24) |
| # define RADEON_DPMS_ON (0 << 24) |
| # define RADEON_DPMS_STANDBY (1 << 24) |
| # define RADEON_DPMS_SUSPEND (2 << 24) |
| # define RADEON_DPMS_OFF (3 << 24) |
| # define RADEON_SCREEN_BLANKING (1 << 26) |
| # define RADEON_DRIVER_CRITICAL (1 << 27) |
| # define RADEON_DISPLAY_SWITCHING_DIS (1 << 30) |
| #define RADEON_BIOS_7_SCRATCH 0x002c |
| # define RADEON_SYS_HOTKEY (1 << 10) |
| # define RADEON_DRV_LOADED (1 << 12) |
| #define RADEON_BIOS_ROM 0x0f30 /* PCI */ |
| #define RADEON_BIST 0x0f0f /* PCI */ |
| #define RADEON_BRUSH_DATA0 0x1480 |
| #define RADEON_BRUSH_DATA1 0x1484 |
| #define RADEON_BRUSH_DATA10 0x14a8 |
| #define RADEON_BRUSH_DATA11 0x14ac |
| #define RADEON_BRUSH_DATA12 0x14b0 |
| #define RADEON_BRUSH_DATA13 0x14b4 |
| #define RADEON_BRUSH_DATA14 0x14b8 |
| #define RADEON_BRUSH_DATA15 0x14bc |
| #define RADEON_BRUSH_DATA16 0x14c0 |
| #define RADEON_BRUSH_DATA17 0x14c4 |
| #define RADEON_BRUSH_DATA18 0x14c8 |
| #define RADEON_BRUSH_DATA19 0x14cc |
| #define RADEON_BRUSH_DATA2 0x1488 |
| #define RADEON_BRUSH_DATA20 0x14d0 |
| #define RADEON_BRUSH_DATA21 0x14d4 |
| #define RADEON_BRUSH_DATA22 0x14d8 |
| #define RADEON_BRUSH_DATA23 0x14dc |
| #define RADEON_BRUSH_DATA24 0x14e0 |
| #define RADEON_BRUSH_DATA25 0x14e4 |
| #define RADEON_BRUSH_DATA26 0x14e8 |
| #define RADEON_BRUSH_DATA27 0x14ec |
| #define RADEON_BRUSH_DATA28 0x14f0 |
| #define RADEON_BRUSH_DATA29 0x14f4 |
| #define RADEON_BRUSH_DATA3 0x148c |
| #define RADEON_BRUSH_DATA30 0x14f8 |
| #define RADEON_BRUSH_DATA31 0x14fc |
| #define RADEON_BRUSH_DATA32 0x1500 |
| #define RADEON_BRUSH_DATA33 0x1504 |
| #define RADEON_BRUSH_DATA34 0x1508 |
| #define RADEON_BRUSH_DATA35 0x150c |
| #define RADEON_BRUSH_DATA36 0x1510 |
| #define RADEON_BRUSH_DATA37 0x1514 |
| #define RADEON_BRUSH_DATA38 0x1518 |
| #define RADEON_BRUSH_DATA39 0x151c |
| #define RADEON_BRUSH_DATA4 0x1490 |
| #define RADEON_BRUSH_DATA40 0x1520 |
| #define RADEON_BRUSH_DATA41 0x1524 |
| #define RADEON_BRUSH_DATA42 0x1528 |
| #define RADEON_BRUSH_DATA43 0x152c |
| #define RADEON_BRUSH_DATA44 0x1530 |
| #define RADEON_BRUSH_DATA45 0x1534 |
| #define RADEON_BRUSH_DATA46 0x1538 |
| #define RADEON_BRUSH_DATA47 0x153c |
| #define RADEON_BRUSH_DATA48 0x1540 |
| #define RADEON_BRUSH_DATA49 0x1544 |
| #define RADEON_BRUSH_DATA5 0x1494 |
| #define RADEON_BRUSH_DATA50 0x1548 |
| #define RADEON_BRUSH_DATA51 0x154c |
| #define RADEON_BRUSH_DATA52 0x1550 |
| #define RADEON_BRUSH_DATA53 0x1554 |
| #define RADEON_BRUSH_DATA54 0x1558 |
| #define RADEON_BRUSH_DATA55 0x155c |
| #define RADEON_BRUSH_DATA56 0x1560 |
| #define RADEON_BRUSH_DATA57 0x1564 |
| #define RADEON_BRUSH_DATA58 0x1568 |
| #define RADEON_BRUSH_DATA59 0x156c |
| #define RADEON_BRUSH_DATA6 0x1498 |
| #define RADEON_BRUSH_DATA60 0x1570 |
| #define RADEON_BRUSH_DATA61 0x1574 |
| #define RADEON_BRUSH_DATA62 0x1578 |
| #define RADEON_BRUSH_DATA63 0x157c |
| #define RADEON_BRUSH_DATA7 0x149c |
| #define RADEON_BRUSH_DATA8 0x14a0 |
| #define RADEON_BRUSH_DATA9 0x14a4 |
| #define RADEON_BRUSH_SCALE 0x1470 |
| #define RADEON_BRUSH_Y_X 0x1474 |
| #define RADEON_BUS_CNTL 0x0030 |
| # define RADEON_BUS_MASTER_DIS (1 << 6) |
| # define RADEON_BUS_BIOS_DIS_ROM (1 << 12) |
| # define RADEON_BUS_RD_DISCARD_EN (1 << 24) |
| # define RADEON_BUS_RD_ABORT_EN (1 << 25) |
| # define RADEON_BUS_MSTR_DISCONNECT_EN (1 << 28) |
| # define RADEON_BUS_WRT_BURST (1 << 29) |
| # define RADEON_BUS_READ_BURST (1 << 30) |
| #define RADEON_BUS_CNTL1 0x0034 |
| # define RADEON_BUS_WAIT_ON_LOCK_EN (1 << 4) |
| #define RADEON_CACHE_CNTL 0x1724 |
| #define RADEON_CACHE_LINE 0x0f0c /* PCI */ |
| #define RADEON_CAPABILITIES_ID 0x0f50 /* PCI */ |
| #define RADEON_CAPABILITIES_PTR 0x0f34 /* PCI */ |
| #define RADEON_CLK_PIN_CNTL 0x0001 /* PLL */ |
| # define RADEON_SCLK_DYN_START_CNTL (1 << 15) |
| #define RADEON_CLOCK_CNTL_DATA 0x000c |
| #define RADEON_CLOCK_CNTL_INDEX 0x0008 |
| # define RADEON_PLL_WR_EN (1 << 7) |
| # define RADEON_PLL_DIV_SEL (3 << 8) |
| # define RADEON_PLL2_DIV_SEL_MASK ~(3 << 8) |
| #define RADEON_CLK_PWRMGT_CNTL 0x0014 |
| # define RADEON_ENGIN_DYNCLK_MODE (1 << 12) |
| # define RADEON_ACTIVE_HILO_LAT_MASK (3 << 13) |
| # define RADEON_ACTIVE_HILO_LAT_SHIFT 13 |
| # define RADEON_DISP_DYN_STOP_LAT_MASK (1 << 12) |
| # define RADEON_MC_BUSY (1 << 16) |
| # define RADEON_DLL_READY (1 << 19) |
| # define RADEON_CG_NO1_DEBUG_0 (1 << 24) |
| # define RADEON_CG_NO1_DEBUG_MASK (0x1f << 24) |
| # define RADEON_DYN_STOP_MODE_MASK (7 << 21) |
| # define RADEON_TVPLL_PWRMGT_OFF (1 << 30) |
| # define RADEON_TVCLK_TURNOFF (1 << 31) |
| #define RADEON_PLL_PWRMGT_CNTL 0x0015 |
| # define RADEON_TCL_BYPASS_DISABLE (1 << 20) |
| #define RADEON_CLR_CMP_CLR_3D 0x1a24 |
| #define RADEON_CLR_CMP_CLR_DST 0x15c8 |
| #define RADEON_CLR_CMP_CLR_SRC 0x15c4 |
| #define RADEON_CLR_CMP_CNTL 0x15c0 |
| # define RADEON_SRC_CMP_EQ_COLOR (4 << 0) |
| # define RADEON_SRC_CMP_NEQ_COLOR (5 << 0) |
| # define RADEON_CLR_CMP_SRC_SOURCE (1 << 24) |
| #define RADEON_CLR_CMP_MASK 0x15cc |
| # define RADEON_CLR_CMP_MSK 0xffffffff |
| #define RADEON_CLR_CMP_MASK_3D 0x1A28 |
| #define RADEON_COMMAND 0x0f04 /* PCI */ |
| #define RADEON_COMPOSITE_SHADOW_ID 0x1a0c |
| #define RADEON_CONFIG_APER_0_BASE 0x0100 |
| #define RADEON_CONFIG_APER_1_BASE 0x0104 |
| #define RADEON_CONFIG_APER_SIZE 0x0108 |
| #define RADEON_CONFIG_BONDS 0x00e8 |
| #define RADEON_CONFIG_CNTL 0x00e0 |
| # define RADEON_CFG_ATI_REV_A11 (0 << 16) |
| # define RADEON_CFG_ATI_REV_A12 (1 << 16) |
| # define RADEON_CFG_ATI_REV_A13 (2 << 16) |
| # define RADEON_CFG_ATI_REV_ID_MASK (0xf << 16) |
| #define RADEON_CONFIG_MEMSIZE 0x00f8 |
| #define RADEON_CONFIG_MEMSIZE_EMBEDDED 0x0114 |
| #define RADEON_CONFIG_REG_1_BASE 0x010c |
| #define RADEON_CONFIG_REG_APER_SIZE 0x0110 |
| #define RADEON_CONFIG_XSTRAP 0x00e4 |
| #define RADEON_CONSTANT_COLOR_C 0x1d34 |
| # define RADEON_CONSTANT_COLOR_MASK 0x00ffffff |
| # define RADEON_CONSTANT_COLOR_ONE 0x00ffffff |
| # define RADEON_CONSTANT_COLOR_ZERO 0x00000000 |
| #define RADEON_CRC_CMDFIFO_ADDR 0x0740 |
| #define RADEON_CRC_CMDFIFO_DOUT 0x0744 |
| #define RADEON_GRPH_BUFFER_CNTL 0x02f0 |
| # define RADEON_GRPH_START_REQ_MASK (0x7f) |
| # define RADEON_GRPH_START_REQ_SHIFT 0 |
| # define RADEON_GRPH_STOP_REQ_MASK (0x7f<<8) |
| # define RADEON_GRPH_STOP_REQ_SHIFT 8 |
| # define RADEON_GRPH_CRITICAL_POINT_MASK (0x7f<<16) |
| # define RADEON_GRPH_CRITICAL_POINT_SHIFT 16 |
| # define RADEON_GRPH_CRITICAL_CNTL (1<<28) |
| # define RADEON_GRPH_BUFFER_SIZE (1<<29) |
| # define RADEON_GRPH_CRITICAL_AT_SOF (1<<30) |
| # define RADEON_GRPH_STOP_CNTL (1<<31) |
| #define RADEON_GRPH2_BUFFER_CNTL 0x03f0 |
| # define RADEON_GRPH2_START_REQ_MASK (0x7f) |
| # define RADEON_GRPH2_START_REQ_SHIFT 0 |
| # define RADEON_GRPH2_STOP_REQ_MASK (0x7f<<8) |
| # define RADEON_GRPH2_STOP_REQ_SHIFT 8 |
| # define RADEON_GRPH2_CRITICAL_POINT_MASK (0x7f<<16) |
| # define RADEON_GRPH2_CRITICAL_POINT_SHIFT 16 |
| # define RADEON_GRPH2_CRITICAL_CNTL (1<<28) |
| # define RADEON_GRPH2_BUFFER_SIZE (1<<29) |
| # define RADEON_GRPH2_CRITICAL_AT_SOF (1<<30) |
| # define RADEON_GRPH2_STOP_CNTL (1<<31) |
| #define RADEON_CRTC_CRNT_FRAME 0x0214 |
| #define RADEON_CRTC_EXT_CNTL 0x0054 |
| # define RADEON_CRTC_VGA_XOVERSCAN (1 << 0) |
| # define RADEON_VGA_ATI_LINEAR (1 << 3) |
| # define RADEON_XCRT_CNT_EN (1 << 6) |
| # define RADEON_CRTC_HSYNC_DIS (1 << 8) |
| # define RADEON_CRTC_VSYNC_DIS (1 << 9) |
| # define RADEON_CRTC_DISPLAY_DIS (1 << 10) |
| # define RADEON_CRTC_SYNC_TRISTAT (1 << 11) |
| # define RADEON_CRTC_CRT_ON (1 << 15) |
| #define RADEON_CRTC_EXT_CNTL_DPMS_BYTE 0x0055 |
| # define RADEON_CRTC_HSYNC_DIS_BYTE (1 << 0) |
| # define RADEON_CRTC_VSYNC_DIS_BYTE (1 << 1) |
| # define RADEON_CRTC_DISPLAY_DIS_BYTE (1 << 2) |
| #define RADEON_CRTC_GEN_CNTL 0x0050 |
| # define RADEON_CRTC_DBL_SCAN_EN (1 << 0) |
| # define RADEON_CRTC_INTERLACE_EN (1 << 1) |
| # define RADEON_CRTC_CSYNC_EN (1 << 4) |
| # define RADEON_CRTC_ICON_EN (1 << 15) |
| # define RADEON_CRTC_CUR_EN (1 << 16) |
| # define RADEON_CRTC_CUR_MODE_MASK (7 << 20) |
| # define RADEON_CRTC_EXT_DISP_EN (1 << 24) |
| # define RADEON_CRTC_EN (1 << 25) |
| # define RADEON_CRTC_DISP_REQ_EN_B (1 << 26) |
| #define RADEON_CRTC2_GEN_CNTL 0x03f8 |
| # define RADEON_CRTC2_DBL_SCAN_EN (1 << 0) |
| # define RADEON_CRTC2_INTERLACE_EN (1 << 1) |
| # define RADEON_CRTC2_SYNC_TRISTAT (1 << 4) |
| # define RADEON_CRTC2_HSYNC_TRISTAT (1 << 5) |
| # define RADEON_CRTC2_VSYNC_TRISTAT (1 << 6) |
| # define RADEON_CRTC2_CRT2_ON (1 << 7) |
| # define RADEON_CRTC2_PIX_WIDTH_SHIFT 8 |
| # define RADEON_CRTC2_PIX_WIDTH_MASK (0xf << 8) |
| # define RADEON_CRTC2_ICON_EN (1 << 15) |
| # define RADEON_CRTC2_CUR_EN (1 << 16) |
| # define RADEON_CRTC2_CUR_MODE_MASK (7 << 20) |
| # define RADEON_CRTC2_DISP_DIS (1 << 23) |
| # define RADEON_CRTC2_EN (1 << 25) |
| # define RADEON_CRTC2_DISP_REQ_EN_B (1 << 26) |
| # define RADEON_CRTC2_CSYNC_EN (1 << 27) |
| # define RADEON_CRTC2_HSYNC_DIS (1 << 28) |
| # define RADEON_CRTC2_VSYNC_DIS (1 << 29) |
| #define RADEON_CRTC_MORE_CNTL 0x27c |
| # define RADEON_CRTC_AUTO_HORZ_CENTER_EN (1<<2) |
| # define RADEON_CRTC_AUTO_VERT_CENTER_EN (1<<3) |
| # define RADEON_CRTC_H_CUTOFF_ACTIVE_EN (1<<4) |
| # define RADEON_CRTC_V_CUTOFF_ACTIVE_EN (1<<5) |
| #define RADEON_CRTC_GUI_TRIG_VLINE 0x0218 |
| #define RADEON_CRTC_H_SYNC_STRT_WID 0x0204 |
| # define RADEON_CRTC_H_SYNC_STRT_PIX (0x07 << 0) |
| # define RADEON_CRTC_H_SYNC_STRT_CHAR (0x3ff << 3) |
| # define RADEON_CRTC_H_SYNC_STRT_CHAR_SHIFT 3 |
| # define RADEON_CRTC_H_SYNC_WID (0x3f << 16) |
| # define RADEON_CRTC_H_SYNC_WID_SHIFT 16 |
| # define RADEON_CRTC_H_SYNC_POL (1 << 23) |
| #define RADEON_CRTC2_H_SYNC_STRT_WID 0x0304 |
| # define RADEON_CRTC2_H_SYNC_STRT_PIX (0x07 << 0) |
| # define RADEON_CRTC2_H_SYNC_STRT_CHAR (0x3ff << 3) |
| # define RADEON_CRTC2_H_SYNC_STRT_CHAR_SHIFT 3 |
| # define RADEON_CRTC2_H_SYNC_WID (0x3f << 16) |
| # define RADEON_CRTC2_H_SYNC_WID_SHIFT 16 |
| # define RADEON_CRTC2_H_SYNC_POL (1 << 23) |
| #define RADEON_CRTC_H_TOTAL_DISP 0x0200 |
| # define RADEON_CRTC_H_TOTAL (0x03ff << 0) |
| # define RADEON_CRTC_H_TOTAL_SHIFT 0 |
| # define RADEON_CRTC_H_DISP (0x01ff << 16) |
| # define RADEON_CRTC_H_DISP_SHIFT 16 |
| #define RADEON_CRTC2_H_TOTAL_DISP 0x0300 |
| # define RADEON_CRTC2_H_TOTAL (0x03ff << 0) |
| # define RADEON_CRTC2_H_TOTAL_SHIFT 0 |
| # define RADEON_CRTC2_H_DISP (0x01ff << 16) |
| # define RADEON_CRTC2_H_DISP_SHIFT 16 |
| #define RADEON_CRTC_OFFSET_RIGHT 0x0220 |
| #define RADEON_CRTC_OFFSET 0x0224 |
| # define RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET (1<<30) |
| # define RADEON_CRTC_OFFSET__OFFSET_LOCK (1<<31) |
| #define RADEON_CRTC2_OFFSET 0x0324 |
| # define RADEON_CRTC2_OFFSET__GUI_TRIG_OFFSET (1<<30) |
| # define RADEON_CRTC2_OFFSET__OFFSET_LOCK (1<<31) |
| #define RADEON_CRTC_OFFSET_CNTL 0x0228 |
| # define RADEON_CRTC_TILE_LINE_SHIFT 0 |
| # define RADEON_CRTC_TILE_LINE_RIGHT_SHIFT 4 |
| # define R300_CRTC_X_Y_MODE_EN_RIGHT (1 << 6) |
| # define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_MASK (3 << 7) |
| # define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_AUTO (0 << 7) |
| # define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_SINGLE (1 << 7) |
| # define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DOUBLE (2 << 7) |
| # define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DIS (3 << 7) |
| # define R300_CRTC_X_Y_MODE_EN (1 << 9) |
| # define R300_CRTC_MICRO_TILE_BUFFER_MASK (3 << 10) |
| # define R300_CRTC_MICRO_TILE_BUFFER_AUTO (0 << 10) |
| # define R300_CRTC_MICRO_TILE_BUFFER_SINGLE (1 << 10) |
| # define R300_CRTC_MICRO_TILE_BUFFER_DOUBLE (2 << 10) |
| # define R300_CRTC_MICRO_TILE_BUFFER_DIS (3 << 10) |
| # define R300_CRTC_MICRO_TILE_EN_RIGHT (1 << 12) |
| # define R300_CRTC_MICRO_TILE_EN (1 << 13) |
| # define R300_CRTC_MACRO_TILE_EN_RIGHT (1 << 14) |
| # define R300_CRTC_MACRO_TILE_EN (1 << 15) |
| # define RADEON_CRTC_TILE_EN_RIGHT (1 << 14) |
| # define RADEON_CRTC_TILE_EN (1 << 15) |
| # define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16) |
| # define RADEON_CRTC_STEREO_OFFSET_EN (1 << 17) |
| #define R300_CRTC_TILE_X0_Y0 0x0350 |
| #define R300_CRTC2_TILE_X0_Y0 0x0358 |
| #define RADEON_CRTC2_OFFSET_CNTL 0x0328 |
| # define RADEON_CRTC2_OFFSET_FLIP_CNTL (1 << 16) |
| # define RADEON_CRTC2_TILE_EN (1 << 15) |
| #define RADEON_CRTC_PITCH 0x022c |
| # define RADEON_CRTC_PITCH__SHIFT 0 |
| # define RADEON_CRTC_PITCH__RIGHT_SHIFT 16 |
| #define RADEON_CRTC2_PITCH 0x032c |
| #define RADEON_CRTC_STATUS 0x005c |
| # define RADEON_CRTC_VBLANK_SAVE (1 << 1) |
| # define RADEON_CRTC_VBLANK_SAVE_CLEAR (1 << 1) |
| #define RADEON_CRTC2_STATUS 0x03fc |
| # define RADEON_CRTC2_VBLANK_SAVE (1 << 1) |
| # define RADEON_CRTC2_VBLANK_SAVE_CLEAR (1 << 1) |
| #define RADEON_CRTC_V_SYNC_STRT_WID 0x020c |
| # define RADEON_CRTC_V_SYNC_STRT (0x7ff << 0) |
| # define RADEON_CRTC_V_SYNC_STRT_SHIFT 0 |
| # define RADEON_CRTC_V_SYNC_WID (0x1f << 16) |
| # define RADEON_CRTC_V_SYNC_WID_SHIFT 16 |
| # define RADEON_CRTC_V_SYNC_POL (1 << 23) |
| #define RADEON_CRTC2_V_SYNC_STRT_WID 0x030c |
| # define RADEON_CRTC2_V_SYNC_STRT (0x7ff << 0) |
| # define RADEON_CRTC2_V_SYNC_STRT_SHIFT 0 |
| # define RADEON_CRTC2_V_SYNC_WID (0x1f << 16) |
| # define RADEON_CRTC2_V_SYNC_WID_SHIFT 16 |
| # define RADEON_CRTC2_V_SYNC_POL (1 << 23) |
| #define RADEON_CRTC_V_TOTAL_DISP 0x0208 |
| # define RADEON_CRTC_V_TOTAL (0x07ff << 0) |
| # define RADEON_CRTC_V_TOTAL_SHIFT 0 |
| # define RADEON_CRTC_V_DISP (0x07ff << 16) |
| # define RADEON_CRTC_V_DISP_SHIFT 16 |
| #define RADEON_CRTC2_V_TOTAL_DISP 0x0308 |
| # define RADEON_CRTC2_V_TOTAL (0x07ff << 0) |
| # define RADEON_CRTC2_V_TOTAL_SHIFT 0 |
| # define RADEON_CRTC2_V_DISP (0x07ff << 16) |
| # define RADEON_CRTC2_V_DISP_SHIFT 16 |
| #define RADEON_CRTC_VLINE_CRNT_VLINE 0x0210 |
| # define RADEON_CRTC_CRNT_VLINE_MASK (0x7ff << 16) |
| #define RADEON_CRTC2_CRNT_FRAME 0x0314 |
| #define RADEON_CRTC2_GUI_TRIG_VLINE 0x0318 |
| #define RADEON_CRTC2_STATUS 0x03fc |
| #define RADEON_CRTC2_VLINE_CRNT_VLINE 0x0310 |
| #define RADEON_CRTC8_DATA 0x03d5 /* VGA, 0x3b5 */ |
| #define RADEON_CRTC8_IDX 0x03d4 /* VGA, 0x3b4 */ |
| #define RADEON_CUR_CLR0 0x026c |
| #define RADEON_CUR_CLR1 0x0270 |
| #define RADEON_CUR_HORZ_VERT_OFF 0x0268 |
| #define RADEON_CUR_HORZ_VERT_POSN 0x0264 |
| #define RADEON_CUR_OFFSET 0x0260 |
| # define RADEON_CUR_LOCK (1 << 31) |
| #define RADEON_CUR2_CLR0 0x036c |
| #define RADEON_CUR2_CLR1 0x0370 |
| #define RADEON_CUR2_HORZ_VERT_OFF 0x0368 |
| #define RADEON_CUR2_HORZ_VERT_POSN 0x0364 |
| #define RADEON_CUR2_OFFSET 0x0360 |
| # define RADEON_CUR2_LOCK (1 << 31) |
| #define RADEON_DAC_CNTL 0x0058 |
| # define RADEON_DAC_RANGE_CNTL (3 << 0) |
| # define RADEON_DAC_RANGE_CNTL_PS2 (2 << 0) |
| # define RADEON_DAC_RANGE_CNTL_MASK 0x03 |
| # define RADEON_DAC_BLANKING (1 << 2) |
| # define RADEON_DAC_CMP_EN (1 << 3) |
| # define RADEON_DAC_CMP_OUTPUT (1 << 7) |
| # define RADEON_DAC_8BIT_EN (1 << 8) |
| # define RADEON_DAC_TVO_EN (1 << 10) |
| # define RADEON_DAC_VGA_ADR_EN (1 << 13) |
| # define RADEON_DAC_PDWN (1 << 15) |
| # define RADEON_DAC_MASK_ALL (0xff << 24) |
| #define RADEON_DAC_CNTL2 0x007c |
| # define RADEON_DAC2_TV_CLK_SEL (0 << 1) |
| # define RADEON_DAC2_DAC_CLK_SEL (1 << 0) |
| # define RADEON_DAC2_DAC2_CLK_SEL (1 << 1) |
| # define RADEON_DAC2_PALETTE_ACC_CTL (1 << 5) |
| # define RADEON_DAC2_CMP_EN (1 << 7) |
| # define RADEON_DAC2_CMP_OUT_R (1 << 8) |
| # define RADEON_DAC2_CMP_OUT_G (1 << 9) |
| # define RADEON_DAC2_CMP_OUT_B (1 << 10) |
| # define RADEON_DAC2_CMP_OUTPUT (1 << 11) |
| #define RADEON_DAC_EXT_CNTL 0x0280 |
| # define RADEON_DAC2_FORCE_BLANK_OFF_EN (1 << 0) |
| # define RADEON_DAC2_FORCE_DATA_EN (1 << 1) |
| # define RADEON_DAC_FORCE_BLANK_OFF_EN (1 << 4) |
| # define RADEON_DAC_FORCE_DATA_EN (1 << 5) |
| # define RADEON_DAC_FORCE_DATA_SEL_MASK (3 << 6) |
| # define RADEON_DAC_FORCE_DATA_SEL_R (0 << 6) |
| # define RADEON_DAC_FORCE_DATA_SEL_G (1 << 6) |
| # define RADEON_DAC_FORCE_DATA_SEL_B (2 << 6) |
| # define RADEON_DAC_FORCE_DATA_SEL_RGB (3 << 6) |
| # define RADEON_DAC_FORCE_DATA_MASK 0x0003ff00 |
| # define RADEON_DAC_FORCE_DATA_SHIFT 8 |
| #define RADEON_DAC_MACRO_CNTL 0x0d04 |
| # define RADEON_DAC_PDWN_R (1 << 16) |
| # define RADEON_DAC_PDWN_G (1 << 17) |
| # define RADEON_DAC_PDWN_B (1 << 18) |
| #define RADEON_TV_DAC_CNTL 0x088c |
| # define RADEON_TV_DAC_NBLANK (1 << 0) |
| # define RADEON_TV_DAC_NHOLD (1 << 1) |
| # define RADEON_TV_DAC_PEDESTAL (1 << 2) |
| # define RADEON_TV_MONITOR_DETECT_EN (1 << 4) |
| # define RADEON_TV_DAC_CMPOUT (1 << 5) |
| # define RADEON_TV_DAC_STD_MASK (3 << 8) |
| # define RADEON_TV_DAC_STD_PAL (0 << 8) |
| # define RADEON_TV_DAC_STD_NTSC (1 << 8) |
| # define RADEON_TV_DAC_STD_PS2 (2 << 8) |
| # define RADEON_TV_DAC_STD_RS343 (3 << 8) |
| # define RADEON_TV_DAC_BGSLEEP (1 << 6) |
| # define RADEON_TV_DAC_BGADJ_MASK (0xf << 16) |
| # define RADEON_TV_DAC_BGADJ_SHIFT 16 |
| # define RADEON_TV_DAC_DACADJ_MASK (0xf << 20) |
| # define RADEON_TV_DAC_DACADJ_SHIFT 20 |
| # define RADEON_TV_DAC_RDACPD (1 << 24) |
| # define RADEON_TV_DAC_GDACPD (1 << 25) |
| # define RADEON_TV_DAC_BDACPD (1 << 26) |
| # define RADEON_TV_DAC_RDACDET (1 << 29) |
| # define RADEON_TV_DAC_GDACDET (1 << 30) |
| # define RADEON_TV_DAC_BDACDET (1 << 31) |
| # define R420_TV_DAC_DACADJ_MASK (0x1f << 20) |
| # define R420_TV_DAC_RDACPD (1 << 25) |
| # define R420_TV_DAC_GDACPD (1 << 26) |
| # define R420_TV_DAC_BDACPD (1 << 27) |
| # define R420_TV_DAC_TVENABLE (1 << 28) |
| #define RADEON_DISP_HW_DEBUG 0x0d14 |
| # define RADEON_CRT2_DISP1_SEL (1 << 5) |
| #define RADEON_DISP_OUTPUT_CNTL 0x0d64 |
| # define RADEON_DISP_DAC_SOURCE_MASK 0x03 |
| # define RADEON_DISP_DAC2_SOURCE_MASK 0x0c |
| # define RADEON_DISP_DAC_SOURCE_CRTC2 0x01 |
| # define RADEON_DISP_DAC_SOURCE_RMX 0x02 |
| # define RADEON_DISP_DAC_SOURCE_LTU 0x03 |
| # define RADEON_DISP_DAC2_SOURCE_CRTC2 0x04 |
| # define RADEON_DISP_TVDAC_SOURCE_MASK (0x03 << 2) |
| # define RADEON_DISP_TVDAC_SOURCE_CRTC 0x0 |
| # define RADEON_DISP_TVDAC_SOURCE_CRTC2 (0x01 << 2) |
| # define RADEON_DISP_TVDAC_SOURCE_RMX (0x02 << 2) |
| # define RADEON_DISP_TVDAC_SOURCE_LTU (0x03 << 2) |
| # define RADEON_DISP_TRANS_MATRIX_MASK (0x03 << 4) |
| # define RADEON_DISP_TRANS_MATRIX_ALPHA_MSB (0x00 << 4) |
| # define RADEON_DISP_TRANS_MATRIX_GRAPHICS (0x01 << 4) |
| # define RADEON_DISP_TRANS_MATRIX_VIDEO (0x02 << 4) |
| # define RADEON_DISP_TV_SOURCE_CRTC (1 << 16) /* crtc1 or crtc2 */ |
| # define RADEON_DISP_TV_SOURCE_LTU (0 << 16) /* linear transform unit */ |
| #define RADEON_DISP_TV_OUT_CNTL 0x0d6c |
| # define RADEON_DISP_TV_PATH_SRC_CRTC2 (1 << 16) |
| # define RADEON_DISP_TV_PATH_SRC_CRTC1 (0 << 16) |
| #define RADEON_DAC_CRC_SIG 0x02cc |
| #define RADEON_DAC_DATA 0x03c9 /* VGA */ |
| #define RADEON_DAC_MASK 0x03c6 /* VGA */ |
| #define RADEON_DAC_R_INDEX 0x03c7 /* VGA */ |
| #define RADEON_DAC_W_INDEX 0x03c8 /* VGA */ |
| #define RADEON_DDA_CONFIG 0x02e0 |
| #define RADEON_DDA_ON_OFF 0x02e4 |
| #define RADEON_DEFAULT_OFFSET 0x16e0 |
| #define RADEON_DEFAULT_PITCH 0x16e4 |
| #define RADEON_DEFAULT_SC_BOTTOM_RIGHT 0x16e8 |
| # define RADEON_DEFAULT_SC_RIGHT_MAX (0x1fff << 0) |
| # define RADEON_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16) |
| #define RADEON_DESTINATION_3D_CLR_CMP_VAL 0x1820 |
| #define RADEON_DESTINATION_3D_CLR_CMP_MSK 0x1824 |
| #define RADEON_DEVICE_ID 0x0f02 /* PCI */ |
| #define RADEON_DISP_MISC_CNTL 0x0d00 |
| # define RADEON_SOFT_RESET_GRPH_PP (1 << 0) |
| #define RADEON_DISP_MERGE_CNTL 0x0d60 |
| # define RADEON_DISP_ALPHA_MODE_MASK 0x03 |
| # define RADEON_DISP_ALPHA_MODE_KEY 0 |
| # define RADEON_DISP_ALPHA_MODE_PER_PIXEL 1 |
| # define RADEON_DISP_ALPHA_MODE_GLOBAL 2 |
| # define RADEON_DISP_RGB_OFFSET_EN (1 << 8) |
| # define RADEON_DISP_GRPH_ALPHA_MASK (0xff << 16) |
| # define RADEON_DISP_OV0_ALPHA_MASK (0xff << 24) |
| # define RADEON_DISP_LIN_TRANS_BYPASS (0x01 << 9) |
| #define RADEON_DISP2_MERGE_CNTL 0x0d68 |
| # define RADEON_DISP2_RGB_OFFSET_EN (1 << 8) |
| #define RADEON_DISP_LIN_TRANS_GRPH_A 0x0d80 |
| #define RADEON_DISP_LIN_TRANS_GRPH_B 0x0d84 |
| #define RADEON_DISP_LIN_TRANS_GRPH_C 0x0d88 |
| #define RADEON_DISP_LIN_TRANS_GRPH_D 0x0d8c |
| #define RADEON_DISP_LIN_TRANS_GRPH_E 0x0d90 |
| #define RADEON_DISP_LIN_TRANS_GRPH_F 0x0d98 |
| #define RADEON_DP_BRUSH_BKGD_CLR 0x1478 |
| #define RADEON_DP_BRUSH_FRGD_CLR 0x147c |
| #define RADEON_DP_CNTL 0x16c0 |
| # define RADEON_DST_X_LEFT_TO_RIGHT (1 << 0) |
| # define RADEON_DST_Y_TOP_TO_BOTTOM (1 << 1) |
| # define RADEON_DP_DST_TILE_LINEAR (0 << 3) |
| # define RADEON_DP_DST_TILE_MACRO (1 << 3) |
| # define RADEON_DP_DST_TILE_MICRO (2 << 3) |
| # define RADEON_DP_DST_TILE_BOTH (3 << 3) |
| #define RADEON_DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0 |
| # define RADEON_DST_Y_MAJOR (1 << 2) |
| # define RADEON_DST_Y_DIR_TOP_TO_BOTTOM (1 << 15) |
| # define RADEON_DST_X_DIR_LEFT_TO_RIGHT (1 << 31) |
| #define RADEON_DP_DATATYPE 0x16c4 |
| # define RADEON_HOST_BIG_ENDIAN_EN (1 << 29) |
| #define RADEON_DP_GUI_MASTER_CNTL 0x146c |
| # define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) |
| # define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) |
| # define RADEON_GMC_SRC_CLIPPING (1 << 2) |
| # define RADEON_GMC_DST_CLIPPING (1 << 3) |
| # define RADEON_GMC_BRUSH_DATATYPE_MASK (0x0f << 4) |
| # define RADEON_GMC_BRUSH_8X8_MONO_FG_BG (0 << 4) |
| # define RADEON_GMC_BRUSH_8X8_MONO_FG_LA (1 << 4) |
| # define RADEON_GMC_BRUSH_1X8_MONO_FG_BG (4 << 4) |
| # define RADEON_GMC_BRUSH_1X8_MONO_FG_LA (5 << 4) |
| # define RADEON_GMC_BRUSH_32x1_MONO_FG_BG (6 << 4) |
| # define RADEON_GMC_BRUSH_32x1_MONO_FG_LA (7 << 4) |
| # define RADEON_GMC_BRUSH_32x32_MONO_FG_BG (8 << 4) |
| # define RADEON_GMC_BRUSH_32x32_MONO_FG_LA (9 << 4) |
| # define RADEON_GMC_BRUSH_8x8_COLOR (10 << 4) |
| # define RADEON_GMC_BRUSH_1X8_COLOR (12 << 4) |
| # define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4) |
| # define RADEON_GMC_BRUSH_NONE (15 << 4) |
| # define RADEON_GMC_DST_8BPP_CI (2 << 8) |
| # define RADEON_GMC_DST_15BPP (3 << 8) |
| # define RADEON_GMC_DST_16BPP (4 << 8) |
| # define RADEON_GMC_DST_24BPP (5 << 8) |
| # define RADEON_GMC_DST_32BPP (6 << 8) |
| # define RADEON_GMC_DST_8BPP_RGB (7 << 8) |
| # define RADEON_GMC_DST_Y8 (8 << 8) |
| # define RADEON_GMC_DST_RGB8 (9 << 8) |
| # define RADEON_GMC_DST_VYUY (11 << 8) |
| # define RADEON_GMC_DST_YVYU (12 << 8) |
| # define RADEON_GMC_DST_AYUV444 (14 << 8) |
| # define RADEON_GMC_DST_ARGB4444 (15 << 8) |
| # define RADEON_GMC_DST_DATATYPE_MASK (0x0f << 8) |
| # define RADEON_GMC_DST_DATATYPE_SHIFT 8 |
| # define RADEON_GMC_SRC_DATATYPE_MASK (3 << 12) |
| # define RADEON_GMC_SRC_DATATYPE_MONO_FG_BG (0 << 12) |
| # define RADEON_GMC_SRC_DATATYPE_MONO_FG_LA (1 << 12) |
| # define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12) |
| # define RADEON_GMC_BYTE_PIX_ORDER (1 << 14) |
| # define RADEON_GMC_BYTE_MSB_TO_LSB (0 << 14) |
| # define RADEON_GMC_BYTE_LSB_TO_MSB (1 << 14) |
| # define RADEON_GMC_CONVERSION_TEMP (1 << 15) |
| # define RADEON_GMC_CONVERSION_TEMP_6500 (0 << 15) |
| # define RADEON_GMC_CONVERSION_TEMP_9300 (1 << 15) |
| # define RADEON_GMC_ROP3_MASK (0xff << 16) |
| # define RADEON_DP_SRC_SOURCE_MASK (7 << 24) |
| # define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24) |
| # define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24) |
| # define RADEON_GMC_3D_FCN_EN (1 << 27) |
| # define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28) |
| # define RADEON_GMC_AUX_CLIP_DIS (1 << 29) |
| # define RADEON_GMC_WR_MSK_DIS (1 << 30) |
| # define RADEON_GMC_LD_BRUSH_Y_X (1 << 31) |
| # define RADEON_ROP3_ZERO 0x00000000 |
| # define RADEON_ROP3_DSa 0x00880000 |
| # define RADEON_ROP3_SDna 0x00440000 |
| # define RADEON_ROP3_S 0x00cc0000 |
| # define RADEON_ROP3_DSna 0x00220000 |
| # define RADEON_ROP3_D 0x00aa0000 |
| # define RADEON_ROP3_DSx 0x00660000 |
| # define RADEON_ROP3_DSo 0x00ee0000 |
| # define RADEON_ROP3_DSon 0x00110000 |
| # define RADEON_ROP3_DSxn 0x00990000 |
| # define RADEON_ROP3_Dn 0x00550000 |
| # define RADEON_ROP3_SDno 0x00dd0000 |
| # define RADEON_ROP3_Sn 0x00330000 |
| # define RADEON_ROP3_DSno 0x00bb0000 |
| # define RADEON_ROP3_DSan 0x00770000 |
| # define RADEON_ROP3_ONE 0x00ff0000 |
| # define RADEON_ROP3_DPa 0x00a00000 |
| # define RADEON_ROP3_PDna 0x00500000 |
| # define RADEON_ROP3_P 0x00f00000 |
| # define RADEON_ROP3_DPna 0x000a0000 |
| # define RADEON_ROP3_D 0x00aa0000 |
| # define RADEON_ROP3_DPx 0x005a0000 |
| # define RADEON_ROP3_DPo 0x00fa0000 |
| # define RADEON_ROP3_DPon 0x00050000 |
| # define RADEON_ROP3_PDxn 0x00a50000 |
| # define RADEON_ROP3_PDno 0x00f50000 |
| # define RADEON_ROP3_Pn 0x000f0000 |
| # define RADEON_ROP3_DPno 0x00af0000 |
| # define RADEON_ROP3_DPan 0x005f0000 |
| #define RADEON_DP_GUI_MASTER_CNTL_C 0x1c84 |
| #define RADEON_DP_MIX 0x16c8 |
| #define RADEON_DP_SRC_BKGD_CLR 0x15dc |
| #define RADEON_DP_SRC_FRGD_CLR 0x15d8 |
| #define RADEON_DP_WRITE_MASK 0x16cc |
| #define RADEON_DST_BRES_DEC 0x1630 |
| #define RADEON_DST_BRES_ERR 0x1628 |
| #define RADEON_DST_BRES_INC 0x162c |
| #define RADEON_DST_BRES_LNTH 0x1634 |
| #define RADEON_DST_BRES_LNTH_SUB 0x1638 |
| #define RADEON_DST_HEIGHT 0x1410 |
| #define RADEON_DST_HEIGHT_WIDTH 0x143c |
| #define RADEON_DST_HEIGHT_WIDTH_8 0x158c |
| #define RADEON_DST_HEIGHT_WIDTH_BW 0x15b4 |
| #define RADEON_DST_HEIGHT_Y 0x15a0 |
| #define RADEON_DST_LINE_START 0x1600 |
| #define RADEON_DST_LINE_END 0x1604 |
| #define RADEON_DST_LINE_PATCOUNT 0x1608 |
| # define RADEON_BRES_CNTL_SHIFT 8 |
| #define RADEON_DST_OFFSET 0x1404 |
| #define RADEON_DST_PITCH 0x1408 |
| #define RADEON_DST_PITCH_OFFSET 0x142c |
| #define RADEON_DST_PITCH_OFFSET_C 0x1c80 |
| # define RADEON_PITCH_SHIFT 21 |
| # define RADEON_DST_TILE_LINEAR (0 << 30) |
| # define RADEON_DST_TILE_MACRO (1 << 30) |
| # define RADEON_DST_TILE_MICRO (2 << 30) |
| # define RADEON_DST_TILE_BOTH (3 << 30) |
| #define RADEON_DST_WIDTH 0x140c |
| #define RADEON_DST_WIDTH_HEIGHT 0x1598 |
| #define RADEON_DST_WIDTH_X 0x1588 |
| #define RADEON_DST_WIDTH_X_INCY 0x159c |
| #define RADEON_DST_X 0x141c |
| #define RADEON_DST_X_SUB 0x15a4 |
| #define RADEON_DST_X_Y 0x1594 |
| #define RADEON_DST_Y 0x1420 |
| #define RADEON_DST_Y_SUB 0x15a8 |
| #define RADEON_DST_Y_X 0x1438 |
| #define RADEON_FCP_CNTL 0x0910 |
| # define RADEON_FCP0_SRC_PCICLK 0 |
| # define RADEON_FCP0_SRC_PCLK 1 |
| # define RADEON_FCP0_SRC_PCLKb 2 |
| # define RADEON_FCP0_SRC_HREF 3 |
| # define RADEON_FCP0_SRC_GND 4 |
| # define RADEON_FCP0_SRC_HREFb 5 |
| #define RADEON_FLUSH_1 0x1704 |
| #define RADEON_FLUSH_2 0x1708 |
| #define RADEON_FLUSH_3 0x170c |
| #define RADEON_FLUSH_4 0x1710 |
| #define RADEON_FLUSH_5 0x1714 |
| #define RADEON_FLUSH_6 0x1718 |
| #define RADEON_FLUSH_7 0x171c |
| #define RADEON_FOG_3D_TABLE_START 0x1810 |
| #define RADEON_FOG_3D_TABLE_END 0x1814 |
| #define RADEON_FOG_3D_TABLE_DENSITY 0x181c |
| #define RADEON_FOG_TABLE_INDEX 0x1a14 |
| #define RADEON_FOG_TABLE_DATA 0x1a18 |
| #define RADEON_FP_CRTC_H_TOTAL_DISP 0x0250 |
| #define RADEON_FP_CRTC_V_TOTAL_DISP 0x0254 |
| # define RADEON_FP_CRTC_H_TOTAL_MASK 0x000003ff |
| # define RADEON_FP_CRTC_H_DISP_MASK 0x01ff0000 |
| # define RADEON_FP_CRTC_V_TOTAL_MASK 0x00000fff |
| # define RADEON_FP_CRTC_V_DISP_MASK 0x0fff0000 |
| # define RADEON_FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8 |
| # define RADEON_FP_H_SYNC_WID_MASK 0x003f0000 |
| # define RADEON_FP_V_SYNC_STRT_MASK 0x00000fff |
| # define RADEON_FP_V_SYNC_WID_MASK 0x001f0000 |
| # define RADEON_FP_CRTC_H_TOTAL_SHIFT 0x00000000 |
| # define RADEON_FP_CRTC_H_DISP_SHIFT 0x00000010 |
| # define RADEON_FP_CRTC_V_TOTAL_SHIFT 0x00000000 |
| # define RADEON_FP_CRTC_V_DISP_SHIFT 0x00000010 |
| # define RADEON_FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003 |
| # define RADEON_FP_H_SYNC_WID_SHIFT 0x00000010 |
| # define RADEON_FP_V_SYNC_STRT_SHIFT 0x00000000 |
| # define RADEON_FP_V_SYNC_WID_SHIFT 0x00000010 |
| #define RADEON_FP_GEN_CNTL 0x0284 |
| # define RADEON_FP_FPON (1 << 0) |
| # define RADEON_FP_BLANK_EN (1 << 1) |
| # define RADEON_FP_TMDS_EN (1 << 2) |
| # define RADEON_FP_PANEL_FORMAT (1 << 3) |
| # define RADEON_FP_EN_TMDS (1 << 7) |
| # define RADEON_FP_DETECT_SENSE (1 << 8) |
| # define R200_FP_SOURCE_SEL_MASK (3 << 10) |
| # define R200_FP_SOURCE_SEL_CRTC1 (0 << 10) |
| # define R200_FP_SOURCE_SEL_CRTC2 (1 << 10) |
| # define R200_FP_SOURCE_SEL_RMX (2 << 10) |
| # define R200_FP_SOURCE_SEL_TRANS (3 << 10) |
| # define RADEON_FP_SEL_CRTC1 (0 << 13) |
| # define RADEON_FP_SEL_CRTC2 (1 << 13) |
| # define RADEON_FP_CRTC_DONT_SHADOW_HPAR (1 << 15) |
| # define RADEON_FP_CRTC_DONT_SHADOW_VPAR (1 << 16) |
| # define RADEON_FP_CRTC_DONT_SHADOW_HEND (1 << 17) |
| # define RADEON_FP_CRTC_USE_SHADOW_VEND (1 << 18) |
| # define RADEON_FP_RMX_HVSYNC_CONTROL_EN (1 << 20) |
| # define RADEON_FP_DFP_SYNC_SEL (1 << 21) |
| # define RADEON_FP_CRTC_LOCK_8DOT (1 << 22) |
| # define RADEON_FP_CRT_SYNC_SEL (1 << 23) |
| # define RADEON_FP_USE_SHADOW_EN (1 << 24) |
| # define RADEON_FP_CRT_SYNC_ALT (1 << 26) |
| #define RADEON_FP2_GEN_CNTL 0x0288 |
| # define RADEON_FP2_BLANK_EN (1 << 1) |
| # define RADEON_FP2_ON (1 << 2) |
| # define RADEON_FP2_PANEL_FORMAT (1 << 3) |
| # define RADEON_FP2_DETECT_SENSE (1 << 8) |
| # define R200_FP2_SOURCE_SEL_MASK (3 << 10) |
| # define R200_FP2_SOURCE_SEL_CRTC1 (0 << 10) |
| # define R200_FP2_SOURCE_SEL_CRTC2 (1 << 10) |
| # define R200_FP2_SOURCE_SEL_RMX (2 << 10) |
| # define R200_FP2_SOURCE_SEL_TRANS_UNIT (3 << 10) |
| # define RADEON_FP2_SRC_SEL_MASK (3 << 13) |
| # define RADEON_FP2_SRC_SEL_CRTC2 (1 << 13) |
| # define RADEON_FP2_FP_POL (1 << 16) |
| # define RADEON_FP2_LP_POL (1 << 17) |
| # define RADEON_FP2_SCK_POL (1 << 18) |
| # define RADEON_FP2_LCD_CNTL_MASK (7 << 19) |
| # define RADEON_FP2_PAD_FLOP_EN (1 << 22) |
| # define RADEON_FP2_CRC_EN (1 << 23) |
| # define RADEON_FP2_CRC_READ_EN (1 << 24) |
| # define RADEON_FP2_DVO_EN (1 << 25) |
| # define RADEON_FP2_DVO_RATE_SEL_SDR (1 << 26) |
| # define R200_FP2_DVO_RATE_SEL_SDR (1 << 27) |
| # define R300_FP2_DVO_CLOCK_MODE_SINGLE (1 << 28) |
| # define R300_FP2_DVO_DUAL_CHANNEL_EN (1 << 29) |
| #define RADEON_FP_H_SYNC_STRT_WID 0x02c4 |
| #define RADEON_FP_H2_SYNC_STRT_WID 0x03c4 |
| #define RADEON_FP_HORZ_STRETCH 0x028c |
| #define RADEON_FP_HORZ2_STRETCH 0x038c |
| # define RADEON_HORZ_STRETCH_RATIO_MASK 0xffff |
| # define RADEON_HORZ_STRETCH_RATIO_MAX 4096 |
| # define RADEON_HORZ_PANEL_SIZE (0x1ff << 16) |
| # define RADEON_HORZ_PANEL_SHIFT 16 |
| # define RADEON_HORZ_STRETCH_PIXREP (0 << 25) |
| # define RADEON_HORZ_STRETCH_BLEND (1 << 26) |
| # define RADEON_HORZ_STRETCH_ENABLE (1 << 25) |
| # define RADEON_HORZ_AUTO_RATIO (1 << 27) |
| # define RADEON_HORZ_FP_LOOP_STRETCH (0x7 << 28) |
| # define RADEON_HORZ_AUTO_RATIO_INC (1 << 31) |
| #define RADEON_FP_HORZ_VERT_ACTIVE 0x0278 |
| #define RADEON_FP_V_SYNC_STRT_WID 0x02c8 |
| #define RADEON_FP_VERT_STRETCH 0x0290 |
| #define RADEON_FP_V2_SYNC_STRT_WID 0x03c8 |
| #define RADEON_FP_VERT2_STRETCH 0x0390 |
| # define RADEON_VERT_PANEL_SIZE (0xfff << 12) |
| # define RADEON_VERT_PANEL_SHIFT 12 |
| # define RADEON_VERT_STRETCH_RATIO_MASK 0xfff |
| # define RADEON_VERT_STRETCH_RATIO_SHIFT 0 |
| # define RADEON_VERT_STRETCH_RATIO_MAX 4096 |
| # define RADEON_VERT_STRETCH_ENABLE (1 << 25) |
| # define RADEON_VERT_STRETCH_LINEREP (0 << 26) |
| # define RADEON_VERT_STRETCH_BLEND (1 << 26) |
| # define RADEON_VERT_AUTO_RATIO_EN (1 << 27) |
| # define RADEON_VERT_AUTO_RATIO_INC (1 << 31) |
| # define RADEON_VERT_STRETCH_RESERVED 0x71000000 |
| #define RS400_FP_2ND_GEN_CNTL 0x0384 |
| # define RS400_FP_2ND_ON (1 << 0) |
| # define RS400_FP_2ND_BLANK_EN (1 << 1) |
| # define RS400_TMDS_2ND_EN (1 << 2) |
| # define RS400_PANEL_FORMAT_2ND (1 << 3) |
| # define RS400_FP_2ND_EN_TMDS (1 << 7) |
| # define RS400_FP_2ND_DETECT_SENSE (1 << 8) |
| # define RS400_FP_2ND_SOURCE_SEL_MASK (3 << 10) |
| # define RS400_FP_2ND_SOURCE_SEL_CRTC1 (0 << 10) |
| # define RS400_FP_2ND_SOURCE_SEL_CRTC2 (1 << 10) |
| # define RS400_FP_2ND_SOURCE_SEL_RMX (2 << 10) |
| # define RS400_FP_2ND_DETECT_EN (1 << 12) |
| # define RS400_HPD_2ND_SEL (1 << 13) |
| #define RS400_FP2_2_GEN_CNTL 0x0388 |
| # define RS400_FP2_2_BLANK_EN (1 << 1) |
| # define RS400_FP2_2_ON (1 << 2) |
| # define RS400_FP2_2_PANEL_FORMAT (1 << 3) |
| # define RS400_FP2_2_DETECT_SENSE (1 << 8) |
| # define RS400_FP2_2_SOURCE_SEL_MASK (3 << 10) |
| # define RS400_FP2_2_SOURCE_SEL_CRTC1 (0 << 10) |
| # define RS400_FP2_2_SOURCE_SEL_CRTC2 (1 << 10) |
| # define RS400_FP2_2_SOURCE_SEL_RMX (2 << 10) |
| # define RS400_FP2_2_DVO2_EN (1 << 25) |
| #define RS400_TMDS2_CNTL 0x0394 |
| #define RS400_TMDS2_TRANSMITTER_CNTL 0x03a4 |
| # define RS400_TMDS2_PLLEN (1 << 0) |
| # define RS400_TMDS2_PLLRST (1 << 1) |
| #define RADEON_GEN_INT_CNTL 0x0040 |
| #define RADEON_GEN_INT_STATUS 0x0044 |
| # define RADEON_VSYNC_INT_AK (1 << 2) |
| # define RADEON_VSYNC_INT (1 << 2) |
| # define RADEON_VSYNC2_INT_AK (1 << 6) |
| # define RADEON_VSYNC2_INT (1 << 6) |
| #define RADEON_GENENB 0x03c3 /* VGA */ |
| #define RADEON_GENFC_RD 0x03ca /* VGA */ |
| #define RADEON_GENFC_WT 0x03da /* VGA, 0x03ba */ |
| #define RADEON_GENMO_RD 0x03cc /* VGA */ |
| #define RADEON_GENMO_WT 0x03c2 /* VGA */ |
| #define RADEON_GENS0 0x03c2 /* VGA */ |
| #define RADEON_GENS1 0x03da /* VGA, 0x03ba */ |
| #define RADEON_GPIO_MONID 0x0068 /* DDC interface via I2C */ |
| #define RADEON_GPIO_MONIDB 0x006c |
| #define RADEON_GPIO_CRT2_DDC 0x006c |
| #define RADEON_GPIO_DVI_DDC 0x0064 |
| #define RADEON_GPIO_VGA_DDC 0x0060 |
| # define RADEON_GPIO_A_0 (1 << 0) |
| # define RADEON_GPIO_A_1 (1 << 1) |
| # define RADEON_GPIO_Y_0 (1 << 8) |
| # define RADEON_GPIO_Y_1 (1 << 9) |
| # define RADEON_GPIO_Y_SHIFT_0 8 |
| # define RADEON_GPIO_Y_SHIFT_1 9 |
| # define RADEON_GPIO_EN_0 (1 << 16) |
| # define RADEON_GPIO_EN_1 (1 << 17) |
| # define RADEON_GPIO_MASK_0 (1 << 24) /*??*/ |
| # define RADEON_GPIO_MASK_1 (1 << 25) /*??*/ |
| #define RADEON_GRPH8_DATA 0x03cf /* VGA */ |
| #define RADEON_GRPH8_IDX 0x03ce /* VGA */ |
| #define RADEON_GUI_SCRATCH_REG0 0x15e0 |
| #define RADEON_GUI_SCRATCH_REG1 0x15e4 |
| #define RADEON_GUI_SCRATCH_REG2 0x15e8 |
| #define RADEON_GUI_SCRATCH_REG3 0x15ec |
| #define RADEON_GUI_SCRATCH_REG4 0x15f0 |
| #define RADEON_GUI_SCRATCH_REG5 0x15f4 |
| #define RADEON_HEADER 0x0f0e /* PCI */ |
| #define RADEON_HOST_DATA0 0x17c0 |
| #define RADEON_HOST_DATA1 0x17c4 |
| #define RADEON_HOST_DATA2 0x17c8 |
| #define RADEON_HOST_DATA3 0x17cc |
| #define RADEON_HOST_DATA4 0x17d0 |
| #define RADEON_HOST_DATA5 0x17d4 |
| #define RADEON_HOST_DATA6 0x17d8 |
| #define RADEON_HOST_DATA7 0x17dc |
| #define RADEON_HOST_DATA_LAST 0x17e0 |
| #define RADEON_HOST_PATH_CNTL 0x0130 |
| # define RADEON_HDP_SOFT_RESET (1 << 26) |
| # define RADEON_HDP_APER_CNTL (1 << 23) |
| #define RADEON_HTOTAL_CNTL 0x0009 /* PLL */ |
| # define RADEON_HTOT_CNTL_VGA_EN (1 << 28) |
| #define RADEON_HTOTAL2_CNTL 0x002e /* PLL */ |
| /* Multimedia I2C bus */ |
| #define RADEON_I2C_CNTL_0 0x0090 |
| #define RADEON_I2C_DONE (1<<0) |
| #define RADEON_I2C_NACK (1<<1) |
| #define RADEON_I2C_HALT (1<<2) |
| #define RADEON_I2C_SOFT_RST (1<<5) |
| #define RADEON_I2C_DRIVE_EN (1<<6) |
| #define RADEON_I2C_DRIVE_SEL (1<<7) |
| #define RADEON_I2C_START (1<<8) |
| #define RADEON_I2C_STOP (1<<9) |
| #define RADEON_I2C_RECEIVE (1<<10) |
| #define RADEON_I2C_ABORT (1<<11) |
| #define RADEON_I2C_GO (1<<12) |
| #define RADEON_I2C_CNTL_1 0x0094 |
| #define RADEON_I2C_SEL (1<<16) |
| #define RADEON_I2C_EN (1<<17) |
| #define RADEON_I2C_DATA 0x0098 |
| #define RADEON_DVI_I2C_CNTL_0 0x02e0 |
| #define RADEON_DVI_I2C_CNTL_1 0x02e4 /* ? */ |
| #define RADEON_DVI_I2C_DATA 0x02e8 |
| #define RADEON_INTERRUPT_LINE 0x0f3c /* PCI */ |
| #define RADEON_INTERRUPT_PIN 0x0f3d /* PCI */ |
| #define RADEON_IO_BASE 0x0f14 /* PCI */ |
| #define RADEON_LATENCY 0x0f0d /* PCI */ |
| #define RADEON_LEAD_BRES_DEC 0x1608 |
| #define RADEON_LEAD_BRES_LNTH 0x161c |
| #define RADEON_LEAD_BRES_LNTH_SUB 0x1624 |
| #define RADEON_LVDS_GEN_CNTL 0x02d0 |
| # define RADEON_LVDS_ON (1 << 0) |
| # define RADEON_LVDS_DISPLAY_DIS (1 << 1) |
| # define RADEON_LVDS_PANEL_TYPE (1 << 2) |
| # define RADEON_LVDS_PANEL_FORMAT (1 << 3) |
| # define RADEON_LVDS_RST_FM (1 << 6) |
| # define RADEON_LVDS_EN (1 << 7) |
| # define RADEON_LVDS_BL_MOD_LEVEL_SHIFT 8 |
| # define RADEON_LVDS_BL_MOD_LEVEL_MASK (0xff << 8) |
| # define RADEON_LVDS_BL_MOD_EN (1 << 16) |
| # define RADEON_LVDS_DIGON (1 << 18) |
| # define RADEON_LVDS_BLON (1 << 19) |
| # define RADEON_LVDS_SEL_CRTC2 (1 << 23) |
| #define RADEON_LVDS_PLL_CNTL 0x02d4 |
| # define RADEON_HSYNC_DELAY_SHIFT 28 |
| # define RADEON_HSYNC_DELAY_MASK (0xf << 28) |
| # define RADEON_LVDS_PLL_EN (1 << 16) |
| # define RADEON_LVDS_PLL_RESET (1 << 17) |
| # define R300_LVDS_SRC_SEL_MASK (3 << 18) |
| # define R300_LVDS_SRC_SEL_CRTC1 (0 << 18) |
| # define R300_LVDS_SRC_SEL_CRTC2 (1 << 18) |
| # define R300_LVDS_SRC_SEL_RMX (2 << 18) |
| #define RADEON_MAX_LATENCY 0x0f3f /* PCI */ |
| #define RADEON_MC_AGP_LOCATION 0x014c |
| #define RADEON_MC_FB_LOCATION 0x0148 |
| #define RADEON_DISPLAY_BASE_ADDR 0x23c |
| #define RADEON_DISPLAY2_BASE_ADDR 0x33c |
| #define RADEON_OV0_BASE_ADDR 0x43c |
| #define RADEON_NB_TOM 0x15c |
| #define R300_MC_INIT_MISC_LAT_TIMER 0x180 |
| # define R300_MC_DISP0R_INIT_LAT_SHIFT 8 |
| # define R300_MC_DISP0R_INIT_LAT_MASK 0xf |
| # define R300_MC_DISP1R_INIT_LAT_SHIFT 12 |
| # define R300_MC_DISP1R_INIT_LAT_MASK 0xf |
| #define RADEON_MCLK_CNTL 0x0012 /* PLL */ |
| # define RADEON_FORCEON_MCLKA (1 << 16) |
| # define RADEON_FORCEON_MCLKB (1 << 17) |
| # define RADEON_FORCEON_YCLKA (1 << 18) |
| # define RADEON_FORCEON_YCLKB (1 << 19) |
| # define RADEON_FORCEON_MC (1 << 20) |
| # define RADEON_FORCEON_AIC (1 << 21) |
| # define R300_DISABLE_MC_MCLKA (1 << 21) |
| # define R300_DISABLE_MC_MCLKB (1 << 21) |
| #define RADEON_MCLK_MISC 0x001f /* PLL */ |
| # define RADEON_MC_MCLK_MAX_DYN_STOP_LAT (1 << 12) |
| # define RADEON_IO_MCLK_MAX_DYN_STOP_LAT (1 << 13) |
| # define RADEON_MC_MCLK_DYN_ENABLE (1 << 14) |
| # define RADEON_IO_MCLK_DYN_ENABLE (1 << 15) |
| #define RADEON_LCD_GPIO_MASK 0x01a0 |
| #define RADEON_GPIOPAD_EN 0x01a0 |
| #define RADEON_LCD_GPIO_Y_REG 0x01a4 |
| #define RADEON_MDGPIO_A_REG 0x01ac |
| #define RADEON_MDGPIO_EN_REG 0x01b0 |
| #define RADEON_MDGPIO_MASK 0x0198 |
| #define RADEON_GPIOPAD_MASK 0x0198 |
| #define RADEON_GPIOPAD_A 0x019c |
| #define RADEON_MDGPIO_Y_REG 0x01b4 |
| #define RADEON_MEM_ADDR_CONFIG 0x0148 |
| #define RADEON_MEM_BASE 0x0f10 /* PCI */ |
| #define RADEON_MEM_CNTL 0x0140 |
| # define RADEON_MEM_NUM_CHANNELS_MASK 0x01 |
| # define RADEON_MEM_USE_B_CH_ONLY (1 << 1) |
| # define RV100_HALF_MODE (1 << 3) |
| # define R300_MEM_NUM_CHANNELS_MASK 0x03 |
| # define R300_MEM_USE_CD_CH_ONLY (1 << 2) |
| #define RADEON_MEM_TIMING_CNTL 0x0144 /* EXT_MEM_CNTL */ |
| #define RADEON_MEM_INIT_LAT_TIMER 0x0154 |
| #define RADEON_MEM_INTF_CNTL 0x014c |
| #define RADEON_MEM_SDRAM_MODE_REG 0x0158 |
| # define RADEON_SDRAM_MODE_MASK 0xffff0000 |
| # define RADEON_B3MEM_RESET_MASK 0x6fffffff |
| # define RADEON_MEM_CFG_TYPE_DDR (1 << 30) |
| #define RADEON_MEM_STR_CNTL 0x0150 |
| # define RADEON_MEM_PWRUP_COMPL_A (1 << 0) |
| # define RADEON_MEM_PWRUP_COMPL_B (1 << 1) |
| # define R300_MEM_PWRUP_COMPL_C (1 << 2) |
| # define R300_MEM_PWRUP_COMPL_D (1 << 3) |
| # define RADEON_MEM_PWRUP_COMPLETE 0x03 |
| # define R300_MEM_PWRUP_COMPLETE 0x0f |
| #define RADEON_MC_STATUS 0x0150 |
| # define RADEON_MC_IDLE (1 << 2) |
| # define R300_MC_IDLE (1 << 4) |
| #define RADEON_MEM_VGA_RP_SEL 0x003c |
| #define RADEON_MEM_VGA_WP_SEL 0x0038 |
| #define RADEON_MIN_GRANT 0x0f3e /* PCI */ |
| #define RADEON_MM_DATA 0x0004 |
| #define RADEON_MM_INDEX 0x0000 |
| #define RADEON_MPLL_CNTL 0x000e /* PLL */ |
| #define RADEON_MPP_TB_CONFIG 0x01c0 /* ? */ |
| #define RADEON_MPP_GP_CONFIG 0x01c8 /* ? */ |
| #define RADEON_SEPROM_CNTL1 0x01c0 |
| # define RADEON_SCK_PRESCALE_SHIFT 24 |
| # define RADEON_SCK_PRESCALE_MASK (0xff << 24) |
| #define R300_MC_IND_INDEX 0x01f8 |
| # define R300_MC_IND_ADDR_MASK 0x3f |
| # define R300_MC_IND_WR_EN (1 << 8) |
| #define R300_MC_IND_DATA 0x01fc |
| #define R300_MC_READ_CNTL_AB 0x017c |
| # define R300_MEM_RBS_POSITION_A_MASK 0x03 |
| #define R300_MC_READ_CNTL_CD_mcind 0x24 |
| # define R300_MEM_RBS_POSITION_C_MASK 0x03 |
| #define RADEON_N_VIF_COUNT 0x0248 |
| #define RADEON_OV0_AUTO_FLIP_CNTL 0x0470 |
| # define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_NUM 0x00000007 |
| # define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_REPEAT_FIELD 0x00000008 |
| # define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD 0x00000010 |
| # define RADEON_OV0_AUTO_FLIP_CNTL_IGNORE_REPEAT_FIELD 0x00000020 |
| # define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE 0x00000040 |
| # define RADEON_OV0_AUTO_FLIP_CNTL_VID_PORT_SELECT 0x00000300 |
| # define RADEON_OV0_AUTO_FLIP_CNTL_P1_FIRST_LINE_EVEN 0x00010000 |
| # define RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_EVEN_DOWN 0x00040000 |
| # define RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_ODD_DOWN 0x00080000 |
| # define RADEON_OV0_AUTO_FLIP_CNTL_FIELD_POL_SOURCE 0x00800000 |
| #define RADEON_OV0_COLOUR_CNTL 0x04E0 |
| #define RADEON_OV0_DEINTERLACE_PATTERN 0x0474 |
| #define RADEON_OV0_EXCLUSIVE_HORZ 0x0408 |
| # define RADEON_EXCL_HORZ_START_MASK 0x000000ff |
| # define RADEON_EXCL_HORZ_END_MASK 0x0000ff00 |
| # define RADEON_EXCL_HORZ_BACK_PORCH_MASK 0x00ff0000 |
| # define RADEON_EXCL_HORZ_EXCLUSIVE_EN 0x80000000 |
| #define RADEON_OV0_EXCLUSIVE_VERT 0x040C |
| # define RADEON_EXCL_VERT_START_MASK 0x000003ff |
| # define RADEON_EXCL_VERT_END_MASK 0x03ff0000 |
| #define RADEON_OV0_FILTER_CNTL 0x04A0 |
| # define RADEON_FILTER_PROGRAMMABLE_COEF 0x0 |
| # define RADEON_FILTER_HC_COEF_HORZ_Y 0x1 |
| # define RADEON_FILTER_HC_COEF_HORZ_UV 0x2 |
| # define RADEON_FILTER_HC_COEF_VERT_Y 0x4 |
| # define RADEON_FILTER_HC_COEF_VERT_UV 0x8 |
| # define RADEON_FILTER_HARDCODED_COEF 0xf |
| # define RADEON_FILTER_COEF_MASK 0xf |
| #define RADEON_OV0_FOUR_TAP_COEF_0 0x04B0 |
| #define RADEON_OV0_FOUR_TAP_COEF_1 0x04B4 |
| #define RADEON_OV0_FOUR_TAP_COEF_2 0x04B8 |
| #define RADEON_OV0_FOUR_TAP_COEF_3 0x04BC |
| #define RADEON_OV0_FOUR_TAP_COEF_4 0x04C0 |
| #define RADEON_OV0_FLAG_CNTL 0x04DC |
| #define RADEON_OV0_GAMMA_000_00F 0x0d40 |
| #define RADEON_OV0_GAMMA_010_01F 0x0d44 |
| #define RADEON_OV0_GAMMA_020_03F 0x0d48 |
| #define RADEON_OV0_GAMMA_040_07F 0x0d4c |
| #define RADEON_OV0_GAMMA_080_0BF 0x0e00 |
| #define RADEON_OV0_GAMMA_0C0_0FF 0x0e04 |
| #define RADEON_OV0_GAMMA_100_13F 0x0e08 |
| #define RADEON_OV0_GAMMA_140_17F 0x0e0c |
| #define RADEON_OV0_GAMMA_180_1BF 0x0e10 |
| #define RADEON_OV0_GAMMA_1C0_1FF 0x0e14 |
| #define RADEON_OV0_GAMMA_200_23F 0x0e18 |
| #define RADEON_OV0_GAMMA_240_27F 0x0e1c |
| #define RADEON_OV0_GAMMA_280_2BF 0x0e20 |
| #define RADEON_OV0_GAMMA_2C0_2FF 0x0e24 |
| #define RADEON_OV0_GAMMA_300_33F 0x0e28 |
| #define RADEON_OV0_GAMMA_340_37F 0x0e2c |
| #define RADEON_OV0_GAMMA_380_3BF 0x0d50 |
| #define RADEON_OV0_GAMMA_3C0_3FF 0x0d54 |
| #define RADEON_OV0_GRAPHICS_KEY_CLR_LOW 0x04EC |
| #define RADEON_OV0_GRAPHICS_KEY_CLR_HIGH 0x04F0 |
| #define RADEON_OV0_H_INC 0x0480 |
| #define RADEON_OV0_KEY_CNTL 0x04F4 |
| # define RADEON_VIDEO_KEY_FN_MASK 0x00000003L |
| # define RADEON_VIDEO_KEY_FN_FALSE 0x00000000L |
| # define RADEON_VIDEO_KEY_FN_TRUE 0x00000001L |
| # define RADEON_VIDEO_KEY_FN_EQ 0x00000002L |
| # define RADEON_VIDEO_KEY_FN_NE 0x00000003L |
| # define RADEON_GRAPHIC_KEY_FN_MASK 0x00000030L |
| # define RADEON_GRAPHIC_KEY_FN_FALSE 0x00000000L |
| # define RADEON_GRAPHIC_KEY_FN_TRUE 0x00000010L |
| # define RADEON_GRAPHIC_KEY_FN_EQ 0x00000020L |
| # define RADEON_GRAPHIC_KEY_FN_NE 0x00000030L |
| # define RADEON_CMP_MIX_MASK 0x00000100L |
| # define RADEON_CMP_MIX_OR 0x00000000L |
| # define RADEON_CMP_MIX_AND 0x00000100L |
| #define RADEON_OV0_LIN_TRANS_A 0x0d20 |
| #define RADEON_OV0_LIN_TRANS_B 0x0d24 |
| #define RADEON_OV0_LIN_TRANS_C 0x0d28 |
| #define RADEON_OV0_LIN_TRANS_D 0x0d2c |
| #define RADEON_OV0_LIN_TRANS_E 0x0d30 |
| #define RADEON_OV0_LIN_TRANS_F 0x0d34 |
| #define RADEON_OV0_P1_BLANK_LINES_AT_TOP 0x0430 |
| # define RADEON_P1_BLNK_LN_AT_TOP_M1_MASK 0x00000fffL |
| # define RADEON_P1_ACTIVE_LINES_M1 0x0fff0000L |
| #define RADEON_OV0_P1_H_ACCUM_INIT 0x0488 |
| #define RADEON_OV0_P1_V_ACCUM_INIT 0x0428 |
| # define RADEON_OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003L |
| # define RADEON_OV0_P1_V_ACCUM_INIT_MASK 0x01ff8000L |
| #define RADEON_OV0_P1_X_START_END 0x0494 |
| #define RADEON_OV0_P2_X_START_END 0x0498 |
| #define RADEON_OV0_P23_BLANK_LINES_AT_TOP 0x0434 |
| # define RADEON_P23_BLNK_LN_AT_TOP_M1_MASK 0x000007ffL |
| # define RADEON_P23_ACTIVE_LINES_M1 0x07ff0000L |
| #define RADEON_OV0_P23_H_ACCUM_INIT 0x048C |
| #define RADEON_OV0_P23_V_ACCUM_INIT 0x042C |
| #define RADEON_OV0_P3_X_START_END 0x049C |
| #define RADEON_OV0_REG_LOAD_CNTL 0x0410 |
| # define RADEON_REG_LD_CTL_LOCK 0x00000001L |
| # define RADEON_REG_LD_CTL_VBLANK_DURING_LOCK 0x00000002L |
| # define RADEON_REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L |
| # define RADEON_REG_LD_CTL_LOCK_READBACK 0x00000008L |
| # define RADEON_REG_LD_CTL_FLIP_READBACK 0x00000010L |
| #define RADEON_OV0_SCALE_CNTL 0x0420 |
| # define RADEON_SCALER_HORZ_PICK_NEAREST 0x00000004L |
| # define RADEON_SCALER_VERT_PICK_NEAREST 0x00000008L |
| # define RADEON_SCALER_SIGNED_UV 0x00000010L |
| # define RADEON_SCALER_GAMMA_SEL_MASK 0x00000060L |
| # define RADEON_SCALER_GAMMA_SEL_BRIGHT 0x00000000L |
| # define RADEON_SCALER_GAMMA_SEL_G22 0x00000020L |
| # define RADEON_SCALER_GAMMA_SEL_G18 0x00000040L |
| # define RADEON_SCALER_GAMMA_SEL_G14 0x00000060L |
| # define RADEON_SCALER_COMCORE_SHIFT_UP_ONE 0x00000080L |
| # define RADEON_SCALER_SURFAC_FORMAT 0x00000f00L |
| # define RADEON_SCALER_SOURCE_15BPP 0x00000300L |
| # define RADEON_SCALER_SOURCE_16BPP 0x00000400L |
| # define RADEON_SCALER_SOURCE_32BPP 0x00000600L |
| # define RADEON_SCALER_SOURCE_YUV9 0x00000900L |
| # define RADEON_SCALER_SOURCE_YUV12 0x00000A00L |
| # define RADEON_SCALER_SOURCE_VYUY422 0x00000B00L |
| # define RADEON_SCALER_SOURCE_YVYU422 0x00000C00L |
| # define RADEON_SCALER_ADAPTIVE_DEINT 0x00001000L |
| # define RADEON_SCALER_TEMPORAL_DEINT 0x00002000L |
| # define RADEON_SCALER_CRTC_SEL 0x00004000L |
| # define RADEON_SCALER_SMART_SWITCH 0x00008000L |
| # define RADEON_SCALER_BURST_PER_PLANE 0x007F0000L |
| # define RADEON_SCALER_DOUBLE_BUFFER 0x01000000L |
| # define RADEON_SCALER_DIS_LIMIT 0x08000000L |
| # define RADEON_SCALER_LIN_TRANS_BYPASS 0x10000000L |
| # define RADEON_SCALER_INT_EMU 0x20000000L |
| # define RADEON_SCALER_ENABLE 0x40000000L |
| # define RADEON_SCALER_SOFT_RESET 0x80000000L |
| #define RADEON_OV0_STEP_BY 0x0484 |
| #define RADEON_OV0_TEST 0x04F8 |
| #define RADEON_OV0_V_INC 0x0424 |
| #define RADEON_OV0_VID_BUF_PITCH0_VALUE 0x0460 |
| #define RADEON_OV0_VID_BUF_PITCH1_VALUE 0x0464 |
| #define RADEON_OV0_VID_BUF0_BASE_ADRS 0x0440 |
| # define RADEON_VIF_BUF0_PITCH_SEL 0x00000001L |
| # define RADEON_VIF_BUF0_TILE_ADRS 0x00000002L |
| # define RADEON_VIF_BUF0_BASE_ADRS_MASK 0x03fffff0L |
| # define RADEON_VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L |
| #define RADEON_OV0_VID_BUF1_BASE_ADRS 0x0444 |
| # define RADEON_VIF_BUF1_PITCH_SEL 0x00000001L |
| # define RADEON_VIF_BUF1_TILE_ADRS 0x00000002L |
| # define RADEON_VIF_BUF1_BASE_ADRS_MASK 0x03fffff0L |
| # define RADEON_VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L |
| #define RADEON_OV0_VID_BUF2_BASE_ADRS 0x0448 |
| # define RADEON_VIF_BUF2_PITCH_SEL 0x00000001L |
| # define RADEON_VIF_BUF2_TILE_ADRS 0x00000002L |
| # define RADEON_VIF_BUF2_BASE_ADRS_MASK 0x03fffff0L |
| # define RADEON_VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L |
| #define RADEON_OV0_VID_BUF3_BASE_ADRS 0x044C |
| #define RADEON_OV0_VID_BUF4_BASE_ADRS 0x0450 |
| #define RADEON_OV0_VID_BUF5_BASE_ADRS 0x0454 |
| #define RADEON_OV0_VIDEO_KEY_CLR_HIGH 0x04E8 |
| #define RADEON_OV0_VIDEO_KEY_CLR_LOW 0x04E4 |
| #define RADEON_OV0_Y_X_START 0x0400 |
| #define RADEON_OV0_Y_X_END 0x0404 |
| #define RADEON_OV1_Y_X_START 0x0600 |
| #define RADEON_OV1_Y_X_END 0x0604 |
| #define RADEON_OVR_CLR 0x0230 |
| #define RADEON_OVR_WID_LEFT_RIGHT 0x0234 |
| #define RADEON_OVR_WID_TOP_BOTTOM 0x0238 |
| /* first capture unit */ |
| #define RADEON_CAP0_BUF0_OFFSET 0x0920 |
| #define RADEON_CAP0_BUF1_OFFSET 0x0924 |
| #define RADEON_CAP0_BUF0_EVEN_OFFSET 0x0928 |
| #define RADEON_CAP0_BUF1_EVEN_OFFSET 0x092C |
| #define RADEON_CAP0_BUF_PITCH 0x0930 |
| #define RADEON_CAP0_V_WINDOW 0x0934 |
| #define RADEON_CAP0_H_WINDOW 0x0938 |
| #define RADEON_CAP0_VBI0_OFFSET 0x093C |
| #define RADEON_CAP0_VBI1_OFFSET 0x0940 |
| #define RADEON_CAP0_VBI_V_WINDOW 0x0944 |
| #define RADEON_CAP0_VBI_H_WINDOW 0x0948 |
| #define RADEON_CAP0_PORT_MODE_CNTL 0x094C |
| #define RADEON_CAP0_TRIG_CNTL 0x0950 |
| #define RADEON_CAP0_DEBUG 0x0954 |
| #define RADEON_CAP0_CONFIG 0x0958 |
| # define RADEON_CAP0_CONFIG_CONTINUOS 0x00000001 |
| # define RADEON_CAP0_CONFIG_START_FIELD_EVEN 0x00000002 |
| # define RADEON_CAP0_CONFIG_START_BUF_GET 0x00000004 |
| # define RADEON_CAP0_CONFIG_START_BUF_SET 0x00000008 |
| # define RADEON_CAP0_CONFIG_BUF_TYPE_ALT 0x00000010 |
| # define RADEON_CAP0_CONFIG_BUF_TYPE_FRAME 0x00000020 |
| # define RADEON_CAP0_CONFIG_ONESHOT_MODE_FRAME 0x00000040 |
| # define RADEON_CAP0_CONFIG_BUF_MODE_DOUBLE 0x00000080 |
| # define RADEON_CAP0_CONFIG_BUF_MODE_TRIPLE 0x00000100 |
| # define RADEON_CAP0_CONFIG_MIRROR_EN 0x00000200 |
| # define RADEON_CAP0_CONFIG_ONESHOT_MIRROR_EN 0x00000400 |
| # define RADEON_CAP0_CONFIG_VIDEO_SIGNED_UV 0x00000800 |
| # define RADEON_CAP0_CONFIG_ANC_DECODE_EN 0x00001000 |
| # define RADEON_CAP0_CONFIG_VBI_EN 0x00002000 |
| # define RADEON_CAP0_CONFIG_SOFT_PULL_DOWN_EN 0x00004000 |
| # define RADEON_CAP0_CONFIG_VIP_EXTEND_FLAG_EN 0x00008000 |
| # define RADEON_CAP0_CONFIG_FAKE_FIELD_EN 0x00010000 |
| # define RADEON_CAP0_CONFIG_ODD_ONE_MORE_LINE 0x00020000 |
| # define RADEON_CAP0_CONFIG_EVEN_ONE_MORE_LINE 0x00040000 |
| # define RADEON_CAP0_CONFIG_HORZ_DIVIDE_2 0x00080000 |
| # define RADEON_CAP0_CONFIG_HORZ_DIVIDE_4 0x00100000 |
| # define RADEON_CAP0_CONFIG_VERT_DIVIDE_2 0x00200000 |
| # define RADEON_CAP0_CONFIG_VERT_DIVIDE_4 0x00400000 |
| # define RADEON_CAP0_CONFIG_FORMAT_BROOKTREE 0x00000000 |
| # define RADEON_CAP0_CONFIG_FORMAT_CCIR656 0x00800000 |
| # define RADEON_CAP0_CONFIG_FORMAT_ZV 0x01000000 |
| # define RADEON_CAP0_CONFIG_FORMAT_VIP 0x01800000 |
| # define RADEON_CAP0_CONFIG_FORMAT_TRANSPORT 0x02000000 |
| # define RADEON_CAP0_CONFIG_HORZ_DECIMATOR 0x04000000 |
| # define RADEON_CAP0_CONFIG_VIDEO_IN_YVYU422 0x00000000 |
| # define RADEON_CAP0_CONFIG_VIDEO_IN_VYUY422 0x20000000 |
| # define RADEON_CAP0_CONFIG_VBI_DIVIDE_2 0x40000000 |
| # define RADEON_CAP0_CONFIG_VBI_DIVIDE_4 0x80000000 |
| #define RADEON_CAP0_ANC_ODD_OFFSET 0x095C |
| #define RADEON_CAP0_ANC_EVEN_OFFSET 0x0960 |
| #define RADEON_CAP0_ANC_H_WINDOW 0x0964 |
| #define RADEON_CAP0_VIDEO_SYNC_TEST 0x0968 |
| #define RADEON_CAP0_ONESHOT_BUF_OFFSET 0x096C |
| #define RADEON_CAP0_BUF_STATUS 0x0970 |
| /* #define RADEON_CAP0_DWNSC_XRATIO 0x0978 */ |
| /* #define RADEON_CAP0_XSHARPNESS 0x097C */ |
| #define RADEON_CAP0_VBI2_OFFSET 0x0980 |
| #define RADEON_CAP0_VBI3_OFFSET 0x0984 |
| #define RADEON_CAP0_ANC2_OFFSET 0x0988 |
| #define RADEON_CAP0_ANC3_OFFSET 0x098C |
| #define RADEON_VID_BUFFER_CONTROL 0x0900 |
| /* second capture unit */ |
| #define RADEON_CAP1_BUF0_OFFSET 0x0990 |
| #define RADEON_CAP1_BUF1_OFFSET 0x0994 |
| #define RADEON_CAP1_BUF0_EVEN_OFFSET 0x0998 |
| #define RADEON_CAP1_BUF1_EVEN_OFFSET 0x099C |
| #define RADEON_CAP1_BUF_PITCH 0x09A0 |
| #define RADEON_CAP1_V_WINDOW 0x09A4 |
| #define RADEON_CAP1_H_WINDOW 0x09A8 |
| #define RADEON_CAP1_VBI_ODD_OFFSET 0x09AC |
| #define RADEON_CAP1_VBI_EVEN_OFFSET 0x09B0 |
| #define RADEON_CAP1_VBI_V_WINDOW 0x09B4 |
| #define RADEON_CAP1_VBI_H_WINDOW 0x09B8 |
| #define RADEON_CAP1_PORT_MODE_CNTL 0x09BC |
| #define RADEON_CAP1_TRIG_CNTL 0x09C0 |
| #define RADEON_CAP1_DEBUG 0x09C4 |
| #define RADEON_CAP1_CONFIG 0x09C8 |
| #define RADEON_CAP1_ANC_ODD_OFFSET 0x09CC |
| #define RADEON_CAP1_ANC_EVEN_OFFSET 0x09D0 |
| #define RADEON_CAP1_ANC_H_WINDOW 0x09D4 |
| #define RADEON_CAP1_VIDEO_SYNC_TEST 0x09D8 |
| #define RADEON_CAP1_ONESHOT_BUF_OFFSET 0x09DC |
| #define RADEON_CAP1_BUF_STATUS 0x09E0 |
| #define RADEON_CAP1_DWNSC_XRATIO 0x09E8 |
| #define RADEON_CAP1_XSHARPNESS 0x09EC |
| /* misc multimedia registers */ |
| #define RADEON_IDCT_RUNS 0x1F80 |
| #define RADEON_IDCT_LEVELS 0x1F84 |
| #define RADEON_IDCT_CONTROL 0x1FBC |
| #define RADEON_IDCT_AUTH_CONTROL 0x1F88 |
| #define RADEON_IDCT_AUTH 0x1F8C |
| #define RADEON_P2PLL_CNTL 0x002a /* P2PLL */ |
| # define RADEON_P2PLL_RESET (1 << 0) |
| # define RADEON_P2PLL_SLEEP (1 << 1) |
| # define RADEON_P2PLL_PVG_MASK (7 << 11) |
| # define RADEON_P2PLL_PVG_SHIFT 11 |
| # define RADEON_P2PLL_ATOMIC_UPDATE_EN (1 << 16) |
| # define RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN (1 << 17) |
| # define RADEON_P2PLL_ATOMIC_UPDATE_VSYNC (1 << 18) |
| #define RADEON_P2PLL_DIV_0 0x002c |
| # define RADEON_P2PLL_FB0_DIV_MASK 0x07ff |
| # define RADEON_P2PLL_POST0_DIV_MASK 0x00070000 |
| #define RADEON_P2PLL_REF_DIV 0x002B /* PLL */ |
| # define RADEON_P2PLL_REF_DIV_MASK 0x03ff |
| # define RADEON_P2PLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ |
| # define RADEON_P2PLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ |
| # define R300_PPLL_REF_DIV_ACC_MASK (0x3ff << 18) |
| # define R300_PPLL_REF_DIV_ACC_SHIFT 18 |
| #define RADEON_PALETTE_DATA 0x00b4 |
| #define RADEON_PALETTE_30_DATA 0x00b8 |
| #define RADEON_PALETTE_INDEX 0x00b0 |
| #define RADEON_PCI_GART_PAGE 0x017c |
| #define RADEON_PIXCLKS_CNTL 0x002d |
| # define RADEON_PIX2CLK_SRC_SEL_MASK 0x03 |
| # define RADEON_PIX2CLK_SRC_SEL_CPUCLK 0x00 |
| # define RADEON_PIX2CLK_SRC_SEL_PSCANCLK 0x01 |
| # define RADEON_PIX2CLK_SRC_SEL_BYTECLK 0x02 |
| # define RADEON_PIX2CLK_SRC_SEL_P2PLLCLK 0x03 |
| # define RADEON_PIX2CLK_ALWAYS_ONb (1<<6) |
| # define RADEON_PIX2CLK_DAC_ALWAYS_ONb (1<<7) |
| # define RADEON_PIXCLK_TV_SRC_SEL (1 << 8) |
| # define RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb (1 << 9) |
| # define R300_DVOCLK_ALWAYS_ONb (1 << 10) |
| # define RADEON_PIXCLK_BLEND_ALWAYS_ONb (1 << 11) |
| # define RADEON_PIXCLK_GV_ALWAYS_ONb (1 << 12) |
| # define RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb (1 << 13) |
| # define R300_PIXCLK_DVO_ALWAYS_ONb (1 << 13) |
| # define RADEON_PIXCLK_LVDS_ALWAYS_ONb (1 << 14) |
| # define RADEON_PIXCLK_TMDS_ALWAYS_ONb (1 << 15) |
| # define R300_PIXCLK_TRANS_ALWAYS_ONb (1 << 16) |
| # define R300_PIXCLK_TVO_ALWAYS_ONb (1 << 17) |
| # define R300_P2G2CLK_ALWAYS_ONb (1 << 18) |
| # define R300_P2G2CLK_DAC_ALWAYS_ONb (1 << 19) |
| # define R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23) |
| #define RADEON_PLANE_3D_MASK_C 0x1d44 |
| #define RADEON_PLL_TEST_CNTL 0x0013 /* PLL */ |
| # define RADEON_PLL_MASK_READ_B (1 << 9) |
| #define RADEON_PMI_CAP_ID 0x0f5c /* PCI */ |
| #define RADEON_PMI_DATA 0x0f63 /* PCI */ |
| #define RADEON_PMI_NXT_CAP_PTR 0x0f5d /* PCI */ |
| #define RADEON_PMI_PMC_REG 0x0f5e /* PCI */ |
| #define RADEON_PMI_PMCSR_REG 0x0f60 /* PCI */ |
| #define RADEON_PMI_REGISTER 0x0f5c /* PCI */ |
| #define RADEON_PPLL_CNTL 0x0002 /* PLL */ |
| # define RADEON_PPLL_RESET (1 << 0) |
| # define RADEON_PPLL_SLEEP (1 << 1) |
| # define RADEON_PPLL_PVG_MASK (7 << 11) |
| # define RADEON_PPLL_PVG_SHIFT 11 |
| # define RADEON_PPLL_ATOMIC_UPDATE_EN (1 << 16) |
| # define RADEON_PPLL_VGA_ATOMIC_UPDATE_EN (1 << 17) |
| # define RADEON_PPLL_ATOMIC_UPDATE_VSYNC (1 << 18) |
| #define RADEON_PPLL_DIV_0 0x0004 /* PLL */ |
| #define RADEON_PPLL_DIV_1 0x0005 /* PLL */ |
| #define RADEON_PPLL_DIV_2 0x0006 /* PLL */ |
| #define RADEON_PPLL_DIV_3 0x0007 /* PLL */ |
| # define RADEON_PPLL_FB3_DIV_MASK 0x07ff |
| # define RADEON_PPLL_POST3_DIV_MASK 0x00070000 |
| #define RADEON_PPLL_REF_DIV 0x0003 /* PLL */ |
| # define RADEON_PPLL_REF_DIV_MASK 0x03ff |
| # define RADEON_PPLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ |
| # define RADEON_PPLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ |
| #define RADEON_PWR_MNGMT_CNTL_STATUS 0x0f60 /* PCI */ |
| #define RADEON_RBBM_GUICNTL 0x172c |
| # define RADEON_HOST_DATA_SWAP_NONE (0 << 0) |
| # define RADEON_HOST_DATA_SWAP_16BIT (1 << 0) |
| # define RADEON_HOST_DATA_SWAP_32BIT (2 << 0) |
| # define RADEON_HOST_DATA_SWAP_HDW (3 << 0) |
| #define RADEON_RBBM_SOFT_RESET 0x00f0 |
| # define RADEON_SOFT_RESET_CP (1 << 0) |
| # define RADEON_SOFT_RESET_HI (1 << 1) |
| # define RADEON_SOFT_RESET_SE (1 << 2) |
| # define RADEON_SOFT_RESET_RE (1 << 3) |
| # define RADEON_SOFT_RESET_PP (1 << 4) |
| # define RADEON_SOFT_RESET_E2 (1 << 5) |
| # define RADEON_SOFT_RESET_RB (1 << 6) |
| # define RADEON_SOFT_RESET_HDP (1 << 7) |
| #define RADEON_RBBM_STATUS 0x0e40 |
| # define RADEON_RBBM_FIFOCNT_MASK 0x007f |
| # define RADEON_RBBM_ACTIVE (1 << 31) |
| #define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c |
| # define RADEON_RB2D_DC_FLUSH (3 << 0) |
| # define RADEON_RB2D_DC_FREE (3 << 2) |
| # define RADEON_RB2D_DC_FLUSH_ALL 0xf |
| # define RADEON_RB2D_DC_BUSY (1 << 31) |
| #define RADEON_RB2D_DSTCACHE_MODE 0x3428 |
| #define RADEON_DSTCACHE_CTLSTAT 0x1714 |
| #define RADEON_RB3D_ZCACHE_MODE 0x3250 |
| #define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254 |
| # define RADEON_RB3D_ZC_FLUSH_ALL 0x5 |
| #define RADEON_RB3D_DSTCACHE_MODE 0x3258 |
| # define RADEON_RB3D_DC_CACHE_ENABLE (0) |
| # define RADEON_RB3D_DC_2D_CACHE_DISABLE (1) |
| # define RADEON_RB3D_DC_3D_CACHE_DISABLE (2) |
| # define RADEON_RB3D_DC_CACHE_DISABLE (3) |
| # define RADEON_RB3D_DC_2D_CACHE_LINESIZE_128 (1 << 2) |
| # define RADEON_RB3D_DC_3D_CACHE_LINESIZE_128 (2 << 2) |
| # define RADEON_RB3D_DC_2D_CACHE_AUTOFLUSH (1 << 8) |
| # define RADEON_RB3D_DC_3D_CACHE_AUTOFLUSH (2 << 8) |
| # define R200_RB3D_DC_2D_CACHE_AUTOFREE (1 << 10) |
| # define R200_RB3D_DC_3D_CACHE_AUTOFREE (2 << 10) |
| # define RADEON_RB3D_DC_FORCE_RMW (1 << 16) |
| # define RADEON_RB3D_DC_DISABLE_RI_FILL (1 << 24) |
| # define RADEON_RB3D_DC_DISABLE_RI_READ (1 << 25) |
| #define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325C |
| # define RADEON_RB3D_DC_FLUSH (3 << 0) |
| # define RADEON_RB3D_DC_FREE (3 << 2) |
| # define RADEON_RB3D_DC_FLUSH_ALL 0xf |
| # define RADEON_RB3D_DC_BUSY (1 << 31) |
| #define RADEON_REG_BASE 0x0f18 /* PCI */ |
| #define RADEON_REGPROG_INF 0x0f09 /* PCI */ |
| #define RADEON_REVISION_ID 0x0f08 /* PCI */ |
| #define RADEON_SC_BOTTOM 0x164c |
| #define RADEON_SC_BOTTOM_RIGHT 0x16f0 |
| #define RADEON_SC_BOTTOM_RIGHT_C 0x1c8c |
| #define RADEON_SC_LEFT 0x1640 |
| #define RADEON_SC_RIGHT 0x1644 |
| #define RADEON_SC_TOP 0x1648 |
| #define RADEON_SC_TOP_LEFT 0x16ec |
| #define RADEON_SC_TOP_LEFT_C 0x1c88 |
| # define RADEON_SC_SIGN_MASK_LO 0x8000 |
| # define RADEON_SC_SIGN_MASK_HI 0x80000000 |
| #define RADEON_SCLK_CNTL 0x000d /* PLL */ |
| # define RADEON_SCLK_SRC_SEL_MASK 0x0007 |
| # define RADEON_DYN_STOP_LAT_MASK 0x00007ff8 |
| # define RADEON_CP_MAX_DYN_STOP_LAT 0x0008 |
| # define RADEON_SCLK_FORCEON_MASK 0xffff8000 |
| # define RADEON_SCLK_FORCE_DISP2 (1<<15) |
| # define RADEON_SCLK_FORCE_CP (1<<16) |
| # define RADEON_SCLK_FORCE_HDP (1<<17) |
| # define RADEON_SCLK_FORCE_DISP1 (1<<18) |
| # define RADEON_SCLK_FORCE_TOP (1<<19) |
| # define RADEON_SCLK_FORCE_E2 (1<<20) |
| # define RADEON_SCLK_FORCE_SE (1<<21) |
| # define RADEON_SCLK_FORCE_IDCT (1<<22) |
| # define RADEON_SCLK_FORCE_VIP (1<<23) |
| # define RADEON_SCLK_FORCE_RE (1<<24) |
| # define RADEON_SCLK_FORCE_PB (1<<25) |
| # define RADEON_SCLK_FORCE_TAM (1<<26) |
| # define RADEON_SCLK_FORCE_TDM (1<<27) |
| # define RADEON_SCLK_FORCE_RB (1<<28) |
| # define RADEON_SCLK_FORCE_TV_SCLK (1<<29) |
| # define RADEON_SCLK_FORCE_SUBPIC (1<<30) |
| # define RADEON_SCLK_FORCE_OV0 (1<<31) |
| # define R300_SCLK_FORCE_VAP (1<<21) |
| # define R300_SCLK_FORCE_SR (1<<25) |
| # define R300_SCLK_FORCE_PX (1<<26) |
| # define R300_SCLK_FORCE_TX (1<<27) |
| # define R300_SCLK_FORCE_US (1<<28) |
| # define R300_SCLK_FORCE_SU (1<<30) |
| #define R300_SCLK_CNTL2 0x1e /* PLL */ |
| # define R300_SCLK_TCL_MAX_DYN_STOP_LAT (1<<10) |
| # define R300_SCLK_GA_MAX_DYN_STOP_LAT (1<<11) |
| # define R300_SCLK_CBA_MAX_DYN_STOP_LAT (1<<12) |
| # define R300_SCLK_FORCE_TCL (1<<13) |
| # define R300_SCLK_FORCE_CBA (1<<14) |
| # define R300_SCLK_FORCE_GA (1<<15) |
| #define RADEON_SCLK_MORE_CNTL 0x0035 /* PLL */ |
| # define RADEON_SCLK_MORE_MAX_DYN_STOP_LAT 0x0007 |
| # define RADEON_SCLK_MORE_FORCEON 0x0700 |
| #define RADEON_SDRAM_MODE_REG 0x0158 |
| #define RADEON_SEQ8_DATA 0x03c5 /* VGA */ |
| #define RADEON_SEQ8_IDX 0x03c4 /* VGA */ |
| #define RADEON_SNAPSHOT_F_COUNT 0x0244 |
| #define RADEON_SNAPSHOT_VH_COUNTS 0x0240 |
| #define RADEON_SNAPSHOT_VIF_COUNT 0x024c |
| #define RADEON_SRC_OFFSET 0x15ac |
| #define RADEON_SRC_PITCH 0x15b0 |
| #define RADEON_SRC_PITCH_OFFSET 0x1428 |
| #define RADEON_SRC_SC_BOTTOM 0x165c |
| #define RADEON_SRC_SC_BOTTOM_RIGHT 0x16f4 |
| #define RADEON_SRC_SC_RIGHT 0x1654 |
| #define RADEON_SRC_X 0x1414 |
| #define RADEON_SRC_X_Y 0x1590 |
| #define RADEON_SRC_Y 0x1418 |
| #define RADEON_SRC_Y_X 0x1434 |
| #define RADEON_STATUS 0x0f06 /* PCI */ |
| #define RADEON_SUBPIC_CNTL 0x0540 /* ? */ |
| #define RADEON_SUB_CLASS 0x0f0a /* PCI */ |
| #define RADEON_SURFACE_CNTL 0x0b00 |
| # define RADEON_SURF_TRANSLATION_DIS (1 << 8) |
| # define RADEON_NONSURF_AP0_SWP_16BPP (1 << 20) |
| # define RADEON_NONSURF_AP0_SWP_32BPP (1 << 21) |
| # define RADEON_NONSURF_AP1_SWP_16BPP (1 << 22) |
| # define RADEON_NONSURF_AP1_SWP_32BPP (1 << 23) |
| #define RADEON_SURFACE0_INFO 0x0b0c |
| # define RADEON_SURF_TILE_COLOR_MACRO (0 << 16) |
| # define RADEON_SURF_TILE_COLOR_BOTH (1 << 16) |
| # define RADEON_SURF_TILE_DEPTH_32BPP (2 << 16) |
| # define RADEON_SURF_TILE_DEPTH_16BPP (3 << 16) |
| # define R200_SURF_TILE_NONE (0 << 16) |
| # define R200_SURF_TILE_COLOR_MACRO (1 << 16) |
| # define R200_SURF_TILE_COLOR_MICRO (2 << 16) |
| # define R200_SURF_TILE_COLOR_BOTH (3 << 16) |
| # define R200_SURF_TILE_DEPTH_32BPP (4 << 16) |
| # define R200_SURF_TILE_DEPTH_16BPP (5 << 16) |
| # define R300_SURF_TILE_NONE (0 << 16) |
| # define R300_SURF_TILE_COLOR_MACRO (1 << 16) |
| # define R300_SURF_TILE_DEPTH_32BPP (2 << 16) |
| # define RADEON_SURF_AP0_SWP_16BPP (1 << 20) |
| # define RADEON_SURF_AP0_SWP_32BPP (1 << 21) |
| # define RADEON_SURF_AP1_SWP_16BPP (1 << 22) |
| # define RADEON_SURF_AP1_SWP_32BPP (1 << 23) |
| #define RADEON_SURFACE0_LOWER_BOUND 0x0b04 |
| #define RADEON_SURFACE0_UPPER_BOUND 0x0b08 |
| #define RADEON_SURFACE1_INFO 0x0b1c |
| #define RADEON_SURFACE1_LOWER_BOUND 0x0b14 |
| #define RADEON_SURFACE1_UPPER_BOUND 0x0b18 |
| #define RADEON_SURFACE2_INFO 0x0b2c |
| #define RADEON_SURFACE2_LOWER_BOUND 0x0b24 |
| #define RADEON_SURFACE2_UPPER_BOUND 0x0b28 |
| #define RADEON_SURFACE3_INFO 0x0b3c |
| #define RADEON_SURFACE3_LOWER_BOUND 0x0b34 |
| #define RADEON_SURFACE3_UPPER_BOUND 0x0b38 |
| #define RADEON_SURFACE4_INFO 0x0b4c |
| #define RADEON_SURFACE4_LOWER_BOUND 0x0b44 |
| #define RADEON_SURFACE4_UPPER_BOUND 0x0b48 |
| #define RADEON_SURFACE5_INFO 0x0b5c |
| #define RADEON_SURFACE5_LOWER_BOUND 0x0b54 |
| #define RADEON_SURFACE5_UPPER_BOUND 0x0b58 |
| #define RADEON_SURFACE6_INFO 0x0b6c |
| #define RADEON_SURFACE6_LOWER_BOUND 0x0b64 |
| #define RADEON_SURFACE6_UPPER_BOUND 0x0b68 |
| #define RADEON_SURFACE7_INFO 0x0b7c |
| #define RADEON_SURFACE7_LOWER_BOUND 0x0b74 |
| #define RADEON_SURFACE7_UPPER_BOUND 0x0b78 |
| #define RADEON_SW_SEMAPHORE 0x013c |
| #define RADEON_TEST_DEBUG_CNTL 0x0120 |
| #define RADEON_TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN 0x00000001 |
| #define RADEON_TEST_DEBUG_MUX 0x0124 |
| #define RADEON_TEST_DEBUG_OUT 0x012c |
| #define RADEON_TMDS_PLL_CNTL 0x02a8 |
| #define RADEON_TMDS_TRANSMITTER_CNTL 0x02a4 |
| # define RADEON_TMDS_TRANSMITTER_PLLEN 1 |
| # define RADEON_TMDS_TRANSMITTER_PLLRST 2 |
| #define RADEON_TRAIL_BRES_DEC 0x1614 |
| #define RADEON_TRAIL_BRES_ERR 0x160c |
| #define RADEON_TRAIL_BRES_INC 0x1610 |
| #define RADEON_TRAIL_X 0x1618 |
| #define RADEON_TRAIL_X_SUB 0x1620 |
| #define RADEON_VCLK_ECP_CNTL 0x0008 /* PLL */ |
| # define RADEON_VCLK_SRC_SEL_MASK 0x03 |
| # define RADEON_VCLK_SRC_SEL_CPUCLK 0x00 |
| # define RADEON_VCLK_SRC_SEL_PSCANCLK 0x01 |
| # define RADEON_VCLK_SRC_SEL_BYTECLK 0x02 |
| # define RADEON_VCLK_SRC_SEL_PPLLCLK 0x03 |
| # define RADEON_PIXCLK_ALWAYS_ONb (1<<6) |
| # define RADEON_PIXCLK_DAC_ALWAYS_ONb (1<<7) |
| # define R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF (1<<23) |
| #define RADEON_VENDOR_ID 0x0f00 /* PCI */ |
| #define RADEON_VGA_DDA_CONFIG 0x02e8 |
| #define RADEON_VGA_DDA_ON_OFF 0x02ec |
| #define RADEON_VID_BUFFER_CONTROL 0x0900 |
| #define RADEON_VIDEOMUX_CNTL 0x0190 |
| /* VIP bus */ |
| #define RADEON_VIPH_CH0_DATA 0x0c00 |
| #define RADEON_VIPH_CH1_DATA 0x0c04 |
| #define RADEON_VIPH_CH2_DATA 0x0c08 |
| #define RADEON_VIPH_CH3_DATA 0x0c0c |
| #define RADEON_VIPH_CH0_ADDR 0x0c10 |
| #define RADEON_VIPH_CH1_ADDR 0x0c14 |
| #define RADEON_VIPH_CH2_ADDR 0x0c18 |
| #define RADEON_VIPH_CH3_ADDR 0x0c1c |
| #define RADEON_VIPH_CH0_SBCNT 0x0c20 |
| #define RADEON_VIPH_CH1_SBCNT 0x0c24 |
| #define RADEON_VIPH_CH2_SBCNT 0x0c28 |
| #define RADEON_VIPH_CH3_SBCNT 0x0c2c |
| #define RADEON_VIPH_CH0_ABCNT 0x0c30 |
| #define RADEON_VIPH_CH1_ABCNT 0x0c34 |
| #define RADEON_VIPH_CH2_ABCNT 0x0c38 |
| #define RADEON_VIPH_CH3_ABCNT 0x0c3c |
| #define RADEON_VIPH_CONTROL 0x0c40 |
| # define RADEON_VIP_BUSY 0 |
| # define RADEON_VIP_IDLE 1 |
| # define RADEON_VIP_RESET 2 |
| # define RADEON_VIPH_EN (1 << 21) |
| #define RADEON_VIPH_DV_LAT 0x0c44 |
| #define RADEON_VIPH_BM_CHUNK 0x0c48 |
| #define RADEON_VIPH_DV_INT 0x0c4c |
| #define RADEON_VIPH_TIMEOUT_STAT 0x0c50 |
| #define RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_STAT 0x00000010 |
| #define RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_AK 0x00000010 |
| #define RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS 0x01000000 |
| #define RADEON_VIPH_REG_DATA 0x0084 |
| #define RADEON_VIPH_REG_ADDR 0x0080 |
| #define RADEON_WAIT_UNTIL 0x1720 |
| # define RADEON_WAIT_CRTC_PFLIP (1 << 0) |
| # define RADEON_WAIT_RE_CRTC_VLINE (1 << 1) |
| # define RADEON_WAIT_FE_CRTC_VLINE (1 << 2) |
| # define RADEON_WAIT_CRTC_VLINE (1 << 3) |
| # define RADEON_WAIT_DMA_VID_IDLE (1 << 8) |
| # define RADEON_WAIT_DMA_GUI_IDLE (1 << 9) |
| # define RADEON_WAIT_CMDFIFO (1 << 10) /* wait for CMDFIFO_ENTRIES */ |
| # define RADEON_WAIT_OV0_FLIP (1 << 11) |
| # define RADEON_WAIT_AGP_FLUSH (1 << 13) |
| # define RADEON_WAIT_2D_IDLE (1 << 14) |
| # define RADEON_WAIT_3D_IDLE (1 << 15) |
| # define RADEON_WAIT_2D_IDLECLEAN (1 << 16) |
| # define RADEON_WAIT_3D_IDLECLEAN (1 << 17) |
| # define RADEON_WAIT_HOST_IDLECLEAN (1 << 18) |
| # define RADEON_CMDFIFO_ENTRIES_SHIFT 10 |
| # define RADEON_CMDFIFO_ENTRIES_MASK 0x7f |
| # define RADEON_WAIT_VAP_IDLE (1 << 28) |
| # define RADEON_WAIT_BOTH_CRTC_PFLIP (1 << 30) |
| # define RADEON_ENG_DISPLAY_SELECT_CRTC0 (0 << 31) |
| # define RADEON_ENG_DISPLAY_SELECT_CRTC1 (1 << 31) |
| #define RADEON_X_MPLL_REF_FB_DIV 0x000a /* PLL */ |
| #define RADEON_XCLK_CNTL 0x000d /* PLL */ |
| #define RADEON_XDLL_CNTL 0x000c /* PLL */ |
| #define RADEON_XPLL_CNTL 0x000b /* PLL */ |
| /* Registers for 3D/TCL */ |
| #define RADEON_PP_BORDER_COLOR_0 0x1d40 |
| #define RADEON_PP_BORDER_COLOR_1 0x1d44 |
| #define RADEON_PP_BORDER_COLOR_2 0x1d48 |
| #define RADEON_PP_CNTL 0x1c38 |
| # define RADEON_STIPPLE_ENABLE (1 << 0) |
| # define RADEON_SCISSOR_ENABLE (1 << 1) |
| # define RADEON_PATTERN_ENABLE (1 << 2) |
| # define RADEON_SHADOW_ENABLE (1 << 3) |
| # define RADEON_TEX_ENABLE_MASK (0xf << 4) |
| # define RADEON_TEX_0_ENABLE (1 << 4) |
| # define RADEON_TEX_1_ENABLE (1 << 5) |
| # define RADEON_TEX_2_ENABLE (1 << 6) |
| # define RADEON_TEX_3_ENABLE (1 << 7) |
| # define RADEON_TEX_BLEND_ENABLE_MASK (0xf << 12) |
| # define RADEON_TEX_BLEND_0_ENABLE (1 << 12) |
| # define RADEON_TEX_BLEND_1_ENABLE (1 << 13) |
| # define RADEON_TEX_BLEND_2_ENABLE (1 << 14) |
| # define RADEON_TEX_BLEND_3_ENABLE (1 << 15) |
| # define RADEON_PLANAR_YUV_ENABLE (1 << 20) |
| # define RADEON_SPECULAR_ENABLE (1 << 21) |
| # define RADEON_FOG_ENABLE (1 << 22) |
| # define RADEON_ALPHA_TEST_ENABLE (1 << 23) |
| # define RADEON_ANTI_ALIAS_NONE (0 << 24) |
| # define RADEON_ANTI_ALIAS_LINE (1 << 24) |
| # define RADEON_ANTI_ALIAS_POLY (2 << 24) |
| # define RADEON_ANTI_ALIAS_LINE_POLY (3 << 24) |
| # define RADEON_BUMP_MAP_ENABLE (1 << 26) |
| # define RADEON_BUMPED_MAP_T0 (0 << 27) |
| # define RADEON_BUMPED_MAP_T1 (1 << 27) |
| # define RADEON_BUMPED_MAP_T2 (2 << 27) |
| # define RADEON_TEX_3D_ENABLE_0 (1 << 29) |
| # define RADEON_TEX_3D_ENABLE_1 (1 << 30) |
| # define RADEON_MC_ENABLE (1 << 31) |
| #define RADEON_PP_FOG_COLOR 0x1c18 |
| # define RADEON_FOG_COLOR_MASK 0x00ffffff |
| # define RADEON_FOG_VERTEX (0 << 24) |
| # define RADEON_FOG_TABLE (1 << 24) |
| # define RADEON_FOG_USE_DEPTH (0 << 25) |
| # define RADEON_FOG_USE_DIFFUSE_ALPHA (2 << 25) |
| # define RADEON_FOG_USE_SPEC_ALPHA (3 << 25) |
| #define RADEON_PP_LUM_MATRIX 0x1d00 |
| #define RADEON_PP_MISC 0x1c14 |
| # define RADEON_REF_ALPHA_MASK 0x000000ff |
| # define RADEON_ALPHA_TEST_FAIL (0 << 8) |
| # define RADEON_ALPHA_TEST_LESS (1 << 8) |
| # define RADEON_ALPHA_TEST_LEQUAL (2 << 8) |
| # define RADEON_ALPHA_TEST_EQUAL (3 << 8) |
| # define RADEON_ALPHA_TEST_GEQUAL (4 << 8) |
| # define RADEON_ALPHA_TEST_GREATER (5 << 8) |
| # define RADEON_ALPHA_TEST_NEQUAL (6 << 8) |
| # define RADEON_ALPHA_TEST_PASS (7 << 8) |
| # define RADEON_ALPHA_TEST_OP_MASK (7 << 8) |
| # define RADEON_CHROMA_FUNC_FAIL (0 << 16) |
| # define RADEON_CHROMA_FUNC_PASS (1 << 16) |
| # define RADEON_CHROMA_FUNC_NEQUAL (2 << 16) |
| # define RADEON_CHROMA_FUNC_EQUAL (3 << 16) |
| # define RADEON_CHROMA_KEY_NEAREST (0 << 18) |
| # define RADEON_CHROMA_KEY_ZERO (1 << 18) |
| # define RADEON_SHADOW_ID_AUTO_INC (1 << 20) |
| # define RADEON_SHADOW_FUNC_EQUAL (0 << 21) |
| # define RADEON_SHADOW_FUNC_NEQUAL (1 << 21) |
| # define RADEON_SHADOW_PASS_1 (0 << 22) |
| # define RADEON_SHADOW_PASS_2 (1 << 22) |
| # define RADEON_RIGHT_HAND_CUBE_D3D (0 << 24) |
| # define RADEON_RIGHT_HAND_CUBE_OGL (1 << 24) |
| #define RADEON_PP_ROT_MATRIX_0 0x1d58 |
| #define RADEON_PP_ROT_MATRIX_1 0x1d5c |
| #define RADEON_PP_TXFILTER_0 0x1c54 |
| #define RADEON_PP_TXFILTER_1 0x1c6c |
| #define RADEON_PP_TXFILTER_2 0x1c84 |
| # define RADEON_MAG_FILTER_NEAREST (0 << 0) |
| # define RADEON_MAG_FILTER_LINEAR (1 << 0) |
| # define RADEON_MAG_FILTER_MASK (1 << 0) |
| # define RADEON_MIN_FILTER_NEAREST (0 << 1) |
| # define RADEON_MIN_FILTER_LINEAR (1 << 1) |
| # define RADEON_MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1) |
| # define RADEON_MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1) |
| # define RADEON_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1) |
| # define RADEON_MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1) |
| # define RADEON_MIN_FILTER_ANISO_NEAREST (8 << 1) |
| # define RADEON_MIN_FILTER_ANISO_LINEAR (9 << 1) |
| # define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1) |
| # define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1) |
| # define RADEON_MIN_FILTER_MASK (15 << 1) |
| # define RADEON_MAX_ANISO_1_TO_1 (0 << 5) |
| # define RADEON_MAX_ANISO_2_TO_1 (1 << 5) |
| # define RADEON_MAX_ANISO_4_TO_1 (2 << 5) |
| # define RADEON_MAX_ANISO_8_TO_1 (3 << 5) |
| # define RADEON_MAX_ANISO_16_TO_1 (4 << 5) |
| # define RADEON_MAX_ANISO_MASK (7 << 5) |
| # define RADEON_LOD_BIAS_MASK (0xff << 8) |
| # define RADEON_LOD_BIAS_SHIFT 8 |
| # define RADEON_MAX_MIP_LEVEL_MASK (0x0f << 16) |
| # define RADEON_MAX_MIP_LEVEL_SHIFT 16 |
| # define RADEON_YUV_TO_RGB (1 << 20) |
| # define RADEON_YUV_TEMPERATURE_COOL (0 << 21) |
| # define RADEON_YUV_TEMPERATURE_HOT (1 << 21) |
| # define RADEON_YUV_TEMPERATURE_MASK (1 << 21) |
| # define RADEON_WRAPEN_S (1 << 22) |
| # define RADEON_CLAMP_S_WRAP (0 << 23) |
| # define RADEON_CLAMP_S_MIRROR (1 << 23) |
| # define RADEON_CLAMP_S_CLAMP_LAST (2 << 23) |
| # define RADEON_CLAMP_S_MIRROR_CLAMP_LAST (3 << 23) |
| # define RADEON_CLAMP_S_CLAMP_BORDER (4 << 23) |
| # define RADEON_CLAMP_S_MIRROR_CLAMP_BORDER (5 << 23) |
| # define RADEON_CLAMP_S_CLAMP_GL (6 << 23) |
| # define RADEON_CLAMP_S_MIRROR_CLAMP_GL (7 << 23) |
| # define RADEON_CLAMP_S_MASK (7 << 23) |
| # define RADEON_WRAPEN_T (1 << 26) |
| # define RADEON_CLAMP_T_WRAP (0 << 27) |
| # define RADEON_CLAMP_T_MIRROR (1 << 27) |
| # define RADEON_CLAMP_T_CLAMP_LAST (2 << 27) |
| # define RADEON_CLAMP_T_MIRROR_CLAMP_LAST (3 << 27) |
| # define RADEON_CLAMP_T_CLAMP_BORDER (4 << 27) |
| # define RADEON_CLAMP_T_MIRROR_CLAMP_BORDER (5 << 27) |
| # define RADEON_CLAMP_T_CLAMP_GL (6 << 27) |
| # define RADEON_CLAMP_T_MIRROR_CLAMP_GL (7 << 27) |
| # define RADEON_CLAMP_T_MASK (7 << 27) |
| # define RADEON_BORDER_MODE_OGL (0 << 31) |
| # define RADEON_BORDER_MODE_D3D (1 << 31) |
| #define RADEON_PP_TXFORMAT_0 0x1c58 |
| #define RADEON_PP_TXFORMAT_1 0x1c70 |
| #define RADEON_PP_TXFORMAT_2 0x1c88 |
| # define RADEON_TXFORMAT_I8 (0 << 0) |
| # define RADEON_TXFORMAT_AI88 (1 << 0) |
| # define RADEON_TXFORMAT_RGB332 (2 << 0) |
| # define RADEON_TXFORMAT_ARGB1555 (3 << 0) |
| # define RADEON_TXFORMAT_RGB565 (4 << 0) |
| # define RADEON_TXFORMAT_ARGB4444 (5 << 0) |
| # define RADEON_TXFORMAT_ARGB8888 (6 << 0) |
| # define RADEON_TXFORMAT_RGBA8888 (7 << 0) |
| # define RADEON_TXFORMAT_Y8 (8 << 0) |
| # define RADEON_TXFORMAT_VYUY422 (10 << 0) |
| # define RADEON_TXFORMAT_YVYU422 (11 << 0) |
| # define RADEON_TXFORMAT_DXT1 (12 << 0) |
| # define RADEON_TXFORMAT_DXT23 (14 << 0) |
| # define RADEON_TXFORMAT_DXT45 (15 << 0) |
| # define RADEON_TXFORMAT_FORMAT_MASK (31 << 0) |
| # define RADEON_TXFORMAT_FORMAT_SHIFT 0 |
| # define RADEON_TXFORMAT_APPLE_YUV_MODE (1 << 5) |
| # define RADEON_TXFORMAT_ALPHA_IN_MAP (1 << 6) |
| # define RADEON_TXFORMAT_NON_POWER2 (1 << 7) |
| # define RADEON_TXFORMAT_WIDTH_MASK (15 << 8) |
| # define RADEON_TXFORMAT_WIDTH_SHIFT 8 |
| # define RADEON_TXFORMAT_HEIGHT_MASK (15 << 12) |
| # define RADEON_TXFORMAT_HEIGHT_SHIFT 12 |
| # define RADEON_TXFORMAT_F5_WIDTH_MASK (15 << 16) |
| # define RADEON_TXFORMAT_F5_WIDTH_SHIFT 16 |
| # define RADEON_TXFORMAT_F5_HEIGHT_MASK (15 << 20) |
| # define RADEON_TXFORMAT_F5_HEIGHT_SHIFT 20 |
| # define RADEON_TXFORMAT_ST_ROUTE_STQ0 (0 << 24) |
| # define RADEON_TXFORMAT_ST_ROUTE_MASK (3 << 24) |
| # define RADEON_TXFORMAT_ST_ROUTE_STQ1 (1 << 24) |
| # define RADEON_TXFORMAT_ST_ROUTE_STQ2 (2 << 24) |
| # define RADEON_TXFORMAT_ENDIAN_NO_SWAP (0 << 26) |
| # define RADEON_TXFORMAT_ENDIAN_16BPP_SWAP (1 << 26) |
| # define RADEON_TXFORMAT_ENDIAN_32BPP_SWAP (2 << 26) |
| # define RADEON_TXFORMAT_ENDIAN_HALFDW_SWAP (3 << 26) |
| # define RADEON_TXFORMAT_ALPHA_MASK_ENABLE (1 << 28) |
| # define RADEON_TXFORMAT_CHROMA_KEY_ENABLE (1 << 29) |
| # define RADEON_TXFORMAT_CUBIC_MAP_ENABLE (1 << 30) |
| # define RADEON_TXFORMAT_PERSPECTIVE_ENABLE (1 << 31) |
| #define RADEON_PP_CUBIC_FACES_0 0x1d24 |
| #define RADEON_PP_CUBIC_FACES_1 0x1d28 |
| #define RADEON_PP_CUBIC_FACES_2 0x1d2c |
| # define RADEON_FACE_WIDTH_1_SHIFT 0 |
| # define RADEON_FACE_HEIGHT_1_SHIFT 4 |
| # define RADEON_FACE_WIDTH_1_MASK (0xf << 0) |
| # define RADEON_FACE_HEIGHT_1_MASK (0xf << 4) |
| # define RADEON_FACE_WIDTH_2_SHIFT 8 |
| # define RADEON_FACE_HEIGHT_2_SHIFT 12 |
| # define RADEON_FACE_WIDTH_2_MASK (0xf << 8) |
| # define RADEON_FACE_HEIGHT_2_MASK (0xf << 12) |
| # define RADEON_FACE_WIDTH_3_SHIFT 16 |
| # define RADEON_FACE_HEIGHT_3_SHIFT 20 |
| # define RADEON_FACE_WIDTH_3_MASK (0xf << 16) |
| # define RADEON_FACE_HEIGHT_3_MASK (0xf << 20) |
| # define RADEON_FACE_WIDTH_4_SHIFT 24 |
| # define RADEON_FACE_HEIGHT_4_SHIFT 28 |
| # define RADEON_FACE_WIDTH_4_MASK (0xf << 24) |
| # define RADEON_FACE_HEIGHT_4_MASK (0xf << 28) |
| #define RADEON_PP_TXOFFSET_0 0x1c5c |
| #define RADEON_PP_TXOFFSET_1 0x1c74 |
| #define RADEON_PP_TXOFFSET_2 0x1c8c |
| # define RADEON_TXO_ENDIAN_NO_SWAP (0 << 0) |
| # define RADEON_TXO_ENDIAN_BYTE_SWAP (1 << 0) |
| # define RADEON_TXO_ENDIAN_WORD_SWAP (2 << 0) |
| # define RADEON_TXO_ENDIAN_HALFDW_SWAP (3 << 0) |
| # define RADEON_TXO_MACRO_LINEAR (0 << 2) |
| # define RADEON_TXO_MACRO_TILE (1 << 2) |
| # define RADEON_TXO_MICRO_LINEAR (0 << 3) |
| # define RADEON_TXO_MICRO_TILE_X2 (1 << 3) |
| # define RADEON_TXO_MICRO_TILE_OPT (2 << 3) |
| # define RADEON_TXO_OFFSET_MASK 0xffffffe0 |
| # define RADEON_TXO_OFFSET_SHIFT 5 |
| #define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */ |
| #define RADEON_PP_CUBIC_OFFSET_T0_1 0x1dd4 |
| #define RADEON_PP_CUBIC_OFFSET_T0_2 0x1dd8 |
| #define RADEON_PP_CUBIC_OFFSET_T0_3 0x1ddc |
| #define RADEON_PP_CUBIC_OFFSET_T0_4 0x1de0 |
| #define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00 |
| #define RADEON_PP_CUBIC_OFFSET_T1_1 0x1e04 |
| #define RADEON_PP_CUBIC_OFFSET_T1_2 0x1e08 |
| #define RADEON_PP_CUBIC_OFFSET_T1_3 0x1e0c |
| #define RADEON_PP_CUBIC_OFFSET_T1_4 0x1e10 |
| #define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14 |
| #define RADEON_PP_CUBIC_OFFSET_T2_1 0x1e18 |
| #define RADEON_PP_CUBIC_OFFSET_T2_2 0x1e1c |
| #define RADEON_PP_CUBIC_OFFSET_T2_3 0x1e20 |
| #define RADEON_PP_CUBIC_OFFSET_T2_4 0x1e24 |
| #define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */ |
| #define RADEON_PP_TEX_SIZE_1 0x1d0c |
| #define RADEON_PP_TEX_SIZE_2 0x1d14 |
| # define RADEON_TEX_USIZE_MASK (0x7ff << 0) |
| # define RADEON_TEX_USIZE_SHIFT 0 |
| # define RADEON_TEX_VSIZE_MASK (0x7ff << 16) |
| # define RADEON_TEX_VSIZE_SHIFT 16 |
| # define RADEON_SIGNED_RGB_MASK (1 << 30) |
| # define RADEON_SIGNED_RGB_SHIFT 30 |
| # define RADEON_SIGNED_ALPHA_MASK (1 << 31) |
| # define RADEON_SIGNED_ALPHA_SHIFT 31 |
| #define RADEON_PP_TEX_PITCH_0 0x1d08 /* NPOT */ |
| #define RADEON_PP_TEX_PITCH_1 0x1d10 /* NPOT */ |
| #define RADEON_PP_TEX_PITCH_2 0x1d18 /* NPOT */ |
| /* note: bits 13-5: 32 byte aligned stride of texture map */ |
| #define RADEON_PP_TXCBLEND_0 0x1c60 |
| #define RADEON_PP_TXCBLEND_1 0x1c78 |
| #define RADEON_PP_TXCBLEND_2 0x1c90 |
| # define RADEON_COLOR_ARG_A_SHIFT 0 |
| # define RADEON_COLOR_ARG_A_MASK (0x1f << 0) |
| # define RADEON_COLOR_ARG_A_ZERO (0 << 0) |
| # define RADEON_COLOR_ARG_A_CURRENT_COLOR (2 << 0) |
| # define RADEON_COLOR_ARG_A_CURRENT_ALPHA (3 << 0) |
| # define RADEON_COLOR_ARG_A_DIFFUSE_COLOR (4 << 0) |
| # define RADEON_COLOR_ARG_A_DIFFUSE_ALPHA (5 << 0) |
| # define RADEON_COLOR_ARG_A_SPECULAR_COLOR (6 << 0) |
| # define RADEON_COLOR_ARG_A_SPECULAR_ALPHA (7 << 0) |
| # define RADEON_COLOR_ARG_A_TFACTOR_COLOR (8 << 0) |
| # define RADEON_COLOR_ARG_A_TFACTOR_ALPHA (9 << 0) |
| # define RADEON_COLOR_ARG_A_T0_COLOR (10 << 0) |
| # define RADEON_COLOR_ARG_A_T0_ALPHA (11 << 0) |
| # define RADEON_COLOR_ARG_A_T1_COLOR (12 << 0) |
| # define RADEON_COLOR_ARG_A_T1_ALPHA (13 << 0) |
| # define RADEON_COLOR_ARG_A_T2_COLOR (14 << 0) |
| # define RADEON_COLOR_ARG_A_T2_ALPHA (15 << 0) |
| # define RADEON_COLOR_ARG_A_T3_COLOR (16 << 0) |
| # define RADEON_COLOR_ARG_A_T3_ALPHA (17 << 0) |
| # define RADEON_COLOR_ARG_B_SHIFT 5 |
| # define RADEON_COLOR_ARG_B_MASK (0x1f << 5) |
| # define RADEON_COLOR_ARG_B_ZERO (0 << 5) |
| # define RADEON_COLOR_ARG_B_CURRENT_COLOR (2 << 5) |
| # define RADEON_COLOR_ARG_B_CURRENT_ALPHA (3 << 5) |
| # define RADEON_COLOR_ARG_B_DIFFUSE_COLOR (4 << 5) |
| # define RADEON_COLOR_ARG_B_DIFFUSE_ALPHA (5 << 5) |
| # define RADEON_COLOR_ARG_B_SPECULAR_COLOR (6 << 5) |
| # define RADEON_COLOR_ARG_B_SPECULAR_ALPHA (7 << 5) |
| # define RADEON_COLOR_ARG_B_TFACTOR_COLOR (8 << 5) |
| # define RADEON_COLOR_ARG_B_TFACTOR_ALPHA (9 << 5) |
| # define RADEON_COLOR_ARG_B_T0_COLOR (10 << 5) |
| # define RADEON_COLOR_ARG_B_T0_ALPHA (11 << 5) |
| # define RADEON_COLOR_ARG_B_T1_COLOR (12 << 5) |
| # define RADEON_COLOR_ARG_B_T1_ALPHA (13 << 5) |
| # define RADEON_COLOR_ARG_B_T2_COLOR (14 << 5) |
| # define RADEON_COLOR_ARG_B_T2_ALPHA (15 << 5) |
| # define RADEON_COLOR_ARG_B_T3_COLOR (16 << 5) |
| # define RADEON_COLOR_ARG_B_T3_ALPHA (17 << 5) |
| # define RADEON_COLOR_ARG_C_SHIFT 10 |
| # define RADEON_COLOR_ARG_C_MASK (0x1f << 10) |
| # define RADEON_COLOR_ARG_C_ZERO (0 << 10) |
| # define RADEON_COLOR_ARG_C_CURRENT_COLOR (2 << 10) |
| # define RADEON_COLOR_ARG_C_CURRENT_ALPHA (3 << 10) |
| # define RADEON_COLOR_ARG_C_DIFFUSE_COLOR (4 << 10) |
| # define RADEON_COLOR_ARG_C_DIFFUSE_ALPHA (5 << 10) |
| # define RADEON_COLOR_ARG_C_SPECULAR_COLOR (6 << 10) |
| # define RADEON_COLOR_ARG_C_SPECULAR_ALPHA (7 << 10) |
| # define RADEON_COLOR_ARG_C_TFACTOR_COLOR (8 << 10) |
| # define RADEON_COLOR_ARG_C_TFACTOR_ALPHA (9 << 10) |
| # define RADEON_COLOR_ARG_C_T0_COLOR (10 << 10) |
| # define RADEON_COLOR_ARG_C_T0_ALPHA (11 << 10) |
| # define RADEON_COLOR_ARG_C_T1_COLOR (12 << 10) |
| # define RADEON_COLOR_ARG_C_T1_ALPHA (13 << 10) |
| # define RADEON_COLOR_ARG_C_T2_COLOR (14 << 10) |
| # define RADEON_COLOR_ARG_C_T2_ALPHA (15 << 10) |
| # define RADEON_COLOR_ARG_C_T3_COLOR (16 << 10) |
| # define RADEON_COLOR_ARG_C_T3_ALPHA (17 << 10) |
| # define RADEON_COMP_ARG_A (1 << 15) |
| # define RADEON_COMP_ARG_A_SHIFT 15 |
| # define RADEON_COMP_ARG_B (1 << 16) |
| # define RADEON_COMP_ARG_B_SHIFT 16 |
| # define RADEON_COMP_ARG_C (1 << 17) |
| # define RADEON_COMP_ARG_C_SHIFT 17 |
| # define RADEON_BLEND_CTL_MASK (7 << 18) |
| # define RADEON_BLEND_CTL_ADD (0 << 18) |
| # define RADEON_BLEND_CTL_SUBTRACT (1 << 18) |
| # define RADEON_BLEND_CTL_ADDSIGNED (2 << 18) |
| # define RADEON_BLEND_CTL_BLEND (3 << 18) |
| # define RADEON_BLEND_CTL_DOT3 (4 << 18) |
| # define RADEON_SCALE_SHIFT 21 |
| # define RADEON_SCALE_MASK (3 << 21) |
| # define RADEON_SCALE_1X (0 << 21) |
| # define RADEON_SCALE_2X (1 << 21) |
| # define RADEON_SCALE_4X (2 << 21) |
| # define RADEON_CLAMP_TX (1 << 23) |
| # define RADEON_T0_EQ_TCUR (1 << 24) |
| # define RADEON_T1_EQ_TCUR (1 << 25) |
| # define RADEON_T2_EQ_TCUR (1 << 26) |
| # define RADEON_T3_EQ_TCUR (1 << 27) |
| # define RADEON_COLOR_ARG_MASK 0x1f |
| # define RADEON_COMP_ARG_SHIFT 15 |
| #define RADEON_PP_TXABLEND_0 0x1c64 |
| #define RADEON_PP_TXABLEND_1 0x1c7c |
| #define RADEON_PP_TXABLEND_2 0x1c94 |
| # define RADEON_ALPHA_ARG_A_SHIFT 0 |
| # define RADEON_ALPHA_ARG_A_MASK (0xf << 0) |
| # define RADEON_ALPHA_ARG_A_ZERO (0 << 0) |
| # define RADEON_ALPHA_ARG_A_CURRENT_ALPHA (1 << 0) |
| # define RADEON_ALPHA_ARG_A_DIFFUSE_ALPHA (2 << 0) |
| # define RADEON_ALPHA_ARG_A_SPECULAR_ALPHA (3 << 0) |
| # define RADEON_ALPHA_ARG_A_TFACTOR_ALPHA (4 << 0) |
| # define RADEON_ALPHA_ARG_A_T0_ALPHA (5 << 0) |
| # define RADEON_ALPHA_ARG_A_T1_ALPHA (6 << 0) |
| # define RADEON_ALPHA_ARG_A_T2_ALPHA (7 << 0) |
| # define RADEON_ALPHA_ARG_A_T3_ALPHA (8 << 0) |
| # define RADEON_ALPHA_ARG_B_SHIFT 4 |
| # define RADEON_ALPHA_ARG_B_MASK (0xf << 4) |
| # define RADEON_ALPHA_ARG_B_ZERO (0 << 4) |
| # define RADEON_ALPHA_ARG_B_CURRENT_ALPHA (1 << 4) |
| # define RADEON_ALPHA_ARG_B_DIFFUSE_ALPHA (2 << 4) |
| # define RADEON_ALPHA_ARG_B_SPECULAR_ALPHA (3 << 4) |
| # define RADEON_ALPHA_ARG_B_TFACTOR_ALPHA (4 << 4) |
| # define RADEON_ALPHA_ARG_B_T0_ALPHA (5 << 4) |
| # define RADEON_ALPHA_ARG_B_T1_ALPHA (6 << 4) |
| # define RADEON_ALPHA_ARG_B_T2_ALPHA (7 << 4) |
| # define RADEON_ALPHA_ARG_B_T3_ALPHA (8 << 4) |
| # define RADEON_ALPHA_ARG_C_SHIFT 8 |
| # define RADEON_ALPHA_ARG_C_MASK (0xf << 8) |
| # define RADEON_ALPHA_ARG_C_ZERO (0 << 8) |
| # define RADEON_ALPHA_ARG_C_CURRENT_ALPHA (1 << 8) |
| # define RADEON_ALPHA_ARG_C_DIFFUSE_ALPHA (2 << 8) |
| # define RADEON_ALPHA_ARG_C_SPECULAR_ALPHA (3 << 8) |
| # define RADEON_ALPHA_ARG_C_TFACTOR_ALPHA (4 << 8) |
| # define RADEON_ALPHA_ARG_C_T0_ALPHA (5 << 8) |
| # define RADEON_ALPHA_ARG_C_T1_ALPHA (6 << 8) |
| # define RADEON_ALPHA_ARG_C_T2_ALPHA (7 << 8) |
| # define RADEON_ALPHA_ARG_C_T3_ALPHA (8 << 8) |
| # define RADEON_DOT_ALPHA_DONT_REPLICATE (1 << 9) |
| # define RADEON_ALPHA_ARG_MASK 0xf |
| #define RADEON_PP_TFACTOR_0 0x1c68 |
| #define RADEON_PP_TFACTOR_1 0x1c80 |
| #define RADEON_PP_TFACTOR_2 0x1c98 |
| #define RADEON_RB3D_BLENDCNTL 0x1c20 |
| # define RADEON_COMB_FCN_MASK (3 << 12) |
| # define RADEON_COMB_FCN_ADD_CLAMP (0 << 12) |
| # define RADEON_COMB_FCN_ADD_NOCLAMP (1 << 12) |
| # define RADEON_COMB_FCN_SUB_CLAMP (2 << 12) |
| # define RADEON_COMB_FCN_SUB_NOCLAMP (3 << 12) |
| # define RADEON_SRC_BLEND_GL_ZERO (32 << 16) |
| # define RADEON_SRC_BLEND_GL_ONE (33 << 16) |
| # define RADEON_SRC_BLEND_GL_SRC_COLOR (34 << 16) |
| # define RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 16) |
| # define RADEON_SRC_BLEND_GL_DST_COLOR (36 << 16) |
| # define RADEON_SRC_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 16) |
| # define RADEON_SRC_BLEND_GL_SRC_ALPHA (38 << 16) |
| # define RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 16) |
| # define RADEON_SRC_BLEND_GL_DST_ALPHA (40 << 16) |
| # define RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 16) |
| # define RADEON_SRC_BLEND_GL_SRC_ALPHA_SATURATE (42 << 16) |
| # define RADEON_SRC_BLEND_MASK (63 << 16) |
| # define RADEON_DST_BLEND_GL_ZERO (32 << 24) |
| # define RADEON_DST_BLEND_GL_ONE (33 << 24) |
| # define RADEON_DST_BLEND_GL_SRC_COLOR (34 << 24) |
| # define RADEON_DST_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 24) |
| # define RADEON_DST_BLEND_GL_DST_COLOR (36 << 24) |
| # define RADEON_DST_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 24) |
| # define RADEON_DST_BLEND_GL_SRC_ALPHA (38 << 24) |
| # define RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 24) |
| # define RADEON_DST_BLEND_GL_DST_ALPHA (40 << 24) |
| # define RADEON_DST_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 24) |
| # define RADEON_DST_BLEND_MASK (63 << 24) |
| #define RADEON_RB3D_CNTL 0x1c3c |
| # define RADEON_ALPHA_BLEND_ENABLE (1 << 0) |
| # define RADEON_PLANE_MASK_ENABLE (1 << 1) |
| # define RADEON_DITHER_ENABLE (1 << 2) |
| # define RADEON_ROUND_ENABLE (1 << 3) |
| # define RADEON_SCALE_DITHER_ENABLE (1 << 4) |
| # define RADEON_DITHER_INIT (1 << 5) |
| # define RADEON_ROP_ENABLE (1 << 6) |
| # define RADEON_STENCIL_ENABLE (1 << 7) |
| # define RADEON_Z_ENABLE (1 << 8) |
| # define RADEON_DEPTH_XZ_OFFEST_ENABLE (1 << 9) |
| # define RADEON_COLOR_FORMAT_ARGB1555 (3 << 10) |
| # define RADEON_COLOR_FORMAT_RGB565 (4 << 10) |
| # define RADEON_COLOR_FORMAT_ARGB8888 (6 << 10) |
| # define RADEON_COLOR_FORMAT_RGB332 (7 << 10) |
| # define RADEON_COLOR_FORMAT_Y8 (8 << 10) |
| # define RADEON_COLOR_FORMAT_RGB8 (9 << 10) |
| # define RADEON_COLOR_FORMAT_YUV422_VYUY (11 << 10) |
| # define RADEON_COLOR_FORMAT_YUV422_YVYU (12 << 10) |
| # define RADEON_COLOR_FORMAT_aYUV444 (14 << 10) |
| # define RADEON_COLOR_FORMAT_ARGB4444 (15 << 10) |
| # define RADEON_CLRCMP_FLIP_ENABLE (1 << 14) |
| #define RADEON_RB3D_COLOROFFSET 0x1c40 |
| # define RADEON_COLOROFFSET_MASK 0xfffffff0 |
| #define RADEON_RB3D_COLORPITCH 0x1c48 |
| # define RADEON_COLORPITCH_MASK 0x000001ff8 |
| # define RADEON_COLOR_TILE_ENABLE (1 << 16) |
| # define RADEON_COLOR_MICROTILE_ENABLE (1 << 17) |
| # define RADEON_COLOR_ENDIAN_NO_SWAP (0 << 18) |
| # define RADEON_COLOR_ENDIAN_WORD_SWAP (1 << 18) |
| # define RADEON_COLOR_ENDIAN_DWORD_SWAP (2 << 18) |
| #define RADEON_RB3D_DEPTHOFFSET 0x1c24 |
| #define RADEON_RB3D_DEPTHPITCH 0x1c28 |
| # define RADEON_DEPTHPITCH_MASK 0x00001ff8 |
| # define RADEON_DEPTH_ENDIAN_NO_SWAP (0 << 18) |
| # define RADEON_DEPTH_ENDIAN_WORD_SWAP (1 << 18) |
| # define RADEON_DEPTH_ENDIAN_DWORD_SWAP (2 << 18) |
| #define RADEON_RB3D_PLANEMASK 0x1d84 |
| #define RADEON_RB3D_ROPCNTL 0x1d80 |
| # define RADEON_ROP_MASK (15 << 8) |
| # define RADEON_ROP_CLEAR (0 << 8) |
| # define RADEON_ROP_NOR (1 << 8) |
| # define RADEON_ROP_AND_INVERTED (2 << 8) |
| # define RADEON_ROP_COPY_INVERTED (3 << 8) |
| # define RADEON_ROP_AND_REVERSE (4 << 8) |
| # define RADEON_ROP_INVERT (5 << 8) |
| # define RADEON_ROP_XOR (6 << 8) |
| # define RADEON_ROP_NAND (7 << 8) |
| # define RADEON_ROP_AND (8 << 8) |
| # define RADEON_ROP_EQUIV (9 << 8) |
| # define RADEON_ROP_NOOP (10 << 8) |
| # define RADEON_ROP_OR_INVERTED (11 << 8) |
| # define RADEON_ROP_COPY (12 << 8) |
| # define RADEON_ROP_OR_REVERSE (13 << 8) |
| # define RADEON_ROP_OR (14 << 8) |
| # define RADEON_ROP_SET (15 << 8) |
| #define RADEON_RB3D_STENCILREFMASK 0x1d7c |
| # define RADEON_STENCIL_REF_SHIFT 0 |
| # define RADEON_STENCIL_REF_MASK (0xff << 0) |
| # define RADEON_STENCIL_MASK_SHIFT 16 |
| # define RADEON_STENCIL_VALUE_MASK (0xff << 16) |
| # define RADEON_STENCIL_WRITEMASK_SHIFT 24 |
| # define RADEON_STENCIL_WRITE_MASK (0xff << 24) |
| #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c |
| # define RADEON_DEPTH_FORMAT_MASK (0xf << 0) |
| # define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0) |
| # define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0) |
| # define RADEON_DEPTH_FORMAT_24BIT_FLOAT_Z (3 << 0) |
| # define RADEON_DEPTH_FORMAT_32BIT_INT_Z (4 << 0) |
| # define RADEON_DEPTH_FORMAT_32BIT_FLOAT_Z (5 << 0) |
| # define RADEON_DEPTH_FORMAT_16BIT_FLOAT_W (7 << 0) |
| # define RADEON_DEPTH_FORMAT_24BIT_FLOAT_W (9 << 0) |
| # define RADEON_DEPTH_FORMAT_32BIT_FLOAT_W (11 << 0) |
| # define RADEON_Z_TEST_NEVER (0 << 4) |
| # define RADEON_Z_TEST_LESS (1 << 4) |
| # define RADEON_Z_TEST_LEQUAL (2 << 4) |
| # define RADEON_Z_TEST_EQUAL (3 << 4) |
| # define RADEON_Z_TEST_GEQUAL (4 << 4) |
| # define RADEON_Z_TEST_GREATER (5 << 4) |
| # define RADEON_Z_TEST_NEQUAL (6 << 4) |
| # define RADEON_Z_TEST_ALWAYS (7 << 4) |
| # define RADEON_Z_TEST_MASK (7 << 4) |
| # define RADEON_STENCIL_TEST_NEVER (0 << 12) |
| # define RADEON_STENCIL_TEST_LESS (1 << 12) |
| # define RADEON_STENCIL_TEST_LEQUAL (2 << 12) |
| # define RADEON_STENCIL_TEST_EQUAL (3 << 12) |
| # define RADEON_STENCIL_TEST_GEQUAL (4 << 12) |
| # define RADEON_STENCIL_TEST_GREATER (5 << 12) |
| # define RADEON_STENCIL_TEST_NEQUAL (6 << 12) |
| # define RADEON_STENCIL_TEST_ALWAYS (7 << 12) |
| # define RADEON_STENCIL_TEST_MASK (0x7 << 12) |
| # define RADEON_STENCIL_FAIL_KEEP (0 << 16) |
| # define RADEON_STENCIL_FAIL_ZERO (1 << 16) |
| # define RADEON_STENCIL_FAIL_REPLACE (2 << 16) |
| # define RADEON_STENCIL_FAIL_INC (3 << 16) |
| # define RADEON_STENCIL_FAIL_DEC (4 << 16) |
| # define RADEON_STENCIL_FAIL_INVERT (5 << 16) |
| # define RADEON_STENCIL_FAIL_MASK (0x7 << 16) |
| # define RADEON_STENCIL_ZPASS_KEEP (0 << 20) |
| # define RADEON_STENCIL_ZPASS_ZERO (1 << 20) |
| # define RADEON_STENCIL_ZPASS_REPLACE (2 << 20) |
| # define RADEON_STENCIL_ZPASS_INC (3 << 20) |
| # define RADEON_STENCIL_ZPASS_DEC (4 << 20) |
| # define RADEON_STENCIL_ZPASS_INVERT (5 << 20) |
| # define RADEON_STENCIL_ZPASS_MASK (0x7 << 20) |
| # define RADEON_STENCIL_ZFAIL_KEEP (0 << 24) |
| # define RADEON_STENCIL_ZFAIL_ZERO (1 << 24) |
| # define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24) |
| # define RADEON_STENCIL_ZFAIL_INC (3 << 24) |
| # define RADEON_STENCIL_ZFAIL_DEC (4 << 24) |
| # define RADEON_STENCIL_ZFAIL_INVERT (5 << 24) |
| # define RADEON_STENCIL_ZFAIL_MASK (0x7 << 24) |
| # define RADEON_Z_COMPRESSION_ENABLE (1 << 28) |
| # define RADEON_FORCE_Z_DIRTY (1 << 29) |
| # define RADEON_Z_WRITE_ENABLE (1 << 30) |
| #define RADEON_RE_LINE_PATTERN 0x1cd0 |
| # define RADEON_LINE_PATTERN_MASK 0x0000ffff |
| # define RADEON_LINE_REPEAT_COUNT_SHIFT 16 |
| # define RADEON_LINE_PATTERN_START_SHIFT 24 |
| # define RADEON_LINE_PATTERN_LITTLE_BIT_ORDER (0 << 28) |
| # define RADEON_LINE_PATTERN_BIG_BIT_ORDER (1 << 28) |
| # define RADEON_LINE_PATTERN_AUTO_RESET (1 << 29) |
| #define RADEON_RE_LINE_STATE 0x1cd4 |
| # define RADEON_LINE_CURRENT_PTR_SHIFT 0 |
| # define RADEON_LINE_CURRENT_COUNT_SHIFT 8 |
| #define RADEON_RE_MISC 0x26c4 |
| # define RADEON_STIPPLE_COORD_MASK 0x1f |
| # define RADEON_STIPPLE_X_OFFSET_SHIFT 0 |
| # define RADEON_STIPPLE_X_OFFSET_MASK (0x1f << 0) |
| # define RADEON_STIPPLE_Y_OFFSET_SHIFT 8 |
| # define RADEON_STIPPLE_Y_OFFSET_MASK (0x1f << 8) |
| # define RADEON_STIPPLE_LITTLE_BIT_ORDER (0 << 16) |
| # define RADEON_STIPPLE_BIG_BIT_ORDER (1 << 16) |
| #define RADEON_RE_SOLID_COLOR 0x1c1c |
| #define RADEON_RE_TOP_LEFT 0x26c0 |
| # define RADEON_RE_LEFT_SHIFT 0 |
| # define RADEON_RE_TOP_SHIFT 16 |
| #define RADEON_RE_WIDTH_HEIGHT 0x1c44 |
| # define RADEON_RE_WIDTH_SHIFT 0 |
| # define RADEON_RE_HEIGHT_SHIFT 16 |
| #define RADEON_SE_CNTL 0x1c4c |
| # define RADEON_FFACE_CULL_CW (0 << 0) |
| # define RADEON_FFACE_CULL_CCW (1 << 0) |
| # define RADEON_FFACE_CULL_DIR_MASK (1 << 0) |
| # define RADEON_BFACE_CULL (0 << 1) |
| # define RADEON_BFACE_SOLID (3 << 1) |
| # define RADEON_FFACE_CULL (0 << 3) |
| # define RADEON_FFACE_SOLID (3 << 3) |
| # define RADEON_FFACE_CULL_MASK (3 << 3) |
| # define RADEON_BADVTX_CULL_DISABLE (1 << 5) |
| # define RADEON_FLAT_SHADE_VTX_0 (0 << 6) |
| # define RADEON_FLAT_SHADE_VTX_1 (1 << 6) |
| # define RADEON_FLAT_SHADE_VTX_2 (2 << 6) |
| # define RADEON_FLAT_SHADE_VTX_LAST (3 << 6) |
| # define RADEON_DIFFUSE_SHADE_SOLID (0 << 8) |
| # define RADEON_DIFFUSE_SHADE_FLAT (1 << 8) |
| # define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8) |
| # define RADEON_DIFFUSE_SHADE_MASK (3 << 8) |
| # define RADEON_ALPHA_SHADE_SOLID (0 << 10) |
| # define RADEON_ALPHA_SHADE_FLAT (1 << 10) |
| # define RADEON_ALPHA_SHADE_GOURAUD (2 << 10) |
| # define RADEON_ALPHA_SHADE_MASK (3 << 10) |
| # define RADEON_SPECULAR_SHADE_SOLID (0 << 12) |
| # define RADEON_SPECULAR_SHADE_FLAT (1 << 12) |
| # define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12) |
| # define RADEON_SPECULAR_SHADE_MASK (3 << 12) |
| # define RADEON_FOG_SHADE_SOLID (0 << 14) |
| # define RADEON_FOG_SHADE_FLAT (1 << 14) |
| # define RADEON_FOG_SHADE_GOURAUD (2 << 14) |
| # define RADEON_FOG_SHADE_MASK (3 << 14) |
| # define RADEON_ZBIAS_ENABLE_POINT (1 << 16) |
| # define RADEON_ZBIAS_ENABLE_LINE (1 << 17) |
| # define RADEON_ZBIAS_ENABLE_TRI (1 << 18) |
| # define RADEON_WIDELINE_ENABLE (1 << 20) |
| # define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24) |
| # define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25) |
| # define RADEON_VTX_PIX_CENTER_D3D (0 << 27) |
| # define RADEON_VTX_PIX_CENTER_OGL (1 << 27) |
| # define RADEON_ROUND_MODE_TRUNC (0 << 28) |
| # define RADEON_ROUND_MODE_ROUND (1 << 28) |
| # define RADEON_ROUND_MODE_ROUND_EVEN (2 << 28) |
| # define RADEON_ROUND_MODE_ROUND_ODD (3 << 28) |
| # define RADEON_ROUND_PREC_16TH_PIX (0 << 30) |
| # define RADEON_ROUND_PREC_8TH_PIX (1 << 30) |
| # define RADEON_ROUND_PREC_4TH_PIX (2 << 30) |
| # define RADEON_ROUND_PREC_HALF_PIX (3 << 30) |
| #define R200_RE_CNTL 0x1c50 |
| # define R200_STIPPLE_ENABLE 0x1 |
| # define R200_SCISSOR_ENABLE 0x2 |
| # define R200_PATTERN_ENABLE 0x4 |
| # define R200_PERSPECTIVE_ENABLE 0x8 |
| # define R200_POINT_SMOOTH 0x20 |
| # define R200_VTX_STQ0_D3D 0x00010000 |
| # define R200_VTX_STQ1_D3D 0x00040000 |
| # define R200_VTX_STQ2_D3D 0x00100000 |
| # define R200_VTX_STQ3_D3D 0x00400000 |
| # define R200_VTX_STQ4_D3D 0x01000000 |
| # define R200_VTX_STQ5_D3D 0x04000000 |
| #define RADEON_SE_CNTL_STATUS 0x2140 |
| # define RADEON_VC_NO_SWAP (0 << 0) |
| # define RADEON_VC_16BIT_SWAP (1 << 0) |
| # define RADEON_VC_32BIT_SWAP (2 << 0) |
| # define RADEON_VC_HALF_DWORD_SWAP (3 << 0) |
| # define RADEON_TCL_BYPASS (1 << 8) |
| #define RADEON_SE_COORD_FMT 0x1c50 |
| # define RADEON_VTX_XY_PRE_MULT_1_OVER_W0 (1 << 0) |
| # define RADEON_VTX_Z_PRE_MULT_1_OVER_W0 (1 << 1) |
| # define RADEON_VTX_ST0_NONPARAMETRIC (1 << 8) |
| # define RADEON_VTX_ST1_NONPARAMETRIC (1 << 9) |
| # define RADEON_VTX_ST2_NONPARAMETRIC (1 << 10) |
| # define RADEON_VTX_ST3_NONPARAMETRIC (1 << 11) |
| # define RADEON_VTX_W0_NORMALIZE (1 << 12) |
| # define RADEON_VTX_W0_IS_NOT_1_OVER_W0 (1 << 16) |
| # define RADEON_VTX_ST0_PRE_MULT_1_OVER_W0 (1 << 17) |
| # define RADEON_VTX_ST1_PRE_MULT_1_OVER_W0 (1 << 19) |
| # define RADEON_VTX_ST2_PRE_MULT_1_OVER_W0 (1 << 21) |
| # define RADEON_VTX_ST3_PRE_MULT_1_OVER_W0 (1 << 23) |
| # define RADEON_TEX1_W_ROUTING_USE_W0 (0 << 26) |
| # define RADEON_TEX1_W_ROUTING_USE_Q1 (1 << 26) |
| #define RADEON_SE_LINE_WIDTH 0x1db8 |
| #define RADEON_SE_TCL_LIGHT_MODEL_CTL 0x226c |
| # define RADEON_LIGHTING_ENABLE (1 << 0) |
| # define RADEON_LIGHT_IN_MODELSPACE (1 << 1) |
| # define RADEON_LOCAL_VIEWER (1 << 2) |
| # define RADEON_NORMALIZE_NORMALS (1 << 3) |
| # define RADEON_RESCALE_NORMALS (1 << 4) |
| # define RADEON_SPECULAR_LIGHTS (1 << 5) |
| # define RADEON_DIFFUSE_SPECULAR_COMBINE (1 << 6) |
| # define RADEON_LIGHT_ALPHA (1 << 7) |
| # define RADEON_LOCAL_LIGHT_VEC_GL (1 << 8) |
| # define RADEON_LIGHT_NO_NORMAL_AMBIENT_ONLY (1 << 9) |
| # define RADEON_LM_SOURCE_STATE_PREMULT 0 |
| # define RADEON_LM_SOURCE_STATE_MULT 1 |
| # define RADEON_LM_SOURCE_VERTEX_DIFFUSE 2 |
| # define RADEON_LM_SOURCE_VERTEX_SPECULAR 3 |
| # define RADEON_EMISSIVE_SOURCE_SHIFT 16 |
| # define RADEON_AMBIENT_SOURCE_SHIFT 18 |
| # define RADEON_DIFFUSE_SOURCE_SHIFT 20 |
| # define RADEON_SPECULAR_SOURCE_SHIFT 22 |
| #define RADEON_SE_TCL_MATERIAL_AMBIENT_RED 0x2220 |
| #define RADEON_SE_TCL_MATERIAL_AMBIENT_GREEN 0x2224 |
| #define RADEON_SE_TCL_MATERIAL_AMBIENT_BLUE 0x2228 |
| #define RADEON_SE_TCL_MATERIAL_AMBIENT_ALPHA 0x222c |
| #define RADEON_SE_TCL_MATERIAL_DIFFUSE_RED 0x2230 |
| #define RADEON_SE_TCL_MATERIAL_DIFFUSE_GREEN 0x2234 |
| #define RADEON_SE_TCL_MATERIAL_DIFFUSE_BLUE 0x2238 |
| #define RADEON_SE_TCL_MATERIAL_DIFFUSE_ALPHA 0x223c |
| #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210 |
| #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_GREEN 0x2214 |
| #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_BLUE 0x2218 |
| #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_ALPHA 0x221c |
| #define RADEON_SE_TCL_MATERIAL_SPECULAR_RED 0x2240 |
| #define RADEON_SE_TCL_MATERIAL_SPECULAR_GREEN 0x2244 |
| #define RADEON_SE_TCL_MATERIAL_SPECULAR_BLUE 0x2248 |
| #define RADEON_SE_TCL_MATERIAL_SPECULAR_ALPHA 0x224c |
| #define RADEON_SE_TCL_MATRIX_SELECT_0 0x225c |
| # define RADEON_MODELVIEW_0_SHIFT 0 |
| # define RADEON_MODELVIEW_1_SHIFT 4 |
| # define RADEON_MODELVIEW_2_SHIFT 8 |
| # define RADEON_MODELVIEW_3_SHIFT 12 |
| # define RADEON_IT_MODELVIEW_0_SHIFT 16 |
| # define RADEON_IT_MODELVIEW_1_SHIFT 20 |
| # define RADEON_IT_MODELVIEW_2_SHIFT 24 |
| # define RADEON_IT_MODELVIEW_3_SHIFT 28 |
| #define RADEON_SE_TCL_MATRIX_SELECT_1 0x2260 |
| # define RADEON_MODELPROJECT_0_SHIFT 0 |
| # define RADEON_MODELPROJECT_1_SHIFT 4 |
| # define RADEON_MODELPROJECT_2_SHIFT 8 |
| # define RADEON_MODELPROJECT_3_SHIFT 12 |
| # define RADEON_TEXMAT_0_SHIFT 16 |
| # define RADEON_TEXMAT_1_SHIFT 20 |
| # define RADEON_TEXMAT_2_SHIFT 24 |
| # define RADEON_TEXMAT_3_SHIFT 28 |
| #define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254 |
| # define RADEON_TCL_VTX_W0 (1 << 0) |
| # define RADEON_TCL_VTX_FP_DIFFUSE (1 << 1) |
| # define RADEON_TCL_VTX_FP_ALPHA (1 << 2) |
| # define RADEON_TCL_VTX_PK_DIFFUSE (1 << 3) |
| # define RADEON_TCL_VTX_FP_SPEC (1 << 4) |
| # define RADEON_TCL_VTX_FP_FOG (1 << 5) |
| # define RADEON_TCL_VTX_PK_SPEC (1 << 6) |
| # define RADEON_TCL_VTX_ST0 (1 << 7) |
| # define RADEON_TCL_VTX_ST1 (1 << 8) |
| # define RADEON_TCL_VTX_Q1 (1 << 9) |
| # define RADEON_TCL_VTX_ST2 (1 << 10) |
| # define RADEON_TCL_VTX_Q2 (1 << 11) |
| # define RADEON_TCL_VTX_ST3 (1 << 12) |
| # define RADEON_TCL_VTX_Q3 (1 << 13) |
| # define RADEON_TCL_VTX_Q0 (1 << 14) |
| # define RADEON_TCL_VTX_WEIGHT_COUNT_SHIFT 15 |
| # define RADEON_TCL_VTX_NORM0 (1 << 18) |
| # define RADEON_TCL_VTX_XY1 (1 << 27) |
| # define RADEON_TCL_VTX_Z1 (1 << 28) |
| # define RADEON_TCL_VTX_W1 (1 << 29) |
| # define RADEON_TCL_VTX_NORM1 (1 << 30) |
| # define RADEON_TCL_VTX_Z0 (1 << 31) |
| #define RADEON_SE_TCL_OUTPUT_VTX_SEL 0x2258 |
| # define RADEON_TCL_COMPUTE_XYZW (1 << 0) |
| # define RADEON_TCL_COMPUTE_DIFFUSE (1 << 1) |
| # define RADEON_TCL_COMPUTE_SPECULAR (1 << 2) |
| # define RADEON_TCL_FORCE_NAN_IF_COLOR_NAN (1 << 3) |
| # define RADEON_TCL_FORCE_INORDER_PROC (1 << 4) |
| # define RADEON_TCL_TEX_INPUT_TEX_0 0 |
| # define RADEON_TCL_TEX_INPUT_TEX_1 1 |
| # define RADEON_TCL_TEX_INPUT_TEX_2 2 |
| # define RADEON_TCL_TEX_INPUT_TEX_3 3 |
| # define RADEON_TCL_TEX_COMPUTED_TEX_0 8 |
| # define RADEON_TCL_TEX_COMPUTED_TEX_1 9 |
| # define RADEON_TCL_TEX_COMPUTED_TEX_2 10 |
| # define RADEON_TCL_TEX_COMPUTED_TEX_3 11 |
| # define RADEON_TCL_TEX_0_OUTPUT_SHIFT 16 |
| # define RADEON_TCL_TEX_1_OUTPUT_SHIFT 20 |
| # define RADEON_TCL_TEX_2_OUTPUT_SHIFT 24 |
| # define RADEON_TCL_TEX_3_OUTPUT_SHIFT 28 |
| #define RADEON_SE_TCL_PER_LIGHT_CTL_0 0x2270 |
| # define RADEON_LIGHT_0_ENABLE (1 << 0) |
| # define RADEON_LIGHT_0_ENABLE_AMBIENT (1 << 1) |
| # define RADEON_LIGHT_0_ENABLE_SPECULAR (1 << 2) |
| # define RADEON_LIGHT_0_IS_LOCAL (1 << 3) |
| # define RADEON_LIGHT_0_IS_SPOT (1 << 4) |
| # define RADEON_LIGHT_0_DUAL_CONE (1 << 5) |
| # define RADEON_LIGHT_0_ENABLE_RANGE_ATTEN (1 << 6) |
| # define RADEON_LIGHT_0_CONSTANT_RANGE_ATTEN (1 << 7) |
| # define RADEON_LIGHT_0_SHIFT 0 |
| # define RADEON_LIGHT_1_ENABLE (1 << 16) |
| # define RADEON_LIGHT_1_ENABLE_AMBIENT (1 << 17) |
| # define RADEON_LIGHT_1_ENABLE_SPECULAR (1 << 18) |
| # define RADEON_LIGHT_1_IS_LOCAL (1 << 19) |
| # define RADEON_LIGHT_1_IS_SPOT (1 << 20) |
| # define RADEON_LIGHT_1_DUAL_CONE (1 << 21) |
| # define RADEON_LIGHT_1_ENABLE_RANGE_ATTEN (1 << 22) |
| # define RADEON_LIGHT_1_CONSTANT_RANGE_ATTEN (1 << 23) |
| # define RADEON_LIGHT_1_SHIFT 16 |
| #define RADEON_SE_TCL_PER_LIGHT_CTL_1 0x2274 |
| # define RADEON_LIGHT_2_SHIFT 0 |
| # define RADEON_LIGHT_3_SHIFT 16 |
| #define RADEON_SE_TCL_PER_LIGHT_CTL_2 0x2278 |
| # define RADEON_LIGHT_4_SHIFT 0 |
| # define RADEON_LIGHT_5_SHIFT 16 |
| #define RADEON_SE_TCL_PER_LIGHT_CTL_3 0x227c |
| # define RADEON_LIGHT_6_SHIFT 0 |
| # define RADEON_LIGHT_7_SHIFT 16 |
| #define RADEON_SE_TCL_SHININESS 0x2250 |
| #define RADEON_SE_TCL_TEXTURE_PROC_CTL 0x2268 |
| # define RADEON_TEXGEN_TEXMAT_0_ENABLE (1 << 0) |
| # define RADEON_TEXGEN_TEXMAT_1_ENABLE (1 << 1) |
| # define RADEON_TEXGEN_TEXMAT_2_ENABLE (1 << 2) |
| # define RADEON_TEXGEN_TEXMAT_3_ENABLE (1 << 3) |
| # define RADEON_TEXMAT_0_ENABLE (1 << 4) |
| # define RADEON_TEXMAT_1_ENABLE (1 << 5) |
| # define RADEON_TEXMAT_2_ENABLE (1 << 6) |
| # define RADEON_TEXMAT_3_ENABLE (1 << 7) |
| # define RADEON_TEXGEN_INPUT_MASK 0xf |
| # define RADEON_TEXGEN_INPUT_TEXCOORD_0 0 |
| # define RADEON_TEXGEN_INPUT_TEXCOORD_1 1 |
| # define RADEON_TEXGEN_INPUT_TEXCOORD_2 2 |
| # define RADEON_TEXGEN_INPUT_TEXCOORD_3 3 |
| # define RADEON_TEXGEN_INPUT_OBJ 4 |
| # define RADEON_TEXGEN_INPUT_EYE 5 |
| # define RADEON_TEXGEN_INPUT_EYE_NORMAL 6 |
| # define RADEON_TEXGEN_INPUT_EYE_REFLECT 7 |
| # define RADEON_TEXGEN_INPUT_EYE_NORMALIZED 8 |
| # define RADEON_TEXGEN_0_INPUT_SHIFT 16 |
| # define RADEON_TEXGEN_1_INPUT_SHIFT 20 |
| # define RADEON_TEXGEN_2_INPUT_SHIFT 24 |
| # define RADEON_TEXGEN_3_INPUT_SHIFT 28 |
| #define RADEON_SE_TCL_UCP_VERT_BLEND_CTL 0x2264 |
| # define RADEON_UCP_IN_CLIP_SPACE (1 << 0) |
| # define RADEON_UCP_IN_MODEL_SPACE (1 << 1) |
| # define RADEON_UCP_ENABLE_0 (1 << 2) |
| # define RADEON_UCP_ENABLE_1 (1 << 3) |
| # define RADEON_UCP_ENABLE_2 (1 << 4) |
| # define RADEON_UCP_ENABLE_3 (1 << 5) |
| # define RADEON_UCP_ENABLE_4 (1 << 6) |
| # define RADEON_UCP_ENABLE_5 (1 << 7) |
| # define RADEON_TCL_FOG_MASK (3 << 8) |
| # define RADEON_TCL_FOG_DISABLE (0 << 8) |
| # define RADEON_TCL_FOG_EXP (1 << 8) |
| # define RADEON_TCL_FOG_EXP2 (2 << 8) |
| # define RADEON_TCL_FOG_LINEAR (3 << 8) |
| # define RADEON_RNG_BASED_FOG (1 << 10) |
| # define RADEON_LIGHT_TWOSIDE (1 << 11) |
| # define RADEON_BLEND_OP_COUNT_MASK (7 << 12) |
| # define RADEON_BLEND_OP_COUNT_SHIFT 12 |
| # define RADEON_POSITION_BLEND_OP_ENABLE (1 << 16) |
| # define RADEON_NORMAL_BLEND_OP_ENABLE (1 << 17) |
| # define RADEON_VERTEX_BLEND_SRC_0_PRIMARY (1 << 18) |
| # define RADEON_VERTEX_BLEND_SRC_0_SECONDARY (1 << 18) |
| # define RADEON_VERTEX_BLEND_SRC_1_PRIMARY (1 << 19) |
| # define RADEON_VERTEX_BLEND_SRC_1_SECONDARY (1 << 19) |
| # define RADEON_VERTEX_BLEND_SRC_2_PRIMARY (1 << 20) |
| # define RADEON_VERTEX_BLEND_SRC_2_SECONDARY (1 << 20) |
| # define RADEON_VERTEX_BLEND_SRC_3_PRIMARY (1 << 21) |
| # define RADEON_VERTEX_BLEND_SRC_3_SECONDARY (1 << 21) |
| # define RADEON_VERTEX_BLEND_WGT_MINUS_ONE (1 << 22) |
| # define RADEON_CULL_FRONT_IS_CW (0 << 28) |
| # define RADEON_CULL_FRONT_IS_CCW (1 << 28) |
| # define RADEON_CULL_FRONT (1 << 29) |
| # define RADEON_CULL_BACK (1 << 30) |
| # define RADEON_FORCE_W_TO_ONE (1 << 31) |
| #define RADEON_SE_VPORT_XSCALE 0x1d98 |
| #define RADEON_SE_VPORT_XOFFSET 0x1d9c |
| #define RADEON_SE_VPORT_YSCALE 0x1da0 |
| #define RADEON_SE_VPORT_YOFFSET 0x1da4 |
| #define RADEON_SE_VPORT_ZSCALE 0x1da8 |
| #define RADEON_SE_VPORT_ZOFFSET 0x1dac |
| #define RADEON_SE_ZBIAS_FACTOR 0x1db0 |
| #define RADEON_SE_ZBIAS_CONSTANT 0x1db4 |
| #define RADEON_SE_VTX_FMT 0x2080 |
| # define RADEON_SE_VTX_FMT_XY 0x00000000 |
| # define RADEON_SE_VTX_FMT_W0 0x00000001 |
| # define RADEON_SE_VTX_FMT_FPCOLOR 0x00000002 |
| # define RADEON_SE_VTX_FMT_FPALPHA 0x00000004 |
| # define RADEON_SE_VTX_FMT_PKCOLOR 0x00000008 |
| # define RADEON_SE_VTX_FMT_FPSPEC 0x00000010 |
| # define RADEON_SE_VTX_FMT_FPFOG 0x00000020 |
| # define RADEON_SE_VTX_FMT_PKSPEC 0x00000040 |
| # define RADEON_SE_VTX_FMT_ST0 0x00000080 |
| # define RADEON_SE_VTX_FMT_ST1 0x00000100 |
| # define RADEON_SE_VTX_FMT_Q1 0x00000200 |
| # define RADEON_SE_VTX_FMT_ST2 0x00000400 |
| # define RADEON_SE_VTX_FMT_Q2 0x00000800 |
| # define RADEON_SE_VTX_FMT_ST3 0x00001000 |
| # define RADEON_SE_VTX_FMT_Q3 0x00002000 |
| # define RADEON_SE_VTX_FMT_Q0 0x00004000 |
| # define RADEON_SE_VTX_FMT_BLND_WEIGHT_CNT_MASK 0x00038000 |
| # define RADEON_SE_VTX_FMT_N0 0x00040000 |
| # define RADEON_SE_VTX_FMT_XY1 0x08000000 |
| # define RADEON_SE_VTX_FMT_Z1 0x10000000 |
| # define RADEON_SE_VTX_FMT_W1 0x20000000 |
| # define RADEON_SE_VTX_FMT_N1 0x40000000 |
| # define RADEON_SE_VTX_FMT_Z 0x80000000 |
| #define RADEON_SE_VF_CNTL 0x2084 |
| # define RADEON_VF_PRIM_TYPE_POINT_LIST 1 |
| # define RADEON_VF_PRIM_TYPE_LINE_LIST 2 |
| # define RADEON_VF_PRIM_TYPE_LINE_STRIP 3 |
| # define RADEON_VF_PRIM_TYPE_TRIANGLE_LIST 4 |
| # define RADEON_VF_PRIM_TYPE_TRIANGLE_FAN 5 |
| # define RADEON_VF_PRIM_TYPE_TRIANGLE_STRIP 6 |
| # define RADEON_VF_PRIM_TYPE_TRIANGLE_FLAG 7 |
| # define RADEON_VF_PRIM_TYPE_RECTANGLE_LIST 8 |
| # define RADEON_VF_PRIM_TYPE_POINT_LIST_3 9 |
| # define RADEON_VF_PRIM_TYPE_LINE_LIST_3 10 |
| # define RADEON_VF_PRIM_TYPE_SPIRIT_LIST 11 |
| # define RADEON_VF_PRIM_TYPE_LINE_LOOP 12 |
| # define RADEON_VF_PRIM_TYPE_QUAD_LIST 13 |
| # define RADEON_VF_PRIM_TYPE_QUAD_STRIP 14 |
| # define RADEON_VF_PRIM_TYPE_POLYGON 15 |
| # define RADEON_VF_PRIM_WALK_STATE (0<<4) |
| # define RADEON_VF_PRIM_WALK_INDEX (1<<4) |
| # define RADEON_VF_PRIM_WALK_LIST (2<<4) |
| # define RADEON_VF_PRIM_WALK_DATA (3<<4) |
| # define RADEON_VF_COLOR_ORDER_RGBA (1<<6) |
| # define RADEON_VF_RADEON_MODE (1<<8) |
| # define RADEON_VF_TCL_OUTPUT_CTL_ENA (1<<9) |
| # define RADEON_VF_PROG_STREAM_ENA (1<<10) |
| # define RADEON_VF_INDEX_SIZE_SHIFT 11 |
| # define RADEON_VF_NUM_VERTICES_SHIFT 16 |
| #define RADEON_SE_PORT_DATA0 0x2000 |
| #define R200_SE_VAP_CNTL 0x2080 |
| # define R200_VAP_TCL_ENABLE 0x00000001 |
| # define R200_VAP_SINGLE_BUF_STATE_ENABLE 0x00000010 |
| # define R200_VAP_FORCE_W_TO_ONE 0x00010000 |
| # define R200_VAP_D3D_TEX_DEFAULT 0x00020000 |
| # define R200_VAP_VF_MAX_VTX_NUM__SHIFT 18 |
| # define R200_VAP_VF_MAX_VTX_NUM (9 << 18) |
| # define R200_VAP_DX_CLIP_SPACE_DEF 0x00400000 |
| #define R200_VF_MAX_VTX_INDX 0x210c |
| #define R200_VF_MIN_VTX_INDX 0x2110 |
| #define R200_SE_VTE_CNTL 0x20b0 |
| # define R200_VPORT_X_SCALE_ENA 0x00000001 |
| # define R200_VPORT_X_OFFSET_ENA 0x00000002 |
| # define R200_VPORT_Y_SCALE_ENA 0x00000004 |
| # define R200_VPORT_Y_OFFSET_ENA 0x00000008 |
| # define R200_VPORT_Z_SCALE_ENA 0x00000010 |
| # define R200_VPORT_Z_OFFSET_ENA 0x00000020 |
| # define R200_VTX_XY_FMT 0x00000100 |
| # define R200_VTX_Z_FMT 0x00000200 |
| # define R200_VTX_W0_FMT 0x00000400 |
| # define R200_VTX_W0_NORMALIZE 0x00000800 |
| # define R200_VTX_ST_DENORMALIZED 0x00001000 |
| #define R200_SE_VAP_CNTL_STATUS 0x2140 |
| # define R200_VC_NO_SWAP (0 << 0) |
| # define R200_VC_16BIT_SWAP (1 << 0) |
| # define R200_VC_32BIT_SWAP (2 << 0) |
| #define R200_PP_TXFILTER_0 0x2c00 |
| #define R200_PP_TXFILTER_1 0x2c20 |
| #define R200_PP_TXFILTER_2 0x2c40 |
| #define R200_PP_TXFILTER_3 0x2c60 |
| #define R200_PP_TXFILTER_4 0x2c80 |
| #define R200_PP_TXFILTER_5 0x2ca0 |
| # define R200_MAG_FILTER_NEAREST (0 << 0) |
| # define R200_MAG_FILTER_LINEAR (1 << 0) |
| # define R200_MAG_FILTER_MASK (1 << 0) |
| # define R200_MIN_FILTER_NEAREST (0 << 1) |
| # define R200_MIN_FILTER_LINEAR (1 << 1) |
| # define R200_MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1) |
| # define R200_MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1) |
| # define R200_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1) |
| # define R200_MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1) |
| # define R200_MIN_FILTER_ANISO_NEAREST (8 << 1) |
| # define R200_MIN_FILTER_ANISO_LINEAR (9 << 1) |
| # define R200_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1) |
| # define R200_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1) |
| # define R200_MIN_FILTER_MASK (15 << 1) |
| # define R200_MAX_ANISO_1_TO_1 (0 << 5) |
| # define R200_MAX_ANISO_2_TO_1 (1 << 5) |
| # define R200_MAX_ANISO_4_TO_1 (2 << 5) |
| # define R200_MAX_ANISO_8_TO_1 (3 << 5) |
| # define R200_MAX_ANISO_16_TO_1 (4 << 5) |
| # define R200_MAX_ANISO_MASK (7 << 5) |
| # define R200_MAX_MIP_LEVEL_MASK (0x0f << 16) |
| # define R200_MAX_MIP_LEVEL_SHIFT 16 |
| # define R200_YUV_TO_RGB (1 << 20) |
| # define R200_YUV_TEMPERATURE_COOL (0 << 21) |
| # define R200_YUV_TEMPERATURE_HOT (1 << 21) |
| # define R200_YUV_TEMPERATURE_MASK (1 << 21) |
| # define R200_WRAPEN_S (1 << 22) |
| # define R200_CLAMP_S_WRAP (0 << 23) |
| # define R200_CLAMP_S_MIRROR (1 << 23) |
| # define R200_CLAMP_S_CLAMP_LAST (2 << 23) |
| # define R200_CLAMP_S_MIRROR_CLAMP_LAST (3 << 23) |
| # define R200_CLAMP_S_CLAMP_BORDER (4 << 23) |
| # define R200_CLAMP_S_MIRROR_CLAMP_BORDER (5 << 23) |
| # define R200_CLAMP_S_CLAMP_GL (6 << 23) |
| # define R200_CLAMP_S_MIRROR_CLAMP_GL (7 << 23) |
| # define R200_CLAMP_S_MASK (7 << 23) |
| # define R200_WRAPEN_T (1 << 26) |
| # define R200_CLAMP_T_WRAP (0 << 27) |
| # define R200_CLAMP_T_MIRROR (1 << 27) |
| # define R200_CLAMP_T_CLAMP_LAST (2 << 27) |
| # define R200_CLAMP_T_MIRROR_CLAMP_LAST (3 << 27) |
| # define R200_CLAMP_T_CLAMP_BORDER (4 << 27) |
| # define R200_CLAMP_T_MIRROR_CLAMP_BORDER (5 << 27) |
| # define R200_CLAMP_T_CLAMP_GL (6 << 27) |
| # define R200_CLAMP_T_MIRROR_CLAMP_GL (7 << 27) |
| # define R200_CLAMP_T_MASK (7 << 27) |
| # define R200_KILL_LT_ZERO (1 << 30) |
| # define R200_BORDER_MODE_OGL (0 << 31) |
| # define R200_BORDER_MODE_D3D (1 << 31) |
| #define R200_PP_TXFORMAT_0 0x2c04 |
| #define R200_PP_TXFORMAT_1 0x2c24 |
| #define R200_PP_TXFORMAT_2 0x2c44 |
| #define R200_PP_TXFORMAT_3 0x2c64 |
| #define R200_PP_TXFORMAT_4 0x2c84 |
| #define R200_PP_TXFORMAT_5 0x2ca4 |
| # define R200_TXFORMAT_I8 (0 << 0) |
| # define R200_TXFORMAT_AI88 (1 << 0) |
| # define R200_TXFORMAT_RGB332 (2 << 0) |
| # define R200_TXFORMAT_ARGB1555 (3 << 0) |
| # define R200_TXFORMAT_RGB565 (4 << 0) |
| # define R200_TXFORMAT_ARGB4444 (5 << 0) |
| # define R200_TXFORMAT_ARGB8888 (6 << 0) |
| # define R200_TXFORMAT_RGBA8888 (7 << 0) |
| # define R200_TXFORMAT_Y8 (8 << 0) |
| # define R200_TXFORMAT_AVYU4444 (9 << 0) |
| # define R200_TXFORMAT_VYUY422 (10 << 0) |
| # define R200_TXFORMAT_YVYU422 (11 << 0) |
| # define R200_TXFORMAT_DXT1 (12 << 0) |
| # define R200_TXFORMAT_DXT23 (14 << 0) |
| # define R200_TXFORMAT_DXT45 (15 << 0) |
| # define R200_TXFORMAT_ABGR8888 (22 << 0) |
| # define R200_TXFORMAT_FORMAT_MASK (31 << 0) |
| # define R200_TXFORMAT_FORMAT_SHIFT 0 |
| # define R200_TXFORMAT_ALPHA_IN_MAP (1 << 6) |
| # define R200_TXFORMAT_NON_POWER2 (1 << 7) |
| # define R200_TXFORMAT_WIDTH_MASK (15 << 8) |
| # define R200_TXFORMAT_WIDTH_SHIFT 8 |
| # define R200_TXFORMAT_HEIGHT_MASK (15 << 12) |
| # define R200_TXFORMAT_HEIGHT_SHIFT 12 |
| # define R200_TXFORMAT_F5_WIDTH_MASK (15 << 16) /* cube face 5 */ |
| # define R200_TXFORMAT_F5_WIDTH_SHIFT 16 |
| # define R200_TXFORMAT_F5_HEIGHT_MASK (15 << 20) |
| # define R200_TXFORMAT_F5_HEIGHT_SHIFT 20 |
| # define R200_TXFORMAT_ST_ROUTE_STQ0 (0 << 24) |
| # define R200_TXFORMAT_ST_ROUTE_STQ1 (1 << 24) |
| # define R200_TXFORMAT_ST_ROUTE_STQ2 (2 << 24) |
| # define R200_TXFORMAT_ST_ROUTE_STQ3 (3 << 24) |
| # define R200_TXFORMAT_ST_ROUTE_STQ4 (4 << 24) |
| # define R200_TXFORMAT_ST_ROUTE_STQ5 (5 << 24) |
| # define R200_TXFORMAT_ST_ROUTE_MASK (7 << 24) |
| # define R200_TXFORMAT_ST_ROUTE_SHIFT 24 |
| # define R200_TXFORMAT_ALPHA_MASK_ENABLE (1 << 28) |
| # define R200_TXFORMAT_CHROMA_KEY_ENABLE (1 << 29) |
| # define R200_TXFORMAT_CUBIC_MAP_ENABLE (1 << 30) |
| #define R200_PP_TXFORMAT_X_0 0x2c08 |
| #define R200_PP_TXFORMAT_X_1 0x2c28 |
| #define R200_PP_TXFORMAT_X_2 0x2c48 |
| #define R200_PP_TXFORMAT_X_3 0x2c68 |
| #define R200_PP_TXFORMAT_X_4 0x2c88 |
| #define R200_PP_TXFORMAT_X_5 0x2ca8 |
| #define R200_PP_TXSIZE_0 0x2c0c /* NPOT only */ |
| #define R200_PP_TXSIZE_1 0x2c2c /* NPOT only */ |
| #define R200_PP_TXSIZE_2 0x2c4c /* NPOT only */ |
| #define R200_PP_TXSIZE_3 0x2c6c /* NPOT only */ |
| #define R200_PP_TXSIZE_4 0x2c8c /* NPOT only */ |
| #define R200_PP_TXSIZE_5 0x2cac /* NPOT only */ |
| #define R200_PP_TXPITCH_0 0x2c10 /* NPOT only */ |
| #define R200_PP_TXPITCH_1 0x2c30 /* NPOT only */ |
| #define R200_PP_TXPITCH_2 0x2c50 /* NPOT only */ |
| #define R200_PP_TXPITCH_3 0x2c70 /* NPOT only */ |
| #define R200_PP_TXPITCH_4 0x2c90 /* NPOT only */ |
| #define R200_PP_TXPITCH_5 0x2cb0 /* NPOT only */ |
| #define R200_PP_TXOFFSET_0 0x2d00 |
| # define R200_TXO_ENDIAN_NO_SWAP (0 << 0) |
| # define R200_TXO_ENDIAN_BYTE_SWAP (1 << 0) |
| # define R200_TXO_ENDIAN_WORD_SWAP (2 << 0) |
| # define R200_TXO_ENDIAN_HALFDW_SWAP (3 << 0) |
| # define R200_TXO_MACRO_LINEAR (0 << 2) |
| # define R200_TXO_MACRO_TILE (1 << 2) |
| # define R200_TXO_MICRO_LINEAR (0 << 3) |
| # define R200_TXO_MICRO_TILE (1 << 3) |
| # define R200_TXO_OFFSET_MASK 0xffffffe0 |
| # define R200_TXO_OFFSET_SHIFT 5 |
| #define R200_PP_TXOFFSET_1 0x2d18 |
| #define R200_PP_TXOFFSET_2 0x2d30 |
| #define R200_PP_TXOFFSET_3 0x2d48 |
| #define R200_PP_TXOFFSET_4 0x2d60 |
| #define R200_PP_TXOFFSET_5 0x2d78 |
| #define R200_PP_TFACTOR_0 0x2ee0 |
| #define R200_PP_TFACTOR_1 0x2ee4 |
| #define R200_PP_TFACTOR_2 0x2ee8 |
| #define R200_PP_TFACTOR_3 0x2eec |
| #define R200_PP_TFACTOR_4 0x2ef0 |
| #define R200_PP_TFACTOR_5 0x2ef4 |
| #define R200_PP_TXCBLEND_0 0x2f00 |
| # define R200_TXC_ARG_A_ZERO (0) |
| # define R200_TXC_ARG_A_CURRENT_COLOR (2) |
| # define R200_TXC_ARG_A_CURRENT_ALPHA (3) |
| # define R200_TXC_ARG_A_DIFFUSE_COLOR (4) |
| # define R200_TXC_ARG_A_DIFFUSE_ALPHA (5) |
| # define R200_TXC_ARG_A_SPECULAR_COLOR (6) |
| # define R200_TXC_ARG_A_SPECULAR_ALPHA (7) |
| # define R200_TXC_ARG_A_TFACTOR_COLOR (8) |
| # define R200_TXC_ARG_A_TFACTOR_ALPHA (9) |
| # define R200_TXC_ARG_A_R0_COLOR (10) |
| # define R200_TXC_ARG_A_R0_ALPHA (11) |
| # define R200_TXC_ARG_A_R1_COLOR (12) |
| # define R200_TXC_ARG_A_R1_ALPHA (13) |
| # define R200_TXC_ARG_A_R2_COLOR (14) |
| # define R200_TXC_ARG_A_R2_ALPHA (15) |
| # define R200_TXC_ARG_A_R3_COLOR (16) |
| # define R200_TXC_ARG_A_R3_ALPHA (17) |
| # define R200_TXC_ARG_A_R4_COLOR (18) |
| # define R200_TXC_ARG_A_R4_ALPHA (19) |
| # define R200_TXC_ARG_A_R5_COLOR (20) |
| # define R200_TXC_ARG_A_R5_ALPHA (21) |
| # define R200_TXC_ARG_A_TFACTOR1_COLOR (26) |
| # define R200_TXC_ARG_A_TFACTOR1_ALPHA (27) |
| # define R200_TXC_ARG_A_MASK (31 << 0) |
| # define R200_TXC_ARG_A_SHIFT 0 |
| # define R200_TXC_ARG_B_ZERO (0 << 5) |
| # define R200_TXC_ARG_B_CURRENT_COLOR (2 << 5) |
| # define R200_TXC_ARG_B_CURRENT_ALPHA (3 << 5) |
| # define R200_TXC_ARG_B_DIFFUSE_COLOR (4 << 5) |
| # define R200_TXC_ARG_B_DIFFUSE_ALPHA (5 << 5) |
| # define R200_TXC_ARG_B_SPECULAR_COLOR (6 << 5) |
| # define R200_TXC_ARG_B_SPECULAR_ALPHA (7 << 5) |
| # define R200_TXC_ARG_B_TFACTOR_COLOR (8 << 5) |
| # define R200_TXC_ARG_B_TFACTOR_ALPHA (9 << 5) |
| # define R200_TXC_ARG_B_R0_COLOR (10 << 5) |
| # define R200_TXC_ARG_B_R0_ALPHA (11 << 5) |
| # define R200_TXC_ARG_B_R1_COLOR (12 << 5) |
| # define R200_TXC_ARG_B_R1_ALPHA (13 << 5) |
| # define R200_TXC_ARG_B_R2_COLOR (14 << 5) |
| # define R200_TXC_ARG_B_R2_ALPHA (15 << 5) |
| # define R200_TXC_ARG_B_R3_COLOR (16 << 5) |
| # define R200_TXC_ARG_B_R3_ALPHA (17 << 5) |
| # define R200_TXC_ARG_B_R4_COLOR (18 << 5) |
| # define R200_TXC_ARG_B_R4_ALPHA (19 << 5) |
| # define R200_TXC_ARG_B_R5_COLOR (20 << 5) |
| # define R200_TXC_ARG_B_R5_ALPHA (21 << 5) |
| # define R200_TXC_ARG_B_TFACTOR1_COLOR (26 << 5) |
| # define R200_TXC_ARG_B_TFACTOR1_ALPHA (27 << 5) |
| # define R200_TXC_ARG_B_MASK (31 << 5) |
| # define R200_TXC_ARG_B_SHIFT 5 |
| # define R200_TXC_ARG_C_ZERO (0 << 10) |
| # define R200_TXC_ARG_C_CURRENT_COLOR (2 << 10) |
| # define R200_TXC_ARG_C_CURRENT_ALPHA (3 << 10) |
| # define R200_TXC_ARG_C_DIFFUSE_COLOR (4 << 10) |
| # define R200_TXC_ARG_C_DIFFUSE_ALPHA (5 << 10) |
| # define R200_TXC_ARG_C_SPECULAR_COLOR (6 << 10) |
| # define R200_TXC_ARG_C_SPECULAR_ALPHA (7 << 10) |
| # define R200_TXC_ARG_C_TFACTOR_COLOR (8 << 10) |
| # define R200_TXC_ARG_C_TFACTOR_ALPHA (9 << 10) |
| # define R200_TXC_ARG_C_R0_COLOR (10 << 10) |
| # define R200_TXC_ARG_C_R0_ALPHA (11 << 10) |
| # define R200_TXC_ARG_C_R1_COLOR (12 << 10) |
| # define R200_TXC_ARG_C_R1_ALPHA (13 << 10) |
| # define R200_TXC_ARG_C_R2_COLOR (14 << 10) |
| # define R200_TXC_ARG_C_R2_ALPHA (15 << 10) |
| # define R200_TXC_ARG_C_R3_COLOR (16 << 10) |
| # define R200_TXC_ARG_C_R3_ALPHA (17 << 10) |
| # define R200_TXC_ARG_C_R4_COLOR (18 << 10) |
| # define R200_TXC_ARG_C_R4_ALPHA (19 << 10) |
| # define R200_TXC_ARG_C_R5_COLOR (20 << 10) |
| # define R200_TXC_ARG_C_R5_ALPHA (21 << 10) |
| # define R200_TXC_ARG_C_TFACTOR1_COLOR (26 << 10) |
| # define R200_TXC_ARG_C_TFACTOR1_ALPHA (27 << 10) |
| # define R200_TXC_ARG_C_MASK (31 << 10) |
| # define R200_TXC_ARG_C_SHIFT 10 |
| # define R200_TXC_COMP_ARG_A (1 << 16) |
| # define R200_TXC_COMP_ARG_A_SHIFT (16) |
| # define R200_TXC_BIAS_ARG_A (1 << 17) |
| # define R200_TXC_SCALE_ARG_A (1 << 18) |
| # define R200_TXC_NEG_ARG_A (1 << 19) |
| # define R200_TXC_COMP_ARG_B (1 << 20) |
| # define R200_TXC_COMP_ARG_B_SHIFT (20) |
| # define R200_TXC_BIAS_ARG_B (1 << 21) |
| # define R200_TXC_SCALE_ARG_B (1 << 22) |
| # define R200_TXC_NEG_ARG_B (1 << 23) |
| # define R200_TXC_COMP_ARG_C (1 << 24) |
| # define R200_TXC_COMP_ARG_C_SHIFT (24) |
| # define R200_TXC_BIAS_ARG_C (1 << 25) |
| # define R200_TXC_SCALE_ARG_C (1 << 26) |
| # define R200_TXC_NEG_ARG_C (1 << 27) |
| # define R200_TXC_OP_MADD (0 << 28) |
| # define R200_TXC_OP_CND0 (2 << 28) |
| # define R200_TXC_OP_LERP (3 << 28) |
| # define R200_TXC_OP_DOT3 (4 << 28) |
| # define R200_TXC_OP_DOT4 (5 << 28) |
| # define R200_TXC_OP_CONDITIONAL (6 << 28) |
| # define R200_TXC_OP_DOT2_ADD (7 << 28) |
| # define R200_TXC_OP_MASK (7 << 28) |
| #define R200_PP_TXCBLEND2_0 0x2f04 |
| # define R200_TXC_TFACTOR_SEL_SHIFT 0 |
| # define R200_TXC_TFACTOR_SEL_MASK 0x7 |
| # define R200_TXC_TFACTOR1_SEL_SHIFT 4 |
| # define R200_TXC_TFACTOR1_SEL_MASK (0x7 << 4) |
| # define R200_TXC_SCALE_SHIFT 8 |
| # define R200_TXC_SCALE_MASK (7 << 8) |
| # define R200_TXC_SCALE_1X (0 << 8) |
| # define R200_TXC_SCALE_2X (1 << 8) |
| # define R200_TXC_SCALE_4X (2 << 8) |
| # define R200_TXC_SCALE_8X (3 << 8) |
| # define R200_TXC_SCALE_INV2 (5 << 8) |
| # define R200_TXC_SCALE_INV4 (6 << 8) |
| # define R200_TXC_SCALE_INV8 (7 << 8) |
| # define R200_TXC_CLAMP_SHIFT 12 |
| # define R200_TXC_CLAMP_MASK (3 << 12) |
| # define R200_TXC_CLAMP_WRAP (0 << 12) |
| # define R200_TXC_CLAMP_0_1 (1 << 12) |
| # define R200_TXC_CLAMP_8_8 (2 << 12) |
| # define R200_TXC_OUTPUT_REG_MASK (7 << 16) |
| # define R200_TXC_OUTPUT_REG_NONE (0 << 16) |
| # define R200_TXC_OUTPUT_REG_R0 (1 << 16) |
| # define R200_TXC_OUTPUT_REG_R1 (2 << 16) |
| # define R200_TXC_OUTPUT_REG_R2 (3 << 16) |
| # define R200_TXC_OUTPUT_REG_R3 (4 << 16) |
| # define R200_TXC_OUTPUT_REG_R4 (5 << 16) |
| # define R200_TXC_OUTPUT_REG_R5 (6 << 16) |
| # define R200_TXC_OUTPUT_MASK_MASK (7 << 20) |
| # define R200_TXC_OUTPUT_MASK_RGB (0 << 20) |
| # define R200_TXC_OUTPUT_MASK_RG (1 << 20) |
| # define R200_TXC_OUTPUT_MASK_RB (2 << 20) |
| # define R200_TXC_OUTPUT_MASK_R (3 << 20) |
| # define R200_TXC_OUTPUT_MASK_GB (4 << 20) |
| # define R200_TXC_OUTPUT_MASK_G (5 << 20) |
| # define R200_TXC_OUTPUT_MASK_B (6 << 20) |
| # define R200_TXC_OUTPUT_MASK_NONE (7 << 20) |
| # define R200_TXC_REPL_NORMAL 0 |
| # define R200_TXC_REPL_RED 1 |
| # define R200_TXC_REPL_GREEN 2 |
| # define R200_TXC_REPL_BLUE 3 |
| # define R200_TXC_REPL_ARG_A_SHIFT 26 |
| # define R200_TXC_REPL_ARG_A_MASK (3 << 26) |
| # define R200_TXC_REPL_ARG_B_SHIFT 28 |
| # define R200_TXC_REPL_ARG_B_MASK (3 << 28) |
| # define R200_TXC_REPL_ARG_C_SHIFT 30 |
| # define R200_TXC_REPL_ARG_C_MASK (3 << 30) |
| #define R200_PP_TXABLEND_0 0x2f08 |
| # define R200_TXA_ARG_A_ZERO (0) |
| # define R200_TXA_ARG_A_CURRENT_ALPHA (2) /* guess */ |
| # define R200_TXA_ARG_A_CURRENT_BLUE (3) /* guess */ |
| # define R200_TXA_ARG_A_DIFFUSE_ALPHA (4) |
| # define R200_TXA_ARG_A_DIFFUSE_BLUE (5) |
| # define R200_TXA_ARG_A_SPECULAR_ALPHA (6) |
| # define R200_TXA_ARG_A_SPECULAR_BLUE (7) |
| # define R200_TXA_ARG_A_TFACTOR_ALPHA (8) |
| # define R200_TXA_ARG_A_TFACTOR_BLUE (9) |
| # define R200_TXA_ARG_A_R0_ALPHA (10) |
| # define R200_TXA_ARG_A_R0_BLUE (11) |
| # define R200_TXA_ARG_A_R1_ALPHA (12) |
| # define R200_TXA_ARG_A_R1_BLUE (13) |
| # define R200_TXA_ARG_A_R2_ALPHA (14) |
| # define R200_TXA_ARG_A_R2_BLUE (15) |
| # define R200_TXA_ARG_A_R3_ALPHA (16) |
| # define R200_TXA_ARG_A_R3_BLUE (17) |
| # define R200_TXA_ARG_A_R4_ALPHA (18) |
| # define R200_TXA_ARG_A_R4_BLUE (19) |
| # define R200_TXA_ARG_A_R5_ALPHA (20) |
| # define R200_TXA_ARG_A_R5_BLUE (21) |
| # define R200_TXA_ARG_A_TFACTOR1_ALPHA (26) |
| # define R200_TXA_ARG_A_TFACTOR1_BLUE (27) |
| # define R200_TXA_ARG_A_MASK (31 << 0) |
| # define R200_TXA_ARG_A_SHIFT 0 |
| # define R200_TXA_ARG_B_ZERO (0 << 5) |
| # define R200_TXA_ARG_B_CURRENT_ALPHA (2 << 5) /* guess */ |
| # define R200_TXA_ARG_B_CURRENT_BLUE (3 << 5) /* guess */ |
| # define R200_TXA_ARG_B_DIFFUSE_ALPHA (4 << 5) |
| # define R200_TXA_ARG_B_DIFFUSE_BLUE (5 << 5) |
| # define R200_TXA_ARG_B_SPECULAR_ALPHA (6 << 5) |
| # define R200_TXA_ARG_B_SPECULAR_BLUE (7 << 5) |
| # define R200_TXA_ARG_B_TFACTOR_ALPHA (8 << 5) |
| # define R200_TXA_ARG_B_TFACTOR_BLUE (9 << 5) |
| # define R200_TXA_ARG_B_R0_ALPHA (10 << 5) |
| # define R200_TXA_ARG_B_R0_BLUE (11 << 5) |
| # define R200_TXA_ARG_B_R1_ALPHA (12 << 5) |
| # define R200_TXA_ARG_B_R1_BLUE (13 << 5) |
| # define R200_TXA_ARG_B_R2_ALPHA (14 << 5) |
| # define R200_TXA_ARG_B_R2_BLUE (15 << 5) |
| # define R200_TXA_ARG_B_R3_ALPHA (16 << 5) |
| # define R200_TXA_ARG_B_R3_BLUE (17 << 5) |
| # define R200_TXA_ARG_B_R4_ALPHA (18 << 5) |
| # define R200_TXA_ARG_B_R4_BLUE (19 << 5) |
| # define R200_TXA_ARG_B_R5_ALPHA (20 << 5) |
| # define R200_TXA_ARG_B_R5_BLUE (21 << 5) |
| # define R200_TXA_ARG_B_TFACTOR1_ALPHA (26 << 5) |
| # define R200_TXA_ARG_B_TFACTOR1_BLUE (27 << 5) |
| # define R200_TXA_ARG_B_MASK (31 << 5) |
| # define R200_TXA_ARG_B_SHIFT 5 |
| # define R200_TXA_ARG_C_ZERO (0 << 10) |
| # define R200_TXA_ARG_C_CURRENT_ALPHA (2 << 10) /* guess */ |
| # define R200_TXA_ARG_C_CURRENT_BLUE (3 << 10) /* guess */ |
| # define R200_TXA_ARG_C_DIFFUSE_ALPHA (4 << 10) |
| # define R200_TXA_ARG_C_DIFFUSE_BLUE (5 << 10) |
| # define R200_TXA_ARG_C_SPECULAR_ALPHA (6 << 10) |
| # define R200_TXA_ARG_C_SPECULAR_BLUE (7 << 10) |
| # define R200_TXA_ARG_C_TFACTOR_ALPHA (8 << 10) |
| # define R200_TXA_ARG_C_TFACTOR_BLUE (9 << 10) |
| # define R200_TXA_ARG_C_R0_ALPHA (10 << 10) |
| # define R200_TXA_ARG_C_R0_BLUE (11 << 10) |
| # define R200_TXA_ARG_C_R1_ALPHA (12 << 10) |
| # define R200_TXA_ARG_C_R1_BLUE (13 << 10) |
| # define R200_TXA_ARG_C_R2_ALPHA (14 << 10) |
| # define R200_TXA_ARG_C_R2_BLUE (15 << 10) |
| # define R200_TXA_ARG_C_R3_ALPHA (16 << 10) |
| # define R200_TXA_ARG_C_R3_BLUE (17 << 10) |
| # define R200_TXA_ARG_C_R4_ALPHA (18 << 10) |
| # define R200_TXA_ARG_C_R4_BLUE (19 << 10) |
| # define R200_TXA_ARG_C_R5_ALPHA (20 << 10) |
| # define R200_TXA_ARG_C_R5_BLUE (21 << 10) |
| # define R200_TXA_ARG_C_TFACTOR1_ALPHA (26 << 10) |
| # define R200_TXA_ARG_C_TFACTOR1_BLUE (27 << 10) |
| # define R200_TXA_ARG_C_MASK (31 << 10) |
| # define R200_TXA_ARG_C_SHIFT 10 |
| # define R200_TXA_COMP_ARG_A (1 << 16) |
| # define R200_TXA_COMP_ARG_A_SHIFT (16) |
| # define R200_TXA_BIAS_ARG_A (1 << 17) |
| # define R200_TXA_SCALE_ARG_A (1 << 18) |
| # define R200_TXA_NEG_ARG_A (1 << 19) |
| # define R200_TXA_COMP_ARG_B (1 << 20) |
| # define R200_TXA_COMP_ARG_B_SHIFT (20) |
| # define R200_TXA_BIAS_ARG_B (1 << 21) |
| # define R200_TXA_SCALE_ARG_B (1 << 22) |
| # define R200_TXA_NEG_ARG_B (1 << 23) |
| # define R200_TXA_COMP_ARG_C (1 << 24) |
| # define R200_TXA_COMP_ARG_C_SHIFT (24) |
| # define R200_TXA_BIAS_ARG_C (1 << 25) |
| # define R200_TXA_SCALE_ARG_C (1 << 26) |
| # define R200_TXA_NEG_ARG_C (1 << 27) |
| # define R200_TXA_OP_MADD (0 << 28) |
| # define R200_TXA_OP_CND0 (2 << 28) |
| # define R200_TXA_OP_LERP (3 << 28) |
| # define R200_TXA_OP_CONDITIONAL (6 << 28) |
| # define R200_TXA_OP_MASK (7 << 28) |
| #define R200_PP_TXABLEND2_0 0x2f0c |
| # define R200_TXA_TFACTOR_SEL_SHIFT 0 |
| # define R200_TXA_TFACTOR_SEL_MASK 0x7 |
| # define R200_TXA_TFACTOR1_SEL_SHIFT 4 |
| # define R200_TXA_TFACTOR1_SEL_MASK (0x7 << 4) |
| # define R200_TXA_SCALE_SHIFT 8 |
| # define R200_TXA_SCALE_MASK (7 << 8) |
| # define R200_TXA_SCALE_1X (0 << 8) |
| # define R200_TXA_SCALE_2X (1 << 8) |
| # define R200_TXA_SCALE_4X (2 << 8) |
| # define R200_TXA_SCALE_8X (3 << 8) |
| # define R200_TXA_SCALE_INV2 (5 << 8) |
| # define R200_TXA_SCALE_INV4 (6 << 8) |
| # define R200_TXA_SCALE_INV8 (7 << 8) |
| # define R200_TXA_CLAMP_SHIFT 12 |
| # define R200_TXA_CLAMP_MASK (3 << 12) |
| # define R200_TXA_CLAMP_WRAP (0 << 12) |
| # define R200_TXA_CLAMP_0_1 (1 << 12) |
| # define R200_TXA_CLAMP_8_8 (2 << 12) |
| # define R200_TXA_OUTPUT_REG_MASK (7 << 16) |
| # define R200_TXA_OUTPUT_REG_NONE (0 << 16) |
| # define R200_TXA_OUTPUT_REG_R0 (1 << 16) |
| # define R200_TXA_OUTPUT_REG_R1 (2 << 16) |
| # define R200_TXA_OUTPUT_REG_R2 (3 << 16) |
| # define R200_TXA_OUTPUT_REG_R3 (4 << 16) |
| # define R200_TXA_OUTPUT_REG_R4 (5 << 16) |
| # define R200_TXA_OUTPUT_REG_R5 (6 << 16) |
| # define R200_TXA_DOT_ALPHA (1 << 20) |
| # define R200_TXA_REPL_NORMAL 0 |
| # define R200_TXA_REPL_RED 1 |
| # define R200_TXA_REPL_GREEN 2 |
| # define R200_TXA_REPL_ARG_A_SHIFT 26 |
| # define R200_TXA_REPL_ARG_A_MASK (3 << 26) |
| # define R200_TXA_REPL_ARG_B_SHIFT 28 |
| # define R200_TXA_REPL_ARG_B_MASK (3 << 28) |
| # define R200_TXA_REPL_ARG_C_SHIFT 30 |
| # define R200_TXA_REPL_ARG_C_MASK (3 << 30) |
| #define R200_SE_VTX_FMT_0 0x2088 |
| # define R200_VTX_XY 0 /* always have xy */ |
| # define R200_VTX_Z0 (1<<0) |
| # define R200_VTX_W0 (1<<1) |
| # define R200_VTX_WEIGHT_COUNT_SHIFT (2) |
| # define R200_VTX_PV_MATRIX_SEL (1<<5) |
| # define R200_VTX_N0 (1<<6) |
| # define R200_VTX_POINT_SIZE (1<<7) |
| # define R200_VTX_DISCRETE_FOG (1<<8) |
| # define R200_VTX_SHININESS_0 (1<<9) |
| # define R200_VTX_SHININESS_1 (1<<10) |
| # define R200_VTX_COLOR_NOT_PRESENT 0 |
| # define R200_VTX_PK_RGBA 1 |
| # define R200_VTX_FP_RGB 2 |
| # define R200_VTX_FP_RGBA 3 |
| # define R200_VTX_COLOR_MASK 3 |
| # define R200_VTX_COLOR_0_SHIFT 11 |
| # define R200_VTX_COLOR_1_SHIFT 13 |
| # define R200_VTX_COLOR_2_SHIFT 15 |
| # define R200_VTX_COLOR_3_SHIFT 17 |
| # define R200_VTX_COLOR_4_SHIFT 19 |
| # define R200_VTX_COLOR_5_SHIFT 21 |
| # define R200_VTX_COLOR_6_SHIFT 23 |
| # define R200_VTX_COLOR_7_SHIFT 25 |
| # define R200_VTX_XY1 (1<<28) |
| # define R200_VTX_Z1 (1<<29) |
| # define R200_VTX_W1 (1<<30) |
| # define R200_VTX_N1 (1<<31) |
| #define R200_SE_VTX_FMT_1 0x208c |
| # define R200_VTX_TEX0_COMP_CNT_SHIFT 0 |
| # define R200_VTX_TEX1_COMP_CNT_SHIFT 3 |
| # define R200_VTX_TEX2_COMP_CNT_SHIFT 6 |
| # define R200_VTX_TEX3_COMP_CNT_SHIFT 9 |
| # define R200_VTX_TEX4_COMP_CNT_SHIFT 12 |
| # define R200_VTX_TEX5_COMP_CNT_SHIFT 15 |
| #define R200_SE_TCL_OUTPUT_VTX_FMT_0 0x2090 |
| #define R200_SE_TCL_OUTPUT_VTX_FMT_1 0x2094 |
| #define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250 |
| # define R200_OUTPUT_XYZW (1<<0) |
| # define R200_OUTPUT_COLOR_0 (1<<8) |
| # define R200_OUTPUT_COLOR_1 (1<<9) |
| # define R200_OUTPUT_TEX_0 (1<<16) |
| # define R200_OUTPUT_TEX_1 (1<<17) |
| # define R200_OUTPUT_TEX_2 (1<<18) |
| # define R200_OUTPUT_TEX_3 (1<<19) |
| # define R200_OUTPUT_TEX_4 (1<<20) |
| # define R200_OUTPUT_TEX_5 (1<<21) |
| # define R200_OUTPUT_TEX_MASK (0x3f<<16) |
| # define R200_OUTPUT_DISCRETE_FOG (1<<24) |
| # define R200_OUTPUT_PT_SIZE (1<<25) |
| # define R200_FORCE_INORDER_PROC (1<<31) |
| #define R200_PP_CNTL_X 0x2cc4 |
| #define R200_PP_TXMULTI_CTL_0 0x2c1c |
| #define R200_SE_VTX_STATE_CNTL 0x2180 |
| # define R200_UPDATE_USER_COLOR_0_ENA_MASK (1<<16) |
| /* Registers for CP and Microcode Engine */ |
| #define RADEON_CP_ME_RAM_ADDR 0x07d4 |
| #define RADEON_CP_ME_RAM_RADDR 0x07d8 |
| #define RADEON_CP_ME_RAM_DATAH 0x07dc |
| #define RADEON_CP_ME_RAM_DATAL 0x07e0 |
| #define RADEON_CP_RB_BASE 0x0700 |
| #define RADEON_CP_RB_CNTL 0x0704 |
| #define RADEON_CP_RB_RPTR_ADDR 0x070c |
| #define RADEON_CP_RB_RPTR 0x0710 |
| #define RADEON_CP_RB_WPTR 0x0714 |
| #define RADEON_CP_IB_BASE 0x0738 |
| #define RADEON_CP_IB_BUFSZ 0x073c |
| #define RADEON_CP_CSQ_CNTL 0x0740 |
| # define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0) |
| # define RADEON_CSQ_PRIDIS_INDDIS (0 << 28) |
| # define RADEON_CSQ_PRIPIO_INDDIS (1 << 28) |
| # define RADEON_CSQ_PRIBM_INDDIS (2 << 28) |
| # define RADEON_CSQ_PRIPIO_INDBM (3 << 28) |
| # define RADEON_CSQ_PRIBM_INDBM (4 << 28) |
| # define RADEON_CSQ_PRIPIO_INDPIO (15 << 28) |
| #define RADEON_CP_CSQ_STAT 0x07f8 |
| # define RADEON_CSQ_RPTR_PRIMARY_MASK (0xff << 0) |
| # define RADEON_CSQ_WPTR_PRIMARY_MASK (0xff << 8) |
| # define RADEON_CSQ_RPTR_INDIRECT_MASK (0xff << 16) |
| # define RADEON_CSQ_WPTR_INDIRECT_MASK (0xff << 24) |
| #define RADEON_CP_CSQ_ADDR 0x07f0 |
| #define RADEON_CP_CSQ_DATA 0x07f4 |
| #define RADEON_CP_CSQ_APER_PRIMARY 0x1000 |
| #define RADEON_CP_CSQ_APER_INDIRECT 0x1300 |
| #define RADEON_CP_RB_WPTR_DELAY 0x0718 |
| # define RADEON_PRE_WRITE_TIMER_SHIFT 0 |
| # define RADEON_PRE_WRITE_LIMIT_SHIFT 23 |
| #define RADEON_AIC_CNTL 0x01d0 |
| # define RADEON_PCIGART_TRANSLATE_EN (1 << 0) |
| #define RADEON_AIC_LO_ADDR 0x01dc |
| /* Constants */ |
| #define RADEON_LAST_FRAME_REG RADEON_GUI_SCRATCH_REG0 |
| #define RADEON_LAST_CLEAR_REG RADEON_GUI_SCRATCH_REG2 |
| /* CP packet types */ |
| #define RADEON_CP_PACKET0 0x00000000 |
| #define RADEON_CP_PACKET1 0x40000000 |
| #define RADEON_CP_PACKET2 0x80000000 |
| #define RADEON_CP_PACKET3 0xC0000000 |
| # define RADEON_CP_PACKET_MASK 0xC0000000 |
| # define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000 |
| # define RADEON_CP_PACKET_MAX_DWORDS (1 << 12) |
| # define RADEON_CP_PACKET0_REG_MASK 0x000007ff |
| # define RADEON_CP_PACKET1_REG0_MASK 0x000007ff |
| # define RADEON_CP_PACKET1_REG1_MASK 0x003ff800 |
| #define RADEON_CP_PACKET0_ONE_REG_WR 0x00008000 |
| #define RADEON_CP_PACKET3_NOP 0xC0001000 |
| #define RADEON_CP_PACKET3_NEXT_CHAR 0xC0001900 |
| #define RADEON_CP_PACKET3_PLY_NEXTSCAN 0xC0001D00 |
| #define RADEON_CP_PACKET3_SET_SCISSORS 0xC0001E00 |
| #define RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM 0xC0002300 |
| #define RADEON_CP_PACKET3_LOAD_MICROCODE 0xC0002400 |
| #define RADEON_CP_PACKET3_WAIT_FOR_IDLE 0xC0002600 |
| #define RADEON_CP_PACKET3_3D_DRAW_VBUF 0xC0002800 |
| #define RADEON_CP_PACKET3_3D_DRAW_IMMD 0xC0002900 |
| #define RADEON_CP_PACKET3_3D_DRAW_INDX 0xC0002A00 |
| #define RADEON_CP_PACKET3_LOAD_PALETTE 0xC0002C00 |
| #define R200_CP_PACKET3_3D_DRAW_IMMD_2 0xc0003500 |
| #define RADEON_CP_PACKET3_3D_LOAD_VBPNTR 0xC0002F00 |
| #define RADEON_CP_PACKET3_CNTL_PAINT 0xC0009100 |
| #define RADEON_CP_PACKET3_CNTL_BITBLT 0xC0009200 |
| #define RADEON_CP_PACKET3_CNTL_SMALLTEXT 0xC0009300 |
| #define RADEON_CP_PACKET3_CNTL_HOSTDATA_BLT 0xC0009400 |
| #define RADEON_CP_PACKET3_CNTL_POLYLINE 0xC0009500 |
| #define RADEON_CP_PACKET3_CNTL_POLYSCANLINES 0xC0009800 |
| #define RADEON_CP_PACKET3_CNTL_PAINT_MULTI 0xC0009A00 |
| #define RADEON_CP_PACKET3_CNTL_BITBLT_MULTI 0xC0009B00 |
| #define RADEON_CP_PACKET3_CNTL_TRANS_BITBLT 0xC0009C00 |
| #define RADEON_CP_VC_FRMT_XY 0x00000000 |
| #define RADEON_CP_VC_FRMT_W0 0x00000001 |
| #define RADEON_CP_VC_FRMT_FPCOLOR 0x00000002 |
| #define RADEON_CP_VC_FRMT_FPALPHA 0x00000004 |
| #define RADEON_CP_VC_FRMT_PKCOLOR 0x00000008 |
| #define RADEON_CP_VC_FRMT_FPSPEC 0x00000010 |
| #define RADEON_CP_VC_FRMT_FPFOG 0x00000020 |
| #define RADEON_CP_VC_FRMT_PKSPEC 0x00000040 |
| #define RADEON_CP_VC_FRMT_ST0 0x00000080 |
| #define RADEON_CP_VC_FRMT_ST1 0x00000100 |
| #define RADEON_CP_VC_FRMT_Q1 0x00000200 |
| #define RADEON_CP_VC_FRMT_ST2 0x00000400 |
| #define RADEON_CP_VC_FRMT_Q2 0x00000800 |
| #define RADEON_CP_VC_FRMT_ST3 0x00001000 |
| #define RADEON_CP_VC_FRMT_Q3 0x00002000 |
| #define RADEON_CP_VC_FRMT_Q0 0x00004000 |
| #define RADEON_CP_VC_FRMT_BLND_WEIGHT_CNT_MASK 0x00038000 |
| #define RADEON_CP_VC_FRMT_N0 0x00040000 |
| #define RADEON_CP_VC_FRMT_XY1 0x08000000 |
| #define RADEON_CP_VC_FRMT_Z1 0x10000000 |
| #define RADEON_CP_VC_FRMT_W1 0x20000000 |
| #define RADEON_CP_VC_FRMT_N1 0x40000000 |
| #define RADEON_CP_VC_FRMT_Z 0x80000000 |
| #define RADEON_CP_VC_CNTL_PRIM_TYPE_NONE 0x00000000 |
| #define RADEON_CP_VC_CNTL_PRIM_TYPE_POINT 0x00000001 |
| #define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE 0x00000002 |
| #define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP 0x00000003 |
| #define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004 |
| #define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005 |
| #define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006 |
| #define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_TYPE_2 0x00000007 |
| #define RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST 0x00000008 |
| #define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_POINT_LIST 0x00000009 |
| #define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_LINE_LIST 0x0000000a |
| #define RADEON_CP_VC_CNTL_PRIM_TYPE_QUAD_LIST 0x0000000d |
| #define RADEON_CP_VC_CNTL_PRIM_WALK_IND 0x00000010 |
| #define RADEON_CP_VC_CNTL_PRIM_WALK_LIST 0x00000020 |
| #define RADEON_CP_VC_CNTL_PRIM_WALK_RING 0x00000030 |
| #define RADEON_CP_VC_CNTL_COLOR_ORDER_BGRA 0x00000000 |
| #define RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA 0x00000040 |
| #define RADEON_CP_VC_CNTL_MAOS_ENABLE 0x00000080 |
| #define RADEON_CP_VC_CNTL_VTX_FMT_NON_RADEON_MODE 0x00000000 |
| #define RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE 0x00000100 |
| #define RADEON_CP_VC_CNTL_TCL_DISABLE 0x00000000 |
| #define RADEON_CP_VC_CNTL_TCL_ENABLE 0x00000200 |
| #define RADEON_CP_VC_CNTL_NUM_SHIFT 16 |
| #define RADEON_VS_MATRIX_0_ADDR 0 |
| #define RADEON_VS_MATRIX_1_ADDR 4 |
| #define RADEON_VS_MATRIX_2_ADDR 8 |
| #define RADEON_VS_MATRIX_3_ADDR 12 |
| #define RADEON_VS_MATRIX_4_ADDR 16 |
| #define RADEON_VS_MATRIX_5_ADDR 20 |
| #define RADEON_VS_MATRIX_6_ADDR 24 |
| #define RADEON_VS_MATRIX_7_ADDR 28 |
| #define RADEON_VS_MATRIX_8_ADDR 32 |
| #define RADEON_VS_MATRIX_9_ADDR 36 |
| #define RADEON_VS_MATRIX_10_ADDR 40 |
| #define RADEON_VS_MATRIX_11_ADDR 44 |
| #define RADEON_VS_MATRIX_12_ADDR 48 |
| #define RADEON_VS_MATRIX_13_ADDR 52 |
| #define RADEON_VS_MATRIX_14_ADDR 56 |
| #define RADEON_VS_MATRIX_15_ADDR 60 |
| #define RADEON_VS_LIGHT_AMBIENT_ADDR 64 |
| #define RADEON_VS_LIGHT_DIFFUSE_ADDR 72 |
| #define RADEON_VS_LIGHT_SPECULAR_ADDR 80 |
| #define RADEON_VS_LIGHT_DIRPOS_ADDR 88 |
| #define RADEON_VS_LIGHT_HWVSPOT_ADDR 96 |
| #define RADEON_VS_LIGHT_ATTENUATION_ADDR 104 |
| #define RADEON_VS_MATRIX_EYE2CLIP_ADDR 112 |
| #define RADEON_VS_UCP_ADDR 116 |
| #define RADEON_VS_GLOBAL_AMBIENT_ADDR 122 |
| #define RADEON_VS_FOG_PARAM_ADDR 123 |
| #define RADEON_VS_EYE_VECTOR_ADDR 124 |
| #define RADEON_SS_LIGHT_DCD_ADDR 0 |
| #define RADEON_SS_LIGHT_SPOT_EXPONENT_ADDR 8 |
| #define RADEON_SS_LIGHT_SPOT_CUTOFF_ADDR 16 |
| #define RADEON_SS_LIGHT_SPECULAR_THRESH_ADDR 24 |
| #define RADEON_SS_LIGHT_RANGE_CUTOFF_ADDR 32 |
| #define RADEON_SS_VERT_GUARD_CLIP_ADJ_ADDR 48 |
| #define RADEON_SS_VERT_GUARD_DISCARD_ADJ_ADDR 49 |
| #define RADEON_SS_HORZ_GUARD_CLIP_ADJ_ADDR 50 |
| #define RADEON_SS_HORZ_GUARD_DISCARD_ADJ_ADDR 51 |
| #define RADEON_SS_SHININESS 60 |
| #define RADEON_TV_MASTER_CNTL 0x0800 |
| # define RADEON_TV_ASYNC_RST (1 << 0) |
| # define RADEON_CRT_ASYNC_RST (1 << 1) |
| # define RADEON_RESTART_PHASE_FIX (1 << 3) |
| # define RADEON_TV_FIFO_ASYNC_RST (1 << 4) |
| # define RADEON_VIN_ASYNC_RST (1 << 5) |
| # define RADEON_AUD_ASYNC_RST (1 << 6) |
| # define RADEON_DVS_ASYNC_RST (1 << 7) |
| # define RADEON_CRT_FIFO_CE_EN (1 << 9) |
| # define RADEON_TV_FIFO_CE_EN (1 << 10) |
| # define RADEON_RE_SYNC_NOW_SEL_MASK (3 << 14) |
| # define RADEON_TVCLK_ALWAYS_ONb (1 << 30) |
| # define RADEON_TV_ON (1 << 31) |
| #define RADEON_TV_PRE_DAC_MUX_CNTL 0x0888 |
| # define RADEON_Y_RED_EN (1 << 0) |
| # define RADEON_C_GRN_EN (1 << 1) |
| # define RADEON_CMP_BLU_EN (1 << 2) |
| # define RADEON_DAC_DITHER_EN (1 << 3) |
| # define RADEON_RED_MX_FORCE_DAC_DATA (6 << 4) |
| # define RADEON_GRN_MX_FORCE_DAC_DATA (6 << 8) |
| # define RADEON_BLU_MX_FORCE_DAC_DATA (6 << 12) |
| # define RADEON_TV_FORCE_DAC_DATA_SHIFT 16 |
| #define RADEON_TV_RGB_CNTL 0x0804 |
| # define RADEON_SWITCH_TO_BLUE (1 << 4) |
| # define RADEON_RGB_DITHER_EN (1 << 5) |
| # define RADEON_RGB_SRC_SEL_MASK (3 << 8) |
| # define RADEON_RGB_SRC_SEL_CRTC1 (0 << 8) |
| # define RADEON_RGB_SRC_SEL_RMX (1 << 8) |
| # define RADEON_RGB_SRC_SEL_CRTC2 (2 << 8) |
| # define RADEON_RGB_CONVERT_BY_PASS (1 << 10) |
| # define RADEON_UVRAM_READ_MARGIN_SHIFT 16 |
| # define RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT 20 |
| # define RADEON_TVOUT_SCALE_EN (1 << 26) |
| #define RADEON_TV_SYNC_CNTL 0x0808 |
| # define RADEON_SYNC_OE (1 << 0) |
| # define RADEON_SYNC_OUT (1 << 1) |
| # define RADEON_SYNC_IN (1 << 2) |
| # define RADEON_SYNC_PUB (1 << 3) |
| # define RADEON_SYNC_PD (1 << 4) |
| # define RADEON_TV_SYNC_IO_DRIVE (1 << 5) |
| #define RADEON_TV_HTOTAL 0x080c |
| #define RADEON_TV_HDISP 0x0810 |
| #define RADEON_TV_HSTART 0x0818 |
| #define RADEON_TV_HCOUNT 0x081C |
| #define RADEON_TV_VTOTAL 0x0820 |
| #define RADEON_TV_VDISP 0x0824 |
| #define RADEON_TV_VCOUNT 0x0828 |
| #define RADEON_TV_FTOTAL 0x082c |
| #define RADEON_TV_FCOUNT 0x0830 |
| #define RADEON_TV_FRESTART 0x0834 |
| #define RADEON_TV_HRESTART 0x0838 |
| #define RADEON_TV_VRESTART 0x083c |
| #define RADEON_TV_HOST_READ_DATA 0x0840 |
| #define RADEON_TV_HOST_WRITE_DATA 0x0844 |
| #define RADEON_TV_HOST_RD_WT_CNTL 0x0848 |
| # define RADEON_HOST_FIFO_RD (1 << 12) |
| # define RADEON_HOST_FIFO_RD_ACK (1 << 13) |
| # define RADEON_HOST_FIFO_WT (1 << 14) |
| # define RADEON_HOST_FIFO_WT_ACK (1 << 15) |
| #define RADEON_TV_VSCALER_CNTL1 0x084c |
| # define RADEON_UV_INC_MASK 0xffff |
| # define RADEON_UV_INC_SHIFT 0 |
| # define RADEON_Y_W_EN (1 << 24) |
| # define RADEON_RESTART_FIELD (1 << 29) /* restart on field 0 */ |
| # define RADEON_Y_DEL_W_SIG_SHIFT 26 |
| #define RADEON_TV_TIMING_CNTL 0x0850 |
| # define RADEON_H_INC_MASK 0xfff |
| # define RADEON_H_INC_SHIFT 0 |
| # define RADEON_REQ_Y_FIRST (1 << 19) |
| # define RADEON_FORCE_BURST_ALWAYS (1 << 21) |
| # define RADEON_UV_POST_SCALE_BYPASS (1 << 23) |
| # define RADEON_UV_OUTPUT_POST_SCALE_SHIFT 24 |
| #define RADEON_TV_VSCALER_CNTL2 0x0854 |
| # define RADEON_DITHER_MODE (1 << 0) |
| # define RADEON_Y_OUTPUT_DITHER_EN (1 << 1) |
| # define RADEON_UV_OUTPUT_DITHER_EN (1 << 2) |
| # define RADEON_UV_TO_BUF_DITHER_EN (1 << 3) |
| #define RADEON_TV_Y_FALL_CNTL 0x0858 |
| # define RADEON_Y_FALL_PING_PONG (1 << 16) |
| # define RADEON_Y_COEF_EN (1 << 17) |
| #define RADEON_TV_Y_RISE_CNTL 0x085c |
| # define RADEON_Y_RISE_PING_PONG (1 << 16) |
| #define RADEON_TV_Y_SAW_TOOTH_CNTL 0x0860 |
| #define RADEON_TV_UPSAMP_AND_GAIN_CNTL 0x0864 |
| # define RADEON_YUPSAMP_EN (1 << 0) |
| # define RADEON_UVUPSAMP_EN (1 << 2) |
| #define RADEON_TV_GAIN_LIMIT_SETTINGS 0x0868 |
| # define RADEON_Y_GAIN_LIMIT_SHIFT 0 |
| # define RADEON_UV_GAIN_LIMIT_SHIFT 16 |
| #define RADEON_TV_LINEAR_GAIN_SETTINGS 0x086c |
| # define RADEON_Y_GAIN_SHIFT 0 |
| # define RADEON_UV_GAIN_SHIFT 16 |
| #define RADEON_TV_MODULATOR_CNTL1 0x0870 |
| # define RADEON_YFLT_EN (1 << 2) |
| # define RADEON_UVFLT_EN (1 << 3) |
| # define RADEON_ALT_PHASE_EN (1 << 6) |
| # define RADEON_SYNC_TIP_LEVEL (1 << 7) |
| # define RADEON_BLANK_LEVEL_SHIFT 8 |
| # define RADEON_SET_UP_LEVEL_SHIFT 16 |
| # define RADEON_SLEW_RATE_LIMIT (1 << 23) |
| # define RADEON_CY_FILT_BLEND_SHIFT 28 |
| #define RADEON_TV_MODULATOR_CNTL2 0x0874 |
| # define RADEON_TV_U_BURST_LEVEL_MASK 0x1ff |
| # define RADEON_TV_V_BURST_LEVEL_MASK 0x1ff |
| # define RADEON_TV_V_BURST_LEVEL_SHIFT 16 |
| #define RADEON_TV_CRC_CNTL 0x0890 |
| #define RADEON_TV_UV_ADR 0x08ac |
| # define RADEON_MAX_UV_ADR_MASK 0x000000ff |
| # define RADEON_MAX_UV_ADR_SHIFT 0 |
| # define RADEON_TABLE1_BOT_ADR_MASK 0x0000ff00 |
| # define RADEON_TABLE1_BOT_ADR_SHIFT 8 |
| # define RADEON_TABLE3_TOP_ADR_MASK 0x00ff0000 |
| # define RADEON_TABLE3_TOP_ADR_SHIFT 16 |
| # define RADEON_HCODE_TABLE_SEL_MASK 0x06000000 |
| # define RADEON_HCODE_TABLE_SEL_SHIFT 25 |
| # define RADEON_VCODE_TABLE_SEL_MASK 0x18000000 |
| # define RADEON_VCODE_TABLE_SEL_SHIFT 27 |
| # define RADEON_TV_MAX_FIFO_ADDR 0x1a7 |
| # define RADEON_TV_MAX_FIFO_ADDR_INTERNAL 0x1ff |
| #define RADEON_TV_PLL_FINE_CNTL 0x0020 /* PLL */ |
| #define RADEON_TV_PLL_CNTL 0x0021 /* PLL */ |
| # define RADEON_TV_M0LO_MASK 0xff |
| # define RADEON_TV_M0HI_MASK 0x7 |
| # define RADEON_TV_M0HI_SHIFT 18 |
| # define RADEON_TV_N0LO_MASK 0x1ff |
| # define RADEON_TV_N0LO_SHIFT 8 |
| # define RADEON_TV_N0HI_MASK 0x3 |
| # define RADEON_TV_N0HI_SHIFT 21 |
| # define RADEON_TV_P_MASK 0xf |
| # define RADEON_TV_P_SHIFT 24 |
| # define RADEON_TV_SLIP_EN (1 << 23) |
| # define RADEON_TV_DTO_EN (1 << 28) |
| #define RADEON_TV_PLL_CNTL1 0x0022 /* PLL */ |
| # define RADEON_TVPLL_RESET (1 << 1) |
| # define RADEON_TVPLL_SLEEP (1 << 3) |
| # define RADEON_TVPLL_REFCLK_SEL (1 << 4) |
| # define RADEON_TVPCP_SHIFT 8 |
| # define RADEON_TVPCP_MASK (7 << 8) |
| # define RADEON_TVPVG_SHIFT 11 |
| # define RADEON_TVPVG_MASK (7 << 11) |
| # define RADEON_TVPDC_SHIFT 14 |
| # define RADEON_TVPDC_MASK (3 << 14) |
| # define RADEON_TVPLL_TEST_DIS (1 << 31) |
| # define RADEON_TVCLK_SRC_SEL_TVPLL (1 << 30) |
| #define RS400_DISP2_REQ_CNTL1 0xe30 |
| # define RS400_DISP2_START_REQ_LEVEL_SHIFT 0 |
| # define RS400_DISP2_START_REQ_LEVEL_MASK 0x3ff |
| # define RS400_DISP2_STOP_REQ_LEVEL_SHIFT 12 |
| # define RS400_DISP2_STOP_REQ_LEVEL_MASK 0x3ff |
| # define RS400_DISP2_ALLOW_FID_LEVEL_SHIFT 22 |
| # define RS400_DISP2_ALLOW_FID_LEVEL_MASK 0x3ff |
| #define RS400_DISP2_REQ_CNTL2 0xe34 |
| # define RS400_DISP2_CRITICAL_POINT_START_SHIFT 12 |
| # define RS400_DISP2_CRITICAL_POINT_START_MASK 0x3ff |
| # define RS400_DISP2_CRITICAL_POINT_STOP_SHIFT 22 |
| # define RS400_DISP2_CRITICAL_POINT_STOP_MASK 0x3ff |
| #define RS400_DMIF_MEM_CNTL1 0xe38 |
| # define RS400_DISP2_START_ADR_SHIFT 0 |
| # define RS400_DISP2_START_ADR_MASK 0x3ff |
| # define RS400_DISP1_CRITICAL_POINT_START_SHIFT 12 |
| # define RS400_DISP1_CRITICAL_POINT_START_MASK 0x3ff |
| # define RS400_DISP1_CRITICAL_POINT_STOP_SHIFT 22 |
| # define RS400_DISP1_CRITICAL_POINT_STOP_MASK 0x3ff |
| #define RS400_DISP1_REQ_CNTL1 0xe3c |
| # define RS400_DISP1_START_REQ_LEVEL_SHIFT 0 |
| # define RS400_DISP1_START_REQ_LEVEL_MASK 0x3ff |
| # define RS400_DISP1_STOP_REQ_LEVEL_SHIFT 12 |
| # define RS400_DISP1_STOP_REQ_LEVEL_MASK 0x3ff |
| # define RS400_DISP1_ALLOW_FID_LEVEL_SHIFT 22 |
| # define RS400_DISP1_ALLOW_FID_LEVEL_MASK 0x3ff |
| #define RS690_MC_INDEX 0x78 |
| # define RS690_MC_INDEX_MASK 0x1ff |
| # define RS690_MC_INDEX_WR_EN (1 << 9) |
| # define RS690_MC_INDEX_WR_ACK 0x7f |
| #define RS690_MC_DATA 0x7c |
| #define RS690_MC_FB_LOCATION 0x100 |
| #define RS690_MC_AGP_LOCATION 0x101 |
| #define RS690_MC_AGP_BASE 0x102 |
| #define RS690_MC_AGP_BASE_2 0x103 |
| #define RS690_MC_INIT_MISC_LAT_TIMER 0x104 |
| #define RS690_MC_STATUS 0x90 |
| #define RS690_MC_STATUS_IDLE (1 << 0) |
| #define RS600_MC_INDEX 0x78 |
| # define RS600_MC_INDEX_MASK 0xff |
| # define RS600_MC_INDEX_WR_EN (1 << 8) |
| # define RS600_MC_INDEX_WR_ACK 0xff |
| #define RS600_MC_DATA 0x7c |
| #define RS600_MC_FB_LOCATION 0xA |
| #define RS600_MC_STATUS 0x0 |
| #define RS600_MC_STATUS_IDLE (1 << 0) |
| #define AVIVO_MC_INDEX 0x0070 |
| #define R520_MC_STATUS 0x00 |
| # define R520_MC_STATUS_IDLE (1 << 1) |
| #define RV515_MC_STATUS 0x08 |
| # define RV515_MC_STATUS_IDLE (1 << 4) |
| #define RV515_MC_INIT_MISC_LAT_TIMER 0x09 |
| #define AVIVO_MC_DATA 0x0074 |
| #define RV515_MC_FB_LOCATION 0x1 |
| #define RV515_MC_AGP_LOCATION 0x2 |
| #define RV515_MC_AGP_BASE 0x3 |
| #define RV515_MC_AGP_BASE_2 0x4 |
| #define RV515_MC_CNTL 0x5 |
| # define RV515_MEM_NUM_CHANNELS_MASK 0x3 |
| #define R520_MC_FB_LOCATION 0x4 |
| #define R520_MC_AGP_LOCATION 0x5 |
| #define R520_MC_AGP_BASE 0x6 |
| #define R520_MC_AGP_BASE_2 0x7 |
| #define R520_MC_CNTL0 0x8 |
| # define R520_MEM_NUM_CHANNELS_MASK (0x3 << 24) |
| # define R520_MEM_NUM_CHANNELS_SHIFT 24 |
| # define R520_MC_CHANNEL_SIZE (1 << 23) |
| #define R600_RAMCFG 0x2408 |
| # define R600_CHANSIZE (1 << 7) |
| # define R600_CHANSIZE_OVERRIDE (1 << 10) |
| #define AVIVO_HDP_FB_LOCATION 0x134 |
| #define AVIVO_VGA_RENDER_CONTROL 0x0300 |
| # define AVIVO_VGA_VSTATUS_CNTL_MASK (3 << 16) |
| #define AVIVO_D1VGA_CONTROL 0x0330 |
| # define AVIVO_DVGA_CONTROL_MODE_ENABLE (1<<0) |
| # define AVIVO_DVGA_CONTROL_TIMING_SELECT (1<<8) |
| # define AVIVO_DVGA_CONTROL_SYNC_POLARITY_SELECT (1<<9) |
| # define AVIVO_DVGA_CONTROL_OVERSCAN_TIMING_SELECT (1<<10) |
| # define AVIVO_DVGA_CONTROL_OVERSCAN_COLOR_EN (1<<16) |
| # define AVIVO_DVGA_CONTROL_ROTATE (1<<24) |
| #define AVIVO_D2VGA_CONTROL 0x0338 |
| #define AVIVO_EXT1_PPLL_REF_DIV_SRC 0x400 |
| #define AVIVO_EXT1_PPLL_REF_DIV 0x404 |
| #define AVIVO_EXT1_PPLL_UPDATE_LOCK 0x408 |
| #define AVIVO_EXT1_PPLL_UPDATE_CNTL 0x40c |
| #define AVIVO_EXT2_PPLL_REF_DIV_SRC 0x410 |
| #define AVIVO_EXT2_PPLL_REF_DIV 0x414 |
| #define AVIVO_EXT2_PPLL_UPDATE_LOCK 0x418 |
| #define AVIVO_EXT2_PPLL_UPDATE_CNTL 0x41c |
| #define AVIVO_EXT1_PPLL_FB_DIV 0x430 |
| #define AVIVO_EXT2_PPLL_FB_DIV 0x434 |
| #define AVIVO_EXT1_PPLL_POST_DIV_SRC 0x438 |
| #define AVIVO_EXT1_PPLL_POST_DIV 0x43c |
| #define AVIVO_EXT2_PPLL_POST_DIV_SRC 0x440 |
| #define AVIVO_EXT2_PPLL_POST_DIV 0x444 |
| #define AVIVO_EXT1_PPLL_CNTL 0x448 |
| #define AVIVO_EXT2_PPLL_CNTL 0x44c |
| #define AVIVO_P1PLL_CNTL 0x450 |
| #define AVIVO_P2PLL_CNTL 0x454 |
| #define AVIVO_P1PLL_INT_SS_CNTL 0x458 |
| #define AVIVO_P2PLL_INT_SS_CNTL 0x45c |
| #define AVIVO_P1PLL_TMDSA_CNTL 0x460 |
| #define AVIVO_P2PLL_LVTMA_CNTL 0x464 |
| #define AVIVO_PCLK_CRTC1_CNTL 0x480 |
| #define AVIVO_PCLK_CRTC2_CNTL 0x484 |
| #define AVIVO_D1CRTC_H_TOTAL 0x6000 |
| #define AVIVO_D1CRTC_H_BLANK_START_END 0x6004 |
| #define AVIVO_D1CRTC_H_SYNC_A 0x6008 |
| #define AVIVO_D1CRTC_H_SYNC_A_CNTL 0x600c |
| #define AVIVO_D1CRTC_H_SYNC_B 0x6010 |
| #define AVIVO_D1CRTC_H_SYNC_B_CNTL 0x6014 |
| #define AVIVO_D1CRTC_V_TOTAL 0x6020 |
| #define AVIVO_D1CRTC_V_BLANK_START_END 0x6024 |
| #define AVIVO_D1CRTC_V_SYNC_A 0x6028 |
| #define AVIVO_D1CRTC_V_SYNC_A_CNTL 0x602c |
| #define AVIVO_D1CRTC_V_SYNC_B 0x6030 |
| #define AVIVO_D1CRTC_V_SYNC_B_CNTL 0x6034 |
| #define AVIVO_D1CRTC_CONTROL 0x6080 |
| # define AVIVO_CRTC_EN (1<<0) |
| #define AVIVO_D1CRTC_BLANK_CONTROL 0x6084 |
| #define AVIVO_D1CRTC_INTERLACE_CONTROL 0x6088 |
| #define AVIVO_D1CRTC_INTERLACE_STATUS 0x608c |
| #define AVIVO_D1CRTC_STEREO_CONTROL 0x60c4 |
| /* master controls */ |
| #define AVIVO_DC_CRTC_MASTER_EN 0x60f8 |
| #define AVIVO_DC_CRTC_TV_CONTROL 0x60fc |
| #define AVIVO_D1GRPH_ENABLE 0x6100 |
| #define AVIVO_D1GRPH_CONTROL 0x6104 |
| # define AVIVO_D1GRPH_CONTROL_DEPTH_8BPP (0<<0) |
| # define AVIVO_D1GRPH_CONTROL_DEPTH_16BPP (1<<0) |
| # define AVIVO_D1GRPH_CONTROL_DEPTH_32BPP (2<<0) |
| # define AVIVO_D1GRPH_CONTROL_DEPTH_64BPP (3<<0) |
| # define AVIVO_D1GRPH_CONTROL_8BPP_INDEXED (0<<8) |
| # define AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555 (0<<8) |
| # define AVIVO_D1GRPH_CONTROL_16BPP_RGB565 (1<<8) |
| # define AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444 (2<<8) |
| # define AVIVO_D1GRPH_CONTROL_16BPP_AI88 (3<<8) |
| # define AVIVO_D1GRPH_CONTROL_16BPP_MONO16 (4<<8) |
| # define AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888 (0<<8) |
| # define AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010 (1<<8) |
| # define AVIVO_D1GRPH_CONTROL_32BPP_DIGITAL (2<<8) |
| # define AVIVO_D1GRPH_CONTROL_32BPP_8B_ARGB2101010 (3<<8) |
| # define AVIVO_D1GRPH_CONTROL_64BPP_ARGB16161616 (0<<8) |
| # define AVIVO_D1GRPH_SWAP_RB (1<<16) |
| # define AVIVO_D1GRPH_TILED (1<<20) |
| # define AVIVO_D1GRPH_MACRO_ADDRESS_MODE (1<<21) |
| #define AVIVO_D1GRPH_LUT_SEL 0x6108 |
| #define AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110 |
| #define AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118 |
| #define AVIVO_D1GRPH_PITCH 0x6120 |
| #define AVIVO_D1GRPH_SURFACE_OFFSET_X 0x6124 |
| #define AVIVO_D1GRPH_SURFACE_OFFSET_Y 0x6128 |
| #define AVIVO_D1GRPH_X_START 0x612c |
| #define AVIVO_D1GRPH_Y_START 0x6130 |
| #define AVIVO_D1GRPH_X_END 0x6134 |
| #define AVIVO_D1GRPH_Y_END 0x6138 |
| #define AVIVO_D1GRPH_UPDATE 0x6144 |
| # define AVIVO_D1GRPH_UPDATE_LOCK (1<<16) |
| #define AVIVO_D1GRPH_FLIP_CONTROL 0x6148 |
| #define AVIVO_D1CUR_CONTROL 0x6400 |
| # define AVIVO_D1CURSOR_EN (1<<0) |
| # define AVIVO_D1CURSOR_MODE_SHIFT 8 |
| # define AVIVO_D1CURSOR_MODE_MASK (0x3<<8) |
| # define AVIVO_D1CURSOR_MODE_24BPP (0x2) |
| #define AVIVO_D1CUR_SURFACE_ADDRESS 0x6408 |
| #define AVIVO_D1CUR_SIZE 0x6410 |
| #define AVIVO_D1CUR_POSITION 0x6414 |
| #define AVIVO_D1CUR_HOT_SPOT 0x6418 |
| #define AVIVO_D1CUR_UPDATE 0x6424 |
| # define AVIVO_D1CURSOR_UPDATE_LOCK (1 << 16) |
| #define AVIVO_DC_LUT_RW_SELECT 0x6480 |
| #define AVIVO_DC_LUT_RW_MODE 0x6484 |
| #define AVIVO_DC_LUT_RW_INDEX 0x6488 |
| #define AVIVO_DC_LUT_SEQ_COLOR 0x648c |
| #define AVIVO_DC_LUT_PWL_DATA 0x6490 |
| #define AVIVO_DC_LUT_30_COLOR 0x6494 |
| #define AVIVO_DC_LUT_READ_PIPE_SELECT 0x6498 |
| #define AVIVO_DC_LUT_WRITE_EN_MASK 0x649c |
| #define AVIVO_DC_LUT_AUTOFILL 0x64a0 |
| #define AVIVO_DC_LUTA_CONTROL 0x64c0 |
| #define AVIVO_DC_LUTA_BLACK_OFFSET_BLUE 0x64c4 |
| #define AVIVO_DC_LUTA_BLACK_OFFSET_GREEN 0x64c8 |
| #define AVIVO_DC_LUTA_BLACK_OFFSET_RED 0x64cc |
| #define AVIVO_DC_LUTA_WHITE_OFFSET_BLUE 0x64d0 |
| #define AVIVO_DC_LUTA_WHITE_OFFSET_GREEN 0x64d4 |
| #define AVIVO_DC_LUTA_WHITE_OFFSET_RED 0x64d8 |
| #define AVIVO_DC_LB_MEMORY_SPLIT 0x6520 |
| # define AVIVO_DC_LB_MEMORY_SPLIT_MASK 0x3 |
| # define AVIVO_DC_LB_MEMORY_SPLIT_SHIFT 0 |
| # define AVIVO_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF 0 |
| # define AVIVO_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q 1 |
| # define AVIVO_DC_LB_MEMORY_SPLIT_D1_ONLY 2 |
| # define AVIVO_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q 3 |
| # define AVIVO_DC_LB_MEMORY_SPLIT_SHIFT_MODE (1 << 2) |
| # define AVIVO_DC_LB_DISP1_END_ADR_SHIFT 4 |
| # define AVIVO_DC_LB_DISP1_END_ADR_MASK 0x7ff |
| #define AVIVO_D1MODE_DATA_FORMAT 0x6528 |
| # define AVIVO_D1MODE_INTERLEAVE_EN (1 << 0) |
| #define AVIVO_D1MODE_DESKTOP_HEIGHT 0x652c |
| #define AVIVO_D1MODE_VIEWPORT_START 0x6580 |
| #define AVIVO_D1MODE_VIEWPORT_SIZE 0x6584 |
| #define AVIVO_D1MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6588 |
| #define AVIVO_D1MODE_EXT_OVERSCAN_TOP_BOTTOM 0x658c |
| #define AVIVO_D1SCL_SCALER_ENABLE 0x6590 |
| #define AVIVO_D1SCL_SCALER_TAP_CONTROL 0x6594 |
| #define AVIVO_D1SCL_UPDATE 0x65cc |
| # define AVIVO_D1SCL_UPDATE_LOCK (1<<16) |
| /* second crtc */ |
| #define AVIVO_D2CRTC_H_TOTAL 0x6800 |
| #define AVIVO_D2CRTC_H_BLANK_START_END 0x6804 |
| #define AVIVO_D2CRTC_H_SYNC_A 0x6808 |
| #define AVIVO_D2CRTC_H_SYNC_A_CNTL 0x680c |
| #define AVIVO_D2CRTC_H_SYNC_B 0x6810 |
| #define AVIVO_D2CRTC_H_SYNC_B_CNTL 0x6814 |
| #define AVIVO_D2CRTC_V_TOTAL 0x6820 |
| #define AVIVO_D2CRTC_V_BLANK_START_END 0x6824 |
| #define AVIVO_D2CRTC_V_SYNC_A 0x6828 |
| #define AVIVO_D2CRTC_V_SYNC_A_CNTL 0x682c |
| #define AVIVO_D2CRTC_V_SYNC_B 0x6830 |
| #define AVIVO_D2CRTC_V_SYNC_B_CNTL 0x6834 |
| #define AVIVO_D2CRTC_CONTROL 0x6880 |
| #define AVIVO_D2CRTC_BLANK_CONTROL 0x6884 |
| #define AVIVO_D2CRTC_INTERLACE_CONTROL 0x6888 |
| #define AVIVO_D2CRTC_INTERLACE_STATUS 0x688c |
| #define AVIVO_D2CRTC_STEREO_CONTROL 0x68c4 |
| #define AVIVO_D2GRPH_ENABLE 0x6900 |
| #define AVIVO_D2GRPH_CONTROL 0x6904 |
| #define AVIVO_D2GRPH_LUT_SEL 0x6908 |
| #define AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS 0x6910 |
| #define AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS 0x6918 |
| #define AVIVO_D2GRPH_PITCH 0x6920 |
| #define AVIVO_D2GRPH_SURFACE_OFFSET_X 0x6924 |
| #define AVIVO_D2GRPH_SURFACE_OFFSET_Y 0x6928 |
| #define AVIVO_D2GRPH_X_START 0x692c |
| #define AVIVO_D2GRPH_Y_START 0x6930 |
| #define AVIVO_D2GRPH_X_END 0x6934 |
| #define AVIVO_D2GRPH_Y_END 0x6938 |
| #define AVIVO_D2GRPH_UPDATE 0x6944 |
| #define AVIVO_D2GRPH_FLIP_CONTROL 0x6948 |
| #define AVIVO_D2CUR_CONTROL 0x6c00 |
| #define AVIVO_D2CUR_SURFACE_ADDRESS 0x6c08 |
| #define AVIVO_D2CUR_SIZE 0x6c10 |
| #define AVIVO_D2CUR_POSITION 0x6c14 |
| #define AVIVO_D2MODE_DATA_FORMAT 0x6d28 |
| #define AVIVO_D2MODE_DESKTOP_HEIGHT 0x6d2c |
| #define AVIVO_D2MODE_VIEWPORT_START 0x6d80 |
| #define AVIVO_D2MODE_VIEWPORT_SIZE 0x6d84 |
| #define AVIVO_D2MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6d88 |
| #define AVIVO_D2MODE_EXT_OVERSCAN_TOP_BOTTOM 0x6d8c |
| #define AVIVO_D2SCL_SCALER_ENABLE 0x6d90 |
| #define AVIVO_D2SCL_SCALER_TAP_CONTROL 0x6d94 |
| #define AVIVO_D2SCL_UPDATE 0x6dcc |
| #define AVIVO_DDIA_BIT_DEPTH_CONTROL 0x7214 |
| #define AVIVO_DACA_ENABLE 0x7800 |
| # define AVIVO_DAC_ENABLE (1 << 0) |
| #define AVIVO_DACA_SOURCE_SELECT 0x7804 |
| # define AVIVO_DAC_SOURCE_CRTC1 (0 << 0) |
| # define AVIVO_DAC_SOURCE_CRTC2 (1 << 0) |
| # define AVIVO_DAC_SOURCE_TV (2 << 0) |
| #define AVIVO_DACA_FORCE_OUTPUT_CNTL 0x783c |
| # define AVIVO_DACA_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0) |
| # define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8) |
| # define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0) |
| # define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1) |
| # define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2) |
| # define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24) |
| #define AVIVO_DACA_POWERDOWN 0x7850 |
| # define AVIVO_DACA_POWERDOWN_POWERDOWN (1 << 0) |
| # define AVIVO_DACA_POWERDOWN_BLUE (1 << 8) |
| # define AVIVO_DACA_POWERDOWN_GREEN (1 << 16) |
| # define AVIVO_DACA_POWERDOWN_RED (1 << 24) |
| #define AVIVO_DACB_ENABLE 0x7a00 |
| #define AVIVO_DACB_SOURCE_SELECT 0x7a04 |
| #define AVIVO_DACB_FORCE_OUTPUT_CNTL 0x7a3c |
| # define AVIVO_DACB_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0) |
| # define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8) |
| # define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0) |
| # define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1) |
| # define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2) |
| # define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24) |
| #define AVIVO_DACB_POWERDOWN 0x7a50 |
| # define AVIVO_DACB_POWERDOWN_POWERDOWN (1 << 0) |
| # define AVIVO_DACB_POWERDOWN_BLUE (1 << 8) |
| # define AVIVO_DACB_POWERDOWN_GREEN (1 << 16) |
| # define AVIVO_DACB_POWERDOWN_RED |
| #define AVIVO_TMDSA_CNTL 0x7880 |
| # define AVIVO_TMDSA_CNTL_ENABLE (1 << 0) |
| # define AVIVO_TMDSA_CNTL_HPD_MASK (1 << 4) |
| # define AVIVO_TMDSA_CNTL_HPD_SELECT (1 << 8) |
| # define AVIVO_TMDSA_CNTL_SYNC_PHASE (1 << 12) |
| # define AVIVO_TMDSA_CNTL_PIXEL_ENCODING (1 << 16) |
| # define AVIVO_TMDSA_CNTL_DUAL_LINK_ENABLE (1 << 24) |
| # define AVIVO_TMDSA_CNTL_SWAP (1 << 28) |
| #define AVIVO_TMDSA_SOURCE_SELECT 0x7884 |
| /* 78a8 appears to be some kind of (reasonably tolerant) clock? |
| * 78d0 definitely hits the transmitter, definitely clock. */ |
| /* MYSTERY1 This appears to control dithering? */ |
| #define AVIVO_TMDSA_BIT_DEPTH_CONTROL 0x7894 |
| # define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0) |
| # define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4) |
| # define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8) |
| # define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12) |
| # define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16) |
| # define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20) |
| # define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24) |
| # define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26) |
| #define AVIVO_TMDSA_DCBALANCER_CONTROL 0x78d0 |
| # define AVIVO_TMDSA_DCBALANCER_CONTROL_EN (1 << 0) |
| # define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_EN (1 << 8) |
| # define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16) |
| # define AVIVO_TMDSA_DCBALANCER_CONTROL_FORCE (1 << 24) |
| #define AVIVO_TMDSA_DATA_SYNCHRONIZATION 0x78d8 |
| # define AVIVO_TMDSA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0) |
| # define AVIVO_TMDSA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8) |
| #define AVIVO_TMDSA_CLOCK_ENABLE 0x7900 |
| #define AVIVO_TMDSA_TRANSMITTER_ENABLE 0x7904 |
| # define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX0_ENABLE (1 << 0) |
| # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1) |
| # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2) |
| # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3) |
| # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4) |
| # define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX1_ENABLE (1 << 8) |
| # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10) |
| # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11) |
| # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12) |
| # define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX_ENABLE_HPD_MASK (1 << 16) |
| # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17) |
| # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18) |
| #define AVIVO_TMDSA_TRANSMITTER_CONTROL 0x7910 |
| # define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0) |
| # define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1) |
| # define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2) |
| # define AVIVO_TMDSA_TRANSMITTER_CONTROL_IDSCKSEL (1 << 4) |
| # define AVIVO_TMDSA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5) |
| # define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN (1 << 6) |
| # define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK (1 << 8) |
| # define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS (1 << 13) |
| # define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK (1 << 14) |
| # define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS (1 << 15) |
| # define AVIVO_TMDSA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16) |
| # define AVIVO_TMDSA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28) |
| # define AVIVO_TMDSA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29) |
| # define AVIVO_TMDSA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31) |
| #define AVIVO_LVTMA_CNTL 0x7a80 |
| # define AVIVO_LVTMA_CNTL_ENABLE (1 << 0) |
| # define AVIVO_LVTMA_CNTL_HPD_MASK (1 << 4) |
| # define AVIVO_LVTMA_CNTL_HPD_SELECT (1 << 8) |
| # define AVIVO_LVTMA_CNTL_SYNC_PHASE (1 << 12) |
| # define AVIVO_LVTMA_CNTL_PIXEL_ENCODING (1 << 16) |
| # define AVIVO_LVTMA_CNTL_DUAL_LINK_ENABLE (1 << 24) |
| # define AVIVO_LVTMA_CNTL_SWAP (1 << 28) |
| #define AVIVO_LVTMA_SOURCE_SELECT 0x7a84 |
| #define AVIVO_LVTMA_COLOR_FORMAT 0x7a88 |
| #define AVIVO_LVTMA_BIT_DEPTH_CONTROL 0x7a94 |
| # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0) |
| # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4) |
| # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8) |
| # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12) |
| # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16) |
| # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20) |
| # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24) |
| # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26) |
| #define AVIVO_LVTMA_DCBALANCER_CONTROL 0x7ad0 |
| # define AVIVO_LVTMA_DCBALANCER_CONTROL_EN (1 << 0) |
| # define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_EN (1 << 8) |
| # define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16) |
| # define AVIVO_LVTMA_DCBALANCER_CONTROL_FORCE (1 << 24) |
| #define AVIVO_LVTMA_DATA_SYNCHRONIZATION 0x78d8 |
| # define AVIVO_LVTMA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0) |
| # define AVIVO_LVTMA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8) |
| #define R500_LVTMA_CLOCK_ENABLE 0x7b00 |
| #define R600_LVTMA_CLOCK_ENABLE 0x7b04 |
| #define R500_LVTMA_TRANSMITTER_ENABLE 0x7b04 |
| #define R600_LVTMA_TRANSMITTER_ENABLE 0x7b08 |
| # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1) |
| # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2) |
| # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3) |
| # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4) |
| # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD03EN (1 << 5) |
| # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC1EN (1 << 9) |
| # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10) |
| # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11) |
| # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12) |
| # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17) |
| # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18) |
| #define R500_LVTMA_TRANSMITTER_CONTROL 0x7b10 |
| #define R600_LVTMA_TRANSMITTER_CONTROL 0x7b14 |
| # define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0) |
| # define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1) |
| # define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2) |
| # define AVIVO_LVTMA_TRANSMITTER_CONTROL_IDSCKSEL (1 << 4) |
| # define AVIVO_LVTMA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5) |
| # define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN (1 << 6) |
| # define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK (1 << 8) |
| # define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS (1 << 13) |
| # define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK (1 << 14) |
| # define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS (1 << 15) |
| # define AVIVO_LVTMA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16) |
| # define AVIVO_LVTMA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28) |
| # define AVIVO_LVTMA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29) |
| # define AVIVO_LVTMA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31) |
| #define R500_LVTMA_PWRSEQ_CNTL 0x7af0 |
| #define R600_LVTMA_PWRSEQ_CNTL 0x7af4 |
| # define AVIVO_LVTMA_PWRSEQ_EN (1 << 0) |
| # define AVIVO_LVTMA_PWRSEQ_PLL_ENABLE_MASK (1 << 2) |
| # define AVIVO_LVTMA_PWRSEQ_PLL_RESET_MASK (1 << 3) |
| # define AVIVO_LVTMA_PWRSEQ_TARGET_STATE (1 << 4) |
| # define AVIVO_LVTMA_SYNCEN (1 << 8) |
| # define AVIVO_LVTMA_SYNCEN_OVRD (1 << 9) |
| # define AVIVO_LVTMA_SYNCEN_POL (1 << 10) |
| # define AVIVO_LVTMA_DIGON (1 << 16) |
| # define AVIVO_LVTMA_DIGON_OVRD (1 << 17) |
| # define AVIVO_LVTMA_DIGON_POL (1 << 18) |
| # define AVIVO_LVTMA_BLON (1 << 24) |
| # define AVIVO_LVTMA_BLON_OVRD (1 << 25) |
| # define AVIVO_LVTMA_BLON_POL (1 << 26) |
| #define R500_LVTMA_PWRSEQ_STATE 0x7af4 |
| #define R600_LVTMA_PWRSEQ_STATE 0x7af8 |
| # define AVIVO_LVTMA_PWRSEQ_STATE_TARGET_STATE_R (1 << 0) |
| # define AVIVO_LVTMA_PWRSEQ_STATE_DIGON (1 << 1) |
| # define AVIVO_LVTMA_PWRSEQ_STATE_SYNCEN (1 << 2) |
| # define AVIVO_LVTMA_PWRSEQ_STATE_BLON (1 << 3) |
| # define AVIVO_LVTMA_PWRSEQ_STATE_DONE (1 << 4) |
| # define AVIVO_LVTMA_PWRSEQ_STATE_STATUS_SHIFT (8) |
| #define AVIVO_LVDS_BACKLIGHT_CNTL 0x7af8 |
| # define AVIVO_LVDS_BACKLIGHT_CNTL_EN (1 << 0) |
| # define AVIVO_LVDS_BACKLIGHT_LEVEL_MASK 0x0000ff00 |
| # define AVIVO_LVDS_BACKLIGHT_LEVEL_SHIFT 8 |
| #define AVIVO_DVOA_BIT_DEPTH_CONTROL 0x7988 |
| #define AVIVO_GPIO_0 0x7e30 |
| #define AVIVO_GPIO_1 0x7e40 |
| #define AVIVO_GPIO_2 0x7e50 |
| #define AVIVO_GPIO_3 0x7e60 |
| #define AVIVO_DC_GPIO_HPD_Y 0x7e9c |
| #define AVIVO_I2C_STATUS 0x7d30 |
| # define AVIVO_I2C_STATUS_DONE (1 << 0) |
| # define AVIVO_I2C_STATUS_NACK (1 << 1) |
| # define AVIVO_I2C_STATUS_HALT (1 << 2) |
| # define AVIVO_I2C_STATUS_GO (1 << 3) |
| # define AVIVO_I2C_STATUS_MASK 0x7 |
| /* If radeon_mm_i2c is to be believed, this is HALT, NACK, and maybe |
| * DONE? */ |
| # define AVIVO_I2C_STATUS_CMD_RESET 0x7 |
| # define AVIVO_I2C_STATUS_CMD_WAIT (1 << 3) |
| #define AVIVO_I2C_STOP 0x7d34 |
| #define AVIVO_I2C_START_CNTL 0x7d38 |
| # define AVIVO_I2C_START (1 << 8) |
| # define AVIVO_I2C_CONNECTOR0 (0 << 16) |
| # define AVIVO_I2C_CONNECTOR1 (1 << 16) |
| #define R520_I2C_START (1<<0) |
| #define R520_I2C_STOP (1<<1) |
| #define R520_I2C_RX (1<<2) |
| #define R520_I2C_EN (1<<8) |
| #define R520_I2C_DDC1 (0<<16) |
| #define R520_I2C_DDC2 (1<<16) |
| #define R520_I2C_DDC3 (2<<16) |
| #define R520_I2C_DDC_MASK (3<<16) |
| #define AVIVO_I2C_CONTROL2 0x7d3c |
| # define AVIVO_I2C_7D3C_SIZE_SHIFT 8 |
| # define AVIVO_I2C_7D3C_SIZE_MASK (0xf << 8) |
| #define AVIVO_I2C_CONTROL3 0x7d40 |
| /* Reading is done 4 bytes at a time: read the bottom 8 bits from |
| * 7d44, four times in a row. |
| * Writing is a little more complex. First write DATA with |
| * 0xnnnnnnzz, then 0xnnnnnnyy, where nnnnnn is some non-deterministic |
| * magic number, zz is, I think, the slave address, and yy is the byte |
| * you want to write. */ |
| #define AVIVO_I2C_DATA 0x7d44 |
| #define R520_I2C_ADDR_COUNT_MASK (0x7) |
| #define R520_I2C_DATA_COUNT_SHIFT (8) |
| #define R520_I2C_DATA_COUNT_MASK (0xF00) |
| #define AVIVO_I2C_CNTL 0x7d50 |
| # define AVIVO_I2C_EN (1 << 0) |
| # define AVIVO_I2C_RESET (1 << 8) |
| #define R600_GENERAL_PWRMGT 0x618 |
| # define R600_OPEN_DRAIN_PADS (1 << 11) |
| #define R600_LOWER_GPIO_ENABLE 0x710 |
| #define R600_CTXSW_VID_LOWER_GPIO_CNTL 0x718 |
| #define R600_HIGH_VID_LOWER_GPIO_CNTL 0x71c |
| #define R600_MEDIUM_VID_LOWER_GPIO_CNTL 0x720 |
| #define R600_LOW_VID_LOWER_GPIO_CNTL 0x724 |
| #define R600_MC_VM_FB_LOCATION 0x2180 |
| #define R600_MC_VM_AGP_TOP 0x2184 |
| #define R600_MC_VM_AGP_BOT 0x2188 |
| #define R600_MC_VM_AGP_BASE 0x218c |
| #define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190 |
| #define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194 |
| #define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198 |
| #define R700_MC_VM_FB_LOCATION 0x2024 |
| #define R600_HDP_NONSURFACE_BASE 0x2c04 |
| #define R600_BUS_CNTL 0x5420 |
| #define R600_CONFIG_CNTL 0x5424 |
| #define R600_CONFIG_MEMSIZE 0x5428 |
| #define R600_CONFIG_F0_BASE 0x542C |
| #define R600_CONFIG_APER_SIZE 0x5430 |
| #define R600_ROM_CNTL 0x1600 |
| # define R600_SCK_OVERWRITE (1 << 1) |
| # define R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT 28 |
| # define R600_SCK_PRESCALE_CRYSTAL_CLK_MASK (0xf << 28) |
| #define R600_BIOS_0_SCRATCH 0x1724 |
| #define R600_BIOS_1_SCRATCH 0x1728 |
| #define R600_BIOS_2_SCRATCH 0x172c |
| #define R600_BIOS_3_SCRATCH 0x1730 |
| #define R600_BIOS_4_SCRATCH 0x1734 |
| #define R600_BIOS_5_SCRATCH 0x1738 |
| #define R600_BIOS_6_SCRATCH 0x173c |
| #define R600_BIOS_7_SCRATCH 0x1740 |
| #define R300_GB_TILE_CONFIG 0x4018 |
| # define R300_ENABLE_TILING (1 << 0) |
| # define R300_PIPE_COUNT_RV350 (0 << 1) |
| # define R300_PIPE_COUNT_R300 (3 << 1) |
| # define R300_PIPE_COUNT_R420_3P (6 << 1) |
| # define R300_PIPE_COUNT_R420 (7 << 1) |
| # define R300_TILE_SIZE_8 (0 << 4) |
| # define R300_TILE_SIZE_16 (1 << 4) |
| # define R300_TILE_SIZE_32 (2 << 4) |
| # define R300_SUBPIXEL_1_12 (0 << 16) |
| # define R300_SUBPIXEL_1_16 (1 << 16) |
| #define R300_GB_SELECT 0x401c |
| #define R300_GB_ENABLE 0x4008 |
| #define R300_GB_AA_CONFIG 0x4020 |
| #define R400_GB_PIPE_SELECT 0x402c |
| #define R300_GB_MSPOS0 0x4010 |
| # define R300_MS_X0_SHIFT 0 |
| # define R300_MS_Y0_SHIFT 4 |
| # define R300_MS_X1_SHIFT 8 |
| # define R300_MS_Y1_SHIFT 12 |
| # define R300_MS_X2_SHIFT 16 |
| # define R300_MS_Y2_SHIFT 20 |
| # define R300_MSBD0_Y_SHIFT 24 |
| # define R300_MSBD0_X_SHIFT 28 |
| #define R300_GB_MSPOS1 0x4014 |
| # define R300_MS_X3_SHIFT 0 |
| # define R300_MS_Y3_SHIFT 4 |
| # define R300_MS_X4_SHIFT 8 |
| # define R300_MS_Y4_SHIFT 12 |
| # define R300_MS_X5_SHIFT 16 |
| # define R300_MS_Y5_SHIFT 20 |
| # define R300_MSBD1_SHIFT 24 |
| #define R300_GA_ENHANCE 0x4274 |
| # define R300_GA_DEADLOCK_CNTL (1 << 0) |
| # define R300_GA_FASTSYNC_CNTL (1 << 1) |
| #define R300_GA_POLY_MODE 0x4288 |
| # define R300_FRONT_PTYPE_POINT (0 << 4) |
| # define R300_FRONT_PTYPE_LINE (1 << 4) |
| # define R300_FRONT_PTYPE_TRIANGE (2 << 4) |
| # define R300_BACK_PTYPE_POINT (0 << 7) |
| # define R300_BACK_PTYPE_LINE (1 << 7) |
| # define R300_BACK_PTYPE_TRIANGE (2 << 7) |
| #define R300_GA_ROUND_MODE 0x428c |
| # define R300_GEOMETRY_ROUND_TRUNC (0 << 0) |
| # define R300_GEOMETRY_ROUND_NEAREST (1 << 0) |
| # define R300_COLOR_ROUND_TRUNC (0 << 2) |
| # define R300_COLOR_ROUND_NEAREST (1 << 2) |
| #define R300_GA_COLOR_CONTROL 0x4278 |
| # define R300_RGB0_SHADING_SOLID (0 << 0) |
| # define R300_RGB0_SHADING_FLAT (1 << 0) |
| # define R300_RGB0_SHADING_GOURAUD (2 << 0) |
| # define R300_ALPHA0_SHADING_SOLID (0 << 2) |
| # define R300_ALPHA0_SHADING_FLAT (1 << 2) |
| # define R300_ALPHA0_SHADING_GOURAUD (2 << 2) |
| # define R300_RGB1_SHADING_SOLID (0 << 4) |
| # define R300_RGB1_SHADING_FLAT (1 << 4) |
| # define R300_RGB1_SHADING_GOURAUD (2 << 4) |
| # define R300_ALPHA1_SHADING_SOLID (0 << 6) |
| # define R300_ALPHA1_SHADING_FLAT (1 << 6) |
| # define R300_ALPHA1_SHADING_GOURAUD (2 << 6) |
| # define R300_RGB2_SHADING_SOLID (0 << 8) |
| # define R300_RGB2_SHADING_FLAT (1 << 8) |
| # define R300_RGB2_SHADING_GOURAUD (2 << 8) |
| # define R300_ALPHA2_SHADING_SOLID (0 << 10) |
| # define R300_ALPHA2_SHADING_FLAT (1 << 10) |
| # define R300_ALPHA2_SHADING_GOURAUD (2 << 10) |
| # define R300_RGB3_SHADING_SOLID (0 << 12) |
| # define R300_RGB3_SHADING_FLAT (1 << 12) |
| # define R300_RGB3_SHADING_GOURAUD (2 << 12) |
| # define R300_ALPHA3_SHADING_SOLID (0 << 14) |
| # define R300_ALPHA3_SHADING_FLAT (1 << 14) |
| # define R300_ALPHA3_SHADING_GOURAUD (2 << 14) |
| #define R300_GA_OFFSET 0x4290 |
| #define R500_SU_REG_DEST 0x42c8 |
| #define R300_VAP_CNTL_STATUS 0x2140 |
| # define R300_PVS_BYPASS (1 << 8) |
| #define R300_VAP_PVS_STATE_FLUSH_REG 0x2284 |
| #define R300_VAP_CNTL 0x2080 |
| # define R300_PVS_NUM_SLOTS_SHIFT 0 |
| # define R300_PVS_NUM_CNTLRS_SHIFT 4 |
| # define R300_PVS_NUM_FPUS_SHIFT 8 |
| # define R300_VF_MAX_VTX_NUM_SHIFT 18 |
| # define R300_GL_CLIP_SPACE_DEF (0 << 22) |
| # define R300_DX_CLIP_SPACE_DEF (1 << 22) |
| # define R500_TCL_STATE_OPTIMIZATION (1 << 23) |
| #define R300_VAP_VTE_CNTL 0x20B0 |
| # define R300_VPORT_X_SCALE_ENA (1 << 0) |
| # define R300_VPORT_X_OFFSET_ENA (1 << 1) |
| # define R300_VPORT_Y_SCALE_ENA (1 << 2) |
| # define R300_VPORT_Y_OFFSET_ENA (1 << 3) |
| # define R300_VPORT_Z_SCALE_ENA (1 << 4) |
| # define R300_VPORT_Z_OFFSET_ENA (1 << 5) |
| # define R300_VTX_XY_FMT (1 << 8) |
| # define R300_VTX_Z_FMT (1 << 9) |
| # define R300_VTX_W0_FMT (1 << 10) |
| #define R300_VAP_VTX_STATE_CNTL 0x2180 |
| #define R300_VAP_PSC_SGN_NORM_CNTL 0x21DC |
| #define R300_VAP_PROG_STREAM_CNTL_0 0x2150 |
| # define R300_DATA_TYPE_0_SHIFT 0 |
| # define R300_DATA_TYPE_FLOAT_1 0 |
| # define R300_DATA_TYPE_FLOAT_2 1 |
| # define R300_DATA_TYPE_FLOAT_3 2 |
| # define R300_DATA_TYPE_FLOAT_4 3 |
| # define R300_DATA_TYPE_BYTE 4 |
| # define R300_DATA_TYPE_D3DCOLOR 5 |
| # define R300_DATA_TYPE_SHORT_2 6 |
| # define R300_DATA_TYPE_SHORT_4 7 |
| # define R300_DATA_TYPE_VECTOR_3_TTT 8 |
| # define R300_DATA_TYPE_VECTOR_3_EET 9 |
| # define R300_SKIP_DWORDS_0_SHIFT 4 |
| # define R300_DST_VEC_LOC_0_SHIFT 8 |
| # define R300_LAST_VEC_0 (1 << 13) |
| # define R300_SIGNED_0 (1 << 14) |
| # define R300_NORMALIZE_0 (1 << 15) |
| # define R300_DATA_TYPE_1_SHIFT 16 |
| # define R300_SKIP_DWORDS_1_SHIFT 20 |
| # define R300_DST_VEC_LOC_1_SHIFT 24 |
| # define R300_LAST_VEC_1 (1 << 29) |
| # define R300_SIGNED_1 (1 << 30) |
| # define R300_NORMALIZE_1 (1 << 31) |
| #define R300_VAP_PROG_STREAM_CNTL_1 0x2154 |
| # define R300_DATA_TYPE_2_SHIFT 0 |
| # define R300_SKIP_DWORDS_2_SHIFT 4 |
| # define R300_DST_VEC_LOC_2_SHIFT 8 |
| # define R300_LAST_VEC_2 (1 << 13) |
| # define R300_SIGNED_2 (1 << 14) |
| # define R300_NORMALIZE_2 (1 << 15) |
| # define R300_DATA_TYPE_3_SHIFT 16 |
| # define R300_SKIP_DWORDS_3_SHIFT 20 |
| # define R300_DST_VEC_LOC_3_SHIFT 24 |
| # define R300_LAST_VEC_3 (1 << 29) |
| # define R300_SIGNED_3 (1 << 30) |
| # define R300_NORMALIZE_3 (1 << 31) |
| #define R300_VAP_PROG_STREAM_CNTL_EXT_0 0x21e0 |
| # define R300_SWIZZLE_SELECT_X_0_SHIFT 0 |
| # define R300_SWIZZLE_SELECT_Y_0_SHIFT 3 |
| # define R300_SWIZZLE_SELECT_Z_0_SHIFT 6 |
| # define R300_SWIZZLE_SELECT_W_0_SHIFT 9 |
| # define R300_SWIZZLE_SELECT_X 0 |
| # define R300_SWIZZLE_SELECT_Y 1 |
| # define R300_SWIZZLE_SELECT_Z 2 |
| # define R300_SWIZZLE_SELECT_W 3 |
| # define R300_SWIZZLE_SELECT_FP_ZERO 4 |
| # define R300_SWIZZLE_SELECT_FP_ONE 5 |
| # define R300_WRITE_ENA_0_SHIFT 12 |
| # define R300_WRITE_ENA_X 1 |
| # define R300_WRITE_ENA_Y 2 |
| # define R300_WRITE_ENA_Z 4 |
| # define R300_WRITE_ENA_W 8 |
| # define R300_SWIZZLE_SELECT_X_1_SHIFT 16 |
| # define R300_SWIZZLE_SELECT_Y_1_SHIFT 19 |
| # define R300_SWIZZLE_SELECT_Z_1_SHIFT 22 |
| # define R300_SWIZZLE_SELECT_W_1_SHIFT 25 |
| # define R300_WRITE_ENA_1_SHIFT 28 |
| #define R300_VAP_PROG_STREAM_CNTL_EXT_1 0x21e4 |
| # define R300_SWIZZLE_SELECT_X_2_SHIFT 0 |
| # define R300_SWIZZLE_SELECT_Y_2_SHIFT 3 |
| # define R300_SWIZZLE_SELECT_Z_2_SHIFT 6 |
| # define R300_SWIZZLE_SELECT_W_2_SHIFT 9 |
| # define R300_WRITE_ENA_2_SHIFT 12 |
| # define R300_SWIZZLE_SELECT_X_3_SHIFT 16 |
| # define R300_SWIZZLE_SELECT_Y_3_SHIFT 19 |
| # define R300_SWIZZLE_SELECT_Z_3_SHIFT 22 |
| # define R300_SWIZZLE_SELECT_W_3_SHIFT 25 |
| # define R300_WRITE_ENA_3_SHIFT 28 |
| #define R300_VAP_PVS_CODE_CNTL_0 0x22D0 |
| # define R300_PVS_FIRST_INST_SHIFT 0 |
| # define R300_PVS_XYZW_VALID_INST_SHIFT 10 |
| # define R300_PVS_LAST_INST_SHIFT 20 |
| #define R300_VAP_PVS_CODE_CNTL_1 0x22D8 |
| # define R300_PVS_LAST_VTX_SRC_INST_SHIFT 0 |
| #define R300_VAP_PVS_VECTOR_INDX_REG 0x2200 |
| #define R300_VAP_PVS_VECTOR_DATA_REG 0x2204 |
| /* PVS instructions */ |
| /* Opcode and dst instruction */ |
| #define R300_PVS_DST_OPCODE(x) (x << 0) |
| /* Vector ops */ |
| # define R300_VECTOR_NO_OP 0 |
| # define R300_VE_DOT_PRODUCT 1 |
| # define R300_VE_MULTIPLY 2 |
| # define R300_VE_ADD 3 |
| # define R300_VE_MULTIPLY_ADD 4 |
| # define R300_VE_DISTANCE_VECTOR 5 |
| # define R300_VE_FRACTION 6 |
| # define R300_VE_MAXIMUM 7 |
| # define R300_VE_MINIMUM 8 |
| # define R300_VE_SET_GREATER_THAN_EQUAL 9 |
| # define R300_VE_SET_LESS_THAN 10 |
| # define R300_VE_MULTIPLYX2_ADD 11 |
| # define R300_VE_MULTIPLY_CLAMP 12 |
| # define R300_VE_FLT2FIX_DX 13 |
| # define R300_VE_FLT2FIX_DX_RND 14 |
| /* R500 additions */ |
| # define R500_VE_PRED_SET_EQ_PUSH 15 |
| # define R500_VE_PRED_SET_GT_PUSH 16 |
| # define R500_VE_PRED_SET_GTE_PUSH 17 |
| # define R500_VE_PRED_SET_NEQ_PUSH 18 |
| # define R500_VE_COND_WRITE_EQ 19 |
| # define R500_VE_COND_WRITE_GT 20 |
| # define R500_VE_COND_WRITE_GTE 21 |
| # define R500_VE_COND_WRITE_NEQ 22 |
| # define R500_VE_COND_MUX_EQ 23 |
| # define R500_VE_COND_MUX_GT 24 |
| # define R500_VE_COND_MUX_GTE 25 |
| # define R500_VE_SET_GREATER_THAN 26 |
| # define R500_VE_SET_EQUAL 27 |
| # define R500_VE_SET_NOT_EQUAL 28 |
| /* Math ops */ |
| # define R300_MATH_NO_OP 0 |
| # define R300_ME_EXP_BASE2_DX 1 |
| # define R300_ME_LOG_BASE2_DX 2 |
| # define R300_ME_EXP_BASEE_FF 3 |
| # define R300_ME_LIGHT_COEFF_DX 4 |
| # define R300_ME_POWER_FUNC_FF 5 |
| # define R300_ME_RECIP_DX 6 |
| # define R300_ME_RECIP_FF 7 |
| # define R300_ME_RECIP_SQRT_DX 8 |
| # define R300_ME_RECIP_SQRT_FF 9 |
| # define R300_ME_MULTIPLY 10 |
| # define R300_ME_EXP_BASE2_FULL_DX 11 |
| # define R300_ME_LOG_BASE2_FULL_DX 12 |
| # define R300_ME_POWER_FUNC_FF_CLAMP_B 13 |
| # define R300_ME_POWER_FUNC_FF_CLAMP_B1 14 |
| # define R300_ME_POWER_FUNC_FF_CLAMP_01 15 |
| # define R300_ME_SIN 16 |
| # define R300_ME_COS 17 |
| /* R500 additions */ |
| # define R500_ME_LOG_BASE2_IEEE 18 |
| # define R500_ME_RECIP_IEEE 19 |
| # define R500_ME_RECIP_SQRT_IEEE 20 |
| # define R500_ME_PRED_SET_EQ 21 |
| # define R500_ME_PRED_SET_GT 22 |
| # define R500_ME_PRED_SET_GTE 23 |
| # define R500_ME_PRED_SET_NEQ 24 |
| # define R500_ME_PRED_SET_CLR 25 |
| # define R500_ME_PRED_SET_INV 26 |
| # define R500_ME_PRED_SET_POP 27 |
| # define R500_ME_PRED_SET_RESTORE 28 |
| /* macro */ |
| # define R300_PVS_MACRO_OP_2CLK_MADD 0 |
| # define R300_PVS_MACRO_OP_2CLK_M2X_ADD 1 |
| #define R300_PVS_DST_MATH_INST (1 << 6) |
| #define R300_PVS_DST_MACRO_INST (1 << 7) |
| #define R300_PVS_DST_REG_TYPE(x) (x << 8) |
| # define R300_PVS_DST_REG_TEMPORARY 0 |
| # define R300_PVS_DST_REG_A0 1 |
| # define R300_PVS_DST_REG_OUT 2 |
| # define R500_PVS_DST_REG_OUT_REPL_X 3 |
| # define R300_PVS_DST_REG_ALT_TEMPORARY 4 |
| # define R300_PVS_DST_REG_INPUT 5 |
| #define R300_PVS_DST_ADDR_MODE_1 (1 << 12) |
| #define R300_PVS_DST_OFFSET(x) (x << 13) |
| #define R300_PVS_DST_WE_X (1 << 20) |
| #define R300_PVS_DST_WE_Y (1 << 21) |
| #define R300_PVS_DST_WE_Z (1 << 22) |
| #define R300_PVS_DST_WE_W (1 << 23) |
| #define R300_PVS_DST_VE_SAT (1 << 24) |
| #define R300_PVS_DST_ME_SAT (1 << 25) |
| #define R300_PVS_DST_PRED_ENABLE (1 << 26) |
| #define R300_PVS_DST_PRED_SENSE (1 << 27) |
| #define R300_PVS_DST_DUAL_MATH_OP (1 << 28) |
| #define R300_PVS_DST_ADDR_SEL(x) (x << 29) |
| #define R300_PVS_DST_ADDR_MODE_0 (1 << 31) |
| /* src operand instruction */ |
| #define R300_PVS_SRC_REG_TYPE(x) (x << 0) |
| # define R300_PVS_SRC_REG_TEMPORARY 0 |
| # define R300_PVS_SRC_REG_INPUT 1 |
| # define R300_PVS_SRC_REG_CONSTANT 2 |
| # define R300_PVS_SRC_REG_ALT_TEMPORARY 3 |
| #define R300_SPARE_0 (1 << 2) |
| #define R300_PVS_SRC_ABS_XYZW (1 << 3) |
| #define R300_PVS_SRC_ADDR_MODE_0 (1 << 4) |
| #define R300_PVS_SRC_OFFSET(x) (x << 5) |
| #define R300_PVS_SRC_SWIZZLE_X(x) (x << 13) |
| #define R300_PVS_SRC_SWIZZLE_Y(x) (x << 16) |
| #define R300_PVS_SRC_SWIZZLE_Z(x) (x << 19) |
| #define R300_PVS_SRC_SWIZZLE_W(x) (x << 22) |
| # define R300_PVS_SRC_SELECT_X 0 |
| # define R300_PVS_SRC_SELECT_Y 1 |
| # define R300_PVS_SRC_SELECT_Z 2 |
| # define R300_PVS_SRC_SELECT_W 3 |
| # define R300_PVS_SRC_SELECT_FORCE_0 4 |
| # define R300_PVS_SRC_SELECT_FORCE_1 5 |
| #define R300_PVS_SRC_NEG_X (1 << 25) |
| #define R300_PVS_SRC_NEG_Y (1 << 26) |
| #define R300_PVS_SRC_NEG_Z (1 << 27) |
| #define R300_PVS_SRC_NEG_W (1 << 28) |
| #define R300_PVS_SRC_ADDR_SEL(x) (x << 29) |
| #define R300_PVS_SRC_ADDR_MODE_1 (1 << 31) |
| #define R300_VAP_PVS_FLOW_CNTL_OPC 0x22dc |
| #define R300_VAP_OUT_VTX_FMT_0 0x2090 |
| # define R300_VTX_POS_PRESENT (1 << 0) |
| # define R300_VTX_COLOR_0_PRESENT (1 << 1) |
| # define R300_VTX_COLOR_1_PRESENT (1 << 2) |
| # define R300_VTX_COLOR_2_PRESENT (1 << 3) |
| # define R300_VTX_COLOR_3_PRESENT (1 << 4) |
| # define R300_VTX_PT_SIZE_PRESENT (1 << 16) |
| #define R300_VAP_OUT_VTX_FMT_1 0x2094 |
| # define R300_TEX_0_COMP_CNT_SHIFT 0 |
| # define R300_TEX_1_COMP_CNT_SHIFT 3 |
| # define R300_TEX_2_COMP_CNT_SHIFT 6 |
| # define R300_TEX_3_COMP_CNT_SHIFT 9 |
| # define R300_TEX_4_COMP_CNT_SHIFT 12 |
| # define R300_TEX_5_COMP_CNT_SHIFT 15 |
| # define R300_TEX_6_COMP_CNT_SHIFT 18 |
| # define R300_TEX_7_COMP_CNT_SHIFT 21 |
| #define R300_VAP_VTX_SIZE 0x20b4 |
| #define R300_VAP_GB_VERT_CLIP_ADJ 0x2220 |
| #define R300_VAP_GB_VERT_DISC_ADJ 0x2224 |
| #define R300_VAP_GB_HORZ_CLIP_ADJ 0x2228 |
| #define R300_VAP_GB_HORZ_DISC_ADJ 0x222c |
| #define R300_VAP_CLIP_CNTL 0x221c |
| # define R300_UCP_ENA_0 (1 << 0) |
| # define R300_UCP_ENA_1 (1 << 1) |
| # define R300_UCP_ENA_2 (1 << 2) |
| # define R300_UCP_ENA_3 (1 << 3) |
| # define R300_UCP_ENA_4 (1 << 4) |
| # define R300_UCP_ENA_5 (1 << 5) |
| # define R300_PS_UCP_MODE_SHIFT 14 |
| # define R300_CLIP_DISABLE (1 << 16) |
| # define R300_UCP_CULL_ONLY_ENA (1 << 17) |
| # define R300_BOUNDARY_EDGE_FLAG_ENA (1 << 18) |
| #define R300_VAP_PVS_STATE_FLUSH_REG 0x2284 |
| #define R500_VAP_INDEX_OFFSET 0x208c |
| #define R300_SU_TEX_WRAP 0x42a0 |
| #define R300_SU_POLY_OFFSET_ENABLE 0x42b4 |
| #define R300_SU_CULL_MODE 0x42b8 |
| # define R300_CULL_FRONT (1 << 0) |
| # define R300_CULL_BACK (1 << 1) |
| # define R300_FACE_POS (0 << 2) |
| # define R300_FACE_NEG (1 << 2) |
| #define R300_SU_DEPTH_SCALE 0x42c0 |
| #define R300_SU_DEPTH_OFFSET 0x42c4 |
| #define R300_RS_COUNT 0x4300 |
| # define R300_RS_COUNT_IT_COUNT_SHIFT 0 |
| # define R300_RS_COUNT_IC_COUNT_SHIFT 7 |
| # define R300_RS_COUNT_HIRES_EN (1 << 18) |
| #define R300_RS_IP_0 0x4310 |
| #define R300_RS_IP_1 0x4314 |
| # define R300_RS_TEX_PTR(x) (x << 0) |
| # define R300_RS_COL_PTR(x) (x << 6) |
| # define R300_RS_COL_FMT(x) (x << 9) |
| # define R300_RS_COL_FMT_RGBA 0 |
| # define R300_RS_COL_FMT_RGB0 2 |
| # define R300_RS_COL_FMT_RGB1 3 |
| # define R300_RS_COL_FMT_000A 4 |
| # define R300_RS_COL_FMT_0000 5 |
| # define R300_RS_COL_FMT_0001 6 |
| # define R300_RS_COL_FMT_111A 8 |
| # define R300_RS_COL_FMT_1110 9 |
| # define R300_RS_COL_FMT_1111 10 |
| # define R300_RS_SEL_S(x) (x << 13) |
| # define R300_RS_SEL_T(x) (x << 16) |
| # define R300_RS_SEL_R(x) (x << 19) |
| # define R300_RS_SEL_Q(x) (x << 22) |
| # define R300_RS_SEL_C0 0 |
| # define R300_RS_SEL_C1 1 |
| # define R300_RS_SEL_C2 2 |
| # define R300_RS_SEL_C3 3 |
| # define R300_RS_SEL_K0 4 |
| # define R300_RS_SEL_K1 5 |
| #define R300_RS_INST_COUNT 0x4304 |
| # define R300_INST_COUNT_RS(x) (x << 0) |
| # define R300_RS_W_EN (1 << 4) |
| # define R300_TX_OFFSET_RS(x) (x << 5) |
| #define R300_RS_INST_0 0x4330 |
| #define R300_RS_INST_1 0x4334 |
| # define R300_INST_TEX_ID(x) (x << 0) |
| # define R300_RS_INST_TEX_CN_WRITE (1 << 3) |
| # define R300_INST_TEX_ADDR(x) (x << 6) |
| #define R300_TX_INVALTAGS 0x4100 |
| #define R300_TX_FILTER0_0 0x4400 |
| #define R300_TX_FILTER0_1 0x4404 |
| # define R300_TX_CLAMP_S(x) (x << 0) |
| # define R300_TX_CLAMP_T(x) (x << 3) |
| # define R300_TX_CLAMP_R(x) (x << 6) |
| # define R300_TX_CLAMP_WRAP 0 |
| # define R300_TX_CLAMP_MIRROR 1 |
| # define R300_TX_CLAMP_CLAMP_LAST 2 |
| # define R300_TX_CLAMP_MIRROR_CLAMP_LAST 3 |
| # define R300_TX_CLAMP_CLAMP_BORDER 4 |
| # define R300_TX_CLAMP_MIRROR_CLAMP_BORDER 5 |
| # define R300_TX_CLAMP_CLAMP_GL 6 |
| # define R300_TX_CLAMP_MIRROR_CLAMP_GL 7 |
| # define R300_TX_MAG_FILTER_NEAREST (1 << 9) |
| # define R300_TX_MIN_FILTER_NEAREST (1 << 11) |
| # define R300_TX_MAG_FILTER_LINEAR (2 << 9) |
| # define R300_TX_MIN_FILTER_LINEAR (2 << 11) |
| # define R300_TX_ID_SHIFT 28 |
| #define R300_TX_FILTER1_0 0x4440 |
| #define R300_TX_FILTER1_1 0x4444 |
| #define R300_TX_FORMAT0_0 0x4480 |
| #define R300_TX_FORMAT0_1 0x4484 |
| # define R300_TXWIDTH_SHIFT 0 |
| # define R300_TXHEIGHT_SHIFT 11 |
| # define R300_NUM_LEVELS_SHIFT 26 |
| # define R300_NUM_LEVELS_MASK 0x |
| # define R300_TXPROJECTED (1 << 30) |
| # define R300_TXPITCH_EN (1 << 31) |
| #define R300_TX_FORMAT1_0 0x44c0 |
| #define R300_TX_FORMAT1_1 0x44c4 |
| # define R300_TX_FORMAT_X8 0x0 |
| # define R300_TX_FORMAT_X16 0x1 |
| # define R300_TX_FORMAT_Y4X4 0x2 |
| # define R300_TX_FORMAT_Y8X8 0x3 |
| # define R300_TX_FORMAT_Y16X16 0x4 |
| # define R300_TX_FORMAT_Z3Y3X2 0x5 |
| # define R300_TX_FORMAT_Z5Y6X5 0x6 |
| # define R300_TX_FORMAT_Z6Y5X5 0x7 |
| # define R300_TX_FORMAT_Z11Y11X10 0x8 |
| # define R300_TX_FORMAT_Z10Y11X11 0x9 |
| # define R300_TX_FORMAT_W4Z4Y4X4 0xA |
| # define R300_TX_FORMAT_W1Z5Y5X5 0xB |
| # define R300_TX_FORMAT_W8Z8Y8X8 0xC |
| # define R300_TX_FORMAT_W2Z10Y10X10 0xD |
| # define R300_TX_FORMAT_W16Z16Y16X16 0xE |
| # define R300_TX_FORMAT_DXT1 0xF |
| # define R300_TX_FORMAT_DXT3 0x10 |
| # define R300_TX_FORMAT_DXT5 0x11 |
| # define R300_TX_FORMAT_D3DMFT_CxV8U8 0x12 /* no swizzle */ |
| # define R300_TX_FORMAT_A8R8G8B8 0x13 /* no swizzle */ |
| # define R300_TX_FORMAT_B8G8_B8G8 0x14 /* no swizzle */ |
| # define R300_TX_FORMAT_G8R8_G8B8 0x15 /* no swizzle */ |
| # define R300_TX_FORMAT_VYUY422 0x14 /* no swizzle */ |
| # define R300_TX_FORMAT_YVYU422 0x15 /* no swizzle */ |
| # define R300_TX_FORMAT_X24_Y8 0x1e |
| # define R300_TX_FORMAT_X32 0x1e |
| /* Floating point formats */ |
| /* Note - hardware supports both 16 and 32 bit floating point */ |
| # define R300_TX_FORMAT_FL_I16 0x18 |
| # define R300_TX_FORMAT_FL_I16A16 0x19 |
| # define R300_TX_FORMAT_FL_R16G16B16A16 0x1A |
| # define R300_TX_FORMAT_FL_I32 0x1B |
| # define R300_TX_FORMAT_FL_I32A32 0x1C |
| # define R300_TX_FORMAT_FL_R32G32B32A32 0x1D |
| /* alpha modes, convenience mostly */ |
| /* if you have alpha, pick constant appropriate to the |
| number of channels (1 for I8, 2 for I8A8, 4 for R8G8B8A8, etc */ |
| # define R300_TX_FORMAT_ALPHA_1CH 0x000 |
| # define R300_TX_FORMAT_ALPHA_2CH 0x200 |
| # define R300_TX_FORMAT_ALPHA_4CH 0x600 |
| # define R300_TX_FORMAT_ALPHA_NONE 0xA00 |
| /* Swizzling */ |
| /* constants */ |
| # define R300_TX_FORMAT_X 0 |
| # define R300_TX_FORMAT_Y 1 |
| # define R300_TX_FORMAT_Z 2 |
| # define R300_TX_FORMAT_W 3 |
| # define R300_TX_FORMAT_ZERO 4 |
| # define R300_TX_FORMAT_ONE 5 |
| /* 2.0*Z, everything above 1.0 is set to 0.0 */ |
| # define R300_TX_FORMAT_CUT_Z 6 |
| /* 2.0*W, everything above 1.0 is set to 0.0 */ |
| # define R300_TX_FORMAT_CUT_W 7 |
| # define R300_TX_FORMAT_B_SHIFT 18 |
| # define R300_TX_FORMAT_G_SHIFT 15 |
| # define R300_TX_FORMAT_R_SHIFT 12 |
| # define R300_TX_FORMAT_A_SHIFT 9 |
| /* Convenience macro to take care of layout and swizzling */ |
| # define R300_EASY_TX_FORMAT(B, G, R, A, FMT) ( \ |
| ((R300_TX_FORMAT_##B)<<R300_TX_FORMAT_B_SHIFT) \ |
| | ((R300_TX_FORMAT_##G)<<R300_TX_FORMAT_G_SHIFT) \ |
| | ((R300_TX_FORMAT_##R)<<R300_TX_FORMAT_R_SHIFT) \ |
| | ((R300_TX_FORMAT_##A)<<R300_TX_FORMAT_A_SHIFT) \ |
| | (R300_TX_FORMAT_##FMT) \ |
| ) |
| # define R300_TX_FORMAT_YUV_TO_RGB_CLAMP (1 << 22) |
| # define R300_TX_FORMAT_YUV_TO_RGB_NO_CLAMP (2 << 22) |
| # define R300_TX_FORMAT_SWAP_YUV (1 << 24) |
| #define R300_TX_FORMAT2_0 0x4500 |
| #define R300_TX_FORMAT2_1 0x4504 |
| # define R500_TXWIDTH_11 (1 << 15) |
| # define R500_TXHEIGHT_11 (1 << 16) |
| #define R300_TX_OFFSET_0 0x4540 |
| #define R300_TX_OFFSET_1 0x4544 |
| # define R300_ENDIAN_SWAP_16_BIT (1 << 0) |
| # define R300_ENDIAN_SWAP_32_BIT (2 << 0) |
| # define R300_ENDIAN_SWAP_HALF_DWORD (3 << 0) |
| # define R300_MACRO_TILE (1 << 2) |
| #define R300_TX_BORDER_COLOR_0 0x45c0 |
| #define R300_TX_ENABLE 0x4104 |
| # define R300_TEX_0_ENABLE (1 << 0) |
| # define R300_TEX_1_ENABLE (1 << 1) |
| #define R300_US_W_FMT 0x46b4 |
| #define R300_US_OUT_FMT_1 0x46a8 |
| #define R300_US_OUT_FMT_2 0x46ac |
| #define R300_US_OUT_FMT_3 0x46b0 |
| #define R300_US_OUT_FMT_0 0x46a4 |
| # define R300_OUT_FMT_C4_8 (0 << 0) |
| # define R300_OUT_FMT_C4_10 (1 << 0) |
| # define R300_OUT_FMT_C4_10_GAMMA (2 << 0) |
| # define R300_OUT_FMT_C_16 (3 << 0) |
| # define R300_OUT_FMT_C2_16 (4 << 0) |
| # define R300_OUT_FMT_C4_16 (5 << 0) |
| # define R300_OUT_FMT_C_16_MPEG (6 << 0) |
| # define R300_OUT_FMT_C2_16_MPEG (7 << 0) |
| # define R300_OUT_FMT_C2_4 (8 << 0) |
| # define R300_OUT_FMT_C_3_3_2 (9 << 0) |
| # define R300_OUT_FMT_C_5_6_5 (10 << 0) |
| # define R300_OUT_FMT_C_11_11_10 (11 << 0) |
| # define R300_OUT_FMT_C_10_11_11 (12 << 0) |
| # define R300_OUT_FMT_C_2_10_10_10 (13 << 0) |
| # define R300_OUT_FMT_UNUSED (15 << 0) |
| # define R300_OUT_FMT_C_16_FP (16 << 0) |
| # define R300_OUT_FMT_C2_16_FP (17 << 0) |
| # define R300_OUT_FMT_C4_16_FP (18 << 0) |
| # define R300_OUT_FMT_C_32_FP (19 << 0) |
| # define R300_OUT_FMT_C2_32_FP (20 << 0) |
| # define R300_OUT_FMT_C4_32_FP (21 << 0) |
| # define R300_OUT_FMT_C0_SEL_ALPHA (0 << 8) |
| # define R300_OUT_FMT_C0_SEL_RED (1 << 8) |
| # define R300_OUT_FMT_C0_SEL_GREEN (2 << 8) |
| # define R300_OUT_FMT_C0_SEL_BLUE (3 << 8) |
| # define R300_OUT_FMT_C1_SEL_ALPHA (0 << 10) |
| # define R300_OUT_FMT_C1_SEL_RED (1 << 10) |
| # define R300_OUT_FMT_C1_SEL_GREEN (2 << 10) |
| # define R300_OUT_FMT_C1_SEL_BLUE (3 << 10) |
| # define R300_OUT_FMT_C2_SEL_ALPHA (0 << 12) |
| # define R300_OUT_FMT_C2_SEL_RED (1 << 12) |
| # define R300_OUT_FMT_C2_SEL_GREEN (2 << 12) |
| # define R300_OUT_FMT_C2_SEL_BLUE (3 << 12) |
| # define R300_OUT_FMT_C3_SEL_ALPHA (0 << 14) |
| # define R300_OUT_FMT_C3_SEL_RED (1 << 14) |
| # define R300_OUT_FMT_C3_SEL_GREEN (2 << 14) |
| # define R300_OUT_FMT_C3_SEL_BLUE (3 << 14) |
| #define R300_US_CONFIG 0x4600 |
| # define R300_NLEVEL_SHIFT 0 |
| # define R300_FIRST_TEX (1 << 3) |
| # define R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO (1 << 1) |
| #define R300_US_PIXSIZE 0x4604 |
| #define R300_US_CODE_OFFSET 0x4608 |
| # define R300_ALU_CODE_OFFSET(x) (x << 0) |
| # define R300_ALU_CODE_SIZE(x) (x << 6) |
| # define R300_TEX_CODE_OFFSET(x) (x << 13) |
| # define R300_TEX_CODE_SIZE(x) (x << 18) |
| #define R300_US_CODE_ADDR_0 0x4610 |
| # define R300_ALU_START(x) (x << 0) |
| # define R300_ALU_SIZE(x) (x << 6) |
| # define R300_TEX_START(x) (x << 12) |
| # define R300_TEX_SIZE(x) (x << 17) |
| # define R300_RGBA_OUT (1 << 22) |
| # define R300_W_OUT (1 << 23) |
| #define R300_US_CODE_ADDR_1 0x4614 |
| #define R300_US_CODE_ADDR_2 0x4618 |
| #define R300_US_CODE_ADDR_3 0x461c |
| #define R300_US_TEX_INST_0 0x4620 |
| #define R300_US_TEX_INST_1 0x4624 |
| #define R300_US_TEX_INST_2 0x4628 |
| #define R300_US_TEX_INST(x) (R300_US_TEX_INST_0 + (x)*4) |
| # define R300_TEX_SRC_ADDR(x) (x << 0) |
| # define R300_TEX_DST_ADDR(x) (x << 6) |
| # define R300_TEX_ID(x) (x << 11) |
| # define R300_TEX_INST(x) (x << 15) |
| # define R300_TEX_INST_NOP 0 |
| # define R300_TEX_INST_LD 1 |
| # define R300_TEX_INST_TEXKILL 2 |
| # define R300_TEX_INST_PROJ 3 |
| # define R300_TEX_INST_LODBIAS 4 |
| #define R300_US_ALU_RGB_ADDR_0 0x46c0 |
| #define R300_US_ALU_RGB_ADDR_1 0x46c4 |
| #define R300_US_ALU_RGB_ADDR_2 0x46c8 |
| #define R300_US_ALU_RGB_ADDR(x) (R300_US_ALU_RGB_ADDR_0 + (x)*4) |
| /* for ADDR0-2, values 0-31 specify a location in the pixel stack, |
| values 32-63 specify a constant */ |
| # define R300_ALU_RGB_ADDR0(x) (x << 0) |
| # define R300_ALU_RGB_ADDR1(x) (x << 6) |
| # define R300_ALU_RGB_ADDR2(x) (x << 12) |
| # define R300_ALU_RGB_CONST(x) ((x) | (1 << 5)) |
| /* ADDRD - where on the pixel stack the result of this instruction |
| will be written */ |
| # define R300_ALU_RGB_ADDRD(x) (x << 18) |
| # define R300_ALU_RGB_WMASK(x) (x << 23) |
| # define R300_ALU_RGB_OMASK(x) (x << 26) |
| # define R300_ALU_RGB_MASK_NONE 0 |
| # define R300_ALU_RGB_MASK_R 1 |
| # define R300_ALU_RGB_MASK_G 2 |
| # define R300_ALU_RGB_MASK_B 4 |
| # define R300_ALU_RGB_MASK_RGB 7 |
| # define R300_ALU_RGB_TARGET_A (0 << 29) |
| # define R300_ALU_RGB_TARGET_B (1 << 29) |
| # define R300_ALU_RGB_TARGET_C (2 << 29) |
| # define R300_ALU_RGB_TARGET_D (3 << 29) |
| #define R300_US_ALU_RGB_INST_0 0x48c0 |
| #define R300_US_ALU_RGB_INST_1 0x48c4 |
| #define R300_US_ALU_RGB_INST_2 0x48c8 |
| #define R300_US_ALU_RGB_INST(x) (R300_US_ALU_RGB_INST_0 + (x)*4) |
| # define R300_ALU_RGB_SEL_A(x) (x << 0) |
| # define R300_ALU_RGB_SRC0_RGB 0 |
| # define R300_ALU_RGB_SRC0_RRR 1 |
| # define R300_ALU_RGB_SRC0_GGG 2 |
| # define R300_ALU_RGB_SRC0_BBB 3 |
| # define R300_ALU_RGB_SRC1_RGB 4 |
| # define R300_ALU_RGB_SRC1_RRR 5 |
| # define R300_ALU_RGB_SRC1_GGG 6 |
| # define R300_ALU_RGB_SRC1_BBB 7 |
| # define R300_ALU_RGB_SRC2_RGB 8 |
| # define R300_ALU_RGB_SRC2_RRR 9 |
| # define R300_ALU_RGB_SRC2_GGG 10 |
| # define R300_ALU_RGB_SRC2_BBB 11 |
| # define R300_ALU_RGB_SRC0_AAA 12 |
| # define R300_ALU_RGB_SRC1_AAA 13 |
| # define R300_ALU_RGB_SRC2_AAA 14 |
| # define R300_ALU_RGB_SRCP_RGB 15 |
| # define R300_ALU_RGB_SRCP_RRR 16 |
| # define R300_ALU_RGB_SRCP_GGG 17 |
| # define R300_ALU_RGB_SRCP_BBB 18 |
| # define R300_ALU_RGB_SRCP_AAA 19 |
| # define R300_ALU_RGB_0_0 20 |
| # define R300_ALU_RGB_1_0 21 |
| # define R300_ALU_RGB_0_5 22 |
| # define R300_ALU_RGB_SRC0_GBR 23 |
| # define R300_ALU_RGB_SRC1_GBR 24 |
| # define R300_ALU_RGB_SRC2_GBR 25 |
| # define R300_ALU_RGB_SRC0_BRG 26 |
| # define R300_ALU_RGB_SRC1_BRG 27 |
| # define R300_ALU_RGB_SRC2_BRG 28 |
| # define R300_ALU_RGB_SRC0_ABG 29 |
| # define R300_ALU_RGB_SRC1_ABG 30 |
| # define R300_ALU_RGB_SRC2_ABG 31 |
| # define R300_ALU_RGB_MOD_A(x) (x << 5) |
| # define R300_ALU_RGB_MOD_NOP 0 |
| # define R300_ALU_RGB_MOD_NEG 1 |
| # define R300_ALU_RGB_MOD_ABS 2 |
| # define R300_ALU_RGB_MOD_NAB 3 |
| # define R300_ALU_RGB_SEL_B(x) (x << 7) |
| # define R300_ALU_RGB_MOD_B(x) (x << 12) |
| # define R300_ALU_RGB_SEL_C(x) (x << 14) |
| # define R300_ALU_RGB_MOD_C(x) (x << 19) |
| # define R300_ALU_RGB_SRCP_OP(x) (x << 21) |
| # define R300_ALU_RGB_SRCP_OP_1_MINUS_2RGB0 0 |
| # define R300_ALU_RGB_SRCP_OP_RGB1_MINUS_RGB0 1 |
| # define R300_ALU_RGB_SRCP_OP_RGB1_PLUS_RGB0 2 |
| # define R300_ALU_RGB_SRCP_OP_1_MINUS_RGB0 3 |
| # define R300_ALU_RGB_OP(x) (x << 23) |
| # define R300_ALU_RGB_OP_MAD 0 |
| # define R300_ALU_RGB_OP_DP3 1 |
| # define R300_ALU_RGB_OP_DP4 2 |
| # define R300_ALU_RGB_OP_D2A 3 |
| # define R300_ALU_RGB_OP_MIN 4 |
| # define R300_ALU_RGB_OP_MAX 5 |
| # define R300_ALU_RGB_OP_CND 7 |
| # define R300_ALU_RGB_OP_CMP 8 |
| # define R300_ALU_RGB_OP_FRC 9 |
| # define R300_ALU_RGB_OP_SOP 10 |
| # define R300_ALU_RGB_OMOD(x) (x << 27) |
| # define R300_ALU_RGB_OMOD_NONE 0 |
| # define R300_ALU_RGB_OMOD_MUL_2 1 |
| # define R300_ALU_RGB_OMOD_MUL_4 2 |
| # define R300_ALU_RGB_OMOD_MUL_8 3 |
| # define R300_ALU_RGB_OMOD_DIV_2 4 |
| # define R300_ALU_RGB_OMOD_DIV_4 5 |
| # define R300_ALU_RGB_OMOD_DIV_8 6 |
| # define R300_ALU_RGB_CLAMP (1 << 30) |
| # define R300_ALU_RGB_INSERT_NOP (1 << 31) |
| #define R300_US_ALU_ALPHA_ADDR_0 0x47c0 |
| #define R300_US_ALU_ALPHA_ADDR_1 0x47c4 |
| #define R300_US_ALU_ALPHA_ADDR_2 0x47c8 |
| #define R300_US_ALU_ALPHA_ADDR(x) (R300_US_ALU_ALPHA_ADDR_0 + (x)*4) |
| /* for ADDR0-2, values 0-31 specify a location in the pixel stack, |
| values 32-63 specify a constant */ |
| # define R300_ALU_ALPHA_ADDR0(x) (x << 0) |
| # define R300_ALU_ALPHA_ADDR1(x) (x << 6) |
| # define R300_ALU_ALPHA_ADDR2(x) (x << 12) |
| # define R300_ALU_ALPHA_CONST(x) ((x) | (1 << 5)) |
| /* ADDRD - where on the pixel stack the result of this instruction |
| will be written */ |
| # define R300_ALU_ALPHA_ADDRD(x) (x << 18) |
| # define R300_ALU_ALPHA_WMASK(x) (x << 23) |
| # define R300_ALU_ALPHA_OMASK(x) (x << 24) |
| # define R300_ALU_ALPHA_OMASK_W(x) (x << 27) |
| # define R300_ALU_ALPHA_MASK_NONE 0 |
| # define R300_ALU_ALPHA_MASK_A 1 |
| # define R300_ALU_ALPHA_TARGET_A (0 << 25) |
| # define R300_ALU_ALPHA_TARGET_B (1 << 25) |
| # define R300_ALU_ALPHA_TARGET_C (2 << 25) |
| # define R300_ALU_ALPHA_TARGET_D (3 << 25) |
| #define R300_US_ALU_ALPHA_INST_0 0x49c0 |
| #define R300_US_ALU_ALPHA_INST_1 0x49c4 |
| #define R300_US_ALU_ALPHA_INST_2 0x49c8 |
| #define R300_US_ALU_ALPHA_INST(x) (R300_US_ALU_ALPHA_INST_0 + (x)*4) |
| # define R300_ALU_ALPHA_SEL_A(x) (x << 0) |
| # define R300_ALU_ALPHA_SRC0_R 0 |
| # define R300_ALU_ALPHA_SRC0_G 1 |
| # define R300_ALU_ALPHA_SRC0_B 2 |
| # define R300_ALU_ALPHA_SRC1_R 3 |
| # define R300_ALU_ALPHA_SRC1_G 4 |
| # define R300_ALU_ALPHA_SRC1_B 5 |
| # define R300_ALU_ALPHA_SRC2_R 6 |
| # define R300_ALU_ALPHA_SRC2_G 7 |
| # define R300_ALU_ALPHA_SRC2_B 8 |
| # define R300_ALU_ALPHA_SRC0_A 9 |
| # define R300_ALU_ALPHA_SRC1_A 10 |
| # define R300_ALU_ALPHA_SRC2_A 11 |
| # define R300_ALU_ALPHA_SRCP_R 12 |
| # define R300_ALU_ALPHA_SRCP_G 13 |
| # define R300_ALU_ALPHA_SRCP_B 14 |
| # define R300_ALU_ALPHA_SRCP_A 15 |
| # define R300_ALU_ALPHA_0_0 16 |
| # define R300_ALU_ALPHA_1_0 17 |
| # define R300_ALU_ALPHA_0_5 18 |
| # define R300_ALU_ALPHA_MOD_A(x) (x << 5) |
| # define R300_ALU_ALPHA_MOD_NOP 0 |
| # define R300_ALU_ALPHA_MOD_NEG 1 |
| # define R300_ALU_ALPHA_MOD_ABS 2 |
| # define R300_ALU_ALPHA_MOD_NAB 3 |
| # define R300_ALU_ALPHA_SEL_B(x) (x << 7) |
| # define R300_ALU_ALPHA_MOD_B(x) (x << 12) |
| # define R300_ALU_ALPHA_SEL_C(x) (x << 14) |
| # define R300_ALU_ALPHA_MOD_C(x) (x << 19) |
| # define R300_ALU_ALPHA_SRCP_OP(x) (x << 21) |
| # define R300_ALU_ALPHA_SRCP_OP_1_MINUS_2RGB0 0 |
| # define R300_ALU_ALPHA_SRCP_OP_RGB1_MINUS_RGB0 1 |
| # define R300_ALU_ALPHA_SRCP_OP_RGB1_PLUS_RGB0 2 |
| # define R300_ALU_ALPHA_SRCP_OP_1_MINUS_RGB0 3 |
| # define R300_ALU_ALPHA_OP(x) (x << 23) |
| # define R300_ALU_ALPHA_OP_MAD 0 |
| # define R300_ALU_ALPHA_OP_DP 1 |
| # define R300_ALU_ALPHA_OP_MIN 2 |
| # define R300_ALU_ALPHA_OP_MAX 3 |
| # define R300_ALU_ALPHA_OP_CND 5 |
| # define R300_ALU_ALPHA_OP_CMP 6 |
| # define R300_ALU_ALPHA_OP_FRC 7 |
| # define R300_ALU_ALPHA_OP_EX2 8 |
| # define R300_ALU_ALPHA_OP_LN2 9 |
| # define R300_ALU_ALPHA_OP_RCP 10 |
| # define R300_ALU_ALPHA_OP_RSQ 11 |
| # define R300_ALU_ALPHA_OMOD(x) (x << 27) |
| # define R300_ALU_ALPHA_OMOD_NONE 0 |
| # define R300_ALU_ALPHA_OMOD_MUL_2 1 |
| # define R300_ALU_ALPHA_OMOD_MUL_4 2 |
| # define R300_ALU_ALPHA_OMOD_MUL_8 3 |
| # define R300_ALU_ALPHA_OMOD_DIV_2 4 |
| # define R300_ALU_ALPHA_OMOD_DIV_4 5 |
| # define R300_ALU_ALPHA_OMOD_DIV_8 6 |
| # define R300_ALU_ALPHA_CLAMP (1 << 30) |
| #define R300_US_ALU_CONST_R_0 0x4c00 |
| #define R300_US_ALU_CONST_R(x) (R300_US_ALU_CONST_R_0 + (x)*16) |
| #define R300_US_ALU_CONST_G_0 0x4c04 |
| #define R300_US_ALU_CONST_G(x) (R300_US_ALU_CONST_G_0 + (x)*16) |
| #define R300_US_ALU_CONST_B_0 0x4c08 |
| #define R300_US_ALU_CONST_B(x) (R300_US_ALU_CONST_B_0 + (x)*16) |
| #define R300_US_ALU_CONST_A_0 0x4c0c |
| #define R300_US_ALU_CONST_A(x) (R300_US_ALU_CONST_A_0 + (x)*16) |
| #define R300_FG_DEPTH_SRC 0x4bd8 |
| #define R300_FG_FOG_BLEND 0x4bc0 |
| #define R300_FG_ALPHA_FUNC 0x4bd4 |
| #define R300_DST_PIPE_CONFIG 0x170c |
| # define R300_PIPE_AUTO_CONFIG (1 << 31) |
| #define R300_RB2D_DSTCACHE_MODE 0x3428 |
| #define R300_RB2D_DSTCACHE_MODE 0x3428 |
| # define R300_DC_AUTOFLUSH_ENABLE (1 << 8) |
| # define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17) |
| #define R300_RB2D_DSTCACHE_CTLSTAT 0x342c /* use DSTCACHE_CTLSTAT instead */ |
| #define R300_DSTCACHE_CTLSTAT 0x1714 |
| # define R300_DC_FLUSH_2D (1 << 0) |
| # define R300_DC_FREE_2D (1 << 2) |
| # define R300_RB2D_DC_FLUSH_ALL (R300_DC_FLUSH_2D | R300_DC_FREE_2D) |
| # define R300_RB2D_DC_BUSY (1 << 31) |
| #define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c |
| # define R300_DC_FLUSH_3D (2 << 0) |
| # define R300_DC_FREE_3D (2 << 2) |
| # define R300_RB3D_DC_FLUSH_ALL (R300_DC_FLUSH_3D | R300_DC_FREE_3D) |
| # define R300_DC_FINISH_3D (1 << 4) |
| #define R300_RB3D_ZCACHE_CTLSTAT 0x4f18 |
| # define R300_ZC_FLUSH (1 << 0) |
| # define R300_ZC_FREE (1 << 1) |
| # define R300_ZC_FLUSH_ALL 0x3 |
| #define R300_RB3D_ZSTENCILCNTL 0x4f04 |
| #define R300_RB3D_ZCACHE_CTLSTAT 0x4f18 |
| #define R300_RB3D_BW_CNTL 0x4f1c |
| #define R300_RB3D_ZCNTL 0x4f00 |
| #define R300_RB3D_ZTOP 0x4f14 |
| #define R300_RB3D_ROPCNTL 0x4e18 |
| #define R300_RB3D_BLENDCNTL 0x4e04 |
| # define R300_ALPHA_BLEND_ENABLE (1 << 0) |
| # define R300_SEPARATE_ALPHA_ENABLE (1 << 1) |
| # define R300_READ_ENABLE (1 << 2) |
| #define R300_RB3D_ABLENDCNTL 0x4e08 |
| #define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c |
| #define R300_RB3D_COLOROFFSET0 0x4e28 |
| #define R300_RB3D_COLORPITCH0 0x4e38 |
| # define R300_COLORTILE (1 << 16) |
| # define R300_COLORENDIAN_WORD (1 << 19) |
| # define R300_COLORENDIAN_DWORD (2 << 19) |
| # define R300_COLORENDIAN_HALF_DWORD (3 << 19) |
| # define R300_COLORFORMAT_ARGB1555 (3 << 21) |
| # define R300_COLORFORMAT_RGB565 (4 << 21) |
| # define R300_COLORFORMAT_ARGB8888 (6 << 21) |
| # define R300_COLORFORMAT_ARGB32323232 (7 << 21) |
| # define R300_COLORFORMAT_I8 (9 << 21) |
| # define R300_COLORFORMAT_ARGB16161616 (10 << 21) |
| # define R300_COLORFORMAT_VYUY (11 << 21) |
| # define R300_COLORFORMAT_YVYU (12 << 21) |
| # define R300_COLORFORMAT_UV88 (13 << 21) |
| # define R300_COLORFORMAT_ARGB4444 (15 << 21) |
| #define R300_RB3D_AARESOLVE_CTL 0x4e88 |
| #define R300_RB3D_COLOR_CHANNEL_MASK 0x4e0c |
| # define R300_BLUE_MASK_EN (1 << 0) |
| # define R300_GREEN_MASK_EN (1 << 1) |
| # define R300_RED_MASK_EN (1 << 2) |
| # define R300_ALPHA_MASK_EN (1 << 3) |
| #define R300_RB3D_COLOR_CLEAR_VALUE 0x4e14 |
| #define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c |
| #define R300_RB3D_CCTL 0x4e00 |
| #define R300_RB3D_DITHER_CTL 0x4e50 |
| #define R300_SC_EDGERULE 0x43a8 |
| #define R300_SC_SCISSOR0 0x43e0 |
| #define R300_SC_SCISSOR1 0x43e4 |
| # define R300_SCISSOR_X_SHIFT 0 |
| # define R300_SCISSOR_Y_SHIFT 13 |
| #define R300_SC_CLIP_0_A 0x43b0 |
| #define R300_SC_CLIP_0_B 0x43b4 |
| # define R300_CLIP_X_SHIFT 0 |
| # define R300_CLIP_Y_SHIFT 13 |
| #define R300_SC_CLIP_RULE 0x43d0 |
| #define R300_SC_SCREENDOOR 0x43e8 |
| /* R500 US has to be loaded through an index/data pair */ |
| #define R500_GA_US_VECTOR_INDEX 0x4250 |
| # define R500_US_VECTOR_TYPE_INST (0 << 16) |
| # define R500_US_VECTOR_TYPE_CONST (1 << 16) |
| # define R500_US_VECTOR_CLAMP (1 << 17) |
| # define R500_US_VECTOR_INST_INDEX(x) ((x) | R500_US_VECTOR_TYPE_INST) |
| # define R500_US_VECTOR_CONST_INDEX(x) ((x) | R500_US_VECTOR_TYPE_CONST) |
| #define R500_GA_US_VECTOR_DATA 0x4254 |
| /* |
| * The R500 unified shader (US) registers come in banks of 512 each, one |
| * for each instruction slot in the shader. You can't touch them directly. |
| * R500_US_VECTOR_INDEX() sets the base instruction to modify; successive |
| * writes to R500_GA_US_VECTOR_DATA autoincrement the index after the |
| * instruction is fully specified. |
| */ |
| #define R500_US_ALU_ALPHA_INST_0 0xa800 |
| # define R500_ALPHA_OP_MAD 0 |
| # define R500_ALPHA_OP_DP 1 |
| # define R500_ALPHA_OP_MIN 2 |
| # define R500_ALPHA_OP_MAX 3 |
| /* #define R500_ALPHA_OP_RESERVED 4 */ |
| # define R500_ALPHA_OP_CND 5 |
| # define R500_ALPHA_OP_CMP 6 |
| # define R500_ALPHA_OP_FRC 7 |
| # define R500_ALPHA_OP_EX2 8 |
| # define R500_ALPHA_OP_LN2 9 |
| # define R500_ALPHA_OP_RCP 10 |
| # define R500_ALPHA_OP_RSQ 11 |
| # define R500_ALPHA_OP_SIN 12 |
| # define R500_ALPHA_OP_COS 13 |
| # define R500_ALPHA_OP_MDH 14 |
| # define R500_ALPHA_OP_MDV 15 |
| # define R500_ALPHA_ADDRD(x) (x << 4) |
| # define R500_ALPHA_ADDRD_REL (1 << 11) |
| # define R500_ALPHA_SEL_A_SRC0 (0 << 12) |
| # define R500_ALPHA_SEL_A_SRC1 (1 << 12) |
| # define R500_ALPHA_SEL_A_SRC2 (2 << 12) |
| # define R500_ALPHA_SEL_A_SRCP (3 << 12) |
| # define R500_ALPHA_SWIZ_A_R (0 << 14) |
| # define R500_ALPHA_SWIZ_A_G (1 << 14) |
| # define R500_ALPHA_SWIZ_A_B (2 << 14) |
| # define R500_ALPHA_SWIZ_A_A (3 << 14) |
| # define R500_ALPHA_SWIZ_A_0 (4 << 14) |
| # define R500_ALPHA_SWIZ_A_HALF (5 << 14) |
| # define R500_ALPHA_SWIZ_A_1 (6 << 14) |
| /* #define R500_ALPHA_SWIZ_A_UNUSED (7 << 14) */ |
| # define R500_ALPHA_MOD_A_NOP (0 << 17) |
| # define R500_ALPHA_MOD_A_NEG (1 << 17) |
| # define R500_ALPHA_MOD_A_ABS (2 << 17) |
| # define R500_ALPHA_MOD_A_NAB (3 << 17) |
| # define R500_ALPHA_SEL_B_SRC0 (0 << 19) |
| # define R500_ALPHA_SEL_B_SRC1 (1 << 19) |
| # define R500_ALPHA_SEL_B_SRC2 (2 << 19) |
| # define R500_ALPHA_SEL_B_SRCP (3 << 19) |
| # define R500_ALPHA_SWIZ_B_R (0 << 21) |
| # define R500_ALPHA_SWIZ_B_G (1 << 21) |
| # define R500_ALPHA_SWIZ_B_B (2 << 21) |
| # define R500_ALPHA_SWIZ_B_A (3 << 21) |
| # define R500_ALPHA_SWIZ_B_0 (4 << 21) |
| # define R500_ALPHA_SWIZ_B_HALF (5 << 21) |
| # define R500_ALPHA_SWIZ_B_1 (6 << 21) |
| /* #define R500_ALPHA_SWIZ_B_UNUSED (7 << 21) */ |
| # define R500_ALPHA_MOD_B_NOP (0 << 24) |
| # define R500_ALPHA_MOD_B_NEG (1 << 24) |
| # define R500_ALPHA_MOD_B_ABS (2 << 24) |
| # define R500_ALPHA_MOD_B_NAB (3 << 24) |
| # define R500_ALPHA_OMOD_IDENTITY (0 << 26) |
| # define R500_ALPHA_OMOD_MUL_2 (1 << 26) |
| # define R500_ALPHA_OMOD_MUL_4 (2 << 26) |
| # define R500_ALPHA_OMOD_MUL_8 (3 << 26) |
| # define R500_ALPHA_OMOD_DIV_2 (4 << 26) |
| # define R500_ALPHA_OMOD_DIV_4 (5 << 26) |
| # define R500_ALPHA_OMOD_DIV_8 (6 << 26) |
| # define R500_ALPHA_OMOD_DISABLE (7 << 26) |
| # define R500_ALPHA_TARGET(x) (x << 29) |
| # define R500_ALPHA_W_OMASK (1 << 31) |
| #define R500_US_ALU_ALPHA_ADDR_0 0x9800 |
| # define R500_ALPHA_ADDR0(x) (x << 0) |
| # define R500_ALPHA_ADDR0_CONST (1 << 8) |
| # define R500_ALPHA_ADDR0_REL (1 << 9) |
| # define R500_ALPHA_ADDR1(x) (x << 10) |
| # define R500_ALPHA_ADDR1_CONST (1 << 18) |
| # define R500_ALPHA_ADDR1_REL (1 << 19) |
| # define R500_ALPHA_ADDR2(x) (x << 20) |
| # define R500_ALPHA_ADDR2_CONST (1 << 28) |
| # define R500_ALPHA_ADDR2_REL (1 << 29) |
| # define R500_ALPHA_SRCP_OP_1_MINUS_2A0 (0 << 30) |
| # define R500_ALPHA_SRCP_OP_A1_MINUS_A0 (1 << 30) |
| # define R500_ALPHA_SRCP_OP_A1_PLUS_A0 (2 << 30) |
| # define R500_ALPHA_SRCP_OP_1_MINUS_A0 (3 << 30) |
| #define R500_US_ALU_RGBA_INST_0 0xb000 |
| # define R500_ALU_RGBA_OP_MAD (0 << 0) |
| # define R500_ALU_RGBA_OP_DP3 (1 << 0) |
| # define R500_ALU_RGBA_OP_DP4 (2 << 0) |
| # define R500_ALU_RGBA_OP_D2A (3 << 0) |
| # define R500_ALU_RGBA_OP_MIN (4 << 0) |
| # define R500_ALU_RGBA_OP_MAX (5 << 0) |
| /* #define R500_ALU_RGBA_OP_RESERVED (6 << 0) */ |
| # define R500_ALU_RGBA_OP_CND (7 << 0) |
| # define R500_ALU_RGBA_OP_CMP (8 << 0) |
| # define R500_ALU_RGBA_OP_FRC (9 << 0) |
| # define R500_ALU_RGBA_OP_SOP (10 << 0) |
| # define R500_ALU_RGBA_OP_MDH (11 << 0) |
| # define R500_ALU_RGBA_OP_MDV (12 << 0) |
| # define R500_ALU_RGBA_ADDRD(x) (x << 4) |
| # define R500_ALU_RGBA_ADDRD_REL (1 << 11) |
| # define R500_ALU_RGBA_SEL_C_SRC0 (0 << 12) |
| # define R500_ALU_RGBA_SEL_C_SRC1 (1 << 12) |
| # define R500_ALU_RGBA_SEL_C_SRC2 (2 << 12) |
| # define R500_ALU_RGBA_SEL_C_SRCP (3 << 12) |
| # define R500_ALU_RGBA_R_SWIZ_R (0 << 14) |
| # define R500_ALU_RGBA_R_SWIZ_G (1 << 14) |
| # define R500_ALU_RGBA_R_SWIZ_B (2 << 14) |
| # define R500_ALU_RGBA_R_SWIZ_A (3 << 14) |
| # define R500_ALU_RGBA_R_SWIZ_0 (4 << 14) |
| # define R500_ALU_RGBA_R_SWIZ_HALF (5 << 14) |
| # define R500_ALU_RGBA_R_SWIZ_1 (6 << 14) |
| /* #define R500_ALU_RGBA_R_SWIZ_UNUSED (7 << 14) */ |
| # define R500_ALU_RGBA_G_SWIZ_R (0 << 17) |
| # define R500_ALU_RGBA_G_SWIZ_G (1 << 17) |
| # define R500_ALU_RGBA_G_SWIZ_B (2 << 17) |
| # define R500_ALU_RGBA_G_SWIZ_A (3 << 17) |
| # define R500_ALU_RGBA_G_SWIZ_0 (4 << 17) |
| # define R500_ALU_RGBA_G_SWIZ_HALF (5 << 17) |
| # define R500_ALU_RGBA_G_SWIZ_1 (6 << 17) |
| /* #define R500_ALU_RGBA_G_SWIZ_UNUSED (7 << 17) */ |
| # define R500_ALU_RGBA_B_SWIZ_R (0 << 20) |
| # define R500_ALU_RGBA_B_SWIZ_G (1 << 20) |
| # define R500_ALU_RGBA_B_SWIZ_B (2 << 20) |
| # define R500_ALU_RGBA_B_SWIZ_A (3 << 20) |
| # define R500_ALU_RGBA_B_SWIZ_0 (4 << 20) |
| # define R500_ALU_RGBA_B_SWIZ_HALF (5 << 20) |
| # define R500_ALU_RGBA_B_SWIZ_1 (6 << 20) |
| /* #define R500_ALU_RGBA_B_SWIZ_UNUSED (7 << 20) */ |
| # define R500_ALU_RGBA_MOD_C_NOP (0 << 23) |
| # define R500_ALU_RGBA_MOD_C_NEG (1 << 23) |
| # define R500_ALU_RGBA_MOD_C_ABS (2 << 23) |
| # define R500_ALU_RGBA_MOD_C_NAB (3 << 23) |
| # define R500_ALU_RGBA_ALPHA_SEL_C_SRC0 (0 << 25) |
| # define R500_ALU_RGBA_ALPHA_SEL_C_SRC1 (1 << 25) |
| # define R500_ALU_RGBA_ALPHA_SEL_C_SRC2 (2 << 25) |
| # define R500_ALU_RGBA_ALPHA_SEL_C_SRCP (3 << 25) |
| # define R500_ALU_RGBA_A_SWIZ_R (0 << 27) |
| # define R500_ALU_RGBA_A_SWIZ_G (1 << 27) |
| # define R500_ALU_RGBA_A_SWIZ_B (2 << 27) |
| # define R500_ALU_RGBA_A_SWIZ_A (3 << 27) |
| # define R500_ALU_RGBA_A_SWIZ_0 (4 << 27) |
| # define R500_ALU_RGBA_A_SWIZ_HALF (5 << 27) |
| # define R500_ALU_RGBA_A_SWIZ_1 (6 << 27) |
| /* #define R500_ALU_RGBA_A_SWIZ_UNUSED (7 << 27) */ |
| # define R500_ALU_RGBA_ALPHA_MOD_C_NOP (0 << 30) |
| # define R500_ALU_RGBA_ALPHA_MOD_C_NEG (1 << 30) |
| # define R500_ALU_RGBA_ALPHA_MOD_C_ABS (2 << 30) |
| # define R500_ALU_RGBA_ALPHA_MOD_C_NAB (3 << 30) |
| #define R500_US_ALU_RGB_INST_0 0xa000 |
| # define R500_ALU_RGB_SEL_A_SRC0 (0 << 0) |
| # define R500_ALU_RGB_SEL_A_SRC1 (1 << 0) |
| # define R500_ALU_RGB_SEL_A_SRC2 (2 << 0) |
| # define R500_ALU_RGB_SEL_A_SRCP (3 << 0) |
| # define R500_ALU_RGB_R_SWIZ_A_R (0 << 2) |
| # define R500_ALU_RGB_R_SWIZ_A_G (1 << 2) |
| # define R500_ALU_RGB_R_SWIZ_A_B (2 << 2) |
| # define R500_ALU_RGB_R_SWIZ_A_A (3 << 2) |
| # define R500_ALU_RGB_R_SWIZ_A_0 (4 << 2) |
| # define R500_ALU_RGB_R_SWIZ_A_HALF (5 << 2) |
| # define R500_ALU_RGB_R_SWIZ_A_1 (6 << 2) |
| /* #define R500_ALU_RGB_R_SWIZ_A_UNUSED (7 << 2) */ |
| # define R500_ALU_RGB_G_SWIZ_A_R (0 << 5) |
| # define R500_ALU_RGB_G_SWIZ_A_G (1 << 5) |
| # define R500_ALU_RGB_G_SWIZ_A_B (2 << 5) |
| # define R500_ALU_RGB_G_SWIZ_A_A (3 << 5) |
| # define R500_ALU_RGB_G_SWIZ_A_0 (4 << 5) |
| # define R500_ALU_RGB_G_SWIZ_A_HALF (5 << 5) |
| # define R500_ALU_RGB_G_SWIZ_A_1 (6 << 5) |
| /* #define R500_ALU_RGB_G_SWIZ_A_UNUSED (7 << 5) */ |
| # define R500_ALU_RGB_B_SWIZ_A_R (0 << 8) |
| # define R500_ALU_RGB_B_SWIZ_A_G (1 << 8) |
| # define R500_ALU_RGB_B_SWIZ_A_B (2 << 8) |
| # define R500_ALU_RGB_B_SWIZ_A_A (3 << 8) |
| # define R500_ALU_RGB_B_SWIZ_A_0 (4 << 8) |
| # define R500_ALU_RGB_B_SWIZ_A_HALF (5 << 8) |
| # define R500_ALU_RGB_B_SWIZ_A_1 (6 << 8) |
| /* #define R500_ALU_RGB_B_SWIZ_A_UNUSED (7 << 8) */ |
| # define R500_ALU_RGB_MOD_A_NOP (0 << 11) |
| # define R500_ALU_RGB_MOD_A_NEG (1 << 11) |
| # define R500_ALU_RGB_MOD_A_ABS (2 << 11) |
| # define R500_ALU_RGB_MOD_A_NAB (3 << 11) |
| # define R500_ALU_RGB_SEL_B_SRC0 (0 << 13) |
| # define R500_ALU_RGB_SEL_B_SRC1 (1 << 13) |
| # define R500_ALU_RGB_SEL_B_SRC2 (2 << 13) |
| # define R500_ALU_RGB_SEL_B_SRCP (3 << 13) |
| # define R500_ALU_RGB_R_SWIZ_B_R (0 << 15) |
| # define R500_ALU_RGB_R_SWIZ_B_G (1 << 15) |
| # define R500_ALU_RGB_R_SWIZ_B_B (2 << 15) |
| # define R500_ALU_RGB_R_SWIZ_B_A (3 << 15) |
| # define R500_ALU_RGB_R_SWIZ_B_0 (4 << 15) |
| # define R500_ALU_RGB_R_SWIZ_B_HALF (5 << 15) |
| # define R500_ALU_RGB_R_SWIZ_B_1 (6 << 15) |
| /* #define R500_ALU_RGB_R_SWIZ_B_UNUSED (7 << 15) */ |
| # define R500_ALU_RGB_G_SWIZ_B_R (0 << 18) |
| # define R500_ALU_RGB_G_SWIZ_B_G (1 << 18) |
| # define R500_ALU_RGB_G_SWIZ_B_B (2 << 18) |
| # define R500_ALU_RGB_G_SWIZ_B_A (3 << 18) |
| # define R500_ALU_RGB_G_SWIZ_B_0 (4 << 18) |
| # define R500_ALU_RGB_G_SWIZ_B_HALF (5 << 18) |
| # define R500_ALU_RGB_G_SWIZ_B_1 (6 << 18) |
| /* #define R500_ALU_RGB_G_SWIZ_B_UNUSED (7 << 18) */ |
| # define R500_ALU_RGB_B_SWIZ_B_R (0 << 21) |
| # define R500_ALU_RGB_B_SWIZ_B_G (1 << 21) |
| # define R500_ALU_RGB_B_SWIZ_B_B (2 << 21) |
| # define R500_ALU_RGB_B_SWIZ_B_A (3 << 21) |
| # define R500_ALU_RGB_B_SWIZ_B_0 (4 << 21) |
| # define R500_ALU_RGB_B_SWIZ_B_HALF (5 << 21) |
| # define R500_ALU_RGB_B_SWIZ_B_1 (6 << 21) |
| /* #define R500_ALU_RGB_B_SWIZ_B_UNUSED (7 << 21) */ |
| # define R500_ALU_RGB_MOD_B_NOP (0 << 24) |
| # define R500_ALU_RGB_MOD_B_NEG (1 << 24) |
| # define R500_ALU_RGB_MOD_B_ABS (2 << 24) |
| # define R500_ALU_RGB_MOD_B_NAB (3 << 24) |
| # define R500_ALU_RGB_OMOD_IDENTITY (0 << 26) |
| # define R500_ALU_RGB_OMOD_MUL_2 (1 << 26) |
| # define R500_ALU_RGB_OMOD_MUL_4 (2 << 26) |
| # define R500_ALU_RGB_OMOD_MUL_8 (3 << 26) |
| # define R500_ALU_RGB_OMOD_DIV_2 (4 << 26) |
| # define R500_ALU_RGB_OMOD_DIV_4 (5 << 26) |
| # define R500_ALU_RGB_OMOD_DIV_8 (6 << 26) |
| # define R500_ALU_RGB_OMOD_DISABLE (7 << 26) |
| # define R500_ALU_RGB_TARGET(x) (x << 29) |
| # define R500_ALU_RGB_WMASK (1 << 31) |
| #define R500_US_ALU_RGB_ADDR_0 0x9000 |
| # define R500_RGB_ADDR0(x) (x << 0) |
| # define R500_RGB_ADDR0_CONST (1 << 8) |
| # define R500_RGB_ADDR0_REL (1 << 9) |
| # define R500_RGB_ADDR1(x) (x << 10) |
| # define R500_RGB_ADDR1_CONST (1 << 18) |
| # define R500_RGB_ADDR1_REL (1 << 19) |
| # define R500_RGB_ADDR2(x) (x << 20) |
| # define R500_RGB_ADDR2_CONST (1 << 28) |
| # define R500_RGB_ADDR2_REL (1 << 29) |
| # define R500_RGB_SRCP_OP_1_MINUS_2RGB0 (0 << 30) |
| # define R500_RGB_SRCP_OP_RGB1_MINUS_RGB0 (1 << 30) |
| # define R500_RGB_SRCP_OP_RGB1_PLUS_RGB0 (2 << 30) |
| # define R500_RGB_SRCP_OP_1_MINUS_RGB0 (3 << 30) |
| #define R500_US_CMN_INST_0 0xb800 |
| # define R500_INST_TYPE_ALU (0 << 0) |
| # define R500_INST_TYPE_OUT (1 << 0) |
| # define R500_INST_TYPE_FC (2 << 0) |
| # define R500_INST_TYPE_TEX (3 << 0) |
| # define R500_INST_TEX_SEM_WAIT (1 << 2) |
| # define R500_INST_RGB_PRED_SEL_NONE (0 << 3) |
| # define R500_INST_RGB_PRED_SEL_RGBA (1 << 3) |
| # define R500_INST_RGB_PRED_SEL_RRRR (2 << 3) |
| # define R500_INST_RGB_PRED_SEL_GGGG (3 << 3) |
| # define R500_INST_RGB_PRED_SEL_BBBB (4 << 3) |
| # define R500_INST_RGB_PRED_SEL_AAAA (5 << 3) |
| # define R500_INST_RGB_PRED_INV (1 << 6) |
| # define R500_INST_WRITE_INACTIVE (1 << 7) |
| # define R500_INST_LAST (1 << 8) |
| # define R500_INST_NOP (1 << 9) |
| # define R500_INST_ALU_WAIT (1 << 10) |
| # define R500_INST_RGB_WMASK_R (1 << 11) |
| # define R500_INST_RGB_WMASK_G (1 << 12) |
| # define R500_INST_RGB_WMASK_B (1 << 13) |
| # define R500_INST_ALPHA_WMASK (1 << 14) |
| # define R500_INST_RGB_OMASK_R (1 << 15) |
| # define R500_INST_RGB_OMASK_G (1 << 16) |
| # define R500_INST_RGB_OMASK_B (1 << 17) |
| # define R500_INST_ALPHA_OMASK (1 << 18) |
| # define R500_INST_RGB_CLAMP (1 << 19) |
| # define R500_INST_ALPHA_CLAMP (1 << 20) |
| # define R500_INST_ALU_RESULT_SEL (1 << 21) |
| # define R500_INST_ALPHA_PRED_INV (1 << 22) |
| # define R500_INST_ALU_RESULT_OP_EQ (0 << 23) |
| # define R500_INST_ALU_RESULT_OP_LT (1 << 23) |
| # define R500_INST_ALU_RESULT_OP_GE (2 << 23) |
| # define R500_INST_ALU_RESULT_OP_NE (3 << 23) |
| # define R500_INST_ALPHA_PRED_SEL_NONE (0 << 25) |
| # define R500_INST_ALPHA_PRED_SEL_RGBA (1 << 25) |
| # define R500_INST_ALPHA_PRED_SEL_RRRR (2 << 25) |
| # define R500_INST_ALPHA_PRED_SEL_GGGG (3 << 25) |
| # define R500_INST_ALPHA_PRED_SEL_BBBB (4 << 25) |
| # define R500_INST_ALPHA_PRED_SEL_AAAA (5 << 25) |
| /* XXX next four are kind of guessed */ |
| # define R500_INST_STAT_WE_R (1 << 28) |
| # define R500_INST_STAT_WE_G (1 << 29) |
| # define R500_INST_STAT_WE_B (1 << 30) |
| # define R500_INST_STAT_WE_A (1 << 31) |
| /* note that these are 8 bit lengths, despite the offsets, at least for R500 */ |
| #define R500_US_CODE_ADDR 0x4630 |
| # define R500_US_CODE_START_ADDR(x) (x << 0) |
| # define R500_US_CODE_END_ADDR(x) (x << 16) |
| #define R500_US_CODE_OFFSET 0x4638 |
| # define R500_US_CODE_OFFSET_ADDR(x) (x << 0) |
| #define R500_US_CODE_RANGE 0x4634 |
| # define R500_US_CODE_RANGE_ADDR(x) (x << 0) |
| # define R500_US_CODE_RANGE_SIZE(x) (x << 16) |
| #define R500_US_CONFIG 0x4600 |
| # define R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO (1 << 1) |
| #define R500_US_FC_ADDR_0 0xa000 |
| # define R500_FC_BOOL_ADDR(x) (x << 0) |
| # define R500_FC_INT_ADDR(x) (x << 8) |
| # define R500_FC_JUMP_ADDR(x) (x << 16) |
| # define R500_FC_JUMP_GLOBAL (1 << 31) |
| #define R500_US_FC_BOOL_CONST 0x4620 |
| # define R500_FC_KBOOL(x) (x) |
| #define R500_US_FC_CTRL 0x4624 |
| # define R500_FC_TEST_EN (1 << 30) |
| # define R500_FC_FULL_FC_EN (1 << 31) |
| #define R500_US_FC_INST_0 0x9800 |
| # define R500_FC_OP_JUMP (0 << 0) |
| # define R500_FC_OP_LOOP (1 << 0) |
| # define R500_FC_OP_ENDLOOP (2 << 0) |
| # define R500_FC_OP_REP (3 << 0) |
| # define R500_FC_OP_ENDREP (4 << 0) |
| # define R500_FC_OP_BREAKLOOP (5 << 0) |
| # define R500_FC_OP_BREAKREP (6 << 0) |
| # define R500_FC_OP_CONTINUE (7 << 0) |
| # define R500_FC_B_ELSE (1 << 4) |
| # define R500_FC_JUMP_ANY (1 << 5) |
| # define R500_FC_A_OP_NONE (0 << 6) |
| # define R500_FC_A_OP_POP (1 << 6) |
| # define R500_FC_A_OP_PUSH (2 << 6) |
| # define R500_FC_JUMP_FUNC(x) (x << 8) |
| # define R500_FC_B_POP_CNT(x) (x << 16) |
| # define R500_FC_B_OP0_NONE (0 << 24) |
| # define R500_FC_B_OP0_DECR (1 << 24) |
| # define R500_FC_B_OP0_INCR (2 << 24) |
| # define R500_FC_B_OP1_DECR (0 << 26) |
| # define R500_FC_B_OP1_NONE (1 << 26) |
| # define R500_FC_B_OP1_INCR (2 << 26) |
| # define R500_FC_IGNORE_UNCOVERED (1 << 28) |
| #define R500_US_FC_INT_CONST_0 0x4c00 |
| # define R500_FC_INT_CONST_KR(x) (x << 0) |
| # define R500_FC_INT_CONST_KG(x) (x << 8) |
| # define R500_FC_INT_CONST_KB(x) (x << 16) |
| /* _0 through _15 */ |
| #define R500_US_FORMAT0_0 0x4640 |
| # define R500_FORMAT_TXWIDTH(x) (x << 0) |
| # define R500_FORMAT_TXHEIGHT(x) (x << 11) |
| # define R500_FORMAT_TXDEPTH(x) (x << 22) |
| /* _0 through _3 */ |
| #define R500_US_OUT_FMT_0 0x46a4 |
| # define R500_OUT_FMT_C4_8 (0 << 0) |
| # define R500_OUT_FMT_C4_10 (1 << 0) |
| # define R500_OUT_FMT_C4_10_GAMMA (2 << 0) |
| # define R500_OUT_FMT_C_16 (3 << 0) |
| # define R500_OUT_FMT_C2_16 (4 << 0) |
| # define R500_OUT_FMT_C4_16 (5 << 0) |
| # define R500_OUT_FMT_C_16_MPEG (6 << 0) |
| # define R500_OUT_FMT_C2_16_MPEG (7 << 0) |
| # define R500_OUT_FMT_C2_4 (8 << 0) |
| # define R500_OUT_FMT_C_3_3_2 (9 << 0) |
| # define R500_OUT_FMT_C_6_5_6 (10 << 0) |
| # define R500_OUT_FMT_C_11_11_10 (11 << 0) |
| # define R500_OUT_FMT_C_10_11_11 (12 << 0) |
| # define R500_OUT_FMT_C_2_10_10_10 (13 << 0) |
| /* #define R500_OUT_FMT_RESERVED (14 << 0) */ |
| # define R500_OUT_FMT_UNUSED (15 << 0) |
| # define R500_OUT_FMT_C_16_FP (16 << 0) |
| # define R500_OUT_FMT_C2_16_FP (17 << 0) |
| # define R500_OUT_FMT_C4_16_FP (18 << 0) |
| # define R500_OUT_FMT_C_32_FP (19 << 0) |
| # define R500_OUT_FMT_C2_32_FP (20 << 0) |
| # define R500_OUT_FMT_C4_32_FP (21 << 0) |
| # define R500_C0_SEL_A (0 << 8) |
| # define R500_C0_SEL_R (1 << 8) |
| # define R500_C0_SEL_G (2 << 8) |
| # define R500_C0_SEL_B (3 << 8) |
| # define R500_C1_SEL_A (0 << 10) |
| # define R500_C1_SEL_R (1 << 10) |
| # define R500_C1_SEL_G (2 << 10) |
| # define R500_C1_SEL_B (3 << 10) |
| # define R500_C2_SEL_A (0 << 12) |
| # define R500_C2_SEL_R (1 << 12) |
| # define R500_C2_SEL_G (2 << 12) |
| # define R500_C2_SEL_B (3 << 12) |
| # define R500_C3_SEL_A (0 << 14) |
| # define R500_C3_SEL_R (1 << 14) |
| # define R500_C3_SEL_G (2 << 14) |
| # define R500_C3_SEL_B (3 << 14) |
| # define R500_OUT_SIGN(x) (x << 16) |
| # define R500_ROUND_ADJ (1 << 20) |
| #define R500_US_PIXSIZE 0x4604 |
| # define R500_PIX_SIZE(x) (x) |
| #define R500_US_TEX_ADDR_0 0x9800 |
| # define R500_TEX_SRC_ADDR(x) (x << 0) |
| # define R500_TEX_SRC_ADDR_REL (1 << 7) |
| # define R500_TEX_SRC_S_SWIZ_R (0 << 8) |
| # define R500_TEX_SRC_S_SWIZ_G (1 << 8) |
| # define R500_TEX_SRC_S_SWIZ_B (2 << 8) |
| # define R500_TEX_SRC_S_SWIZ_A (3 << 8) |
| # define R500_TEX_SRC_T_SWIZ_R (0 << 10) |
| # define R500_TEX_SRC_T_SWIZ_G (1 << 10) |
| # define R500_TEX_SRC_T_SWIZ_B (2 << 10) |
| # define R500_TEX_SRC_T_SWIZ_A (3 << 10) |
| # define R500_TEX_SRC_R_SWIZ_R (0 << 12) |
| # define R500_TEX_SRC_R_SWIZ_G (1 << 12) |
| # define R500_TEX_SRC_R_SWIZ_B (2 << 12) |
| # define R500_TEX_SRC_R_SWIZ_A (3 << 12) |
| # define R500_TEX_SRC_Q_SWIZ_R (0 << 14) |
| # define R500_TEX_SRC_Q_SWIZ_G (1 << 14) |
| # define R500_TEX_SRC_Q_SWIZ_B (2 << 14) |
| # define R500_TEX_SRC_Q_SWIZ_A (3 << 14) |
| # define R500_TEX_DST_ADDR(x) (x << 16) |
| # define R500_TEX_DST_ADDR_REL (1 << 23) |
| # define R500_TEX_DST_R_SWIZ_R (0 << 24) |
| # define R500_TEX_DST_R_SWIZ_G (1 << 24) |
| # define R500_TEX_DST_R_SWIZ_B (2 << 24) |
| # define R500_TEX_DST_R_SWIZ_A (3 << 24) |
| # define R500_TEX_DST_G_SWIZ_R (0 << 26) |
| # define R500_TEX_DST_G_SWIZ_G (1 << 26) |
| # define R500_TEX_DST_G_SWIZ_B (2 << 26) |
| # define R500_TEX_DST_G_SWIZ_A (3 << 26) |
| # define R500_TEX_DST_B_SWIZ_R (0 << 28) |
| # define R500_TEX_DST_B_SWIZ_G (1 << 28) |
| # define R500_TEX_DST_B_SWIZ_B (2 << 28) |
| # define R500_TEX_DST_B_SWIZ_A (3 << 28) |
| # define R500_TEX_DST_A_SWIZ_R (0 << 30) |
| # define R500_TEX_DST_A_SWIZ_G (1 << 30) |
| # define R500_TEX_DST_A_SWIZ_B (2 << 30) |
| # define R500_TEX_DST_A_SWIZ_A (3 << 30) |
| #define R500_US_TEX_ADDR_DXDY_0 0xa000 |
| # define R500_DX_ADDR(x) (x << 0) |
| # define R500_DX_ADDR_REL (1 << 7) |
| # define R500_DX_S_SWIZ_R (0 << 8) |
| # define R500_DX_S_SWIZ_G (1 << 8) |
| # define R500_DX_S_SWIZ_B (2 << 8) |
| # define R500_DX_S_SWIZ_A (3 << 8) |
| # define R500_DX_T_SWIZ_R (0 << 10) |
| # define R500_DX_T_SWIZ_G (1 << 10) |
| # define R500_DX_T_SWIZ_B (2 << 10) |
| # define R500_DX_T_SWIZ_A (3 << 10) |
| # define R500_DX_R_SWIZ_R (0 << 12) |
| # define R500_DX_R_SWIZ_G (1 << 12) |
| # define R500_DX_R_SWIZ_B (2 << 12) |
| # define R500_DX_R_SWIZ_A (3 << 12) |
| # define R500_DX_Q_SWIZ_R (0 << 14) |
| # define R500_DX_Q_SWIZ_G (1 << 14) |
| # define R500_DX_Q_SWIZ_B (2 << 14) |
| # define R500_DX_Q_SWIZ_A (3 << 14) |
| # define R500_DY_ADDR(x) (x << 16) |
| # define R500_DY_ADDR_REL (1 << 17) |
| # define R500_DY_S_SWIZ_R (0 << 24) |
| # define R500_DY_S_SWIZ_G (1 << 24) |
| # define R500_DY_S_SWIZ_B (2 << 24) |
| # define R500_DY_S_SWIZ_A (3 << 24) |
| # define R500_DY_T_SWIZ_R (0 << 26) |
| # define R500_DY_T_SWIZ_G (1 << 26) |
| # define R500_DY_T_SWIZ_B (2 << 26) |
| # define R500_DY_T_SWIZ_A (3 << 26) |
| # define R500_DY_R_SWIZ_R (0 << 28) |
| # define R500_DY_R_SWIZ_G (1 << 28) |
| # define R500_DY_R_SWIZ_B (2 << 28) |
| # define R500_DY_R_SWIZ_A (3 << 28) |
| # define R500_DY_Q_SWIZ_R (0 << 30) |
| # define R500_DY_Q_SWIZ_G (1 << 30) |
| # define R500_DY_Q_SWIZ_B (2 << 30) |
| # define R500_DY_Q_SWIZ_A (3 << 30) |
| #define R500_US_TEX_INST_0 0x9000 |
| # define R500_TEX_ID(x) (x << 16) |
| # define R500_TEX_INST_NOP (0 << 22) |
| # define R500_TEX_INST_LD (1 << 22) |
| # define R500_TEX_INST_TEXKILL (2 << 22) |
| # define R500_TEX_INST_PROJ (3 << 22) |
| # define R500_TEX_INST_LODBIAS (4 << 22) |
| # define R500_TEX_INST_LOD (5 << 22) |
| # define R500_TEX_INST_DXDY (6 << 22) |
| # define R500_TEX_SEM_ACQUIRE (1 << 25) |
| # define R500_TEX_IGNORE_UNCOVERED (1 << 26) |
| # define R500_TEX_UNSCALED (1 << 27) |
| #define R500_US_W_FMT 0x46b4 |
| # define R500_W_FMT_W0 (0 << 0) |
| # define R500_W_FMT_W24 (1 << 0) |
| # define R500_W_FMT_W24FP (2 << 0) |
| # define R500_W_SRC_US (0 << 2) |
| # define R500_W_SRC_RAS (1 << 2) |
| #define R500_GA_US_VECTOR_INDEX 0x4250 |
| #define R500_GA_US_VECTOR_DATA 0x4254 |
| #define R500_RS_INST_0 0x4320 |
| #define R500_RS_INST_1 0x4324 |
| # define R500_RS_INST_TEX_ID_SHIFT 0 |
| # define R500_RS_INST_TEX_CN_WRITE (1 << 4) |
| # define R500_RS_INST_TEX_ADDR_SHIFT 5 |
| # define R500_RS_INST_COL_ID_SHIFT 12 |
| # define R500_RS_INST_COL_CN_NO_WRITE (0 << 16) |
| # define R500_RS_INST_COL_CN_WRITE (1 << 16) |
| # define R500_RS_INST_COL_CN_WRITE_FBUFFER (2 << 16) |
| # define R500_RS_INST_COL_CN_WRITE_BACKFACE (3 << 16) |
| # define R500_RS_INST_COL_COL_ADDR_SHIFT 18 |
| # define R500_RS_INST_TEX_ADJ (1 << 25) |
| # define R500_RS_INST_W_CN (1 << 26) |
| #define R500_US_FC_CTRL 0x4624 |
| #define R500_US_CODE_ADDR 0x4630 |
| #define R500_US_CODE_RANGE 0x4634 |
| #define R500_US_CODE_OFFSET 0x4638 |
| #define R500_RS_IP_0 0x4074 |
| #define R500_RS_IP_1 0x4078 |
| # define R500_RS_IP_PTR_K0 62 |
| # define R500_RS_IP_PTR_K1 63 |
| # define R500_RS_IP_TEX_PTR_S_SHIFT 0 |
| # define R500_RS_IP_TEX_PTR_T_SHIFT 6 |
| # define R500_RS_IP_TEX_PTR_R_SHIFT 12 |
| # define R500_RS_IP_TEX_PTR_Q_SHIFT 18 |
| # define R500_RS_IP_COL_PTR_SHIFT 24 |
| # define R500_RS_IP_COL_FMT_SHIFT 27 |
| # define R500_RS_IP_COL_FMT_RGBA (0 << 27) |
| # define R500_RS_IP_OFFSET_EN (1 << 31) |
| #define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */ |
| #endif |
| /drivers/old/ati2d/rhd_regs.h |
|---|
| 0,0 → 1,836 |
| /* |
| * Copyright 2007, 2008 Luc Verhaegen <lverhaegen@novell.com> |
| * Copyright 2007, 2008 Matthias Hopf <mhopf@novell.com> |
| * Copyright 2007, 2008 Egbert Eich <eich@novell.com> |
| * Copyright 2007, 2008 Advanced Micro Devices, Inc. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice shall be included in |
| * all copies or substantial portions of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| * OTHER DEALINGS IN THE SOFTWARE. |
| */ |
| #ifndef _RHD_REGS_H |
| # define _RHD_REGS_H |
| enum { |
| CLOCK_CNTL_INDEX = 0x8, /* (RW) */ |
| CLOCK_CNTL_DATA = 0xC, /* (RW) */ |
| BUS_CNTL = 0x4C, /* (RW) */ |
| MC_IND_INDEX = 0x70, /* (RW) */ |
| MC_IND_DATA = 0x74, /* (RW) */ |
| CONFIG_CNTL = 0xE0, |
| /* RS690 ?? */ |
| RS69_MC_INDEX = 0xE8, |
| RS69_MC_DATA = 0xEC, |
| R5XX_CONFIG_MEMSIZE = 0x00F8, |
| HDP_FB_LOCATION = 0x0134, |
| SEPROM_CNTL1 = 0x1C0, /* (RW) */ |
| GPIOPAD_MASK = 0x198, /* (RW) */ |
| GPIOPAD_A = 0x19C, /* (RW) */ |
| GPIOPAD_EN = 0x1A0, /* (RW) */ |
| VIPH_CONTROL = 0xC40, /* (RW) */ |
| /* VGA registers */ |
| VGA_RENDER_CONTROL = 0x0300, |
| VGA_MODE_CONTROL = 0x0308, |
| VGA_MEMORY_BASE_ADDRESS = 0x0310, |
| VGA_HDP_CONTROL = 0x0328, |
| D1VGA_CONTROL = 0x0330, |
| D2VGA_CONTROL = 0x0338, |
| EXT1_PPLL_REF_DIV_SRC = 0x0400, |
| EXT1_PPLL_REF_DIV = 0x0404, |
| EXT1_PPLL_UPDATE_LOCK = 0x0408, |
| EXT1_PPLL_UPDATE_CNTL = 0x040C, |
| EXT2_PPLL_REF_DIV_SRC = 0x0410, |
| EXT2_PPLL_REF_DIV = 0x0414, |
| EXT2_PPLL_UPDATE_LOCK = 0x0418, |
| EXT2_PPLL_UPDATE_CNTL = 0x041C, |
| EXT1_PPLL_FB_DIV = 0x0430, |
| EXT2_PPLL_FB_DIV = 0x0434, |
| EXT1_PPLL_POST_DIV_SRC = 0x0438, |
| EXT1_PPLL_POST_DIV = 0x043C, |
| EXT2_PPLL_POST_DIV_SRC = 0x0440, |
| EXT2_PPLL_POST_DIV = 0x0444, |
| EXT1_PPLL_CNTL = 0x0448, |
| EXT2_PPLL_CNTL = 0x044C, |
| P1PLL_CNTL = 0x0450, |
| P2PLL_CNTL = 0x0454, |
| P1PLL_INT_SS_CNTL = 0x0458, |
| P2PLL_INT_SS_CNTL = 0x045C, |
| P1PLL_DISP_CLK_CNTL = 0x0468, /* rv620+ */ |
| P2PLL_DISP_CLK_CNTL = 0x046C, /* rv620+ */ |
| EXT1_SYM_PPLL_POST_DIV = 0x0470, /* rv620+ */ |
| EXT2_SYM_PPLL_POST_DIV = 0x0474, /* rv620+ */ |
| PCLK_CRTC1_CNTL = 0x0480, |
| PCLK_CRTC2_CNTL = 0x0484, |
| DCCG_DISP_CLK_SRCSEL = 0x0538, /* rv620+ */ |
| R6XX_MC_VM_FB_LOCATION = 0x2180, |
| R6XX_HDP_NONSURFACE_BASE = 0x2C04, |
| R6XX_CONFIG_MEMSIZE = 0x5428, |
| R6XX_CONFIG_FB_BASE = 0x542C, /* AKA CONFIG_F0_BASE */ |
| /* CRTC1 registers */ |
| D1CRTC_H_TOTAL = 0x6000, |
| D1CRTC_H_BLANK_START_END = 0x6004, |
| D1CRTC_H_SYNC_A = 0x6008, |
| D1CRTC_H_SYNC_A_CNTL = 0x600C, |
| D1CRTC_H_SYNC_B = 0x6010, |
| D1CRTC_H_SYNC_B_CNTL = 0x6014, |
| D1CRTC_V_TOTAL = 0x6020, |
| D1CRTC_V_BLANK_START_END = 0x6024, |
| D1CRTC_V_SYNC_A = 0x6028, |
| D1CRTC_V_SYNC_A_CNTL = 0x602C, |
| D1CRTC_V_SYNC_B = 0x6030, |
| D1CRTC_V_SYNC_B_CNTL = 0x6034, |
| D1CRTC_CONTROL = 0x6080, |
| D1CRTC_BLANK_CONTROL = 0x6084, |
| D1CRTC_INTERLACE_CONTROL = 0x6088, |
| D1CRTC_BLACK_COLOR = 0x6098, |
| D1CRTC_STATUS = 0x609C, |
| D1CRTC_COUNT_CONTROL = 0x60B4, |
| /* D1GRPH registers */ |
| D1GRPH_ENABLE = 0x6100, |
| D1GRPH_CONTROL = 0x6104, |
| D1GRPH_LUT_SEL = 0x6108, |
| D1GRPH_SWAP_CNTL = 0x610C, |
| D1GRPH_PRIMARY_SURFACE_ADDRESS = 0x6110, |
| D1GRPH_SECONDARY_SURFACE_ADDRESS = 0x6118, |
| D1GRPH_PITCH = 0x6120, |
| D1GRPH_SURFACE_OFFSET_X = 0x6124, |
| D1GRPH_SURFACE_OFFSET_Y = 0x6128, |
| D1GRPH_X_START = 0x612C, |
| D1GRPH_Y_START = 0x6130, |
| D1GRPH_X_END = 0x6134, |
| D1GRPH_Y_END = 0x6138, |
| D1GRPH_UPDATE = 0x6144, |
| /* LUT */ |
| DC_LUT_RW_SELECT = 0x6480, |
| DC_LUT_RW_MODE = 0x6484, |
| DC_LUT_RW_INDEX = 0x6488, |
| DC_LUT_SEQ_COLOR = 0x648C, |
| DC_LUT_PWL_DATA = 0x6490, |
| DC_LUT_30_COLOR = 0x6494, |
| DC_LUT_READ_PIPE_SELECT = 0x6498, |
| DC_LUT_WRITE_EN_MASK = 0x649C, |
| DC_LUT_AUTOFILL = 0x64A0, |
| /* LUTA */ |
| DC_LUTA_CONTROL = 0x64C0, |
| DC_LUTA_BLACK_OFFSET_BLUE = 0x64C4, |
| DC_LUTA_BLACK_OFFSET_GREEN = 0x64C8, |
| DC_LUTA_BLACK_OFFSET_RED = 0x64CC, |
| DC_LUTA_WHITE_OFFSET_BLUE = 0x64D0, |
| DC_LUTA_WHITE_OFFSET_GREEN = 0x64D4, |
| DC_LUTA_WHITE_OFFSET_RED = 0x64D8, |
| /* D1CUR */ |
| D1CUR_CONTROL = 0x6400, |
| D1CUR_SURFACE_ADDRESS = 0x6408, |
| D1CUR_SIZE = 0x6410, |
| D1CUR_POSITION = 0x6414, |
| D1CUR_HOT_SPOT = 0x6418, |
| D1CUR_UPDATE = 0x6424, |
| /* D1MODE */ |
| D1MODE_DESKTOP_HEIGHT = 0x652C, |
| D1MODE_VIEWPORT_START = 0x6580, |
| D1MODE_VIEWPORT_SIZE = 0x6584, |
| D1MODE_EXT_OVERSCAN_LEFT_RIGHT = 0x6588, |
| D1MODE_EXT_OVERSCAN_TOP_BOTTOM = 0x658C, |
| D1MODE_DATA_FORMAT = 0x6528, |
| /* D1SCL */ |
| D1SCL_ENABLE = 0x6590, |
| D1SCL_TAP_CONTROL = 0x6594, |
| D1MODE_CENTER = 0x659C, /* guess */ |
| D1SCL_HVSCALE = 0x65A4, /* guess */ |
| D1SCL_HFILTER = 0x65B0, /* guess */ |
| D1SCL_VFILTER = 0x65C0, /* guess */ |
| D1SCL_UPDATE = 0x65CC, |
| D1SCL_DITHER = 0x65D4, /* guess */ |
| D1SCL_FLIP_CONTROL = 0x65D8, /* guess */ |
| /* CRTC2 registers */ |
| D2CRTC_H_TOTAL = 0x6800, |
| D2CRTC_H_BLANK_START_END = 0x6804, |
| D2CRTC_H_SYNC_A = 0x6808, |
| D2CRTC_H_SYNC_A_CNTL = 0x680C, |
| D2CRTC_H_SYNC_B = 0x6810, |
| D2CRTC_H_SYNC_B_CNTL = 0x6814, |
| D2CRTC_V_TOTAL = 0x6820, |
| D2CRTC_V_BLANK_START_END = 0x6824, |
| D2CRTC_V_SYNC_A = 0x6828, |
| D2CRTC_V_SYNC_A_CNTL = 0x682C, |
| D2CRTC_V_SYNC_B = 0x6830, |
| D2CRTC_V_SYNC_B_CNTL = 0x6834, |
| D2CRTC_CONTROL = 0x6880, |
| D2CRTC_BLANK_CONTROL = 0x6884, |
| D2CRTC_BLACK_COLOR = 0x6898, |
| D2CRTC_INTERLACE_CONTROL = 0x6888, |
| D2CRTC_STATUS = 0x689C, |
| D2CRTC_COUNT_CONTROL = 0x68B4, |
| /* D2GRPH registers */ |
| D2GRPH_ENABLE = 0x6900, |
| D2GRPH_CONTROL = 0x6904, |
| D2GRPH_LUT_SEL = 0x6908, |
| D2GRPH_SWAP_CNTL = 0x690C, |
| D2GRPH_PRIMARY_SURFACE_ADDRESS = 0x6910, |
| D2GRPH_PITCH = 0x6920, |
| D2GRPH_SURFACE_OFFSET_X = 0x6924, |
| D2GRPH_SURFACE_OFFSET_Y = 0x6928, |
| D2GRPH_X_START = 0x692C, |
| D2GRPH_Y_START = 0x6930, |
| D2GRPH_X_END = 0x6934, |
| D2GRPH_Y_END = 0x6938, |
| /* LUTB */ |
| DC_LUTB_CONTROL = 0x6CC0, |
| DC_LUTB_BLACK_OFFSET_BLUE = 0x6CC4, |
| DC_LUTB_BLACK_OFFSET_GREEN = 0x6CC8, |
| DC_LUTB_BLACK_OFFSET_RED = 0x6CCC, |
| DC_LUTB_WHITE_OFFSET_BLUE = 0x6CD0, |
| DC_LUTB_WHITE_OFFSET_GREEN = 0x6CD4, |
| DC_LUTB_WHITE_OFFSET_RED = 0x6CD8, |
| /* D2MODE */ |
| D2MODE_DESKTOP_HEIGHT = 0x6D2C, |
| D2MODE_VIEWPORT_START = 0x6D80, |
| D2MODE_VIEWPORT_SIZE = 0x6D84, |
| D2MODE_EXT_OVERSCAN_LEFT_RIGHT = 0x6D88, |
| D2MODE_EXT_OVERSCAN_TOP_BOTTOM = 0x6D8C, |
| D2MODE_DATA_FORMAT = 0x6D28, |
| /* D2SCL */ |
| D2SCL_ENABLE = 0x6D90, |
| D2SCL_TAP_CONTROL = 0x6D94, |
| D2MODE_CENTER = 0x6D9C, /* guess */ |
| D2SCL_HVSCALE = 0x6DA4, /* guess */ |
| D2SCL_HFILTER = 0x6DB0, /* guess */ |
| D2SCL_VFILTER = 0x6DC0, /* guess */ |
| D2SCL_UPDATE = 0x6DCC, |
| D2SCL_DITHER = 0x6DD4, /* guess */ |
| D2SCL_FLIP_CONTROL = 0x6DD8, /* guess */ |
| /* R500 DAC A */ |
| DACA_ENABLE = 0x7800, |
| DACA_SOURCE_SELECT = 0x7804, |
| DACA_SYNC_TRISTATE_CONTROL = 0x7820, |
| DACA_SYNC_SELECT = 0x7824, |
| DACA_AUTODETECT_CONTROL = 0x7828, |
| DACA_FORCE_OUTPUT_CNTL = 0x783C, |
| DACA_FORCE_DATA = 0x7840, |
| DACA_POWERDOWN = 0x7850, |
| DACA_CONTROL1 = 0x7854, |
| DACA_CONTROL2 = 0x7858, |
| DACA_COMPARATOR_ENABLE = 0x785C, |
| DACA_COMPARATOR_OUTPUT = 0x7860, |
| /* TMDSA */ |
| TMDSA_CNTL = 0x7880, |
| TMDSA_SOURCE_SELECT = 0x7884, |
| TMDSA_COLOR_FORMAT = 0x7888, |
| TMDSA_FORCE_OUTPUT_CNTL = 0x788C, |
| TMDSA_BIT_DEPTH_CONTROL = 0x7894, |
| TMDSA_DCBALANCER_CONTROL = 0x78D0, |
| TMDSA_DATA_SYNCHRONIZATION_R500 = 0x78D8, |
| TMDSA_DATA_SYNCHRONIZATION_R600 = 0x78DC, |
| TMDSA_TRANSMITTER_ENABLE = 0x7904, |
| TMDSA_LOAD_DETECT = 0x7908, |
| TMDSA_MACRO_CONTROL = 0x790C, /* r5x0 and r600: 3 for pll and 1 for TX */ |
| TMDSA_PLL_ADJUST = 0x790C, /* rv6x0: pll only */ |
| TMDSA_TRANSMITTER_CONTROL = 0x7910, |
| TMDSA_TRANSMITTER_ADJUST = 0x7920, /* rv6x0: TX part of macro control */ |
| /* DAC B */ |
| DACB_ENABLE = 0x7A00, |
| DACB_SOURCE_SELECT = 0x7A04, |
| DACB_SYNC_TRISTATE_CONTROL = 0x7A20, |
| DACB_SYNC_SELECT = 0x7A24, |
| DACB_AUTODETECT_CONTROL = 0x7A28, |
| DACB_FORCE_OUTPUT_CNTL = 0x7A3C, |
| DACB_FORCE_DATA = 0x7A40, |
| DACB_POWERDOWN = 0x7A50, |
| DACB_CONTROL1 = 0x7A54, |
| DACB_CONTROL2 = 0x7A58, |
| DACB_COMPARATOR_ENABLE = 0x7A5C, |
| DACB_COMPARATOR_OUTPUT = 0x7A60, |
| /* LVTMA */ |
| LVTMA_CNTL = 0x7A80, |
| LVTMA_SOURCE_SELECT = 0x7A84, |
| LVTMA_COLOR_FORMAT = 0x7A88, |
| LVTMA_FORCE_OUTPUT_CNTL = 0x7A8C, |
| LVTMA_BIT_DEPTH_CONTROL = 0x7A94, |
| LVTMA_DCBALANCER_CONTROL = 0x7AD0, |
| /* no longer shared between both r5xx and r6xx */ |
| LVTMA_R500_DATA_SYNCHRONIZATION = 0x7AD8, |
| LVTMA_R500_PWRSEQ_REF_DIV = 0x7AE4, |
| LVTMA_R500_PWRSEQ_DELAY1 = 0x7AE8, |
| LVTMA_R500_PWRSEQ_DELAY2 = 0x7AEC, |
| LVTMA_R500_PWRSEQ_CNTL = 0x7AF0, |
| LVTMA_R500_PWRSEQ_STATE = 0x7AF4, |
| LVTMA_R500_LVDS_DATA_CNTL = 0x7AFC, |
| LVTMA_R500_MODE = 0x7B00, |
| LVTMA_R500_TRANSMITTER_ENABLE = 0x7B04, |
| LVTMA_R500_MACRO_CONTROL = 0x7B0C, |
| LVTMA_R500_TRANSMITTER_CONTROL = 0x7B10, |
| LVTMA_R500_REG_TEST_OUTPUT = 0x7B14, |
| /* R600 adds an undocumented register at 0x7AD8, |
| * shifting all subsequent registers by exactly one. */ |
| LVTMA_R600_DATA_SYNCHRONIZATION = 0x7ADC, |
| LVTMA_R600_PWRSEQ_REF_DIV = 0x7AE8, |
| LVTMA_R600_PWRSEQ_DELAY1 = 0x7AEC, |
| LVTMA_R600_PWRSEQ_DELAY2 = 0x7AF0, |
| LVTMA_R600_PWRSEQ_CNTL = 0x7AF4, |
| LVTMA_R600_PWRSEQ_STATE = 0x7AF8, |
| LVTMA_R600_LVDS_DATA_CNTL = 0x7B00, |
| LVTMA_R600_MODE = 0x7B04, |
| LVTMA_R600_TRANSMITTER_ENABLE = 0x7B08, |
| LVTMA_R600_MACRO_CONTROL = 0x7B10, |
| LVTMA_R600_TRANSMITTER_CONTROL = 0x7B14, |
| LVTMA_R600_REG_TEST_OUTPUT = 0x7B18, |
| LVTMA_TRANSMITTER_ADJUST = 0x7B24, /* RV630 */ |
| LVTMA_PREEMPHASIS_CONTROL = 0x7B28, /* RV630 */ |
| /* I2C in separate enum */ |
| /* HPD */ |
| DC_GPIO_HPD_MASK = 0x7E90, |
| DC_GPIO_HPD_A = 0x7E94, |
| DC_GPIO_HPD_EN = 0x7E98, |
| DC_GPIO_HPD_Y = 0x7E9C |
| }; |
| enum CONFIG_CNTL_BITS { |
| RS69_CFG_ATI_REV_ID_SHIFT = 8, |
| RS69_CFG_ATI_REV_ID_MASK = 0xF << RS69_CFG_ATI_REV_ID_SHIFT |
| }; |
| enum rv620Regs { |
| /* DAC common */ |
| RV620_DAC_COMPARATOR_MISC = 0x7da4, |
| RV620_DAC_COMPARATOR_OUTPUT = 0x7da8, |
| /* RV620 DAC A */ |
| RV620_DACA_ENABLE = 0x7000, |
| RV620_DACA_SOURCE_SELECT = 0x7004, |
| RV620_DACA_SYNC_TRISTATE_CONTROL = 0x7020, |
| /* RV620_DACA_SYNC_SELECT = 0x7024, ?? */ |
| RV620_DACA_AUTODETECT_CONTROL = 0x7028, |
| RV620_DACA_AUTODETECT_STATUS = 0x7034, |
| RV620_DACA_AUTODETECT_INT_CONTROL = 0x7038, |
| RV620_DACA_FORCE_OUTPUT_CNTL = 0x703C, |
| RV620_DACA_FORCE_DATA = 0x7040, |
| RV620_DACA_POWERDOWN = 0x7050, |
| /* RV620_DACA_CONTROL1 moved */ |
| RV620_DACA_CONTROL2 = 0x7058, |
| RV620_DACA_COMPARATOR_ENABLE = 0x705C, |
| /* RV620_DACA_COMPARATOR_OUTPUT changed */ |
| RV620_DACA_BGADJ_SRC = 0x7ef0, |
| RV620_DACA_MACRO_CNTL = 0x7ef4, |
| RV620_DACA_AUTO_CALIB_CONTROL = 0x7ef8, |
| /* DAC B */ |
| RV620_DACB_ENABLE = 0x7100, |
| RV620_DACB_SOURCE_SELECT = 0x7104, |
| RV620_DACB_SYNC_TRISTATE_CONTROL = 0x7120, |
| /* RV620_DACB_SYNC_SELECT = 0x7124, ?? */ |
| RV620_DACB_AUTODETECT_CONTROL = 0x7128, |
| RV620_DACB_AUTODETECT_STATUS = 0x7134, |
| RV620_DACB_AUTODETECT_INT_CONTROL = 0x7138, |
| RV620_DACB_FORCE_OUTPUT_CNTL = 0x713C, |
| RV620_DACB_FORCE_DATA = 0x7140, |
| RV620_DACB_POWERDOWN = 0x7150, |
| /* RV620_DACB_CONTROL1 moved */ |
| RV620_DACB_CONTROL2 = 0x7158, |
| RV620_DACB_COMPARATOR_ENABLE = 0x715C, |
| RV620_DACB_BGADJ_SRC = 0x7ef0, |
| RV620_DACB_MACRO_CNTL = 0x7ff4, |
| RV620_DACB_AUTO_CALIB_CONTROL = 0x7ef8, |
| /* DIG1 */ |
| RV620_DIG1_CNTL = 0x75A0, |
| RV620_DIG1_CLOCK_PATTERN = 0x75AC, |
| RV620_LVDS1_DATA_CNTL = 0x75BC, |
| RV620_TMDS1_CNTL = 0x75C0, |
| /* DIG2 */ |
| RV620_DIG2_CNTL = 0x79A0, |
| RV620_DIG2_CLOCK_PATTERN = 0x79AC, |
| RV620_LVDS2_DATA_CNTL = 0x79BC, |
| RV620_TMDS2_CNTL = 0x79C0, |
| /* RV62x I2C */ |
| RV62_GENERIC_I2C_CONTROL = 0x7d80, /* (RW) */ |
| RV62_GENERIC_I2C_INTERRUPT_CONTROL = 0x7d84, /* (RW) */ |
| RV62_GENERIC_I2C_STATUS = 0x7d88, /* (RW) */ |
| RV62_GENERIC_I2C_SPEED = 0x7d8c, /* (RW) */ |
| RV62_GENERIC_I2C_SETUP = 0x7d90, /* (RW) */ |
| RV62_GENERIC_I2C_TRANSACTION = 0x7d94, /* (RW) */ |
| RV62_GENERIC_I2C_DATA = 0x7d98, /* (RW) */ |
| RV62_GENERIC_I2C_PIN_SELECTION = 0x7d9c, /* (RW) */ |
| RV62_DC_GPIO_DDC4_MASK = 0x7e20, /* (RW) */ |
| RV62_DC_GPIO_DDC1_MASK = 0x7e40, /* (RW) */ |
| RV62_DC_GPIO_DDC2_MASK = 0x7e50, /* (RW) */ |
| RV62_DC_GPIO_DDC3_MASK = 0x7e60, /* (RW) */ |
| /* ?? */ |
| RV620_DCIO_LINK_STEER_CNTL = 0x7FA4, |
| RV620_LVTMA_TRANSMITTER_CONTROL= 0x7F00, |
| RV620_LVTMA_TRANSMITTER_ENABLE = 0x7F04, |
| RV620_LVTMA_TRANSMITTER_ADJUST = 0x7F18, |
| RV620_LVTMA_PREEMPHASIS_CONTROL= 0x7F1C, |
| RV620_LVTMA_MACRO_CONTROL = 0x7F0C, |
| RV620_LVTMA_DATA_SYNCHRONIZATION = 0x7F98, |
| RV620_FMT1_CONTROL = 0x6700, |
| RV620_FMT1_BIT_DEPTH_CONTROL= 0x6710, |
| RV620_FMT1_CLAMP_CNTL = 0x672C, |
| RV620_FMT2_CONTROL = 0x6F00, |
| RV620_FMT2_CNTL = 0x6F10, |
| RV620_FMT2_CLAMP_CNTL = 0x6F2C, |
| RV620_DCCG_PCLK_DIGA_CNTL = 0x04b0, |
| RV620_DCCG_PCLK_DIGB_CNTL = 0x04b4, |
| RV620_DCCG_SYMCLK_CNTL = 0x04b8 |
| }; |
| enum RV620_LVTMA_TRANSMITTER_CONTROL_BITS { |
| RV62_LVTMA_PLL_ENABLE = 1 << 0, |
| RV62_LVTMA_PLL_RESET = 1 << 1, |
| RV62_LVTMA_IDSCKSEL = 1 << 4, |
| RV62_LVTMA_BGSLEEP = 1 << 5, |
| RV62_LVTMA_IDCLK_SEL = 1 << 6, |
| RV62_LVTMA_TMCLK = 1 << 8, |
| RV62_LVTMA_TMCLK_FROM_PADS = 1 << 13, |
| RV62_LVTMA_TDCLK = 1 << 14, |
| RV62_LVTMA_TDCLK_FROM_PADS = 1 << 15, |
| RV62_LVTMA_BYPASS_PLL = 1 << 28, |
| RV62_LVTMA_USE_CLK_DATA = 1 << 29, |
| RV62_LVTMA_MODE = 1 << 30, |
| RV62_LVTMA_INPUT_TEST_CLK_SEL = 1 << 31 |
| }; |
| enum RV620_DCCG_SYMCLK_CNTL { |
| RV62_SYMCLKA_SRC_SHIFT = 8, |
| RV62_SYMCLKB_SRC_SHIFT = 12 |
| }; |
| enum RV620_DCCG_DIG_CNTL { |
| RV62_PCLK_DIGA_ON = 0x1 |
| }; |
| enum RV620_DCIO_LINK_STEER_CNTL { |
| RV62_LINK_STEER_SWAP = 1 << 0, |
| RV62_LINK_STEER_PLLSEL_OVERWRITE_EN = 1 << 16, |
| RV62_LINK_STEER_PLLSELA = 1 << 17, |
| RV62_LINK_STEER_PLLSELB = 1 << 18 |
| }; |
| enum R620_LVTMA_TRANSMITTER_ENABLE_BITS { |
| RV62_LVTMA_LNK0EN = 1 << 0, |
| RV62_LVTMA_LNK1EN = 1 << 1, |
| RV62_LVTMA_LNK2EN = 1 << 2, |
| RV62_LVTMA_LNK3EN = 1 << 3, |
| RV62_LVTMA_LNK4EN = 1 << 4, |
| RV62_LVTMA_LNK5EN = 1 << 5, |
| RV62_LVTMA_LNK6EN = 1 << 6, |
| RV62_LVTMA_LNK7EN = 1 << 7, |
| RV62_LVTMA_LNK8EN = 1 << 8, |
| RV62_LVTMA_LNK9EN = 1 << 9, |
| RV62_LVTMA_LNKL = RV62_LVTMA_LNK0EN | RV62_LVTMA_LNK1EN |
| | RV62_LVTMA_LNK2EN | RV62_LVTMA_LNK3EN, |
| RV62_LVTMA_LNKU = RV62_LVTMA_LNK4EN | RV62_LVTMA_LNK5EN |
| | RV62_LVTMA_LNK6EN | RV62_LVTMA_LNK7EN, |
| RV62_LVTMA_LNK_ALL = RV62_LVTMA_LNKL | RV62_LVTMA_LNKU |
| | RV62_LVTMA_LNK8EN | RV62_LVTMA_LNK9EN, |
| RV62_LVTMA_LNKEN_HPD_MASK = 1 << 16 |
| }; |
| enum RV620_LVTMA_DATA_SYNCHRONIZATION { |
| RV62_LVTMA_DSYNSEL = (1 << 0), |
| RV62_LVTMA_PFREQCHG = (1 << 8) |
| }; |
| enum RV620_DIG_CNTL_BITS { |
| /* 0x75A0 */ |
| RV62_DIG_SWAP = (0x1 << 16), |
| RV62_DIG_DUAL_LINK_ENABLE = (0x1 << 12), |
| RV62_DIG_START = (0x1 << 6), |
| RV62_DIG_MODE = (0x7 << 8), |
| RV62_DIG_STEREOSYNC_SELECT = (1 << 2), |
| RV62_DIG_SOURCE_SELECT = (1 << 0) |
| }; |
| enum RV620_DIG_LVDS_DATA_CNTL_BITS { |
| /* 0x75BC */ |
| RV62_LVDS_24BIT_ENABLE = (0x1 << 0), |
| RV62_LVDS_24BIT_FORMAT = (0x1 << 4) |
| }; |
| enum RV620_TMDS_CNTL_BITS { |
| /* 0x75C0 */ |
| RV62_TMDS_PIXEL_ENCODING = (0x1 << 4), |
| RV62_TMDS_COLOR_FORMAT = (0x3 << 8) |
| }; |
| enum RV620_FMT_BIT_DEPTH_CONTROL { |
| RV62_FMT_TRUNCATE_EN = 1 << 0, |
| RV62_FMT_TRUNCATE_DEPTH = 1 << 4, |
| RV62_FMT_SPATIAL_DITHER_EN = 1 << 8, |
| RV62_FMT_SPATIAL_DITHER_MODE = 1 << 9, |
| RV62_FMT_SPATIAL_DITHER_DEPTH = 1 << 12, |
| RV62_FMT_FRAME_RANDOM_ENABLE = 1 << 13, |
| RV62_FMT_RGB_RANDOM_ENABLE = 1 << 14, |
| RV62_FMT_HIGHPASS_RANDOM_ENABLE = 1 << 15, |
| RV62_FMT_TEMPORAL_DITHER_EN = 1 << 16, |
| RV62_FMT_TEMPORAL_DITHER_DEPTH = 1 << 20, |
| RV62_FMT_TEMPORAL_DITHER_OFFSET = 3 << 21, |
| RV62_FMT_TEMPORAL_LEVEL = 1 << 24, |
| RV62_FMT_TEMPORAL_DITHER_RESET = 1 << 25, |
| RV62_FMT_25FRC_SEL = 3 << 26, |
| RV62_FMT_50FRC_SEL = 3 << 28, |
| RV62_FMT_75FRC_SEL = 3 << 30 |
| }; |
| enum RV620_FMT_CONTROL { |
| RV62_FMT_PIXEL_ENCODING = 1 << 16 |
| }; |
| enum _r5xxMCRegs { |
| R5XX_MC_STATUS = 0x0000, |
| RV515_MC_FB_LOCATION = 0x0001, |
| R5XX_MC_FB_LOCATION = 0x0004, |
| RV515_MC_STATUS = 0x0008 |
| }; |
| enum _r5xxRegs { |
| /* I2C */ |
| R5_DC_I2C_STATUS1 = 0x7D30, /* (RW) */ |
| R5_DC_I2C_RESET = 0x7D34, /* (RW) */ |
| R5_DC_I2C_CONTROL1 = 0x7D38, /* (RW) */ |
| R5_DC_I2C_CONTROL2 = 0x7D3C, /* (RW) */ |
| R5_DC_I2C_CONTROL3 = 0x7D40, /* (RW) */ |
| R5_DC_I2C_DATA = 0x7D44, /* (RW) */ |
| R5_DC_I2C_INTERRUPT_CONTROL = 0x7D48, /* (RW) */ |
| R5_DC_I2C_ARBITRATION = 0x7D50, /* (RW) */ |
| R5_DC_GPIO_DDC1_MASK = 0x7E40, /* (RW) */ |
| R5_DC_GPIO_DDC1_A = 0x7E44, /* (RW) */ |
| R5_DC_GPIO_DDC1_EN = 0x7E48, /* (RW) */ |
| R5_DC_GPIO_DDC2_MASK = 0x7E50, /* (RW) */ |
| R5_DC_GPIO_DDC2_A = 0x7E54, /* (RW) */ |
| R5_DC_GPIO_DDC2_EN = 0x7E58, /* (RW) */ |
| R5_DC_GPIO_DDC3_MASK = 0x7E60, /* (RW) */ |
| R5_DC_GPIO_DDC3_A = 0x7E64, /* (RW) */ |
| R5_DC_GPIO_DDC3_EN = 0x7E68 /* (RW) */ |
| }; |
| enum _r5xxSPLLRegs { |
| SPLL_FUNC_CNTL = 0x0 /* (RW) */ |
| }; |
| enum _r6xxRegs { |
| /* MCLK */ |
| R6_MCLK_PWRMGT_CNTL = 0x620, |
| /* I2C */ |
| R6_DC_I2C_CONTROL = 0x7D30, /* (RW) */ |
| R6_DC_I2C_ARBITRATION = 0x7D34, /* (RW) */ |
| R6_DC_I2C_INTERRUPT_CONTROL = 0x7D38, /* (RW) */ |
| R6_DC_I2C_SW_STATUS = 0x7d3c, /* (RW) */ |
| R6_DC_I2C_DDC1_SPEED = 0x7D4C, /* (RW) */ |
| R6_DC_I2C_DDC1_SETUP = 0x7D50, /* (RW) */ |
| R6_DC_I2C_DDC2_SPEED = 0x7D54, /* (RW) */ |
| R6_DC_I2C_DDC2_SETUP = 0x7D58, /* (RW) */ |
| R6_DC_I2C_DDC3_SPEED = 0x7D5C, /* (RW) */ |
| R6_DC_I2C_DDC3_SETUP = 0x7D60, /* (RW) */ |
| R6_DC_I2C_TRANSACTION0 = 0x7D64, /* (RW) */ |
| R6_DC_I2C_TRANSACTION1 = 0x7D68, /* (RW) */ |
| R6_DC_I2C_DATA = 0x7D74, /* (RW) */ |
| R6_DC_I2C_DDC4_SPEED = 0x7DB4, /* (RW) */ |
| R6_DC_I2C_DDC4_SETUP = 0x7DBC, /* (RW) */ |
| R6_DC_GPIO_DDC4_MASK = 0x7E00, /* (RW) */ |
| R6_DC_GPIO_DDC4_A = 0x7E04, /* (RW) */ |
| R6_DC_GPIO_DDC4_EN = 0x7E08, /* (RW) */ |
| R6_DC_GPIO_DDC1_MASK = 0x7E40, /* (RW) */ |
| R6_DC_GPIO_DDC1_A = 0x7E44, /* (RW) */ |
| R6_DC_GPIO_DDC1_EN = 0x7E48, /* (RW) */ |
| R6_DC_GPIO_DDC1_Y = 0x7E4C, /* (RW) */ |
| R6_DC_GPIO_DDC2_MASK = 0x7E50, /* (RW) */ |
| R6_DC_GPIO_DDC2_A = 0x7E54, /* (RW) */ |
| R6_DC_GPIO_DDC2_EN = 0x7E58, /* (RW) */ |
| R6_DC_GPIO_DDC2_Y = 0x7E5C, /* (RW) */ |
| R6_DC_GPIO_DDC3_MASK = 0x7E60, /* (RW) */ |
| R6_DC_GPIO_DDC3_A = 0x7E64, /* (RW) */ |
| R6_DC_GPIO_DDC3_EN = 0x7E68, /* (RW) */ |
| R6_DC_GPIO_DDC3_Y = 0x7E6C /* (RW) */ |
| }; |
| enum R6_MCLK_PWRMGT_CNTL { |
| R6_MC_BUSY = (1 << 5) |
| }; |
| /* *_Q: questionbable */ |
| enum _rs69xRegs { |
| /* I2C */ |
| RS69_DC_I2C_CONTROL = 0x7D30, /* (RW) *//* */ |
| RS69_DC_I2C_UNKNOWN_2 = 0x7D34, /* (RW) */ |
| RS69_DC_I2C_INTERRUPT_CONTROL = 0x7D38, /* (RW) */ |
| RS69_DC_I2C_SW_STATUS = 0x7d3c, /* (RW) *//**/ |
| RS69_DC_I2C_UNKNOWN_1 = 0x7d40, |
| RS69_DC_I2C_DDC_SETUP_Q = 0x7D44, /* (RW) */ |
| RS69_DC_I2C_DATA = 0x7D58, /* (RW) *//**/ |
| RS69_DC_I2C_TRANSACTION0 = 0x7D48, /* (RW) *//**/ |
| RS69_DC_I2C_TRANSACTION1 = 0x7D4C, /* (RW) *//**/ |
| /* DDIA */ |
| RS69_DDIA_CNTL = 0x7200, |
| RS69_DDIA_SOURCE_SELECT = 0x7204, |
| RS69_DDIA_BIT_DEPTH_CONTROL = 0x7214, |
| RS69_DDIA_DCBALANCER_CONTROL = 0x7250, |
| RS69_DDIA_PATH_CONTROL = 0x7264, |
| RS69_DDIA_PCIE_LINK_CONTROL2 = 0x7278, |
| RS69_DDIA_PCIE_LINK_CONTROL3 = 0x727c, |
| RS69_DDIA_PCIE_PHY_CONTROL1 = 0x728c, |
| RS69_DDIA_PCIE_PHY_CONTROL2 = 0x7290 |
| }; |
| enum RS69_DDIA_CNTL_BITS { |
| RS69_DDIA_ENABLE = 1 << 0, |
| RS69_DDIA_HDMI_EN = 1 << 2, |
| RS69_DDIA_ENABLE_HPD_MASK = 1 << 4, |
| RS69_DDIA_HPD_SELECT = 1 << 8, |
| RS69_DDIA_SYNC_PHASE = 1 << 12, |
| RS69_DDIA_PIXEL_ENCODING = 1 << 16, |
| RS69_DDIA_DUAL_LINK_ENABLE = 1 << 24, |
| RS69_DDIA_SWAP = 1 << 28 |
| }; |
| enum RS69_DDIA_SOURCE_SELECT_BITS { |
| RS69_DDIA_SOURCE_SELECT_BIT = 1 << 0, |
| RS69_DDIA_SYNC_SELECT = 1 << 8, |
| RS69_DDIA_STEREOSYNC_SELECT = 1 << 16 |
| }; |
| enum RS69_DDIA_LINK_CONTROL2_SHIFT { |
| RS69_DDIA_PCIE_OUTPUT_MUX_SEL0 = 0, |
| RS69_DDIA_PCIE_OUTPUT_MUX_SEL1 = 4, |
| RS69_DDIA_PCIE_OUTPUT_MUX_SEL2 = 8, |
| RS69_DDIA_PCIE_OUTPUT_MUX_SEL3 = 12 |
| }; |
| enum RS69_DDIA_BIT_DEPTH_CONTROL_BITS { |
| RS69_DDIA_TRUNCATE_EN = 1 << 0, |
| RS69_DDIA_TRUNCATE_DEPTH = 1 << 4, |
| RS69_DDIA_SPATIAL_DITHER_EN = 1 << 8, |
| RS69_DDIA_SPATIAL_DITHER_DEPTH = 1 << 12, |
| RS69_DDIA_TEMPORAL_DITHER_EN = 1 << 16, |
| RS69_DDIA_TEMPORAL_DITHER_DEPTH = 1 << 20, |
| RS69_DDIA_TEMPORAL_LEVEL = 1 << 24, |
| RS69_DDIA_TEMPORAL_DITHER_RESET = 1 << 25 |
| }; |
| enum RS69_DDIA_DCBALANCER_CONTROL_BITS { |
| RS69_DDIA_DCBALANCER_EN = 1 << 0, |
| RS69_DDIA_SYNC_DCBAL_EN = 1 << 4, |
| RS69_DDIA_DCBALANCER_TEST_EN = 1 << 8, |
| RS69_DDIA_DCBALANCER_TEST_IN_SHIFT = 16, |
| RS69_DDIA_DCBALANCER_FORCE = 1 << 24 |
| }; |
| enum RS69_DDIA_PATH_CONTROL_BITS { |
| RS69_DDIA_PATH_SELECT_SHIFT = 0, |
| RS69_DDIA_DDPII_DE_ALIGN_EN = 1 << 4, |
| RS69_DDIA_DDPII_TRAIN_EN = 1 << 8, |
| RS69_DDIA_DDPII_TRAIN_SELECT = 1 << 12, |
| RS69_DDIA_DDPII_SCRAMBLE_EN = 1 << 16, |
| RS69_DDIA_REPL_MODE_SELECT = 1 << 20, |
| RS69_DDIA_RB_30b_SWAP_EN = 1 << 24, |
| RS69_DDIA_PIXVLD_RESET = 1 << 28, |
| RS69_DDIA_REARRANGER_EN = 1 << 30 |
| }; |
| enum RS69_DDIA_PCIE_LINK_CONTROL3_BITS { |
| RS69_DDIA_PCIE_MIRROR_EN = 1 << 0, |
| RS69_DDIA_PCIE_CFGDUALLINK = 1 << 4, |
| RS69_DDIA_PCIE_NCHG3EN = 1 << 8, |
| RS69_DDIA_PCIE_RX_PDNB_SHIFT = 12 |
| }; |
| enum RS69_MC_INDEX_BITS { |
| RS69_MC_IND_ADDR = (0x1 << 0), |
| RS69_C_IND_WR_EN = (0x1 << 9) |
| }; |
| enum _rs690MCRegs { |
| RS69_MC_SYSTEM_STATUS = 0x90, /* (RW) */ |
| RS69_MCCFG_FB_LOCATION = 0x100, |
| RS69MCCFG_AGP_LOCATION = 0x101 |
| }; |
| enum RS69_MC_SYSTEM_STATUS_BITS { |
| RS69_MC_SYSTEM_IDLE = (0x1 << 0), |
| RS69_MC_SEQUENCER_IDLE = (0x1 << 1), |
| RS69_MC_ARBITER_IDLE = (0x1 << 2), |
| RS69_MC_SELECT_PM = (0x1 << 3), |
| RS69_RESERVED4 = (0xf << 4), |
| RS69_RESERVED8 = (0xf << 8), |
| RS69_RESERVED12_SYSTEM_STATUS = (0xf << 12), |
| RS69_MCA_INIT_EXECUTED = (0x1 << 16), |
| RS69_MCA_IDLE = (0x1 << 17), |
| RS69_MCA_SEQ_IDLE = (0x1 << 18), |
| RS69_MCA_ARB_IDLE = (0x1 << 19), |
| RS69_RESERVED20_SYSTEM_STATUS = (0xfff << 20) |
| }; |
| enum R5XX_MC_STATUS_BITS { |
| R5XX_MEM_PWRUP_COMPL = (0x1 << 0), |
| R5XX_MC_IDLE = (0x1 << 1) |
| }; |
| enum RV515_MC_STATUS_BITS { |
| RV515_MC_IDLE = (0x1 << 4) |
| }; |
| enum BUS_CNTL_BITS { |
| /* BUS_CNTL */ |
| BUS_DBL_RESYNC = (0x1 << 0), |
| BIOS_ROM_WRT_EN = (0x1 << 1), |
| BIOS_ROM_DIS = (0x1 << 2), |
| PMI_IO_DIS = (0x1 << 3), |
| PMI_MEM_DIS = (0x1 << 4), |
| PMI_BM_DIS = (0x1 << 5), |
| PMI_INT_DIS = (0x1 << 6) |
| }; |
| enum SEPROM_SNTL1_BITS { |
| /* SEPROM_CNTL1 */ |
| WRITE_ENABLE = (0x1 << 0), |
| WRITE_DISABLE = (0x1 << 1), |
| READ_CONFIG = (0x1 << 2), |
| WRITE_CONFIG = (0x1 << 3), |
| READ_STATUS = (0x1 << 4), |
| SECT_TO_SRAM = (0x1 << 5), |
| READY_BUSY = (0x1 << 7), |
| SEPROM_BUSY = (0x1 << 8), |
| BCNT_OVER_WTE_EN = (0x1 << 9), |
| RB_MASKB = (0x1 << 10), |
| SOFT_RESET = (0x1 << 11), |
| STATE_IDLEb = (0x1 << 12), |
| SECTOR_ERASE = (0x1 << 13), |
| BYTE_CNT = (0xff << 16), |
| SCK_PRESCALE = (0xff << 24) |
| }; |
| enum VIPH_CONTROL_BITS { |
| /* VIPH_CONTROL */ |
| VIPH_CLK_SEL = (0xff << 0), |
| VIPH_REG_RDY = (0x1 << 13), |
| VIPH_MAX_WAIT = (0xf << 16), |
| VIPH_DMA_MODE = (0x1 << 20), |
| VIPH_EN = (0x1 << 21), |
| VIPH_DV0_WID = (0x1 << 24), |
| VIPH_DV1_WID = (0x1 << 25), |
| VIPH_DV2_WID = (0x1 << 26), |
| VIPH_DV3_WID = (0x1 << 27), |
| VIPH_PWR_DOWN = (0x1 << 28), |
| VIPH_PWR_DOWN_AK = (0x1 << 28), |
| VIPH_VIPCLK_DIS = (0x1 << 29) |
| }; |
| enum VGA_RENDER_CONTROL_BITS { |
| /* VGA_RENDER_CONTROL */ |
| VGA_BLINK_RATE = (0x1f << 0), |
| VGA_BLINK_MODE = (0x3 << 5), |
| VGA_CURSOR_BLINK_INVERT = (0x1 << 7), |
| VGA_EXTD_ADDR_COUNT_ENABLE = (0x1 << 8), |
| VGA_VSTATUS_CNTL = (0x3 << 16), |
| VGA_LOCK_8DOT = (0x1 << 24), |
| VGAREG_LINECMP_COMPATIBILITY_SEL = (0x1 << 25) |
| }; |
| enum D1VGA_CONTROL_BITS { |
| /* D1VGA_CONTROL */ |
| D1VGA_MODE_ENABLE = (0x1 << 0), |
| D1VGA_TIMING_SELECT = (0x1 << 8), |
| D1VGA_SYNC_POLARITY_SELECT = (0x1 << 9), |
| D1VGA_OVERSCAN_TIMING_SELECT = (0x1 << 10), |
| D1VGA_OVERSCAN_COLOR_EN = (0x1 << 16), |
| D1VGA_ROTATE = (0x3 << 24) |
| }; |
| enum D2VGA_CONTROL_BITS { |
| /* D2VGA_CONTROL */ |
| D2VGA_MODE_ENABLE = (0x1 << 0), |
| D2VGA_TIMING_SELECT = (0x1 << 8), |
| D2VGA_SYNC_POLARITY_SELECT = (0x1 << 9), |
| D2VGA_OVERSCAN_TIMING_SELECT = (0x1 << 10), |
| D2VGA_OVERSCAN_COLOR_EN = (0x1 << 16), |
| D2VGA_ROTATE = (0x3 << 24) |
| }; |
| enum { |
| /* CLOCK_CNTL_INDEX */ |
| PLL_ADDR = (0x3f << 0), |
| PLL_WR_EN = (0x1 << 7), |
| PPLL_DIV_SEL = (0x3 << 8), |
| /* CLOCK_CNTL_DATA */ |
| #define PLL_DATA 0xffffffff |
| /* SPLL_FUNC_CNTL */ |
| SPLL_CHG_STATUS = (0x1 << 29), |
| SPLL_BYPASS_EN = (0x1 << 25), |
| /* MC_IND_INDEX */ |
| MC_IND_ADDR = (0xffff << 0), |
| MC_IND_SEQ_RBS_0 = (0x1 << 16), |
| MC_IND_SEQ_RBS_1 = (0x1 << 17), |
| MC_IND_SEQ_RBS_2 = (0x1 << 18), |
| MC_IND_SEQ_RBS_3 = (0x1 << 19), |
| MC_IND_AIC_RBS = (0x1 << 20), |
| MC_IND_CITF_ARB0 = (0x1 << 21), |
| MC_IND_CITF_ARB1 = (0x1 << 22), |
| MC_IND_WR_EN = (0x1 << 23), |
| MC_IND_RD_INV = (0x1 << 24) |
| #define MC_IND_ALL (MC_IND_SEQ_RBS_0 | MC_IND_SEQ_RBS_1 \ |
| | MC_IND_SEQ_RBS_2 | MC_IND_SEQ_RBS_3 \ |
| | MC_IND_AIC_RBS | MC_IND_CITF_ARB0 | MC_IND_CITF_ARB1) |
| /* MC_IND_DATA */ |
| #define MC_IND_DATA_BIT 0xffffffff |
| }; |
| #endif /* _RHD_REGS_H */ |
| /drivers/old/ati2d/vs_prog.inc |
|---|
| 0,0 → 1,566 |
| typedef unsigned int u32_t; |
| typedef enum |
| { |
| VS_OUT_POS = 0, |
| VS_OUT_PSIZE, |
| VS_OUT_COL0, |
| VS_OUT_COL1, |
| VS_OUT_COL2, |
| VS_OUT_COL3, |
| VS_OUT_TEX0, |
| VS_OUT_TEX1, |
| VS_OUT_TEX2, |
| VS_OUT_TEX3, |
| VS_OUT_TEX4, |
| VS_OUT_TEX5, |
| VS_OUT_TEX6, |
| VS_OUT_TEX7, |
| VS_OUT_FOG, |
| VS_OUT_MAX = 0xFFFFFFFF |
| }v_out_t; |
| #if 0 |
| vs_1_1 |
| dcl_position v0 |
| dcl_color v1 |
| dcl_color1 v2 |
| dcl_fog v3 |
| dcl_psize v4 |
| dcl_texcoord v5 |
| dcl_texcoord1 v6 |
| mov oPos, v0 |
| mov oD0, v1 |
| mov oD1, v2 |
| mov oFog, v3.x |
| mov oPts, v4.x |
| mov oT0, v5 |
| mov oT1, v6 |
| #endif |
| const u32_t vs11[] = |
| { |
| 0xfffe0101, 0x0000001f, 0x80000000, 0x900f0000, 0x0000001f, 0x8000000a, |
| 0x900f0001, 0x0000001f, 0x8001000a, 0x900f0002, 0x0000001f, 0x8000000b, |
| 0x900f0003, 0x0000001f, 0x80000004, 0x900f0004, 0x0000001f, 0x80000005, |
| 0x900f0005, 0x0000001f, 0x80010005, 0x900f0006, 0x00000001, 0xc00f0000, |
| 0x90e40000, 0x00000001, 0xd00f0000, 0x90e40001, 0x00000001, 0xd00f0001, |
| 0x90e40002, 0x00000001, 0xc00f0001, 0x90000003, 0x00000001, 0xc00f0002, |
| 0x90000004, 0x00000001, 0xe00f0000, 0x90e40005, 0x00000001, 0xe00f0001, |
| 0x90e40006, 0x0000ffff |
| }; |
| char *sz_vs_command[] = |
| { |
| "nop", |
| "mov", |
| "add", |
| "sub", |
| "mad", |
| "mul", |
| "rcp", |
| "rsq", |
| "dp3", |
| "dp4", |
| "min", |
| "max", |
| "slt", |
| "sge", |
| "exp", |
| "log", |
| "lit", |
| "dst", |
| "lrp", |
| "frc", |
| "m4x4", |
| "m4x3", |
| "m3x4", |
| "m3x3", |
| "m3x2", |
| }; |
| /* |
| char *sz_ps_command[] = |
| { |
| texcoord |
| texkill |
| tex |
| texbem |
| texbeml |
| texreg2ar |
| texreg2gb |
| texm3x2pad |
| texm3x3tex |
| texm3x3pad |
| texm3x3tex |
| texm3x3diff |
| texm3x3spec |
| texm3x3vspec |
| expp |
| logp |
| cnd |
| def |
| texreg2rgb |
| texdp3tex |
| texm3x2depth |
| texdp3 |
| texm3x3 |
| texdepth |
| cmp |
| bem |
| } |
| */ |
| char *szusage[]= |
| { |
| "position", |
| "blendweight", |
| "blendindices", |
| "normal", |
| "psize", |
| "texcoord", |
| "tangent", |
| "binormal", |
| "tessfactor", |
| "positiont", |
| "color", |
| "fog", |
| "depth", |
| "sample" |
| }; |
| char *sztype[]= |
| { |
| "r", |
| "v", |
| "c" |
| "a", |
| "t", |
| "rasout", |
| "attrout", |
| "texcrdout", |
| "output", |
| "constint", |
| "colorout", |
| "depthout", |
| "sampler", |
| "const2", |
| "const3", |
| "const4", |
| "constbool", |
| "loop", |
| "tempfloat16", |
| "misctype", |
| "label", |
| "predicate" |
| }; |
| typedef struct |
| { |
| u32_t minor: 8; |
| u32_t major: 8; |
| u32_t type :16; |
| }version_t; |
| typedef struct |
| { |
| u32_t type:5; |
| u32_t rsv :11; |
| u32_t ind :4; |
| u32_t rsv2:11; |
| u32_t sign:1; |
| }usage_t; |
| typedef struct |
| { |
| u32_t ind :11; |
| u32_t typeh :2; |
| u32_t rsv :3; |
| u32_t wr :4; |
| u32_t mod :4; |
| u32_t scale :4; |
| u32_t typel :3; |
| u32_t sign :1; |
| }dst_t; |
| typedef struct |
| { |
| u32_t ind :11; |
| u32_t rsv :5; |
| u32_t swzl :8; |
| u32_t mod :4; |
| u32_t typel :3; |
| u32_t sign :1; |
| }src_t; |
| int parse_vs(const u32_t *stream); |
| static void assign_outputs(); |
| int translate_vs(const u32_t *stream); |
| u32_t vs_out_written; |
| u32_t inp_mask; |
| u32_t vs_outputs[16]; |
| int main() |
| { |
| version_t *ver; |
| ver = (version_t*)vs11; |
| if(ver->type == 0xFFFE) |
| { |
| printf("vs_%d_%d\n\n",ver->major,ver->minor); |
| if( parse_vs(vs11+1) ) |
| translate_vs(vs11+1); |
| }; |
| return 0; |
| }; |
| static char txt_swzl[4] = {'x','y','z','w'}; |
| static char *txt_mod[2] = { "","_sat"}; |
| int parse_vs(const u32_t *stream) |
| { |
| dst_t *dst; |
| src_t *src; |
| u32_t swzl; |
| u32_t wr; |
| char szswzl[5]; |
| char szwm[5]; |
| int i,j; |
| while(1) |
| { |
| op_type_t instr = *stream++ & 0xFFFF; |
| switch( instr ) |
| { |
| case D3DSIO_MOV: |
| dst = (dst_t*)stream++; |
| src = (src_t*)stream++; |
| swzl = src->swzl; |
| wr = dst->wr; |
| for(i=0,j=0; i < 4; i++) |
| { |
| szswzl[i] = txt_swzl[swzl&3]; |
| swzl>>=2; |
| if(wr & (1<<i)) |
| szwm[j++] = txt_swzl[i]; |
| }; |
| szswzl[4] = 0; |
| szwm[j] = 0; |
| switch(dst->typel) |
| { |
| case 4: // Rasterizer Register File |
| if(dst->ind == 0) |
| vs_out_written |= (1 << VS_OUT_POS); |
| else if (dst->ind == 1) |
| vs_out_written |= (1 << VS_OUT_FOG); |
| else if (dst->ind == 2) |
| vs_out_written |= (1 << VS_OUT_PSIZE); |
| else |
| printf("invalid raster register %d",dst->ind); |
| break; |
| case 5: // Attribute Output Register File |
| if(dst->ind == 0) |
| vs_out_written |= (1 << VS_OUT_COL0); |
| else if (dst->ind == 1) |
| vs_out_written |= (1 << VS_OUT_COL1); |
| else |
| printf("invalid attribute register %d",dst->ind); |
| break; |
| case 6: // Texture Coordinate Output Register File |
| if(dst->ind < 8) |
| vs_out_written |= (1 << (VS_OUT_TEX0+dst->ind)); |
| else |
| printf("invalid texture register %d",dst->ind); |
| }; |
| printf("%s%s %s%d.%s,\t %s%d.%s\n",sz_vs_command[instr],txt_mod[dst->mod], |
| sztype[dst->typel],dst->ind,szwm, |
| sztype[src->typel],src->ind,szswzl); |
| break; |
| case D3DSIO_DCL: |
| parse_dcl(stream); |
| stream+=2; |
| break; |
| case 0xFFFF: |
| return 1; |
| default: |
| return 0; |
| }; |
| }; |
| }; |
| int parse_dcl(const u32_t *stream) |
| { |
| usage_t *usage; |
| dst_t *dst; |
| int dsttype; |
| char szwm[5]; |
| int i; |
| u32_t wr; |
| usage = (usage_t*)stream++; |
| dst = (dst_t*)stream++; |
| dsttype = (dst->typeh << 4) | dst->typel; |
| wr = dst->wr; |
| for(i=0; wr; i++, wr>>=1) |
| { |
| if(wr & 1) |
| szwm[i] = txt_swzl[i]; |
| }; |
| szwm[i] = 0; |
| printf("dcl_%s%d \t\t %s%d.%s\n",szusage[usage->type],usage->ind, |
| sztype[dsttype],dst->ind, szwm); |
| return 2; |
| } |
| int translate_dcl(const u32_t *stream); |
| int translate_mov(const u32_t *stream); |
| int translate_vs(const u32_t *stream) |
| { |
| assign_outputs(); |
| while(1) |
| { |
| op_type_t instr = *stream++ & 0xFFFF; |
| switch( instr ) |
| { |
| case D3DSIO_MOV: |
| translate_mov(stream); |
| stream+=2; |
| break; |
| case D3DSIO_DCL: |
| translate_dcl(stream); |
| stream+=2; |
| break; |
| case 0xFFFF: |
| return 1; |
| default: |
| return 0; |
| }; |
| }; |
| }; |
| int translate_dcl(const u32_t *stream) |
| { |
| return 1; |
| }; |
| u32_t inst[4]; |
| #include "r300_vertprog.h" |
| /** |
| * Swizzle indexes. |
| * Do not change! |
| */ |
| /*@{*/ |
| #define SWIZZLE_X 0 |
| #define SWIZZLE_Y 1 |
| #define SWIZZLE_Z 2 |
| #define SWIZZLE_W 3 |
| #define SWIZZLE_ZERO 4 /**< For SWZ instruction only */ |
| #define SWIZZLE_ONE 5 /**< For SWZ instruction only */ |
| #define SWIZZLE_NIL 7 /**< used during shader code gen (undefined value) */ |
| /*@}*/ |
| #define __CONST(x, y) \ |
| (PVS_SRC_OPERAND(t_src_index(vp, &src[x]), \ |
| t_swizzle(y), \ |
| t_swizzle(y), \ |
| t_swizzle(y), \ |
| t_swizzle(y), \ |
| t_src_class(src[x].File), \ |
| VSF_FLAG_NONE) | (src[x].RelAddr << 4)) |
| static unsigned long t_swizzle(u32_t swizzle) |
| { |
| /* this is in fact a NOP as the Mesa SWIZZLE_* are all identical to VSF_IN_COMPONENT_* */ |
| return swizzle; |
| } |
| static unsigned long t_dst_mask(u32_t mask) |
| { |
| /* WRITEMASK_* is equivalent to VSF_FLAG_* */ |
| return mask & VSF_FLAG_ALL; |
| } |
| static unsigned long t_dst_class(int file) |
| { |
| switch (file) { |
| case 0: //D3DSPR_TEMP |
| return PVS_DST_REG_TEMPORARY; |
| case 3: //D3DSPR_ADDR |
| return PVS_DST_REG_A0; |
| case 4: //D3DSPR_RASTOUT |
| case 5: |
| case 6: //D3DSPR_TEXCRDOUT |
| return PVS_DST_REG_OUT; |
| /* |
| case PROGRAM_INPUT: |
| case PROGRAM_LOCAL_PARAM: |
| case PROGRAM_ENV_PARAM: |
| case PROGRAM_NAMED_PARAM: |
| case PROGRAM_STATE_VAR: |
| case PROGRAM_WRITE_ONLY: |
| case PROGRAM_ADDRESS: |
| */ |
| default: |
| printf("problem in %s", __FUNCTION__); |
| return -1; |
| } |
| } |
| static unsigned long t_dst_index(dst_t *dst) |
| { |
| switch(dst->typel) |
| { |
| case 4: |
| if(dst->ind == 0) |
| return vs_outputs[VS_OUT_POS]; |
| else if (dst->ind == 1) |
| return vs_outputs[VS_OUT_FOG]; |
| else if (dst->ind == 2) |
| return vs_outputs[VS_OUT_PSIZE]; |
| break; |
| case 5: |
| if(dst->ind == 0) |
| return vs_outputs[VS_OUT_COL0]; |
| else if (dst->ind == 1) |
| return vs_outputs[VS_OUT_COL1]; |
| case 6: |
| return vs_outputs[VS_OUT_TEX0+dst->ind]; |
| default: |
| return dst->ind; |
| } |
| } |
| static void assign_outputs() |
| { |
| int i; |
| int cur_reg = 0; |
| for (i = 0; i < 16; i++) |
| vs_outputs[i] = -1; |
| // assert(vs_out_written & (1 << VS_OUT_POS)); |
| if (vs_out_written & (1 << VS_OUT_POS)) { |
| vs_outputs[VS_OUT_POS] = cur_reg++; |
| } |
| if (vs_out_written & (1 << VS_OUT_PSIZE)) { |
| vs_outputs[VS_OUT_PSIZE] = cur_reg++; |
| } |
| if (vs_out_written & (1 << VS_OUT_COL0)) { |
| vs_outputs[VS_OUT_COL0] = cur_reg++; |
| } |
| if (vs_out_written & (1 << VS_OUT_COL1)) { |
| vs_outputs[VS_OUT_COL1] = vs_outputs[VS_OUT_COL0] + 1; // ??? |
| cur_reg = vs_outputs[VS_OUT_COL1] + 1; |
| } |
| #if 0 |
| if (vp->key.OutputsWritten & (1 << VERT_RESULT_FOGC)) { //fog must be in |
| vp->outputs[VERT_RESULT_FOGC] = cur_reg++; //one of the color regs |
| } |
| #endif |
| for (i = VS_OUT_TEX0; i <= VS_OUT_TEX7; i++) { |
| if (vs_out_written & (1 << i)) { |
| vs_outputs[i] = cur_reg++; |
| } |
| } |
| } |
| int translate_mov(const u32_t *stream) |
| { |
| dst_t *dst = (dst_t*)stream++; |
| src_t *src = (src_t*)stream++; |
| int swzl = src->swzl; |
| int wr = dst->wr; |
| inst[0] = PVS_OP_DST_OPERAND(VE_ADD, |
| 0, |
| 0, |
| t_dst_index(dst), |
| (dst->wr), |
| t_dst_class(dst->typel)); |
| //inst[1] = t_src(vp, &src[0]); |
| // inst[2] = __CONST(0, SWIZZLE_ZERO); |
| //inst[3] = __CONST(0, SWIZZLE_ZERO); |
| printf("inst_0 %x\n", inst[0]); |
| return 1; |
| } |
| /* |
| static GLuint *r300TranslateOpcodeMOV(struct r300_vertex_program *vp, |
| struct prog_instruction *vpi, |
| GLuint * inst, |
| struct prog_src_register src[3]) |
| { |
| //ADD RESULT 1.X Y Z W PARAM 0{} {X Y Z W} PARAM 0{} {ZERO ZERO ZERO ZERO} |
| inst[0] = PVS_OP_DST_OPERAND(VE_ADD, |
| GL_FALSE, |
| GL_FALSE, |
| t_dst_index(vp, &vpi->DstReg), |
| t_dst_mask(vpi->DstReg.WriteMask), |
| t_dst_class(vpi->DstReg.File)); |
| inst[1] = t_src(vp, &src[0]); |
| inst[2] = __CONST(0, SWIZZLE_ZERO); |
| inst[3] = __CONST(0, SWIZZLE_ZERO); |
| return inst; |
| } |
| */ |
| /drivers/video/ati2d/ati_pciids_gen.h |
|---|
| File deleted |
| /drivers/video/ati2d/vs_prog.inc |
|---|
| File deleted |
| /drivers/video/ati2d/radeon_reg.h |
|---|
| File deleted |
| /drivers/video/ati2d/blend.inc |
|---|
| File deleted |
| /drivers/video/ati2d/pci.c |
|---|
| File deleted |
| /drivers/video/ati2d/ati_mem.c |
|---|
| File deleted |
| /drivers/video/ati2d/r500.inc |
|---|
| File deleted |
| /drivers/video/ati2d/clip.inc |
|---|
| File deleted |
| /drivers/video/ati2d/init_3d.inc |
|---|
| File deleted |
| /drivers/video/ati2d/r5xx_2dregs.h |
|---|
| File deleted |
| /drivers/video/ati2d/atihw.h |
|---|
| File deleted |
| /drivers/video/ati2d/accel_2d.inc |
|---|
| File deleted |
| /drivers/video/ati2d/accel_3d.inc |
|---|
| File deleted |
| /drivers/video/ati2d/radeon_chipset_gen.h |
|---|
| File deleted |
| /drivers/video/ati2d/radeon_chipinfo_gen.h |
|---|
| File deleted |
| /drivers/video/ati2d/pixmap.inc |
|---|
| File deleted |
| /drivers/video/ati2d/init_cp.c |
|---|
| File deleted |
| /drivers/video/ati2d/ati2d.lk |
|---|
| File deleted |
| /drivers/video/ati2d/r5xx_regs.h |
|---|
| File deleted |
| /drivers/video/ati2d/makefile |
|---|
| File deleted |
| /drivers/video/ati2d/radeon_microcode.h |
|---|
| File deleted |
| /drivers/video/ati2d/accel_2d.h |
|---|
| File deleted |
| /drivers/video/ati2d/rhd_regs.h |
|---|
| File deleted |
| /drivers/video/ati2d/init.c |
|---|
| File deleted |
| /drivers/video/ati2d/ati2d.c |
|---|
| File deleted |