| /drivers/video/drm/include/drm_crtc.h |
|---|
| 0,0 → 1,739 |
| /* |
| * Copyright © 2006 Keith Packard |
| * Copyright © 2007-2008 Dave Airlie |
| * Copyright © 2007-2008 Intel Corporation |
| * Jesse Barnes <jesse.barnes@intel.com> |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice shall be included in |
| * all copies or substantial portions of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| * OTHER DEALINGS IN THE SOFTWARE. |
| */ |
| #ifndef __DRM_CRTC_H__ |
| #define __DRM_CRTC_H__ |
| //#include <linux/i2c.h> |
| //#include <linux/spinlock.h> |
| //#include <linux/types.h> |
| //#include <linux/idr.h> |
| //#include <linux/fb.h> |
| struct drm_device; |
| struct drm_mode_set; |
| struct drm_framebuffer; |
| #define DRM_MODE_OBJECT_CRTC 0xcccccccc |
| #define DRM_MODE_OBJECT_CONNECTOR 0xc0c0c0c0 |
| #define DRM_MODE_OBJECT_ENCODER 0xe0e0e0e0 |
| #define DRM_MODE_OBJECT_MODE 0xdededede |
| #define DRM_MODE_OBJECT_PROPERTY 0xb0b0b0b0 |
| #define DRM_MODE_OBJECT_FB 0xfbfbfbfb |
| #define DRM_MODE_OBJECT_BLOB 0xbbbbbbbb |
| struct drm_mode_object { |
| uint32_t id; |
| uint32_t type; |
| }; |
| /* |
| * Note on terminology: here, for brevity and convenience, we refer to connector |
| * control chips as 'CRTCs'. They can control any type of connector, VGA, LVDS, |
| * DVI, etc. And 'screen' refers to the whole of the visible display, which |
| * may span multiple monitors (and therefore multiple CRTC and connector |
| * structures). |
| */ |
| enum drm_mode_status { |
| MODE_OK = 0, /* Mode OK */ |
| MODE_HSYNC, /* hsync out of range */ |
| MODE_VSYNC, /* vsync out of range */ |
| MODE_H_ILLEGAL, /* mode has illegal horizontal timings */ |
| MODE_V_ILLEGAL, /* mode has illegal horizontal timings */ |
| MODE_BAD_WIDTH, /* requires an unsupported linepitch */ |
| MODE_NOMODE, /* no mode with a maching name */ |
| MODE_NO_INTERLACE, /* interlaced mode not supported */ |
| MODE_NO_DBLESCAN, /* doublescan mode not supported */ |
| MODE_NO_VSCAN, /* multiscan mode not supported */ |
| MODE_MEM, /* insufficient video memory */ |
| MODE_VIRTUAL_X, /* mode width too large for specified virtual size */ |
| MODE_VIRTUAL_Y, /* mode height too large for specified virtual size */ |
| MODE_MEM_VIRT, /* insufficient video memory given virtual size */ |
| MODE_NOCLOCK, /* no fixed clock available */ |
| MODE_CLOCK_HIGH, /* clock required is too high */ |
| MODE_CLOCK_LOW, /* clock required is too low */ |
| MODE_CLOCK_RANGE, /* clock/mode isn't in a ClockRange */ |
| MODE_BAD_HVALUE, /* horizontal timing was out of range */ |
| MODE_BAD_VVALUE, /* vertical timing was out of range */ |
| MODE_BAD_VSCAN, /* VScan value out of range */ |
| MODE_HSYNC_NARROW, /* horizontal sync too narrow */ |
| MODE_HSYNC_WIDE, /* horizontal sync too wide */ |
| MODE_HBLANK_NARROW, /* horizontal blanking too narrow */ |
| MODE_HBLANK_WIDE, /* horizontal blanking too wide */ |
| MODE_VSYNC_NARROW, /* vertical sync too narrow */ |
| MODE_VSYNC_WIDE, /* vertical sync too wide */ |
| MODE_VBLANK_NARROW, /* vertical blanking too narrow */ |
| MODE_VBLANK_WIDE, /* vertical blanking too wide */ |
| MODE_PANEL, /* exceeds panel dimensions */ |
| MODE_INTERLACE_WIDTH, /* width too large for interlaced mode */ |
| MODE_ONE_WIDTH, /* only one width is supported */ |
| MODE_ONE_HEIGHT, /* only one height is supported */ |
| MODE_ONE_SIZE, /* only one resolution is supported */ |
| MODE_NO_REDUCED, /* monitor doesn't accept reduced blanking */ |
| MODE_UNVERIFIED = -3, /* mode needs to reverified */ |
| MODE_BAD = -2, /* unspecified reason */ |
| MODE_ERROR = -1 /* error condition */ |
| }; |
| #define DRM_MODE_TYPE_CLOCK_CRTC_C (DRM_MODE_TYPE_CLOCK_C | \ |
| DRM_MODE_TYPE_CRTC_C) |
| #define DRM_MODE(nm, t, c, hd, hss, hse, ht, hsk, vd, vss, vse, vt, vs, f) \ |
| .name = nm, .status = 0, .type = (t), .clock = (c), \ |
| .hdisplay = (hd), .hsync_start = (hss), .hsync_end = (hse), \ |
| .htotal = (ht), .hskew = (hsk), .vdisplay = (vd), \ |
| .vsync_start = (vss), .vsync_end = (vse), .vtotal = (vt), \ |
| .vscan = (vs), .flags = (f), .vrefresh = 0 |
| #define CRTC_INTERLACE_HALVE_V 0x1 /* halve V values for interlacing */ |
| struct drm_display_mode { |
| /* Header */ |
| // struct list_head head; |
| struct drm_mode_object base; |
| char name[DRM_DISPLAY_MODE_LEN]; |
| int connector_count; |
| enum drm_mode_status status; |
| int type; |
| /* Proposed mode values */ |
| int clock; |
| int hdisplay; |
| int hsync_start; |
| int hsync_end; |
| int htotal; |
| int hskew; |
| int vdisplay; |
| int vsync_start; |
| int vsync_end; |
| int vtotal; |
| int vscan; |
| unsigned int flags; |
| /* Addressable image size (may be 0 for projectors, etc.) */ |
| int width_mm; |
| int height_mm; |
| /* Actual mode we give to hw */ |
| int clock_index; |
| int synth_clock; |
| int crtc_hdisplay; |
| int crtc_hblank_start; |
| int crtc_hblank_end; |
| int crtc_hsync_start; |
| int crtc_hsync_end; |
| int crtc_htotal; |
| int crtc_hskew; |
| int crtc_vdisplay; |
| int crtc_vblank_start; |
| int crtc_vblank_end; |
| int crtc_vsync_start; |
| int crtc_vsync_end; |
| int crtc_vtotal; |
| int crtc_hadjusted; |
| int crtc_vadjusted; |
| /* Driver private mode info */ |
| int private_size; |
| int *private; |
| int private_flags; |
| int vrefresh; |
| float hsync; |
| }; |
| enum drm_connector_status { |
| connector_status_connected = 1, |
| connector_status_disconnected = 2, |
| connector_status_unknown = 3, |
| }; |
| enum subpixel_order { |
| SubPixelUnknown = 0, |
| SubPixelHorizontalRGB, |
| SubPixelHorizontalBGR, |
| SubPixelVerticalRGB, |
| SubPixelVerticalBGR, |
| SubPixelNone, |
| }; |
| /* |
| * Describes a given display (e.g. CRT or flat panel) and its limitations. |
| */ |
| struct drm_display_info { |
| char name[DRM_DISPLAY_INFO_LEN]; |
| /* Input info */ |
| bool serration_vsync; |
| bool sync_on_green; |
| bool composite_sync; |
| bool separate_syncs; |
| bool blank_to_black; |
| unsigned char video_level; |
| bool digital; |
| /* Physical size */ |
| unsigned int width_mm; |
| unsigned int height_mm; |
| /* Display parameters */ |
| unsigned char gamma; /* FIXME: storage format */ |
| bool gtf_supported; |
| bool standard_color; |
| enum { |
| monochrome = 0, |
| rgb, |
| other, |
| unknown, |
| } display_type; |
| bool active_off_supported; |
| bool suspend_supported; |
| bool standby_supported; |
| /* Color info FIXME: storage format */ |
| unsigned short redx, redy; |
| unsigned short greenx, greeny; |
| unsigned short bluex, bluey; |
| unsigned short whitex, whitey; |
| /* Clock limits FIXME: storage format */ |
| unsigned int min_vfreq, max_vfreq; |
| unsigned int min_hfreq, max_hfreq; |
| unsigned int pixel_clock; |
| /* White point indices FIXME: storage format */ |
| unsigned int wpx1, wpy1; |
| unsigned int wpgamma1; |
| unsigned int wpx2, wpy2; |
| unsigned int wpgamma2; |
| enum subpixel_order subpixel_order; |
| char *raw_edid; /* if any */ |
| }; |
| struct drm_framebuffer_funcs { |
| void (*destroy)(struct drm_framebuffer *framebuffer); |
| int (*create_handle)(struct drm_framebuffer *fb, |
| struct drm_file *file_priv, |
| unsigned int *handle); |
| }; |
| struct drm_framebuffer { |
| struct drm_device *dev; |
| // struct list_head head; |
| struct drm_mode_object base; |
| const struct drm_framebuffer_funcs *funcs; |
| unsigned int pitch; |
| unsigned int width; |
| unsigned int height; |
| /* depth can be 15 or 16 */ |
| unsigned int depth; |
| int bits_per_pixel; |
| int flags; |
| void *fbdev; |
| u32_t pseudo_palette[17]; |
| // struct list_head filp_head; |
| }; |
| struct drm_property_blob { |
| struct drm_mode_object base; |
| // struct list_head head; |
| unsigned int length; |
| void *data; |
| }; |
| struct drm_property_enum { |
| uint64_t value; |
| // struct list_head head; |
| char name[DRM_PROP_NAME_LEN]; |
| }; |
| struct drm_property { |
| // struct list_head head; |
| struct drm_mode_object base; |
| uint32_t flags; |
| char name[DRM_PROP_NAME_LEN]; |
| uint32_t num_values; |
| uint64_t *values; |
| // struct list_head enum_blob_list; |
| }; |
| struct drm_crtc; |
| struct drm_connector; |
| struct drm_encoder; |
| /** |
| * drm_crtc_funcs - control CRTCs for a given device |
| * @dpms: control display power levels |
| * @save: save CRTC state |
| * @resore: restore CRTC state |
| * @lock: lock the CRTC |
| * @unlock: unlock the CRTC |
| * @shadow_allocate: allocate shadow pixmap |
| * @shadow_create: create shadow pixmap for rotation support |
| * @shadow_destroy: free shadow pixmap |
| * @mode_fixup: fixup proposed mode |
| * @mode_set: set the desired mode on the CRTC |
| * @gamma_set: specify color ramp for CRTC |
| * @destroy: deinit and free object. |
| * |
| * The drm_crtc_funcs structure is the central CRTC management structure |
| * in the DRM. Each CRTC controls one or more connectors (note that the name |
| * CRTC is simply historical, a CRTC may control LVDS, VGA, DVI, TV out, etc. |
| * connectors, not just CRTs). |
| * |
| * Each driver is responsible for filling out this structure at startup time, |
| * in addition to providing other modesetting features, like i2c and DDC |
| * bus accessors. |
| */ |
| struct drm_crtc_funcs { |
| /* Save CRTC state */ |
| void (*save)(struct drm_crtc *crtc); /* suspend? */ |
| /* Restore CRTC state */ |
| void (*restore)(struct drm_crtc *crtc); /* resume? */ |
| /* cursor controls */ |
| int (*cursor_set)(struct drm_crtc *crtc, struct drm_file *file_priv, |
| uint32_t handle, uint32_t width, uint32_t height); |
| int (*cursor_move)(struct drm_crtc *crtc, int x, int y); |
| /* Set gamma on the CRTC */ |
| void (*gamma_set)(struct drm_crtc *crtc, u16_t *r, u16_t *g, u16_t *b, |
| uint32_t size); |
| /* Object destroy routine */ |
| void (*destroy)(struct drm_crtc *crtc); |
| int (*set_config)(struct drm_mode_set *set); |
| }; |
| /** |
| * drm_crtc - central CRTC control structure |
| * @enabled: is this CRTC enabled? |
| * @x: x position on screen |
| * @y: y position on screen |
| * @desired_mode: new desired mode |
| * @desired_x: desired x for desired_mode |
| * @desired_y: desired y for desired_mode |
| * @funcs: CRTC control functions |
| * |
| * Each CRTC may have one or more connectors associated with it. This structure |
| * allows the CRTC to be controlled. |
| */ |
| struct drm_crtc { |
| struct drm_device *dev; |
| // struct list_head head; |
| struct drm_mode_object base; |
| /* framebuffer the connector is currently bound to */ |
| struct drm_framebuffer *fb; |
| bool enabled; |
| struct drm_display_mode mode; |
| int x, y; |
| struct drm_display_mode *desired_mode; |
| int desired_x, desired_y; |
| const struct drm_crtc_funcs *funcs; |
| /* CRTC gamma size for reporting to userspace */ |
| uint32_t gamma_size; |
| uint16_t *gamma_store; |
| /* if you are using the helper */ |
| void *helper_private; |
| }; |
| /** |
| * drm_connector_funcs - control connectors on a given device |
| * @dpms: set power state (see drm_crtc_funcs above) |
| * @save: save connector state |
| * @restore: restore connector state |
| * @mode_valid: is this mode valid on the given connector? |
| * @mode_fixup: try to fixup proposed mode for this connector |
| * @mode_set: set this mode |
| * @detect: is this connector active? |
| * @get_modes: get mode list for this connector |
| * @set_property: property for this connector may need update |
| * @destroy: make object go away |
| * |
| * Each CRTC may have one or more connectors attached to it. The functions |
| * below allow the core DRM code to control connectors, enumerate available modes, |
| * etc. |
| */ |
| struct drm_connector_funcs { |
| void (*dpms)(struct drm_connector *connector, int mode); |
| void (*save)(struct drm_connector *connector); |
| void (*restore)(struct drm_connector *connector); |
| enum drm_connector_status (*detect)(struct drm_connector *connector); |
| int (*fill_modes)(struct drm_connector *connector, uint32_t max_width, uint32_t max_height); |
| int (*set_property)(struct drm_connector *connector, struct drm_property *property, |
| uint64_t val); |
| void (*destroy)(struct drm_connector *connector); |
| }; |
| struct drm_encoder_funcs { |
| void (*destroy)(struct drm_encoder *encoder); |
| }; |
| #define DRM_CONNECTOR_MAX_UMODES 16 |
| #define DRM_CONNECTOR_MAX_PROPERTY 16 |
| #define DRM_CONNECTOR_LEN 32 |
| #define DRM_CONNECTOR_MAX_ENCODER 2 |
| /** |
| * drm_encoder - central DRM encoder structure |
| */ |
| struct drm_encoder { |
| struct drm_device *dev; |
| // struct list_head head; |
| struct drm_mode_object base; |
| int encoder_type; |
| uint32_t possible_crtcs; |
| uint32_t possible_clones; |
| struct drm_crtc *crtc; |
| const struct drm_encoder_funcs *funcs; |
| void *helper_private; |
| }; |
| /** |
| * drm_connector - central DRM connector control structure |
| * @crtc: CRTC this connector is currently connected to, NULL if none |
| * @interlace_allowed: can this connector handle interlaced modes? |
| * @doublescan_allowed: can this connector handle doublescan? |
| * @available_modes: modes available on this connector (from get_modes() + user) |
| * @initial_x: initial x position for this connector |
| * @initial_y: initial y position for this connector |
| * @status: connector connected? |
| * @funcs: connector control functions |
| * |
| * Each connector may be connected to one or more CRTCs, or may be clonable by |
| * another connector if they can share a CRTC. Each connector also has a specific |
| * position in the broader display (referred to as a 'screen' though it could |
| * span multiple monitors). |
| */ |
| struct drm_connector { |
| struct drm_device *dev; |
| // struct device kdev; |
| struct device_attribute *attr; |
| // struct list_head head; |
| struct drm_mode_object base; |
| int connector_type; |
| int connector_type_id; |
| bool interlace_allowed; |
| bool doublescan_allowed; |
| // struct list_head modes; /* list of modes on this connector */ |
| int initial_x, initial_y; |
| enum drm_connector_status status; |
| /* these are modes added by probing with DDC or the BIOS */ |
| // struct list_head probed_modes; |
| struct drm_display_info display_info; |
| const struct drm_connector_funcs *funcs; |
| // struct list_head user_modes; |
| struct drm_property_blob *edid_blob_ptr; |
| u32_t property_ids[DRM_CONNECTOR_MAX_PROPERTY]; |
| uint64_t property_values[DRM_CONNECTOR_MAX_PROPERTY]; |
| /* requested DPMS state */ |
| int dpms; |
| void *helper_private; |
| uint32_t encoder_ids[DRM_CONNECTOR_MAX_ENCODER]; |
| uint32_t force_encoder_id; |
| struct drm_encoder *encoder; /* currently active encoder */ |
| }; |
| /** |
| * struct drm_mode_set |
| * |
| * Represents a single crtc the connectors that it drives with what mode |
| * and from which framebuffer it scans out from. |
| * |
| * This is used to set modes. |
| */ |
| struct drm_mode_set { |
| // struct list_head head; |
| struct drm_framebuffer *fb; |
| struct drm_crtc *crtc; |
| struct drm_display_mode *mode; |
| uint32_t x; |
| uint32_t y; |
| struct drm_connector **connectors; |
| size_t num_connectors; |
| }; |
| /** |
| * struct drm_mode_config_funcs - configure CRTCs for a given screen layout |
| * @resize: adjust CRTCs as necessary for the proposed layout |
| * |
| * Currently only a resize hook is available. DRM will call back into the |
| * driver with a new screen width and height. If the driver can't support |
| * the proposed size, it can return false. Otherwise it should adjust |
| * the CRTC<->connector mappings as needed and update its view of the screen. |
| */ |
| struct drm_mode_config_funcs { |
| struct drm_framebuffer *(*fb_create)(struct drm_device *dev, struct drm_file *file_priv, struct drm_mode_fb_cmd *mode_cmd); |
| int (*fb_changed)(struct drm_device *dev); |
| }; |
| struct drm_mode_group { |
| uint32_t num_crtcs; |
| uint32_t num_encoders; |
| uint32_t num_connectors; |
| /* list of object IDs for this group */ |
| uint32_t *id_list; |
| }; |
| /** |
| * drm_mode_config - Mode configuration control structure |
| * |
| */ |
| struct drm_mode_config { |
| // struct mutex mutex; /* protects configuration (mode lists etc.) */ |
| // struct mutex idr_mutex; /* for IDR management */ |
| // struct idr crtc_idr; /* use this idr for all IDs, fb, crtc, connector, modes - just makes life easier */ |
| /* this is limited to one for now */ |
| int num_fb; |
| // struct list_head fb_list; |
| int num_connector; |
| // struct list_head connector_list; |
| int num_encoder; |
| // struct list_head encoder_list; |
| int num_crtc; |
| // struct list_head crtc_list; |
| // struct list_head property_list; |
| /* in-kernel framebuffers - hung of filp_head in drm_framebuffer */ |
| // struct list_head fb_kernel_list; |
| int min_width, min_height; |
| int max_width, max_height; |
| struct drm_mode_config_funcs *funcs; |
| resource_size_t fb_base; |
| /* pointers to standard properties */ |
| // struct list_head property_blob_list; |
| struct drm_property *edid_property; |
| struct drm_property *dpms_property; |
| /* DVI-I properties */ |
| struct drm_property *dvi_i_subconnector_property; |
| struct drm_property *dvi_i_select_subconnector_property; |
| /* TV properties */ |
| struct drm_property *tv_subconnector_property; |
| struct drm_property *tv_select_subconnector_property; |
| struct drm_property *tv_mode_property; |
| struct drm_property *tv_left_margin_property; |
| struct drm_property *tv_right_margin_property; |
| struct drm_property *tv_top_margin_property; |
| struct drm_property *tv_bottom_margin_property; |
| /* Optional properties */ |
| struct drm_property *scaling_mode_property; |
| struct drm_property *dithering_mode_property; |
| }; |
| #define obj_to_crtc(x) container_of(x, struct drm_crtc, base) |
| #define obj_to_connector(x) container_of(x, struct drm_connector, base) |
| #define obj_to_encoder(x) container_of(x, struct drm_encoder, base) |
| #define obj_to_mode(x) container_of(x, struct drm_display_mode, base) |
| #define obj_to_fb(x) container_of(x, struct drm_framebuffer, base) |
| #define obj_to_property(x) container_of(x, struct drm_property, base) |
| #define obj_to_blob(x) container_of(x, struct drm_property_blob, base) |
| extern void drm_crtc_init(struct drm_device *dev, |
| struct drm_crtc *crtc, |
| const struct drm_crtc_funcs *funcs); |
| extern void drm_crtc_cleanup(struct drm_crtc *crtc); |
| extern void drm_connector_init(struct drm_device *dev, |
| struct drm_connector *connector, |
| const struct drm_connector_funcs *funcs, |
| int connector_type); |
| extern void drm_connector_cleanup(struct drm_connector *connector); |
| extern void drm_encoder_init(struct drm_device *dev, |
| struct drm_encoder *encoder, |
| const struct drm_encoder_funcs *funcs, |
| int encoder_type); |
| extern void drm_encoder_cleanup(struct drm_encoder *encoder); |
| extern char *drm_get_connector_name(struct drm_connector *connector); |
| extern char *drm_get_dpms_name(int val); |
| extern char *drm_get_dvi_i_subconnector_name(int val); |
| extern char *drm_get_dvi_i_select_name(int val); |
| extern char *drm_get_tv_subconnector_name(int val); |
| extern char *drm_get_tv_select_name(int val); |
| extern void drm_fb_release(struct drm_file *file_priv); |
| extern int drm_mode_group_init_legacy_group(struct drm_device *dev, struct drm_mode_group *group); |
| //extern struct edid *drm_get_edid(struct drm_connector *connector, |
| // struct i2c_adapter *adapter); |
| //extern int drm_do_probe_ddc_edid(struct i2c_adapter *adapter, |
| // unsigned char *buf, int len); |
| //extern int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid); |
| extern void drm_mode_probed_add(struct drm_connector *connector, struct drm_display_mode *mode); |
| extern void drm_mode_remove(struct drm_connector *connector, struct drm_display_mode *mode); |
| extern struct drm_display_mode *drm_mode_duplicate(struct drm_device *dev, |
| struct drm_display_mode *mode); |
| extern void drm_mode_debug_printmodeline(struct drm_display_mode *mode); |
| extern void drm_mode_config_init(struct drm_device *dev); |
| extern void drm_mode_config_cleanup(struct drm_device *dev); |
| extern void drm_mode_set_name(struct drm_display_mode *mode); |
| extern bool drm_mode_equal(struct drm_display_mode *mode1, struct drm_display_mode *mode2); |
| extern int drm_mode_width(struct drm_display_mode *mode); |
| extern int drm_mode_height(struct drm_display_mode *mode); |
| /* for us by fb module */ |
| extern int drm_mode_attachmode_crtc(struct drm_device *dev, |
| struct drm_crtc *crtc, |
| struct drm_display_mode *mode); |
| extern int drm_mode_detachmode_crtc(struct drm_device *dev, struct drm_display_mode *mode); |
| extern struct drm_display_mode *drm_mode_create(struct drm_device *dev); |
| extern void drm_mode_destroy(struct drm_device *dev, struct drm_display_mode *mode); |
| //extern void drm_mode_list_concat(struct list_head *head, |
| // struct list_head *new); |
| //extern void drm_mode_validate_size(struct drm_device *dev, |
| // struct list_head *mode_list, |
| // int maxX, int maxY, int maxPitch); |
| //extern void drm_mode_prune_invalid(struct drm_device *dev, |
| // struct list_head *mode_list, bool verbose); |
| //extern void drm_mode_sort(struct list_head *mode_list); |
| extern int drm_mode_vrefresh(struct drm_display_mode *mode); |
| extern void drm_mode_set_crtcinfo(struct drm_display_mode *p, |
| int adjust_flags); |
| extern void drm_mode_connector_list_update(struct drm_connector *connector); |
| //extern int drm_mode_connector_update_edid_property(struct drm_connector *connector, |
| // struct edid *edid); |
| extern int drm_connector_property_set_value(struct drm_connector *connector, |
| struct drm_property *property, |
| uint64_t value); |
| extern int drm_connector_property_get_value(struct drm_connector *connector, |
| struct drm_property *property, |
| uint64_t *value); |
| extern struct drm_display_mode *drm_crtc_mode_create(struct drm_device *dev); |
| extern void drm_framebuffer_set_object(struct drm_device *dev, |
| unsigned long handle); |
| extern int drm_framebuffer_init(struct drm_device *dev, |
| struct drm_framebuffer *fb, |
| const struct drm_framebuffer_funcs *funcs); |
| extern void drm_framebuffer_cleanup(struct drm_framebuffer *fb); |
| extern int drmfb_probe(struct drm_device *dev, struct drm_crtc *crtc); |
| extern int drmfb_remove(struct drm_device *dev, struct drm_framebuffer *fb); |
| extern void drm_crtc_probe_connector_modes(struct drm_device *dev, int maxX, int maxY); |
| extern bool drm_crtc_in_use(struct drm_crtc *crtc); |
| extern int drm_connector_attach_property(struct drm_connector *connector, |
| struct drm_property *property, uint64_t init_val); |
| extern struct drm_property *drm_property_create(struct drm_device *dev, int flags, |
| const char *name, int num_values); |
| extern void drm_property_destroy(struct drm_device *dev, struct drm_property *property); |
| extern int drm_property_add_enum(struct drm_property *property, int index, |
| uint64_t value, const char *name); |
| extern int drm_mode_create_dvi_i_properties(struct drm_device *dev); |
| extern int drm_mode_create_tv_properties(struct drm_device *dev, int num_formats, |
| char *formats[]); |
| extern int drm_mode_create_scaling_mode_property(struct drm_device *dev); |
| extern int drm_mode_create_dithering_property(struct drm_device *dev); |
| extern char *drm_get_encoder_name(struct drm_encoder *encoder); |
| extern int drm_mode_connector_attach_encoder(struct drm_connector *connector, |
| struct drm_encoder *encoder); |
| extern void drm_mode_connector_detach_encoder(struct drm_connector *connector, |
| struct drm_encoder *encoder); |
| extern bool drm_mode_crtc_set_gamma_size(struct drm_crtc *crtc, |
| int gamma_size); |
| extern void *drm_mode_object_find(struct drm_device *dev, uint32_t id, uint32_t type); |
| /* IOCTLs */ |
| extern int drm_mode_getresources(struct drm_device *dev, |
| void *data, struct drm_file *file_priv); |
| extern int drm_mode_getcrtc(struct drm_device *dev, |
| void *data, struct drm_file *file_priv); |
| extern int drm_mode_getconnector(struct drm_device *dev, |
| void *data, struct drm_file *file_priv); |
| extern int drm_mode_setcrtc(struct drm_device *dev, |
| void *data, struct drm_file *file_priv); |
| extern int drm_mode_cursor_ioctl(struct drm_device *dev, |
| void *data, struct drm_file *file_priv); |
| extern int drm_mode_addfb(struct drm_device *dev, |
| void *data, struct drm_file *file_priv); |
| extern int drm_mode_rmfb(struct drm_device *dev, |
| void *data, struct drm_file *file_priv); |
| extern int drm_mode_getfb(struct drm_device *dev, |
| void *data, struct drm_file *file_priv); |
| extern int drm_mode_addmode_ioctl(struct drm_device *dev, |
| void *data, struct drm_file *file_priv); |
| extern int drm_mode_rmmode_ioctl(struct drm_device *dev, |
| void *data, struct drm_file *file_priv); |
| extern int drm_mode_attachmode_ioctl(struct drm_device *dev, |
| void *data, struct drm_file *file_priv); |
| extern int drm_mode_detachmode_ioctl(struct drm_device *dev, |
| void *data, struct drm_file *file_priv); |
| extern int drm_mode_getproperty_ioctl(struct drm_device *dev, |
| void *data, struct drm_file *file_priv); |
| extern int drm_mode_getblob_ioctl(struct drm_device *dev, |
| void *data, struct drm_file *file_priv); |
| extern int drm_mode_connector_property_set_ioctl(struct drm_device *dev, |
| void *data, struct drm_file *file_priv); |
| extern int drm_mode_hotplug_ioctl(struct drm_device *dev, |
| void *data, struct drm_file *file_priv); |
| extern int drm_mode_replacefb(struct drm_device *dev, |
| void *data, struct drm_file *file_priv); |
| extern int drm_mode_getencoder(struct drm_device *dev, |
| void *data, struct drm_file *file_priv); |
| extern int drm_mode_gamma_get_ioctl(struct drm_device *dev, |
| void *data, struct drm_file *file_priv); |
| extern int drm_mode_gamma_set_ioctl(struct drm_device *dev, |
| void *data, struct drm_file *file_priv); |
| //extern bool drm_detect_hdmi_monitor(struct edid *edid); |
| #endif /* __DRM_CRTC_H__ */ |
| /drivers/video/drm/include/drm_mode.h |
|---|
| 0,0 → 1,268 |
| /* |
| * Copyright (c) 2007 Dave Airlie <airlied@linux.ie> |
| * Copyright (c) 2007 Jakob Bornecrantz <wallbraker@gmail.com> |
| * Copyright (c) 2008 Red Hat Inc. |
| * Copyright (c) 2007-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA |
| * Copyright (c) 2007-2008 Intel Corporation |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice shall be included in |
| * all copies or substantial portions of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
| * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| * IN THE SOFTWARE. |
| */ |
| #ifndef _DRM_MODE_H |
| #define _DRM_MODE_H |
| //#include <linux/kernel.h> |
| //#include <linux/types.h> |
| #define DRM_DISPLAY_INFO_LEN 32 |
| #define DRM_CONNECTOR_NAME_LEN 32 |
| #define DRM_DISPLAY_MODE_LEN 32 |
| #define DRM_PROP_NAME_LEN 32 |
| #define DRM_MODE_TYPE_BUILTIN (1<<0) |
| #define DRM_MODE_TYPE_CLOCK_C ((1<<1) | DRM_MODE_TYPE_BUILTIN) |
| #define DRM_MODE_TYPE_CRTC_C ((1<<2) | DRM_MODE_TYPE_BUILTIN) |
| #define DRM_MODE_TYPE_PREFERRED (1<<3) |
| #define DRM_MODE_TYPE_DEFAULT (1<<4) |
| #define DRM_MODE_TYPE_USERDEF (1<<5) |
| #define DRM_MODE_TYPE_DRIVER (1<<6) |
| /* Video mode flags */ |
| /* bit compatible with the xorg definitions. */ |
| #define DRM_MODE_FLAG_PHSYNC (1<<0) |
| #define DRM_MODE_FLAG_NHSYNC (1<<1) |
| #define DRM_MODE_FLAG_PVSYNC (1<<2) |
| #define DRM_MODE_FLAG_NVSYNC (1<<3) |
| #define DRM_MODE_FLAG_INTERLACE (1<<4) |
| #define DRM_MODE_FLAG_DBLSCAN (1<<5) |
| #define DRM_MODE_FLAG_CSYNC (1<<6) |
| #define DRM_MODE_FLAG_PCSYNC (1<<7) |
| #define DRM_MODE_FLAG_NCSYNC (1<<8) |
| #define DRM_MODE_FLAG_HSKEW (1<<9) /* hskew provided */ |
| #define DRM_MODE_FLAG_BCAST (1<<10) |
| #define DRM_MODE_FLAG_PIXMUX (1<<11) |
| #define DRM_MODE_FLAG_DBLCLK (1<<12) |
| #define DRM_MODE_FLAG_CLKDIV2 (1<<13) |
| /* DPMS flags */ |
| /* bit compatible with the xorg definitions. */ |
| #define DRM_MODE_DPMS_ON 0 |
| #define DRM_MODE_DPMS_STANDBY 1 |
| #define DRM_MODE_DPMS_SUSPEND 2 |
| #define DRM_MODE_DPMS_OFF 3 |
| /* Scaling mode options */ |
| #define DRM_MODE_SCALE_NON_GPU 0 |
| #define DRM_MODE_SCALE_FULLSCREEN 1 |
| #define DRM_MODE_SCALE_NO_SCALE 2 |
| #define DRM_MODE_SCALE_ASPECT 3 |
| /* Dithering mode options */ |
| #define DRM_MODE_DITHERING_OFF 0 |
| #define DRM_MODE_DITHERING_ON 1 |
| struct drm_mode_modeinfo { |
| __u32 clock; |
| __u16 hdisplay, hsync_start, hsync_end, htotal, hskew; |
| __u16 vdisplay, vsync_start, vsync_end, vtotal, vscan; |
| __u32 vrefresh; /* vertical refresh * 1000 */ |
| __u32 flags; |
| __u32 type; |
| char name[DRM_DISPLAY_MODE_LEN]; |
| }; |
| struct drm_mode_card_res { |
| __u64 fb_id_ptr; |
| __u64 crtc_id_ptr; |
| __u64 connector_id_ptr; |
| __u64 encoder_id_ptr; |
| __u32 count_fbs; |
| __u32 count_crtcs; |
| __u32 count_connectors; |
| __u32 count_encoders; |
| __u32 min_width, max_width; |
| __u32 min_height, max_height; |
| }; |
| struct drm_mode_crtc { |
| __u64 set_connectors_ptr; |
| __u32 count_connectors; |
| __u32 crtc_id; /**< Id */ |
| __u32 fb_id; /**< Id of framebuffer */ |
| __u32 x, y; /**< Position on the frameuffer */ |
| __u32 gamma_size; |
| __u32 mode_valid; |
| struct drm_mode_modeinfo mode; |
| }; |
| #define DRM_MODE_ENCODER_NONE 0 |
| #define DRM_MODE_ENCODER_DAC 1 |
| #define DRM_MODE_ENCODER_TMDS 2 |
| #define DRM_MODE_ENCODER_LVDS 3 |
| #define DRM_MODE_ENCODER_TVDAC 4 |
| struct drm_mode_get_encoder { |
| __u32 encoder_id; |
| __u32 encoder_type; |
| __u32 crtc_id; /**< Id of crtc */ |
| __u32 possible_crtcs; |
| __u32 possible_clones; |
| }; |
| /* This is for connectors with multiple signal types. */ |
| /* Try to match DRM_MODE_CONNECTOR_X as closely as possible. */ |
| #define DRM_MODE_SUBCONNECTOR_Automatic 0 |
| #define DRM_MODE_SUBCONNECTOR_Unknown 0 |
| #define DRM_MODE_SUBCONNECTOR_DVID 3 |
| #define DRM_MODE_SUBCONNECTOR_DVIA 4 |
| #define DRM_MODE_SUBCONNECTOR_Composite 5 |
| #define DRM_MODE_SUBCONNECTOR_SVIDEO 6 |
| #define DRM_MODE_SUBCONNECTOR_Component 8 |
| #define DRM_MODE_CONNECTOR_Unknown 0 |
| #define DRM_MODE_CONNECTOR_VGA 1 |
| #define DRM_MODE_CONNECTOR_DVII 2 |
| #define DRM_MODE_CONNECTOR_DVID 3 |
| #define DRM_MODE_CONNECTOR_DVIA 4 |
| #define DRM_MODE_CONNECTOR_Composite 5 |
| #define DRM_MODE_CONNECTOR_SVIDEO 6 |
| #define DRM_MODE_CONNECTOR_LVDS 7 |
| #define DRM_MODE_CONNECTOR_Component 8 |
| #define DRM_MODE_CONNECTOR_9PinDIN 9 |
| #define DRM_MODE_CONNECTOR_DisplayPort 10 |
| #define DRM_MODE_CONNECTOR_HDMIA 11 |
| #define DRM_MODE_CONNECTOR_HDMIB 12 |
| struct drm_mode_get_connector { |
| __u64 encoders_ptr; |
| __u64 modes_ptr; |
| __u64 props_ptr; |
| __u64 prop_values_ptr; |
| __u32 count_modes; |
| __u32 count_props; |
| __u32 count_encoders; |
| __u32 encoder_id; /**< Current Encoder */ |
| __u32 connector_id; /**< Id */ |
| __u32 connector_type; |
| __u32 connector_type_id; |
| __u32 connection; |
| __u32 mm_width, mm_height; /**< HxW in millimeters */ |
| __u32 subpixel; |
| }; |
| #define DRM_MODE_PROP_PENDING (1<<0) |
| #define DRM_MODE_PROP_RANGE (1<<1) |
| #define DRM_MODE_PROP_IMMUTABLE (1<<2) |
| #define DRM_MODE_PROP_ENUM (1<<3) /* enumerated type with text strings */ |
| #define DRM_MODE_PROP_BLOB (1<<4) |
| struct drm_mode_property_enum { |
| __u64 value; |
| char name[DRM_PROP_NAME_LEN]; |
| }; |
| struct drm_mode_get_property { |
| __u64 values_ptr; /* values and blob lengths */ |
| __u64 enum_blob_ptr; /* enum and blob id ptrs */ |
| __u32 prop_id; |
| __u32 flags; |
| char name[DRM_PROP_NAME_LEN]; |
| __u32 count_values; |
| __u32 count_enum_blobs; |
| }; |
| struct drm_mode_connector_set_property { |
| __u64 value; |
| __u32 prop_id; |
| __u32 connector_id; |
| }; |
| struct drm_mode_get_blob { |
| __u32 blob_id; |
| __u32 length; |
| __u64 data; |
| }; |
| struct drm_mode_fb_cmd { |
| __u32 fb_id; |
| __u32 width, height; |
| __u32 pitch; |
| __u32 bpp; |
| __u32 depth; |
| /* driver specific handle */ |
| __u32 handle; |
| }; |
| struct drm_mode_mode_cmd { |
| __u32 connector_id; |
| struct drm_mode_modeinfo mode; |
| }; |
| #define DRM_MODE_CURSOR_BO (1<<0) |
| #define DRM_MODE_CURSOR_MOVE (1<<1) |
| /* |
| * depending on the value in flags diffrent members are used. |
| * |
| * CURSOR_BO uses |
| * crtc |
| * width |
| * height |
| * handle - if 0 turns the cursor of |
| * |
| * CURSOR_MOVE uses |
| * crtc |
| * x |
| * y |
| */ |
| struct drm_mode_cursor { |
| __u32 flags; |
| __u32 crtc_id; |
| __s32 x; |
| __s32 y; |
| __u32 width; |
| __u32 height; |
| /* driver specific handle */ |
| __u32 handle; |
| }; |
| struct drm_mode_crtc_lut { |
| __u32 crtc_id; |
| __u32 gamma_size; |
| /* pointers to arrays */ |
| __u64 red; |
| __u64 green; |
| __u64 blue; |
| }; |
| #endif |
| /drivers/video/drm/include/errno-base.h |
|---|
| 0,0 → 1,39 |
| #ifndef _ASM_GENERIC_ERRNO_BASE_H |
| #define _ASM_GENERIC_ERRNO_BASE_H |
| #define EPERM 1 /* Operation not permitted */ |
| #define ENOENT 2 /* No such file or directory */ |
| #define ESRCH 3 /* No such process */ |
| #define EINTR 4 /* Interrupted system call */ |
| #define EIO 5 /* I/O error */ |
| #define ENXIO 6 /* No such device or address */ |
| #define E2BIG 7 /* Argument list too long */ |
| #define ENOEXEC 8 /* Exec format error */ |
| #define EBADF 9 /* Bad file number */ |
| #define ECHILD 10 /* No child processes */ |
| #define EAGAIN 11 /* Try again */ |
| #define ENOMEM 12 /* Out of memory */ |
| #define EACCES 13 /* Permission denied */ |
| #define EFAULT 14 /* Bad address */ |
| #define ENOTBLK 15 /* Block device required */ |
| #define EBUSY 16 /* Device or resource busy */ |
| #define EEXIST 17 /* File exists */ |
| #define EXDEV 18 /* Cross-device link */ |
| #define ENODEV 19 /* No such device */ |
| #define ENOTDIR 20 /* Not a directory */ |
| #define EISDIR 21 /* Is a directory */ |
| #define EINVAL 22 /* Invalid argument */ |
| #define ENFILE 23 /* File table overflow */ |
| #define EMFILE 24 /* Too many open files */ |
| #define ENOTTY 25 /* Not a typewriter */ |
| #define ETXTBSY 26 /* Text file busy */ |
| #define EFBIG 27 /* File too large */ |
| #define ENOSPC 28 /* No space left on device */ |
| #define ESPIPE 29 /* Illegal seek */ |
| #define EROFS 30 /* Read-only file system */ |
| #define EMLINK 31 /* Too many links */ |
| #define EPIPE 32 /* Broken pipe */ |
| #define EDOM 33 /* Math argument out of domain of func */ |
| #define ERANGE 34 /* Math result not representable */ |
| #endif |
| /drivers/video/drm/include/pci.h |
|---|
| 0,0 → 1,562 |
| #include <types.h> |
| #include <link.h> |
| #ifndef __PCI_H__ |
| #define __PCI_H__ |
| #define PCI_ANY_ID (~0) |
| #define PCI_CLASS_NOT_DEFINED 0x0000 |
| #define PCI_CLASS_NOT_DEFINED_VGA 0x0001 |
| #define PCI_BASE_CLASS_STORAGE 0x01 |
| #define PCI_CLASS_STORAGE_SCSI 0x0100 |
| #define PCI_CLASS_STORAGE_IDE 0x0101 |
| #define PCI_CLASS_STORAGE_FLOPPY 0x0102 |
| #define PCI_CLASS_STORAGE_IPI 0x0103 |
| #define PCI_CLASS_STORAGE_RAID 0x0104 |
| #define PCI_CLASS_STORAGE_SATA 0x0106 |
| #define PCI_CLASS_STORAGE_SATA_AHCI 0x010601 |
| #define PCI_CLASS_STORAGE_SAS 0x0107 |
| #define PCI_CLASS_STORAGE_OTHER 0x0180 |
| #define PCI_BASE_CLASS_NETWORK 0x02 |
| #define PCI_CLASS_NETWORK_ETHERNET 0x0200 |
| #define PCI_CLASS_NETWORK_TOKEN_RING 0x0201 |
| #define PCI_CLASS_NETWORK_FDDI 0x0202 |
| #define PCI_CLASS_NETWORK_ATM 0x0203 |
| #define PCI_CLASS_NETWORK_OTHER 0x0280 |
| #define PCI_BASE_CLASS_DISPLAY 0x03 |
| #define PCI_CLASS_DISPLAY_VGA 0x0300 |
| #define PCI_CLASS_DISPLAY_XGA 0x0301 |
| #define PCI_CLASS_DISPLAY_3D 0x0302 |
| #define PCI_CLASS_DISPLAY_OTHER 0x0380 |
| #define PCI_BASE_CLASS_MULTIMEDIA 0x04 |
| #define PCI_CLASS_MULTIMEDIA_VIDEO 0x0400 |
| #define PCI_CLASS_MULTIMEDIA_AUDIO 0x0401 |
| #define PCI_CLASS_MULTIMEDIA_PHONE 0x0402 |
| #define PCI_CLASS_MULTIMEDIA_OTHER 0x0480 |
| #define PCI_BASE_CLASS_MEMORY 0x05 |
| #define PCI_CLASS_MEMORY_RAM 0x0500 |
| #define PCI_CLASS_MEMORY_FLASH 0x0501 |
| #define PCI_CLASS_MEMORY_OTHER 0x0580 |
| #define PCI_BASE_CLASS_BRIDGE 0x06 |
| #define PCI_CLASS_BRIDGE_HOST 0x0600 |
| #define PCI_CLASS_BRIDGE_ISA 0x0601 |
| #define PCI_CLASS_BRIDGE_EISA 0x0602 |
| #define PCI_CLASS_BRIDGE_MC 0x0603 |
| #define PCI_CLASS_BRIDGE_PCI 0x0604 |
| #define PCI_CLASS_BRIDGE_PCMCIA 0x0605 |
| #define PCI_CLASS_BRIDGE_NUBUS 0x0606 |
| #define PCI_CLASS_BRIDGE_CARDBUS 0x0607 |
| #define PCI_CLASS_BRIDGE_RACEWAY 0x0608 |
| #define PCI_CLASS_BRIDGE_OTHER 0x0680 |
| #define PCI_BASE_CLASS_COMMUNICATION 0x07 |
| #define PCI_CLASS_COMMUNICATION_SERIAL 0x0700 |
| #define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701 |
| #define PCI_CLASS_COMMUNICATION_MULTISERIAL 0x0702 |
| #define PCI_CLASS_COMMUNICATION_MODEM 0x0703 |
| #define PCI_CLASS_COMMUNICATION_OTHER 0x0780 |
| #define PCI_BASE_CLASS_SYSTEM 0x08 |
| #define PCI_CLASS_SYSTEM_PIC 0x0800 |
| #define PCI_CLASS_SYSTEM_PIC_IOAPIC 0x080010 |
| #define PCI_CLASS_SYSTEM_PIC_IOXAPIC 0x080020 |
| #define PCI_CLASS_SYSTEM_DMA 0x0801 |
| #define PCI_CLASS_SYSTEM_TIMER 0x0802 |
| #define PCI_CLASS_SYSTEM_RTC 0x0803 |
| #define PCI_CLASS_SYSTEM_PCI_HOTPLUG 0x0804 |
| #define PCI_CLASS_SYSTEM_SDHCI 0x0805 |
| #define PCI_CLASS_SYSTEM_OTHER 0x0880 |
| #define PCI_BASE_CLASS_INPUT 0x09 |
| #define PCI_CLASS_INPUT_KEYBOARD 0x0900 |
| #define PCI_CLASS_INPUT_PEN 0x0901 |
| #define PCI_CLASS_INPUT_MOUSE 0x0902 |
| #define PCI_CLASS_INPUT_SCANNER 0x0903 |
| #define PCI_CLASS_INPUT_GAMEPORT 0x0904 |
| #define PCI_CLASS_INPUT_OTHER 0x0980 |
| #define PCI_BASE_CLASS_DOCKING 0x0a |
| #define PCI_CLASS_DOCKING_GENERIC 0x0a00 |
| #define PCI_CLASS_DOCKING_OTHER 0x0a80 |
| #define PCI_BASE_CLASS_PROCESSOR 0x0b |
| #define PCI_CLASS_PROCESSOR_386 0x0b00 |
| #define PCI_CLASS_PROCESSOR_486 0x0b01 |
| #define PCI_CLASS_PROCESSOR_PENTIUM 0x0b02 |
| #define PCI_CLASS_PROCESSOR_ALPHA 0x0b10 |
| #define PCI_CLASS_PROCESSOR_POWERPC 0x0b20 |
| #define PCI_CLASS_PROCESSOR_MIPS 0x0b30 |
| #define PCI_CLASS_PROCESSOR_CO 0x0b40 |
| #define PCI_BASE_CLASS_SERIAL 0x0c |
| #define PCI_CLASS_SERIAL_FIREWIRE 0x0c00 |
| #define PCI_CLASS_SERIAL_FIREWIRE_OHCI 0x0c0010 |
| #define PCI_CLASS_SERIAL_ACCESS 0x0c01 |
| #define PCI_CLASS_SERIAL_SSA 0x0c02 |
| #define PCI_CLASS_SERIAL_USB 0x0c03 |
| #define PCI_CLASS_SERIAL_USB_UHCI 0x0c0300 |
| #define PCI_CLASS_SERIAL_USB_OHCI 0x0c0310 |
| #define PCI_CLASS_SERIAL_USB_EHCI 0x0c0320 |
| #define PCI_CLASS_SERIAL_FIBER 0x0c04 |
| #define PCI_CLASS_SERIAL_SMBUS 0x0c05 |
| #define PCI_BASE_CLASS_WIRELESS 0x0d |
| #define PCI_CLASS_WIRELESS_RF_CONTROLLER 0x0d10 |
| #define PCI_CLASS_WIRELESS_WHCI 0x0d1010 |
| #define PCI_BASE_CLASS_INTELLIGENT 0x0e |
| #define PCI_CLASS_INTELLIGENT_I2O 0x0e00 |
| #define PCI_BASE_CLASS_SATELLITE 0x0f |
| #define PCI_CLASS_SATELLITE_TV 0x0f00 |
| #define PCI_CLASS_SATELLITE_AUDIO 0x0f01 |
| #define PCI_CLASS_SATELLITE_VOICE 0x0f03 |
| #define PCI_CLASS_SATELLITE_DATA 0x0f04 |
| #define PCI_BASE_CLASS_CRYPT 0x10 |
| #define PCI_CLASS_CRYPT_NETWORK 0x1000 |
| #define PCI_CLASS_CRYPT_ENTERTAINMENT 0x1001 |
| #define PCI_CLASS_CRYPT_OTHER 0x1080 |
| #define PCI_BASE_CLASS_SIGNAL_PROCESSING 0x11 |
| #define PCI_CLASS_SP_DPIO 0x1100 |
| #define PCI_CLASS_SP_OTHER 0x1180 |
| #define PCI_CLASS_OTHERS 0xff |
| /* |
| * Under PCI, each device has 256 bytes of configuration address space, |
| * of which the first 64 bytes are standardized as follows: |
| */ |
| #define PCI_VENDOR_ID 0x000 /* 16 bits */ |
| #define PCI_DEVICE_ID 0x002 /* 16 bits */ |
| #define PCI_COMMAND 0x004 /* 16 bits */ |
| #define PCI_COMMAND_IO 0x001 /* Enable response in I/O space */ |
| #define PCI_COMMAND_MEMORY 0x002 /* Enable response in Memory space */ |
| #define PCI_COMMAND_MASTER 0x004 /* Enable bus mastering */ |
| #define PCI_COMMAND_SPECIAL 0x008 /* Enable response to special cycles */ |
| #define PCI_COMMAND_INVALIDATE 0x010 /* Use memory write and invalidate */ |
| #define PCI_COMMAND_VGA_PALETTE 0x020 /* Enable palette snooping */ |
| #define PCI_COMMAND_PARITY 0x040 /* Enable parity checking */ |
| #define PCI_COMMAND_WAIT 0x080 /* Enable address/data stepping */ |
| #define PCI_COMMAND_SERR 0x100 /* Enable SERR */ |
| #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */ |
| #define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */ |
| #define PCI_STATUS 0x006 /* 16 bits */ |
| #define PCI_STATUS_CAP_LIST 0x010 /* Support Capability List */ |
| #define PCI_STATUS_66MHZ 0x020 /* Support 66 Mhz PCI 2.1 bus */ |
| #define PCI_STATUS_UDF 0x040 /* Support User Definable Features [obsolete] */ |
| #define PCI_STATUS_FAST_BACK 0x080 /* Accept fast-back to back */ |
| #define PCI_STATUS_PARITY 0x100 /* Detected parity error */ |
| #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */ |
| #define PCI_STATUS_DEVSEL_FAST 0x000 |
| #define PCI_STATUS_DEVSEL_MEDIUM 0x200 |
| #define PCI_STATUS_DEVSEL_SLOW 0x400 |
| #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */ |
| #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */ |
| #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */ |
| #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */ |
| #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */ |
| #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 revision */ |
| #define PCI_REVISION_ID 0x08 /* Revision ID */ |
| #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ |
| #define PCI_CLASS_DEVICE 0x0a /* Device class */ |
| #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ |
| #define PCI_LATENCY_TIMER 0x0d /* 8 bits */ |
| #define PCI_HEADER_TYPE 0x0e /* 8 bits */ |
| #define PCI_HEADER_TYPE_NORMAL 0 |
| #define PCI_HEADER_TYPE_BRIDGE 1 |
| #define PCI_HEADER_TYPE_CARDBUS 2 |
| #define PCI_BIST 0x0f /* 8 bits */ |
| #define PCI_BIST_CODE_MASK 0x0f /* Return result */ |
| #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ |
| #define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */ |
| /* |
| * Base addresses specify locations in memory or I/O space. |
| * Decoded size can be determined by writing a value of |
| * 0xffffffff to the register, and reading it back. Only |
| * 1 bits are decoded. |
| */ |
| #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */ |
| #define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */ |
| #define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */ |
| #define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */ |
| #define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */ |
| #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */ |
| #define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */ |
| #define PCI_BASE_ADDRESS_SPACE_IO 0x01 |
| #define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 |
| #define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06 |
| #define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */ |
| #define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */ |
| #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */ |
| #define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */ |
| #define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL) |
| #define PCI_BASE_ADDRESS_IO_MASK (~0x03UL) |
| /* bit 1 is reserved if address_space = 1 */ |
| #define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */ |
| /* Header type 0 (normal devices) */ |
| #define PCI_CARDBUS_CIS 0x28 |
| #define PCI_SUBSYSTEM_VENDOR_ID 0x2c |
| #define PCI_SUBSYSTEM_ID 0x2e |
| #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */ |
| #define PCI_ROM_ADDRESS_ENABLE 0x01 |
| #define PCI_ROM_ADDRESS_MASK (~0x7ffUL) |
| #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ |
| #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ |
| #define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40 |
| #define PCI_CB_SUBSYSTEM_ID 0x42 |
| #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */ |
| #define PCI_CB_CAPABILITY_LIST 0x14 |
| /* Capability lists */ |
| #define PCI_CAP_LIST_ID 0 /* Capability ID */ |
| #define PCI_CAP_ID_PM 0x01 /* Power Management */ |
| #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */ |
| #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */ |
| #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */ |
| #define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */ |
| #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ |
| #define PCI_CAP_ID_PCIX 0x07 /* PCI-X */ |
| #define PCI_CAP_ID_HT 0x08 /* HyperTransport */ |
| #define PCI_CAP_ID_VNDR 0x09 /* Vendor specific capability */ |
| #define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */ |
| #define PCI_CAP_ID_EXP 0x10 /* PCI Express */ |
| #define PCI_CAP_ID_MSIX 0x11 /* MSI-X */ |
| #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ |
| #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */ |
| #define PCI_CAP_SIZEOF 4 |
| /* AGP registers */ |
| #define PCI_AGP_VERSION 2 /* BCD version number */ |
| #define PCI_AGP_RFU 3 /* Rest of capability flags */ |
| #define PCI_AGP_STATUS 4 /* Status register */ |
| #define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */ |
| #define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */ |
| #define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */ |
| #define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */ |
| #define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */ |
| #define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */ |
| #define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */ |
| #define PCI_AGP_COMMAND 8 /* Control register */ |
| #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */ |
| #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */ |
| #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */ |
| #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */ |
| #define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */ |
| #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */ |
| #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate */ |
| #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate */ |
| #define PCI_AGP_SIZEOF 12 |
| #define PCI_MAP_REG_START 0x10 |
| #define PCI_MAP_REG_END 0x28 |
| #define PCI_MAP_ROM_REG 0x30 |
| #define PCI_MAP_MEMORY 0x00000000 |
| #define PCI_MAP_IO 0x00000001 |
| #define PCI_MAP_MEMORY_TYPE 0x00000007 |
| #define PCI_MAP_IO_TYPE 0x00000003 |
| #define PCI_MAP_MEMORY_TYPE_32BIT 0x00000000 |
| #define PCI_MAP_MEMORY_TYPE_32BIT_1M 0x00000002 |
| #define PCI_MAP_MEMORY_TYPE_64BIT 0x00000004 |
| #define PCI_MAP_MEMORY_TYPE_MASK 0x00000006 |
| #define PCI_MAP_MEMORY_CACHABLE 0x00000008 |
| #define PCI_MAP_MEMORY_ATTR_MASK 0x0000000e |
| #define PCI_MAP_MEMORY_ADDRESS_MASK 0xfffffff0 |
| #define PCI_MAP_IO_ATTR_MASK 0x00000003 |
| #define PCI_MAP_IS_IO(b) ((b) & PCI_MAP_IO) |
| #define PCI_MAP_IS_MEM(b) (!PCI_MAP_IS_IO(b)) |
| #define PCI_MAP_IS64BITMEM(b) \ |
| (((b) & PCI_MAP_MEMORY_TYPE_MASK) == PCI_MAP_MEMORY_TYPE_64BIT) |
| #define PCIGETMEMORY(b) ((b) & PCI_MAP_MEMORY_ADDRESS_MASK) |
| #define PCIGETMEMORY64HIGH(b) (*((CARD32*)&b + 1)) |
| #define PCIGETMEMORY64(b) \ |
| (PCIGETMEMORY(b) | ((CARD64)PCIGETMEMORY64HIGH(b) << 32)) |
| #define PCI_MAP_IO_ADDRESS_MASK 0xfffffffc |
| #define PCIGETIO(b) ((b) & PCI_MAP_IO_ADDRESS_MASK) |
| #define PCI_MAP_ROM_DECODE_ENABLE 0x00000001 |
| #define PCI_MAP_ROM_ADDRESS_MASK 0xfffff800 |
| #define PCIGETROM(b) ((b) & PCI_MAP_ROM_ADDRESS_MASK) |
| #ifndef PCI_DOM_MASK |
| # define PCI_DOM_MASK 0x0ffu |
| #endif |
| #define PCI_DOMBUS_MASK (((PCI_DOM_MASK) << 8) | 0x0ffu) |
| #define PCI_MAKE_TAG(b,d,f) ((((b) & (PCI_DOMBUS_MASK)) << 16) | \ |
| (((d) & 0x00001fu) << 11) | \ |
| (((f) & 0x000007u) << 8)) |
| #define PCI_BUS_FROM_TAG(tag) (((tag) >> 16) & (PCI_DOMBUS_MASK)) |
| #define PCI_DEV_FROM_TAG(tag) (((tag) & 0x0000f800u) >> 11) |
| #define PCI_FUNC_FROM_TAG(tag) (((tag) & 0x00000700u) >> 8) |
| #define PCI_DFN_FROM_TAG(tag) (((tag) & 0x0000ff00u) >> 8) |
| #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) |
| #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) |
| #define PCI_FUNC(devfn) ((devfn) & 0x07) |
| typedef unsigned int PCITAG; |
| extern inline PCITAG |
| pciTag(int busnum, int devnum, int funcnum) |
| { |
| return(PCI_MAKE_TAG(busnum,devnum,funcnum)); |
| } |
| struct resource |
| { |
| resource_size_t start; |
| resource_size_t end; |
| // const char *name; |
| unsigned long flags; |
| // struct resource *parent, *sibling, *child; |
| }; |
| /* |
| * IO resources have these defined flags. |
| */ |
| #define IORESOURCE_BITS 0x000000ff /* Bus-specific bits */ |
| #define IORESOURCE_IO 0x00000100 /* Resource type */ |
| #define IORESOURCE_MEM 0x00000200 |
| #define IORESOURCE_IRQ 0x00000400 |
| #define IORESOURCE_DMA 0x00000800 |
| #define IORESOURCE_PREFETCH 0x00001000 /* No side effects */ |
| #define IORESOURCE_READONLY 0x00002000 |
| #define IORESOURCE_CACHEABLE 0x00004000 |
| #define IORESOURCE_RANGELENGTH 0x00008000 |
| #define IORESOURCE_SHADOWABLE 0x00010000 |
| #define IORESOURCE_BUS_HAS_VGA 0x00080000 |
| #define IORESOURCE_DISABLED 0x10000000 |
| #define IORESOURCE_UNSET 0x20000000 |
| #define IORESOURCE_AUTO 0x40000000 |
| #define IORESOURCE_BUSY 0x80000000 /* Driver has marked this resource busy */ |
| /* ISA PnP IRQ specific bits (IORESOURCE_BITS) */ |
| #define IORESOURCE_IRQ_HIGHEDGE (1<<0) |
| #define IORESOURCE_IRQ_LOWEDGE (1<<1) |
| #define IORESOURCE_IRQ_HIGHLEVEL (1<<2) |
| #define IORESOURCE_IRQ_LOWLEVEL (1<<3) |
| #define IORESOURCE_IRQ_SHAREABLE (1<<4) |
| /* ISA PnP DMA specific bits (IORESOURCE_BITS) */ |
| #define IORESOURCE_DMA_TYPE_MASK (3<<0) |
| #define IORESOURCE_DMA_8BIT (0<<0) |
| #define IORESOURCE_DMA_8AND16BIT (1<<0) |
| #define IORESOURCE_DMA_16BIT (2<<0) |
| #define IORESOURCE_DMA_MASTER (1<<2) |
| #define IORESOURCE_DMA_BYTE (1<<3) |
| #define IORESOURCE_DMA_WORD (1<<4) |
| #define IORESOURCE_DMA_SPEED_MASK (3<<6) |
| #define IORESOURCE_DMA_COMPATIBLE (0<<6) |
| #define IORESOURCE_DMA_TYPEA (1<<6) |
| #define IORESOURCE_DMA_TYPEB (2<<6) |
| #define IORESOURCE_DMA_TYPEF (3<<6) |
| /* ISA PnP memory I/O specific bits (IORESOURCE_BITS) */ |
| #define IORESOURCE_MEM_WRITEABLE (1<<0) /* dup: IORESOURCE_READONLY */ |
| #define IORESOURCE_MEM_CACHEABLE (1<<1) /* dup: IORESOURCE_CACHEABLE */ |
| #define IORESOURCE_MEM_RANGELENGTH (1<<2) /* dup: IORESOURCE_RANGELENGTH */ |
| #define IORESOURCE_MEM_TYPE_MASK (3<<3) |
| #define IORESOURCE_MEM_8BIT (0<<3) |
| #define IORESOURCE_MEM_16BIT (1<<3) |
| #define IORESOURCE_MEM_8AND16BIT (2<<3) |
| #define IORESOURCE_MEM_32BIT (3<<3) |
| #define IORESOURCE_MEM_SHADOWABLE (1<<5) /* dup: IORESOURCE_SHADOWABLE */ |
| #define IORESOURCE_MEM_EXPANSIONROM (1<<6) |
| /* PCI ROM control bits (IORESOURCE_BITS) */ |
| #define IORESOURCE_ROM_ENABLE (1<<0) /* ROM is enabled, same as PCI_ROM_ADDRESS_ENABLE */ |
| #define IORESOURCE_ROM_SHADOW (1<<1) /* ROM is copy at C000:0 */ |
| #define IORESOURCE_ROM_COPY (1<<2) /* ROM is alloc'd copy, resource field overlaid */ |
| #define IORESOURCE_ROM_BIOS_COPY (1<<3) /* ROM is BIOS copy, resource field overlaid */ |
| /* PCI control bits. Shares IORESOURCE_BITS with above PCI ROM. */ |
| #define IORESOURCE_PCI_FIXED (1<<4) /* Do not move resource */ |
| /* |
| * For PCI devices, the region numbers are assigned this way: |
| * |
| * 0-5 standard PCI regions |
| * 6 expansion ROM |
| * 7-10 bridges: address space assigned to buses behind the bridge |
| */ |
| #define PCI_ROM_RESOURCE 6 |
| #define PCI_BRIDGE_RESOURCES 7 |
| #define PCI_NUM_RESOURCES 11 |
| #ifndef PCI_BUS_NUM_RESOURCES |
| #define PCI_BUS_NUM_RESOURCES 8 |
| #endif |
| #define DEVICE_COUNT_RESOURCE 12 |
| /* |
| * The pci_dev structure is used to describe PCI devices. |
| */ |
| struct pci_dev { |
| // struct list_head bus_list; /* node in per-bus list */ |
| // struct pci_bus *bus; /* bus this device is on */ |
| // struct pci_bus *subordinate; /* bus this device bridges to */ |
| // void *sysdata; /* hook for sys-specific extension */ |
| // struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */ |
| // struct pci_slot *slot; /* Physical slot this device is in */ |
| u32_t bus; |
| u32_t devfn; /* encoded device & function index */ |
| u16_t vendor; |
| u16_t device; |
| u16_t subsystem_vendor; |
| u16_t subsystem_device; |
| u32_t class; /* 3 bytes: (base,sub,prog-if) */ |
| uint8_t revision; /* PCI revision, low byte of class word */ |
| uint8_t hdr_type; /* PCI header type (`multi' flag masked out) */ |
| uint8_t pcie_type; /* PCI-E device/port type */ |
| uint8_t rom_base_reg; /* which config register controls the ROM */ |
| uint8_t pin; /* which interrupt pin this device uses */ |
| // struct pci_driver *driver; /* which driver has allocated this device */ |
| uint64_t dma_mask; /* Mask of the bits of bus address this |
| device implements. Normally this is |
| 0xffffffff. You only need to change |
| this if your device has broken DMA |
| or supports 64-bit transfers. */ |
| // struct device_dma_parameters dma_parms; |
| // pci_power_t current_state; /* Current operating state. In ACPI-speak, |
| // this is D0-D3, D0 being fully functional, |
| // and D3 being off. */ |
| // int pm_cap; /* PM capability offset in the |
| // configuration space */ |
| unsigned int pme_support:5; /* Bitmask of states from which PME# |
| can be generated */ |
| unsigned int d1_support:1; /* Low power state D1 is supported */ |
| unsigned int d2_support:1; /* Low power state D2 is supported */ |
| unsigned int no_d1d2:1; /* Only allow D0 and D3 */ |
| // pci_channel_state_t error_state; /* current connectivity state */ |
| // struct device dev; /* Generic device interface */ |
| // int cfg_size; /* Size of configuration space */ |
| /* |
| * Instead of touching interrupt line and base address registers |
| * directly, use the values stored here. They might be different! |
| */ |
| unsigned int irq; |
| struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ |
| /* These fields are used by common fixups */ |
| unsigned int transparent:1; /* Transparent PCI bridge */ |
| unsigned int multifunction:1;/* Part of multi-function device */ |
| /* keep track of device state */ |
| unsigned int is_added:1; |
| unsigned int is_busmaster:1; /* device is busmaster */ |
| unsigned int no_msi:1; /* device may not use msi */ |
| unsigned int block_ucfg_access:1; /* userspace config space access is blocked */ |
| unsigned int broken_parity_status:1; /* Device generates false positive parity */ |
| unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */ |
| unsigned int msi_enabled:1; |
| unsigned int msix_enabled:1; |
| unsigned int ari_enabled:1; /* ARI forwarding */ |
| unsigned int is_managed:1; |
| unsigned int is_pcie:1; |
| unsigned int state_saved:1; |
| unsigned int is_physfn:1; |
| unsigned int is_virtfn:1; |
| // pci_dev_flags_t dev_flags; |
| // atomic_t enable_cnt; /* pci_enable_device has been called */ |
| // u32 saved_config_space[16]; /* config space saved at suspend time */ |
| // struct hlist_head saved_cap_space; |
| // struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */ |
| // int rom_attr_enabled; /* has display of the rom attribute been enabled? */ |
| // struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ |
| // struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ |
| }; |
| #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) |
| #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) |
| #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) |
| #define pci_resource_len(dev,bar) \ |
| ((pci_resource_start((dev), (bar)) == 0 && \ |
| pci_resource_end((dev), (bar)) == \ |
| pci_resource_start((dev), (bar))) ? 0 : \ |
| \ |
| (pci_resource_end((dev), (bar)) - \ |
| pci_resource_start((dev), (bar)) + 1)) |
| struct pci_device_id |
| { |
| u16_t vendor, device; /* Vendor and device ID or PCI_ANY_ID*/ |
| u16_t subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */ |
| u32_t class, class_mask; /* (class,subclass,prog-if) triplet */ |
| u32_t driver_data; /* Data private to the driver */ |
| }; |
| typedef struct |
| { |
| link_t link; |
| struct pci_dev pci_dev; |
| }dev_t; |
| int enum_pci_devices(void); |
| struct pci_device_id* |
| find_pci_device(dev_t* pdev, struct pci_device_id *idlist); |
| #define pci_name(x) "radeon" |
| #endif //__PCI__H__ |
| /drivers/video/drm/include/syscall.h |
|---|
| 0,0 → 1,351 |
| #ifndef __SYSCALL_H__ |
| #define __SYSCALL_H__ |
| #define OS_BASE 0x80000000 |
| typedef struct |
| { |
| u32_t handle; |
| u32_t io_code; |
| void *input; |
| int inp_size; |
| void *output; |
| int out_size; |
| }ioctl_t; |
| typedef int (__stdcall *srv_proc_t)(ioctl_t *); |
| #define ERR_OK 0 |
| #define ERR_PARAM -1 |
| u32_t __stdcall drvEntry(int)__asm__("_drvEntry"); |
| /////////////////////////////////////////////////////////////////////////////// |
| #define STDCALL __attribute__ ((stdcall)) __attribute__ ((dllimport)) |
| #define IMPORT __attribute__ ((dllimport)) |
| /////////////////////////////////////////////////////////////////////////////// |
| #define SysMsgBoardStr __SysMsgBoardStr |
| #define PciApi __PciApi |
| //#define RegService __RegService |
| #define CreateObject __CreateObject |
| #define DestroyObject __DestroyObject |
| /////////////////////////////////////////////////////////////////////////////// |
| #define PG_SW 0x003 |
| #define PG_NOCACHE 0x018 |
| void* STDCALL AllocKernelSpace(size_t size)__asm__("AllocKernelSpace"); |
| void* STDCALL KernelAlloc(size_t size)__asm__("KernelAlloc"); |
| void* STDCALL KernelFree(void *mem)__asm__("KernelFree"); |
| void* STDCALL UserAlloc(size_t size)__asm__("UserAlloc"); |
| int STDCALL UserFree(void *mem)__asm__("UserFree"); |
| addr_t STDCALL AllocPages(count_t count)__asm__("AllocPages"); |
| void* STDCALL CreateRingBuffer(size_t size, u32_t map)__asm__("CreateRingBuffer"); |
| u32_t STDCALL RegService(char *name, srv_proc_t proc)__asm__("RegService"); |
| int STDCALL AttachIntHandler(int irq, void *handler, u32_t access) __asm__("AttachIntHandler"); |
| //void *CreateObject(u32 pid, size_t size); |
| //void *DestroyObject(void *obj); |
| addr_t STDCALL MapIoMem(addr_t base, size_t size, u32_t flags)__asm__("MapIoMem"); |
| /////////////////////////////////////////////////////////////////////////////// |
| void STDCALL SetMouseData(int btn, int x, int y, |
| int z, int h)__asm__("SetMouseData"); |
| static u32_t PciApi(int cmd); |
| u8_t STDCALL PciRead8 (u32_t bus, u32_t devfn, u32_t reg)__asm__("PciRead8"); |
| u16_t STDCALL PciRead16(u32_t bus, u32_t devfn, u32_t reg)__asm__("PciRead16"); |
| u32_t STDCALL PciRead32(u32_t bus, u32_t devfn, u32_t reg)__asm__("PciRead32"); |
| u32_t STDCALL PciWrite8 (u32_t bus, u32_t devfn, u32_t reg,u8_t val) __asm__("PciWrite8"); |
| u32_t STDCALL PciWrite16(u32_t bus, u32_t devfn, u32_t reg,u16_t val)__asm__("PciWrite16"); |
| u32_t STDCALL PciWrite32(u32_t bus, u32_t devfn, u32_t reg,u32_t val)__asm__("PciWrite32"); |
| #define pciReadByte(tag, reg) \ |
| PciRead8(PCI_BUS_FROM_TAG(tag),PCI_DFN_FROM_TAG(tag),(reg)) |
| #define pciReadWord(tag, reg) \ |
| PciRead16(PCI_BUS_FROM_TAG(tag),PCI_DFN_FROM_TAG(tag),(reg)) |
| #define pciReadLong(tag, reg) \ |
| PciRead32(PCI_BUS_FROM_TAG(tag),PCI_DFN_FROM_TAG(tag),(reg)) |
| #define pciWriteByte(tag, reg, val) \ |
| PciWrite8(PCI_BUS_FROM_TAG(tag),PCI_DFN_FROM_TAG(tag),(reg),(val)) |
| #define pciWriteWord(tag, reg, val) \ |
| PciWrite16(PCI_BUS_FROM_TAG(tag),PCI_DFN_FROM_TAG(tag),(reg),(val)) |
| #define pciWriteLong(tag, reg, val) \ |
| PciWrite32(PCI_BUS_FROM_TAG(tag),PCI_DFN_FROM_TAG(tag),(reg),(val)) |
| /////////////////////////////////////////////////////////////////////////////// |
| int dbg_open(char *path); |
| int dbgprintf(const char* format, ...); |
| /////////////////////////////////////////////////////////////////////////////// |
| extern inline int GetScreenSize() |
| { |
| int retval; |
| asm("int $0x40" |
| :"=a"(retval) |
| :"a"(61), "b"(1)); |
| return retval; |
| } |
| extern inline int GetScreenBpp() |
| { |
| int retval; |
| asm("int $0x40" |
| :"=a"(retval) |
| :"a"(61), "b"(2)); |
| return retval; |
| } |
| extern inline int GetScreenPitch() |
| { |
| int retval; |
| asm("int $0x40" |
| :"=a"(retval) |
| :"a"(61), "b"(3)); |
| return retval; |
| } |
| extern inline u32_t GetPgAddr(void *mem) |
| { |
| u32_t retval; |
| __asm__ __volatile__ ( |
| "call *__imp__GetPgAddr \n\t" |
| :"=eax" (retval) |
| :"a" (mem) ); |
| return retval; |
| }; |
| extern inline void CommitPages(void *mem, u32_t page, u32_t size) |
| { |
| size = (size+4095) & ~4095; |
| __asm__ __volatile__ ( |
| "call *__imp__CommitPages" |
| ::"a" (page), "b"(mem),"c"(size>>12) |
| :"edx" ); |
| __asm__ __volatile__ ("":::"eax","ebx","ecx"); |
| }; |
| extern inline void UnmapPages(void *mem, size_t size) |
| { |
| size = (size+4095) & ~4095; |
| __asm__ __volatile__ ( |
| "call *__imp__UnmapPages" |
| ::"a" (mem), "c"(size>>12) |
| :"edx"); |
| __asm__ __volatile__ ("":::"eax","ecx"); |
| }; |
| extern inline void usleep(u32_t delay) |
| { |
| if( !delay ) |
| delay++; |
| delay*=1000; |
| while(delay--) |
| __asm__ __volatile__ ( |
| "xorl %%eax, %%eax \n\t" |
| "cpuid \n\t" |
| :::"eax","ebx","ecx","edx"); |
| }; |
| static inline void udelay(u32_t delay) |
| { |
| if(!delay) delay++; |
| delay*=500; |
| while(delay--) |
| { |
| __asm__ __volatile__( |
| "xorl %%eax, %%eax \n\t" |
| "cpuid" |
| :::"eax","ebx","ecx","edx" ); |
| } |
| } |
| static inline void mdelay(u32_t time) |
| { |
| time /= 10; |
| if(!time) time = 1; |
| __asm__ __volatile__ ( |
| "call *__imp__Delay" |
| ::"b" (time)); |
| __asm__ __volatile__ ( |
| "":::"ebx"); |
| }; |
| extern inline u32_t __PciApi(int cmd) |
| { |
| u32_t retval; |
| __asm__ __volatile__ ( |
| "call *__imp__PciApi" |
| :"=a" (retval) |
| :"a" (cmd) |
| :"memory"); |
| return retval; |
| }; |
| extern inline void* __CreateObject(u32_t pid, size_t size) |
| { |
| void *retval; |
| __asm__ __volatile__ ( |
| "call *__imp__CreateObject \n\t" |
| :"=a" (retval) |
| :"a" (size),"b"(pid) |
| :"esi","edi", "memory"); |
| return retval; |
| } |
| extern inline void *__DestroyObject(void *obj) |
| { |
| __asm__ __volatile__ ( |
| "call *__imp__DestroyObject" |
| : |
| :"a" (obj) |
| :"ebx","edx","esi","edi", "memory"); |
| } |
| /* |
| u32 __RegService(char *name, srv_proc_t proc) |
| { |
| u32 retval; |
| asm __volatile__ |
| ( |
| "pushl %%eax \n\t" |
| "pushl %%ebx \n\t" |
| "call *__imp__RegService \n\t" |
| :"=eax" (retval) |
| :"a" (proc), "b" (name) |
| :"memory" |
| ); |
| return retval; |
| }; |
| */ |
| extern inline u32_t safe_cli(void) |
| { |
| u32_t ifl; |
| __asm__ __volatile__ ( |
| "pushf\n\t" |
| "popl %0\n\t" |
| "cli\n" |
| : "=r" (ifl)); |
| return ifl; |
| } |
| extern inline void safe_sti(u32_t ifl) |
| { |
| __asm__ __volatile__ ( |
| "pushl %0\n\t" |
| "popf\n" |
| : : "r" (ifl) |
| ); |
| } |
| extern inline void __clear (void * dst, unsigned len) |
| { |
| u32_t tmp; |
| __asm__ __volatile__ ( |
| // "xorl %%eax, %%eax \n\t" |
| "cld \n\t" |
| "rep stosb \n" |
| :"=c"(tmp),"=D"(tmp) |
| :"a"(0),"c"(len),"D"(dst)); |
| __asm__ __volatile__ ("":::"ecx","edi"); |
| }; |
| extern inline void out8(const u16_t port, const u8_t val) |
| { |
| __asm__ __volatile__ |
| ("outb %1, %0\n" : : "dN"(port), "a"(val)); |
| } |
| extern inline void out16(const u16_t port, const u16_t val) |
| { |
| __asm__ __volatile__ |
| ("outw %1, %0\n" : : "dN"(port), "a"(val)); |
| } |
| extern inline void out32(const u16_t port, const u32_t val) |
| { |
| __asm__ __volatile__ |
| ("outl %1, %0\n" : : "dN"(port), "a"(val)); |
| } |
| extern inline u8_t in8(const u16_t port) |
| { |
| u8_t tmp; |
| __asm__ __volatile__ |
| ("inb %1, %0\n" : "=a"(tmp) : "dN"(port)); |
| return tmp; |
| }; |
| extern inline u16_t in16(const u16_t port) |
| { |
| u16_t tmp; |
| __asm__ __volatile__ |
| ("inw %1, %0\n" : "=a"(tmp) : "dN"(port)); |
| return tmp; |
| }; |
| extern inline u32_t in32(const u16_t port) |
| { |
| u32_t tmp; |
| __asm__ __volatile__ |
| ("inl %1, %0\n" : "=a"(tmp) : "dN"(port)); |
| return tmp; |
| }; |
| extern inline void delay(int time) |
| { |
| __asm__ __volatile__ ( |
| "call *__imp__Delay" |
| ::"b" (time)); |
| __asm__ __volatile__ ( |
| "":::"ebx"); |
| } |
| extern inline void change_task() |
| { |
| __asm__ __volatile__ ( |
| "call *__imp__ChangeTask"); |
| } |
| int drm_order(unsigned long size); |
| #endif |
| /drivers/video/drm/include/types.h |
|---|
| 0,0 → 1,199 |
| #ifndef __TYPES_H__ |
| #define __TYPES_H__ |
| typedef int bool; |
| #define false 0 |
| #define true 1 |
| typedef unsigned int size_t; |
| typedef unsigned int count_t; |
| typedef unsigned int addr_t; |
| typedef unsigned char u8; |
| typedef unsigned short u16; |
| typedef unsigned int u32; |
| typedef unsigned long long u64; |
| typedef unsigned char __u8; |
| typedef unsigned short __u16; |
| typedef unsigned int __u32; |
| typedef unsigned long long __u64; |
| typedef signed char __s8; |
| typedef signed short __s16; |
| typedef signed int __s32; |
| typedef signed long long __s64; |
| typedef unsigned char uint8_t; |
| typedef unsigned short uint16_t; |
| typedef unsigned int uint32_t; |
| typedef unsigned long long uint64_t; |
| typedef unsigned char u8_t; |
| typedef unsigned short u16_t; |
| typedef unsigned int u32_t; |
| typedef unsigned long long u64_t; |
| #define NULL (void*)0 |
| typedef uint32_t dma_addr_t; |
| typedef uint32_t resource_size_t; |
| #define __user |
| #define cpu_to_le16(v16) (v16) |
| #define cpu_to_le32(v32) (v32) |
| #define cpu_to_le64(v64) (v64) |
| #define le16_to_cpu(v16) (v16) |
| #define le32_to_cpu(v32) (v32) |
| #define le64_to_cpu(v64) (v64) |
| #define likely(x) __builtin_expect(!!(x), 1) |
| #define unlikely(x) __builtin_expect(!!(x), 0) |
| #define KERN_EMERG "<0>" /* system is unusable */ |
| #define KERN_ALERT "<1>" /* action must be taken immediately */ |
| #define KERN_CRIT "<2>" /* critical conditions */ |
| #define KERN_ERR "<3>" /* error conditions */ |
| #define KERN_WARNING "<4>" /* warning conditions */ |
| #define KERN_NOTICE "<5>" /* normal but significant condition */ |
| #define KERN_INFO "<6>" /* informational */ |
| #define KERN_DEBUG "<7>" /* debug-level messages */ |
| //int printk(const char *fmt, ...); |
| #define printk(fmt, arg...) dbgprintf(fmt , ##arg) |
| #define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */ |
| #define DRM_INFO(fmt, arg...) dbgprintf("DRM: "fmt , ##arg) |
| #define DRM_DEBUG(fmt, arg...) \ |
| printk(KERN_ERR "[" DRM_NAME ":%s] *ERROR* " fmt , __func__ , ##arg) |
| #define DRM_ERROR(fmt, arg...) \ |
| printk(KERN_ERR "[" DRM_NAME ":%s] *ERROR* " fmt , __func__ , ##arg) |
| #define BUILD_BUG_ON_ZERO(e) (sizeof(char[1 - 2 * !!(e)]) - 1) |
| #define __must_be_array(a) \ |
| BUILD_BUG_ON_ZERO(__builtin_types_compatible_p(typeof(a), typeof(&a[0]))) |
| #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]) + __must_be_array(arr)) |
| #ifndef HAVE_ARCH_BUG |
| #define BUG() do { \ |
| printk("BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __FUNCTION__); \ |
| /* panic("BUG!"); */ \ |
| } while (0) |
| #endif |
| #ifndef HAVE_ARCH_BUG_ON |
| #define BUG_ON(condition) do { if (unlikely(condition)) BUG(); } while(0) |
| #endif |
| #define MTRR_TYPE_UNCACHABLE 0 |
| #define MTRR_TYPE_WRCOMB 1 |
| #define MTRR_TYPE_WRTHROUGH 4 |
| #define MTRR_TYPE_WRPROT 5 |
| #define MTRR_TYPE_WRBACK 6 |
| #define MTRR_NUM_TYPES 7 |
| int dbgprintf(const char* format, ...); |
| #define GFP_KERNEL 0 |
| //#include <string.h> |
| void* memcpy(void *s1, const void *s2, size_t n); |
| void* memset(void *s, int c, size_t n); |
| size_t strlen(const char *s); |
| void *malloc(size_t size); |
| #define kfree free |
| static inline void *kzalloc(size_t size, u32_t flags) |
| { |
| void *ret = malloc(size); |
| memset(ret, 0, size); |
| return ret; |
| } |
| struct drm_gem_object { |
| /** Reference count of this object */ |
| // struct kref refcount; |
| /** Handle count of this object. Each handle also holds a reference */ |
| // struct kref handlecount; |
| /** Related drm device */ |
| // struct drm_device *dev; |
| /** File representing the shmem storage */ |
| // struct file *filp; |
| /* Mapping info for this object */ |
| // struct drm_map_list map_list; |
| /** |
| * Size of the object, in bytes. Immutable over the object's |
| * lifetime. |
| */ |
| size_t size; |
| /** |
| * Global name for this object, starts at 1. 0 means unnamed. |
| * Access is covered by the object_name_lock in the related drm_device |
| */ |
| int name; |
| /** |
| * Memory domains. These monitor which caches contain read/write data |
| * related to the object. When transitioning from one set of domains |
| * to another, the driver is called to ensure that caches are suitably |
| * flushed and invalidated |
| */ |
| uint32_t read_domains; |
| uint32_t write_domain; |
| /** |
| * While validating an exec operation, the |
| * new read/write domain values are computed here. |
| * They will be transferred to the above values |
| * at the point that any cache flushing occurs |
| */ |
| uint32_t pending_read_domains; |
| uint32_t pending_write_domain; |
| void *driver_private; |
| }; |
| struct drm_file; |
| #define offsetof(TYPE,MEMBER) __builtin_offsetof(TYPE,MEMBER) |
| #define container_of(ptr, type, member) ({ \ |
| const typeof( ((type *)0)->member ) *__mptr = (ptr); \ |
| (type *)( (char *)__mptr - offsetof(type,member) );}) |
| #define DRM_MEMORYBARRIER() __asm__ __volatile__("lock; addl $0,0(%esp)") |
| #endif //__TYPES_H__ |
| /drivers/video/drm/radeon/ObjectID.h |
|---|
| 0,0 → 1,578 |
| /* |
| * Copyright 2006-2007 Advanced Micro Devices, Inc. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice shall be included in |
| * all copies or substantial portions of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| * OTHER DEALINGS IN THE SOFTWARE. |
| */ |
| /* based on stg/asic_reg/drivers/inc/asic_reg/ObjectID.h ver 23 */ |
| #ifndef _OBJECTID_H |
| #define _OBJECTID_H |
| #if defined(_X86_) |
| #pragma pack(1) |
| #endif |
| /****************************************************/ |
| /* Graphics Object Type Definition */ |
| /****************************************************/ |
| #define GRAPH_OBJECT_TYPE_NONE 0x0 |
| #define GRAPH_OBJECT_TYPE_GPU 0x1 |
| #define GRAPH_OBJECT_TYPE_ENCODER 0x2 |
| #define GRAPH_OBJECT_TYPE_CONNECTOR 0x3 |
| #define GRAPH_OBJECT_TYPE_ROUTER 0x4 |
| /* deleted */ |
| /****************************************************/ |
| /* Encoder Object ID Definition */ |
| /****************************************************/ |
| #define ENCODER_OBJECT_ID_NONE 0x00 |
| /* Radeon Class Display Hardware */ |
| #define ENCODER_OBJECT_ID_INTERNAL_LVDS 0x01 |
| #define ENCODER_OBJECT_ID_INTERNAL_TMDS1 0x02 |
| #define ENCODER_OBJECT_ID_INTERNAL_TMDS2 0x03 |
| #define ENCODER_OBJECT_ID_INTERNAL_DAC1 0x04 |
| #define ENCODER_OBJECT_ID_INTERNAL_DAC2 0x05 /* TV/CV DAC */ |
| #define ENCODER_OBJECT_ID_INTERNAL_SDVOA 0x06 |
| #define ENCODER_OBJECT_ID_INTERNAL_SDVOB 0x07 |
| /* External Third Party Encoders */ |
| #define ENCODER_OBJECT_ID_SI170B 0x08 |
| #define ENCODER_OBJECT_ID_CH7303 0x09 |
| #define ENCODER_OBJECT_ID_CH7301 0x0A |
| #define ENCODER_OBJECT_ID_INTERNAL_DVO1 0x0B /* This belongs to Radeon Class Display Hardware */ |
| #define ENCODER_OBJECT_ID_EXTERNAL_SDVOA 0x0C |
| #define ENCODER_OBJECT_ID_EXTERNAL_SDVOB 0x0D |
| #define ENCODER_OBJECT_ID_TITFP513 0x0E |
| #define ENCODER_OBJECT_ID_INTERNAL_LVTM1 0x0F /* not used for Radeon */ |
| #define ENCODER_OBJECT_ID_VT1623 0x10 |
| #define ENCODER_OBJECT_ID_HDMI_SI1930 0x11 |
| #define ENCODER_OBJECT_ID_HDMI_INTERNAL 0x12 |
| /* Kaleidoscope (KLDSCP) Class Display Hardware (internal) */ |
| #define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 0x13 |
| #define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1 0x14 |
| #define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1 0x15 |
| #define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2 0x16 /* Shared with CV/TV and CRT */ |
| #define ENCODER_OBJECT_ID_SI178 0X17 /* External TMDS (dual link, no HDCP.) */ |
| #define ENCODER_OBJECT_ID_MVPU_FPGA 0x18 /* MVPU FPGA chip */ |
| #define ENCODER_OBJECT_ID_INTERNAL_DDI 0x19 |
| #define ENCODER_OBJECT_ID_VT1625 0x1A |
| #define ENCODER_OBJECT_ID_HDMI_SI1932 0x1B |
| #define ENCODER_OBJECT_ID_DP_AN9801 0x1C |
| #define ENCODER_OBJECT_ID_DP_DP501 0x1D |
| #define ENCODER_OBJECT_ID_INTERNAL_UNIPHY 0x1E |
| #define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA 0x1F |
| #define ENCODER_OBJECT_ID_INTERNAL_UNIPHY1 0x20 |
| #define ENCODER_OBJECT_ID_INTERNAL_UNIPHY2 0x21 |
| #define ENCODER_OBJECT_ID_GENERAL_EXTERNAL_DVO 0xFF |
| /****************************************************/ |
| /* Connector Object ID Definition */ |
| /****************************************************/ |
| #define CONNECTOR_OBJECT_ID_NONE 0x00 |
| #define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I 0x01 |
| #define CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I 0x02 |
| #define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D 0x03 |
| #define CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D 0x04 |
| #define CONNECTOR_OBJECT_ID_VGA 0x05 |
| #define CONNECTOR_OBJECT_ID_COMPOSITE 0x06 |
| #define CONNECTOR_OBJECT_ID_SVIDEO 0x07 |
| #define CONNECTOR_OBJECT_ID_YPbPr 0x08 |
| #define CONNECTOR_OBJECT_ID_D_CONNECTOR 0x09 |
| #define CONNECTOR_OBJECT_ID_9PIN_DIN 0x0A /* Supports both CV & TV */ |
| #define CONNECTOR_OBJECT_ID_SCART 0x0B |
| #define CONNECTOR_OBJECT_ID_HDMI_TYPE_A 0x0C |
| #define CONNECTOR_OBJECT_ID_HDMI_TYPE_B 0x0D |
| #define CONNECTOR_OBJECT_ID_LVDS 0x0E |
| #define CONNECTOR_OBJECT_ID_7PIN_DIN 0x0F |
| #define CONNECTOR_OBJECT_ID_PCIE_CONNECTOR 0x10 |
| #define CONNECTOR_OBJECT_ID_CROSSFIRE 0x11 |
| #define CONNECTOR_OBJECT_ID_HARDCODE_DVI 0x12 |
| #define CONNECTOR_OBJECT_ID_DISPLAYPORT 0x13 |
| /* deleted */ |
| /****************************************************/ |
| /* Router Object ID Definition */ |
| /****************************************************/ |
| #define ROUTER_OBJECT_ID_NONE 0x00 |
| #define ROUTER_OBJECT_ID_I2C_EXTENDER_CNTL 0x01 |
| /****************************************************/ |
| /* Graphics Object ENUM ID Definition */ |
| /****************************************************/ |
| #define GRAPH_OBJECT_ENUM_ID1 0x01 |
| #define GRAPH_OBJECT_ENUM_ID2 0x02 |
| #define GRAPH_OBJECT_ENUM_ID3 0x03 |
| #define GRAPH_OBJECT_ENUM_ID4 0x04 |
| #define GRAPH_OBJECT_ENUM_ID5 0x05 |
| #define GRAPH_OBJECT_ENUM_ID6 0x06 |
| /****************************************************/ |
| /* Graphics Object ID Bit definition */ |
| /****************************************************/ |
| #define OBJECT_ID_MASK 0x00FF |
| #define ENUM_ID_MASK 0x0700 |
| #define RESERVED1_ID_MASK 0x0800 |
| #define OBJECT_TYPE_MASK 0x7000 |
| #define RESERVED2_ID_MASK 0x8000 |
| #define OBJECT_ID_SHIFT 0x00 |
| #define ENUM_ID_SHIFT 0x08 |
| #define OBJECT_TYPE_SHIFT 0x0C |
| /****************************************************/ |
| /* Graphics Object family definition */ |
| /****************************************************/ |
| #define CONSTRUCTOBJECTFAMILYID(GRAPHICS_OBJECT_TYPE, GRAPHICS_OBJECT_ID) \ |
| (GRAPHICS_OBJECT_TYPE << OBJECT_TYPE_SHIFT | \ |
| GRAPHICS_OBJECT_ID << OBJECT_ID_SHIFT) |
| /****************************************************/ |
| /* GPU Object ID definition - Shared with BIOS */ |
| /****************************************************/ |
| #define GPU_ENUM_ID1 (GRAPH_OBJECT_TYPE_GPU << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT) |
| /****************************************************/ |
| /* Encoder Object ID definition - Shared with BIOS */ |
| /****************************************************/ |
| /* |
| #define ENCODER_INTERNAL_LVDS_ENUM_ID1 0x2101 |
| #define ENCODER_INTERNAL_TMDS1_ENUM_ID1 0x2102 |
| #define ENCODER_INTERNAL_TMDS2_ENUM_ID1 0x2103 |
| #define ENCODER_INTERNAL_DAC1_ENUM_ID1 0x2104 |
| #define ENCODER_INTERNAL_DAC2_ENUM_ID1 0x2105 |
| #define ENCODER_INTERNAL_SDVOA_ENUM_ID1 0x2106 |
| #define ENCODER_INTERNAL_SDVOB_ENUM_ID1 0x2107 |
| #define ENCODER_SIL170B_ENUM_ID1 0x2108 |
| #define ENCODER_CH7303_ENUM_ID1 0x2109 |
| #define ENCODER_CH7301_ENUM_ID1 0x210A |
| #define ENCODER_INTERNAL_DVO1_ENUM_ID1 0x210B |
| #define ENCODER_EXTERNAL_SDVOA_ENUM_ID1 0x210C |
| #define ENCODER_EXTERNAL_SDVOB_ENUM_ID1 0x210D |
| #define ENCODER_TITFP513_ENUM_ID1 0x210E |
| #define ENCODER_INTERNAL_LVTM1_ENUM_ID1 0x210F |
| #define ENCODER_VT1623_ENUM_ID1 0x2110 |
| #define ENCODER_HDMI_SI1930_ENUM_ID1 0x2111 |
| #define ENCODER_HDMI_INTERNAL_ENUM_ID1 0x2112 |
| #define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1 0x2113 |
| #define ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1 0x2114 |
| #define ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1 0x2115 |
| #define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1 0x2116 |
| #define ENCODER_SI178_ENUM_ID1 0x2117 |
| #define ENCODER_MVPU_FPGA_ENUM_ID1 0x2118 |
| #define ENCODER_INTERNAL_DDI_ENUM_ID1 0x2119 |
| #define ENCODER_VT1625_ENUM_ID1 0x211A |
| #define ENCODER_HDMI_SI1932_ENUM_ID1 0x211B |
| #define ENCODER_ENCODER_DP_AN9801_ENUM_ID1 0x211C |
| #define ENCODER_DP_DP501_ENUM_ID1 0x211D |
| #define ENCODER_INTERNAL_UNIPHY_ENUM_ID1 0x211E |
| */ |
| #define ENCODER_INTERNAL_LVDS_ENUM_ID1 \ |
| (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ |
| ENCODER_OBJECT_ID_INTERNAL_LVDS << OBJECT_ID_SHIFT) |
| #define ENCODER_INTERNAL_TMDS1_ENUM_ID1 \ |
| (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ |
| ENCODER_OBJECT_ID_INTERNAL_TMDS1 << OBJECT_ID_SHIFT) |
| #define ENCODER_INTERNAL_TMDS2_ENUM_ID1 \ |
| (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ |
| ENCODER_OBJECT_ID_INTERNAL_TMDS2 << OBJECT_ID_SHIFT) |
| #define ENCODER_INTERNAL_DAC1_ENUM_ID1 \ |
| (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ |
| ENCODER_OBJECT_ID_INTERNAL_DAC1 << OBJECT_ID_SHIFT) |
| #define ENCODER_INTERNAL_DAC2_ENUM_ID1 \ |
| (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ |
| ENCODER_OBJECT_ID_INTERNAL_DAC2 << OBJECT_ID_SHIFT) |
| #define ENCODER_INTERNAL_SDVOA_ENUM_ID1 \ |
| (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ |
| ENCODER_OBJECT_ID_INTERNAL_SDVOA << OBJECT_ID_SHIFT) |
| #define ENCODER_INTERNAL_SDVOA_ENUM_ID2 \ |
| (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ |
| ENCODER_OBJECT_ID_INTERNAL_SDVOA << OBJECT_ID_SHIFT) |
| #define ENCODER_INTERNAL_SDVOB_ENUM_ID1 \ |
| (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ |
| ENCODER_OBJECT_ID_INTERNAL_SDVOB << OBJECT_ID_SHIFT) |
| #define ENCODER_SIL170B_ENUM_ID1 \ |
| (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ |
| ENCODER_OBJECT_ID_SI170B << OBJECT_ID_SHIFT) |
| #define ENCODER_CH7303_ENUM_ID1 \ |
| (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ |
| ENCODER_OBJECT_ID_CH7303 << OBJECT_ID_SHIFT) |
| #define ENCODER_CH7301_ENUM_ID1 \ |
| (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ |
| ENCODER_OBJECT_ID_CH7301 << OBJECT_ID_SHIFT) |
| #define ENCODER_INTERNAL_DVO1_ENUM_ID1 \ |
| (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ |
| ENCODER_OBJECT_ID_INTERNAL_DVO1 << OBJECT_ID_SHIFT) |
| #define ENCODER_EXTERNAL_SDVOA_ENUM_ID1 \ |
| (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ |
| ENCODER_OBJECT_ID_EXTERNAL_SDVOA << OBJECT_ID_SHIFT) |
| #define ENCODER_EXTERNAL_SDVOA_ENUM_ID2 \ |
| (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ |
| ENCODER_OBJECT_ID_EXTERNAL_SDVOA << OBJECT_ID_SHIFT) |
| #define ENCODER_EXTERNAL_SDVOB_ENUM_ID1 \ |
| (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ |
| ENCODER_OBJECT_ID_EXTERNAL_SDVOB << OBJECT_ID_SHIFT) |
| #define ENCODER_TITFP513_ENUM_ID1 \ |
| (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ |
| ENCODER_OBJECT_ID_TITFP513 << OBJECT_ID_SHIFT) |
| #define ENCODER_INTERNAL_LVTM1_ENUM_ID1 \ |
| (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ |
| ENCODER_OBJECT_ID_INTERNAL_LVTM1 << OBJECT_ID_SHIFT) |
| #define ENCODER_VT1623_ENUM_ID1 \ |
| (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ |
| ENCODER_OBJECT_ID_VT1623 << OBJECT_ID_SHIFT) |
| #define ENCODER_HDMI_SI1930_ENUM_ID1 \ |
| (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ |
| ENCODER_OBJECT_ID_HDMI_SI1930 << OBJECT_ID_SHIFT) |
| #define ENCODER_HDMI_INTERNAL_ENUM_ID1 \ |
| (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ |
| ENCODER_OBJECT_ID_HDMI_INTERNAL << OBJECT_ID_SHIFT) |
| #define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1 \ |
| (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ |
| ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 << OBJECT_ID_SHIFT) |
| #define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID2 \ |
| (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ |
| ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 << OBJECT_ID_SHIFT) |
| #define ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1 \ |
| (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ |
| ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1 << OBJECT_ID_SHIFT) |
| #define ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1 \ |
| (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ |
| ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1 << OBJECT_ID_SHIFT) |
| #define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1 \ |
| (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ |
| ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2 << OBJECT_ID_SHIFT) /* Shared with CV/TV and CRT */ |
| #define ENCODER_SI178_ENUM_ID1 \ |
| (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ |
| ENCODER_OBJECT_ID_SI178 << OBJECT_ID_SHIFT) |
| #define ENCODER_MVPU_FPGA_ENUM_ID1 \ |
| (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ |
| ENCODER_OBJECT_ID_MVPU_FPGA << OBJECT_ID_SHIFT) |
| #define ENCODER_INTERNAL_DDI_ENUM_ID1 \ |
| (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ |
| ENCODER_OBJECT_ID_INTERNAL_DDI << OBJECT_ID_SHIFT) |
| #define ENCODER_VT1625_ENUM_ID1 \ |
| (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ |
| ENCODER_OBJECT_ID_VT1625 << OBJECT_ID_SHIFT) |
| #define ENCODER_HDMI_SI1932_ENUM_ID1 \ |
| (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ |
| ENCODER_OBJECT_ID_HDMI_SI1932 << OBJECT_ID_SHIFT) |
| #define ENCODER_DP_DP501_ENUM_ID1 \ |
| (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ |
| ENCODER_OBJECT_ID_DP_DP501 << OBJECT_ID_SHIFT) |
| #define ENCODER_DP_AN9801_ENUM_ID1 \ |
| (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ |
| ENCODER_OBJECT_ID_DP_AN9801 << OBJECT_ID_SHIFT) |
| #define ENCODER_INTERNAL_UNIPHY_ENUM_ID1 \ |
| (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ |
| ENCODER_OBJECT_ID_INTERNAL_UNIPHY << OBJECT_ID_SHIFT) |
| #define ENCODER_INTERNAL_UNIPHY_ENUM_ID2 \ |
| (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ |
| ENCODER_OBJECT_ID_INTERNAL_UNIPHY << OBJECT_ID_SHIFT) |
| #define ENCODER_INTERNAL_KLDSCP_LVTMA_ENUM_ID1 \ |
| (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ |
| ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA << OBJECT_ID_SHIFT) |
| #define ENCODER_INTERNAL_UNIPHY1_ENUM_ID1 \ |
| (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ |
| ENCODER_OBJECT_ID_INTERNAL_UNIPHY1 << OBJECT_ID_SHIFT) |
| #define ENCODER_INTERNAL_UNIPHY1_ENUM_ID2 \ |
| (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ |
| ENCODER_OBJECT_ID_INTERNAL_UNIPHY1 << OBJECT_ID_SHIFT) |
| #define ENCODER_INTERNAL_UNIPHY2_ENUM_ID1 \ |
| (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ |
| ENCODER_OBJECT_ID_INTERNAL_UNIPHY2 << OBJECT_ID_SHIFT) |
| #define ENCODER_INTERNAL_UNIPHY2_ENUM_ID2 \ |
| (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ |
| ENCODER_OBJECT_ID_INTERNAL_UNIPHY2 << OBJECT_ID_SHIFT) |
| #define ENCODER_GENERAL_EXTERNAL_DVO_ENUM_ID1 \ |
| (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ |
| ENCODER_OBJECT_ID_GENERAL_EXTERNAL_DVO << OBJECT_ID_SHIFT) |
| /****************************************************/ |
| /* Connector Object ID definition - Shared with BIOS */ |
| /****************************************************/ |
| /* |
| #define CONNECTOR_SINGLE_LINK_DVI_I_ENUM_ID1 0x3101 |
| #define CONNECTOR_DUAL_LINK_DVI_I_ENUM_ID1 0x3102 |
| #define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID1 0x3103 |
| #define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID1 0x3104 |
| #define CONNECTOR_VGA_ENUM_ID1 0x3105 |
| #define CONNECTOR_COMPOSITE_ENUM_ID1 0x3106 |
| #define CONNECTOR_SVIDEO_ENUM_ID1 0x3107 |
| #define CONNECTOR_YPbPr_ENUM_ID1 0x3108 |
| #define CONNECTOR_D_CONNECTORE_ENUM_ID1 0x3109 |
| #define CONNECTOR_9PIN_DIN_ENUM_ID1 0x310A |
| #define CONNECTOR_SCART_ENUM_ID1 0x310B |
| #define CONNECTOR_HDMI_TYPE_A_ENUM_ID1 0x310C |
| #define CONNECTOR_HDMI_TYPE_B_ENUM_ID1 0x310D |
| #define CONNECTOR_LVDS_ENUM_ID1 0x310E |
| #define CONNECTOR_7PIN_DIN_ENUM_ID1 0x310F |
| #define CONNECTOR_PCIE_CONNECTOR_ENUM_ID1 0x3110 |
| */ |
| #define CONNECTOR_LVDS_ENUM_ID1 \ |
| (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ |
| CONNECTOR_OBJECT_ID_LVDS << OBJECT_ID_SHIFT) |
| #define CONNECTOR_SINGLE_LINK_DVI_I_ENUM_ID1 \ |
| (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ |
| CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I << OBJECT_ID_SHIFT) |
| #define CONNECTOR_SINGLE_LINK_DVI_I_ENUM_ID2 \ |
| (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ |
| CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I << OBJECT_ID_SHIFT) |
| #define CONNECTOR_DUAL_LINK_DVI_I_ENUM_ID1 \ |
| (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ |
| CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I << OBJECT_ID_SHIFT) |
| #define CONNECTOR_DUAL_LINK_DVI_I_ENUM_ID2 \ |
| (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ |
| CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I << OBJECT_ID_SHIFT) |
| #define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID1 \ |
| (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ |
| CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT) |
| #define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID2 \ |
| (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ |
| CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT) |
| #define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID1 \ |
| (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ |
| CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D << OBJECT_ID_SHIFT) |
| #define CONNECTOR_VGA_ENUM_ID1 \ |
| (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ |
| CONNECTOR_OBJECT_ID_VGA << OBJECT_ID_SHIFT) |
| #define CONNECTOR_VGA_ENUM_ID2 \ |
| (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ |
| CONNECTOR_OBJECT_ID_VGA << OBJECT_ID_SHIFT) |
| #define CONNECTOR_COMPOSITE_ENUM_ID1 \ |
| (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ |
| CONNECTOR_OBJECT_ID_COMPOSITE << OBJECT_ID_SHIFT) |
| #define CONNECTOR_SVIDEO_ENUM_ID1 \ |
| (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ |
| CONNECTOR_OBJECT_ID_SVIDEO << OBJECT_ID_SHIFT) |
| #define CONNECTOR_YPbPr_ENUM_ID1 \ |
| (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ |
| CONNECTOR_OBJECT_ID_YPbPr << OBJECT_ID_SHIFT) |
| #define CONNECTOR_D_CONNECTOR_ENUM_ID1 \ |
| (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ |
| CONNECTOR_OBJECT_ID_D_CONNECTOR << OBJECT_ID_SHIFT) |
| #define CONNECTOR_9PIN_DIN_ENUM_ID1 \ |
| (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ |
| CONNECTOR_OBJECT_ID_9PIN_DIN << OBJECT_ID_SHIFT) |
| #define CONNECTOR_SCART_ENUM_ID1 \ |
| (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ |
| CONNECTOR_OBJECT_ID_SCART << OBJECT_ID_SHIFT) |
| #define CONNECTOR_HDMI_TYPE_A_ENUM_ID1 \ |
| (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ |
| CONNECTOR_OBJECT_ID_HDMI_TYPE_A << OBJECT_ID_SHIFT) |
| #define CONNECTOR_HDMI_TYPE_B_ENUM_ID1 \ |
| (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ |
| CONNECTOR_OBJECT_ID_HDMI_TYPE_B << OBJECT_ID_SHIFT) |
| #define CONNECTOR_7PIN_DIN_ENUM_ID1 \ |
| (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ |
| CONNECTOR_OBJECT_ID_7PIN_DIN << OBJECT_ID_SHIFT) |
| #define CONNECTOR_PCIE_CONNECTOR_ENUM_ID1 \ |
| (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ |
| CONNECTOR_OBJECT_ID_PCIE_CONNECTOR << OBJECT_ID_SHIFT) |
| #define CONNECTOR_PCIE_CONNECTOR_ENUM_ID2 \ |
| (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ |
| CONNECTOR_OBJECT_ID_PCIE_CONNECTOR << OBJECT_ID_SHIFT) |
| #define CONNECTOR_CROSSFIRE_ENUM_ID1 \ |
| (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ |
| CONNECTOR_OBJECT_ID_CROSSFIRE << OBJECT_ID_SHIFT) |
| #define CONNECTOR_CROSSFIRE_ENUM_ID2 \ |
| (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ |
| CONNECTOR_OBJECT_ID_CROSSFIRE << OBJECT_ID_SHIFT) |
| #define CONNECTOR_HARDCODE_DVI_ENUM_ID1 \ |
| (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ |
| CONNECTOR_OBJECT_ID_HARDCODE_DVI << OBJECT_ID_SHIFT) |
| #define CONNECTOR_HARDCODE_DVI_ENUM_ID2 \ |
| (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ |
| CONNECTOR_OBJECT_ID_HARDCODE_DVI << OBJECT_ID_SHIFT) |
| #define CONNECTOR_DISPLAYPORT_ENUM_ID1 \ |
| (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ |
| CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT) |
| #define CONNECTOR_DISPLAYPORT_ENUM_ID2 \ |
| (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ |
| CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT) |
| #define CONNECTOR_DISPLAYPORT_ENUM_ID3 \ |
| (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID3 << ENUM_ID_SHIFT |\ |
| CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT) |
| #define CONNECTOR_DISPLAYPORT_ENUM_ID4 \ |
| (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID4 << ENUM_ID_SHIFT |\ |
| CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT) |
| /****************************************************/ |
| /* Router Object ID definition - Shared with BIOS */ |
| /****************************************************/ |
| #define ROUTER_I2C_EXTENDER_CNTL_ENUM_ID1 \ |
| (GRAPH_OBJECT_TYPE_ROUTER << OBJECT_TYPE_SHIFT |\ |
| GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ |
| ROUTER_OBJECT_ID_I2C_EXTENDER_CNTL << OBJECT_ID_SHIFT) |
| /* deleted */ |
| /****************************************************/ |
| /* Object Cap definition - Shared with BIOS */ |
| /****************************************************/ |
| #define GRAPHICS_OBJECT_CAP_I2C 0x00000001L |
| #define GRAPHICS_OBJECT_CAP_TABLE_ID 0x00000002L |
| #define GRAPHICS_OBJECT_I2CCOMMAND_TABLE_ID 0x01 |
| #define GRAPHICS_OBJECT_HOTPLUGDETECTIONINTERUPT_TABLE_ID 0x02 |
| #define GRAPHICS_OBJECT_ENCODER_OUTPUT_PROTECTION_TABLE_ID 0x03 |
| #if defined(_X86_) |
| #pragma pack() |
| #endif |
| #endif /*GRAPHICTYPE */ |
| /drivers/video/drm/radeon/atom-bits.h |
|---|
| 0,0 → 1,48 |
| /* |
| * Copyright 2008 Advanced Micro Devices, Inc. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice shall be included in |
| * all copies or substantial portions of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| * OTHER DEALINGS IN THE SOFTWARE. |
| * |
| * Author: Stanislaw Skowronek |
| */ |
| #ifndef ATOM_BITS_H |
| #define ATOM_BITS_H |
| static inline uint8_t get_u8(void *bios, int ptr) |
| { |
| return ((unsigned char *)bios)[ptr]; |
| } |
| #define U8(ptr) get_u8(ctx->ctx->bios, (ptr)) |
| #define CU8(ptr) get_u8(ctx->bios, (ptr)) |
| static inline uint16_t get_u16(void *bios, int ptr) |
| { |
| return get_u8(bios ,ptr)|(((uint16_t)get_u8(bios, ptr+1))<<8); |
| } |
| #define U16(ptr) get_u16(ctx->ctx->bios, (ptr)) |
| #define CU16(ptr) get_u16(ctx->bios, (ptr)) |
| static inline uint32_t get_u32(void *bios, int ptr) |
| { |
| return get_u16(bios, ptr)|(((uint32_t)get_u16(bios, ptr+2))<<16); |
| } |
| #define U32(ptr) get_u32(ctx->ctx->bios, (ptr)) |
| #define CU32(ptr) get_u32(ctx->bios, (ptr)) |
| #define CSTR(ptr) (((char *)(ctx->bios))+(ptr)) |
| #endif |
| /drivers/video/drm/radeon/atom-names.h |
|---|
| 0,0 → 1,100 |
| /* |
| * Copyright 2008 Advanced Micro Devices, Inc. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice shall be included in |
| * all copies or substantial portions of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| * OTHER DEALINGS IN THE SOFTWARE. |
| * |
| * Author: Stanislaw Skowronek |
| */ |
| #ifndef ATOM_NAMES_H |
| #define ATOM_NAMES_H |
| #include "atom.h" |
| #ifdef ATOM_DEBUG |
| #define ATOM_OP_NAMES_CNT 123 |
| static char *atom_op_names[ATOM_OP_NAMES_CNT] = { |
| "RESERVED", "MOVE_REG", "MOVE_PS", "MOVE_WS", "MOVE_FB", "MOVE_PLL", |
| "MOVE_MC", "AND_REG", "AND_PS", "AND_WS", "AND_FB", "AND_PLL", "AND_MC", |
| "OR_REG", "OR_PS", "OR_WS", "OR_FB", "OR_PLL", "OR_MC", "SHIFT_LEFT_REG", |
| "SHIFT_LEFT_PS", "SHIFT_LEFT_WS", "SHIFT_LEFT_FB", "SHIFT_LEFT_PLL", |
| "SHIFT_LEFT_MC", "SHIFT_RIGHT_REG", "SHIFT_RIGHT_PS", "SHIFT_RIGHT_WS", |
| "SHIFT_RIGHT_FB", "SHIFT_RIGHT_PLL", "SHIFT_RIGHT_MC", "MUL_REG", |
| "MUL_PS", "MUL_WS", "MUL_FB", "MUL_PLL", "MUL_MC", "DIV_REG", "DIV_PS", |
| "DIV_WS", "DIV_FB", "DIV_PLL", "DIV_MC", "ADD_REG", "ADD_PS", "ADD_WS", |
| "ADD_FB", "ADD_PLL", "ADD_MC", "SUB_REG", "SUB_PS", "SUB_WS", "SUB_FB", |
| "SUB_PLL", "SUB_MC", "SET_ATI_PORT", "SET_PCI_PORT", "SET_SYS_IO_PORT", |
| "SET_REG_BLOCK", "SET_FB_BASE", "COMPARE_REG", "COMPARE_PS", |
| "COMPARE_WS", "COMPARE_FB", "COMPARE_PLL", "COMPARE_MC", "SWITCH", |
| "JUMP", "JUMP_EQUAL", "JUMP_BELOW", "JUMP_ABOVE", "JUMP_BELOW_OR_EQUAL", |
| "JUMP_ABOVE_OR_EQUAL", "JUMP_NOT_EQUAL", "TEST_REG", "TEST_PS", "TEST_WS", |
| "TEST_FB", "TEST_PLL", "TEST_MC", "DELAY_MILLISEC", "DELAY_MICROSEC", |
| "CALL_TABLE", "REPEAT", "CLEAR_REG", "CLEAR_PS", "CLEAR_WS", "CLEAR_FB", |
| "CLEAR_PLL", "CLEAR_MC", "NOP", "EOT", "MASK_REG", "MASK_PS", "MASK_WS", |
| "MASK_FB", "MASK_PLL", "MASK_MC", "POST_CARD", "BEEP", "SAVE_REG", |
| "RESTORE_REG", "SET_DATA_BLOCK", "XOR_REG", "XOR_PS", "XOR_WS", "XOR_FB", |
| "XOR_PLL", "XOR_MC", "SHL_REG", "SHL_PS", "SHL_WS", "SHL_FB", "SHL_PLL", |
| "SHL_MC", "SHR_REG", "SHR_PS", "SHR_WS", "SHR_FB", "SHR_PLL", "SHR_MC", |
| "DEBUG", "CTB_DS", |
| }; |
| #define ATOM_TABLE_NAMES_CNT 74 |
| static char *atom_table_names[ATOM_TABLE_NAMES_CNT] = { |
| "ASIC_Init", "GetDisplaySurfaceSize", "ASIC_RegistersInit", |
| "VRAM_BlockVenderDetection", "SetClocksRatio", "MemoryControllerInit", |
| "GPIO_PinInit", "MemoryParamAdjust", "DVOEncoderControl", |
| "GPIOPinControl", "SetEngineClock", "SetMemoryClock", "SetPixelClock", |
| "DynamicClockGating", "ResetMemoryDLL", "ResetMemoryDevice", |
| "MemoryPLLInit", "EnableMemorySelfRefresh", "AdjustMemoryController", |
| "EnableASIC_StaticPwrMgt", "ASIC_StaticPwrMgtStatusChange", |
| "DAC_LoadDetection", "TMDS2EncoderControl", "LCD1OutputControl", |
| "DAC1EncoderControl", "DAC2EncoderControl", "DVOOutputControl", |
| "CV1OutputControl", "SetCRTC_DPM_State", "TVEncoderControl", |
| "TMDS1EncoderControl", "LVDSEncoderControl", "TV1OutputControl", |
| "EnableScaler", "BlankCRTC", "EnableCRTC", "GetPixelClock", |
| "EnableVGA_Render", "EnableVGA_Access", "SetCRTC_Timing", |
| "SetCRTC_OverScan", "SetCRTC_Replication", "SelectCRTC_Source", |
| "EnableGraphSurfaces", "UpdateCRTC_DoubleBufferRegisters", |
| "LUT_AutoFill", "EnableHW_IconCursor", "GetMemoryClock", |
| "GetEngineClock", "SetCRTC_UsingDTDTiming", "TVBootUpStdPinDetection", |
| "DFP2OutputControl", "VRAM_BlockDetectionByStrap", "MemoryCleanUp", |
| "ReadEDIDFromHWAssistedI2C", "WriteOneByteToHWAssistedI2C", |
| "ReadHWAssistedI2CStatus", "SpeedFanControl", "PowerConnectorDetection", |
| "MC_Synchronization", "ComputeMemoryEnginePLL", "MemoryRefreshConversion", |
| "VRAM_GetCurrentInfoBlock", "DynamicMemorySettings", "MemoryTraining", |
| "EnableLVDS_SS", "DFP1OutputControl", "SetVoltage", "CRT1OutputControl", |
| "CRT2OutputControl", "SetupHWAssistedI2CStatus", "ClockSource", |
| "MemoryDeviceInit", "EnableYUV", |
| }; |
| #define ATOM_IO_NAMES_CNT 5 |
| static char *atom_io_names[ATOM_IO_NAMES_CNT] = { |
| "MM", "PLL", "MC", "PCIE", "PCIE PORT", |
| }; |
| #else |
| #define ATOM_OP_NAMES_CNT 0 |
| #define ATOM_TABLE_NAMES_CNT 0 |
| #define ATOM_IO_NAMES_CNT 0 |
| #endif |
| #endif |
| /drivers/video/drm/radeon/atom-types.h |
|---|
| 0,0 → 1,42 |
| /* |
| * Copyright 2008 Red Hat Inc. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice shall be included in |
| * all copies or substantial portions of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| * OTHER DEALINGS IN THE SOFTWARE. |
| * |
| * Author: Dave Airlie |
| */ |
| #ifndef ATOM_TYPES_H |
| #define ATOM_TYPES_H |
| /* sync atom types to kernel types */ |
| typedef uint16_t USHORT; |
| typedef uint32_t ULONG; |
| typedef uint8_t UCHAR; |
| #ifndef ATOM_BIG_ENDIAN |
| #if defined(__BIG_ENDIAN) |
| #define ATOM_BIG_ENDIAN 1 |
| #else |
| #define ATOM_BIG_ENDIAN 0 |
| #endif |
| #endif |
| #endif |
| /drivers/video/drm/radeon/atom.c |
|---|
| 0,0 → 1,1220 |
| /* |
| * Copyright 2008 Advanced Micro Devices, Inc. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice shall be included in |
| * all copies or substantial portions of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| * OTHER DEALINGS IN THE SOFTWARE. |
| * |
| * Author: Stanislaw Skowronek |
| */ |
| //#include <linux/module.h> |
| //#include <linux/sched.h> |
| #include <types.h> |
| #define ATOM_DEBUG |
| #include "atom.h" |
| #include "atom-names.h" |
| #include "atom-bits.h" |
| #define ATOM_COND_ABOVE 0 |
| #define ATOM_COND_ABOVEOREQUAL 1 |
| #define ATOM_COND_ALWAYS 2 |
| #define ATOM_COND_BELOW 3 |
| #define ATOM_COND_BELOWOREQUAL 4 |
| #define ATOM_COND_EQUAL 5 |
| #define ATOM_COND_NOTEQUAL 6 |
| #define ATOM_PORT_ATI 0 |
| #define ATOM_PORT_PCI 1 |
| #define ATOM_PORT_SYSIO 2 |
| #define ATOM_UNIT_MICROSEC 0 |
| #define ATOM_UNIT_MILLISEC 1 |
| #define PLL_INDEX 2 |
| #define PLL_DATA 3 |
| typedef struct { |
| struct atom_context *ctx; |
| uint32_t *ps, *ws; |
| int ps_shift; |
| uint16_t start; |
| } atom_exec_context; |
| int atom_debug = 0; |
| void atom_execute_table(struct atom_context *ctx, int index, uint32_t * params); |
| static uint32_t atom_arg_mask[8] = |
| { 0xFFFFFFFF, 0xFFFF, 0xFFFF00, 0xFFFF0000, 0xFF, 0xFF00, 0xFF0000, |
| 0xFF000000 }; |
| static int atom_arg_shift[8] = { 0, 0, 8, 16, 0, 8, 16, 24 }; |
| static int atom_dst_to_src[8][4] = { |
| /* translate destination alignment field to the source alignment encoding */ |
| {0, 0, 0, 0}, |
| {1, 2, 3, 0}, |
| {1, 2, 3, 0}, |
| {1, 2, 3, 0}, |
| {4, 5, 6, 7}, |
| {4, 5, 6, 7}, |
| {4, 5, 6, 7}, |
| {4, 5, 6, 7}, |
| }; |
| static int atom_def_dst[8] = { 0, 0, 1, 2, 0, 1, 2, 3 }; |
| static int debug_depth = 0; |
| #ifdef ATOM_DEBUG |
| static void debug_print_spaces(int n) |
| { |
| while (n--) |
| printk(" "); |
| } |
| #define DEBUG(...) do if (atom_debug) { printk(KERN_DEBUG __VA_ARGS__); } while (0) |
| #define SDEBUG(...) do if (atom_debug) { printk(KERN_DEBUG); debug_print_spaces(debug_depth); printk(__VA_ARGS__); } while (0) |
| #else |
| #define DEBUG(...) do { } while (0) |
| #define SDEBUG(...) do { } while (0) |
| #endif |
| static uint32_t atom_iio_execute(struct atom_context *ctx, int base, |
| uint32_t index, uint32_t data) |
| { |
| uint32_t temp = 0xCDCDCDCD; |
| while (1) |
| switch (CU8(base)) { |
| case ATOM_IIO_NOP: |
| base++; |
| break; |
| case ATOM_IIO_READ: |
| temp = ctx->card->reg_read(ctx->card, CU16(base + 1)); |
| base += 3; |
| break; |
| case ATOM_IIO_WRITE: |
| ctx->card->reg_write(ctx->card, CU16(base + 1), temp); |
| base += 3; |
| break; |
| case ATOM_IIO_CLEAR: |
| temp &= |
| ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << |
| CU8(base + 2)); |
| base += 3; |
| break; |
| case ATOM_IIO_SET: |
| temp |= |
| (0xFFFFFFFF >> (32 - CU8(base + 1))) << CU8(base + |
| 2); |
| base += 3; |
| break; |
| case ATOM_IIO_MOVE_INDEX: |
| temp &= |
| ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << |
| CU8(base + 2)); |
| temp |= |
| ((index >> CU8(base + 2)) & |
| (0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base + |
| 3); |
| base += 4; |
| break; |
| case ATOM_IIO_MOVE_DATA: |
| temp &= |
| ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << |
| CU8(base + 2)); |
| temp |= |
| ((data >> CU8(base + 2)) & |
| (0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base + |
| 3); |
| base += 4; |
| break; |
| case ATOM_IIO_MOVE_ATTR: |
| temp &= |
| ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << |
| CU8(base + 2)); |
| temp |= |
| ((ctx-> |
| io_attr >> CU8(base + 2)) & (0xFFFFFFFF >> (32 - |
| CU8 |
| (base |
| + |
| 1)))) |
| << CU8(base + 3); |
| base += 4; |
| break; |
| case ATOM_IIO_END: |
| return temp; |
| default: |
| printk(KERN_INFO "Unknown IIO opcode.\n"); |
| return 0; |
| } |
| } |
| static uint32_t atom_get_src_int(atom_exec_context *ctx, uint8_t attr, |
| int *ptr, uint32_t *saved, int print) |
| { |
| uint32_t idx, val = 0xCDCDCDCD, align, arg; |
| struct atom_context *gctx = ctx->ctx; |
| arg = attr & 7; |
| align = (attr >> 3) & 7; |
| switch (arg) { |
| case ATOM_ARG_REG: |
| idx = U16(*ptr); |
| (*ptr) += 2; |
| if (print) |
| DEBUG("REG[0x%04X]", idx); |
| idx += gctx->reg_block; |
| switch (gctx->io_mode) { |
| case ATOM_IO_MM: |
| val = gctx->card->reg_read(gctx->card, idx); |
| break; |
| case ATOM_IO_PCI: |
| printk(KERN_INFO |
| "PCI registers are not implemented.\n"); |
| return 0; |
| case ATOM_IO_SYSIO: |
| printk(KERN_INFO |
| "SYSIO registers are not implemented.\n"); |
| return 0; |
| default: |
| if (!(gctx->io_mode & 0x80)) { |
| printk(KERN_INFO "Bad IO mode.\n"); |
| return 0; |
| } |
| if (!gctx->iio[gctx->io_mode & 0x7F]) { |
| printk(KERN_INFO |
| "Undefined indirect IO read method %d.\n", |
| gctx->io_mode & 0x7F); |
| return 0; |
| } |
| val = |
| atom_iio_execute(gctx, |
| gctx->iio[gctx->io_mode & 0x7F], |
| idx, 0); |
| } |
| break; |
| case ATOM_ARG_PS: |
| idx = U8(*ptr); |
| (*ptr)++; |
| val = le32_to_cpu(ctx->ps[idx]); |
| if (print) |
| DEBUG("PS[0x%02X,0x%04X]", idx, val); |
| break; |
| case ATOM_ARG_WS: |
| idx = U8(*ptr); |
| (*ptr)++; |
| if (print) |
| DEBUG("WS[0x%02X]", idx); |
| switch (idx) { |
| case ATOM_WS_QUOTIENT: |
| val = gctx->divmul[0]; |
| break; |
| case ATOM_WS_REMAINDER: |
| val = gctx->divmul[1]; |
| break; |
| case ATOM_WS_DATAPTR: |
| val = gctx->data_block; |
| break; |
| case ATOM_WS_SHIFT: |
| val = gctx->shift; |
| break; |
| case ATOM_WS_OR_MASK: |
| val = 1 << gctx->shift; |
| break; |
| case ATOM_WS_AND_MASK: |
| val = ~(1 << gctx->shift); |
| break; |
| case ATOM_WS_FB_WINDOW: |
| val = gctx->fb_base; |
| break; |
| case ATOM_WS_ATTRIBUTES: |
| val = gctx->io_attr; |
| break; |
| default: |
| val = ctx->ws[idx]; |
| } |
| break; |
| case ATOM_ARG_ID: |
| idx = U16(*ptr); |
| (*ptr) += 2; |
| if (print) { |
| if (gctx->data_block) |
| DEBUG("ID[0x%04X+%04X]", idx, gctx->data_block); |
| else |
| DEBUG("ID[0x%04X]", idx); |
| } |
| val = U32(idx + gctx->data_block); |
| break; |
| case ATOM_ARG_FB: |
| idx = U8(*ptr); |
| (*ptr)++; |
| if (print) |
| DEBUG("FB[0x%02X]", idx); |
| printk(KERN_INFO "FB access is not implemented.\n"); |
| return 0; |
| case ATOM_ARG_IMM: |
| switch (align) { |
| case ATOM_SRC_DWORD: |
| val = U32(*ptr); |
| (*ptr) += 4; |
| if (print) |
| DEBUG("IMM 0x%08X\n", val); |
| return val; |
| case ATOM_SRC_WORD0: |
| case ATOM_SRC_WORD8: |
| case ATOM_SRC_WORD16: |
| val = U16(*ptr); |
| (*ptr) += 2; |
| if (print) |
| DEBUG("IMM 0x%04X\n", val); |
| return val; |
| case ATOM_SRC_BYTE0: |
| case ATOM_SRC_BYTE8: |
| case ATOM_SRC_BYTE16: |
| case ATOM_SRC_BYTE24: |
| val = U8(*ptr); |
| (*ptr)++; |
| if (print) |
| DEBUG("IMM 0x%02X\n", val); |
| return val; |
| } |
| return 0; |
| case ATOM_ARG_PLL: |
| idx = U8(*ptr); |
| (*ptr)++; |
| if (print) |
| DEBUG("PLL[0x%02X]", idx); |
| val = gctx->card->pll_read(gctx->card, idx); |
| break; |
| case ATOM_ARG_MC: |
| idx = U8(*ptr); |
| (*ptr)++; |
| if (print) |
| DEBUG("MC[0x%02X]", idx); |
| val = gctx->card->mc_read(gctx->card, idx); |
| break; |
| } |
| if (saved) |
| *saved = val; |
| val &= atom_arg_mask[align]; |
| val >>= atom_arg_shift[align]; |
| if (print) |
| switch (align) { |
| case ATOM_SRC_DWORD: |
| DEBUG(".[31:0] -> 0x%08X\n", val); |
| break; |
| case ATOM_SRC_WORD0: |
| DEBUG(".[15:0] -> 0x%04X\n", val); |
| break; |
| case ATOM_SRC_WORD8: |
| DEBUG(".[23:8] -> 0x%04X\n", val); |
| break; |
| case ATOM_SRC_WORD16: |
| DEBUG(".[31:16] -> 0x%04X\n", val); |
| break; |
| case ATOM_SRC_BYTE0: |
| DEBUG(".[7:0] -> 0x%02X\n", val); |
| break; |
| case ATOM_SRC_BYTE8: |
| DEBUG(".[15:8] -> 0x%02X\n", val); |
| break; |
| case ATOM_SRC_BYTE16: |
| DEBUG(".[23:16] -> 0x%02X\n", val); |
| break; |
| case ATOM_SRC_BYTE24: |
| DEBUG(".[31:24] -> 0x%02X\n", val); |
| break; |
| } |
| return val; |
| } |
| static void atom_skip_src_int(atom_exec_context *ctx, uint8_t attr, int *ptr) |
| { |
| uint32_t align = (attr >> 3) & 7, arg = attr & 7; |
| switch (arg) { |
| case ATOM_ARG_REG: |
| case ATOM_ARG_ID: |
| (*ptr) += 2; |
| break; |
| case ATOM_ARG_PLL: |
| case ATOM_ARG_MC: |
| case ATOM_ARG_PS: |
| case ATOM_ARG_WS: |
| case ATOM_ARG_FB: |
| (*ptr)++; |
| break; |
| case ATOM_ARG_IMM: |
| switch (align) { |
| case ATOM_SRC_DWORD: |
| (*ptr) += 4; |
| return; |
| case ATOM_SRC_WORD0: |
| case ATOM_SRC_WORD8: |
| case ATOM_SRC_WORD16: |
| (*ptr) += 2; |
| return; |
| case ATOM_SRC_BYTE0: |
| case ATOM_SRC_BYTE8: |
| case ATOM_SRC_BYTE16: |
| case ATOM_SRC_BYTE24: |
| (*ptr)++; |
| return; |
| } |
| return; |
| } |
| } |
| static uint32_t atom_get_src(atom_exec_context *ctx, uint8_t attr, int *ptr) |
| { |
| return atom_get_src_int(ctx, attr, ptr, NULL, 1); |
| } |
| static uint32_t atom_get_dst(atom_exec_context *ctx, int arg, uint8_t attr, |
| int *ptr, uint32_t *saved, int print) |
| { |
| return atom_get_src_int(ctx, |
| arg | atom_dst_to_src[(attr >> 3) & |
| 7][(attr >> 6) & 3] << 3, |
| ptr, saved, print); |
| } |
| static void atom_skip_dst(atom_exec_context *ctx, int arg, uint8_t attr, int *ptr) |
| { |
| atom_skip_src_int(ctx, |
| arg | atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & |
| 3] << 3, ptr); |
| } |
| static void atom_put_dst(atom_exec_context *ctx, int arg, uint8_t attr, |
| int *ptr, uint32_t val, uint32_t saved) |
| { |
| uint32_t align = |
| atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3], old_val = |
| val, idx; |
| struct atom_context *gctx = ctx->ctx; |
| old_val &= atom_arg_mask[align] >> atom_arg_shift[align]; |
| val <<= atom_arg_shift[align]; |
| val &= atom_arg_mask[align]; |
| saved &= ~atom_arg_mask[align]; |
| val |= saved; |
| switch (arg) { |
| case ATOM_ARG_REG: |
| idx = U16(*ptr); |
| (*ptr) += 2; |
| DEBUG("REG[0x%04X]", idx); |
| idx += gctx->reg_block; |
| switch (gctx->io_mode) { |
| case ATOM_IO_MM: |
| if (idx == 0) |
| gctx->card->reg_write(gctx->card, idx, |
| val << 2); |
| else |
| gctx->card->reg_write(gctx->card, idx, val); |
| break; |
| case ATOM_IO_PCI: |
| printk(KERN_INFO |
| "PCI registers are not implemented.\n"); |
| return; |
| case ATOM_IO_SYSIO: |
| printk(KERN_INFO |
| "SYSIO registers are not implemented.\n"); |
| return; |
| default: |
| if (!(gctx->io_mode & 0x80)) { |
| printk(KERN_INFO "Bad IO mode.\n"); |
| return; |
| } |
| if (!gctx->iio[gctx->io_mode & 0xFF]) { |
| printk(KERN_INFO |
| "Undefined indirect IO write method %d.\n", |
| gctx->io_mode & 0x7F); |
| return; |
| } |
| atom_iio_execute(gctx, gctx->iio[gctx->io_mode & 0xFF], |
| idx, val); |
| } |
| break; |
| case ATOM_ARG_PS: |
| idx = U8(*ptr); |
| (*ptr)++; |
| DEBUG("PS[0x%02X]", idx); |
| ctx->ps[idx] = cpu_to_le32(val); |
| break; |
| case ATOM_ARG_WS: |
| idx = U8(*ptr); |
| (*ptr)++; |
| DEBUG("WS[0x%02X]", idx); |
| switch (idx) { |
| case ATOM_WS_QUOTIENT: |
| gctx->divmul[0] = val; |
| break; |
| case ATOM_WS_REMAINDER: |
| gctx->divmul[1] = val; |
| break; |
| case ATOM_WS_DATAPTR: |
| gctx->data_block = val; |
| break; |
| case ATOM_WS_SHIFT: |
| gctx->shift = val; |
| break; |
| case ATOM_WS_OR_MASK: |
| case ATOM_WS_AND_MASK: |
| break; |
| case ATOM_WS_FB_WINDOW: |
| gctx->fb_base = val; |
| break; |
| case ATOM_WS_ATTRIBUTES: |
| gctx->io_attr = val; |
| break; |
| default: |
| ctx->ws[idx] = val; |
| } |
| break; |
| case ATOM_ARG_FB: |
| idx = U8(*ptr); |
| (*ptr)++; |
| DEBUG("FB[0x%02X]", idx); |
| printk(KERN_INFO "FB access is not implemented.\n"); |
| return; |
| case ATOM_ARG_PLL: |
| idx = U8(*ptr); |
| (*ptr)++; |
| DEBUG("PLL[0x%02X]", idx); |
| gctx->card->pll_write(gctx->card, idx, val); |
| break; |
| case ATOM_ARG_MC: |
| idx = U8(*ptr); |
| (*ptr)++; |
| DEBUG("MC[0x%02X]", idx); |
| gctx->card->mc_write(gctx->card, idx, val); |
| return; |
| } |
| switch (align) { |
| case ATOM_SRC_DWORD: |
| DEBUG(".[31:0] <- 0x%08X\n", old_val); |
| break; |
| case ATOM_SRC_WORD0: |
| DEBUG(".[15:0] <- 0x%04X\n", old_val); |
| break; |
| case ATOM_SRC_WORD8: |
| DEBUG(".[23:8] <- 0x%04X\n", old_val); |
| break; |
| case ATOM_SRC_WORD16: |
| DEBUG(".[31:16] <- 0x%04X\n", old_val); |
| break; |
| case ATOM_SRC_BYTE0: |
| DEBUG(".[7:0] <- 0x%02X\n", old_val); |
| break; |
| case ATOM_SRC_BYTE8: |
| DEBUG(".[15:8] <- 0x%02X\n", old_val); |
| break; |
| case ATOM_SRC_BYTE16: |
| DEBUG(".[23:16] <- 0x%02X\n", old_val); |
| break; |
| case ATOM_SRC_BYTE24: |
| DEBUG(".[31:24] <- 0x%02X\n", old_val); |
| break; |
| } |
| } |
| static void atom_op_add(atom_exec_context *ctx, int *ptr, int arg) |
| { |
| uint8_t attr = U8((*ptr)++); |
| uint32_t dst, src, saved; |
| int dptr = *ptr; |
| SDEBUG(" dst: "); |
| dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); |
| SDEBUG(" src: "); |
| src = atom_get_src(ctx, attr, ptr); |
| dst += src; |
| SDEBUG(" dst: "); |
| atom_put_dst(ctx, arg, attr, &dptr, dst, saved); |
| } |
| static void atom_op_and(atom_exec_context *ctx, int *ptr, int arg) |
| { |
| uint8_t attr = U8((*ptr)++); |
| uint32_t dst, src, saved; |
| int dptr = *ptr; |
| SDEBUG(" dst: "); |
| dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); |
| SDEBUG(" src: "); |
| src = atom_get_src(ctx, attr, ptr); |
| dst &= src; |
| SDEBUG(" dst: "); |
| atom_put_dst(ctx, arg, attr, &dptr, dst, saved); |
| } |
| static void atom_op_beep(atom_exec_context *ctx, int *ptr, int arg) |
| { |
| printk("ATOM BIOS beeped!\n"); |
| } |
| static void atom_op_calltable(atom_exec_context *ctx, int *ptr, int arg) |
| { |
| int idx = U8((*ptr)++); |
| if (idx < ATOM_TABLE_NAMES_CNT) |
| SDEBUG(" table: %d (%s)\n", idx, atom_table_names[idx]); |
| else |
| SDEBUG(" table: %d\n", idx); |
| if (U16(ctx->ctx->cmd_table + 4 + 2 * idx)) |
| atom_execute_table(ctx->ctx, idx, ctx->ps + ctx->ps_shift); |
| } |
| static void atom_op_clear(atom_exec_context *ctx, int *ptr, int arg) |
| { |
| uint8_t attr = U8((*ptr)++); |
| uint32_t saved; |
| int dptr = *ptr; |
| attr &= 0x38; |
| attr |= atom_def_dst[attr >> 3] << 6; |
| atom_get_dst(ctx, arg, attr, ptr, &saved, 0); |
| SDEBUG(" dst: "); |
| atom_put_dst(ctx, arg, attr, &dptr, 0, saved); |
| } |
| static void atom_op_compare(atom_exec_context *ctx, int *ptr, int arg) |
| { |
| uint8_t attr = U8((*ptr)++); |
| uint32_t dst, src; |
| SDEBUG(" src1: "); |
| dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1); |
| SDEBUG(" src2: "); |
| src = atom_get_src(ctx, attr, ptr); |
| ctx->ctx->cs_equal = (dst == src); |
| ctx->ctx->cs_above = (dst > src); |
| SDEBUG(" result: %s %s\n", ctx->ctx->cs_equal ? "EQ" : "NE", |
| ctx->ctx->cs_above ? "GT" : "LE"); |
| } |
| static void atom_op_delay(atom_exec_context *ctx, int *ptr, int arg) |
| { |
| uint8_t count = U8((*ptr)++); |
| SDEBUG(" count: %d\n", count); |
| // if (arg == ATOM_UNIT_MICROSEC) |
| // schedule_timeout_uninterruptible(usecs_to_jiffies(count)); |
| // else |
| // schedule_timeout_uninterruptible(msecs_to_jiffies(count)); |
| } |
| static void atom_op_div(atom_exec_context *ctx, int *ptr, int arg) |
| { |
| uint8_t attr = U8((*ptr)++); |
| uint32_t dst, src; |
| SDEBUG(" src1: "); |
| dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1); |
| SDEBUG(" src2: "); |
| src = atom_get_src(ctx, attr, ptr); |
| if (src != 0) { |
| ctx->ctx->divmul[0] = dst / src; |
| ctx->ctx->divmul[1] = dst % src; |
| } else { |
| ctx->ctx->divmul[0] = 0; |
| ctx->ctx->divmul[1] = 0; |
| } |
| } |
| static void atom_op_eot(atom_exec_context *ctx, int *ptr, int arg) |
| { |
| /* functionally, a nop */ |
| } |
| static void atom_op_jump(atom_exec_context *ctx, int *ptr, int arg) |
| { |
| int execute = 0, target = U16(*ptr); |
| (*ptr) += 2; |
| switch (arg) { |
| case ATOM_COND_ABOVE: |
| execute = ctx->ctx->cs_above; |
| break; |
| case ATOM_COND_ABOVEOREQUAL: |
| execute = ctx->ctx->cs_above || ctx->ctx->cs_equal; |
| break; |
| case ATOM_COND_ALWAYS: |
| execute = 1; |
| break; |
| case ATOM_COND_BELOW: |
| execute = !(ctx->ctx->cs_above || ctx->ctx->cs_equal); |
| break; |
| case ATOM_COND_BELOWOREQUAL: |
| execute = !ctx->ctx->cs_above; |
| break; |
| case ATOM_COND_EQUAL: |
| execute = ctx->ctx->cs_equal; |
| break; |
| case ATOM_COND_NOTEQUAL: |
| execute = !ctx->ctx->cs_equal; |
| break; |
| } |
| if (arg != ATOM_COND_ALWAYS) |
| SDEBUG(" taken: %s\n", execute ? "yes" : "no"); |
| SDEBUG(" target: 0x%04X\n", target); |
| if (execute) |
| *ptr = ctx->start + target; |
| } |
| static void atom_op_mask(atom_exec_context *ctx, int *ptr, int arg) |
| { |
| uint8_t attr = U8((*ptr)++); |
| uint32_t dst, src1, src2, saved; |
| int dptr = *ptr; |
| SDEBUG(" dst: "); |
| dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); |
| SDEBUG(" src1: "); |
| src1 = atom_get_src(ctx, attr, ptr); |
| SDEBUG(" src2: "); |
| src2 = atom_get_src(ctx, attr, ptr); |
| dst &= src1; |
| dst |= src2; |
| SDEBUG(" dst: "); |
| atom_put_dst(ctx, arg, attr, &dptr, dst, saved); |
| } |
| static void atom_op_move(atom_exec_context *ctx, int *ptr, int arg) |
| { |
| uint8_t attr = U8((*ptr)++); |
| uint32_t src, saved; |
| int dptr = *ptr; |
| if (((attr >> 3) & 7) != ATOM_SRC_DWORD) |
| atom_get_dst(ctx, arg, attr, ptr, &saved, 0); |
| else { |
| atom_skip_dst(ctx, arg, attr, ptr); |
| saved = 0xCDCDCDCD; |
| } |
| SDEBUG(" src: "); |
| src = atom_get_src(ctx, attr, ptr); |
| SDEBUG(" dst: "); |
| atom_put_dst(ctx, arg, attr, &dptr, src, saved); |
| } |
| static void atom_op_mul(atom_exec_context *ctx, int *ptr, int arg) |
| { |
| uint8_t attr = U8((*ptr)++); |
| uint32_t dst, src; |
| SDEBUG(" src1: "); |
| dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1); |
| SDEBUG(" src2: "); |
| src = atom_get_src(ctx, attr, ptr); |
| ctx->ctx->divmul[0] = dst * src; |
| } |
| static void atom_op_nop(atom_exec_context *ctx, int *ptr, int arg) |
| { |
| /* nothing */ |
| } |
| static void atom_op_or(atom_exec_context *ctx, int *ptr, int arg) |
| { |
| uint8_t attr = U8((*ptr)++); |
| uint32_t dst, src, saved; |
| int dptr = *ptr; |
| SDEBUG(" dst: "); |
| dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); |
| SDEBUG(" src: "); |
| src = atom_get_src(ctx, attr, ptr); |
| dst |= src; |
| SDEBUG(" dst: "); |
| atom_put_dst(ctx, arg, attr, &dptr, dst, saved); |
| } |
| static void atom_op_postcard(atom_exec_context *ctx, int *ptr, int arg) |
| { |
| uint8_t val = U8((*ptr)++); |
| SDEBUG("POST card output: 0x%02X\n", val); |
| } |
| static void atom_op_repeat(atom_exec_context *ctx, int *ptr, int arg) |
| { |
| printk(KERN_INFO "unimplemented!\n"); |
| } |
| static void atom_op_restorereg(atom_exec_context *ctx, int *ptr, int arg) |
| { |
| printk(KERN_INFO "unimplemented!\n"); |
| } |
| static void atom_op_savereg(atom_exec_context *ctx, int *ptr, int arg) |
| { |
| printk(KERN_INFO "unimplemented!\n"); |
| } |
| static void atom_op_setdatablock(atom_exec_context *ctx, int *ptr, int arg) |
| { |
| int idx = U8(*ptr); |
| (*ptr)++; |
| SDEBUG(" block: %d\n", idx); |
| if (!idx) |
| ctx->ctx->data_block = 0; |
| else if (idx == 255) |
| ctx->ctx->data_block = ctx->start; |
| else |
| ctx->ctx->data_block = U16(ctx->ctx->data_table + 4 + 2 * idx); |
| SDEBUG(" base: 0x%04X\n", ctx->ctx->data_block); |
| } |
| static void atom_op_setfbbase(atom_exec_context *ctx, int *ptr, int arg) |
| { |
| uint8_t attr = U8((*ptr)++); |
| SDEBUG(" fb_base: "); |
| ctx->ctx->fb_base = atom_get_src(ctx, attr, ptr); |
| } |
| static void atom_op_setport(atom_exec_context *ctx, int *ptr, int arg) |
| { |
| int port; |
| switch (arg) { |
| case ATOM_PORT_ATI: |
| port = U16(*ptr); |
| if (port < ATOM_IO_NAMES_CNT) |
| SDEBUG(" port: %d (%s)\n", port, atom_io_names[port]); |
| else |
| SDEBUG(" port: %d\n", port); |
| if (!port) |
| ctx->ctx->io_mode = ATOM_IO_MM; |
| else |
| ctx->ctx->io_mode = ATOM_IO_IIO | port; |
| (*ptr) += 2; |
| break; |
| case ATOM_PORT_PCI: |
| ctx->ctx->io_mode = ATOM_IO_PCI; |
| (*ptr)++; |
| break; |
| case ATOM_PORT_SYSIO: |
| ctx->ctx->io_mode = ATOM_IO_SYSIO; |
| (*ptr)++; |
| break; |
| } |
| } |
| static void atom_op_setregblock(atom_exec_context *ctx, int *ptr, int arg) |
| { |
| ctx->ctx->reg_block = U16(*ptr); |
| (*ptr) += 2; |
| SDEBUG(" base: 0x%04X\n", ctx->ctx->reg_block); |
| } |
| static void atom_op_shl(atom_exec_context *ctx, int *ptr, int arg) |
| { |
| uint8_t attr = U8((*ptr)++), shift; |
| uint32_t saved, dst; |
| int dptr = *ptr; |
| attr &= 0x38; |
| attr |= atom_def_dst[attr >> 3] << 6; |
| SDEBUG(" dst: "); |
| dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); |
| shift = U8((*ptr)++); |
| SDEBUG(" shift: %d\n", shift); |
| dst <<= shift; |
| SDEBUG(" dst: "); |
| atom_put_dst(ctx, arg, attr, &dptr, dst, saved); |
| } |
| static void atom_op_shr(atom_exec_context *ctx, int *ptr, int arg) |
| { |
| uint8_t attr = U8((*ptr)++), shift; |
| uint32_t saved, dst; |
| int dptr = *ptr; |
| attr &= 0x38; |
| attr |= atom_def_dst[attr >> 3] << 6; |
| SDEBUG(" dst: "); |
| dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); |
| shift = U8((*ptr)++); |
| SDEBUG(" shift: %d\n", shift); |
| dst >>= shift; |
| SDEBUG(" dst: "); |
| atom_put_dst(ctx, arg, attr, &dptr, dst, saved); |
| } |
| static void atom_op_sub(atom_exec_context *ctx, int *ptr, int arg) |
| { |
| uint8_t attr = U8((*ptr)++); |
| uint32_t dst, src, saved; |
| int dptr = *ptr; |
| SDEBUG(" dst: "); |
| dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); |
| SDEBUG(" src: "); |
| src = atom_get_src(ctx, attr, ptr); |
| dst -= src; |
| SDEBUG(" dst: "); |
| atom_put_dst(ctx, arg, attr, &dptr, dst, saved); |
| } |
| static void atom_op_switch(atom_exec_context *ctx, int *ptr, int arg) |
| { |
| uint8_t attr = U8((*ptr)++); |
| uint32_t src, val, target; |
| SDEBUG(" switch: "); |
| src = atom_get_src(ctx, attr, ptr); |
| while (U16(*ptr) != ATOM_CASE_END) |
| if (U8(*ptr) == ATOM_CASE_MAGIC) { |
| (*ptr)++; |
| SDEBUG(" case: "); |
| val = |
| atom_get_src(ctx, (attr & 0x38) | ATOM_ARG_IMM, |
| ptr); |
| target = U16(*ptr); |
| if (val == src) { |
| SDEBUG(" target: %04X\n", target); |
| *ptr = ctx->start + target; |
| return; |
| } |
| (*ptr) += 2; |
| } else { |
| printk(KERN_INFO "Bad case.\n"); |
| return; |
| } |
| (*ptr) += 2; |
| } |
| static void atom_op_test(atom_exec_context *ctx, int *ptr, int arg) |
| { |
| uint8_t attr = U8((*ptr)++); |
| uint32_t dst, src; |
| SDEBUG(" src1: "); |
| dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1); |
| SDEBUG(" src2: "); |
| src = atom_get_src(ctx, attr, ptr); |
| ctx->ctx->cs_equal = ((dst & src) == 0); |
| SDEBUG(" result: %s\n", ctx->ctx->cs_equal ? "EQ" : "NE"); |
| } |
| static void atom_op_xor(atom_exec_context *ctx, int *ptr, int arg) |
| { |
| uint8_t attr = U8((*ptr)++); |
| uint32_t dst, src, saved; |
| int dptr = *ptr; |
| SDEBUG(" dst: "); |
| dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); |
| SDEBUG(" src: "); |
| src = atom_get_src(ctx, attr, ptr); |
| dst ^= src; |
| SDEBUG(" dst: "); |
| atom_put_dst(ctx, arg, attr, &dptr, dst, saved); |
| } |
| static void atom_op_debug(atom_exec_context *ctx, int *ptr, int arg) |
| { |
| printk(KERN_INFO "unimplemented!\n"); |
| } |
| static struct { |
| void (*func) (atom_exec_context *, int *, int); |
| int arg; |
| } opcode_table[ATOM_OP_CNT] = { |
| { |
| NULL, 0}, { |
| atom_op_move, ATOM_ARG_REG}, { |
| atom_op_move, ATOM_ARG_PS}, { |
| atom_op_move, ATOM_ARG_WS}, { |
| atom_op_move, ATOM_ARG_FB}, { |
| atom_op_move, ATOM_ARG_PLL}, { |
| atom_op_move, ATOM_ARG_MC}, { |
| atom_op_and, ATOM_ARG_REG}, { |
| atom_op_and, ATOM_ARG_PS}, { |
| atom_op_and, ATOM_ARG_WS}, { |
| atom_op_and, ATOM_ARG_FB}, { |
| atom_op_and, ATOM_ARG_PLL}, { |
| atom_op_and, ATOM_ARG_MC}, { |
| atom_op_or, ATOM_ARG_REG}, { |
| atom_op_or, ATOM_ARG_PS}, { |
| atom_op_or, ATOM_ARG_WS}, { |
| atom_op_or, ATOM_ARG_FB}, { |
| atom_op_or, ATOM_ARG_PLL}, { |
| atom_op_or, ATOM_ARG_MC}, { |
| atom_op_shl, ATOM_ARG_REG}, { |
| atom_op_shl, ATOM_ARG_PS}, { |
| atom_op_shl, ATOM_ARG_WS}, { |
| atom_op_shl, ATOM_ARG_FB}, { |
| atom_op_shl, ATOM_ARG_PLL}, { |
| atom_op_shl, ATOM_ARG_MC}, { |
| atom_op_shr, ATOM_ARG_REG}, { |
| atom_op_shr, ATOM_ARG_PS}, { |
| atom_op_shr, ATOM_ARG_WS}, { |
| atom_op_shr, ATOM_ARG_FB}, { |
| atom_op_shr, ATOM_ARG_PLL}, { |
| atom_op_shr, ATOM_ARG_MC}, { |
| atom_op_mul, ATOM_ARG_REG}, { |
| atom_op_mul, ATOM_ARG_PS}, { |
| atom_op_mul, ATOM_ARG_WS}, { |
| atom_op_mul, ATOM_ARG_FB}, { |
| atom_op_mul, ATOM_ARG_PLL}, { |
| atom_op_mul, ATOM_ARG_MC}, { |
| atom_op_div, ATOM_ARG_REG}, { |
| atom_op_div, ATOM_ARG_PS}, { |
| atom_op_div, ATOM_ARG_WS}, { |
| atom_op_div, ATOM_ARG_FB}, { |
| atom_op_div, ATOM_ARG_PLL}, { |
| atom_op_div, ATOM_ARG_MC}, { |
| atom_op_add, ATOM_ARG_REG}, { |
| atom_op_add, ATOM_ARG_PS}, { |
| atom_op_add, ATOM_ARG_WS}, { |
| atom_op_add, ATOM_ARG_FB}, { |
| atom_op_add, ATOM_ARG_PLL}, { |
| atom_op_add, ATOM_ARG_MC}, { |
| atom_op_sub, ATOM_ARG_REG}, { |
| atom_op_sub, ATOM_ARG_PS}, { |
| atom_op_sub, ATOM_ARG_WS}, { |
| atom_op_sub, ATOM_ARG_FB}, { |
| atom_op_sub, ATOM_ARG_PLL}, { |
| atom_op_sub, ATOM_ARG_MC}, { |
| atom_op_setport, ATOM_PORT_ATI}, { |
| atom_op_setport, ATOM_PORT_PCI}, { |
| atom_op_setport, ATOM_PORT_SYSIO}, { |
| atom_op_setregblock, 0}, { |
| atom_op_setfbbase, 0}, { |
| atom_op_compare, ATOM_ARG_REG}, { |
| atom_op_compare, ATOM_ARG_PS}, { |
| atom_op_compare, ATOM_ARG_WS}, { |
| atom_op_compare, ATOM_ARG_FB}, { |
| atom_op_compare, ATOM_ARG_PLL}, { |
| atom_op_compare, ATOM_ARG_MC}, { |
| atom_op_switch, 0}, { |
| atom_op_jump, ATOM_COND_ALWAYS}, { |
| atom_op_jump, ATOM_COND_EQUAL}, { |
| atom_op_jump, ATOM_COND_BELOW}, { |
| atom_op_jump, ATOM_COND_ABOVE}, { |
| atom_op_jump, ATOM_COND_BELOWOREQUAL}, { |
| atom_op_jump, ATOM_COND_ABOVEOREQUAL}, { |
| atom_op_jump, ATOM_COND_NOTEQUAL}, { |
| atom_op_test, ATOM_ARG_REG}, { |
| atom_op_test, ATOM_ARG_PS}, { |
| atom_op_test, ATOM_ARG_WS}, { |
| atom_op_test, ATOM_ARG_FB}, { |
| atom_op_test, ATOM_ARG_PLL}, { |
| atom_op_test, ATOM_ARG_MC}, { |
| atom_op_delay, ATOM_UNIT_MILLISEC}, { |
| atom_op_delay, ATOM_UNIT_MICROSEC}, { |
| atom_op_calltable, 0}, { |
| atom_op_repeat, 0}, { |
| atom_op_clear, ATOM_ARG_REG}, { |
| atom_op_clear, ATOM_ARG_PS}, { |
| atom_op_clear, ATOM_ARG_WS}, { |
| atom_op_clear, ATOM_ARG_FB}, { |
| atom_op_clear, ATOM_ARG_PLL}, { |
| atom_op_clear, ATOM_ARG_MC}, { |
| atom_op_nop, 0}, { |
| atom_op_eot, 0}, { |
| atom_op_mask, ATOM_ARG_REG}, { |
| atom_op_mask, ATOM_ARG_PS}, { |
| atom_op_mask, ATOM_ARG_WS}, { |
| atom_op_mask, ATOM_ARG_FB}, { |
| atom_op_mask, ATOM_ARG_PLL}, { |
| atom_op_mask, ATOM_ARG_MC}, { |
| atom_op_postcard, 0}, { |
| atom_op_beep, 0}, { |
| atom_op_savereg, 0}, { |
| atom_op_restorereg, 0}, { |
| atom_op_setdatablock, 0}, { |
| atom_op_xor, ATOM_ARG_REG}, { |
| atom_op_xor, ATOM_ARG_PS}, { |
| atom_op_xor, ATOM_ARG_WS}, { |
| atom_op_xor, ATOM_ARG_FB}, { |
| atom_op_xor, ATOM_ARG_PLL}, { |
| atom_op_xor, ATOM_ARG_MC}, { |
| atom_op_shl, ATOM_ARG_REG}, { |
| atom_op_shl, ATOM_ARG_PS}, { |
| atom_op_shl, ATOM_ARG_WS}, { |
| atom_op_shl, ATOM_ARG_FB}, { |
| atom_op_shl, ATOM_ARG_PLL}, { |
| atom_op_shl, ATOM_ARG_MC}, { |
| atom_op_shr, ATOM_ARG_REG}, { |
| atom_op_shr, ATOM_ARG_PS}, { |
| atom_op_shr, ATOM_ARG_WS}, { |
| atom_op_shr, ATOM_ARG_FB}, { |
| atom_op_shr, ATOM_ARG_PLL}, { |
| atom_op_shr, ATOM_ARG_MC}, { |
| atom_op_debug, 0},}; |
| void atom_execute_table(struct atom_context *ctx, int index, uint32_t * params) |
| { |
| int base = CU16(ctx->cmd_table + 4 + 2 * index); |
| int len, ws, ps, ptr; |
| unsigned char op; |
| atom_exec_context ectx; |
| if (!base) |
| return; |
| len = CU16(base + ATOM_CT_SIZE_PTR); |
| ws = CU8(base + ATOM_CT_WS_PTR); |
| ps = CU8(base + ATOM_CT_PS_PTR) & ATOM_CT_PS_MASK; |
| ptr = base + ATOM_CT_CODE_PTR; |
| SDEBUG(">> execute %04X (len %d, WS %d, PS %d)\n", base, len, ws, ps); |
| /* reset reg block */ |
| ctx->reg_block = 0; |
| ectx.ctx = ctx; |
| ectx.ps_shift = ps / 4; |
| ectx.start = base; |
| ectx.ps = params; |
| if (ws) |
| ectx.ws = kzalloc(4 * ws, GFP_KERNEL); |
| else |
| ectx.ws = NULL; |
| debug_depth++; |
| while (1) { |
| op = CU8(ptr++); |
| if (op < ATOM_OP_NAMES_CNT) |
| SDEBUG("%s @ 0x%04X\n", atom_op_names[op], ptr - 1); |
| else |
| SDEBUG("[%d] @ 0x%04X\n", op, ptr - 1); |
| if (op < ATOM_OP_CNT && op > 0) |
| opcode_table[op].func(&ectx, &ptr, |
| opcode_table[op].arg); |
| else |
| break; |
| if (op == ATOM_OP_EOT) |
| break; |
| } |
| debug_depth--; |
| SDEBUG("<<\n"); |
| if (ws) |
| kfree(ectx.ws); |
| } |
| static int atom_iio_len[] = { 1, 2, 3, 3, 3, 3, 4, 4, 4, 3 }; |
| static void atom_index_iio(struct atom_context *ctx, int base) |
| { |
| ctx->iio = kzalloc(2 * 256, GFP_KERNEL); |
| while (CU8(base) == ATOM_IIO_START) { |
| ctx->iio[CU8(base + 1)] = base + 2; |
| base += 2; |
| while (CU8(base) != ATOM_IIO_END) |
| base += atom_iio_len[CU8(base)]; |
| base += 3; |
| } |
| } |
| struct atom_context *atom_parse(struct card_info *card, void *bios) |
| { |
| int base; |
| struct atom_context *ctx = |
| kzalloc(sizeof(struct atom_context), GFP_KERNEL); |
| char *str; |
| char name[512]; |
| int i; |
| ctx->card = card; |
| ctx->bios = bios; |
| if (CU16(0) != ATOM_BIOS_MAGIC) { |
| printk(KERN_INFO "Invalid BIOS magic.\n"); |
| kfree(ctx); |
| return NULL; |
| } |
| if (strncmp |
| (CSTR(ATOM_ATI_MAGIC_PTR), ATOM_ATI_MAGIC, |
| strlen(ATOM_ATI_MAGIC))) { |
| printk(KERN_INFO "Invalid ATI magic.\n"); |
| kfree(ctx); |
| return NULL; |
| } |
| base = CU16(ATOM_ROM_TABLE_PTR); |
| if (strncmp |
| (CSTR(base + ATOM_ROM_MAGIC_PTR), ATOM_ROM_MAGIC, |
| strlen(ATOM_ROM_MAGIC))) { |
| printk(KERN_INFO "Invalid ATOM magic.\n"); |
| kfree(ctx); |
| return NULL; |
| } |
| ctx->cmd_table = CU16(base + ATOM_ROM_CMD_PTR); |
| ctx->data_table = CU16(base + ATOM_ROM_DATA_PTR); |
| atom_index_iio(ctx, CU16(ctx->data_table + ATOM_DATA_IIO_PTR) + 4); |
| str = CSTR(CU16(base + ATOM_ROM_MSG_PTR)); |
| while (*str && ((*str == '\n') || (*str == '\r'))) |
| str++; |
| /* name string isn't always 0 terminated */ |
| for (i = 0; i < 511; i++) { |
| name[i] = str[i]; |
| if (name[i] < '.' || name[i] > 'z') { |
| name[i] = 0; |
| break; |
| } |
| } |
| printk(KERN_INFO "ATOM BIOS: %s\n", name); |
| return ctx; |
| } |
| int atom_asic_init(struct atom_context *ctx) |
| { |
| dbgprintf("%s\n\r",__FUNCTION__); |
| int hwi = CU16(ctx->data_table + ATOM_DATA_FWI_PTR); |
| uint32_t ps[16]; |
| memset(ps, 0, 64); |
| ps[0] = cpu_to_le32(CU32(hwi + ATOM_FWI_DEFSCLK_PTR)); |
| ps[1] = cpu_to_le32(CU32(hwi + ATOM_FWI_DEFMCLK_PTR)); |
| if (!ps[0] || !ps[1]) |
| return 1; |
| if (!CU16(ctx->cmd_table + 4 + 2 * ATOM_CMD_INIT)) |
| return 1; |
| atom_execute_table(ctx, ATOM_CMD_INIT, ps); |
| return 0; |
| } |
| void atom_destroy(struct atom_context *ctx) |
| { |
| if (ctx->iio) |
| kfree(ctx->iio); |
| kfree(ctx); |
| } |
| void atom_parse_data_header(struct atom_context *ctx, int index, |
| uint16_t * size, uint8_t * frev, uint8_t * crev, |
| uint16_t * data_start) |
| { |
| int offset = index * 2 + 4; |
| int idx = CU16(ctx->data_table + offset); |
| if (size) |
| *size = CU16(idx); |
| if (frev) |
| *frev = CU8(idx + 2); |
| if (crev) |
| *crev = CU8(idx + 3); |
| *data_start = idx; |
| return; |
| } |
| void atom_parse_cmd_header(struct atom_context *ctx, int index, uint8_t * frev, |
| uint8_t * crev) |
| { |
| int offset = index * 2 + 4; |
| int idx = CU16(ctx->cmd_table + offset); |
| if (frev) |
| *frev = CU8(idx + 2); |
| if (crev) |
| *crev = CU8(idx + 3); |
| return; |
| } |
| /drivers/video/drm/radeon/atom.h |
|---|
| 0,0 → 1,149 |
| /* |
| * Copyright 2008 Advanced Micro Devices, Inc. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice shall be included in |
| * all copies or substantial portions of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| * OTHER DEALINGS IN THE SOFTWARE. |
| * |
| * Author: Stanislaw Skowronek |
| */ |
| #ifndef ATOM_H |
| #define ATOM_H |
| #include <types.h> |
| //#include "drmP.h" |
| #define ATOM_BIOS_MAGIC 0xAA55 |
| #define ATOM_ATI_MAGIC_PTR 0x30 |
| #define ATOM_ATI_MAGIC " 761295520" |
| #define ATOM_ROM_TABLE_PTR 0x48 |
| #define ATOM_ROM_MAGIC "ATOM" |
| #define ATOM_ROM_MAGIC_PTR 4 |
| #define ATOM_ROM_MSG_PTR 0x10 |
| #define ATOM_ROM_CMD_PTR 0x1E |
| #define ATOM_ROM_DATA_PTR 0x20 |
| #define ATOM_CMD_INIT 0 |
| #define ATOM_CMD_SETSCLK 0x0A |
| #define ATOM_CMD_SETMCLK 0x0B |
| #define ATOM_CMD_SETPCLK 0x0C |
| #define ATOM_DATA_FWI_PTR 0xC |
| #define ATOM_DATA_IIO_PTR 0x32 |
| #define ATOM_FWI_DEFSCLK_PTR 8 |
| #define ATOM_FWI_DEFMCLK_PTR 0xC |
| #define ATOM_FWI_MAXSCLK_PTR 0x24 |
| #define ATOM_FWI_MAXMCLK_PTR 0x28 |
| #define ATOM_CT_SIZE_PTR 0 |
| #define ATOM_CT_WS_PTR 4 |
| #define ATOM_CT_PS_PTR 5 |
| #define ATOM_CT_PS_MASK 0x7F |
| #define ATOM_CT_CODE_PTR 6 |
| #define ATOM_OP_CNT 123 |
| #define ATOM_OP_EOT 91 |
| #define ATOM_CASE_MAGIC 0x63 |
| #define ATOM_CASE_END 0x5A5A |
| #define ATOM_ARG_REG 0 |
| #define ATOM_ARG_PS 1 |
| #define ATOM_ARG_WS 2 |
| #define ATOM_ARG_FB 3 |
| #define ATOM_ARG_ID 4 |
| #define ATOM_ARG_IMM 5 |
| #define ATOM_ARG_PLL 6 |
| #define ATOM_ARG_MC 7 |
| #define ATOM_SRC_DWORD 0 |
| #define ATOM_SRC_WORD0 1 |
| #define ATOM_SRC_WORD8 2 |
| #define ATOM_SRC_WORD16 3 |
| #define ATOM_SRC_BYTE0 4 |
| #define ATOM_SRC_BYTE8 5 |
| #define ATOM_SRC_BYTE16 6 |
| #define ATOM_SRC_BYTE24 7 |
| #define ATOM_WS_QUOTIENT 0x40 |
| #define ATOM_WS_REMAINDER 0x41 |
| #define ATOM_WS_DATAPTR 0x42 |
| #define ATOM_WS_SHIFT 0x43 |
| #define ATOM_WS_OR_MASK 0x44 |
| #define ATOM_WS_AND_MASK 0x45 |
| #define ATOM_WS_FB_WINDOW 0x46 |
| #define ATOM_WS_ATTRIBUTES 0x47 |
| #define ATOM_IIO_NOP 0 |
| #define ATOM_IIO_START 1 |
| #define ATOM_IIO_READ 2 |
| #define ATOM_IIO_WRITE 3 |
| #define ATOM_IIO_CLEAR 4 |
| #define ATOM_IIO_SET 5 |
| #define ATOM_IIO_MOVE_INDEX 6 |
| #define ATOM_IIO_MOVE_ATTR 7 |
| #define ATOM_IIO_MOVE_DATA 8 |
| #define ATOM_IIO_END 9 |
| #define ATOM_IO_MM 0 |
| #define ATOM_IO_PCI 1 |
| #define ATOM_IO_SYSIO 2 |
| #define ATOM_IO_IIO 0x80 |
| struct card_info { |
| struct drm_device *dev; |
| void (* reg_write)(struct card_info *, uint32_t, uint32_t); /* filled by driver */ |
| uint32_t (* reg_read)(struct card_info *, uint32_t); /* filled by driver */ |
| void (* mc_write)(struct card_info *, uint32_t, uint32_t); /* filled by driver */ |
| uint32_t (* mc_read)(struct card_info *, uint32_t); /* filled by driver */ |
| void (* pll_write)(struct card_info *, uint32_t, uint32_t); /* filled by driver */ |
| uint32_t (* pll_read)(struct card_info *, uint32_t); /* filled by driver */ |
| }; |
| struct atom_context { |
| struct card_info *card; |
| void *bios; |
| uint32_t cmd_table, data_table; |
| uint16_t *iio; |
| uint16_t data_block; |
| uint32_t fb_base; |
| uint32_t divmul[2]; |
| uint16_t io_attr; |
| uint16_t reg_block; |
| uint8_t shift; |
| int cs_equal, cs_above; |
| int io_mode; |
| }; |
| extern int atom_debug; |
| struct atom_context *atom_parse(struct card_info *, void *); |
| void atom_execute_table(struct atom_context *, int, uint32_t *); |
| int atom_asic_init(struct atom_context *); |
| void atom_destroy(struct atom_context *); |
| void atom_parse_data_header(struct atom_context *ctx, int index, uint16_t *size, uint8_t *frev, uint8_t *crev, uint16_t *data_start); |
| void atom_parse_cmd_header(struct atom_context *ctx, int index, uint8_t *frev, uint8_t *crev); |
| #include "atom-types.h" |
| #include "atombios.h" |
| #include "ObjectID.h" |
| #endif |
| /drivers/video/drm/radeon/atombios.h |
|---|
| 0,0 → 1,4785 |
| /* |
| * Copyright 2006-2007 Advanced Micro Devices, Inc. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice shall be included in |
| * all copies or substantial portions of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| * OTHER DEALINGS IN THE SOFTWARE. |
| */ |
| /****************************************************************************/ |
| /*Portion I: Definitions shared between VBIOS and Driver */ |
| /****************************************************************************/ |
| #ifndef _ATOMBIOS_H |
| #define _ATOMBIOS_H |
| #define ATOM_VERSION_MAJOR 0x00020000 |
| #define ATOM_VERSION_MINOR 0x00000002 |
| #define ATOM_HEADER_VERSION (ATOM_VERSION_MAJOR | ATOM_VERSION_MINOR) |
| /* Endianness should be specified before inclusion, |
| * default to little endian |
| */ |
| #ifndef ATOM_BIG_ENDIAN |
| #error Endian not specified |
| #endif |
| #ifdef _H2INC |
| #ifndef ULONG |
| typedef unsigned long ULONG; |
| #endif |
| #ifndef UCHAR |
| typedef unsigned char UCHAR; |
| #endif |
| #ifndef USHORT |
| typedef unsigned short USHORT; |
| #endif |
| #endif |
| #define ATOM_DAC_A 0 |
| #define ATOM_DAC_B 1 |
| #define ATOM_EXT_DAC 2 |
| #define ATOM_CRTC1 0 |
| #define ATOM_CRTC2 1 |
| #define ATOM_DIGA 0 |
| #define ATOM_DIGB 1 |
| #define ATOM_PPLL1 0 |
| #define ATOM_PPLL2 1 |
| #define ATOM_SCALER1 0 |
| #define ATOM_SCALER2 1 |
| #define ATOM_SCALER_DISABLE 0 |
| #define ATOM_SCALER_CENTER 1 |
| #define ATOM_SCALER_EXPANSION 2 |
| #define ATOM_SCALER_MULTI_EX 3 |
| #define ATOM_DISABLE 0 |
| #define ATOM_ENABLE 1 |
| #define ATOM_LCD_BLOFF (ATOM_DISABLE+2) |
| #define ATOM_LCD_BLON (ATOM_ENABLE+2) |
| #define ATOM_LCD_BL_BRIGHTNESS_CONTROL (ATOM_ENABLE+3) |
| #define ATOM_LCD_SELFTEST_START (ATOM_DISABLE+5) |
| #define ATOM_LCD_SELFTEST_STOP (ATOM_ENABLE+5) |
| #define ATOM_ENCODER_INIT (ATOM_DISABLE+7) |
| #define ATOM_BLANKING 1 |
| #define ATOM_BLANKING_OFF 0 |
| #define ATOM_CURSOR1 0 |
| #define ATOM_CURSOR2 1 |
| #define ATOM_ICON1 0 |
| #define ATOM_ICON2 1 |
| #define ATOM_CRT1 0 |
| #define ATOM_CRT2 1 |
| #define ATOM_TV_NTSC 1 |
| #define ATOM_TV_NTSCJ 2 |
| #define ATOM_TV_PAL 3 |
| #define ATOM_TV_PALM 4 |
| #define ATOM_TV_PALCN 5 |
| #define ATOM_TV_PALN 6 |
| #define ATOM_TV_PAL60 7 |
| #define ATOM_TV_SECAM 8 |
| #define ATOM_TV_CV 16 |
| #define ATOM_DAC1_PS2 1 |
| #define ATOM_DAC1_CV 2 |
| #define ATOM_DAC1_NTSC 3 |
| #define ATOM_DAC1_PAL 4 |
| #define ATOM_DAC2_PS2 ATOM_DAC1_PS2 |
| #define ATOM_DAC2_CV ATOM_DAC1_CV |
| #define ATOM_DAC2_NTSC ATOM_DAC1_NTSC |
| #define ATOM_DAC2_PAL ATOM_DAC1_PAL |
| #define ATOM_PM_ON 0 |
| #define ATOM_PM_STANDBY 1 |
| #define ATOM_PM_SUSPEND 2 |
| #define ATOM_PM_OFF 3 |
| /* Bit0:{=0:single, =1:dual}, |
| Bit1 {=0:666RGB, =1:888RGB}, |
| Bit2:3:{Grey level} |
| Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}*/ |
| #define ATOM_PANEL_MISC_DUAL 0x00000001 |
| #define ATOM_PANEL_MISC_888RGB 0x00000002 |
| #define ATOM_PANEL_MISC_GREY_LEVEL 0x0000000C |
| #define ATOM_PANEL_MISC_FPDI 0x00000010 |
| #define ATOM_PANEL_MISC_GREY_LEVEL_SHIFT 2 |
| #define ATOM_PANEL_MISC_SPATIAL 0x00000020 |
| #define ATOM_PANEL_MISC_TEMPORAL 0x00000040 |
| #define ATOM_PANEL_MISC_API_ENABLED 0x00000080 |
| #define MEMTYPE_DDR1 "DDR1" |
| #define MEMTYPE_DDR2 "DDR2" |
| #define MEMTYPE_DDR3 "DDR3" |
| #define MEMTYPE_DDR4 "DDR4" |
| #define ASIC_BUS_TYPE_PCI "PCI" |
| #define ASIC_BUS_TYPE_AGP "AGP" |
| #define ASIC_BUS_TYPE_PCIE "PCI_EXPRESS" |
| /* Maximum size of that FireGL flag string */ |
| #define ATOM_FIREGL_FLAG_STRING "FGL" /* Flag used to enable FireGL Support */ |
| #define ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING 3 /* sizeof( ATOM_FIREGL_FLAG_STRING ) */ |
| #define ATOM_FAKE_DESKTOP_STRING "DSK" /* Flag used to enable mobile ASIC on Desktop */ |
| #define ATOM_MAX_SIZE_OF_FAKE_DESKTOP_STRING ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING |
| #define ATOM_M54T_FLAG_STRING "M54T" /* Flag used to enable M54T Support */ |
| #define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING 4 /* sizeof( ATOM_M54T_FLAG_STRING ) */ |
| #define HW_ASSISTED_I2C_STATUS_FAILURE 2 |
| #define HW_ASSISTED_I2C_STATUS_SUCCESS 1 |
| #pragma pack(1) /* BIOS data must use byte aligment */ |
| /* Define offset to location of ROM header. */ |
| #define OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER 0x00000048L |
| #define OFFSET_TO_ATOM_ROM_IMAGE_SIZE 0x00000002L |
| #define OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE 0x94 |
| #define MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE 20 /* including the terminator 0x0! */ |
| #define OFFSET_TO_GET_ATOMBIOS_STRINGS_NUMBER 0x002f |
| #define OFFSET_TO_GET_ATOMBIOS_STRINGS_START 0x006e |
| /* Common header for all ROM Data tables. |
| Every table pointed _ATOM_MASTER_DATA_TABLE has this common header. |
| And the pointer actually points to this header. */ |
| typedef struct _ATOM_COMMON_TABLE_HEADER { |
| USHORT usStructureSize; |
| UCHAR ucTableFormatRevision; /*Change it when the Parser is not backward compatible */ |
| UCHAR ucTableContentRevision; /*Change it only when the table needs to change but the firmware */ |
| /*Image can't be updated, while Driver needs to carry the new table! */ |
| } ATOM_COMMON_TABLE_HEADER; |
| typedef struct _ATOM_ROM_HEADER { |
| ATOM_COMMON_TABLE_HEADER sHeader; |
| UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios, |
| atombios should init it as "ATOM", don't change the position */ |
| USHORT usBiosRuntimeSegmentAddress; |
| USHORT usProtectedModeInfoOffset; |
| USHORT usConfigFilenameOffset; |
| USHORT usCRC_BlockOffset; |
| USHORT usBIOS_BootupMessageOffset; |
| USHORT usInt10Offset; |
| USHORT usPciBusDevInitCode; |
| USHORT usIoBaseAddress; |
| USHORT usSubsystemVendorID; |
| USHORT usSubsystemID; |
| USHORT usPCI_InfoOffset; |
| USHORT usMasterCommandTableOffset; /*Offset for SW to get all command table offsets, Don't change the position */ |
| USHORT usMasterDataTableOffset; /*Offset for SW to get all data table offsets, Don't change the position */ |
| UCHAR ucExtendedFunctionCode; |
| UCHAR ucReserved; |
| } ATOM_ROM_HEADER; |
| /*==============================Command Table Portion==================================== */ |
| #ifdef UEFI_BUILD |
| #define UTEMP USHORT |
| #define USHORT void* |
| #endif |
| typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES { |
| USHORT ASIC_Init; /* Function Table, used by various SW components,latest version 1.1 */ |
| USHORT GetDisplaySurfaceSize; /* Atomic Table, Used by Bios when enabling HW ICON */ |
| USHORT ASIC_RegistersInit; /* Atomic Table, indirectly used by various SW components,called from ASIC_Init */ |
| USHORT VRAM_BlockVenderDetection; /* Atomic Table, used only by Bios */ |
| USHORT DIGxEncoderControl; /* Only used by Bios */ |
| USHORT MemoryControllerInit; /* Atomic Table, indirectly used by various SW components,called from ASIC_Init */ |
| USHORT EnableCRTCMemReq; /* Function Table,directly used by various SW components,latest version 2.1 */ |
| USHORT MemoryParamAdjust; /* Atomic Table, indirectly used by various SW components,called from SetMemoryClock if needed */ |
| USHORT DVOEncoderControl; /* Function Table,directly used by various SW components,latest version 1.2 */ |
| USHORT GPIOPinControl; /* Atomic Table, only used by Bios */ |
| USHORT SetEngineClock; /*Function Table,directly used by various SW components,latest version 1.1 */ |
| USHORT SetMemoryClock; /* Function Table,directly used by various SW components,latest version 1.1 */ |
| USHORT SetPixelClock; /*Function Table,directly used by various SW components,latest version 1.2 */ |
| USHORT DynamicClockGating; /* Atomic Table, indirectly used by various SW components,called from ASIC_Init */ |
| USHORT ResetMemoryDLL; /* Atomic Table, indirectly used by various SW components,called from SetMemoryClock */ |
| USHORT ResetMemoryDevice; /* Atomic Table, indirectly used by various SW components,called from SetMemoryClock */ |
| USHORT MemoryPLLInit; |
| USHORT AdjustDisplayPll; /* only used by Bios */ |
| USHORT AdjustMemoryController; /* Atomic Table, indirectly used by various SW components,called from SetMemoryClock */ |
| USHORT EnableASIC_StaticPwrMgt; /* Atomic Table, only used by Bios */ |
| USHORT ASIC_StaticPwrMgtStatusChange; /* Obsolete, only used by Bios */ |
| USHORT DAC_LoadDetection; /* Atomic Table, directly used by various SW components,latest version 1.2 */ |
| USHORT LVTMAEncoderControl; /* Atomic Table,directly used by various SW components,latest version 1.3 */ |
| USHORT LCD1OutputControl; /* Atomic Table, directly used by various SW components,latest version 1.1 */ |
| USHORT DAC1EncoderControl; /* Atomic Table, directly used by various SW components,latest version 1.1 */ |
| USHORT DAC2EncoderControl; /* Atomic Table, directly used by various SW components,latest version 1.1 */ |
| USHORT DVOOutputControl; /* Atomic Table, directly used by various SW components,latest version 1.1 */ |
| USHORT CV1OutputControl; /* Atomic Table, directly used by various SW components,latest version 1.1 */ |
| USHORT GetConditionalGoldenSetting; /* only used by Bios */ |
| USHORT TVEncoderControl; /* Function Table,directly used by various SW components,latest version 1.1 */ |
| USHORT TMDSAEncoderControl; /* Atomic Table, directly used by various SW components,latest version 1.3 */ |
| USHORT LVDSEncoderControl; /* Atomic Table, directly used by various SW components,latest version 1.3 */ |
| USHORT TV1OutputControl; /* Atomic Table, directly used by various SW components,latest version 1.1 */ |
| USHORT EnableScaler; /* Atomic Table, used only by Bios */ |
| USHORT BlankCRTC; /* Atomic Table, directly used by various SW components,latest version 1.1 */ |
| USHORT EnableCRTC; /* Atomic Table, directly used by various SW components,latest version 1.1 */ |
| USHORT GetPixelClock; /* Atomic Table, directly used by various SW components,latest version 1.1 */ |
| USHORT EnableVGA_Render; /* Function Table,directly used by various SW components,latest version 1.1 */ |
| USHORT EnableVGA_Access; /* Obsolete , only used by Bios */ |
| USHORT SetCRTC_Timing; /* Atomic Table, directly used by various SW components,latest version 1.1 */ |
| USHORT SetCRTC_OverScan; /* Atomic Table, used by various SW components,latest version 1.1 */ |
| USHORT SetCRTC_Replication; /* Atomic Table, used only by Bios */ |
| USHORT SelectCRTC_Source; /* Atomic Table, directly used by various SW components,latest version 1.1 */ |
| USHORT EnableGraphSurfaces; /* Atomic Table, used only by Bios */ |
| USHORT UpdateCRTC_DoubleBufferRegisters; |
| USHORT LUT_AutoFill; /* Atomic Table, only used by Bios */ |
| USHORT EnableHW_IconCursor; /* Atomic Table, only used by Bios */ |
| USHORT GetMemoryClock; /* Atomic Table, directly used by various SW components,latest version 1.1 */ |
| USHORT GetEngineClock; /* Atomic Table, directly used by various SW components,latest version 1.1 */ |
| USHORT SetCRTC_UsingDTDTiming; /* Atomic Table, directly used by various SW components,latest version 1.1 */ |
| USHORT ExternalEncoderControl; /* Atomic Table, directly used by various SW components,latest version 2.1 */ |
| USHORT LVTMAOutputControl; /* Atomic Table, directly used by various SW components,latest version 1.1 */ |
| USHORT VRAM_BlockDetectionByStrap; /* Atomic Table, used only by Bios */ |
| USHORT MemoryCleanUp; /* Atomic Table, only used by Bios */ |
| USHORT ProcessI2cChannelTransaction; /* Function Table,only used by Bios */ |
| USHORT WriteOneByteToHWAssistedI2C; /* Function Table,indirectly used by various SW components */ |
| USHORT ReadHWAssistedI2CStatus; /* Atomic Table, indirectly used by various SW components */ |
| USHORT SpeedFanControl; /* Function Table,indirectly used by various SW components,called from ASIC_Init */ |
| USHORT PowerConnectorDetection; /* Atomic Table, directly used by various SW components,latest version 1.1 */ |
| USHORT MC_Synchronization; /* Atomic Table, indirectly used by various SW components,called from SetMemoryClock */ |
| USHORT ComputeMemoryEnginePLL; /* Atomic Table, indirectly used by various SW components,called from SetMemory/EngineClock */ |
| USHORT MemoryRefreshConversion; /* Atomic Table, indirectly used by various SW components,called from SetMemory or SetEngineClock */ |
| USHORT VRAM_GetCurrentInfoBlock; /* Atomic Table, used only by Bios */ |
| USHORT DynamicMemorySettings; /* Atomic Table, indirectly used by various SW components,called from SetMemoryClock */ |
| USHORT MemoryTraining; /* Atomic Table, used only by Bios */ |
| USHORT EnableSpreadSpectrumOnPPLL; /* Atomic Table, directly used by various SW components,latest version 1.2 */ |
| USHORT TMDSAOutputControl; /* Atomic Table, directly used by various SW components,latest version 1.1 */ |
| USHORT SetVoltage; /* Function Table,directly and/or indirectly used by various SW components,latest version 1.1 */ |
| USHORT DAC1OutputControl; /* Atomic Table, directly used by various SW components,latest version 1.1 */ |
| USHORT DAC2OutputControl; /* Atomic Table, directly used by various SW components,latest version 1.1 */ |
| USHORT SetupHWAssistedI2CStatus; /* Function Table,only used by Bios, obsolete soon.Switch to use "ReadEDIDFromHWAssistedI2C" */ |
| USHORT ClockSource; /* Atomic Table, indirectly used by various SW components,called from ASIC_Init */ |
| USHORT MemoryDeviceInit; /* Atomic Table, indirectly used by various SW components,called from SetMemoryClock */ |
| USHORT EnableYUV; /* Atomic Table, indirectly used by various SW components,called from EnableVGARender */ |
| USHORT DIG1EncoderControl; /* Atomic Table,directly used by various SW components,latest version 1.1 */ |
| USHORT DIG2EncoderControl; /* Atomic Table,directly used by various SW components,latest version 1.1 */ |
| USHORT DIG1TransmitterControl; /* Atomic Table,directly used by various SW components,latest version 1.1 */ |
| USHORT DIG2TransmitterControl; /* Atomic Table,directly used by various SW components,latest version 1.1 */ |
| USHORT ProcessAuxChannelTransaction; /* Function Table,only used by Bios */ |
| USHORT DPEncoderService; /* Function Table,only used by Bios */ |
| } ATOM_MASTER_LIST_OF_COMMAND_TABLES; |
| /* For backward compatible */ |
| #define ReadEDIDFromHWAssistedI2C ProcessI2cChannelTransaction |
| #define UNIPHYTransmitterControl DIG1TransmitterControl |
| #define LVTMATransmitterControl DIG2TransmitterControl |
| #define SetCRTC_DPM_State GetConditionalGoldenSetting |
| #define SetUniphyInstance ASIC_StaticPwrMgtStatusChange |
| typedef struct _ATOM_MASTER_COMMAND_TABLE { |
| ATOM_COMMON_TABLE_HEADER sHeader; |
| ATOM_MASTER_LIST_OF_COMMAND_TABLES ListOfCommandTables; |
| } ATOM_MASTER_COMMAND_TABLE; |
| /****************************************************************************/ |
| /* Structures used in every command table */ |
| /****************************************************************************/ |
| typedef struct _ATOM_TABLE_ATTRIBUTE { |
| #if ATOM_BIG_ENDIAN |
| USHORT UpdatedByUtility:1; /* [15]=Table updated by utility flag */ |
| USHORT PS_SizeInBytes:7; /* [14:8]=Size of parameter space in Bytes (multiple of a dword), */ |
| USHORT WS_SizeInBytes:8; /* [7:0]=Size of workspace in Bytes (in multiple of a dword), */ |
| #else |
| USHORT WS_SizeInBytes:8; /* [7:0]=Size of workspace in Bytes (in multiple of a dword), */ |
| USHORT PS_SizeInBytes:7; /* [14:8]=Size of parameter space in Bytes (multiple of a dword), */ |
| USHORT UpdatedByUtility:1; /* [15]=Table updated by utility flag */ |
| #endif |
| } ATOM_TABLE_ATTRIBUTE; |
| typedef union _ATOM_TABLE_ATTRIBUTE_ACCESS { |
| ATOM_TABLE_ATTRIBUTE sbfAccess; |
| USHORT susAccess; |
| } ATOM_TABLE_ATTRIBUTE_ACCESS; |
| /****************************************************************************/ |
| /* Common header for all command tables. */ |
| /* Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header. */ |
| /* And the pointer actually points to this header. */ |
| /****************************************************************************/ |
| typedef struct _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER { |
| ATOM_COMMON_TABLE_HEADER CommonHeader; |
| ATOM_TABLE_ATTRIBUTE TableAttribute; |
| } ATOM_COMMON_ROM_COMMAND_TABLE_HEADER; |
| /****************************************************************************/ |
| /* Structures used by ComputeMemoryEnginePLLTable */ |
| /****************************************************************************/ |
| #define COMPUTE_MEMORY_PLL_PARAM 1 |
| #define COMPUTE_ENGINE_PLL_PARAM 2 |
| typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS { |
| ULONG ulClock; /* When returen, it's the re-calculated clock based on given Fb_div Post_Div and ref_div */ |
| UCHAR ucAction; /* 0:reserved //1:Memory //2:Engine */ |
| UCHAR ucReserved; /* may expand to return larger Fbdiv later */ |
| UCHAR ucFbDiv; /* return value */ |
| UCHAR ucPostDiv; /* return value */ |
| } COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS; |
| typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 { |
| ULONG ulClock; /* When return, [23:0] return real clock */ |
| UCHAR ucAction; /* 0:reserved;COMPUTE_MEMORY_PLL_PARAM:Memory;COMPUTE_ENGINE_PLL_PARAM:Engine. it return ref_div to be written to register */ |
| USHORT usFbDiv; /* return Feedback value to be written to register */ |
| UCHAR ucPostDiv; /* return post div to be written to register */ |
| } COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2; |
| #define COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS |
| #define SET_CLOCK_FREQ_MASK 0x00FFFFFF /* Clock change tables only take bit [23:0] as the requested clock value */ |
| #define USE_NON_BUS_CLOCK_MASK 0x01000000 /* Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) */ |
| #define USE_MEMORY_SELF_REFRESH_MASK 0x02000000 /* Only applicable to memory clock change, when set, using memory self refresh during clock transition */ |
| #define SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04000000 /* Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change */ |
| #define FIRST_TIME_CHANGE_CLOCK 0x08000000 /* Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup */ |
| #define SKIP_SW_PROGRAM_PLL 0x10000000 /* Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL */ |
| #define USE_SS_ENABLED_PIXEL_CLOCK USE_NON_BUS_CLOCK_MASK |
| #define b3USE_NON_BUS_CLOCK_MASK 0x01 /* Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) */ |
| #define b3USE_MEMORY_SELF_REFRESH 0x02 /* Only applicable to memory clock change, when set, using memory self refresh during clock transition */ |
| #define b3SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04 /* Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change */ |
| #define b3FIRST_TIME_CHANGE_CLOCK 0x08 /* Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup */ |
| #define b3SKIP_SW_PROGRAM_PLL 0x10 /* Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL */ |
| typedef struct _ATOM_COMPUTE_CLOCK_FREQ { |
| #if ATOM_BIG_ENDIAN |
| ULONG ulComputeClockFlag:8; /* =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM */ |
| ULONG ulClockFreq:24; /* in unit of 10kHz */ |
| #else |
| ULONG ulClockFreq:24; /* in unit of 10kHz */ |
| ULONG ulComputeClockFlag:8; /* =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM */ |
| #endif |
| } ATOM_COMPUTE_CLOCK_FREQ; |
| typedef struct _ATOM_S_MPLL_FB_DIVIDER { |
| USHORT usFbDivFrac; |
| USHORT usFbDiv; |
| } ATOM_S_MPLL_FB_DIVIDER; |
| typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 { |
| union { |
| ATOM_COMPUTE_CLOCK_FREQ ulClock; /* Input Parameter */ |
| ATOM_S_MPLL_FB_DIVIDER ulFbDiv; /* Output Parameter */ |
| }; |
| UCHAR ucRefDiv; /* Output Parameter */ |
| UCHAR ucPostDiv; /* Output Parameter */ |
| UCHAR ucCntlFlag; /* Output Parameter */ |
| UCHAR ucReserved; |
| } COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3; |
| /* ucCntlFlag */ |
| #define ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN 1 |
| #define ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE 2 |
| #define ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE 4 |
| typedef struct _DYNAMICE_MEMORY_SETTINGS_PARAMETER { |
| ATOM_COMPUTE_CLOCK_FREQ ulClock; |
| ULONG ulReserved[2]; |
| } DYNAMICE_MEMORY_SETTINGS_PARAMETER; |
| typedef struct _DYNAMICE_ENGINE_SETTINGS_PARAMETER { |
| ATOM_COMPUTE_CLOCK_FREQ ulClock; |
| ULONG ulMemoryClock; |
| ULONG ulReserved; |
| } DYNAMICE_ENGINE_SETTINGS_PARAMETER; |
| /****************************************************************************/ |
| /* Structures used by SetEngineClockTable */ |
| /****************************************************************************/ |
| typedef struct _SET_ENGINE_CLOCK_PARAMETERS { |
| ULONG ulTargetEngineClock; /* In 10Khz unit */ |
| } SET_ENGINE_CLOCK_PARAMETERS; |
| typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION { |
| ULONG ulTargetEngineClock; /* In 10Khz unit */ |
| COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; |
| } SET_ENGINE_CLOCK_PS_ALLOCATION; |
| /****************************************************************************/ |
| /* Structures used by SetMemoryClockTable */ |
| /****************************************************************************/ |
| typedef struct _SET_MEMORY_CLOCK_PARAMETERS { |
| ULONG ulTargetMemoryClock; /* In 10Khz unit */ |
| } SET_MEMORY_CLOCK_PARAMETERS; |
| typedef struct _SET_MEMORY_CLOCK_PS_ALLOCATION { |
| ULONG ulTargetMemoryClock; /* In 10Khz unit */ |
| COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; |
| } SET_MEMORY_CLOCK_PS_ALLOCATION; |
| /****************************************************************************/ |
| /* Structures used by ASIC_Init.ctb */ |
| /****************************************************************************/ |
| typedef struct _ASIC_INIT_PARAMETERS { |
| ULONG ulDefaultEngineClock; /* In 10Khz unit */ |
| ULONG ulDefaultMemoryClock; /* In 10Khz unit */ |
| } ASIC_INIT_PARAMETERS; |
| typedef struct _ASIC_INIT_PS_ALLOCATION { |
| ASIC_INIT_PARAMETERS sASICInitClocks; |
| SET_ENGINE_CLOCK_PS_ALLOCATION sReserved; /* Caller doesn't need to init this structure */ |
| } ASIC_INIT_PS_ALLOCATION; |
| /****************************************************************************/ |
| /* Structure used by DynamicClockGatingTable.ctb */ |
| /****************************************************************************/ |
| typedef struct _DYNAMIC_CLOCK_GATING_PARAMETERS { |
| UCHAR ucEnable; /* ATOM_ENABLE or ATOM_DISABLE */ |
| UCHAR ucPadding[3]; |
| } DYNAMIC_CLOCK_GATING_PARAMETERS; |
| #define DYNAMIC_CLOCK_GATING_PS_ALLOCATION DYNAMIC_CLOCK_GATING_PARAMETERS |
| /****************************************************************************/ |
| /* Structure used by EnableASIC_StaticPwrMgtTable.ctb */ |
| /****************************************************************************/ |
| typedef struct _ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS { |
| UCHAR ucEnable; /* ATOM_ENABLE or ATOM_DISABLE */ |
| UCHAR ucPadding[3]; |
| } ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS; |
| #define ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS |
| /****************************************************************************/ |
| /* Structures used by DAC_LoadDetectionTable.ctb */ |
| /****************************************************************************/ |
| typedef struct _DAC_LOAD_DETECTION_PARAMETERS { |
| USHORT usDeviceID; /* {ATOM_DEVICE_CRTx_SUPPORT,ATOM_DEVICE_TVx_SUPPORT,ATOM_DEVICE_CVx_SUPPORT} */ |
| UCHAR ucDacType; /* {ATOM_DAC_A,ATOM_DAC_B, ATOM_EXT_DAC} */ |
| UCHAR ucMisc; /* Valid only when table revision =1.3 and above */ |
| } DAC_LOAD_DETECTION_PARAMETERS; |
| /* DAC_LOAD_DETECTION_PARAMETERS.ucMisc */ |
| #define DAC_LOAD_MISC_YPrPb 0x01 |
| typedef struct _DAC_LOAD_DETECTION_PS_ALLOCATION { |
| DAC_LOAD_DETECTION_PARAMETERS sDacload; |
| ULONG Reserved[2]; /* Don't set this one, allocation for EXT DAC */ |
| } DAC_LOAD_DETECTION_PS_ALLOCATION; |
| /****************************************************************************/ |
| /* Structures used by DAC1EncoderControlTable.ctb and DAC2EncoderControlTable.ctb */ |
| /****************************************************************************/ |
| typedef struct _DAC_ENCODER_CONTROL_PARAMETERS { |
| USHORT usPixelClock; /* in 10KHz; for bios convenient */ |
| UCHAR ucDacStandard; /* See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as internal flag to indicate DAC2 (==1) or DAC1 (==0) */ |
| UCHAR ucAction; /* 0: turn off encoder */ |
| /* 1: setup and turn on encoder */ |
| /* 7: ATOM_ENCODER_INIT Initialize DAC */ |
| } DAC_ENCODER_CONTROL_PARAMETERS; |
| #define DAC_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PARAMETERS |
| /****************************************************************************/ |
| /* Structures used by DIG1EncoderControlTable */ |
| /* DIG2EncoderControlTable */ |
| /* ExternalEncoderControlTable */ |
| /****************************************************************************/ |
| typedef struct _DIG_ENCODER_CONTROL_PARAMETERS { |
| USHORT usPixelClock; /* in 10KHz; for bios convenient */ |
| UCHAR ucConfig; |
| /* [2] Link Select: */ |
| /* =0: PHY linkA if bfLane<3 */ |
| /* =1: PHY linkB if bfLanes<3 */ |
| /* =0: PHY linkA+B if bfLanes=3 */ |
| /* [3] Transmitter Sel */ |
| /* =0: UNIPHY or PCIEPHY */ |
| /* =1: LVTMA */ |
| UCHAR ucAction; /* =0: turn off encoder */ |
| /* =1: turn on encoder */ |
| UCHAR ucEncoderMode; |
| /* =0: DP encoder */ |
| /* =1: LVDS encoder */ |
| /* =2: DVI encoder */ |
| /* =3: HDMI encoder */ |
| /* =4: SDVO encoder */ |
| UCHAR ucLaneNum; /* how many lanes to enable */ |
| UCHAR ucReserved[2]; |
| } DIG_ENCODER_CONTROL_PARAMETERS; |
| #define DIG_ENCODER_CONTROL_PS_ALLOCATION DIG_ENCODER_CONTROL_PARAMETERS |
| #define EXTERNAL_ENCODER_CONTROL_PARAMETER DIG_ENCODER_CONTROL_PARAMETERS |
| /* ucConfig */ |
| #define ATOM_ENCODER_CONFIG_DPLINKRATE_MASK 0x01 |
| #define ATOM_ENCODER_CONFIG_DPLINKRATE_1_62GHZ 0x00 |
| #define ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ 0x01 |
| #define ATOM_ENCODER_CONFIG_LINK_SEL_MASK 0x04 |
| #define ATOM_ENCODER_CONFIG_LINKA 0x00 |
| #define ATOM_ENCODER_CONFIG_LINKB 0x04 |
| #define ATOM_ENCODER_CONFIG_LINKA_B ATOM_TRANSMITTER_CONFIG_LINKA |
| #define ATOM_ENCODER_CONFIG_LINKB_A ATOM_ENCODER_CONFIG_LINKB |
| #define ATOM_ENCODER_CONFIG_TRANSMITTER_SEL_MASK 0x08 |
| #define ATOM_ENCODER_CONFIG_UNIPHY 0x00 |
| #define ATOM_ENCODER_CONFIG_LVTMA 0x08 |
| #define ATOM_ENCODER_CONFIG_TRANSMITTER1 0x00 |
| #define ATOM_ENCODER_CONFIG_TRANSMITTER2 0x08 |
| #define ATOM_ENCODER_CONFIG_DIGB 0x80 /* VBIOS Internal use, outside SW should set this bit=0 */ |
| /* ucAction */ |
| /* ATOM_ENABLE: Enable Encoder */ |
| /* ATOM_DISABLE: Disable Encoder */ |
| /* ucEncoderMode */ |
| #define ATOM_ENCODER_MODE_DP 0 |
| #define ATOM_ENCODER_MODE_LVDS 1 |
| #define ATOM_ENCODER_MODE_DVI 2 |
| #define ATOM_ENCODER_MODE_HDMI 3 |
| #define ATOM_ENCODER_MODE_SDVO 4 |
| #define ATOM_ENCODER_MODE_TV 13 |
| #define ATOM_ENCODER_MODE_CV 14 |
| #define ATOM_ENCODER_MODE_CRT 15 |
| typedef struct _ATOM_DIG_ENCODER_CONFIG_V2 { |
| #if ATOM_BIG_ENDIAN |
| UCHAR ucReserved1:2; |
| UCHAR ucTransmitterSel:2; /* =0: UniphyAB, =1: UniphyCD =2: UniphyEF */ |
| UCHAR ucLinkSel:1; /* =0: linkA/C/E =1: linkB/D/F */ |
| UCHAR ucReserved:1; |
| UCHAR ucDPLinkRate:1; /* =0: 1.62Ghz, =1: 2.7Ghz */ |
| #else |
| UCHAR ucDPLinkRate:1; /* =0: 1.62Ghz, =1: 2.7Ghz */ |
| UCHAR ucReserved:1; |
| UCHAR ucLinkSel:1; /* =0: linkA/C/E =1: linkB/D/F */ |
| UCHAR ucTransmitterSel:2; /* =0: UniphyAB, =1: UniphyCD =2: UniphyEF */ |
| UCHAR ucReserved1:2; |
| #endif |
| } ATOM_DIG_ENCODER_CONFIG_V2; |
| typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V2 { |
| USHORT usPixelClock; /* in 10KHz; for bios convenient */ |
| ATOM_DIG_ENCODER_CONFIG_V2 acConfig; |
| UCHAR ucAction; |
| UCHAR ucEncoderMode; |
| /* =0: DP encoder */ |
| /* =1: LVDS encoder */ |
| /* =2: DVI encoder */ |
| /* =3: HDMI encoder */ |
| /* =4: SDVO encoder */ |
| UCHAR ucLaneNum; /* how many lanes to enable */ |
| UCHAR ucReserved[2]; |
| } DIG_ENCODER_CONTROL_PARAMETERS_V2; |
| /* ucConfig */ |
| #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_MASK 0x01 |
| #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_1_62GHZ 0x00 |
| #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_2_70GHZ 0x01 |
| #define ATOM_ENCODER_CONFIG_V2_LINK_SEL_MASK 0x04 |
| #define ATOM_ENCODER_CONFIG_V2_LINKA 0x00 |
| #define ATOM_ENCODER_CONFIG_V2_LINKB 0x04 |
| #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER_SEL_MASK 0x18 |
| #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER1 0x00 |
| #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER2 0x08 |
| #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER3 0x10 |
| /****************************************************************************/ |
| /* Structures used by UNIPHYTransmitterControlTable */ |
| /* LVTMATransmitterControlTable */ |
| /* DVOOutputControlTable */ |
| /****************************************************************************/ |
| typedef struct _ATOM_DP_VS_MODE { |
| UCHAR ucLaneSel; |
| UCHAR ucLaneSet; |
| } ATOM_DP_VS_MODE; |
| typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS { |
| union { |
| USHORT usPixelClock; /* in 10KHz; for bios convenient */ |
| USHORT usInitInfo; /* when init uniphy,lower 8bit is used for connector type defined in objectid.h */ |
| ATOM_DP_VS_MODE asMode; /* DP Voltage swing mode */ |
| }; |
| UCHAR ucConfig; |
| /* [0]=0: 4 lane Link, */ |
| /* =1: 8 lane Link ( Dual Links TMDS ) */ |
| /* [1]=0: InCoherent mode */ |
| /* =1: Coherent Mode */ |
| /* [2] Link Select: */ |
| /* =0: PHY linkA if bfLane<3 */ |
| /* =1: PHY linkB if bfLanes<3 */ |
| /* =0: PHY linkA+B if bfLanes=3 */ |
| /* [5:4]PCIE lane Sel */ |
| /* =0: lane 0~3 or 0~7 */ |
| /* =1: lane 4~7 */ |
| /* =2: lane 8~11 or 8~15 */ |
| /* =3: lane 12~15 */ |
| UCHAR ucAction; /* =0: turn off encoder */ |
| /* =1: turn on encoder */ |
| UCHAR ucReserved[4]; |
| } DIG_TRANSMITTER_CONTROL_PARAMETERS; |
| #define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PARAMETERS |
| /* ucInitInfo */ |
| #define ATOM_TRAMITTER_INITINFO_CONNECTOR_MASK 0x00ff |
| /* ucConfig */ |
| #define ATOM_TRANSMITTER_CONFIG_8LANE_LINK 0x01 |
| #define ATOM_TRANSMITTER_CONFIG_COHERENT 0x02 |
| #define ATOM_TRANSMITTER_CONFIG_LINK_SEL_MASK 0x04 |
| #define ATOM_TRANSMITTER_CONFIG_LINKA 0x00 |
| #define ATOM_TRANSMITTER_CONFIG_LINKB 0x04 |
| #define ATOM_TRANSMITTER_CONFIG_LINKA_B 0x00 |
| #define ATOM_TRANSMITTER_CONFIG_LINKB_A 0x04 |
| #define ATOM_TRANSMITTER_CONFIG_ENCODER_SEL_MASK 0x08 /* only used when ATOM_TRANSMITTER_ACTION_ENABLE */ |
| #define ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER 0x00 /* only used when ATOM_TRANSMITTER_ACTION_ENABLE */ |
| #define ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER 0x08 /* only used when ATOM_TRANSMITTER_ACTION_ENABLE */ |
| #define ATOM_TRANSMITTER_CONFIG_CLKSRC_MASK 0x30 |
| #define ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL 0x00 |
| #define ATOM_TRANSMITTER_CONFIG_CLKSRC_PCIE 0x20 |
| #define ATOM_TRANSMITTER_CONFIG_CLKSRC_XTALIN 0x30 |
| #define ATOM_TRANSMITTER_CONFIG_LANE_SEL_MASK 0xc0 |
| #define ATOM_TRANSMITTER_CONFIG_LANE_0_3 0x00 |
| #define ATOM_TRANSMITTER_CONFIG_LANE_0_7 0x00 |
| #define ATOM_TRANSMITTER_CONFIG_LANE_4_7 0x40 |
| #define ATOM_TRANSMITTER_CONFIG_LANE_8_11 0x80 |
| #define ATOM_TRANSMITTER_CONFIG_LANE_8_15 0x80 |
| #define ATOM_TRANSMITTER_CONFIG_LANE_12_15 0xc0 |
| /* ucAction */ |
| #define ATOM_TRANSMITTER_ACTION_DISABLE 0 |
| #define ATOM_TRANSMITTER_ACTION_ENABLE 1 |
| #define ATOM_TRANSMITTER_ACTION_LCD_BLOFF 2 |
| #define ATOM_TRANSMITTER_ACTION_LCD_BLON 3 |
| #define ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL 4 |
| #define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START 5 |
| #define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP 6 |
| #define ATOM_TRANSMITTER_ACTION_INIT 7 |
| #define ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT 8 |
| #define ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT 9 |
| #define ATOM_TRANSMITTER_ACTION_SETUP 10 |
| #define ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH 11 |
| /* Following are used for DigTransmitterControlTable ver1.2 */ |
| typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V2 { |
| #if ATOM_BIG_ENDIAN |
| UCHAR ucTransmitterSel:2; /* bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) */ |
| /* =1 Dig Transmitter 2 ( Uniphy CD ) */ |
| /* =2 Dig Transmitter 3 ( Uniphy EF ) */ |
| UCHAR ucReserved:1; |
| UCHAR fDPConnector:1; /* bit4=0: DP connector =1: None DP connector */ |
| UCHAR ucEncoderSel:1; /* bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 ) */ |
| UCHAR ucLinkSel:1; /* bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E */ |
| /* =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F */ |
| UCHAR fCoherentMode:1; /* bit1=1: Coherent Mode ( for DVI/HDMI mode ) */ |
| UCHAR fDualLinkConnector:1; /* bit0=1: Dual Link DVI connector */ |
| #else |
| UCHAR fDualLinkConnector:1; /* bit0=1: Dual Link DVI connector */ |
| UCHAR fCoherentMode:1; /* bit1=1: Coherent Mode ( for DVI/HDMI mode ) */ |
| UCHAR ucLinkSel:1; /* bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E */ |
| /* =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F */ |
| UCHAR ucEncoderSel:1; /* bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 ) */ |
| UCHAR fDPConnector:1; /* bit4=0: DP connector =1: None DP connector */ |
| UCHAR ucReserved:1; |
| UCHAR ucTransmitterSel:2; /* bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) */ |
| /* =1 Dig Transmitter 2 ( Uniphy CD ) */ |
| /* =2 Dig Transmitter 3 ( Uniphy EF ) */ |
| #endif |
| } ATOM_DIG_TRANSMITTER_CONFIG_V2; |
| /* ucConfig */ |
| /* Bit0 */ |
| #define ATOM_TRANSMITTER_CONFIG_V2_DUAL_LINK_CONNECTOR 0x01 |
| /* Bit1 */ |
| #define ATOM_TRANSMITTER_CONFIG_V2_COHERENT 0x02 |
| /* Bit2 */ |
| #define ATOM_TRANSMITTER_CONFIG_V2_LINK_SEL_MASK 0x04 |
| #define ATOM_TRANSMITTER_CONFIG_V2_LINKA 0x00 |
| #define ATOM_TRANSMITTER_CONFIG_V2_LINKB 0x04 |
| /* Bit3 */ |
| #define ATOM_TRANSMITTER_CONFIG_V2_ENCODER_SEL_MASK 0x08 |
| #define ATOM_TRANSMITTER_CONFIG_V2_DIG1_ENCODER 0x00 /* only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP */ |
| #define ATOM_TRANSMITTER_CONFIG_V2_DIG2_ENCODER 0x08 /* only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP */ |
| /* Bit4 */ |
| #define ATOM_TRASMITTER_CONFIG_V2_DP_CONNECTOR 0x10 |
| /* Bit7:6 */ |
| #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER_SEL_MASK 0xC0 |
| #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER1 0x00 /* AB */ |
| #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER2 0x40 /* CD */ |
| #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER3 0x80 /* EF */ |
| typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 { |
| union { |
| USHORT usPixelClock; /* in 10KHz; for bios convenient */ |
| USHORT usInitInfo; /* when init uniphy,lower 8bit is used for connector type defined in objectid.h */ |
| ATOM_DP_VS_MODE asMode; /* DP Voltage swing mode */ |
| }; |
| ATOM_DIG_TRANSMITTER_CONFIG_V2 acConfig; |
| UCHAR ucAction; /* define as ATOM_TRANSMITER_ACTION_XXX */ |
| UCHAR ucReserved[4]; |
| } DIG_TRANSMITTER_CONTROL_PARAMETERS_V2; |
| /****************************************************************************/ |
| /* Structures used by DAC1OuputControlTable */ |
| /* DAC2OuputControlTable */ |
| /* LVTMAOutputControlTable (Before DEC30) */ |
| /* TMDSAOutputControlTable (Before DEC30) */ |
| /****************************************************************************/ |
| typedef struct _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS { |
| UCHAR ucAction; /* Possible input:ATOM_ENABLE||ATOMDISABLE */ |
| /* When the display is LCD, in addition to above: */ |
| /* ATOM_LCD_BLOFF|| ATOM_LCD_BLON ||ATOM_LCD_BL_BRIGHTNESS_CONTROL||ATOM_LCD_SELFTEST_START|| */ |
| /* ATOM_LCD_SELFTEST_STOP */ |
| UCHAR aucPadding[3]; /* padding to DWORD aligned */ |
| } DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS; |
| #define DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS |
| #define CRT1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS |
| #define CRT1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION |
| #define CRT2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS |
| #define CRT2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION |
| #define CV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS |
| #define CV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION |
| #define TV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS |
| #define TV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION |
| #define DFP1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS |
| #define DFP1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION |
| #define DFP2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS |
| #define DFP2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION |
| #define LCD1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS |
| #define LCD1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION |
| #define DVO_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS |
| #define DVO_OUTPUT_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PS_ALLOCATION |
| #define DVO_OUTPUT_CONTROL_PARAMETERS_V3 DIG_TRANSMITTER_CONTROL_PARAMETERS |
| /****************************************************************************/ |
| /* Structures used by BlankCRTCTable */ |
| /****************************************************************************/ |
| typedef struct _BLANK_CRTC_PARAMETERS { |
| UCHAR ucCRTC; /* ATOM_CRTC1 or ATOM_CRTC2 */ |
| UCHAR ucBlanking; /* ATOM_BLANKING or ATOM_BLANKINGOFF */ |
| USHORT usBlackColorRCr; |
| USHORT usBlackColorGY; |
| USHORT usBlackColorBCb; |
| } BLANK_CRTC_PARAMETERS; |
| #define BLANK_CRTC_PS_ALLOCATION BLANK_CRTC_PARAMETERS |
| /****************************************************************************/ |
| /* Structures used by EnableCRTCTable */ |
| /* EnableCRTCMemReqTable */ |
| /* UpdateCRTC_DoubleBufferRegistersTable */ |
| /****************************************************************************/ |
| typedef struct _ENABLE_CRTC_PARAMETERS { |
| UCHAR ucCRTC; /* ATOM_CRTC1 or ATOM_CRTC2 */ |
| UCHAR ucEnable; /* ATOM_ENABLE or ATOM_DISABLE */ |
| UCHAR ucPadding[2]; |
| } ENABLE_CRTC_PARAMETERS; |
| #define ENABLE_CRTC_PS_ALLOCATION ENABLE_CRTC_PARAMETERS |
| /****************************************************************************/ |
| /* Structures used by SetCRTC_OverScanTable */ |
| /****************************************************************************/ |
| typedef struct _SET_CRTC_OVERSCAN_PARAMETERS { |
| USHORT usOverscanRight; /* right */ |
| USHORT usOverscanLeft; /* left */ |
| USHORT usOverscanBottom; /* bottom */ |
| USHORT usOverscanTop; /* top */ |
| UCHAR ucCRTC; /* ATOM_CRTC1 or ATOM_CRTC2 */ |
| UCHAR ucPadding[3]; |
| } SET_CRTC_OVERSCAN_PARAMETERS; |
| #define SET_CRTC_OVERSCAN_PS_ALLOCATION SET_CRTC_OVERSCAN_PARAMETERS |
| /****************************************************************************/ |
| /* Structures used by SetCRTC_ReplicationTable */ |
| /****************************************************************************/ |
| typedef struct _SET_CRTC_REPLICATION_PARAMETERS { |
| UCHAR ucH_Replication; /* horizontal replication */ |
| UCHAR ucV_Replication; /* vertical replication */ |
| UCHAR usCRTC; /* ATOM_CRTC1 or ATOM_CRTC2 */ |
| UCHAR ucPadding; |
| } SET_CRTC_REPLICATION_PARAMETERS; |
| #define SET_CRTC_REPLICATION_PS_ALLOCATION SET_CRTC_REPLICATION_PARAMETERS |
| /****************************************************************************/ |
| /* Structures used by SelectCRTC_SourceTable */ |
| /****************************************************************************/ |
| typedef struct _SELECT_CRTC_SOURCE_PARAMETERS { |
| UCHAR ucCRTC; /* ATOM_CRTC1 or ATOM_CRTC2 */ |
| UCHAR ucDevice; /* ATOM_DEVICE_CRT1|ATOM_DEVICE_CRT2|.... */ |
| UCHAR ucPadding[2]; |
| } SELECT_CRTC_SOURCE_PARAMETERS; |
| #define SELECT_CRTC_SOURCE_PS_ALLOCATION SELECT_CRTC_SOURCE_PARAMETERS |
| typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V2 { |
| UCHAR ucCRTC; /* ATOM_CRTC1 or ATOM_CRTC2 */ |
| UCHAR ucEncoderID; /* DAC1/DAC2/TVOUT/DIG1/DIG2/DVO */ |
| UCHAR ucEncodeMode; /* Encoding mode, only valid when using DIG1/DIG2/DVO */ |
| UCHAR ucPadding; |
| } SELECT_CRTC_SOURCE_PARAMETERS_V2; |
| /* ucEncoderID */ |
| /* #define ASIC_INT_DAC1_ENCODER_ID 0x00 */ |
| /* #define ASIC_INT_TV_ENCODER_ID 0x02 */ |
| /* #define ASIC_INT_DIG1_ENCODER_ID 0x03 */ |
| /* #define ASIC_INT_DAC2_ENCODER_ID 0x04 */ |
| /* #define ASIC_EXT_TV_ENCODER_ID 0x06 */ |
| /* #define ASIC_INT_DVO_ENCODER_ID 0x07 */ |
| /* #define ASIC_INT_DIG2_ENCODER_ID 0x09 */ |
| /* #define ASIC_EXT_DIG_ENCODER_ID 0x05 */ |
| /* ucEncodeMode */ |
| /* #define ATOM_ENCODER_MODE_DP 0 */ |
| /* #define ATOM_ENCODER_MODE_LVDS 1 */ |
| /* #define ATOM_ENCODER_MODE_DVI 2 */ |
| /* #define ATOM_ENCODER_MODE_HDMI 3 */ |
| /* #define ATOM_ENCODER_MODE_SDVO 4 */ |
| /* #define ATOM_ENCODER_MODE_TV 13 */ |
| /* #define ATOM_ENCODER_MODE_CV 14 */ |
| /* #define ATOM_ENCODER_MODE_CRT 15 */ |
| /****************************************************************************/ |
| /* Structures used by SetPixelClockTable */ |
| /* GetPixelClockTable */ |
| /****************************************************************************/ |
| /* Major revision=1., Minor revision=1 */ |
| typedef struct _PIXEL_CLOCK_PARAMETERS { |
| USHORT usPixelClock; /* in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) */ |
| /* 0 means disable PPLL */ |
| USHORT usRefDiv; /* Reference divider */ |
| USHORT usFbDiv; /* feedback divider */ |
| UCHAR ucPostDiv; /* post divider */ |
| UCHAR ucFracFbDiv; /* fractional feedback divider */ |
| UCHAR ucPpll; /* ATOM_PPLL1 or ATOM_PPL2 */ |
| UCHAR ucRefDivSrc; /* ATOM_PJITTER or ATO_NONPJITTER */ |
| UCHAR ucCRTC; /* Which CRTC uses this Ppll */ |
| UCHAR ucPadding; |
| } PIXEL_CLOCK_PARAMETERS; |
| /* Major revision=1., Minor revision=2, add ucMiscIfno */ |
| /* ucMiscInfo: */ |
| #define MISC_FORCE_REPROG_PIXEL_CLOCK 0x1 |
| #define MISC_DEVICE_INDEX_MASK 0xF0 |
| #define MISC_DEVICE_INDEX_SHIFT 4 |
| typedef struct _PIXEL_CLOCK_PARAMETERS_V2 { |
| USHORT usPixelClock; /* in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) */ |
| /* 0 means disable PPLL */ |
| USHORT usRefDiv; /* Reference divider */ |
| USHORT usFbDiv; /* feedback divider */ |
| UCHAR ucPostDiv; /* post divider */ |
| UCHAR ucFracFbDiv; /* fractional feedback divider */ |
| UCHAR ucPpll; /* ATOM_PPLL1 or ATOM_PPL2 */ |
| UCHAR ucRefDivSrc; /* ATOM_PJITTER or ATO_NONPJITTER */ |
| UCHAR ucCRTC; /* Which CRTC uses this Ppll */ |
| UCHAR ucMiscInfo; /* Different bits for different purpose, bit [7:4] as device index, bit[0]=Force prog */ |
| } PIXEL_CLOCK_PARAMETERS_V2; |
| /* Major revision=1., Minor revision=3, structure/definition change */ |
| /* ucEncoderMode: */ |
| /* ATOM_ENCODER_MODE_DP */ |
| /* ATOM_ENOCDER_MODE_LVDS */ |
| /* ATOM_ENOCDER_MODE_DVI */ |
| /* ATOM_ENOCDER_MODE_HDMI */ |
| /* ATOM_ENOCDER_MODE_SDVO */ |
| /* ATOM_ENCODER_MODE_TV 13 */ |
| /* ATOM_ENCODER_MODE_CV 14 */ |
| /* ATOM_ENCODER_MODE_CRT 15 */ |
| /* ucDVOConfig */ |
| /* #define DVO_ENCODER_CONFIG_RATE_SEL 0x01 */ |
| /* #define DVO_ENCODER_CONFIG_DDR_SPEED 0x00 */ |
| /* #define DVO_ENCODER_CONFIG_SDR_SPEED 0x01 */ |
| /* #define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c */ |
| /* #define DVO_ENCODER_CONFIG_LOW12BIT 0x00 */ |
| /* #define DVO_ENCODER_CONFIG_UPPER12BIT 0x04 */ |
| /* #define DVO_ENCODER_CONFIG_24BIT 0x08 */ |
| /* ucMiscInfo: also changed, see below */ |
| #define PIXEL_CLOCK_MISC_FORCE_PROG_PPLL 0x01 |
| #define PIXEL_CLOCK_MISC_VGA_MODE 0x02 |
| #define PIXEL_CLOCK_MISC_CRTC_SEL_MASK 0x04 |
| #define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1 0x00 |
| #define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2 0x04 |
| #define PIXEL_CLOCK_MISC_USE_ENGINE_FOR_DISPCLK 0x08 |
| typedef struct _PIXEL_CLOCK_PARAMETERS_V3 { |
| USHORT usPixelClock; /* in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) */ |
| /* 0 means disable PPLL. For VGA PPLL,make sure this value is not 0. */ |
| USHORT usRefDiv; /* Reference divider */ |
| USHORT usFbDiv; /* feedback divider */ |
| UCHAR ucPostDiv; /* post divider */ |
| UCHAR ucFracFbDiv; /* fractional feedback divider */ |
| UCHAR ucPpll; /* ATOM_PPLL1 or ATOM_PPL2 */ |
| UCHAR ucTransmitterId; /* graphic encoder id defined in objectId.h */ |
| union { |
| UCHAR ucEncoderMode; /* encoder type defined as ATOM_ENCODER_MODE_DP/DVI/HDMI/ */ |
| UCHAR ucDVOConfig; /* when use DVO, need to know SDR/DDR, 12bit or 24bit */ |
| }; |
| UCHAR ucMiscInfo; /* bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC sel */ |
| /* bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source */ |
| } PIXEL_CLOCK_PARAMETERS_V3; |
| #define PIXEL_CLOCK_PARAMETERS_LAST PIXEL_CLOCK_PARAMETERS_V2 |
| #define GET_PIXEL_CLOCK_PS_ALLOCATION PIXEL_CLOCK_PARAMETERS_LAST |
| /****************************************************************************/ |
| /* Structures used by AdjustDisplayPllTable */ |
| /****************************************************************************/ |
| typedef struct _ADJUST_DISPLAY_PLL_PARAMETERS { |
| USHORT usPixelClock; |
| UCHAR ucTransmitterID; |
| UCHAR ucEncodeMode; |
| union { |
| UCHAR ucDVOConfig; /* if DVO, need passing link rate and output 12bitlow or 24bit */ |
| UCHAR ucConfig; /* if none DVO, not defined yet */ |
| }; |
| UCHAR ucReserved[3]; |
| } ADJUST_DISPLAY_PLL_PARAMETERS; |
| #define ADJUST_DISPLAY_CONFIG_SS_ENABLE 0x10 |
| #define ADJUST_DISPLAY_PLL_PS_ALLOCATION ADJUST_DISPLAY_PLL_PARAMETERS |
| /****************************************************************************/ |
| /* Structures used by EnableYUVTable */ |
| /****************************************************************************/ |
| typedef struct _ENABLE_YUV_PARAMETERS { |
| UCHAR ucEnable; /* ATOM_ENABLE:Enable YUV or ATOM_DISABLE:Disable YUV (RGB) */ |
| UCHAR ucCRTC; /* Which CRTC needs this YUV or RGB format */ |
| UCHAR ucPadding[2]; |
| } ENABLE_YUV_PARAMETERS; |
| #define ENABLE_YUV_PS_ALLOCATION ENABLE_YUV_PARAMETERS |
| /****************************************************************************/ |
| /* Structures used by GetMemoryClockTable */ |
| /****************************************************************************/ |
| typedef struct _GET_MEMORY_CLOCK_PARAMETERS { |
| ULONG ulReturnMemoryClock; /* current memory speed in 10KHz unit */ |
| } GET_MEMORY_CLOCK_PARAMETERS; |
| #define GET_MEMORY_CLOCK_PS_ALLOCATION GET_MEMORY_CLOCK_PARAMETERS |
| /****************************************************************************/ |
| /* Structures used by GetEngineClockTable */ |
| /****************************************************************************/ |
| typedef struct _GET_ENGINE_CLOCK_PARAMETERS { |
| ULONG ulReturnEngineClock; /* current engine speed in 10KHz unit */ |
| } GET_ENGINE_CLOCK_PARAMETERS; |
| #define GET_ENGINE_CLOCK_PS_ALLOCATION GET_ENGINE_CLOCK_PARAMETERS |
| /****************************************************************************/ |
| /* Following Structures and constant may be obsolete */ |
| /****************************************************************************/ |
| /* Maxium 8 bytes,the data read in will be placed in the parameter space. */ |
| /* Read operaion successeful when the paramter space is non-zero, otherwise read operation failed */ |
| typedef struct _READ_EDID_FROM_HW_I2C_DATA_PARAMETERS { |
| USHORT usPrescale; /* Ratio between Engine clock and I2C clock */ |
| USHORT usVRAMAddress; /* Adress in Frame Buffer where to pace raw EDID */ |
| USHORT usStatus; /* When use output: lower byte EDID checksum, high byte hardware status */ |
| /* WHen use input: lower byte as 'byte to read':currently limited to 128byte or 1byte */ |
| UCHAR ucSlaveAddr; /* Read from which slave */ |
| UCHAR ucLineNumber; /* Read from which HW assisted line */ |
| } READ_EDID_FROM_HW_I2C_DATA_PARAMETERS; |
| #define READ_EDID_FROM_HW_I2C_DATA_PS_ALLOCATION READ_EDID_FROM_HW_I2C_DATA_PARAMETERS |
| #define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSDATABYTE 0 |
| #define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSTWODATABYTES 1 |
| #define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_PSOFFSET_IDDATABLOCK 2 |
| #define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_IDOFFSET_PLUS_IDDATABLOCK 3 |
| #define ATOM_WRITE_I2C_FORMAT_IDCOUNTER_IDOFFSET_IDDATABLOCK 4 |
| typedef struct _WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS { |
| USHORT usPrescale; /* Ratio between Engine clock and I2C clock */ |
| USHORT usByteOffset; /* Write to which byte */ |
| /* Upper portion of usByteOffset is Format of data */ |
| /* 1bytePS+offsetPS */ |
| /* 2bytesPS+offsetPS */ |
| /* blockID+offsetPS */ |
| /* blockID+offsetID */ |
| /* blockID+counterID+offsetID */ |
| UCHAR ucData; /* PS data1 */ |
| UCHAR ucStatus; /* Status byte 1=success, 2=failure, Also is used as PS data2 */ |
| UCHAR ucSlaveAddr; /* Write to which slave */ |
| UCHAR ucLineNumber; /* Write from which HW assisted line */ |
| } WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS; |
| #define WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS |
| typedef struct _SET_UP_HW_I2C_DATA_PARAMETERS { |
| USHORT usPrescale; /* Ratio between Engine clock and I2C clock */ |
| UCHAR ucSlaveAddr; /* Write to which slave */ |
| UCHAR ucLineNumber; /* Write from which HW assisted line */ |
| } SET_UP_HW_I2C_DATA_PARAMETERS; |
| /**************************************************************************/ |
| #define SPEED_FAN_CONTROL_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS |
| /****************************************************************************/ |
| /* Structures used by PowerConnectorDetectionTable */ |
| /****************************************************************************/ |
| typedef struct _POWER_CONNECTOR_DETECTION_PARAMETERS { |
| UCHAR ucPowerConnectorStatus; /* Used for return value 0: detected, 1:not detected */ |
| UCHAR ucPwrBehaviorId; |
| USHORT usPwrBudget; /* how much power currently boot to in unit of watt */ |
| } POWER_CONNECTOR_DETECTION_PARAMETERS; |
| typedef struct POWER_CONNECTOR_DETECTION_PS_ALLOCATION { |
| UCHAR ucPowerConnectorStatus; /* Used for return value 0: detected, 1:not detected */ |
| UCHAR ucReserved; |
| USHORT usPwrBudget; /* how much power currently boot to in unit of watt */ |
| WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; |
| } POWER_CONNECTOR_DETECTION_PS_ALLOCATION; |
| /****************************LVDS SS Command Table Definitions**********************/ |
| /****************************************************************************/ |
| /* Structures used by EnableSpreadSpectrumOnPPLLTable */ |
| /****************************************************************************/ |
| typedef struct _ENABLE_LVDS_SS_PARAMETERS { |
| USHORT usSpreadSpectrumPercentage; |
| UCHAR ucSpreadSpectrumType; /* Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD */ |
| UCHAR ucSpreadSpectrumStepSize_Delay; /* bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY */ |
| UCHAR ucEnable; /* ATOM_ENABLE or ATOM_DISABLE */ |
| UCHAR ucPadding[3]; |
| } ENABLE_LVDS_SS_PARAMETERS; |
| /* ucTableFormatRevision=1,ucTableContentRevision=2 */ |
| typedef struct _ENABLE_LVDS_SS_PARAMETERS_V2 { |
| USHORT usSpreadSpectrumPercentage; |
| UCHAR ucSpreadSpectrumType; /* Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD */ |
| UCHAR ucSpreadSpectrumStep; /* */ |
| UCHAR ucEnable; /* ATOM_ENABLE or ATOM_DISABLE */ |
| UCHAR ucSpreadSpectrumDelay; |
| UCHAR ucSpreadSpectrumRange; |
| UCHAR ucPadding; |
| } ENABLE_LVDS_SS_PARAMETERS_V2; |
| /* This new structure is based on ENABLE_LVDS_SS_PARAMETERS but expands to SS on PPLL, so other devices can use SS. */ |
| typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL { |
| USHORT usSpreadSpectrumPercentage; |
| UCHAR ucSpreadSpectrumType; /* Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD */ |
| UCHAR ucSpreadSpectrumStep; /* */ |
| UCHAR ucEnable; /* ATOM_ENABLE or ATOM_DISABLE */ |
| UCHAR ucSpreadSpectrumDelay; |
| UCHAR ucSpreadSpectrumRange; |
| UCHAR ucPpll; /* ATOM_PPLL1/ATOM_PPLL2 */ |
| } ENABLE_SPREAD_SPECTRUM_ON_PPLL; |
| #define ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION ENABLE_SPREAD_SPECTRUM_ON_PPLL |
| /**************************************************************************/ |
| typedef struct _SET_PIXEL_CLOCK_PS_ALLOCATION { |
| PIXEL_CLOCK_PARAMETERS sPCLKInput; |
| ENABLE_SPREAD_SPECTRUM_ON_PPLL sReserved; /* Caller doesn't need to init this portion */ |
| } SET_PIXEL_CLOCK_PS_ALLOCATION; |
| #define ENABLE_VGA_RENDER_PS_ALLOCATION SET_PIXEL_CLOCK_PS_ALLOCATION |
| /****************************************************************************/ |
| /* Structures used by ### */ |
| /****************************************************************************/ |
| typedef struct _MEMORY_TRAINING_PARAMETERS { |
| ULONG ulTargetMemoryClock; /* In 10Khz unit */ |
| } MEMORY_TRAINING_PARAMETERS; |
| #define MEMORY_TRAINING_PS_ALLOCATION MEMORY_TRAINING_PARAMETERS |
| /****************************LVDS and other encoder command table definitions **********************/ |
| /****************************************************************************/ |
| /* Structures used by LVDSEncoderControlTable (Before DCE30) */ |
| /* LVTMAEncoderControlTable (Before DCE30) */ |
| /* TMDSAEncoderControlTable (Before DCE30) */ |
| /****************************************************************************/ |
| typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS { |
| USHORT usPixelClock; /* in 10KHz; for bios convenient */ |
| UCHAR ucMisc; /* bit0=0: Enable single link */ |
| /* =1: Enable dual link */ |
| /* Bit1=0: 666RGB */ |
| /* =1: 888RGB */ |
| UCHAR ucAction; /* 0: turn off encoder */ |
| /* 1: setup and turn on encoder */ |
| } LVDS_ENCODER_CONTROL_PARAMETERS; |
| #define LVDS_ENCODER_CONTROL_PS_ALLOCATION LVDS_ENCODER_CONTROL_PARAMETERS |
| #define TMDS1_ENCODER_CONTROL_PARAMETERS LVDS_ENCODER_CONTROL_PARAMETERS |
| #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION TMDS1_ENCODER_CONTROL_PARAMETERS |
| #define TMDS2_ENCODER_CONTROL_PARAMETERS TMDS1_ENCODER_CONTROL_PARAMETERS |
| #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION TMDS2_ENCODER_CONTROL_PARAMETERS |
| /* ucTableFormatRevision=1,ucTableContentRevision=2 */ |
| typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V2 { |
| USHORT usPixelClock; /* in 10KHz; for bios convenient */ |
| UCHAR ucMisc; /* see PANEL_ENCODER_MISC_xx defintions below */ |
| UCHAR ucAction; /* 0: turn off encoder */ |
| /* 1: setup and turn on encoder */ |
| UCHAR ucTruncate; /* bit0=0: Disable truncate */ |
| /* =1: Enable truncate */ |
| /* bit4=0: 666RGB */ |
| /* =1: 888RGB */ |
| UCHAR ucSpatial; /* bit0=0: Disable spatial dithering */ |
| /* =1: Enable spatial dithering */ |
| /* bit4=0: 666RGB */ |
| /* =1: 888RGB */ |
| UCHAR ucTemporal; /* bit0=0: Disable temporal dithering */ |
| /* =1: Enable temporal dithering */ |
| /* bit4=0: 666RGB */ |
| /* =1: 888RGB */ |
| /* bit5=0: Gray level 2 */ |
| /* =1: Gray level 4 */ |
| UCHAR ucFRC; /* bit4=0: 25FRC_SEL pattern E */ |
| /* =1: 25FRC_SEL pattern F */ |
| /* bit6:5=0: 50FRC_SEL pattern A */ |
| /* =1: 50FRC_SEL pattern B */ |
| /* =2: 50FRC_SEL pattern C */ |
| /* =3: 50FRC_SEL pattern D */ |
| /* bit7=0: 75FRC_SEL pattern E */ |
| /* =1: 75FRC_SEL pattern F */ |
| } LVDS_ENCODER_CONTROL_PARAMETERS_V2; |
| #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 |
| #define TMDS1_ENCODER_CONTROL_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 |
| #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2 |
| #define TMDS2_ENCODER_CONTROL_PARAMETERS_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2 |
| #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS2_ENCODER_CONTROL_PARAMETERS_V2 |
| #define LVDS_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V2 |
| #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 |
| #define TMDS1_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 |
| #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS1_ENCODER_CONTROL_PARAMETERS_V3 |
| #define TMDS2_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 |
| #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS2_ENCODER_CONTROL_PARAMETERS_V3 |
| /****************************************************************************/ |
| /* Structures used by ### */ |
| /****************************************************************************/ |
| typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS { |
| UCHAR ucEnable; /* Enable or Disable External TMDS encoder */ |
| UCHAR ucMisc; /* Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1:888RGB} */ |
| UCHAR ucPadding[2]; |
| } ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS; |
| typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION { |
| ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS sXTmdsEncoder; |
| WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; /* Caller doesn't need to init this portion */ |
| } ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION; |
| #define ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 |
| typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2 { |
| ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 sXTmdsEncoder; |
| WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; /* Caller doesn't need to init this portion */ |
| } ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2; |
| typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION { |
| DIG_ENCODER_CONTROL_PARAMETERS sDigEncoder; |
| WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; |
| } EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION; |
| /****************************************************************************/ |
| /* Structures used by DVOEncoderControlTable */ |
| /****************************************************************************/ |
| /* ucTableFormatRevision=1,ucTableContentRevision=3 */ |
| /* ucDVOConfig: */ |
| #define DVO_ENCODER_CONFIG_RATE_SEL 0x01 |
| #define DVO_ENCODER_CONFIG_DDR_SPEED 0x00 |
| #define DVO_ENCODER_CONFIG_SDR_SPEED 0x01 |
| #define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c |
| #define DVO_ENCODER_CONFIG_LOW12BIT 0x00 |
| #define DVO_ENCODER_CONFIG_UPPER12BIT 0x04 |
| #define DVO_ENCODER_CONFIG_24BIT 0x08 |
| typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V3 { |
| USHORT usPixelClock; |
| UCHAR ucDVOConfig; |
| UCHAR ucAction; /* ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT */ |
| UCHAR ucReseved[4]; |
| } DVO_ENCODER_CONTROL_PARAMETERS_V3; |
| #define DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 DVO_ENCODER_CONTROL_PARAMETERS_V3 |
| /* ucTableFormatRevision=1 */ |
| /* ucTableContentRevision=3 structure is not changed but usMisc add bit 1 as another input for */ |
| /* bit1=0: non-coherent mode */ |
| /* =1: coherent mode */ |
| /* ========================================================================================== */ |
| /* Only change is here next time when changing encoder parameter definitions again! */ |
| #define LVDS_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 |
| #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_LAST LVDS_ENCODER_CONTROL_PARAMETERS_LAST |
| #define TMDS1_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 |
| #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS1_ENCODER_CONTROL_PARAMETERS_LAST |
| #define TMDS2_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 |
| #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS2_ENCODER_CONTROL_PARAMETERS_LAST |
| #define DVO_ENCODER_CONTROL_PARAMETERS_LAST DVO_ENCODER_CONTROL_PARAMETERS |
| #define DVO_ENCODER_CONTROL_PS_ALLOCATION_LAST DVO_ENCODER_CONTROL_PS_ALLOCATION |
| /* ========================================================================================== */ |
| #define PANEL_ENCODER_MISC_DUAL 0x01 |
| #define PANEL_ENCODER_MISC_COHERENT 0x02 |
| #define PANEL_ENCODER_MISC_TMDS_LINKB 0x04 |
| #define PANEL_ENCODER_MISC_HDMI_TYPE 0x08 |
| #define PANEL_ENCODER_ACTION_DISABLE ATOM_DISABLE |
| #define PANEL_ENCODER_ACTION_ENABLE ATOM_ENABLE |
| #define PANEL_ENCODER_ACTION_COHERENTSEQ (ATOM_ENABLE+1) |
| #define PANEL_ENCODER_TRUNCATE_EN 0x01 |
| #define PANEL_ENCODER_TRUNCATE_DEPTH 0x10 |
| #define PANEL_ENCODER_SPATIAL_DITHER_EN 0x01 |
| #define PANEL_ENCODER_SPATIAL_DITHER_DEPTH 0x10 |
| #define PANEL_ENCODER_TEMPORAL_DITHER_EN 0x01 |
| #define PANEL_ENCODER_TEMPORAL_DITHER_DEPTH 0x10 |
| #define PANEL_ENCODER_TEMPORAL_LEVEL_4 0x20 |
| #define PANEL_ENCODER_25FRC_MASK 0x10 |
| #define PANEL_ENCODER_25FRC_E 0x00 |
| #define PANEL_ENCODER_25FRC_F 0x10 |
| #define PANEL_ENCODER_50FRC_MASK 0x60 |
| #define PANEL_ENCODER_50FRC_A 0x00 |
| #define PANEL_ENCODER_50FRC_B 0x20 |
| #define PANEL_ENCODER_50FRC_C 0x40 |
| #define PANEL_ENCODER_50FRC_D 0x60 |
| #define PANEL_ENCODER_75FRC_MASK 0x80 |
| #define PANEL_ENCODER_75FRC_E 0x00 |
| #define PANEL_ENCODER_75FRC_F 0x80 |
| /****************************************************************************/ |
| /* Structures used by SetVoltageTable */ |
| /****************************************************************************/ |
| #define SET_VOLTAGE_TYPE_ASIC_VDDC 1 |
| #define SET_VOLTAGE_TYPE_ASIC_MVDDC 2 |
| #define SET_VOLTAGE_TYPE_ASIC_MVDDQ 3 |
| #define SET_VOLTAGE_TYPE_ASIC_VDDCI 4 |
| #define SET_VOLTAGE_INIT_MODE 5 |
| #define SET_VOLTAGE_GET_MAX_VOLTAGE 6 /* Gets the Max. voltage for the soldered Asic */ |
| #define SET_ASIC_VOLTAGE_MODE_ALL_SOURCE 0x1 |
| #define SET_ASIC_VOLTAGE_MODE_SOURCE_A 0x2 |
| #define SET_ASIC_VOLTAGE_MODE_SOURCE_B 0x4 |
| #define SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE 0x0 |
| #define SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL 0x1 |
| #define SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK 0x2 |
| typedef struct _SET_VOLTAGE_PARAMETERS { |
| UCHAR ucVoltageType; /* To tell which voltage to set up, VDDC/MVDDC/MVDDQ */ |
| UCHAR ucVoltageMode; /* To set all, to set source A or source B or ... */ |
| UCHAR ucVoltageIndex; /* An index to tell which voltage level */ |
| UCHAR ucReserved; |
| } SET_VOLTAGE_PARAMETERS; |
| typedef struct _SET_VOLTAGE_PARAMETERS_V2 { |
| UCHAR ucVoltageType; /* To tell which voltage to set up, VDDC/MVDDC/MVDDQ */ |
| UCHAR ucVoltageMode; /* Not used, maybe use for state machine for differen power mode */ |
| USHORT usVoltageLevel; /* real voltage level */ |
| } SET_VOLTAGE_PARAMETERS_V2; |
| typedef struct _SET_VOLTAGE_PS_ALLOCATION { |
| SET_VOLTAGE_PARAMETERS sASICSetVoltage; |
| WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; |
| } SET_VOLTAGE_PS_ALLOCATION; |
| /****************************************************************************/ |
| /* Structures used by TVEncoderControlTable */ |
| /****************************************************************************/ |
| typedef struct _TV_ENCODER_CONTROL_PARAMETERS { |
| USHORT usPixelClock; /* in 10KHz; for bios convenient */ |
| UCHAR ucTvStandard; /* See definition "ATOM_TV_NTSC ..." */ |
| UCHAR ucAction; /* 0: turn off encoder */ |
| /* 1: setup and turn on encoder */ |
| } TV_ENCODER_CONTROL_PARAMETERS; |
| typedef struct _TV_ENCODER_CONTROL_PS_ALLOCATION { |
| TV_ENCODER_CONTROL_PARAMETERS sTVEncoder; |
| WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; /* Don't set this one */ |
| } TV_ENCODER_CONTROL_PS_ALLOCATION; |
| /* ==============================Data Table Portion==================================== */ |
| #ifdef UEFI_BUILD |
| #define UTEMP USHORT |
| #define USHORT void* |
| #endif |
| /****************************************************************************/ |
| /* Structure used in Data.mtb */ |
| /****************************************************************************/ |
| typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES { |
| USHORT UtilityPipeLine; /* Offest for the utility to get parser info,Don't change this position! */ |
| USHORT MultimediaCapabilityInfo; /* Only used by MM Lib,latest version 1.1, not configuable from Bios, need to include the table to build Bios */ |
| USHORT MultimediaConfigInfo; /* Only used by MM Lib,latest version 2.1, not configuable from Bios, need to include the table to build Bios */ |
| USHORT StandardVESA_Timing; /* Only used by Bios */ |
| USHORT FirmwareInfo; /* Shared by various SW components,latest version 1.4 */ |
| USHORT DAC_Info; /* Will be obsolete from R600 */ |
| USHORT LVDS_Info; /* Shared by various SW components,latest version 1.1 */ |
| USHORT TMDS_Info; /* Will be obsolete from R600 */ |
| USHORT AnalogTV_Info; /* Shared by various SW components,latest version 1.1 */ |
| USHORT SupportedDevicesInfo; /* Will be obsolete from R600 */ |
| USHORT GPIO_I2C_Info; /* Shared by various SW components,latest version 1.2 will be used from R600 */ |
| USHORT VRAM_UsageByFirmware; /* Shared by various SW components,latest version 1.3 will be used from R600 */ |
| USHORT GPIO_Pin_LUT; /* Shared by various SW components,latest version 1.1 */ |
| USHORT VESA_ToInternalModeLUT; /* Only used by Bios */ |
| USHORT ComponentVideoInfo; /* Shared by various SW components,latest version 2.1 will be used from R600 */ |
| USHORT PowerPlayInfo; /* Shared by various SW components,latest version 2.1,new design from R600 */ |
| USHORT CompassionateData; /* Will be obsolete from R600 */ |
| USHORT SaveRestoreInfo; /* Only used by Bios */ |
| USHORT PPLL_SS_Info; /* Shared by various SW components,latest version 1.2, used to call SS_Info, change to new name because of int ASIC SS info */ |
| USHORT OemInfo; /* Defined and used by external SW, should be obsolete soon */ |
| USHORT XTMDS_Info; /* Will be obsolete from R600 */ |
| USHORT MclkSS_Info; /* Shared by various SW components,latest version 1.1, only enabled when ext SS chip is used */ |
| USHORT Object_Header; /* Shared by various SW components,latest version 1.1 */ |
| USHORT IndirectIOAccess; /* Only used by Bios,this table position can't change at all!! */ |
| USHORT MC_InitParameter; /* Only used by command table */ |
| USHORT ASIC_VDDC_Info; /* Will be obsolete from R600 */ |
| USHORT ASIC_InternalSS_Info; /* New tabel name from R600, used to be called "ASIC_MVDDC_Info" */ |
| USHORT TV_VideoMode; /* Only used by command table */ |
| USHORT VRAM_Info; /* Only used by command table, latest version 1.3 */ |
| USHORT MemoryTrainingInfo; /* Used for VBIOS and Diag utility for memory training purpose since R600. the new table rev start from 2.1 */ |
| USHORT IntegratedSystemInfo; /* Shared by various SW components */ |
| USHORT ASIC_ProfilingInfo; /* New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600 */ |
| USHORT VoltageObjectInfo; /* Shared by various SW components, latest version 1.1 */ |
| USHORT PowerSourceInfo; /* Shared by various SW components, latest versoin 1.1 */ |
| } ATOM_MASTER_LIST_OF_DATA_TABLES; |
| #ifdef UEFI_BUILD |
| #define USHORT UTEMP |
| #endif |
| typedef struct _ATOM_MASTER_DATA_TABLE { |
| ATOM_COMMON_TABLE_HEADER sHeader; |
| ATOM_MASTER_LIST_OF_DATA_TABLES ListOfDataTables; |
| } ATOM_MASTER_DATA_TABLE; |
| /****************************************************************************/ |
| /* Structure used in MultimediaCapabilityInfoTable */ |
| /****************************************************************************/ |
| typedef struct _ATOM_MULTIMEDIA_CAPABILITY_INFO { |
| ATOM_COMMON_TABLE_HEADER sHeader; |
| ULONG ulSignature; /* HW info table signature string "$ATI" */ |
| UCHAR ucI2C_Type; /* I2C type (normal GP_IO, ImpactTV GP_IO, Dedicated I2C pin, etc) */ |
| UCHAR ucTV_OutInfo; /* Type of TV out supported (3:0) and video out crystal frequency (6:4) and TV data port (7) */ |
| UCHAR ucVideoPortInfo; /* Provides the video port capabilities */ |
| UCHAR ucHostPortInfo; /* Provides host port configuration information */ |
| } ATOM_MULTIMEDIA_CAPABILITY_INFO; |
| /****************************************************************************/ |
| /* Structure used in MultimediaConfigInfoTable */ |
| /****************************************************************************/ |
| typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO { |
| ATOM_COMMON_TABLE_HEADER sHeader; |
| ULONG ulSignature; /* MM info table signature sting "$MMT" */ |
| UCHAR ucTunerInfo; /* Type of tuner installed on the adapter (4:0) and video input for tuner (7:5) */ |
| UCHAR ucAudioChipInfo; /* List the audio chip type (3:0) product type (4) and OEM revision (7:5) */ |
| UCHAR ucProductID; /* Defines as OEM ID or ATI board ID dependent on product type setting */ |
| UCHAR ucMiscInfo1; /* Tuner voltage (1:0) HW teletext support (3:2) FM audio decoder (5:4) reserved (6) audio scrambling (7) */ |
| UCHAR ucMiscInfo2; /* I2S input config (0) I2S output config (1) I2S Audio Chip (4:2) SPDIF Output Config (5) reserved (7:6) */ |
| UCHAR ucMiscInfo3; /* Video Decoder Type (3:0) Video In Standard/Crystal (7:4) */ |
| UCHAR ucMiscInfo4; /* Video Decoder Host Config (2:0) reserved (7:3) */ |
| UCHAR ucVideoInput0Info; /* Video Input 0 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) */ |
| UCHAR ucVideoInput1Info; /* Video Input 1 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) */ |
| UCHAR ucVideoInput2Info; /* Video Input 2 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) */ |
| UCHAR ucVideoInput3Info; /* Video Input 3 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) */ |
| UCHAR ucVideoInput4Info; /* Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) */ |
| } ATOM_MULTIMEDIA_CONFIG_INFO; |
| /****************************************************************************/ |
| /* Structures used in FirmwareInfoTable */ |
| /****************************************************************************/ |
| /* usBIOSCapability Defintion: */ |
| /* Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted; */ |
| /* Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported; */ |
| /* Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported; */ |
| /* Others: Reserved */ |
| #define ATOM_BIOS_INFO_ATOM_FIRMWARE_POSTED 0x0001 |
| #define ATOM_BIOS_INFO_DUAL_CRTC_SUPPORT 0x0002 |
| #define ATOM_BIOS_INFO_EXTENDED_DESKTOP_SUPPORT 0x0004 |
| #define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT 0x0008 |
| #define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT 0x0010 |
| #define ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU 0x0020 |
| #define ATOM_BIOS_INFO_WMI_SUPPORT 0x0040 |
| #define ATOM_BIOS_INFO_PPMODE_ASSIGNGED_BY_SYSTEM 0x0080 |
| #define ATOM_BIOS_INFO_HYPERMEMORY_SUPPORT 0x0100 |
| #define ATOM_BIOS_INFO_HYPERMEMORY_SIZE_MASK 0x1E00 |
| #define ATOM_BIOS_INFO_VPOST_WITHOUT_FIRST_MODE_SET 0x2000 |
| #define ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE 0x4000 |
| #ifndef _H2INC |
| /* Please don't add or expand this bitfield structure below, this one will retire soon.! */ |
| typedef struct _ATOM_FIRMWARE_CAPABILITY { |
| #if ATOM_BIG_ENDIAN |
| USHORT Reserved:3; |
| USHORT HyperMemory_Size:4; |
| USHORT HyperMemory_Support:1; |
| USHORT PPMode_Assigned:1; |
| USHORT WMI_SUPPORT:1; |
| USHORT GPUControlsBL:1; |
| USHORT EngineClockSS_Support:1; |
| USHORT MemoryClockSS_Support:1; |
| USHORT ExtendedDesktopSupport:1; |
| USHORT DualCRTC_Support:1; |
| USHORT FirmwarePosted:1; |
| #else |
| USHORT FirmwarePosted:1; |
| USHORT DualCRTC_Support:1; |
| USHORT ExtendedDesktopSupport:1; |
| USHORT MemoryClockSS_Support:1; |
| USHORT EngineClockSS_Support:1; |
| USHORT GPUControlsBL:1; |
| USHORT WMI_SUPPORT:1; |
| USHORT PPMode_Assigned:1; |
| USHORT HyperMemory_Support:1; |
| USHORT HyperMemory_Size:4; |
| USHORT Reserved:3; |
| #endif |
| } ATOM_FIRMWARE_CAPABILITY; |
| typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS { |
| ATOM_FIRMWARE_CAPABILITY sbfAccess; |
| USHORT susAccess; |
| } ATOM_FIRMWARE_CAPABILITY_ACCESS; |
| #else |
| typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS { |
| USHORT susAccess; |
| } ATOM_FIRMWARE_CAPABILITY_ACCESS; |
| #endif |
| typedef struct _ATOM_FIRMWARE_INFO { |
| ATOM_COMMON_TABLE_HEADER sHeader; |
| ULONG ulFirmwareRevision; |
| ULONG ulDefaultEngineClock; /* In 10Khz unit */ |
| ULONG ulDefaultMemoryClock; /* In 10Khz unit */ |
| ULONG ulDriverTargetEngineClock; /* In 10Khz unit */ |
| ULONG ulDriverTargetMemoryClock; /* In 10Khz unit */ |
| ULONG ulMaxEngineClockPLL_Output; /* In 10Khz unit */ |
| ULONG ulMaxMemoryClockPLL_Output; /* In 10Khz unit */ |
| ULONG ulMaxPixelClockPLL_Output; /* In 10Khz unit */ |
| ULONG ulASICMaxEngineClock; /* In 10Khz unit */ |
| ULONG ulASICMaxMemoryClock; /* In 10Khz unit */ |
| UCHAR ucASICMaxTemperature; |
| UCHAR ucPadding[3]; /* Don't use them */ |
| ULONG aulReservedForBIOS[3]; /* Don't use them */ |
| USHORT usMinEngineClockPLL_Input; /* In 10Khz unit */ |
| USHORT usMaxEngineClockPLL_Input; /* In 10Khz unit */ |
| USHORT usMinEngineClockPLL_Output; /* In 10Khz unit */ |
| USHORT usMinMemoryClockPLL_Input; /* In 10Khz unit */ |
| USHORT usMaxMemoryClockPLL_Input; /* In 10Khz unit */ |
| USHORT usMinMemoryClockPLL_Output; /* In 10Khz unit */ |
| USHORT usMaxPixelClock; /* In 10Khz unit, Max. Pclk */ |
| USHORT usMinPixelClockPLL_Input; /* In 10Khz unit */ |
| USHORT usMaxPixelClockPLL_Input; /* In 10Khz unit */ |
| USHORT usMinPixelClockPLL_Output; /* In 10Khz unit, the definitions above can't change!!! */ |
| ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; |
| USHORT usReferenceClock; /* In 10Khz unit */ |
| USHORT usPM_RTS_Location; /* RTS PM4 starting location in ROM in 1Kb unit */ |
| UCHAR ucPM_RTS_StreamSize; /* RTS PM4 packets in Kb unit */ |
| UCHAR ucDesign_ID; /* Indicate what is the board design */ |
| UCHAR ucMemoryModule_ID; /* Indicate what is the board design */ |
| } ATOM_FIRMWARE_INFO; |
| typedef struct _ATOM_FIRMWARE_INFO_V1_2 { |
| ATOM_COMMON_TABLE_HEADER sHeader; |
| ULONG ulFirmwareRevision; |
| ULONG ulDefaultEngineClock; /* In 10Khz unit */ |
| ULONG ulDefaultMemoryClock; /* In 10Khz unit */ |
| ULONG ulDriverTargetEngineClock; /* In 10Khz unit */ |
| ULONG ulDriverTargetMemoryClock; /* In 10Khz unit */ |
| ULONG ulMaxEngineClockPLL_Output; /* In 10Khz unit */ |
| ULONG ulMaxMemoryClockPLL_Output; /* In 10Khz unit */ |
| ULONG ulMaxPixelClockPLL_Output; /* In 10Khz unit */ |
| ULONG ulASICMaxEngineClock; /* In 10Khz unit */ |
| ULONG ulASICMaxMemoryClock; /* In 10Khz unit */ |
| UCHAR ucASICMaxTemperature; |
| UCHAR ucMinAllowedBL_Level; |
| UCHAR ucPadding[2]; /* Don't use them */ |
| ULONG aulReservedForBIOS[2]; /* Don't use them */ |
| ULONG ulMinPixelClockPLL_Output; /* In 10Khz unit */ |
| USHORT usMinEngineClockPLL_Input; /* In 10Khz unit */ |
| USHORT usMaxEngineClockPLL_Input; /* In 10Khz unit */ |
| USHORT usMinEngineClockPLL_Output; /* In 10Khz unit */ |
| USHORT usMinMemoryClockPLL_Input; /* In 10Khz unit */ |
| USHORT usMaxMemoryClockPLL_Input; /* In 10Khz unit */ |
| USHORT usMinMemoryClockPLL_Output; /* In 10Khz unit */ |
| USHORT usMaxPixelClock; /* In 10Khz unit, Max. Pclk */ |
| USHORT usMinPixelClockPLL_Input; /* In 10Khz unit */ |
| USHORT usMaxPixelClockPLL_Input; /* In 10Khz unit */ |
| USHORT usMinPixelClockPLL_Output; /* In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output */ |
| ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; |
| USHORT usReferenceClock; /* In 10Khz unit */ |
| USHORT usPM_RTS_Location; /* RTS PM4 starting location in ROM in 1Kb unit */ |
| UCHAR ucPM_RTS_StreamSize; /* RTS PM4 packets in Kb unit */ |
| UCHAR ucDesign_ID; /* Indicate what is the board design */ |
| UCHAR ucMemoryModule_ID; /* Indicate what is the board design */ |
| } ATOM_FIRMWARE_INFO_V1_2; |
| typedef struct _ATOM_FIRMWARE_INFO_V1_3 { |
| ATOM_COMMON_TABLE_HEADER sHeader; |
| ULONG ulFirmwareRevision; |
| ULONG ulDefaultEngineClock; /* In 10Khz unit */ |
| ULONG ulDefaultMemoryClock; /* In 10Khz unit */ |
| ULONG ulDriverTargetEngineClock; /* In 10Khz unit */ |
| ULONG ulDriverTargetMemoryClock; /* In 10Khz unit */ |
| ULONG ulMaxEngineClockPLL_Output; /* In 10Khz unit */ |
| ULONG ulMaxMemoryClockPLL_Output; /* In 10Khz unit */ |
| ULONG ulMaxPixelClockPLL_Output; /* In 10Khz unit */ |
| ULONG ulASICMaxEngineClock; /* In 10Khz unit */ |
| ULONG ulASICMaxMemoryClock; /* In 10Khz unit */ |
| UCHAR ucASICMaxTemperature; |
| UCHAR ucMinAllowedBL_Level; |
| UCHAR ucPadding[2]; /* Don't use them */ |
| ULONG aulReservedForBIOS; /* Don't use them */ |
| ULONG ul3DAccelerationEngineClock; /* In 10Khz unit */ |
| ULONG ulMinPixelClockPLL_Output; /* In 10Khz unit */ |
| USHORT usMinEngineClockPLL_Input; /* In 10Khz unit */ |
| USHORT usMaxEngineClockPLL_Input; /* In 10Khz unit */ |
| USHORT usMinEngineClockPLL_Output; /* In 10Khz unit */ |
| USHORT usMinMemoryClockPLL_Input; /* In 10Khz unit */ |
| USHORT usMaxMemoryClockPLL_Input; /* In 10Khz unit */ |
| USHORT usMinMemoryClockPLL_Output; /* In 10Khz unit */ |
| USHORT usMaxPixelClock; /* In 10Khz unit, Max. Pclk */ |
| USHORT usMinPixelClockPLL_Input; /* In 10Khz unit */ |
| USHORT usMaxPixelClockPLL_Input; /* In 10Khz unit */ |
| USHORT usMinPixelClockPLL_Output; /* In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output */ |
| ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; |
| USHORT usReferenceClock; /* In 10Khz unit */ |
| USHORT usPM_RTS_Location; /* RTS PM4 starting location in ROM in 1Kb unit */ |
| UCHAR ucPM_RTS_StreamSize; /* RTS PM4 packets in Kb unit */ |
| UCHAR ucDesign_ID; /* Indicate what is the board design */ |
| UCHAR ucMemoryModule_ID; /* Indicate what is the board design */ |
| } ATOM_FIRMWARE_INFO_V1_3; |
| typedef struct _ATOM_FIRMWARE_INFO_V1_4 { |
| ATOM_COMMON_TABLE_HEADER sHeader; |
| ULONG ulFirmwareRevision; |
| ULONG ulDefaultEngineClock; /* In 10Khz unit */ |
| ULONG ulDefaultMemoryClock; /* In 10Khz unit */ |
| ULONG ulDriverTargetEngineClock; /* In 10Khz unit */ |
| ULONG ulDriverTargetMemoryClock; /* In 10Khz unit */ |
| ULONG ulMaxEngineClockPLL_Output; /* In 10Khz unit */ |
| ULONG ulMaxMemoryClockPLL_Output; /* In 10Khz unit */ |
| ULONG ulMaxPixelClockPLL_Output; /* In 10Khz unit */ |
| ULONG ulASICMaxEngineClock; /* In 10Khz unit */ |
| ULONG ulASICMaxMemoryClock; /* In 10Khz unit */ |
| UCHAR ucASICMaxTemperature; |
| UCHAR ucMinAllowedBL_Level; |
| USHORT usBootUpVDDCVoltage; /* In MV unit */ |
| USHORT usLcdMinPixelClockPLL_Output; /* In MHz unit */ |
| USHORT usLcdMaxPixelClockPLL_Output; /* In MHz unit */ |
| ULONG ul3DAccelerationEngineClock; /* In 10Khz unit */ |
| ULONG ulMinPixelClockPLL_Output; /* In 10Khz unit */ |
| USHORT usMinEngineClockPLL_Input; /* In 10Khz unit */ |
| USHORT usMaxEngineClockPLL_Input; /* In 10Khz unit */ |
| USHORT usMinEngineClockPLL_Output; /* In 10Khz unit */ |
| USHORT usMinMemoryClockPLL_Input; /* In 10Khz unit */ |
| USHORT usMaxMemoryClockPLL_Input; /* In 10Khz unit */ |
| USHORT usMinMemoryClockPLL_Output; /* In 10Khz unit */ |
| USHORT usMaxPixelClock; /* In 10Khz unit, Max. Pclk */ |
| USHORT usMinPixelClockPLL_Input; /* In 10Khz unit */ |
| USHORT usMaxPixelClockPLL_Input; /* In 10Khz unit */ |
| USHORT usMinPixelClockPLL_Output; /* In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output */ |
| ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; |
| USHORT usReferenceClock; /* In 10Khz unit */ |
| USHORT usPM_RTS_Location; /* RTS PM4 starting location in ROM in 1Kb unit */ |
| UCHAR ucPM_RTS_StreamSize; /* RTS PM4 packets in Kb unit */ |
| UCHAR ucDesign_ID; /* Indicate what is the board design */ |
| UCHAR ucMemoryModule_ID; /* Indicate what is the board design */ |
| } ATOM_FIRMWARE_INFO_V1_4; |
| #define ATOM_FIRMWARE_INFO_LAST ATOM_FIRMWARE_INFO_V1_4 |
| /****************************************************************************/ |
| /* Structures used in IntegratedSystemInfoTable */ |
| /****************************************************************************/ |
| #define IGP_CAP_FLAG_DYNAMIC_CLOCK_EN 0x2 |
| #define IGP_CAP_FLAG_AC_CARD 0x4 |
| #define IGP_CAP_FLAG_SDVO_CARD 0x8 |
| #define IGP_CAP_FLAG_POSTDIV_BY_2_MODE 0x10 |
| typedef struct _ATOM_INTEGRATED_SYSTEM_INFO { |
| ATOM_COMMON_TABLE_HEADER sHeader; |
| ULONG ulBootUpEngineClock; /* in 10kHz unit */ |
| ULONG ulBootUpMemoryClock; /* in 10kHz unit */ |
| ULONG ulMaxSystemMemoryClock; /* in 10kHz unit */ |
| ULONG ulMinSystemMemoryClock; /* in 10kHz unit */ |
| UCHAR ucNumberOfCyclesInPeriodHi; |
| UCHAR ucLCDTimingSel; /* =0:not valid.!=0 sel this timing descriptor from LCD EDID. */ |
| USHORT usReserved1; |
| USHORT usInterNBVoltageLow; /* An intermidiate PMW value to set the voltage */ |
| USHORT usInterNBVoltageHigh; /* Another intermidiate PMW value to set the voltage */ |
| ULONG ulReserved[2]; |
| USHORT usFSBClock; /* In MHz unit */ |
| USHORT usCapabilityFlag; /* Bit0=1 indicates the fake HDMI support,Bit1=0/1 for Dynamic clocking dis/enable */ |
| /* Bit[3:2]== 0:No PCIE card, 1:AC card, 2:SDVO card */ |
| /* Bit[4]==1: P/2 mode, ==0: P/1 mode */ |
| USHORT usPCIENBCfgReg7; /* bit[7:0]=MUX_Sel, bit[9:8]=MUX_SEL_LEVEL2, bit[10]=Lane_Reversal */ |
| USHORT usK8MemoryClock; /* in MHz unit */ |
| USHORT usK8SyncStartDelay; /* in 0.01 us unit */ |
| USHORT usK8DataReturnTime; /* in 0.01 us unit */ |
| UCHAR ucMaxNBVoltage; |
| UCHAR ucMinNBVoltage; |
| UCHAR ucMemoryType; /* [7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is reserved */ |
| UCHAR ucNumberOfCyclesInPeriod; /* CG.FVTHROT_PWM_CTRL_REG0.NumberOfCyclesInPeriod */ |
| UCHAR ucStartingPWM_HighTime; /* CG.FVTHROT_PWM_CTRL_REG0.StartingPWM_HighTime */ |
| UCHAR ucHTLinkWidth; /* 16 bit vs. 8 bit */ |
| UCHAR ucMaxNBVoltageHigh; |
| UCHAR ucMinNBVoltageHigh; |
| } ATOM_INTEGRATED_SYSTEM_INFO; |
| /* Explanation on entries in ATOM_INTEGRATED_SYSTEM_INFO |
| ulBootUpMemoryClock: For Intel IGP,it's the UMA system memory clock |
| For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock |
| ulMaxSystemMemoryClock: For Intel IGP,it's the Max freq from memory SPD if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 |
| For AMD IGP,for now this can be 0 |
| ulMinSystemMemoryClock: For Intel IGP,it's 133MHz if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 |
| For AMD IGP,for now this can be 0 |
| usFSBClock: For Intel IGP,it's FSB Freq |
| For AMD IGP,it's HT Link Speed |
| usK8MemoryClock: For AMD IGP only. For RevF CPU, set it to 200 |
| usK8SyncStartDelay: For AMD IGP only. Memory access latency in K8, required for watermark calculation |
| usK8DataReturnTime: For AMD IGP only. Memory access latency in K8, required for watermark calculation |
| VC:Voltage Control |
| ucMaxNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all. |
| ucMinNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all. |
| ucNumberOfCyclesInPeriod: Indicate how many cycles when PWM duty is 100%. low 8 bits of the value. |
| ucNumberOfCyclesInPeriodHi: Indicate how many cycles when PWM duty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise set it 0 |
| ucMaxNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all. |
| ucMinNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all. |
| usInterNBVoltageLow: Voltage regulator dependent PWM value. The value makes the the voltage >=Min NB voltage but <=InterNBVoltageHigh. Set this to 0x0000 if VC without PWM or no VC at all. |
| usInterNBVoltageHigh: Voltage regulator dependent PWM value. The value makes the the voltage >=InterNBVoltageLow but <=Max NB voltage.Set this to 0x0000 if VC without PWM or no VC at all. |
| */ |
| /* |
| The following IGP table is introduced from RS780, which is supposed to be put by SBIOS in FB before IGP VBIOS starts VPOST; |
| Then VBIOS will copy the whole structure to its image so all GPU SW components can access this data structure to get whatever they need. |
| The enough reservation should allow us to never change table revisions. Whenever needed, a GPU SW component can use reserved portion for new data entries. |
| SW components can access the IGP system infor structure in the same way as before |
| */ |
| typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 { |
| ATOM_COMMON_TABLE_HEADER sHeader; |
| ULONG ulBootUpEngineClock; /* in 10kHz unit */ |
| ULONG ulReserved1[2]; /* must be 0x0 for the reserved */ |
| ULONG ulBootUpUMAClock; /* in 10kHz unit */ |
| ULONG ulBootUpSidePortClock; /* in 10kHz unit */ |
| ULONG ulMinSidePortClock; /* in 10kHz unit */ |
| ULONG ulReserved2[6]; /* must be 0x0 for the reserved */ |
| ULONG ulSystemConfig; /* see explanation below */ |
| ULONG ulBootUpReqDisplayVector; |
| ULONG ulOtherDisplayMisc; |
| ULONG ulDDISlot1Config; |
| ULONG ulDDISlot2Config; |
| UCHAR ucMemoryType; /* [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved */ |
| UCHAR ucUMAChannelNumber; |
| UCHAR ucDockingPinBit; |
| UCHAR ucDockingPinPolarity; |
| ULONG ulDockingPinCFGInfo; |
| ULONG ulCPUCapInfo; |
| USHORT usNumberOfCyclesInPeriod; |
| USHORT usMaxNBVoltage; |
| USHORT usMinNBVoltage; |
| USHORT usBootUpNBVoltage; |
| ULONG ulHTLinkFreq; /* in 10Khz */ |
| USHORT usMinHTLinkWidth; |
| USHORT usMaxHTLinkWidth; |
| USHORT usUMASyncStartDelay; |
| USHORT usUMADataReturnTime; |
| USHORT usLinkStatusZeroTime; |
| USHORT usReserved; |
| ULONG ulHighVoltageHTLinkFreq; /* in 10Khz */ |
| ULONG ulLowVoltageHTLinkFreq; /* in 10Khz */ |
| USHORT usMaxUpStreamHTLinkWidth; |
| USHORT usMaxDownStreamHTLinkWidth; |
| USHORT usMinUpStreamHTLinkWidth; |
| USHORT usMinDownStreamHTLinkWidth; |
| ULONG ulReserved3[97]; /* must be 0x0 */ |
| } ATOM_INTEGRATED_SYSTEM_INFO_V2; |
| /* |
| ulBootUpEngineClock: Boot-up Engine Clock in 10Khz; |
| ulBootUpUMAClock: Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present |
| ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not present,this could be equal to or less than maximum supported Sideport memory clock |
| ulSystemConfig: |
| Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode; |
| Bit[1]=1: system boots up at AMD overdrived state or user customized mode. In this case, driver will just stick to this boot-up mode. No other PowerPlay state |
| =0: system boots up at driver control state. Power state depends on PowerPlay table. |
| Bit[2]=1: PWM method is used on NB voltage control. =0: GPIO method is used. |
| Bit[3]=1: Only one power state(Performance) will be supported. |
| =0: Multiple power states supported from PowerPlay table. |
| Bit[4]=1: CLMC is supported and enabled on current system. |
| =0: CLMC is not supported or enabled on current system. SBIOS need to support HT link/freq change through ATIF interface. |
| Bit[5]=1: Enable CDLW for all driver control power states. Max HT width is from SBIOS, while Min HT width is determined by display requirement. |
| =0: CDLW is disabled. If CLMC is enabled case, Min HT width will be set equal to Max HT width. If CLMC disabled case, Max HT width will be applied. |
| Bit[6]=1: High Voltage requested for all power states. In this case, voltage will be forced at 1.1v and powerplay table voltage drop/throttling request will be ignored. |
| =0: Voltage settings is determined by powerplay table. |
| Bit[7]=1: Enable CLMC as hybrid Mode. CDLD and CILR will be disabled in this case and we're using legacy C1E. This is workaround for CPU(Griffin) performance issue. |
| =0: Enable CLMC as regular mode, CDLD and CILR will be enabled. |
| ulBootUpReqDisplayVector: This dword is a bit vector indicates what display devices are requested during boot-up. Refer to ATOM_DEVICE_xxx_SUPPORT for the bit vector definitions. |
| ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion; |
| [7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are supported by the system. Refer to ucTVSuppportedStd definition; |
| ulDDISlot1Config: Describes the PCIE lane configuration on this DDI PCIE slot (ADD2 card) or connector (Mobile design). |
| [3:0] - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12) |
| [7:4] - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12) |
| [15:8] - Lane configuration attribute; |
| [23:16]- Connector type, possible value: |
| CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D |
| CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D |
| CONNECTOR_OBJECT_ID_HDMI_TYPE_A |
| CONNECTOR_OBJECT_ID_DISPLAYPORT |
| [31:24]- Reserved |
| ulDDISlot2Config: Same as Slot1. |
| ucMemoryType: SidePort memory type, set it to 0x0 when Sideport memory is not installed. Driver needs this info to change sideport memory clock. Not for display in CCC. |
| For IGP, Hypermemory is the only memory type showed in CCC. |
| ucUMAChannelNumber: how many channels for the UMA; |
| ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offset in CFG to read this pin |
| ucDockingPinBit: which bit in this register to read the pin status; |
| ucDockingPinPolarity:Polarity of the pin when docked; |
| ulCPUCapInfo: [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, other bits reserved for now and must be 0x0 |
| usNumberOfCyclesInPeriod:Indicate how many cycles when PWM duty is 100%. |
| usMaxNBVoltage:Max. voltage control value in either PWM or GPIO mode. |
| usMinNBVoltage:Min. voltage control value in either PWM or GPIO mode. |
| GPIO mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=0 |
| PWM mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=1 |
| GPU SW don't control mode: usMaxNBVoltage & usMinNBVoltage=0 and no care about ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE |
| usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value. |
| ulHTLinkFreq: Bootup HT link Frequency in 10Khz. |
| usMinHTLinkWidth: Bootup minimum HT link width. If CDLW disabled, this is equal to usMaxHTLinkWidth. |
| If CDLW enabled, both upstream and downstream width should be the same during bootup. |
| usMaxHTLinkWidth: Bootup maximum HT link width. If CDLW disabled, this is equal to usMinHTLinkWidth. |
| If CDLW enabled, both upstream and downstream width should be the same during bootup. |
| usUMASyncStartDelay: Memory access latency, required for watermark calculation |
| usUMADataReturnTime: Memory access latency, required for watermark calculation |
| usLinkStatusZeroTime:Memory access latency required for watermark calculation, set this to 0x0 for K8 CPU, set a proper value in 0.01 the unit of us |
| for Griffin or Greyhound. SBIOS needs to convert to actual time by: |
| if T0Ttime [5:4]=00b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.1us (0.0 to 1.5us) |
| if T0Ttime [5:4]=01b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.5us (0.0 to 7.5us) |
| if T0Ttime [5:4]=10b, then usLinkStatusZeroTime=T0Ttime [3:0]*2.0us (0.0 to 30us) |
| if T0Ttime [5:4]=11b, and T0Ttime [3:0]=0x0 to 0xa, then usLinkStatusZeroTime=T0Ttime [3:0]*20us (0.0 to 200us) |
| ulHighVoltageHTLinkFreq: HT link frequency for power state with low voltage. If boot up runs in HT1, this must be 0. |
| This must be less than or equal to ulHTLinkFreq(bootup frequency). |
| ulLowVoltageHTLinkFreq: HT link frequency for power state with low voltage or voltage scaling 1.0v~1.1v. If boot up runs in HT1, this must be 0. |
| This must be less than or equal to ulHighVoltageHTLinkFreq. |
| usMaxUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMaxHTLinkWidth. Not used for now. |
| usMaxDownStreamHTLinkWidth: same as above. |
| usMinUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMinHTLinkWidth. Not used for now. |
| usMinDownStreamHTLinkWidth: same as above. |
| */ |
| #define SYSTEM_CONFIG_POWEREXPRESS_ENABLE 0x00000001 |
| #define SYSTEM_CONFIG_RUN_AT_OVERDRIVE_ENGINE 0x00000002 |
| #define SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE 0x00000004 |
| #define SYSTEM_CONFIG_PERFORMANCE_POWERSTATE_ONLY 0x00000008 |
| #define SYSTEM_CONFIG_CLMC_ENABLED 0x00000010 |
| #define SYSTEM_CONFIG_CDLW_ENABLED 0x00000020 |
| #define SYSTEM_CONFIG_HIGH_VOLTAGE_REQUESTED 0x00000040 |
| #define SYSTEM_CONFIG_CLMC_HYBRID_MODE_ENABLED 0x00000080 |
| #define IGP_DDI_SLOT_LANE_CONFIG_MASK 0x000000FF |
| #define b0IGP_DDI_SLOT_LANE_MAP_MASK 0x0F |
| #define b0IGP_DDI_SLOT_DOCKING_LANE_MAP_MASK 0xF0 |
| #define b0IGP_DDI_SLOT_CONFIG_LANE_0_3 0x01 |
| #define b0IGP_DDI_SLOT_CONFIG_LANE_4_7 0x02 |
| #define b0IGP_DDI_SLOT_CONFIG_LANE_8_11 0x04 |
| #define b0IGP_DDI_SLOT_CONFIG_LANE_12_15 0x08 |
| #define IGP_DDI_SLOT_ATTRIBUTE_MASK 0x0000FF00 |
| #define IGP_DDI_SLOT_CONFIG_REVERSED 0x00000100 |
| #define b1IGP_DDI_SLOT_CONFIG_REVERSED 0x01 |
| #define IGP_DDI_SLOT_CONNECTOR_TYPE_MASK 0x00FF0000 |
| #define ATOM_CRT_INT_ENCODER1_INDEX 0x00000000 |
| #define ATOM_LCD_INT_ENCODER1_INDEX 0x00000001 |
| #define ATOM_TV_INT_ENCODER1_INDEX 0x00000002 |
| #define ATOM_DFP_INT_ENCODER1_INDEX 0x00000003 |
| #define ATOM_CRT_INT_ENCODER2_INDEX 0x00000004 |
| #define ATOM_LCD_EXT_ENCODER1_INDEX 0x00000005 |
| #define ATOM_TV_EXT_ENCODER1_INDEX 0x00000006 |
| #define ATOM_DFP_EXT_ENCODER1_INDEX 0x00000007 |
| #define ATOM_CV_INT_ENCODER1_INDEX 0x00000008 |
| #define ATOM_DFP_INT_ENCODER2_INDEX 0x00000009 |
| #define ATOM_CRT_EXT_ENCODER1_INDEX 0x0000000A |
| #define ATOM_CV_EXT_ENCODER1_INDEX 0x0000000B |
| #define ATOM_DFP_INT_ENCODER3_INDEX 0x0000000C |
| #define ATOM_DFP_INT_ENCODER4_INDEX 0x0000000D |
| /* define ASIC internal encoder id ( bit vector ) */ |
| #define ASIC_INT_DAC1_ENCODER_ID 0x00 |
| #define ASIC_INT_TV_ENCODER_ID 0x02 |
| #define ASIC_INT_DIG1_ENCODER_ID 0x03 |
| #define ASIC_INT_DAC2_ENCODER_ID 0x04 |
| #define ASIC_EXT_TV_ENCODER_ID 0x06 |
| #define ASIC_INT_DVO_ENCODER_ID 0x07 |
| #define ASIC_INT_DIG2_ENCODER_ID 0x09 |
| #define ASIC_EXT_DIG_ENCODER_ID 0x05 |
| /* define Encoder attribute */ |
| #define ATOM_ANALOG_ENCODER 0 |
| #define ATOM_DIGITAL_ENCODER 1 |
| #define ATOM_DEVICE_CRT1_INDEX 0x00000000 |
| #define ATOM_DEVICE_LCD1_INDEX 0x00000001 |
| #define ATOM_DEVICE_TV1_INDEX 0x00000002 |
| #define ATOM_DEVICE_DFP1_INDEX 0x00000003 |
| #define ATOM_DEVICE_CRT2_INDEX 0x00000004 |
| #define ATOM_DEVICE_LCD2_INDEX 0x00000005 |
| #define ATOM_DEVICE_TV2_INDEX 0x00000006 |
| #define ATOM_DEVICE_DFP2_INDEX 0x00000007 |
| #define ATOM_DEVICE_CV_INDEX 0x00000008 |
| #define ATOM_DEVICE_DFP3_INDEX 0x00000009 |
| #define ATOM_DEVICE_DFP4_INDEX 0x0000000A |
| #define ATOM_DEVICE_DFP5_INDEX 0x0000000B |
| #define ATOM_DEVICE_RESERVEDC_INDEX 0x0000000C |
| #define ATOM_DEVICE_RESERVEDD_INDEX 0x0000000D |
| #define ATOM_DEVICE_RESERVEDE_INDEX 0x0000000E |
| #define ATOM_DEVICE_RESERVEDF_INDEX 0x0000000F |
| #define ATOM_MAX_SUPPORTED_DEVICE_INFO (ATOM_DEVICE_DFP3_INDEX+1) |
| #define ATOM_MAX_SUPPORTED_DEVICE_INFO_2 ATOM_MAX_SUPPORTED_DEVICE_INFO |
| #define ATOM_MAX_SUPPORTED_DEVICE_INFO_3 (ATOM_DEVICE_DFP5_INDEX + 1) |
| #define ATOM_MAX_SUPPORTED_DEVICE (ATOM_DEVICE_RESERVEDF_INDEX+1) |
| #define ATOM_DEVICE_CRT1_SUPPORT (0x1L << ATOM_DEVICE_CRT1_INDEX) |
| #define ATOM_DEVICE_LCD1_SUPPORT (0x1L << ATOM_DEVICE_LCD1_INDEX) |
| #define ATOM_DEVICE_TV1_SUPPORT (0x1L << ATOM_DEVICE_TV1_INDEX) |
| #define ATOM_DEVICE_DFP1_SUPPORT (0x1L << ATOM_DEVICE_DFP1_INDEX) |
| #define ATOM_DEVICE_CRT2_SUPPORT (0x1L << ATOM_DEVICE_CRT2_INDEX) |
| #define ATOM_DEVICE_LCD2_SUPPORT (0x1L << ATOM_DEVICE_LCD2_INDEX) |
| #define ATOM_DEVICE_TV2_SUPPORT (0x1L << ATOM_DEVICE_TV2_INDEX) |
| #define ATOM_DEVICE_DFP2_SUPPORT (0x1L << ATOM_DEVICE_DFP2_INDEX) |
| #define ATOM_DEVICE_CV_SUPPORT (0x1L << ATOM_DEVICE_CV_INDEX) |
| #define ATOM_DEVICE_DFP3_SUPPORT (0x1L << ATOM_DEVICE_DFP3_INDEX) |
| #define ATOM_DEVICE_DFP4_SUPPORT (0x1L << ATOM_DEVICE_DFP4_INDEX ) |
| #define ATOM_DEVICE_DFP5_SUPPORT (0x1L << ATOM_DEVICE_DFP5_INDEX) |
| #define ATOM_DEVICE_CRT_SUPPORT \ |
| (ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_CRT2_SUPPORT) |
| #define ATOM_DEVICE_DFP_SUPPORT \ |
| (ATOM_DEVICE_DFP1_SUPPORT | ATOM_DEVICE_DFP2_SUPPORT | \ |
| ATOM_DEVICE_DFP3_SUPPORT | ATOM_DEVICE_DFP4_SUPPORT | \ |
| ATOM_DEVICE_DFP5_SUPPORT) |
| #define ATOM_DEVICE_TV_SUPPORT \ |
| (ATOM_DEVICE_TV1_SUPPORT | ATOM_DEVICE_TV2_SUPPORT) |
| #define ATOM_DEVICE_LCD_SUPPORT \ |
| (ATOM_DEVICE_LCD1_SUPPORT | ATOM_DEVICE_LCD2_SUPPORT) |
| #define ATOM_DEVICE_CONNECTOR_TYPE_MASK 0x000000F0 |
| #define ATOM_DEVICE_CONNECTOR_TYPE_SHIFT 0x00000004 |
| #define ATOM_DEVICE_CONNECTOR_VGA 0x00000001 |
| #define ATOM_DEVICE_CONNECTOR_DVI_I 0x00000002 |
| #define ATOM_DEVICE_CONNECTOR_DVI_D 0x00000003 |
| #define ATOM_DEVICE_CONNECTOR_DVI_A 0x00000004 |
| #define ATOM_DEVICE_CONNECTOR_SVIDEO 0x00000005 |
| #define ATOM_DEVICE_CONNECTOR_COMPOSITE 0x00000006 |
| #define ATOM_DEVICE_CONNECTOR_LVDS 0x00000007 |
| #define ATOM_DEVICE_CONNECTOR_DIGI_LINK 0x00000008 |
| #define ATOM_DEVICE_CONNECTOR_SCART 0x00000009 |
| #define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_A 0x0000000A |
| #define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_B 0x0000000B |
| #define ATOM_DEVICE_CONNECTOR_CASE_1 0x0000000E |
| #define ATOM_DEVICE_CONNECTOR_DISPLAYPORT 0x0000000F |
| #define ATOM_DEVICE_DAC_INFO_MASK 0x0000000F |
| #define ATOM_DEVICE_DAC_INFO_SHIFT 0x00000000 |
| #define ATOM_DEVICE_DAC_INFO_NODAC 0x00000000 |
| #define ATOM_DEVICE_DAC_INFO_DACA 0x00000001 |
| #define ATOM_DEVICE_DAC_INFO_DACB 0x00000002 |
| #define ATOM_DEVICE_DAC_INFO_EXDAC 0x00000003 |
| #define ATOM_DEVICE_I2C_ID_NOI2C 0x00000000 |
| #define ATOM_DEVICE_I2C_LINEMUX_MASK 0x0000000F |
| #define ATOM_DEVICE_I2C_LINEMUX_SHIFT 0x00000000 |
| #define ATOM_DEVICE_I2C_ID_MASK 0x00000070 |
| #define ATOM_DEVICE_I2C_ID_SHIFT 0x00000004 |
| #define ATOM_DEVICE_I2C_ID_IS_FOR_NON_MM_USE 0x00000001 |
| #define ATOM_DEVICE_I2C_ID_IS_FOR_MM_USE 0x00000002 |
| #define ATOM_DEVICE_I2C_ID_IS_FOR_SDVO_USE 0x00000003 /* For IGP RS600 */ |
| #define ATOM_DEVICE_I2C_ID_IS_FOR_DAC_SCL 0x00000004 /* For IGP RS690 */ |
| #define ATOM_DEVICE_I2C_HARDWARE_CAP_MASK 0x00000080 |
| #define ATOM_DEVICE_I2C_HARDWARE_CAP_SHIFT 0x00000007 |
| #define ATOM_DEVICE_USES_SOFTWARE_ASSISTED_I2C 0x00000000 |
| #define ATOM_DEVICE_USES_HARDWARE_ASSISTED_I2C 0x00000001 |
| /* usDeviceSupport: */ |
| /* Bits0 = 0 - no CRT1 support= 1- CRT1 is supported */ |
| /* Bit 1 = 0 - no LCD1 support= 1- LCD1 is supported */ |
| /* Bit 2 = 0 - no TV1 support= 1- TV1 is supported */ |
| /* Bit 3 = 0 - no DFP1 support= 1- DFP1 is supported */ |
| /* Bit 4 = 0 - no CRT2 support= 1- CRT2 is supported */ |
| /* Bit 5 = 0 - no LCD2 support= 1- LCD2 is supported */ |
| /* Bit 6 = 0 - no TV2 support= 1- TV2 is supported */ |
| /* Bit 7 = 0 - no DFP2 support= 1- DFP2 is supported */ |
| /* Bit 8 = 0 - no CV support= 1- CV is supported */ |
| /* Bit 9 = 0 - no DFP3 support= 1- DFP3 is supported */ |
| /* Byte1 (Supported Device Info) */ |
| /* Bit 0 = = 0 - no CV support= 1- CV is supported */ |
| /* */ |
| /* */ |
| /* ucI2C_ConfigID */ |
| /* [7:0] - I2C LINE Associate ID */ |
| /* = 0 - no I2C */ |
| /* [7] - HW_Cap = 1, [6:0]=HW assisted I2C ID(HW line selection) */ |
| /* = 0, [6:0]=SW assisted I2C ID */ |
| /* [6-4] - HW_ENGINE_ID = 1, HW engine for NON multimedia use */ |
| /* = 2, HW engine for Multimedia use */ |
| /* = 3-7 Reserved for future I2C engines */ |
| /* [3-0] - I2C_LINE_MUX = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C */ |
| typedef struct _ATOM_I2C_ID_CONFIG { |
| #if ATOM_BIG_ENDIAN |
| UCHAR bfHW_Capable:1; |
| UCHAR bfHW_EngineID:3; |
| UCHAR bfI2C_LineMux:4; |
| #else |
| UCHAR bfI2C_LineMux:4; |
| UCHAR bfHW_EngineID:3; |
| UCHAR bfHW_Capable:1; |
| #endif |
| } ATOM_I2C_ID_CONFIG; |
| typedef union _ATOM_I2C_ID_CONFIG_ACCESS { |
| ATOM_I2C_ID_CONFIG sbfAccess; |
| UCHAR ucAccess; |
| } ATOM_I2C_ID_CONFIG_ACCESS; |
| /****************************************************************************/ |
| /* Structure used in GPIO_I2C_InfoTable */ |
| /****************************************************************************/ |
| typedef struct _ATOM_GPIO_I2C_ASSIGMENT { |
| USHORT usClkMaskRegisterIndex; |
| USHORT usClkEnRegisterIndex; |
| USHORT usClkY_RegisterIndex; |
| USHORT usClkA_RegisterIndex; |
| USHORT usDataMaskRegisterIndex; |
| USHORT usDataEnRegisterIndex; |
| USHORT usDataY_RegisterIndex; |
| USHORT usDataA_RegisterIndex; |
| ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; |
| UCHAR ucClkMaskShift; |
| UCHAR ucClkEnShift; |
| UCHAR ucClkY_Shift; |
| UCHAR ucClkA_Shift; |
| UCHAR ucDataMaskShift; |
| UCHAR ucDataEnShift; |
| UCHAR ucDataY_Shift; |
| UCHAR ucDataA_Shift; |
| UCHAR ucReserved1; |
| UCHAR ucReserved2; |
| } ATOM_GPIO_I2C_ASSIGMENT; |
| typedef struct _ATOM_GPIO_I2C_INFO { |
| ATOM_COMMON_TABLE_HEADER sHeader; |
| ATOM_GPIO_I2C_ASSIGMENT asGPIO_Info[ATOM_MAX_SUPPORTED_DEVICE]; |
| } ATOM_GPIO_I2C_INFO; |
| /****************************************************************************/ |
| /* Common Structure used in other structures */ |
| /****************************************************************************/ |
| #ifndef _H2INC |
| /* Please don't add or expand this bitfield structure below, this one will retire soon.! */ |
| typedef struct _ATOM_MODE_MISC_INFO { |
| #if ATOM_BIG_ENDIAN |
| USHORT Reserved:6; |
| USHORT RGB888:1; |
| USHORT DoubleClock:1; |
| USHORT Interlace:1; |
| USHORT CompositeSync:1; |
| USHORT V_ReplicationBy2:1; |
| USHORT H_ReplicationBy2:1; |
| USHORT VerticalCutOff:1; |
| USHORT VSyncPolarity:1; /* 0=Active High, 1=Active Low */ |
| USHORT HSyncPolarity:1; /* 0=Active High, 1=Active Low */ |
| USHORT HorizontalCutOff:1; |
| #else |
| USHORT HorizontalCutOff:1; |
| USHORT HSyncPolarity:1; /* 0=Active High, 1=Active Low */ |
| USHORT VSyncPolarity:1; /* 0=Active High, 1=Active Low */ |
| USHORT VerticalCutOff:1; |
| USHORT H_ReplicationBy2:1; |
| USHORT V_ReplicationBy2:1; |
| USHORT CompositeSync:1; |
| USHORT Interlace:1; |
| USHORT DoubleClock:1; |
| USHORT RGB888:1; |
| USHORT Reserved:6; |
| #endif |
| } ATOM_MODE_MISC_INFO; |
| typedef union _ATOM_MODE_MISC_INFO_ACCESS { |
| ATOM_MODE_MISC_INFO sbfAccess; |
| USHORT usAccess; |
| } ATOM_MODE_MISC_INFO_ACCESS; |
| #else |
| typedef union _ATOM_MODE_MISC_INFO_ACCESS { |
| USHORT usAccess; |
| } ATOM_MODE_MISC_INFO_ACCESS; |
| #endif |
| /* usModeMiscInfo- */ |
| #define ATOM_H_CUTOFF 0x01 |
| #define ATOM_HSYNC_POLARITY 0x02 /* 0=Active High, 1=Active Low */ |
| #define ATOM_VSYNC_POLARITY 0x04 /* 0=Active High, 1=Active Low */ |
| #define ATOM_V_CUTOFF 0x08 |
| #define ATOM_H_REPLICATIONBY2 0x10 |
| #define ATOM_V_REPLICATIONBY2 0x20 |
| #define ATOM_COMPOSITESYNC 0x40 |
| #define ATOM_INTERLACE 0x80 |
| #define ATOM_DOUBLE_CLOCK_MODE 0x100 |
| #define ATOM_RGB888_MODE 0x200 |
| /* usRefreshRate- */ |
| #define ATOM_REFRESH_43 43 |
| #define ATOM_REFRESH_47 47 |
| #define ATOM_REFRESH_56 56 |
| #define ATOM_REFRESH_60 60 |
| #define ATOM_REFRESH_65 65 |
| #define ATOM_REFRESH_70 70 |
| #define ATOM_REFRESH_72 72 |
| #define ATOM_REFRESH_75 75 |
| #define ATOM_REFRESH_85 85 |
| /* ATOM_MODE_TIMING data are exactly the same as VESA timing data. */ |
| /* Translation from EDID to ATOM_MODE_TIMING, use the following formula. */ |
| /* */ |
| /* VESA_HTOTAL = VESA_ACTIVE + 2* VESA_BORDER + VESA_BLANK */ |
| /* = EDID_HA + EDID_HBL */ |
| /* VESA_HDISP = VESA_ACTIVE = EDID_HA */ |
| /* VESA_HSYNC_START = VESA_ACTIVE + VESA_BORDER + VESA_FRONT_PORCH */ |
| /* = EDID_HA + EDID_HSO */ |
| /* VESA_HSYNC_WIDTH = VESA_HSYNC_TIME = EDID_HSPW */ |
| /* VESA_BORDER = EDID_BORDER */ |
| /****************************************************************************/ |
| /* Structure used in SetCRTC_UsingDTDTimingTable */ |
| /****************************************************************************/ |
| typedef struct _SET_CRTC_USING_DTD_TIMING_PARAMETERS { |
| USHORT usH_Size; |
| USHORT usH_Blanking_Time; |
| USHORT usV_Size; |
| USHORT usV_Blanking_Time; |
| USHORT usH_SyncOffset; |
| USHORT usH_SyncWidth; |
| USHORT usV_SyncOffset; |
| USHORT usV_SyncWidth; |
| ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; |
| UCHAR ucH_Border; /* From DFP EDID */ |
| UCHAR ucV_Border; |
| UCHAR ucCRTC; /* ATOM_CRTC1 or ATOM_CRTC2 */ |
| UCHAR ucPadding[3]; |
| } SET_CRTC_USING_DTD_TIMING_PARAMETERS; |
| /****************************************************************************/ |
| /* Structure used in SetCRTC_TimingTable */ |
| /****************************************************************************/ |
| typedef struct _SET_CRTC_TIMING_PARAMETERS { |
| USHORT usH_Total; /* horizontal total */ |
| USHORT usH_Disp; /* horizontal display */ |
| USHORT usH_SyncStart; /* horozontal Sync start */ |
| USHORT usH_SyncWidth; /* horizontal Sync width */ |
| USHORT usV_Total; /* vertical total */ |
| USHORT usV_Disp; /* vertical display */ |
| USHORT usV_SyncStart; /* vertical Sync start */ |
| USHORT usV_SyncWidth; /* vertical Sync width */ |
| ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; |
| UCHAR ucCRTC; /* ATOM_CRTC1 or ATOM_CRTC2 */ |
| UCHAR ucOverscanRight; /* right */ |
| UCHAR ucOverscanLeft; /* left */ |
| UCHAR ucOverscanBottom; /* bottom */ |
| UCHAR ucOverscanTop; /* top */ |
| UCHAR ucReserved; |
| } SET_CRTC_TIMING_PARAMETERS; |
| #define SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION SET_CRTC_TIMING_PARAMETERS |
| /****************************************************************************/ |
| /* Structure used in StandardVESA_TimingTable */ |
| /* AnalogTV_InfoTable */ |
| /* ComponentVideoInfoTable */ |
| /****************************************************************************/ |
| typedef struct _ATOM_MODE_TIMING { |
| USHORT usCRTC_H_Total; |
| USHORT usCRTC_H_Disp; |
| USHORT usCRTC_H_SyncStart; |
| USHORT usCRTC_H_SyncWidth; |
| USHORT usCRTC_V_Total; |
| USHORT usCRTC_V_Disp; |
| USHORT usCRTC_V_SyncStart; |
| USHORT usCRTC_V_SyncWidth; |
| USHORT usPixelClock; /* in 10Khz unit */ |
| ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; |
| USHORT usCRTC_OverscanRight; |
| USHORT usCRTC_OverscanLeft; |
| USHORT usCRTC_OverscanBottom; |
| USHORT usCRTC_OverscanTop; |
| USHORT usReserve; |
| UCHAR ucInternalModeNumber; |
| UCHAR ucRefreshRate; |
| } ATOM_MODE_TIMING; |
| typedef struct _ATOM_DTD_FORMAT { |
| USHORT usPixClk; |
| USHORT usHActive; |
| USHORT usHBlanking_Time; |
| USHORT usVActive; |
| USHORT usVBlanking_Time; |
| USHORT usHSyncOffset; |
| USHORT usHSyncWidth; |
| USHORT usVSyncOffset; |
| USHORT usVSyncWidth; |
| USHORT usImageHSize; |
| USHORT usImageVSize; |
| UCHAR ucHBorder; |
| UCHAR ucVBorder; |
| ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; |
| UCHAR ucInternalModeNumber; |
| UCHAR ucRefreshRate; |
| } ATOM_DTD_FORMAT; |
| /****************************************************************************/ |
| /* Structure used in LVDS_InfoTable */ |
| /* * Need a document to describe this table */ |
| /****************************************************************************/ |
| #define SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 |
| #define SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 |
| #define SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 |
| #define SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 |
| /* Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12. */ |
| /* Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL */ |
| #define LCDPANEL_CAP_READ_EDID 0x1 |
| /* ucTableFormatRevision=1 */ |
| /* ucTableContentRevision=1 */ |
| typedef struct _ATOM_LVDS_INFO { |
| ATOM_COMMON_TABLE_HEADER sHeader; |
| ATOM_DTD_FORMAT sLCDTiming; |
| USHORT usModePatchTableOffset; |
| USHORT usSupportedRefreshRate; /* Refer to panel info table in ATOMBIOS extension Spec. */ |
| USHORT usOffDelayInMs; |
| UCHAR ucPowerSequenceDigOntoDEin10Ms; |
| UCHAR ucPowerSequenceDEtoBLOnin10Ms; |
| UCHAR ucLVDS_Misc; /* Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level} */ |
| /* Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} */ |
| /* Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled} */ |
| /* Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled} */ |
| UCHAR ucPanelDefaultRefreshRate; |
| UCHAR ucPanelIdentification; |
| UCHAR ucSS_Id; |
| } ATOM_LVDS_INFO; |
| /* ucTableFormatRevision=1 */ |
| /* ucTableContentRevision=2 */ |
| typedef struct _ATOM_LVDS_INFO_V12 { |
| ATOM_COMMON_TABLE_HEADER sHeader; |
| ATOM_DTD_FORMAT sLCDTiming; |
| USHORT usExtInfoTableOffset; |
| USHORT usSupportedRefreshRate; /* Refer to panel info table in ATOMBIOS extension Spec. */ |
| USHORT usOffDelayInMs; |
| UCHAR ucPowerSequenceDigOntoDEin10Ms; |
| UCHAR ucPowerSequenceDEtoBLOnin10Ms; |
| UCHAR ucLVDS_Misc; /* Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level} */ |
| /* Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} */ |
| /* Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled} */ |
| /* Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled} */ |
| UCHAR ucPanelDefaultRefreshRate; |
| UCHAR ucPanelIdentification; |
| UCHAR ucSS_Id; |
| USHORT usLCDVenderID; |
| USHORT usLCDProductID; |
| UCHAR ucLCDPanel_SpecialHandlingCap; |
| UCHAR ucPanelInfoSize; /* start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable */ |
| UCHAR ucReserved[2]; |
| } ATOM_LVDS_INFO_V12; |
| #define ATOM_LVDS_INFO_LAST ATOM_LVDS_INFO_V12 |
| typedef struct _ATOM_PATCH_RECORD_MODE { |
| UCHAR ucRecordType; |
| USHORT usHDisp; |
| USHORT usVDisp; |
| } ATOM_PATCH_RECORD_MODE; |
| typedef struct _ATOM_LCD_RTS_RECORD { |
| UCHAR ucRecordType; |
| UCHAR ucRTSValue; |
| } ATOM_LCD_RTS_RECORD; |
| /* !! If the record below exits, it shoud always be the first record for easy use in command table!!! */ |
| typedef struct _ATOM_LCD_MODE_CONTROL_CAP { |
| UCHAR ucRecordType; |
| USHORT usLCDCap; |
| } ATOM_LCD_MODE_CONTROL_CAP; |
| #define LCD_MODE_CAP_BL_OFF 1 |
| #define LCD_MODE_CAP_CRTC_OFF 2 |
| #define LCD_MODE_CAP_PANEL_OFF 4 |
| typedef struct _ATOM_FAKE_EDID_PATCH_RECORD { |
| UCHAR ucRecordType; |
| UCHAR ucFakeEDIDLength; |
| UCHAR ucFakeEDIDString[1]; /* This actually has ucFakeEdidLength elements. */ |
| } ATOM_FAKE_EDID_PATCH_RECORD; |
| typedef struct _ATOM_PANEL_RESOLUTION_PATCH_RECORD { |
| UCHAR ucRecordType; |
| USHORT usHSize; |
| USHORT usVSize; |
| } ATOM_PANEL_RESOLUTION_PATCH_RECORD; |
| #define LCD_MODE_PATCH_RECORD_MODE_TYPE 1 |
| #define LCD_RTS_RECORD_TYPE 2 |
| #define LCD_CAP_RECORD_TYPE 3 |
| #define LCD_FAKE_EDID_PATCH_RECORD_TYPE 4 |
| #define LCD_PANEL_RESOLUTION_RECORD_TYPE 5 |
| #define ATOM_RECORD_END_TYPE 0xFF |
| /****************************Spread Spectrum Info Table Definitions **********************/ |
| /* ucTableFormatRevision=1 */ |
| /* ucTableContentRevision=2 */ |
| typedef struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT { |
| USHORT usSpreadSpectrumPercentage; |
| UCHAR ucSpreadSpectrumType; /* Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD */ |
| UCHAR ucSS_Step; |
| UCHAR ucSS_Delay; |
| UCHAR ucSS_Id; |
| UCHAR ucRecommandedRef_Div; |
| UCHAR ucSS_Range; /* it was reserved for V11 */ |
| } ATOM_SPREAD_SPECTRUM_ASSIGNMENT; |
| #define ATOM_MAX_SS_ENTRY 16 |
| #define ATOM_DP_SS_ID1 0x0f1 /* SS modulation freq=30k */ |
| #define ATOM_DP_SS_ID2 0x0f2 /* SS modulation freq=33k */ |
| #define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000 |
| #define ATOM_SS_DOWN_SPREAD_MODE 0x00000000 |
| #define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001 |
| #define ATOM_SS_CENTRE_SPREAD_MODE 0x00000001 |
| #define ATOM_INTERNAL_SS_MASK 0x00000000 |
| #define ATOM_EXTERNAL_SS_MASK 0x00000002 |
| #define EXEC_SS_STEP_SIZE_SHIFT 2 |
| #define EXEC_SS_DELAY_SHIFT 4 |
| #define ACTIVEDATA_TO_BLON_DELAY_SHIFT 4 |
| typedef struct _ATOM_SPREAD_SPECTRUM_INFO { |
| ATOM_COMMON_TABLE_HEADER sHeader; |
| ATOM_SPREAD_SPECTRUM_ASSIGNMENT asSS_Info[ATOM_MAX_SS_ENTRY]; |
| } ATOM_SPREAD_SPECTRUM_INFO; |
| /****************************************************************************/ |
| /* Structure used in AnalogTV_InfoTable (Top level) */ |
| /****************************************************************************/ |
| /* ucTVBootUpDefaultStd definiton: */ |
| /* ATOM_TV_NTSC 1 */ |
| /* ATOM_TV_NTSCJ 2 */ |
| /* ATOM_TV_PAL 3 */ |
| /* ATOM_TV_PALM 4 */ |
| /* ATOM_TV_PALCN 5 */ |
| /* ATOM_TV_PALN 6 */ |
| /* ATOM_TV_PAL60 7 */ |
| /* ATOM_TV_SECAM 8 */ |
| /* ucTVSuppportedStd definition: */ |
| #define NTSC_SUPPORT 0x1 |
| #define NTSCJ_SUPPORT 0x2 |
| #define PAL_SUPPORT 0x4 |
| #define PALM_SUPPORT 0x8 |
| #define PALCN_SUPPORT 0x10 |
| #define PALN_SUPPORT 0x20 |
| #define PAL60_SUPPORT 0x40 |
| #define SECAM_SUPPORT 0x80 |
| #define MAX_SUPPORTED_TV_TIMING 2 |
| typedef struct _ATOM_ANALOG_TV_INFO { |
| ATOM_COMMON_TABLE_HEADER sHeader; |
| UCHAR ucTV_SupportedStandard; |
| UCHAR ucTV_BootUpDefaultStandard; |
| UCHAR ucExt_TV_ASIC_ID; |
| UCHAR ucExt_TV_ASIC_SlaveAddr; |
| /*ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING]; */ |
| ATOM_MODE_TIMING aModeTimings[MAX_SUPPORTED_TV_TIMING]; |
| } ATOM_ANALOG_TV_INFO; |
| /**************************************************************************/ |
| /* VRAM usage and their defintions */ |
| /* One chunk of VRAM used by Bios are for HWICON surfaces,EDID data. */ |
| /* Current Mode timing and Dail Timing and/or STD timing data EACH device. They can be broken down as below. */ |
| /* All the addresses below are the offsets from the frame buffer start.They all MUST be Dword aligned! */ |
| /* To driver: The physical address of this memory portion=mmFB_START(4K aligned)+ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR */ |
| /* To Bios: ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX */ |
| #ifndef VESA_MEMORY_IN_64K_BLOCK |
| #define VESA_MEMORY_IN_64K_BLOCK 0x100 /* 256*64K=16Mb (Max. VESA memory is 16Mb!) */ |
| #endif |
| #define ATOM_EDID_RAW_DATASIZE 256 /* In Bytes */ |
| #define ATOM_HWICON_SURFACE_SIZE 4096 /* In Bytes */ |
| #define ATOM_HWICON_INFOTABLE_SIZE 32 |
| #define MAX_DTD_MODE_IN_VRAM 6 |
| #define ATOM_DTD_MODE_SUPPORT_TBL_SIZE (MAX_DTD_MODE_IN_VRAM*28) /* 28= (SIZEOF ATOM_DTD_FORMAT) */ |
| #define ATOM_STD_MODE_SUPPORT_TBL_SIZE (32*8) /* 32 is a predefined number,8= (SIZEOF ATOM_STD_FORMAT) */ |
| #define DFP_ENCODER_TYPE_OFFSET 0x80 |
| #define DP_ENCODER_LANE_NUM_OFFSET 0x84 |
| #define DP_ENCODER_LINK_RATE_OFFSET 0x88 |
| #define ATOM_HWICON1_SURFACE_ADDR 0 |
| #define ATOM_HWICON2_SURFACE_ADDR (ATOM_HWICON1_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE) |
| #define ATOM_HWICON_INFOTABLE_ADDR (ATOM_HWICON2_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE) |
| #define ATOM_CRT1_EDID_ADDR (ATOM_HWICON_INFOTABLE_ADDR + ATOM_HWICON_INFOTABLE_SIZE) |
| #define ATOM_CRT1_DTD_MODE_TBL_ADDR (ATOM_CRT1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) |
| #define ATOM_CRT1_STD_MODE_TBL_ADDR (ATOM_CRT1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) |
| #define ATOM_LCD1_EDID_ADDR (ATOM_CRT1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) |
| #define ATOM_LCD1_DTD_MODE_TBL_ADDR (ATOM_LCD1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) |
| #define ATOM_LCD1_STD_MODE_TBL_ADDR (ATOM_LCD1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) |
| #define ATOM_TV1_DTD_MODE_TBL_ADDR (ATOM_LCD1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) |
| #define ATOM_DFP1_EDID_ADDR (ATOM_TV1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) |
| #define ATOM_DFP1_DTD_MODE_TBL_ADDR (ATOM_DFP1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) |
| #define ATOM_DFP1_STD_MODE_TBL_ADDR (ATOM_DFP1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) |
| #define ATOM_CRT2_EDID_ADDR (ATOM_DFP1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) |
| #define ATOM_CRT2_DTD_MODE_TBL_ADDR (ATOM_CRT2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) |
| #define ATOM_CRT2_STD_MODE_TBL_ADDR (ATOM_CRT2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) |
| #define ATOM_LCD2_EDID_ADDR (ATOM_CRT2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) |
| #define ATOM_LCD2_DTD_MODE_TBL_ADDR (ATOM_LCD2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) |
| #define ATOM_LCD2_STD_MODE_TBL_ADDR (ATOM_LCD2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) |
| #define ATOM_TV2_EDID_ADDR (ATOM_LCD2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) |
| #define ATOM_TV2_DTD_MODE_TBL_ADDR (ATOM_TV2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) |
| #define ATOM_TV2_STD_MODE_TBL_ADDR (ATOM_TV2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) |
| #define ATOM_DFP2_EDID_ADDR (ATOM_TV2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) |
| #define ATOM_DFP2_DTD_MODE_TBL_ADDR (ATOM_DFP2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) |
| #define ATOM_DFP2_STD_MODE_TBL_ADDR (ATOM_DFP2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) |
| #define ATOM_CV_EDID_ADDR (ATOM_DFP2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) |
| #define ATOM_CV_DTD_MODE_TBL_ADDR (ATOM_CV_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) |
| #define ATOM_CV_STD_MODE_TBL_ADDR (ATOM_CV_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) |
| #define ATOM_DFP3_EDID_ADDR (ATOM_CV_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) |
| #define ATOM_DFP3_DTD_MODE_TBL_ADDR (ATOM_DFP3_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) |
| #define ATOM_DFP3_STD_MODE_TBL_ADDR (ATOM_DFP3_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) |
| #define ATOM_DFP4_EDID_ADDR (ATOM_DFP3_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) |
| #define ATOM_DFP4_DTD_MODE_TBL_ADDR (ATOM_DFP4_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) |
| #define ATOM_DFP4_STD_MODE_TBL_ADDR (ATOM_DFP4_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) |
| #define ATOM_DFP5_EDID_ADDR (ATOM_DFP4_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) |
| #define ATOM_DFP5_DTD_MODE_TBL_ADDR (ATOM_DFP5_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) |
| #define ATOM_DFP5_STD_MODE_TBL_ADDR (ATOM_DFP5_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) |
| #define ATOM_DP_TRAINING_TBL_ADDR (ATOM_DFP5_STD_MODE_TBL_ADDR+ATOM_STD_MODE_SUPPORT_TBL_SIZE) |
| #define ATOM_STACK_STORAGE_START (ATOM_DP_TRAINING_TBL_ADDR + 256) |
| #define ATOM_STACK_STORAGE_END (ATOM_STACK_STORAGE_START + 512) |
| /* The size below is in Kb! */ |
| #define ATOM_VRAM_RESERVE_SIZE ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)+4)&0xFFFC) |
| #define ATOM_VRAM_OPERATION_FLAGS_MASK 0xC0000000L |
| #define ATOM_VRAM_OPERATION_FLAGS_SHIFT 30 |
| #define ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION 0x1 |
| #define ATOM_VRAM_BLOCK_NEEDS_RESERVATION 0x0 |
| /***********************************************************************************/ |
| /* Structure used in VRAM_UsageByFirmwareTable */ |
| /* Note1: This table is filled by SetBiosReservationStartInFB in CoreCommSubs.asm */ |
| /* at running time. */ |
| /* note2: From RV770, the memory is more than 32bit addressable, so we will change */ |
| /* ucTableFormatRevision=1,ucTableContentRevision=4, the strcuture remains */ |
| /* exactly same as 1.1 and 1.2 (1.3 is never in use), but ulStartAddrUsedByFirmware */ |
| /* (in offset to start of memory address) is KB aligned instead of byte aligend. */ |
| /***********************************************************************************/ |
| #define ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO 1 |
| typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO { |
| ULONG ulStartAddrUsedByFirmware; |
| USHORT usFirmwareUseInKb; |
| USHORT usReserved; |
| } ATOM_FIRMWARE_VRAM_RESERVE_INFO; |
| typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE { |
| ATOM_COMMON_TABLE_HEADER sHeader; |
| ATOM_FIRMWARE_VRAM_RESERVE_INFO |
| asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO]; |
| } ATOM_VRAM_USAGE_BY_FIRMWARE; |
| /****************************************************************************/ |
| /* Structure used in GPIO_Pin_LUTTable */ |
| /****************************************************************************/ |
| typedef struct _ATOM_GPIO_PIN_ASSIGNMENT { |
| USHORT usGpioPin_AIndex; |
| UCHAR ucGpioPinBitShift; |
| UCHAR ucGPIO_ID; |
| } ATOM_GPIO_PIN_ASSIGNMENT; |
| typedef struct _ATOM_GPIO_PIN_LUT { |
| ATOM_COMMON_TABLE_HEADER sHeader; |
| ATOM_GPIO_PIN_ASSIGNMENT asGPIO_Pin[1]; |
| } ATOM_GPIO_PIN_LUT; |
| /****************************************************************************/ |
| /* Structure used in ComponentVideoInfoTable */ |
| /****************************************************************************/ |
| #define GPIO_PIN_ACTIVE_HIGH 0x1 |
| #define MAX_SUPPORTED_CV_STANDARDS 5 |
| /* definitions for ATOM_D_INFO.ucSettings */ |
| #define ATOM_GPIO_SETTINGS_BITSHIFT_MASK 0x1F /* [4:0] */ |
| #define ATOM_GPIO_SETTINGS_RESERVED_MASK 0x60 /* [6:5] = must be zeroed out */ |
| #define ATOM_GPIO_SETTINGS_ACTIVE_MASK 0x80 /* [7] */ |
| typedef struct _ATOM_GPIO_INFO { |
| USHORT usAOffset; |
| UCHAR ucSettings; |
| UCHAR ucReserved; |
| } ATOM_GPIO_INFO; |
| /* definitions for ATOM_COMPONENT_VIDEO_INFO.ucMiscInfo (bit vector) */ |
| #define ATOM_CV_RESTRICT_FORMAT_SELECTION 0x2 |
| /* definitions for ATOM_COMPONENT_VIDEO_INFO.uc480i/uc480p/uc720p/uc1080i */ |
| #define ATOM_GPIO_DEFAULT_MODE_EN 0x80 /* [7]; */ |
| #define ATOM_GPIO_SETTING_PERMODE_MASK 0x7F /* [6:0] */ |
| /* definitions for ATOM_COMPONENT_VIDEO_INFO.ucLetterBoxMode */ |
| /* Line 3 out put 5V. */ |
| #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_A 0x01 /* represent gpio 3 state for 16:9 */ |
| #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_B 0x02 /* represent gpio 4 state for 16:9 */ |
| #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_SHIFT 0x0 |
| /* Line 3 out put 2.2V */ |
| #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_A 0x04 /* represent gpio 3 state for 4:3 Letter box */ |
| #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_B 0x08 /* represent gpio 4 state for 4:3 Letter box */ |
| #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_SHIFT 0x2 |
| /* Line 3 out put 0V */ |
| #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_A 0x10 /* represent gpio 3 state for 4:3 */ |
| #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_B 0x20 /* represent gpio 4 state for 4:3 */ |
| #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_SHIFT 0x4 |
| #define ATOM_CV_LINE3_ASPECTRATIO_MASK 0x3F /* bit [5:0] */ |
| #define ATOM_CV_LINE3_ASPECTRATIO_EXIST 0x80 /* bit 7 */ |
| /* GPIO bit index in gpio setting per mode value, also represend the block no. in gpio blocks. */ |
| #define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_A 3 /* bit 3 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode. */ |
| #define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_B 4 /* bit 4 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode. */ |
| typedef struct _ATOM_COMPONENT_VIDEO_INFO { |
| ATOM_COMMON_TABLE_HEADER sHeader; |
| USHORT usMask_PinRegisterIndex; |
| USHORT usEN_PinRegisterIndex; |
| USHORT usY_PinRegisterIndex; |
| USHORT usA_PinRegisterIndex; |
| UCHAR ucBitShift; |
| UCHAR ucPinActiveState; /* ucPinActiveState: Bit0=1 active high, =0 active low */ |
| ATOM_DTD_FORMAT sReserved; /* must be zeroed out */ |
| UCHAR ucMiscInfo; |
| UCHAR uc480i; |
| UCHAR uc480p; |
| UCHAR uc720p; |
| UCHAR uc1080i; |
| UCHAR ucLetterBoxMode; |
| UCHAR ucReserved[3]; |
| UCHAR ucNumOfWbGpioBlocks; /* For Component video D-Connector support. If zere, NTSC type connector */ |
| ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS]; |
| ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS]; |
| } ATOM_COMPONENT_VIDEO_INFO; |
| /* ucTableFormatRevision=2 */ |
| /* ucTableContentRevision=1 */ |
| typedef struct _ATOM_COMPONENT_VIDEO_INFO_V21 { |
| ATOM_COMMON_TABLE_HEADER sHeader; |
| UCHAR ucMiscInfo; |
| UCHAR uc480i; |
| UCHAR uc480p; |
| UCHAR uc720p; |
| UCHAR uc1080i; |
| UCHAR ucReserved; |
| UCHAR ucLetterBoxMode; |
| UCHAR ucNumOfWbGpioBlocks; /* For Component video D-Connector support. If zere, NTSC type connector */ |
| ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS]; |
| ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS]; |
| } ATOM_COMPONENT_VIDEO_INFO_V21; |
| #define ATOM_COMPONENT_VIDEO_INFO_LAST ATOM_COMPONENT_VIDEO_INFO_V21 |
| /****************************************************************************/ |
| /* Structure used in object_InfoTable */ |
| /****************************************************************************/ |
| typedef struct _ATOM_OBJECT_HEADER { |
| ATOM_COMMON_TABLE_HEADER sHeader; |
| USHORT usDeviceSupport; |
| USHORT usConnectorObjectTableOffset; |
| USHORT usRouterObjectTableOffset; |
| USHORT usEncoderObjectTableOffset; |
| USHORT usProtectionObjectTableOffset; /* only available when Protection block is independent. */ |
| USHORT usDisplayPathTableOffset; |
| } ATOM_OBJECT_HEADER; |
| typedef struct _ATOM_DISPLAY_OBJECT_PATH { |
| USHORT usDeviceTag; /* supported device */ |
| USHORT usSize; /* the size of ATOM_DISPLAY_OBJECT_PATH */ |
| USHORT usConnObjectId; /* Connector Object ID */ |
| USHORT usGPUObjectId; /* GPU ID */ |
| USHORT usGraphicObjIds[1]; /* 1st Encoder Obj source from GPU to last Graphic Obj destinate to connector. */ |
| } ATOM_DISPLAY_OBJECT_PATH; |
| typedef struct _ATOM_DISPLAY_OBJECT_PATH_TABLE { |
| UCHAR ucNumOfDispPath; |
| UCHAR ucVersion; |
| UCHAR ucPadding[2]; |
| ATOM_DISPLAY_OBJECT_PATH asDispPath[1]; |
| } ATOM_DISPLAY_OBJECT_PATH_TABLE; |
| typedef struct _ATOM_OBJECT /* each object has this structure */ |
| { |
| USHORT usObjectID; |
| USHORT usSrcDstTableOffset; |
| USHORT usRecordOffset; /* this pointing to a bunch of records defined below */ |
| USHORT usReserved; |
| } ATOM_OBJECT; |
| typedef struct _ATOM_OBJECT_TABLE /* Above 4 object table offset pointing to a bunch of objects all have this structure */ |
| { |
| UCHAR ucNumberOfObjects; |
| UCHAR ucPadding[3]; |
| ATOM_OBJECT asObjects[1]; |
| } ATOM_OBJECT_TABLE; |
| typedef struct _ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT /* usSrcDstTableOffset pointing to this structure */ |
| { |
| UCHAR ucNumberOfSrc; |
| USHORT usSrcObjectID[1]; |
| UCHAR ucNumberOfDst; |
| USHORT usDstObjectID[1]; |
| } ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT; |
| /* Related definitions, all records are differnt but they have a commond header */ |
| typedef struct _ATOM_COMMON_RECORD_HEADER { |
| UCHAR ucRecordType; /* An emun to indicate the record type */ |
| UCHAR ucRecordSize; /* The size of the whole record in byte */ |
| } ATOM_COMMON_RECORD_HEADER; |
| #define ATOM_I2C_RECORD_TYPE 1 |
| #define ATOM_HPD_INT_RECORD_TYPE 2 |
| #define ATOM_OUTPUT_PROTECTION_RECORD_TYPE 3 |
| #define ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE 4 |
| #define ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD_TYPE 5 /* Obsolete, switch to use GPIO_CNTL_RECORD_TYPE */ |
| #define ATOM_ENCODER_FPGA_CONTROL_RECORD_TYPE 6 /* Obsolete, switch to use GPIO_CNTL_RECORD_TYPE */ |
| #define ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD_TYPE 7 |
| #define ATOM_JTAG_RECORD_TYPE 8 /* Obsolete, switch to use GPIO_CNTL_RECORD_TYPE */ |
| #define ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE 9 |
| #define ATOM_ENCODER_DVO_CF_RECORD_TYPE 10 |
| #define ATOM_CONNECTOR_CF_RECORD_TYPE 11 |
| #define ATOM_CONNECTOR_HARDCODE_DTD_RECORD_TYPE 12 |
| #define ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE 13 |
| #define ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE 14 |
| #define ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE 15 |
| /* Must be updated when new record type is added,equal to that record definition! */ |
| #define ATOM_MAX_OBJECT_RECORD_NUMBER ATOM_CONNECTOR_CF_RECORD_TYPE |
| typedef struct _ATOM_I2C_RECORD { |
| ATOM_COMMON_RECORD_HEADER sheader; |
| ATOM_I2C_ID_CONFIG sucI2cId; |
| UCHAR ucI2CAddr; /* The slave address, it's 0 when the record is attached to connector for DDC */ |
| } ATOM_I2C_RECORD; |
| typedef struct _ATOM_HPD_INT_RECORD { |
| ATOM_COMMON_RECORD_HEADER sheader; |
| UCHAR ucHPDIntGPIOID; /* Corresponding block in GPIO_PIN_INFO table gives the pin info */ |
| UCHAR ucPluggged_PinState; |
| } ATOM_HPD_INT_RECORD; |
| typedef struct _ATOM_OUTPUT_PROTECTION_RECORD { |
| ATOM_COMMON_RECORD_HEADER sheader; |
| UCHAR ucProtectionFlag; |
| UCHAR ucReserved; |
| } ATOM_OUTPUT_PROTECTION_RECORD; |
| typedef struct _ATOM_CONNECTOR_DEVICE_TAG { |
| ULONG ulACPIDeviceEnum; /* Reserved for now */ |
| USHORT usDeviceID; /* This Id is same as "ATOM_DEVICE_XXX_SUPPORT" */ |
| USHORT usPadding; |
| } ATOM_CONNECTOR_DEVICE_TAG; |
| typedef struct _ATOM_CONNECTOR_DEVICE_TAG_RECORD { |
| ATOM_COMMON_RECORD_HEADER sheader; |
| UCHAR ucNumberOfDevice; |
| UCHAR ucReserved; |
| ATOM_CONNECTOR_DEVICE_TAG asDeviceTag[1]; /* This Id is same as "ATOM_DEVICE_XXX_SUPPORT", 1 is only for allocation */ |
| } ATOM_CONNECTOR_DEVICE_TAG_RECORD; |
| typedef struct _ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD { |
| ATOM_COMMON_RECORD_HEADER sheader; |
| UCHAR ucConfigGPIOID; |
| UCHAR ucConfigGPIOState; /* Set to 1 when it's active high to enable external flow in */ |
| UCHAR ucFlowinGPIPID; |
| UCHAR ucExtInGPIPID; |
| } ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD; |
| typedef struct _ATOM_ENCODER_FPGA_CONTROL_RECORD { |
| ATOM_COMMON_RECORD_HEADER sheader; |
| UCHAR ucCTL1GPIO_ID; |
| UCHAR ucCTL1GPIOState; /* Set to 1 when it's active high */ |
| UCHAR ucCTL2GPIO_ID; |
| UCHAR ucCTL2GPIOState; /* Set to 1 when it's active high */ |
| UCHAR ucCTL3GPIO_ID; |
| UCHAR ucCTL3GPIOState; /* Set to 1 when it's active high */ |
| UCHAR ucCTLFPGA_IN_ID; |
| UCHAR ucPadding[3]; |
| } ATOM_ENCODER_FPGA_CONTROL_RECORD; |
| typedef struct _ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD { |
| ATOM_COMMON_RECORD_HEADER sheader; |
| UCHAR ucGPIOID; /* Corresponding block in GPIO_PIN_INFO table gives the pin info */ |
| UCHAR ucTVActiveState; /* Indicating when the pin==0 or 1 when TV is connected */ |
| } ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD; |
| typedef struct _ATOM_JTAG_RECORD { |
| ATOM_COMMON_RECORD_HEADER sheader; |
| UCHAR ucTMSGPIO_ID; |
| UCHAR ucTMSGPIOState; /* Set to 1 when it's active high */ |
| UCHAR ucTCKGPIO_ID; |
| UCHAR ucTCKGPIOState; /* Set to 1 when it's active high */ |
| UCHAR ucTDOGPIO_ID; |
| UCHAR ucTDOGPIOState; /* Set to 1 when it's active high */ |
| UCHAR ucTDIGPIO_ID; |
| UCHAR ucTDIGPIOState; /* Set to 1 when it's active high */ |
| UCHAR ucPadding[2]; |
| } ATOM_JTAG_RECORD; |
| /* The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually */ |
| typedef struct _ATOM_GPIO_PIN_CONTROL_PAIR { |
| UCHAR ucGPIOID; /* GPIO_ID, find the corresponding ID in GPIO_LUT table */ |
| UCHAR ucGPIO_PinState; /* Pin state showing how to set-up the pin */ |
| } ATOM_GPIO_PIN_CONTROL_PAIR; |
| typedef struct _ATOM_OBJECT_GPIO_CNTL_RECORD { |
| ATOM_COMMON_RECORD_HEADER sheader; |
| UCHAR ucFlags; /* Future expnadibility */ |
| UCHAR ucNumberOfPins; /* Number of GPIO pins used to control the object */ |
| ATOM_GPIO_PIN_CONTROL_PAIR asGpio[1]; /* the real gpio pin pair determined by number of pins ucNumberOfPins */ |
| } ATOM_OBJECT_GPIO_CNTL_RECORD; |
| /* Definitions for GPIO pin state */ |
| #define GPIO_PIN_TYPE_INPUT 0x00 |
| #define GPIO_PIN_TYPE_OUTPUT 0x10 |
| #define GPIO_PIN_TYPE_HW_CONTROL 0x20 |
| /* For GPIO_PIN_TYPE_OUTPUT the following is defined */ |
| #define GPIO_PIN_OUTPUT_STATE_MASK 0x01 |
| #define GPIO_PIN_OUTPUT_STATE_SHIFT 0 |
| #define GPIO_PIN_STATE_ACTIVE_LOW 0x0 |
| #define GPIO_PIN_STATE_ACTIVE_HIGH 0x1 |
| typedef struct _ATOM_ENCODER_DVO_CF_RECORD { |
| ATOM_COMMON_RECORD_HEADER sheader; |
| ULONG ulStrengthControl; /* DVOA strength control for CF */ |
| UCHAR ucPadding[2]; |
| } ATOM_ENCODER_DVO_CF_RECORD; |
| /* value for ATOM_CONNECTOR_CF_RECORD.ucConnectedDvoBundle */ |
| #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_UPPER12BITBUNDLEA 1 |
| #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_LOWER12BITBUNDLEB 2 |
| typedef struct _ATOM_CONNECTOR_CF_RECORD { |
| ATOM_COMMON_RECORD_HEADER sheader; |
| USHORT usMaxPixClk; |
| UCHAR ucFlowCntlGpioId; |
| UCHAR ucSwapCntlGpioId; |
| UCHAR ucConnectedDvoBundle; |
| UCHAR ucPadding; |
| } ATOM_CONNECTOR_CF_RECORD; |
| typedef struct _ATOM_CONNECTOR_HARDCODE_DTD_RECORD { |
| ATOM_COMMON_RECORD_HEADER sheader; |
| ATOM_DTD_FORMAT asTiming; |
| } ATOM_CONNECTOR_HARDCODE_DTD_RECORD; |
| typedef struct _ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD { |
| ATOM_COMMON_RECORD_HEADER sheader; /* ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE */ |
| UCHAR ucSubConnectorType; /* CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D|X_ID_DUAL_LINK_DVI_D|HDMI_TYPE_A */ |
| UCHAR ucReserved; |
| } ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD; |
| typedef struct _ATOM_ROUTER_DDC_PATH_SELECT_RECORD { |
| ATOM_COMMON_RECORD_HEADER sheader; |
| UCHAR ucMuxType; /* decide the number of ucMuxState, =0, no pin state, =1: single state with complement, >1: multiple state */ |
| UCHAR ucMuxControlPin; |
| UCHAR ucMuxState[2]; /* for alligment purpose */ |
| } ATOM_ROUTER_DDC_PATH_SELECT_RECORD; |
| typedef struct _ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD { |
| ATOM_COMMON_RECORD_HEADER sheader; |
| UCHAR ucMuxType; |
| UCHAR ucMuxControlPin; |
| UCHAR ucMuxState[2]; /* for alligment purpose */ |
| } ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD; |
| /* define ucMuxType */ |
| #define ATOM_ROUTER_MUX_PIN_STATE_MASK 0x0f |
| #define ATOM_ROUTER_MUX_PIN_SINGLE_STATE_COMPLEMENT 0x01 |
| /****************************************************************************/ |
| /* ASIC voltage data table */ |
| /****************************************************************************/ |
| typedef struct _ATOM_VOLTAGE_INFO_HEADER { |
| USHORT usVDDCBaseLevel; /* In number of 50mv unit */ |
| USHORT usReserved; /* For possible extension table offset */ |
| UCHAR ucNumOfVoltageEntries; |
| UCHAR ucBytesPerVoltageEntry; |
| UCHAR ucVoltageStep; /* Indicating in how many mv increament is one step, 0.5mv unit */ |
| UCHAR ucDefaultVoltageEntry; |
| UCHAR ucVoltageControlI2cLine; |
| UCHAR ucVoltageControlAddress; |
| UCHAR ucVoltageControlOffset; |
| } ATOM_VOLTAGE_INFO_HEADER; |
| typedef struct _ATOM_VOLTAGE_INFO { |
| ATOM_COMMON_TABLE_HEADER sHeader; |
| ATOM_VOLTAGE_INFO_HEADER viHeader; |
| UCHAR ucVoltageEntries[64]; /* 64 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries*ucBytesPerVoltageEntry */ |
| } ATOM_VOLTAGE_INFO; |
| typedef struct _ATOM_VOLTAGE_FORMULA { |
| USHORT usVoltageBaseLevel; /* In number of 1mv unit */ |
| USHORT usVoltageStep; /* Indicating in how many mv increament is one step, 1mv unit */ |
| UCHAR ucNumOfVoltageEntries; /* Number of Voltage Entry, which indicate max Voltage */ |
| UCHAR ucFlag; /* bit0=0 :step is 1mv =1 0.5mv */ |
| UCHAR ucBaseVID; /* if there is no lookup table, VID= BaseVID + ( Vol - BaseLevle ) /VoltageStep */ |
| UCHAR ucReserved; |
| UCHAR ucVIDAdjustEntries[32]; /* 32 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries */ |
| } ATOM_VOLTAGE_FORMULA; |
| typedef struct _ATOM_VOLTAGE_CONTROL { |
| UCHAR ucVoltageControlId; /* Indicate it is controlled by I2C or GPIO or HW state machine */ |
| UCHAR ucVoltageControlI2cLine; |
| UCHAR ucVoltageControlAddress; |
| UCHAR ucVoltageControlOffset; |
| USHORT usGpioPin_AIndex; /* GPIO_PAD register index */ |
| UCHAR ucGpioPinBitShift[9]; /* at most 8 pin support 255 VIDs, termintate with 0xff */ |
| UCHAR ucReserved; |
| } ATOM_VOLTAGE_CONTROL; |
| /* Define ucVoltageControlId */ |
| #define VOLTAGE_CONTROLLED_BY_HW 0x00 |
| #define VOLTAGE_CONTROLLED_BY_I2C_MASK 0x7F |
| #define VOLTAGE_CONTROLLED_BY_GPIO 0x80 |
| #define VOLTAGE_CONTROL_ID_LM64 0x01 /* I2C control, used for R5xx Core Voltage */ |
| #define VOLTAGE_CONTROL_ID_DAC 0x02 /* I2C control, used for R5xx/R6xx MVDDC,MVDDQ or VDDCI */ |
| #define VOLTAGE_CONTROL_ID_VT116xM 0x03 /* I2C control, used for R6xx Core Voltage */ |
| #define VOLTAGE_CONTROL_ID_DS4402 0x04 |
| typedef struct _ATOM_VOLTAGE_OBJECT { |
| UCHAR ucVoltageType; /* Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI */ |
| UCHAR ucSize; /* Size of Object */ |
| ATOM_VOLTAGE_CONTROL asControl; /* describ how to control */ |
| ATOM_VOLTAGE_FORMULA asFormula; /* Indicate How to convert real Voltage to VID */ |
| } ATOM_VOLTAGE_OBJECT; |
| typedef struct _ATOM_VOLTAGE_OBJECT_INFO { |
| ATOM_COMMON_TABLE_HEADER sHeader; |
| ATOM_VOLTAGE_OBJECT asVoltageObj[3]; /* Info for Voltage control */ |
| } ATOM_VOLTAGE_OBJECT_INFO; |
| typedef struct _ATOM_LEAKID_VOLTAGE { |
| UCHAR ucLeakageId; |
| UCHAR ucReserved; |
| USHORT usVoltage; |
| } ATOM_LEAKID_VOLTAGE; |
| typedef struct _ATOM_ASIC_PROFILE_VOLTAGE { |
| UCHAR ucProfileId; |
| UCHAR ucReserved; |
| USHORT usSize; |
| USHORT usEfuseSpareStartAddr; |
| USHORT usFuseIndex[8]; /* from LSB to MSB, Max 8bit,end of 0xffff if less than 8 efuse id, */ |
| ATOM_LEAKID_VOLTAGE asLeakVol[2]; /* Leakid and relatd voltage */ |
| } ATOM_ASIC_PROFILE_VOLTAGE; |
| /* ucProfileId */ |
| #define ATOM_ASIC_PROFILE_ID_EFUSE_VOLTAGE 1 |
| #define ATOM_ASIC_PROFILE_ID_EFUSE_PERFORMANCE_VOLTAGE 1 |
| #define ATOM_ASIC_PROFILE_ID_EFUSE_THERMAL_VOLTAGE 2 |
| typedef struct _ATOM_ASIC_PROFILING_INFO { |
| ATOM_COMMON_TABLE_HEADER asHeader; |
| ATOM_ASIC_PROFILE_VOLTAGE asVoltage; |
| } ATOM_ASIC_PROFILING_INFO; |
| typedef struct _ATOM_POWER_SOURCE_OBJECT { |
| UCHAR ucPwrSrcId; /* Power source */ |
| UCHAR ucPwrSensorType; /* GPIO, I2C or none */ |
| UCHAR ucPwrSensId; /* if GPIO detect, it is GPIO id, if I2C detect, it is I2C id */ |
| UCHAR ucPwrSensSlaveAddr; /* Slave address if I2C detect */ |
| UCHAR ucPwrSensRegIndex; /* I2C register Index if I2C detect */ |
| UCHAR ucPwrSensRegBitMask; /* detect which bit is used if I2C detect */ |
| UCHAR ucPwrSensActiveState; /* high active or low active */ |
| UCHAR ucReserve[3]; /* reserve */ |
| USHORT usSensPwr; /* in unit of watt */ |
| } ATOM_POWER_SOURCE_OBJECT; |
| typedef struct _ATOM_POWER_SOURCE_INFO { |
| ATOM_COMMON_TABLE_HEADER asHeader; |
| UCHAR asPwrbehave[16]; |
| ATOM_POWER_SOURCE_OBJECT asPwrObj[1]; |
| } ATOM_POWER_SOURCE_INFO; |
| /* Define ucPwrSrcId */ |
| #define POWERSOURCE_PCIE_ID1 0x00 |
| #define POWERSOURCE_6PIN_CONNECTOR_ID1 0x01 |
| #define POWERSOURCE_8PIN_CONNECTOR_ID1 0x02 |
| #define POWERSOURCE_6PIN_CONNECTOR_ID2 0x04 |
| #define POWERSOURCE_8PIN_CONNECTOR_ID2 0x08 |
| /* define ucPwrSensorId */ |
| #define POWER_SENSOR_ALWAYS 0x00 |
| #define POWER_SENSOR_GPIO 0x01 |
| #define POWER_SENSOR_I2C 0x02 |
| /**************************************************************************/ |
| /* This portion is only used when ext thermal chip or engine/memory clock SS chip is populated on a design */ |
| /* Memory SS Info Table */ |
| /* Define Memory Clock SS chip ID */ |
| #define ICS91719 1 |
| #define ICS91720 2 |
| /* Define one structure to inform SW a "block of data" writing to external SS chip via I2C protocol */ |
| typedef struct _ATOM_I2C_DATA_RECORD { |
| UCHAR ucNunberOfBytes; /* Indicates how many bytes SW needs to write to the external ASIC for one block, besides to "Start" and "Stop" */ |
| UCHAR ucI2CData[1]; /* I2C data in bytes, should be less than 16 bytes usually */ |
| } ATOM_I2C_DATA_RECORD; |
| /* Define one structure to inform SW how many blocks of data writing to external SS chip via I2C protocol, in addition to other information */ |
| typedef struct _ATOM_I2C_DEVICE_SETUP_INFO { |
| ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; /* I2C line and HW/SW assisted cap. */ |
| UCHAR ucSSChipID; /* SS chip being used */ |
| UCHAR ucSSChipSlaveAddr; /* Slave Address to set up this SS chip */ |
| UCHAR ucNumOfI2CDataRecords; /* number of data block */ |
| ATOM_I2C_DATA_RECORD asI2CData[1]; |
| } ATOM_I2C_DEVICE_SETUP_INFO; |
| /* ========================================================================================== */ |
| typedef struct _ATOM_ASIC_MVDD_INFO { |
| ATOM_COMMON_TABLE_HEADER sHeader; |
| ATOM_I2C_DEVICE_SETUP_INFO asI2CSetup[1]; |
| } ATOM_ASIC_MVDD_INFO; |
| /* ========================================================================================== */ |
| #define ATOM_MCLK_SS_INFO ATOM_ASIC_MVDD_INFO |
| /* ========================================================================================== */ |
| /**************************************************************************/ |
| typedef struct _ATOM_ASIC_SS_ASSIGNMENT { |
| ULONG ulTargetClockRange; /* Clock Out frequence (VCO ), in unit of 10Khz */ |
| USHORT usSpreadSpectrumPercentage; /* in unit of 0.01% */ |
| USHORT usSpreadRateInKhz; /* in unit of kHz, modulation freq */ |
| UCHAR ucClockIndication; /* Indicate which clock source needs SS */ |
| UCHAR ucSpreadSpectrumMode; /* Bit1=0 Down Spread,=1 Center Spread. */ |
| UCHAR ucReserved[2]; |
| } ATOM_ASIC_SS_ASSIGNMENT; |
| /* Define ucSpreadSpectrumType */ |
| #define ASIC_INTERNAL_MEMORY_SS 1 |
| #define ASIC_INTERNAL_ENGINE_SS 2 |
| #define ASIC_INTERNAL_UVD_SS 3 |
| typedef struct _ATOM_ASIC_INTERNAL_SS_INFO { |
| ATOM_COMMON_TABLE_HEADER sHeader; |
| ATOM_ASIC_SS_ASSIGNMENT asSpreadSpectrum[4]; |
| } ATOM_ASIC_INTERNAL_SS_INFO; |
| /* ==============================Scratch Pad Definition Portion=============================== */ |
| #define ATOM_DEVICE_CONNECT_INFO_DEF 0 |
| #define ATOM_ROM_LOCATION_DEF 1 |
| #define ATOM_TV_STANDARD_DEF 2 |
| #define ATOM_ACTIVE_INFO_DEF 3 |
| #define ATOM_LCD_INFO_DEF 4 |
| #define ATOM_DOS_REQ_INFO_DEF 5 |
| #define ATOM_ACC_CHANGE_INFO_DEF 6 |
| #define ATOM_DOS_MODE_INFO_DEF 7 |
| #define ATOM_I2C_CHANNEL_STATUS_DEF 8 |
| #define ATOM_I2C_CHANNEL_STATUS1_DEF 9 |
| /* BIOS_0_SCRATCH Definition */ |
| #define ATOM_S0_CRT1_MONO 0x00000001L |
| #define ATOM_S0_CRT1_COLOR 0x00000002L |
| #define ATOM_S0_CRT1_MASK (ATOM_S0_CRT1_MONO+ATOM_S0_CRT1_COLOR) |
| #define ATOM_S0_TV1_COMPOSITE_A 0x00000004L |
| #define ATOM_S0_TV1_SVIDEO_A 0x00000008L |
| #define ATOM_S0_TV1_MASK_A (ATOM_S0_TV1_COMPOSITE_A+ATOM_S0_TV1_SVIDEO_A) |
| #define ATOM_S0_CV_A 0x00000010L |
| #define ATOM_S0_CV_DIN_A 0x00000020L |
| #define ATOM_S0_CV_MASK_A (ATOM_S0_CV_A+ATOM_S0_CV_DIN_A) |
| #define ATOM_S0_CRT2_MONO 0x00000100L |
| #define ATOM_S0_CRT2_COLOR 0x00000200L |
| #define ATOM_S0_CRT2_MASK (ATOM_S0_CRT2_MONO+ATOM_S0_CRT2_COLOR) |
| #define ATOM_S0_TV1_COMPOSITE 0x00000400L |
| #define ATOM_S0_TV1_SVIDEO 0x00000800L |
| #define ATOM_S0_TV1_SCART 0x00004000L |
| #define ATOM_S0_TV1_MASK (ATOM_S0_TV1_COMPOSITE+ATOM_S0_TV1_SVIDEO+ATOM_S0_TV1_SCART) |
| #define ATOM_S0_CV 0x00001000L |
| #define ATOM_S0_CV_DIN 0x00002000L |
| #define ATOM_S0_CV_MASK (ATOM_S0_CV+ATOM_S0_CV_DIN) |
| #define ATOM_S0_DFP1 0x00010000L |
| #define ATOM_S0_DFP2 0x00020000L |
| #define ATOM_S0_LCD1 0x00040000L |
| #define ATOM_S0_LCD2 0x00080000L |
| #define ATOM_S0_TV2 0x00100000L |
| #define ATOM_S0_DFP3 0x00200000L |
| #define ATOM_S0_DFP4 0x00400000L |
| #define ATOM_S0_DFP5 0x00800000L |
| #define ATOM_S0_DFP_MASK \ |
| (ATOM_S0_DFP1 | ATOM_S0_DFP2 | ATOM_S0_DFP3 | ATOM_S0_DFP4 | ATOM_S0_DFP5) |
| #define ATOM_S0_FAD_REGISTER_BUG 0x02000000L /* If set, indicates we are running a PCIE asic with */ |
| /* the FAD/HDP reg access bug. Bit is read by DAL */ |
| #define ATOM_S0_THERMAL_STATE_MASK 0x1C000000L |
| #define ATOM_S0_THERMAL_STATE_SHIFT 26 |
| #define ATOM_S0_SYSTEM_POWER_STATE_MASK 0xE0000000L |
| #define ATOM_S0_SYSTEM_POWER_STATE_SHIFT 29 |
| #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_AC 1 |
| #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_DC 2 |
| #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LITEAC 3 |
| /* Byte aligned defintion for BIOS usage */ |
| #define ATOM_S0_CRT1_MONOb0 0x01 |
| #define ATOM_S0_CRT1_COLORb0 0x02 |
| #define ATOM_S0_CRT1_MASKb0 (ATOM_S0_CRT1_MONOb0+ATOM_S0_CRT1_COLORb0) |
| #define ATOM_S0_TV1_COMPOSITEb0 0x04 |
| #define ATOM_S0_TV1_SVIDEOb0 0x08 |
| #define ATOM_S0_TV1_MASKb0 (ATOM_S0_TV1_COMPOSITEb0+ATOM_S0_TV1_SVIDEOb0) |
| #define ATOM_S0_CVb0 0x10 |
| #define ATOM_S0_CV_DINb0 0x20 |
| #define ATOM_S0_CV_MASKb0 (ATOM_S0_CVb0+ATOM_S0_CV_DINb0) |
| #define ATOM_S0_CRT2_MONOb1 0x01 |
| #define ATOM_S0_CRT2_COLORb1 0x02 |
| #define ATOM_S0_CRT2_MASKb1 (ATOM_S0_CRT2_MONOb1+ATOM_S0_CRT2_COLORb1) |
| #define ATOM_S0_TV1_COMPOSITEb1 0x04 |
| #define ATOM_S0_TV1_SVIDEOb1 0x08 |
| #define ATOM_S0_TV1_SCARTb1 0x40 |
| #define ATOM_S0_TV1_MASKb1 (ATOM_S0_TV1_COMPOSITEb1+ATOM_S0_TV1_SVIDEOb1+ATOM_S0_TV1_SCARTb1) |
| #define ATOM_S0_CVb1 0x10 |
| #define ATOM_S0_CV_DINb1 0x20 |
| #define ATOM_S0_CV_MASKb1 (ATOM_S0_CVb1+ATOM_S0_CV_DINb1) |
| #define ATOM_S0_DFP1b2 0x01 |
| #define ATOM_S0_DFP2b2 0x02 |
| #define ATOM_S0_LCD1b2 0x04 |
| #define ATOM_S0_LCD2b2 0x08 |
| #define ATOM_S0_TV2b2 0x10 |
| #define ATOM_S0_DFP3b2 0x20 |
| #define ATOM_S0_THERMAL_STATE_MASKb3 0x1C |
| #define ATOM_S0_THERMAL_STATE_SHIFTb3 2 |
| #define ATOM_S0_SYSTEM_POWER_STATE_MASKb3 0xE0 |
| #define ATOM_S0_LCD1_SHIFT 18 |
| /* BIOS_1_SCRATCH Definition */ |
| #define ATOM_S1_ROM_LOCATION_MASK 0x0000FFFFL |
| #define ATOM_S1_PCI_BUS_DEV_MASK 0xFFFF0000L |
| /* BIOS_2_SCRATCH Definition */ |
| #define ATOM_S2_TV1_STANDARD_MASK 0x0000000FL |
| #define ATOM_S2_CURRENT_BL_LEVEL_MASK 0x0000FF00L |
| #define ATOM_S2_CURRENT_BL_LEVEL_SHIFT 8 |
| #define ATOM_S2_CRT1_DPMS_STATE 0x00010000L |
| #define ATOM_S2_LCD1_DPMS_STATE 0x00020000L |
| #define ATOM_S2_TV1_DPMS_STATE 0x00040000L |
| #define ATOM_S2_DFP1_DPMS_STATE 0x00080000L |
| #define ATOM_S2_CRT2_DPMS_STATE 0x00100000L |
| #define ATOM_S2_LCD2_DPMS_STATE 0x00200000L |
| #define ATOM_S2_TV2_DPMS_STATE 0x00400000L |
| #define ATOM_S2_DFP2_DPMS_STATE 0x00800000L |
| #define ATOM_S2_CV_DPMS_STATE 0x01000000L |
| #define ATOM_S2_DFP3_DPMS_STATE 0x02000000L |
| #define ATOM_S2_DFP4_DPMS_STATE 0x04000000L |
| #define ATOM_S2_DFP5_DPMS_STATE 0x08000000L |
| #define ATOM_S2_DFP_DPM_STATE \ |
| (ATOM_S2_DFP1_DPMS_STATE | ATOM_S2_DFP2_DPMS_STATE | \ |
| ATOM_S2_DFP3_DPMS_STATE | ATOM_S2_DFP4_DPMS_STATE | \ |
| ATOM_S2_DFP5_DPMS_STATE) |
| #define ATOM_S2_DEVICE_DPMS_STATE \ |
| (ATOM_S2_CRT1_DPMS_STATE + ATOM_S2_LCD1_DPMS_STATE + \ |
| ATOM_S2_TV1_DPMS_STATE + ATOM_S2_DFP_DPMS_STATE + \ |
| ATOM_S2_CRT2_DPMS_STATE + ATOM_S2_LCD2_DPMS_STATE + \ |
| ATOM_S2_TV2_DPMS_STATE + ATOM_S2_CV_DPMS_STATE) |
| #define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK 0x0C000000L |
| #define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK_SHIFT 26 |
| #define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGE 0x10000000L |
| #define ATOM_S2_VRI_BRIGHT_ENABLE 0x20000000L |
| #define ATOM_S2_DISPLAY_ROTATION_0_DEGREE 0x0 |
| #define ATOM_S2_DISPLAY_ROTATION_90_DEGREE 0x1 |
| #define ATOM_S2_DISPLAY_ROTATION_180_DEGREE 0x2 |
| #define ATOM_S2_DISPLAY_ROTATION_270_DEGREE 0x3 |
| #define ATOM_S2_DISPLAY_ROTATION_DEGREE_SHIFT 30 |
| #define ATOM_S2_DISPLAY_ROTATION_ANGLE_MASK 0xC0000000L |
| /* Byte aligned defintion for BIOS usage */ |
| #define ATOM_S2_TV1_STANDARD_MASKb0 0x0F |
| #define ATOM_S2_CURRENT_BL_LEVEL_MASKb1 0xFF |
| #define ATOM_S2_CRT1_DPMS_STATEb2 0x01 |
| #define ATOM_S2_LCD1_DPMS_STATEb2 0x02 |
| #define ATOM_S2_TV1_DPMS_STATEb2 0x04 |
| #define ATOM_S2_DFP1_DPMS_STATEb2 0x08 |
| #define ATOM_S2_CRT2_DPMS_STATEb2 0x10 |
| #define ATOM_S2_LCD2_DPMS_STATEb2 0x20 |
| #define ATOM_S2_TV2_DPMS_STATEb2 0x40 |
| #define ATOM_S2_DFP2_DPMS_STATEb2 0x80 |
| #define ATOM_S2_CV_DPMS_STATEb3 0x01 |
| #define ATOM_S2_DFP3_DPMS_STATEb3 0x02 |
| #define ATOM_S2_DFP4_DPMS_STATEb3 0x04 |
| #define ATOM_S2_DFP5_DPMS_STATEb3 0x08 |
| #define ATOM_S2_DEVICE_DPMS_MASKw1 0x3FF |
| #define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASKb3 0x0C |
| #define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGEb3 0x10 |
| #define ATOM_S2_VRI_BRIGHT_ENABLEb3 0x20 |
| #define ATOM_S2_ROTATION_STATE_MASKb3 0xC0 |
| /* BIOS_3_SCRATCH Definition */ |
| #define ATOM_S3_CRT1_ACTIVE 0x00000001L |
| #define ATOM_S3_LCD1_ACTIVE 0x00000002L |
| #define ATOM_S3_TV1_ACTIVE 0x00000004L |
| #define ATOM_S3_DFP1_ACTIVE 0x00000008L |
| #define ATOM_S3_CRT2_ACTIVE 0x00000010L |
| #define ATOM_S3_LCD2_ACTIVE 0x00000020L |
| #define ATOM_S3_TV2_ACTIVE 0x00000040L |
| #define ATOM_S3_DFP2_ACTIVE 0x00000080L |
| #define ATOM_S3_CV_ACTIVE 0x00000100L |
| #define ATOM_S3_DFP3_ACTIVE 0x00000200L |
| #define ATOM_S3_DFP4_ACTIVE 0x00000400L |
| #define ATOM_S3_DFP5_ACTIVE 0x00000800L |
| #define ATOM_S3_DEVICE_ACTIVE_MASK 0x000003FFL |
| #define ATOM_S3_LCD_FULLEXPANSION_ACTIVE 0x00001000L |
| #define ATOM_S3_LCD_EXPANSION_ASPEC_RATIO_ACTIVE 0x00002000L |
| #define ATOM_S3_CRT1_CRTC_ACTIVE 0x00010000L |
| #define ATOM_S3_LCD1_CRTC_ACTIVE 0x00020000L |
| #define ATOM_S3_TV1_CRTC_ACTIVE 0x00040000L |
| #define ATOM_S3_DFP1_CRTC_ACTIVE 0x00080000L |
| #define ATOM_S3_CRT2_CRTC_ACTIVE 0x00100000L |
| #define ATOM_S3_LCD2_CRTC_ACTIVE 0x00200000L |
| #define ATOM_S3_TV2_CRTC_ACTIVE 0x00400000L |
| #define ATOM_S3_DFP2_CRTC_ACTIVE 0x00800000L |
| #define ATOM_S3_CV_CRTC_ACTIVE 0x01000000L |
| #define ATOM_S3_DFP3_CRTC_ACTIVE 0x02000000L |
| #define ATOM_S3_DFP4_CRTC_ACTIVE 0x04000000L |
| #define ATOM_S3_DFP5_CRTC_ACTIVE 0x08000000L |
| #define ATOM_S3_DEVICE_CRTC_ACTIVE_MASK 0x0FFF0000L |
| #define ATOM_S3_ASIC_GUI_ENGINE_HUNG 0x20000000L |
| #define ATOM_S3_ALLOW_FAST_PWR_SWITCH 0x40000000L |
| #define ATOM_S3_RQST_GPU_USE_MIN_PWR 0x80000000L |
| /* Byte aligned defintion for BIOS usage */ |
| #define ATOM_S3_CRT1_ACTIVEb0 0x01 |
| #define ATOM_S3_LCD1_ACTIVEb0 0x02 |
| #define ATOM_S3_TV1_ACTIVEb0 0x04 |
| #define ATOM_S3_DFP1_ACTIVEb0 0x08 |
| #define ATOM_S3_CRT2_ACTIVEb0 0x10 |
| #define ATOM_S3_LCD2_ACTIVEb0 0x20 |
| #define ATOM_S3_TV2_ACTIVEb0 0x40 |
| #define ATOM_S3_DFP2_ACTIVEb0 0x80 |
| #define ATOM_S3_CV_ACTIVEb1 0x01 |
| #define ATOM_S3_DFP3_ACTIVEb1 0x02 |
| #define ATOM_S3_DFP4_ACTIVEb1 0x04 |
| #define ATOM_S3_DFP5_ACTIVEb1 0x08 |
| #define ATOM_S3_ACTIVE_CRTC1w0 0xFFF |
| #define ATOM_S3_CRT1_CRTC_ACTIVEb2 0x01 |
| #define ATOM_S3_LCD1_CRTC_ACTIVEb2 0x02 |
| #define ATOM_S3_TV1_CRTC_ACTIVEb2 0x04 |
| #define ATOM_S3_DFP1_CRTC_ACTIVEb2 0x08 |
| #define ATOM_S3_CRT2_CRTC_ACTIVEb2 0x10 |
| #define ATOM_S3_LCD2_CRTC_ACTIVEb2 0x20 |
| #define ATOM_S3_TV2_CRTC_ACTIVEb2 0x40 |
| #define ATOM_S3_DFP2_CRTC_ACTIVEb2 0x80 |
| #define ATOM_S3_CV_CRTC_ACTIVEb3 0x01 |
| #define ATOM_S3_DFP3_CRTC_ACTIVEb3 0x02 |
| #define ATOM_S3_DFP4_CRTC_ACTIVEb3 0x04 |
| #define ATOM_S3_DFP5_CRTC_ACTIVEb3 0x08 |
| #define ATOM_S3_ACTIVE_CRTC2w1 0xFFF |
| #define ATOM_S3_ASIC_GUI_ENGINE_HUNGb3 0x20 |
| #define ATOM_S3_ALLOW_FAST_PWR_SWITCHb3 0x40 |
| #define ATOM_S3_RQST_GPU_USE_MIN_PWRb3 0x80 |
| /* BIOS_4_SCRATCH Definition */ |
| #define ATOM_S4_LCD1_PANEL_ID_MASK 0x000000FFL |
| #define ATOM_S4_LCD1_REFRESH_MASK 0x0000FF00L |
| #define ATOM_S4_LCD1_REFRESH_SHIFT 8 |
| /* Byte aligned defintion for BIOS usage */ |
| #define ATOM_S4_LCD1_PANEL_ID_MASKb0 0x0FF |
| #define ATOM_S4_LCD1_REFRESH_MASKb1 ATOM_S4_LCD1_PANEL_ID_MASKb0 |
| #define ATOM_S4_VRAM_INFO_MASKb2 ATOM_S4_LCD1_PANEL_ID_MASKb0 |
| /* BIOS_5_SCRATCH Definition, BIOS_5_SCRATCH is used by Firmware only !!!! */ |
| #define ATOM_S5_DOS_REQ_CRT1b0 0x01 |
| #define ATOM_S5_DOS_REQ_LCD1b0 0x02 |
| #define ATOM_S5_DOS_REQ_TV1b0 0x04 |
| #define ATOM_S5_DOS_REQ_DFP1b0 0x08 |
| #define ATOM_S5_DOS_REQ_CRT2b0 0x10 |
| #define ATOM_S5_DOS_REQ_LCD2b0 0x20 |
| #define ATOM_S5_DOS_REQ_TV2b0 0x40 |
| #define ATOM_S5_DOS_REQ_DFP2b0 0x80 |
| #define ATOM_S5_DOS_REQ_CVb1 0x01 |
| #define ATOM_S5_DOS_REQ_DFP3b1 0x02 |
| #define ATOM_S5_DOS_REQ_DFP4b1 0x04 |
| #define ATOM_S5_DOS_REQ_DFP5b1 0x08 |
| #define ATOM_S5_DOS_REQ_DEVICEw0 0x03FF |
| #define ATOM_S5_DOS_REQ_CRT1 0x0001 |
| #define ATOM_S5_DOS_REQ_LCD1 0x0002 |
| #define ATOM_S5_DOS_REQ_TV1 0x0004 |
| #define ATOM_S5_DOS_REQ_DFP1 0x0008 |
| #define ATOM_S5_DOS_REQ_CRT2 0x0010 |
| #define ATOM_S5_DOS_REQ_LCD2 0x0020 |
| #define ATOM_S5_DOS_REQ_TV2 0x0040 |
| #define ATOM_S5_DOS_REQ_DFP2 0x0080 |
| #define ATOM_S5_DOS_REQ_CV 0x0100 |
| #define ATOM_S5_DOS_REQ_DFP3 0x0200 |
| #define ATOM_S5_DOS_REQ_DFP4 0x0400 |
| #define ATOM_S5_DOS_REQ_DFP5 0x0800 |
| #define ATOM_S5_DOS_FORCE_CRT1b2 ATOM_S5_DOS_REQ_CRT1b0 |
| #define ATOM_S5_DOS_FORCE_TV1b2 ATOM_S5_DOS_REQ_TV1b0 |
| #define ATOM_S5_DOS_FORCE_CRT2b2 ATOM_S5_DOS_REQ_CRT2b0 |
| #define ATOM_S5_DOS_FORCE_CVb3 ATOM_S5_DOS_REQ_CVb1 |
| #define ATOM_S5_DOS_FORCE_DEVICEw1 \ |
| (ATOM_S5_DOS_FORCE_CRT1b2 + ATOM_S5_DOS_FORCE_TV1b2 + \ |
| ATOM_S5_DOS_FORCE_CRT2b2 + (ATOM_S5_DOS_FORCE_CVb3 << 8)) |
| /* BIOS_6_SCRATCH Definition */ |
| #define ATOM_S6_DEVICE_CHANGE 0x00000001L |
| #define ATOM_S6_SCALER_CHANGE 0x00000002L |
| #define ATOM_S6_LID_CHANGE 0x00000004L |
| #define ATOM_S6_DOCKING_CHANGE 0x00000008L |
| #define ATOM_S6_ACC_MODE 0x00000010L |
| #define ATOM_S6_EXT_DESKTOP_MODE 0x00000020L |
| #define ATOM_S6_LID_STATE 0x00000040L |
| #define ATOM_S6_DOCK_STATE 0x00000080L |
| #define ATOM_S6_CRITICAL_STATE 0x00000100L |
| #define ATOM_S6_HW_I2C_BUSY_STATE 0x00000200L |
| #define ATOM_S6_THERMAL_STATE_CHANGE 0x00000400L |
| #define ATOM_S6_INTERRUPT_SET_BY_BIOS 0x00000800L |
| #define ATOM_S6_REQ_LCD_EXPANSION_FULL 0x00001000L /* Normal expansion Request bit for LCD */ |
| #define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO 0x00002000L /* Aspect ratio expansion Request bit for LCD */ |
| #define ATOM_S6_DISPLAY_STATE_CHANGE 0x00004000L /* This bit is recycled when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_H_expansion */ |
| #define ATOM_S6_I2C_STATE_CHANGE 0x00008000L /* This bit is recycled,when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_V_expansion */ |
| #define ATOM_S6_ACC_REQ_CRT1 0x00010000L |
| #define ATOM_S6_ACC_REQ_LCD1 0x00020000L |
| #define ATOM_S6_ACC_REQ_TV1 0x00040000L |
| #define ATOM_S6_ACC_REQ_DFP1 0x00080000L |
| #define ATOM_S6_ACC_REQ_CRT2 0x00100000L |
| #define ATOM_S6_ACC_REQ_LCD2 0x00200000L |
| #define ATOM_S6_ACC_REQ_TV2 0x00400000L |
| #define ATOM_S6_ACC_REQ_DFP2 0x00800000L |
| #define ATOM_S6_ACC_REQ_CV 0x01000000L |
| #define ATOM_S6_ACC_REQ_DFP3 0x02000000L |
| #define ATOM_S6_ACC_REQ_DFP4 0x04000000L |
| #define ATOM_S6_ACC_REQ_DFP5 0x08000000L |
| #define ATOM_S6_ACC_REQ_MASK 0x0FFF0000L |
| #define ATOM_S6_SYSTEM_POWER_MODE_CHANGE 0x10000000L |
| #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH 0x20000000L |
| #define ATOM_S6_VRI_BRIGHTNESS_CHANGE 0x40000000L |
| #define ATOM_S6_CONFIG_DISPLAY_CHANGE_MASK 0x80000000L |
| /* Byte aligned defintion for BIOS usage */ |
| #define ATOM_S6_DEVICE_CHANGEb0 0x01 |
| #define ATOM_S6_SCALER_CHANGEb0 0x02 |
| #define ATOM_S6_LID_CHANGEb0 0x04 |
| #define ATOM_S6_DOCKING_CHANGEb0 0x08 |
| #define ATOM_S6_ACC_MODEb0 0x10 |
| #define ATOM_S6_EXT_DESKTOP_MODEb0 0x20 |
| #define ATOM_S6_LID_STATEb0 0x40 |
| #define ATOM_S6_DOCK_STATEb0 0x80 |
| #define ATOM_S6_CRITICAL_STATEb1 0x01 |
| #define ATOM_S6_HW_I2C_BUSY_STATEb1 0x02 |
| #define ATOM_S6_THERMAL_STATE_CHANGEb1 0x04 |
| #define ATOM_S6_INTERRUPT_SET_BY_BIOSb1 0x08 |
| #define ATOM_S6_REQ_LCD_EXPANSION_FULLb1 0x10 |
| #define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIOb1 0x20 |
| #define ATOM_S6_ACC_REQ_CRT1b2 0x01 |
| #define ATOM_S6_ACC_REQ_LCD1b2 0x02 |
| #define ATOM_S6_ACC_REQ_TV1b2 0x04 |
| #define ATOM_S6_ACC_REQ_DFP1b2 0x08 |
| #define ATOM_S6_ACC_REQ_CRT2b2 0x10 |
| #define ATOM_S6_ACC_REQ_LCD2b2 0x20 |
| #define ATOM_S6_ACC_REQ_TV2b2 0x40 |
| #define ATOM_S6_ACC_REQ_DFP2b2 0x80 |
| #define ATOM_S6_ACC_REQ_CVb3 0x01 |
| #define ATOM_S6_ACC_REQ_DFP3b3 0x02 |
| #define ATOM_S6_ACC_REQ_DFP4b3 0x04 |
| #define ATOM_S6_ACC_REQ_DFP5b3 0x08 |
| #define ATOM_S6_ACC_REQ_DEVICEw1 ATOM_S5_DOS_REQ_DEVICEw0 |
| #define ATOM_S6_SYSTEM_POWER_MODE_CHANGEb3 0x10 |
| #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCHb3 0x20 |
| #define ATOM_S6_VRI_BRIGHTNESS_CHANGEb3 0x40 |
| #define ATOM_S6_CONFIG_DISPLAY_CHANGEb3 0x80 |
| #define ATOM_S6_DEVICE_CHANGE_SHIFT 0 |
| #define ATOM_S6_SCALER_CHANGE_SHIFT 1 |
| #define ATOM_S6_LID_CHANGE_SHIFT 2 |
| #define ATOM_S6_DOCKING_CHANGE_SHIFT 3 |
| #define ATOM_S6_ACC_MODE_SHIFT 4 |
| #define ATOM_S6_EXT_DESKTOP_MODE_SHIFT 5 |
| #define ATOM_S6_LID_STATE_SHIFT 6 |
| #define ATOM_S6_DOCK_STATE_SHIFT 7 |
| #define ATOM_S6_CRITICAL_STATE_SHIFT 8 |
| #define ATOM_S6_HW_I2C_BUSY_STATE_SHIFT 9 |
| #define ATOM_S6_THERMAL_STATE_CHANGE_SHIFT 10 |
| #define ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT 11 |
| #define ATOM_S6_REQ_SCALER_SHIFT 12 |
| #define ATOM_S6_REQ_SCALER_ARATIO_SHIFT 13 |
| #define ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT 14 |
| #define ATOM_S6_I2C_STATE_CHANGE_SHIFT 15 |
| #define ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT 28 |
| #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH_SHIFT 29 |
| #define ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT 30 |
| #define ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT 31 |
| /* BIOS_7_SCRATCH Definition, BIOS_7_SCRATCH is used by Firmware only !!!! */ |
| #define ATOM_S7_DOS_MODE_TYPEb0 0x03 |
| #define ATOM_S7_DOS_MODE_VGAb0 0x00 |
| #define ATOM_S7_DOS_MODE_VESAb0 0x01 |
| #define ATOM_S7_DOS_MODE_EXTb0 0x02 |
| #define ATOM_S7_DOS_MODE_PIXEL_DEPTHb0 0x0C |
| #define ATOM_S7_DOS_MODE_PIXEL_FORMATb0 0xF0 |
| #define ATOM_S7_DOS_8BIT_DAC_ENb1 0x01 |
| #define ATOM_S7_DOS_MODE_NUMBERw1 0x0FFFF |
| #define ATOM_S7_DOS_8BIT_DAC_EN_SHIFT 8 |
| /* BIOS_8_SCRATCH Definition */ |
| #define ATOM_S8_I2C_CHANNEL_BUSY_MASK 0x00000FFFF |
| #define ATOM_S8_I2C_HW_ENGINE_BUSY_MASK 0x0FFFF0000 |
| #define ATOM_S8_I2C_CHANNEL_BUSY_SHIFT 0 |
| #define ATOM_S8_I2C_ENGINE_BUSY_SHIFT 16 |
| /* BIOS_9_SCRATCH Definition */ |
| #ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_MASK |
| #define ATOM_S9_I2C_CHANNEL_COMPLETED_MASK 0x0000FFFF |
| #endif |
| #ifndef ATOM_S9_I2C_CHANNEL_ABORTED_MASK |
| #define ATOM_S9_I2C_CHANNEL_ABORTED_MASK 0xFFFF0000 |
| #endif |
| #ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT |
| #define ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT 0 |
| #endif |
| #ifndef ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT |
| #define ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT 16 |
| #endif |
| #define ATOM_FLAG_SET 0x20 |
| #define ATOM_FLAG_CLEAR 0 |
| #define CLEAR_ATOM_S6_ACC_MODE \ |
| ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \ |
| ATOM_S6_ACC_MODE_SHIFT | ATOM_FLAG_CLEAR) |
| #define SET_ATOM_S6_DEVICE_CHANGE \ |
| ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \ |
| ATOM_S6_DEVICE_CHANGE_SHIFT | ATOM_FLAG_SET) |
| #define SET_ATOM_S6_VRI_BRIGHTNESS_CHANGE \ |
| ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \ |
| ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT | ATOM_FLAG_SET) |
| #define SET_ATOM_S6_SCALER_CHANGE \ |
| ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \ |
| ATOM_S6_SCALER_CHANGE_SHIFT | ATOM_FLAG_SET) |
| #define SET_ATOM_S6_LID_CHANGE \ |
| ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \ |
| ATOM_S6_LID_CHANGE_SHIFT | ATOM_FLAG_SET) |
| #define SET_ATOM_S6_LID_STATE \ |
| ((ATOM_ACC_CHANGE_INFO_DEF << 8) |\ |
| ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_SET) |
| #define CLEAR_ATOM_S6_LID_STATE \ |
| ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \ |
| ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_CLEAR) |
| #define SET_ATOM_S6_DOCK_CHANGE \ |
| ((ATOM_ACC_CHANGE_INFO_DEF << 8)| \ |
| ATOM_S6_DOCKING_CHANGE_SHIFT | ATOM_FLAG_SET) |
| #define SET_ATOM_S6_DOCK_STATE \ |
| ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \ |
| ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_SET) |
| #define CLEAR_ATOM_S6_DOCK_STATE \ |
| ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \ |
| ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_CLEAR) |
| #define SET_ATOM_S6_THERMAL_STATE_CHANGE \ |
| ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \ |
| ATOM_S6_THERMAL_STATE_CHANGE_SHIFT | ATOM_FLAG_SET) |
| #define SET_ATOM_S6_SYSTEM_POWER_MODE_CHANGE \ |
| ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \ |
| ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT | ATOM_FLAG_SET) |
| #define SET_ATOM_S6_INTERRUPT_SET_BY_BIOS \ |
| ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \ |
| ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT | ATOM_FLAG_SET) |
| #define SET_ATOM_S6_CRITICAL_STATE \ |
| ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \ |
| ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_SET) |
| #define CLEAR_ATOM_S6_CRITICAL_STATE \ |
| ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \ |
| ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_CLEAR) |
| #define SET_ATOM_S6_REQ_SCALER \ |
| ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \ |
| ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_SET) |
| #define CLEAR_ATOM_S6_REQ_SCALER \ |
| ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \ |
| ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_CLEAR ) |
| #define SET_ATOM_S6_REQ_SCALER_ARATIO \ |
| ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \ |
| ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_SET ) |
| #define CLEAR_ATOM_S6_REQ_SCALER_ARATIO \ |
| ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \ |
| ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_CLEAR ) |
| #define SET_ATOM_S6_I2C_STATE_CHANGE \ |
| ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \ |
| ATOM_S6_I2C_STATE_CHANGE_SHIFT | ATOM_FLAG_SET ) |
| #define SET_ATOM_S6_DISPLAY_STATE_CHANGE \ |
| ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \ |
| ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT | ATOM_FLAG_SET ) |
| #define SET_ATOM_S6_DEVICE_RECONFIG \ |
| ((ATOM_ACC_CHANGE_INFO_DEF << 8) | \ |
| ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT | ATOM_FLAG_SET) |
| #define CLEAR_ATOM_S0_LCD1 \ |
| ((ATOM_DEVICE_CONNECT_INFO_DEF << 8 ) | \ |
| ATOM_S0_LCD1_SHIFT | ATOM_FLAG_CLEAR ) |
| #define SET_ATOM_S7_DOS_8BIT_DAC_EN \ |
| ((ATOM_DOS_MODE_INFO_DEF << 8) | \ |
| ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_SET ) |
| #define CLEAR_ATOM_S7_DOS_8BIT_DAC_EN \ |
| ((ATOM_DOS_MODE_INFO_DEF << 8) | \ |
| ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_CLEAR ) |
| /****************************************************************************/ |
| /* Portion II: Definitinos only used in Driver */ |
| /****************************************************************************/ |
| /* Macros used by driver */ |
| #define GetIndexIntoMasterTable(MasterOrData, FieldName) (((char *)(&((ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES *)0)->FieldName)-(char *)0)/sizeof(USHORT)) |
| #define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevision)&0x3F) |
| #define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevision)&0x3F) |
| #define GET_DATA_TABLE_MAJOR_REVISION GET_COMMAND_TABLE_COMMANDSET_REVISION |
| #define GET_DATA_TABLE_MINOR_REVISION GET_COMMAND_TABLE_PARAMETER_REVISION |
| /****************************************************************************/ |
| /* Portion III: Definitinos only used in VBIOS */ |
| /****************************************************************************/ |
| #define ATOM_DAC_SRC 0x80 |
| #define ATOM_SRC_DAC1 0 |
| #define ATOM_SRC_DAC2 0x80 |
| #ifdef UEFI_BUILD |
| #define USHORT UTEMP |
| #endif |
| typedef struct _MEMORY_PLLINIT_PARAMETERS { |
| ULONG ulTargetMemoryClock; /* In 10Khz unit */ |
| UCHAR ucAction; /* not define yet */ |
| UCHAR ucFbDiv_Hi; /* Fbdiv Hi byte */ |
| UCHAR ucFbDiv; /* FB value */ |
| UCHAR ucPostDiv; /* Post div */ |
| } MEMORY_PLLINIT_PARAMETERS; |
| #define MEMORY_PLLINIT_PS_ALLOCATION MEMORY_PLLINIT_PARAMETERS |
| #define GPIO_PIN_WRITE 0x01 |
| #define GPIO_PIN_READ 0x00 |
| typedef struct _GPIO_PIN_CONTROL_PARAMETERS { |
| UCHAR ucGPIO_ID; /* return value, read from GPIO pins */ |
| UCHAR ucGPIOBitShift; /* define which bit in uGPIOBitVal need to be update */ |
| UCHAR ucGPIOBitVal; /* Set/Reset corresponding bit defined in ucGPIOBitMask */ |
| UCHAR ucAction; /* =GPIO_PIN_WRITE: Read; =GPIO_PIN_READ: Write */ |
| } GPIO_PIN_CONTROL_PARAMETERS; |
| typedef struct _ENABLE_SCALER_PARAMETERS { |
| UCHAR ucScaler; /* ATOM_SCALER1, ATOM_SCALER2 */ |
| UCHAR ucEnable; /* ATOM_SCALER_DISABLE or ATOM_SCALER_CENTER or ATOM_SCALER_EXPANSION */ |
| UCHAR ucTVStandard; /* */ |
| UCHAR ucPadding[1]; |
| } ENABLE_SCALER_PARAMETERS; |
| #define ENABLE_SCALER_PS_ALLOCATION ENABLE_SCALER_PARAMETERS |
| /* ucEnable: */ |
| #define SCALER_BYPASS_AUTO_CENTER_NO_REPLICATION 0 |
| #define SCALER_BYPASS_AUTO_CENTER_AUTO_REPLICATION 1 |
| #define SCALER_ENABLE_2TAP_ALPHA_MODE 2 |
| #define SCALER_ENABLE_MULTITAP_MODE 3 |
| typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS { |
| ULONG usHWIconHorzVertPosn; /* Hardware Icon Vertical position */ |
| UCHAR ucHWIconVertOffset; /* Hardware Icon Vertical offset */ |
| UCHAR ucHWIconHorzOffset; /* Hardware Icon Horizontal offset */ |
| UCHAR ucSelection; /* ATOM_CURSOR1 or ATOM_ICON1 or ATOM_CURSOR2 or ATOM_ICON2 */ |
| UCHAR ucEnable; /* ATOM_ENABLE or ATOM_DISABLE */ |
| } ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS; |
| typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION { |
| ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS sEnableIcon; |
| ENABLE_CRTC_PARAMETERS sReserved; |
| } ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION; |
| typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS { |
| USHORT usHight; /* Image Hight */ |
| USHORT usWidth; /* Image Width */ |
| UCHAR ucSurface; /* Surface 1 or 2 */ |
| UCHAR ucPadding[3]; |
| } ENABLE_GRAPH_SURFACE_PARAMETERS; |
| typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2 { |
| USHORT usHight; /* Image Hight */ |
| USHORT usWidth; /* Image Width */ |
| UCHAR ucSurface; /* Surface 1 or 2 */ |
| UCHAR ucEnable; /* ATOM_ENABLE or ATOM_DISABLE */ |
| UCHAR ucPadding[2]; |
| } ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2; |
| typedef struct _ENABLE_GRAPH_SURFACE_PS_ALLOCATION { |
| ENABLE_GRAPH_SURFACE_PARAMETERS sSetSurface; |
| ENABLE_YUV_PS_ALLOCATION sReserved; /* Don't set this one */ |
| } ENABLE_GRAPH_SURFACE_PS_ALLOCATION; |
| typedef struct _MEMORY_CLEAN_UP_PARAMETERS { |
| USHORT usMemoryStart; /* in 8Kb boundry, offset from memory base address */ |
| USHORT usMemorySize; /* 8Kb blocks aligned */ |
| } MEMORY_CLEAN_UP_PARAMETERS; |
| #define MEMORY_CLEAN_UP_PS_ALLOCATION MEMORY_CLEAN_UP_PARAMETERS |
| typedef struct _GET_DISPLAY_SURFACE_SIZE_PARAMETERS { |
| USHORT usX_Size; /* When use as input parameter, usX_Size indicates which CRTC */ |
| USHORT usY_Size; |
| } GET_DISPLAY_SURFACE_SIZE_PARAMETERS; |
| typedef struct _INDIRECT_IO_ACCESS { |
| ATOM_COMMON_TABLE_HEADER sHeader; |
| UCHAR IOAccessSequence[256]; |
| } INDIRECT_IO_ACCESS; |
| #define INDIRECT_READ 0x00 |
| #define INDIRECT_WRITE 0x80 |
| #define INDIRECT_IO_MM 0 |
| #define INDIRECT_IO_PLL 1 |
| #define INDIRECT_IO_MC 2 |
| #define INDIRECT_IO_PCIE 3 |
| #define INDIRECT_IO_PCIEP 4 |
| #define INDIRECT_IO_NBMISC 5 |
| #define INDIRECT_IO_PLL_READ INDIRECT_IO_PLL | INDIRECT_READ |
| #define INDIRECT_IO_PLL_WRITE INDIRECT_IO_PLL | INDIRECT_WRITE |
| #define INDIRECT_IO_MC_READ INDIRECT_IO_MC | INDIRECT_READ |
| #define INDIRECT_IO_MC_WRITE INDIRECT_IO_MC | INDIRECT_WRITE |
| #define INDIRECT_IO_PCIE_READ INDIRECT_IO_PCIE | INDIRECT_READ |
| #define INDIRECT_IO_PCIE_WRITE INDIRECT_IO_PCIE | INDIRECT_WRITE |
| #define INDIRECT_IO_PCIEP_READ INDIRECT_IO_PCIEP | INDIRECT_READ |
| #define INDIRECT_IO_PCIEP_WRITE INDIRECT_IO_PCIEP | INDIRECT_WRITE |
| #define INDIRECT_IO_NBMISC_READ INDIRECT_IO_NBMISC | INDIRECT_READ |
| #define INDIRECT_IO_NBMISC_WRITE INDIRECT_IO_NBMISC | INDIRECT_WRITE |
| typedef struct _ATOM_OEM_INFO { |
| ATOM_COMMON_TABLE_HEADER sHeader; |
| ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; |
| } ATOM_OEM_INFO; |
| typedef struct _ATOM_TV_MODE { |
| UCHAR ucVMode_Num; /* Video mode number */ |
| UCHAR ucTV_Mode_Num; /* Internal TV mode number */ |
| } ATOM_TV_MODE; |
| typedef struct _ATOM_BIOS_INT_TVSTD_MODE { |
| ATOM_COMMON_TABLE_HEADER sHeader; |
| USHORT usTV_Mode_LUT_Offset; /* Pointer to standard to internal number conversion table */ |
| USHORT usTV_FIFO_Offset; /* Pointer to FIFO entry table */ |
| USHORT usNTSC_Tbl_Offset; /* Pointer to SDTV_Mode_NTSC table */ |
| USHORT usPAL_Tbl_Offset; /* Pointer to SDTV_Mode_PAL table */ |
| USHORT usCV_Tbl_Offset; /* Pointer to SDTV_Mode_PAL table */ |
| } ATOM_BIOS_INT_TVSTD_MODE; |
| typedef struct _ATOM_TV_MODE_SCALER_PTR { |
| USHORT ucFilter0_Offset; /* Pointer to filter format 0 coefficients */ |
| USHORT usFilter1_Offset; /* Pointer to filter format 0 coefficients */ |
| UCHAR ucTV_Mode_Num; |
| } ATOM_TV_MODE_SCALER_PTR; |
| typedef struct _ATOM_STANDARD_VESA_TIMING { |
| ATOM_COMMON_TABLE_HEADER sHeader; |
| ATOM_DTD_FORMAT aModeTimings[16]; /* 16 is not the real array number, just for initial allocation */ |
| } ATOM_STANDARD_VESA_TIMING; |
| typedef struct _ATOM_STD_FORMAT { |
| USHORT usSTD_HDisp; |
| USHORT usSTD_VDisp; |
| USHORT usSTD_RefreshRate; |
| USHORT usReserved; |
| } ATOM_STD_FORMAT; |
| typedef struct _ATOM_VESA_TO_EXTENDED_MODE { |
| USHORT usVESA_ModeNumber; |
| USHORT usExtendedModeNumber; |
| } ATOM_VESA_TO_EXTENDED_MODE; |
| typedef struct _ATOM_VESA_TO_INTENAL_MODE_LUT { |
| ATOM_COMMON_TABLE_HEADER sHeader; |
| ATOM_VESA_TO_EXTENDED_MODE asVESA_ToExtendedModeInfo[76]; |
| } ATOM_VESA_TO_INTENAL_MODE_LUT; |
| /*************** ATOM Memory Related Data Structure ***********************/ |
| typedef struct _ATOM_MEMORY_VENDOR_BLOCK { |
| UCHAR ucMemoryType; |
| UCHAR ucMemoryVendor; |
| UCHAR ucAdjMCId; |
| UCHAR ucDynClkId; |
| ULONG ulDllResetClkRange; |
| } ATOM_MEMORY_VENDOR_BLOCK; |
| typedef struct _ATOM_MEMORY_SETTING_ID_CONFIG { |
| #if ATOM_BIG_ENDIAN |
| ULONG ucMemBlkId:8; |
| ULONG ulMemClockRange:24; |
| #else |
| ULONG ulMemClockRange:24; |
| ULONG ucMemBlkId:8; |
| #endif |
| } ATOM_MEMORY_SETTING_ID_CONFIG; |
| typedef union _ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS { |
| ATOM_MEMORY_SETTING_ID_CONFIG slAccess; |
| ULONG ulAccess; |
| } ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS; |
| typedef struct _ATOM_MEMORY_SETTING_DATA_BLOCK { |
| ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS ulMemoryID; |
| ULONG aulMemData[1]; |
| } ATOM_MEMORY_SETTING_DATA_BLOCK; |
| typedef struct _ATOM_INIT_REG_INDEX_FORMAT { |
| USHORT usRegIndex; /* MC register index */ |
| UCHAR ucPreRegDataLength; /* offset in ATOM_INIT_REG_DATA_BLOCK.saRegDataBuf */ |
| } ATOM_INIT_REG_INDEX_FORMAT; |
| typedef struct _ATOM_INIT_REG_BLOCK { |
| USHORT usRegIndexTblSize; /* size of asRegIndexBuf */ |
| USHORT usRegDataBlkSize; /* size of ATOM_MEMORY_SETTING_DATA_BLOCK */ |
| ATOM_INIT_REG_INDEX_FORMAT asRegIndexBuf[1]; |
| ATOM_MEMORY_SETTING_DATA_BLOCK asRegDataBuf[1]; |
| } ATOM_INIT_REG_BLOCK; |
| #define END_OF_REG_INDEX_BLOCK 0x0ffff |
| #define END_OF_REG_DATA_BLOCK 0x00000000 |
| #define ATOM_INIT_REG_MASK_FLAG 0x80 |
| #define CLOCK_RANGE_HIGHEST 0x00ffffff |
| #define VALUE_DWORD SIZEOF ULONG |
| #define VALUE_SAME_AS_ABOVE 0 |
| #define VALUE_MASK_DWORD 0x84 |
| #define INDEX_ACCESS_RANGE_BEGIN (VALUE_DWORD + 1) |
| #define INDEX_ACCESS_RANGE_END (INDEX_ACCESS_RANGE_BEGIN + 1) |
| #define VALUE_INDEX_ACCESS_SINGLE (INDEX_ACCESS_RANGE_END + 1) |
| typedef struct _ATOM_MC_INIT_PARAM_TABLE { |
| ATOM_COMMON_TABLE_HEADER sHeader; |
| USHORT usAdjustARB_SEQDataOffset; |
| USHORT usMCInitMemTypeTblOffset; |
| USHORT usMCInitCommonTblOffset; |
| USHORT usMCInitPowerDownTblOffset; |
| ULONG ulARB_SEQDataBuf[32]; |
| ATOM_INIT_REG_BLOCK asMCInitMemType; |
| ATOM_INIT_REG_BLOCK asMCInitCommon; |
| } ATOM_MC_INIT_PARAM_TABLE; |
| #define _4Mx16 0x2 |
| #define _4Mx32 0x3 |
| #define _8Mx16 0x12 |
| #define _8Mx32 0x13 |
| #define _16Mx16 0x22 |
| #define _16Mx32 0x23 |
| #define _32Mx16 0x32 |
| #define _32Mx32 0x33 |
| #define _64Mx8 0x41 |
| #define _64Mx16 0x42 |
| #define SAMSUNG 0x1 |
| #define INFINEON 0x2 |
| #define ELPIDA 0x3 |
| #define ETRON 0x4 |
| #define NANYA 0x5 |
| #define HYNIX 0x6 |
| #define MOSEL 0x7 |
| #define WINBOND 0x8 |
| #define ESMT 0x9 |
| #define MICRON 0xF |
| #define QIMONDA INFINEON |
| #define PROMOS MOSEL |
| /* ///////////Support for GDDR5 MC uCode to reside in upper 64K of ROM///////////// */ |
| #define UCODE_ROM_START_ADDRESS 0x1c000 |
| #define UCODE_SIGNATURE 0x4375434d /* 'MCuC' - MC uCode */ |
| /* uCode block header for reference */ |
| typedef struct _MCuCodeHeader { |
| ULONG ulSignature; |
| UCHAR ucRevision; |
| UCHAR ucChecksum; |
| UCHAR ucReserved1; |
| UCHAR ucReserved2; |
| USHORT usParametersLength; |
| USHORT usUCodeLength; |
| USHORT usReserved1; |
| USHORT usReserved2; |
| } MCuCodeHeader; |
| /* //////////////////////////////////////////////////////////////////////////////// */ |
| #define ATOM_MAX_NUMBER_OF_VRAM_MODULE 16 |
| #define ATOM_VRAM_MODULE_MEMORY_VENDOR_ID_MASK 0xF |
| typedef struct _ATOM_VRAM_MODULE_V1 { |
| ULONG ulReserved; |
| USHORT usEMRSValue; |
| USHORT usMRSValue; |
| USHORT usReserved; |
| UCHAR ucExtMemoryID; /* An external indicator (by hardcode, callback or pin) to tell what is the current memory module */ |
| UCHAR ucMemoryType; /* [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] reserved; */ |
| UCHAR ucMemoryVenderID; /* Predefined,never change across designs or memory type/vender */ |
| UCHAR ucMemoryDeviceCfg; /* [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32... */ |
| UCHAR ucRow; /* Number of Row,in power of 2; */ |
| UCHAR ucColumn; /* Number of Column,in power of 2; */ |
| UCHAR ucBank; /* Nunber of Bank; */ |
| UCHAR ucRank; /* Number of Rank, in power of 2 */ |
| UCHAR ucChannelNum; /* Number of channel; */ |
| UCHAR ucChannelConfig; /* [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2 */ |
| UCHAR ucDefaultMVDDQ_ID; /* Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data; */ |
| UCHAR ucDefaultMVDDC_ID; /* Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data; */ |
| UCHAR ucReserved[2]; |
| } ATOM_VRAM_MODULE_V1; |
| typedef struct _ATOM_VRAM_MODULE_V2 { |
| ULONG ulReserved; |
| ULONG ulFlags; /* To enable/disable functionalities based on memory type */ |
| ULONG ulEngineClock; /* Override of default engine clock for particular memory type */ |
| ULONG ulMemoryClock; /* Override of default memory clock for particular memory type */ |
| USHORT usEMRS2Value; /* EMRS2 Value is used for GDDR2 and GDDR4 memory type */ |
| USHORT usEMRS3Value; /* EMRS3 Value is used for GDDR2 and GDDR4 memory type */ |
| USHORT usEMRSValue; |
| USHORT usMRSValue; |
| USHORT usReserved; |
| UCHAR ucExtMemoryID; /* An external indicator (by hardcode, callback or pin) to tell what is the current memory module */ |
| UCHAR ucMemoryType; /* [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now; */ |
| UCHAR ucMemoryVenderID; /* Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed */ |
| UCHAR ucMemoryDeviceCfg; /* [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32... */ |
| UCHAR ucRow; /* Number of Row,in power of 2; */ |
| UCHAR ucColumn; /* Number of Column,in power of 2; */ |
| UCHAR ucBank; /* Nunber of Bank; */ |
| UCHAR ucRank; /* Number of Rank, in power of 2 */ |
| UCHAR ucChannelNum; /* Number of channel; */ |
| UCHAR ucChannelConfig; /* [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2 */ |
| UCHAR ucDefaultMVDDQ_ID; /* Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data; */ |
| UCHAR ucDefaultMVDDC_ID; /* Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data; */ |
| UCHAR ucRefreshRateFactor; |
| UCHAR ucReserved[3]; |
| } ATOM_VRAM_MODULE_V2; |
| typedef struct _ATOM_MEMORY_TIMING_FORMAT { |
| ULONG ulClkRange; /* memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing */ |
| union { |
| USHORT usMRS; /* mode register */ |
| USHORT usDDR3_MR0; |
| }; |
| union { |
| USHORT usEMRS; /* extended mode register */ |
| USHORT usDDR3_MR1; |
| }; |
| UCHAR ucCL; /* CAS latency */ |
| UCHAR ucWL; /* WRITE Latency */ |
| UCHAR uctRAS; /* tRAS */ |
| UCHAR uctRC; /* tRC */ |
| UCHAR uctRFC; /* tRFC */ |
| UCHAR uctRCDR; /* tRCDR */ |
| UCHAR uctRCDW; /* tRCDW */ |
| UCHAR uctRP; /* tRP */ |
| UCHAR uctRRD; /* tRRD */ |
| UCHAR uctWR; /* tWR */ |
| UCHAR uctWTR; /* tWTR */ |
| UCHAR uctPDIX; /* tPDIX */ |
| UCHAR uctFAW; /* tFAW */ |
| UCHAR uctAOND; /* tAOND */ |
| union { |
| struct { |
| UCHAR ucflag; /* flag to control memory timing calculation. bit0= control EMRS2 Infineon */ |
| UCHAR ucReserved; |
| }; |
| USHORT usDDR3_MR2; |
| }; |
| } ATOM_MEMORY_TIMING_FORMAT; |
| typedef struct _ATOM_MEMORY_TIMING_FORMAT_V1 { |
| ULONG ulClkRange; /* memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing */ |
| USHORT usMRS; /* mode register */ |
| USHORT usEMRS; /* extended mode register */ |
| UCHAR ucCL; /* CAS latency */ |
| UCHAR ucWL; /* WRITE Latency */ |
| UCHAR uctRAS; /* tRAS */ |
| UCHAR uctRC; /* tRC */ |
| UCHAR uctRFC; /* tRFC */ |
| UCHAR uctRCDR; /* tRCDR */ |
| UCHAR uctRCDW; /* tRCDW */ |
| UCHAR uctRP; /* tRP */ |
| UCHAR uctRRD; /* tRRD */ |
| UCHAR uctWR; /* tWR */ |
| UCHAR uctWTR; /* tWTR */ |
| UCHAR uctPDIX; /* tPDIX */ |
| UCHAR uctFAW; /* tFAW */ |
| UCHAR uctAOND; /* tAOND */ |
| UCHAR ucflag; /* flag to control memory timing calculation. bit0= control EMRS2 Infineon */ |
| /* ///////////////////////GDDR parameters/////////////////////////////////// */ |
| UCHAR uctCCDL; /* */ |
| UCHAR uctCRCRL; /* */ |
| UCHAR uctCRCWL; /* */ |
| UCHAR uctCKE; /* */ |
| UCHAR uctCKRSE; /* */ |
| UCHAR uctCKRSX; /* */ |
| UCHAR uctFAW32; /* */ |
| UCHAR ucReserved1; /* */ |
| UCHAR ucReserved2; /* */ |
| UCHAR ucTerminator; |
| } ATOM_MEMORY_TIMING_FORMAT_V1; |
| typedef struct _ATOM_MEMORY_FORMAT { |
| ULONG ulDllDisClock; /* memory DLL will be disable when target memory clock is below this clock */ |
| union { |
| USHORT usEMRS2Value; /* EMRS2 Value is used for GDDR2 and GDDR4 memory type */ |
| USHORT usDDR3_Reserved; /* Not used for DDR3 memory */ |
| }; |
| union { |
| USHORT usEMRS3Value; /* EMRS3 Value is used for GDDR2 and GDDR4 memory type */ |
| USHORT usDDR3_MR3; /* Used for DDR3 memory */ |
| }; |
| UCHAR ucMemoryType; /* [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now; */ |
| UCHAR ucMemoryVenderID; /* Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed */ |
| UCHAR ucRow; /* Number of Row,in power of 2; */ |
| UCHAR ucColumn; /* Number of Column,in power of 2; */ |
| UCHAR ucBank; /* Nunber of Bank; */ |
| UCHAR ucRank; /* Number of Rank, in power of 2 */ |
| UCHAR ucBurstSize; /* burst size, 0= burst size=4 1= burst size=8 */ |
| UCHAR ucDllDisBit; /* position of DLL Enable/Disable bit in EMRS ( Extended Mode Register ) */ |
| UCHAR ucRefreshRateFactor; /* memory refresh rate in unit of ms */ |
| UCHAR ucDensity; /* _8Mx32, _16Mx32, _16Mx16, _32Mx16 */ |
| UCHAR ucPreamble; /* [7:4] Write Preamble, [3:0] Read Preamble */ |
| UCHAR ucMemAttrib; /* Memory Device Addribute, like RDBI/WDBI etc */ |
| ATOM_MEMORY_TIMING_FORMAT asMemTiming[5]; /* Memory Timing block sort from lower clock to higher clock */ |
| } ATOM_MEMORY_FORMAT; |
| typedef struct _ATOM_VRAM_MODULE_V3 { |
| ULONG ulChannelMapCfg; /* board dependent paramenter:Channel combination */ |
| USHORT usSize; /* size of ATOM_VRAM_MODULE_V3 */ |
| USHORT usDefaultMVDDQ; /* board dependent parameter:Default Memory Core Voltage */ |
| USHORT usDefaultMVDDC; /* board dependent parameter:Default Memory IO Voltage */ |
| UCHAR ucExtMemoryID; /* An external indicator (by hardcode, callback or pin) to tell what is the current memory module */ |
| UCHAR ucChannelNum; /* board dependent parameter:Number of channel; */ |
| UCHAR ucChannelSize; /* board dependent parameter:32bit or 64bit */ |
| UCHAR ucVREFI; /* board dependnt parameter: EXT or INT +160mv to -140mv */ |
| UCHAR ucNPL_RT; /* board dependent parameter:NPL round trip delay, used for calculate memory timing parameters */ |
| UCHAR ucFlag; /* To enable/disable functionalities based on memory type */ |
| ATOM_MEMORY_FORMAT asMemory; /* describ all of video memory parameters from memory spec */ |
| } ATOM_VRAM_MODULE_V3; |
| /* ATOM_VRAM_MODULE_V3.ucNPL_RT */ |
| #define NPL_RT_MASK 0x0f |
| #define BATTERY_ODT_MASK 0xc0 |
| #define ATOM_VRAM_MODULE ATOM_VRAM_MODULE_V3 |
| typedef struct _ATOM_VRAM_MODULE_V4 { |
| ULONG ulChannelMapCfg; /* board dependent parameter: Channel combination */ |
| USHORT usModuleSize; /* size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE */ |
| USHORT usPrivateReserved; /* BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! */ |
| /* MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) */ |
| USHORT usReserved; |
| UCHAR ucExtMemoryID; /* An external indicator (by hardcode, callback or pin) to tell what is the current memory module */ |
| UCHAR ucMemoryType; /* [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; */ |
| UCHAR ucChannelNum; /* Number of channels present in this module config */ |
| UCHAR ucChannelWidth; /* 0 - 32 bits; 1 - 64 bits */ |
| UCHAR ucDensity; /* _8Mx32, _16Mx32, _16Mx16, _32Mx16 */ |
| UCHAR ucFlag; /* To enable/disable functionalities based on memory type */ |
| UCHAR ucMisc; /* bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 */ |
| UCHAR ucVREFI; /* board dependent parameter */ |
| UCHAR ucNPL_RT; /* board dependent parameter:NPL round trip delay, used for calculate memory timing parameters */ |
| UCHAR ucPreamble; /* [7:4] Write Preamble, [3:0] Read Preamble */ |
| UCHAR ucMemorySize; /* BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! */ |
| /* Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros */ |
| UCHAR ucReserved[3]; |
| /* compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level */ |
| union { |
| USHORT usEMRS2Value; /* EMRS2 Value is used for GDDR2 and GDDR4 memory type */ |
| USHORT usDDR3_Reserved; |
| }; |
| union { |
| USHORT usEMRS3Value; /* EMRS3 Value is used for GDDR2 and GDDR4 memory type */ |
| USHORT usDDR3_MR3; /* Used for DDR3 memory */ |
| }; |
| UCHAR ucMemoryVenderID; /* Predefined, If not predefined, vendor detection table gets executed */ |
| UCHAR ucRefreshRateFactor; /* [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) */ |
| UCHAR ucReserved2[2]; |
| ATOM_MEMORY_TIMING_FORMAT asMemTiming[5]; /* Memory Timing block sort from lower clock to higher clock */ |
| } ATOM_VRAM_MODULE_V4; |
| #define VRAM_MODULE_V4_MISC_RANK_MASK 0x3 |
| #define VRAM_MODULE_V4_MISC_DUAL_RANK 0x1 |
| #define VRAM_MODULE_V4_MISC_BL_MASK 0x4 |
| #define VRAM_MODULE_V4_MISC_BL8 0x4 |
| #define VRAM_MODULE_V4_MISC_DUAL_CS 0x10 |
| typedef struct _ATOM_VRAM_MODULE_V5 { |
| ULONG ulChannelMapCfg; /* board dependent parameter: Channel combination */ |
| USHORT usModuleSize; /* size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE */ |
| USHORT usPrivateReserved; /* BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! */ |
| /* MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) */ |
| USHORT usReserved; |
| UCHAR ucExtMemoryID; /* An external indicator (by hardcode, callback or pin) to tell what is the current memory module */ |
| UCHAR ucMemoryType; /* [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; */ |
| UCHAR ucChannelNum; /* Number of channels present in this module config */ |
| UCHAR ucChannelWidth; /* 0 - 32 bits; 1 - 64 bits */ |
| UCHAR ucDensity; /* _8Mx32, _16Mx32, _16Mx16, _32Mx16 */ |
| UCHAR ucFlag; /* To enable/disable functionalities based on memory type */ |
| UCHAR ucMisc; /* bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 */ |
| UCHAR ucVREFI; /* board dependent parameter */ |
| UCHAR ucNPL_RT; /* board dependent parameter:NPL round trip delay, used for calculate memory timing parameters */ |
| UCHAR ucPreamble; /* [7:4] Write Preamble, [3:0] Read Preamble */ |
| UCHAR ucMemorySize; /* BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! */ |
| /* Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros */ |
| UCHAR ucReserved[3]; |
| /* compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level */ |
| USHORT usEMRS2Value; /* EMRS2 Value is used for GDDR2 and GDDR4 memory type */ |
| USHORT usEMRS3Value; /* EMRS3 Value is used for GDDR2 and GDDR4 memory type */ |
| UCHAR ucMemoryVenderID; /* Predefined, If not predefined, vendor detection table gets executed */ |
| UCHAR ucRefreshRateFactor; /* [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) */ |
| UCHAR ucFIFODepth; /* FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth */ |
| UCHAR ucCDR_Bandwidth; /* [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth */ |
| ATOM_MEMORY_TIMING_FORMAT_V1 asMemTiming[5]; /* Memory Timing block sort from lower clock to higher clock */ |
| } ATOM_VRAM_MODULE_V5; |
| typedef struct _ATOM_VRAM_INFO_V2 { |
| ATOM_COMMON_TABLE_HEADER sHeader; |
| UCHAR ucNumOfVRAMModule; |
| ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; /* just for allocation, real number of blocks is in ucNumOfVRAMModule; */ |
| } ATOM_VRAM_INFO_V2; |
| typedef struct _ATOM_VRAM_INFO_V3 { |
| ATOM_COMMON_TABLE_HEADER sHeader; |
| USHORT usMemAdjustTblOffset; /* offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting */ |
| USHORT usMemClkPatchTblOffset; /* offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting */ |
| USHORT usRerseved; |
| UCHAR aVID_PinsShift[9]; /* 8 bit strap maximum+terminator */ |
| UCHAR ucNumOfVRAMModule; |
| ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; /* just for allocation, real number of blocks is in ucNumOfVRAMModule; */ |
| ATOM_INIT_REG_BLOCK asMemPatch; /* for allocation */ |
| /* ATOM_INIT_REG_BLOCK aMemAdjust; */ |
| } ATOM_VRAM_INFO_V3; |
| #define ATOM_VRAM_INFO_LAST ATOM_VRAM_INFO_V3 |
| typedef struct _ATOM_VRAM_INFO_V4 { |
| ATOM_COMMON_TABLE_HEADER sHeader; |
| USHORT usMemAdjustTblOffset; /* offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting */ |
| USHORT usMemClkPatchTblOffset; /* offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting */ |
| USHORT usRerseved; |
| UCHAR ucMemDQ7_0ByteRemap; /* DQ line byte remap, =0: Memory Data line BYTE0, =1: BYTE1, =2: BYTE2, =3: BYTE3 */ |
| ULONG ulMemDQ7_0BitRemap; /* each DQ line ( 7~0) use 3bits, like: DQ0=Bit[2:0], DQ1:[5:3], ... DQ7:[23:21] */ |
| UCHAR ucReservde[4]; |
| UCHAR ucNumOfVRAMModule; |
| ATOM_VRAM_MODULE_V4 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; /* just for allocation, real number of blocks is in ucNumOfVRAMModule; */ |
| ATOM_INIT_REG_BLOCK asMemPatch; /* for allocation */ |
| /* ATOM_INIT_REG_BLOCK aMemAdjust; */ |
| } ATOM_VRAM_INFO_V4; |
| typedef struct _ATOM_VRAM_GPIO_DETECTION_INFO { |
| ATOM_COMMON_TABLE_HEADER sHeader; |
| UCHAR aVID_PinsShift[9]; /* 8 bit strap maximum+terminator */ |
| } ATOM_VRAM_GPIO_DETECTION_INFO; |
| typedef struct _ATOM_MEMORY_TRAINING_INFO { |
| ATOM_COMMON_TABLE_HEADER sHeader; |
| UCHAR ucTrainingLoop; |
| UCHAR ucReserved[3]; |
| ATOM_INIT_REG_BLOCK asMemTrainingSetting; |
| } ATOM_MEMORY_TRAINING_INFO; |
| typedef struct SW_I2C_CNTL_DATA_PARAMETERS { |
| UCHAR ucControl; |
| UCHAR ucData; |
| UCHAR ucSatus; |
| UCHAR ucTemp; |
| } SW_I2C_CNTL_DATA_PARAMETERS; |
| #define SW_I2C_CNTL_DATA_PS_ALLOCATION SW_I2C_CNTL_DATA_PARAMETERS |
| typedef struct _SW_I2C_IO_DATA_PARAMETERS { |
| USHORT GPIO_Info; |
| UCHAR ucAct; |
| UCHAR ucData; |
| } SW_I2C_IO_DATA_PARAMETERS; |
| #define SW_I2C_IO_DATA_PS_ALLOCATION SW_I2C_IO_DATA_PARAMETERS |
| /****************************SW I2C CNTL DEFINITIONS**********************/ |
| #define SW_I2C_IO_RESET 0 |
| #define SW_I2C_IO_GET 1 |
| #define SW_I2C_IO_DRIVE 2 |
| #define SW_I2C_IO_SET 3 |
| #define SW_I2C_IO_START 4 |
| #define SW_I2C_IO_CLOCK 0 |
| #define SW_I2C_IO_DATA 0x80 |
| #define SW_I2C_IO_ZERO 0 |
| #define SW_I2C_IO_ONE 0x100 |
| #define SW_I2C_CNTL_READ 0 |
| #define SW_I2C_CNTL_WRITE 1 |
| #define SW_I2C_CNTL_START 2 |
| #define SW_I2C_CNTL_STOP 3 |
| #define SW_I2C_CNTL_OPEN 4 |
| #define SW_I2C_CNTL_CLOSE 5 |
| #define SW_I2C_CNTL_WRITE1BIT 6 |
| /* ==============================VESA definition Portion=============================== */ |
| #define VESA_OEM_PRODUCT_REV '01.00' |
| #define VESA_MODE_ATTRIBUTE_MODE_SUPPORT 0xBB /* refer to VBE spec p.32, no TTY support */ |
| #define VESA_MODE_WIN_ATTRIBUTE 7 |
| #define VESA_WIN_SIZE 64 |
| typedef struct _PTR_32_BIT_STRUCTURE { |
| USHORT Offset16; |
| USHORT Segment16; |
| } PTR_32_BIT_STRUCTURE; |
| typedef union _PTR_32_BIT_UNION { |
| PTR_32_BIT_STRUCTURE SegmentOffset; |
| ULONG Ptr32_Bit; |
| } PTR_32_BIT_UNION; |
| typedef struct _VBE_1_2_INFO_BLOCK_UPDATABLE { |
| UCHAR VbeSignature[4]; |
| USHORT VbeVersion; |
| PTR_32_BIT_UNION OemStringPtr; |
| UCHAR Capabilities[4]; |
| PTR_32_BIT_UNION VideoModePtr; |
| USHORT TotalMemory; |
| } VBE_1_2_INFO_BLOCK_UPDATABLE; |
| typedef struct _VBE_2_0_INFO_BLOCK_UPDATABLE { |
| VBE_1_2_INFO_BLOCK_UPDATABLE CommonBlock; |
| USHORT OemSoftRev; |
| PTR_32_BIT_UNION OemVendorNamePtr; |
| PTR_32_BIT_UNION OemProductNamePtr; |
| PTR_32_BIT_UNION OemProductRevPtr; |
| } VBE_2_0_INFO_BLOCK_UPDATABLE; |
| typedef union _VBE_VERSION_UNION { |
| VBE_2_0_INFO_BLOCK_UPDATABLE VBE_2_0_InfoBlock; |
| VBE_1_2_INFO_BLOCK_UPDATABLE VBE_1_2_InfoBlock; |
| } VBE_VERSION_UNION; |
| typedef struct _VBE_INFO_BLOCK { |
| VBE_VERSION_UNION UpdatableVBE_Info; |
| UCHAR Reserved[222]; |
| UCHAR OemData[256]; |
| } VBE_INFO_BLOCK; |
| typedef struct _VBE_FP_INFO { |
| USHORT HSize; |
| USHORT VSize; |
| USHORT FPType; |
| UCHAR RedBPP; |
| UCHAR GreenBPP; |
| UCHAR BlueBPP; |
| UCHAR ReservedBPP; |
| ULONG RsvdOffScrnMemSize; |
| ULONG RsvdOffScrnMEmPtr; |
| UCHAR Reserved[14]; |
| } VBE_FP_INFO; |
| typedef struct _VESA_MODE_INFO_BLOCK { |
| /* Mandatory information for all VBE revisions */ |
| USHORT ModeAttributes; /* dw ? ; mode attributes */ |
| UCHAR WinAAttributes; /* db ? ; window A attributes */ |
| UCHAR WinBAttributes; /* db ? ; window B attributes */ |
| USHORT WinGranularity; /* dw ? ; window granularity */ |
| USHORT WinSize; /* dw ? ; window size */ |
| USHORT WinASegment; /* dw ? ; window A start segment */ |
| USHORT WinBSegment; /* dw ? ; window B start segment */ |
| ULONG WinFuncPtr; /* dd ? ; real mode pointer to window function */ |
| USHORT BytesPerScanLine; /* dw ? ; bytes per scan line */ |
| /* ; Mandatory information for VBE 1.2 and above */ |
| USHORT XResolution; /* dw ? ; horizontal resolution in pixels or characters */ |
| USHORT YResolution; /* dw ? ; vertical resolution in pixels or characters */ |
| UCHAR XCharSize; /* db ? ; character cell width in pixels */ |
| UCHAR YCharSize; /* db ? ; character cell height in pixels */ |
| UCHAR NumberOfPlanes; /* db ? ; number of memory planes */ |
| UCHAR BitsPerPixel; /* db ? ; bits per pixel */ |
| UCHAR NumberOfBanks; /* db ? ; number of banks */ |
| UCHAR MemoryModel; /* db ? ; memory model type */ |
| UCHAR BankSize; /* db ? ; bank size in KB */ |
| UCHAR NumberOfImagePages; /* db ? ; number of images */ |
| UCHAR ReservedForPageFunction; /* db 1 ; reserved for page function */ |
| /* ; Direct Color fields(required for direct/6 and YUV/7 memory models) */ |
| UCHAR RedMaskSize; /* db ? ; size of direct color red mask in bits */ |
| UCHAR RedFieldPosition; /* db ? ; bit position of lsb of red mask */ |
| UCHAR GreenMaskSize; /* db ? ; size of direct color green mask in bits */ |
| UCHAR GreenFieldPosition; /* db ? ; bit position of lsb of green mask */ |
| UCHAR BlueMaskSize; /* db ? ; size of direct color blue mask in bits */ |
| UCHAR BlueFieldPosition; /* db ? ; bit position of lsb of blue mask */ |
| UCHAR RsvdMaskSize; /* db ? ; size of direct color reserved mask in bits */ |
| UCHAR RsvdFieldPosition; /* db ? ; bit position of lsb of reserved mask */ |
| UCHAR DirectColorModeInfo; /* db ? ; direct color mode attributes */ |
| /* ; Mandatory information for VBE 2.0 and above */ |
| ULONG PhysBasePtr; /* dd ? ; physical address for flat memory frame buffer */ |
| ULONG Reserved_1; /* dd 0 ; reserved - always set to 0 */ |
| USHORT Reserved_2; /* dw 0 ; reserved - always set to 0 */ |
| /* ; Mandatory information for VBE 3.0 and above */ |
| USHORT LinBytesPerScanLine; /* dw ? ; bytes per scan line for linear modes */ |
| UCHAR BnkNumberOfImagePages; /* db ? ; number of images for banked modes */ |
| UCHAR LinNumberOfImagPages; /* db ? ; number of images for linear modes */ |
| UCHAR LinRedMaskSize; /* db ? ; size of direct color red mask(linear modes) */ |
| UCHAR LinRedFieldPosition; /* db ? ; bit position of lsb of red mask(linear modes) */ |
| UCHAR LinGreenMaskSize; /* db ? ; size of direct color green mask(linear modes) */ |
| UCHAR LinGreenFieldPosition; /* db ? ; bit position of lsb of green mask(linear modes) */ |
| UCHAR LinBlueMaskSize; /* db ? ; size of direct color blue mask(linear modes) */ |
| UCHAR LinBlueFieldPosition; /* db ? ; bit position of lsb of blue mask(linear modes) */ |
| UCHAR LinRsvdMaskSize; /* db ? ; size of direct color reserved mask(linear modes) */ |
| UCHAR LinRsvdFieldPosition; /* db ? ; bit position of lsb of reserved mask(linear modes) */ |
| ULONG MaxPixelClock; /* dd ? ; maximum pixel clock(in Hz) for graphics mode */ |
| UCHAR Reserved; /* db 190 dup (0) */ |
| } VESA_MODE_INFO_BLOCK; |
| /* BIOS function CALLS */ |
| #define ATOM_BIOS_EXTENDED_FUNCTION_CODE 0xA0 /* ATI Extended Function code */ |
| #define ATOM_BIOS_FUNCTION_COP_MODE 0x00 |
| #define ATOM_BIOS_FUNCTION_SHORT_QUERY1 0x04 |
| #define ATOM_BIOS_FUNCTION_SHORT_QUERY2 0x05 |
| #define ATOM_BIOS_FUNCTION_SHORT_QUERY3 0x06 |
| #define ATOM_BIOS_FUNCTION_GET_DDC 0x0B |
| #define ATOM_BIOS_FUNCTION_ASIC_DSTATE 0x0E |
| #define ATOM_BIOS_FUNCTION_DEBUG_PLAY 0x0F |
| #define ATOM_BIOS_FUNCTION_STV_STD 0x16 |
| #define ATOM_BIOS_FUNCTION_DEVICE_DET 0x17 |
| #define ATOM_BIOS_FUNCTION_DEVICE_SWITCH 0x18 |
| #define ATOM_BIOS_FUNCTION_PANEL_CONTROL 0x82 |
| #define ATOM_BIOS_FUNCTION_OLD_DEVICE_DET 0x83 |
| #define ATOM_BIOS_FUNCTION_OLD_DEVICE_SWITCH 0x84 |
| #define ATOM_BIOS_FUNCTION_HW_ICON 0x8A |
| #define ATOM_BIOS_FUNCTION_SET_CMOS 0x8B |
| #define SUB_FUNCTION_UPDATE_DISPLAY_INFO 0x8000 /* Sub function 80 */ |
| #define SUB_FUNCTION_UPDATE_EXPANSION_INFO 0x8100 /* Sub function 80 */ |
| #define ATOM_BIOS_FUNCTION_DISPLAY_INFO 0x8D |
| #define ATOM_BIOS_FUNCTION_DEVICE_ON_OFF 0x8E |
| #define ATOM_BIOS_FUNCTION_VIDEO_STATE 0x8F |
| #define ATOM_SUB_FUNCTION_GET_CRITICAL_STATE 0x0300 /* Sub function 03 */ |
| #define ATOM_SUB_FUNCTION_GET_LIDSTATE 0x0700 /* Sub function 7 */ |
| #define ATOM_SUB_FUNCTION_THERMAL_STATE_NOTICE 0x1400 /* Notify caller the current thermal state */ |
| #define ATOM_SUB_FUNCTION_CRITICAL_STATE_NOTICE 0x8300 /* Notify caller the current critical state */ |
| #define ATOM_SUB_FUNCTION_SET_LIDSTATE 0x8500 /* Sub function 85 */ |
| #define ATOM_SUB_FUNCTION_GET_REQ_DISPLAY_FROM_SBIOS_MODE 0x8900 /* Sub function 89 */ |
| #define ATOM_SUB_FUNCTION_INFORM_ADC_SUPPORT 0x9400 /* Notify caller that ADC is supported */ |
| #define ATOM_BIOS_FUNCTION_VESA_DPMS 0x4F10 /* Set DPMS */ |
| #define ATOM_SUB_FUNCTION_SET_DPMS 0x0001 /* BL: Sub function 01 */ |
| #define ATOM_SUB_FUNCTION_GET_DPMS 0x0002 /* BL: Sub function 02 */ |
| #define ATOM_PARAMETER_VESA_DPMS_ON 0x0000 /* BH Parameter for DPMS ON. */ |
| #define ATOM_PARAMETER_VESA_DPMS_STANDBY 0x0100 /* BH Parameter for DPMS STANDBY */ |
| #define ATOM_PARAMETER_VESA_DPMS_SUSPEND 0x0200 /* BH Parameter for DPMS SUSPEND */ |
| #define ATOM_PARAMETER_VESA_DPMS_OFF 0x0400 /* BH Parameter for DPMS OFF */ |
| #define ATOM_PARAMETER_VESA_DPMS_REDUCE_ON 0x0800 /* BH Parameter for DPMS REDUCE ON (NOT SUPPORTED) */ |
| #define ATOM_BIOS_RETURN_CODE_MASK 0x0000FF00L |
| #define ATOM_BIOS_REG_HIGH_MASK 0x0000FF00L |
| #define ATOM_BIOS_REG_LOW_MASK 0x000000FFL |
| /* structure used for VBIOS only */ |
| /* DispOutInfoTable */ |
| typedef struct _ASIC_TRANSMITTER_INFO { |
| USHORT usTransmitterObjId; |
| USHORT usSupportDevice; |
| UCHAR ucTransmitterCmdTblId; |
| UCHAR ucConfig; |
| UCHAR ucEncoderID; /* available 1st encoder ( default ) */ |
| UCHAR ucOptionEncoderID; /* available 2nd encoder ( optional ) */ |
| UCHAR uc2ndEncoderID; |
| UCHAR ucReserved; |
| } ASIC_TRANSMITTER_INFO; |
| typedef struct _ASIC_ENCODER_INFO { |
| UCHAR ucEncoderID; |
| UCHAR ucEncoderConfig; |
| USHORT usEncoderCmdTblId; |
| } ASIC_ENCODER_INFO; |
| typedef struct _ATOM_DISP_OUT_INFO { |
| ATOM_COMMON_TABLE_HEADER sHeader; |
| USHORT ptrTransmitterInfo; |
| USHORT ptrEncoderInfo; |
| ASIC_TRANSMITTER_INFO asTransmitterInfo[1]; |
| ASIC_ENCODER_INFO asEncoderInfo[1]; |
| } ATOM_DISP_OUT_INFO; |
| /* DispDevicePriorityInfo */ |
| typedef struct _ATOM_DISPLAY_DEVICE_PRIORITY_INFO { |
| ATOM_COMMON_TABLE_HEADER sHeader; |
| USHORT asDevicePriority[16]; |
| } ATOM_DISPLAY_DEVICE_PRIORITY_INFO; |
| /* ProcessAuxChannelTransactionTable */ |
| typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS { |
| USHORT lpAuxRequest; |
| USHORT lpDataOut; |
| UCHAR ucChannelID; |
| union { |
| UCHAR ucReplyStatus; |
| UCHAR ucDelay; |
| }; |
| UCHAR ucDataOutLen; |
| UCHAR ucReserved; |
| } PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS; |
| #define PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS |
| /* GetSinkType */ |
| typedef struct _DP_ENCODER_SERVICE_PARAMETERS { |
| USHORT ucLinkClock; |
| union { |
| UCHAR ucConfig; /* for DP training command */ |
| UCHAR ucI2cId; /* use for GET_SINK_TYPE command */ |
| }; |
| UCHAR ucAction; |
| UCHAR ucStatus; |
| UCHAR ucLaneNum; |
| UCHAR ucReserved[2]; |
| } DP_ENCODER_SERVICE_PARAMETERS; |
| /* ucAction */ |
| #define ATOM_DP_ACTION_GET_SINK_TYPE 0x01 |
| #define ATOM_DP_ACTION_TRAINING_START 0x02 |
| #define ATOM_DP_ACTION_TRAINING_COMPLETE 0x03 |
| #define ATOM_DP_ACTION_TRAINING_PATTERN_SEL 0x04 |
| #define ATOM_DP_ACTION_SET_VSWING_PREEMP 0x05 |
| #define ATOM_DP_ACTION_GET_VSWING_PREEMP 0x06 |
| #define ATOM_DP_ACTION_BLANKING 0x07 |
| /* ucConfig */ |
| #define ATOM_DP_CONFIG_ENCODER_SEL_MASK 0x03 |
| #define ATOM_DP_CONFIG_DIG1_ENCODER 0x00 |
| #define ATOM_DP_CONFIG_DIG2_ENCODER 0x01 |
| #define ATOM_DP_CONFIG_EXTERNAL_ENCODER 0x02 |
| #define ATOM_DP_CONFIG_LINK_SEL_MASK 0x04 |
| #define ATOM_DP_CONFIG_LINK_A 0x00 |
| #define ATOM_DP_CONFIG_LINK_B 0x04 |
| #define DP_ENCODER_SERVICE_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS |
| /* DP_TRAINING_TABLE */ |
| #define DPCD_SET_LINKRATE_LANENUM_PATTERN1_TBL_ADDR ATOM_DP_TRAINING_TBL_ADDR |
| #define DPCD_SET_SS_CNTL_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 8 ) |
| #define DPCD_SET_LANE_VSWING_PREEMP_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 16) |
| #define DPCD_SET_TRAINING_PATTERN0_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 24) |
| #define DPCD_SET_TRAINING_PATTERN2_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 32) |
| #define DPCD_GET_LINKRATE_LANENUM_SS_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 40) |
| #define DPCD_GET_LANE_STATUS_ADJUST_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 48) |
| #define DP_I2C_AUX_DDC_WRITE_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 60) |
| #define DP_I2C_AUX_DDC_WRITE_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 64) |
| #define DP_I2C_AUX_DDC_READ_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 72) |
| #define DP_I2C_AUX_DDC_READ_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 76) |
| #define DP_I2C_AUX_DDC_READ_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 80) |
| typedef struct _PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS { |
| UCHAR ucI2CSpeed; |
| union { |
| UCHAR ucRegIndex; |
| UCHAR ucStatus; |
| }; |
| USHORT lpI2CDataOut; |
| UCHAR ucFlag; |
| UCHAR ucTransBytes; |
| UCHAR ucSlaveAddr; |
| UCHAR ucLineNumber; |
| } PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS; |
| #define PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS |
| /* ucFlag */ |
| #define HW_I2C_WRITE 1 |
| #define HW_I2C_READ 0 |
| /****************************************************************************/ |
| /* Portion VI: Definitinos being oboselete */ |
| /****************************************************************************/ |
| /* ========================================================================================== */ |
| /* Remove the definitions below when driver is ready! */ |
| typedef struct _ATOM_DAC_INFO { |
| ATOM_COMMON_TABLE_HEADER sHeader; |
| USHORT usMaxFrequency; /* in 10kHz unit */ |
| USHORT usReserved; |
| } ATOM_DAC_INFO; |
| typedef struct _COMPASSIONATE_DATA { |
| ATOM_COMMON_TABLE_HEADER sHeader; |
| /* ============================== DAC1 portion */ |
| UCHAR ucDAC1_BG_Adjustment; |
| UCHAR ucDAC1_DAC_Adjustment; |
| USHORT usDAC1_FORCE_Data; |
| /* ============================== DAC2 portion */ |
| UCHAR ucDAC2_CRT2_BG_Adjustment; |
| UCHAR ucDAC2_CRT2_DAC_Adjustment; |
| USHORT usDAC2_CRT2_FORCE_Data; |
| USHORT usDAC2_CRT2_MUX_RegisterIndex; |
| UCHAR ucDAC2_CRT2_MUX_RegisterInfo; /* Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low */ |
| UCHAR ucDAC2_NTSC_BG_Adjustment; |
| UCHAR ucDAC2_NTSC_DAC_Adjustment; |
| USHORT usDAC2_TV1_FORCE_Data; |
| USHORT usDAC2_TV1_MUX_RegisterIndex; |
| UCHAR ucDAC2_TV1_MUX_RegisterInfo; /* Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low */ |
| UCHAR ucDAC2_CV_BG_Adjustment; |
| UCHAR ucDAC2_CV_DAC_Adjustment; |
| USHORT usDAC2_CV_FORCE_Data; |
| USHORT usDAC2_CV_MUX_RegisterIndex; |
| UCHAR ucDAC2_CV_MUX_RegisterInfo; /* Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low */ |
| UCHAR ucDAC2_PAL_BG_Adjustment; |
| UCHAR ucDAC2_PAL_DAC_Adjustment; |
| USHORT usDAC2_TV2_FORCE_Data; |
| } COMPASSIONATE_DATA; |
| /****************************Supported Device Info Table Definitions**********************/ |
| /* ucConnectInfo: */ |
| /* [7:4] - connector type */ |
| /* = 1 - VGA connector */ |
| /* = 2 - DVI-I */ |
| /* = 3 - DVI-D */ |
| /* = 4 - DVI-A */ |
| /* = 5 - SVIDEO */ |
| /* = 6 - COMPOSITE */ |
| /* = 7 - LVDS */ |
| /* = 8 - DIGITAL LINK */ |
| /* = 9 - SCART */ |
| /* = 0xA - HDMI_type A */ |
| /* = 0xB - HDMI_type B */ |
| /* = 0xE - Special case1 (DVI+DIN) */ |
| /* Others=TBD */ |
| /* [3:0] - DAC Associated */ |
| /* = 0 - no DAC */ |
| /* = 1 - DACA */ |
| /* = 2 - DACB */ |
| /* = 3 - External DAC */ |
| /* Others=TBD */ |
| /* */ |
| typedef struct _ATOM_CONNECTOR_INFO { |
| #if ATOM_BIG_ENDIAN |
| UCHAR bfConnectorType:4; |
| UCHAR bfAssociatedDAC:4; |
| #else |
| UCHAR bfAssociatedDAC:4; |
| UCHAR bfConnectorType:4; |
| #endif |
| } ATOM_CONNECTOR_INFO; |
| typedef union _ATOM_CONNECTOR_INFO_ACCESS { |
| ATOM_CONNECTOR_INFO sbfAccess; |
| UCHAR ucAccess; |
| } ATOM_CONNECTOR_INFO_ACCESS; |
| typedef struct _ATOM_CONNECTOR_INFO_I2C { |
| ATOM_CONNECTOR_INFO_ACCESS sucConnectorInfo; |
| ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; |
| } ATOM_CONNECTOR_INFO_I2C; |
| typedef struct _ATOM_SUPPORTED_DEVICES_INFO { |
| ATOM_COMMON_TABLE_HEADER sHeader; |
| USHORT usDeviceSupport; |
| ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO]; |
| } ATOM_SUPPORTED_DEVICES_INFO; |
| #define NO_INT_SRC_MAPPED 0xFF |
| typedef struct _ATOM_CONNECTOR_INC_SRC_BITMAP { |
| UCHAR ucIntSrcBitmap; |
| } ATOM_CONNECTOR_INC_SRC_BITMAP; |
| typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2 { |
| ATOM_COMMON_TABLE_HEADER sHeader; |
| USHORT usDeviceSupport; |
| ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2]; |
| ATOM_CONNECTOR_INC_SRC_BITMAP |
| asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2]; |
| } ATOM_SUPPORTED_DEVICES_INFO_2; |
| typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 { |
| ATOM_COMMON_TABLE_HEADER sHeader; |
| USHORT usDeviceSupport; |
| ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE]; |
| ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE]; |
| } ATOM_SUPPORTED_DEVICES_INFO_2d1; |
| #define ATOM_SUPPORTED_DEVICES_INFO_LAST ATOM_SUPPORTED_DEVICES_INFO_2d1 |
| typedef struct _ATOM_MISC_CONTROL_INFO { |
| USHORT usFrequency; |
| UCHAR ucPLL_ChargePump; /* PLL charge-pump gain control */ |
| UCHAR ucPLL_DutyCycle; /* PLL duty cycle control */ |
| UCHAR ucPLL_VCO_Gain; /* PLL VCO gain control */ |
| UCHAR ucPLL_VoltageSwing; /* PLL driver voltage swing control */ |
| } ATOM_MISC_CONTROL_INFO; |
| #define ATOM_MAX_MISC_INFO 4 |
| typedef struct _ATOM_TMDS_INFO { |
| ATOM_COMMON_TABLE_HEADER sHeader; |
| USHORT usMaxFrequency; /* in 10Khz */ |
| ATOM_MISC_CONTROL_INFO asMiscInfo[ATOM_MAX_MISC_INFO]; |
| } ATOM_TMDS_INFO; |
| typedef struct _ATOM_ENCODER_ANALOG_ATTRIBUTE { |
| UCHAR ucTVStandard; /* Same as TV standards defined above, */ |
| UCHAR ucPadding[1]; |
| } ATOM_ENCODER_ANALOG_ATTRIBUTE; |
| typedef struct _ATOM_ENCODER_DIGITAL_ATTRIBUTE { |
| UCHAR ucAttribute; /* Same as other digital encoder attributes defined above */ |
| UCHAR ucPadding[1]; |
| } ATOM_ENCODER_DIGITAL_ATTRIBUTE; |
| typedef union _ATOM_ENCODER_ATTRIBUTE { |
| ATOM_ENCODER_ANALOG_ATTRIBUTE sAlgAttrib; |
| ATOM_ENCODER_DIGITAL_ATTRIBUTE sDigAttrib; |
| } ATOM_ENCODER_ATTRIBUTE; |
| typedef struct _DVO_ENCODER_CONTROL_PARAMETERS { |
| USHORT usPixelClock; |
| USHORT usEncoderID; |
| UCHAR ucDeviceType; /* Use ATOM_DEVICE_xxx1_Index to indicate device type only. */ |
| UCHAR ucAction; /* ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT */ |
| ATOM_ENCODER_ATTRIBUTE usDevAttr; |
| } DVO_ENCODER_CONTROL_PARAMETERS; |
| typedef struct _DVO_ENCODER_CONTROL_PS_ALLOCATION { |
| DVO_ENCODER_CONTROL_PARAMETERS sDVOEncoder; |
| WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; /* Caller doesn't need to init this portion */ |
| } DVO_ENCODER_CONTROL_PS_ALLOCATION; |
| #define ATOM_XTMDS_ASIC_SI164_ID 1 |
| #define ATOM_XTMDS_ASIC_SI178_ID 2 |
| #define ATOM_XTMDS_ASIC_TFP513_ID 3 |
| #define ATOM_XTMDS_SUPPORTED_SINGLELINK 0x00000001 |
| #define ATOM_XTMDS_SUPPORTED_DUALLINK 0x00000002 |
| #define ATOM_XTMDS_MVPU_FPGA 0x00000004 |
| typedef struct _ATOM_XTMDS_INFO { |
| ATOM_COMMON_TABLE_HEADER sHeader; |
| USHORT usSingleLinkMaxFrequency; |
| ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; /* Point the ID on which I2C is used to control external chip */ |
| UCHAR ucXtransimitterID; |
| UCHAR ucSupportedLink; /* Bit field, bit0=1, single link supported;bit1=1,dual link supported */ |
| UCHAR ucSequnceAlterID; /* Even with the same external TMDS asic, it's possible that the program seqence alters */ |
| /* due to design. This ID is used to alert driver that the sequence is not "standard"! */ |
| UCHAR ucMasterAddress; /* Address to control Master xTMDS Chip */ |
| UCHAR ucSlaveAddress; /* Address to control Slave xTMDS Chip */ |
| } ATOM_XTMDS_INFO; |
| typedef struct _DFP_DPMS_STATUS_CHANGE_PARAMETERS { |
| UCHAR ucEnable; /* ATOM_ENABLE=On or ATOM_DISABLE=Off */ |
| UCHAR ucDevice; /* ATOM_DEVICE_DFP1_INDEX.... */ |
| UCHAR ucPadding[2]; |
| } DFP_DPMS_STATUS_CHANGE_PARAMETERS; |
| /****************************Legacy Power Play Table Definitions **********************/ |
| /* Definitions for ulPowerPlayMiscInfo */ |
| #define ATOM_PM_MISCINFO_SPLIT_CLOCK 0x00000000L |
| #define ATOM_PM_MISCINFO_USING_MCLK_SRC 0x00000001L |
| #define ATOM_PM_MISCINFO_USING_SCLK_SRC 0x00000002L |
| #define ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT 0x00000004L |
| #define ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH 0x00000008L |
| #define ATOM_PM_MISCINFO_LOAD_PERFORMANCE_EN 0x00000010L |
| #define ATOM_PM_MISCINFO_ENGINE_CLOCK_CONTRL_EN 0x00000020L |
| #define ATOM_PM_MISCINFO_MEMORY_CLOCK_CONTRL_EN 0x00000040L |
| #define ATOM_PM_MISCINFO_PROGRAM_VOLTAGE 0x00000080L /* When this bit set, ucVoltageDropIndex is not an index for GPIO pin, but a voltage ID that SW needs program */ |
| #define ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN 0x00000100L |
| #define ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN 0x00000200L |
| #define ATOM_PM_MISCINFO_ASIC_SLEEP_MODE_EN 0x00000400L |
| #define ATOM_PM_MISCINFO_LOAD_BALANCE_EN 0x00000800L |
| #define ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE 0x00001000L |
| #define ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE 0x00002000L |
| #define ATOM_PM_MISCINFO_LOW_LCD_REFRESH_RATE 0x00004000L |
| #define ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE 0x00008000L |
| #define ATOM_PM_MISCINFO_OVER_CLOCK_MODE 0x00010000L |
| #define ATOM_PM_MISCINFO_OVER_DRIVE_MODE 0x00020000L |
| #define ATOM_PM_MISCINFO_POWER_SAVING_MODE 0x00040000L |
| #define ATOM_PM_MISCINFO_THERMAL_DIODE_MODE 0x00080000L |
| #define ATOM_PM_MISCINFO_FRAME_MODULATION_MASK 0x00300000L /* 0-FM Disable, 1-2 level FM, 2-4 level FM, 3-Reserved */ |
| #define ATOM_PM_MISCINFO_FRAME_MODULATION_SHIFT 20 |
| #define ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE 0x00400000L |
| #define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2 0x00800000L |
| #define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4 0x01000000L |
| #define ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN 0x02000000L /* When set, Dynamic */ |
| #define ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN 0x04000000L /* When set, Dynamic */ |
| #define ATOM_PM_MISCINFO_3D_ACCELERATION_EN 0x08000000L /* When set, This mode is for acceleated 3D mode */ |
| #define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_MASK 0x70000000L /* 1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-High Performance, 5- Optimal Performance (Default state with Default clocks) */ |
| #define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_SHIFT 28 |
| #define ATOM_PM_MISCINFO_ENABLE_BACK_BIAS 0x80000000L |
| #define ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE 0x00000001L |
| #define ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT 0x00000002L |
| #define ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN 0x00000004L |
| #define ATOM_PM_MISCINFO2_FS3D_OVERDRIVE_INFO 0x00000008L |
| #define ATOM_PM_MISCINFO2_FORCEDLOWPWR_MODE 0x00000010L |
| #define ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN 0x00000020L |
| #define ATOM_PM_MISCINFO2_VIDEO_PLAYBACK_CAPABLE 0x00000040L /* If this bit is set in multi-pp mode, then driver will pack up one with the minior power consumption. */ |
| /* If it's not set in any pp mode, driver will use its default logic to pick a pp mode in video playback */ |
| #define ATOM_PM_MISCINFO2_NOT_VALID_ON_DC 0x00000080L |
| #define ATOM_PM_MISCINFO2_STUTTER_MODE_EN 0x00000100L |
| #define ATOM_PM_MISCINFO2_UVD_SUPPORT_MODE 0x00000200L |
| /* ucTableFormatRevision=1 */ |
| /* ucTableContentRevision=1 */ |
| typedef struct _ATOM_POWERMODE_INFO { |
| ULONG ulMiscInfo; /* The power level should be arranged in ascending order */ |
| ULONG ulReserved1; /* must set to 0 */ |
| ULONG ulReserved2; /* must set to 0 */ |
| USHORT usEngineClock; |
| USHORT usMemoryClock; |
| UCHAR ucVoltageDropIndex; /* index to GPIO table */ |
| UCHAR ucSelectedPanel_RefreshRate; /* panel refresh rate */ |
| UCHAR ucMinTemperature; |
| UCHAR ucMaxTemperature; |
| UCHAR ucNumPciELanes; /* number of PCIE lanes */ |
| } ATOM_POWERMODE_INFO; |
| /* ucTableFormatRevision=2 */ |
| /* ucTableContentRevision=1 */ |
| typedef struct _ATOM_POWERMODE_INFO_V2 { |
| ULONG ulMiscInfo; /* The power level should be arranged in ascending order */ |
| ULONG ulMiscInfo2; |
| ULONG ulEngineClock; |
| ULONG ulMemoryClock; |
| UCHAR ucVoltageDropIndex; /* index to GPIO table */ |
| UCHAR ucSelectedPanel_RefreshRate; /* panel refresh rate */ |
| UCHAR ucMinTemperature; |
| UCHAR ucMaxTemperature; |
| UCHAR ucNumPciELanes; /* number of PCIE lanes */ |
| } ATOM_POWERMODE_INFO_V2; |
| /* ucTableFormatRevision=2 */ |
| /* ucTableContentRevision=2 */ |
| typedef struct _ATOM_POWERMODE_INFO_V3 { |
| ULONG ulMiscInfo; /* The power level should be arranged in ascending order */ |
| ULONG ulMiscInfo2; |
| ULONG ulEngineClock; |
| ULONG ulMemoryClock; |
| UCHAR ucVoltageDropIndex; /* index to Core (VDDC) votage table */ |
| UCHAR ucSelectedPanel_RefreshRate; /* panel refresh rate */ |
| UCHAR ucMinTemperature; |
| UCHAR ucMaxTemperature; |
| UCHAR ucNumPciELanes; /* number of PCIE lanes */ |
| UCHAR ucVDDCI_VoltageDropIndex; /* index to VDDCI votage table */ |
| } ATOM_POWERMODE_INFO_V3; |
| #define ATOM_MAX_NUMBEROF_POWER_BLOCK 8 |
| #define ATOM_PP_OVERDRIVE_INTBITMAP_AUXWIN 0x01 |
| #define ATOM_PP_OVERDRIVE_INTBITMAP_OVERDRIVE 0x02 |
| #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM63 0x01 |
| #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1032 0x02 |
| #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1030 0x03 |
| #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_MUA6649 0x04 |
| #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM64 0x05 |
| #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_F75375 0x06 |
| #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ASC7512 0x07 /* Andigilog */ |
| typedef struct _ATOM_POWERPLAY_INFO { |
| ATOM_COMMON_TABLE_HEADER sHeader; |
| UCHAR ucOverdriveThermalController; |
| UCHAR ucOverdriveI2cLine; |
| UCHAR ucOverdriveIntBitmap; |
| UCHAR ucOverdriveControllerAddress; |
| UCHAR ucSizeOfPowerModeEntry; |
| UCHAR ucNumOfPowerModeEntries; |
| ATOM_POWERMODE_INFO asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; |
| } ATOM_POWERPLAY_INFO; |
| typedef struct _ATOM_POWERPLAY_INFO_V2 { |
| ATOM_COMMON_TABLE_HEADER sHeader; |
| UCHAR ucOverdriveThermalController; |
| UCHAR ucOverdriveI2cLine; |
| UCHAR ucOverdriveIntBitmap; |
| UCHAR ucOverdriveControllerAddress; |
| UCHAR ucSizeOfPowerModeEntry; |
| UCHAR ucNumOfPowerModeEntries; |
| ATOM_POWERMODE_INFO_V2 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; |
| } ATOM_POWERPLAY_INFO_V2; |
| typedef struct _ATOM_POWERPLAY_INFO_V3 { |
| ATOM_COMMON_TABLE_HEADER sHeader; |
| UCHAR ucOverdriveThermalController; |
| UCHAR ucOverdriveI2cLine; |
| UCHAR ucOverdriveIntBitmap; |
| UCHAR ucOverdriveControllerAddress; |
| UCHAR ucSizeOfPowerModeEntry; |
| UCHAR ucNumOfPowerModeEntries; |
| ATOM_POWERMODE_INFO_V3 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; |
| } ATOM_POWERPLAY_INFO_V3; |
| /**************************************************************************/ |
| /* Following definitions are for compatiblity issue in different SW components. */ |
| #define ATOM_MASTER_DATA_TABLE_REVISION 0x01 |
| #define Object_Info Object_Header |
| #define AdjustARB_SEQ MC_InitParameter |
| #define VRAM_GPIO_DetectionInfo VoltageObjectInfo |
| #define ASIC_VDDCI_Info ASIC_ProfilingInfo |
| #define ASIC_MVDDQ_Info MemoryTrainingInfo |
| #define SS_Info PPLL_SS_Info |
| #define ASIC_MVDDC_Info ASIC_InternalSS_Info |
| #define DispDevicePriorityInfo SaveRestoreInfo |
| #define DispOutInfo TV_VideoMode |
| #define ATOM_ENCODER_OBJECT_TABLE ATOM_OBJECT_TABLE |
| #define ATOM_CONNECTOR_OBJECT_TABLE ATOM_OBJECT_TABLE |
| /* New device naming, remove them when both DAL/VBIOS is ready */ |
| #define DFP2I_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS |
| #define DFP2I_OUTPUT_CONTROL_PS_ALLOCATION DFP2I_OUTPUT_CONTROL_PARAMETERS |
| #define DFP1X_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS |
| #define DFP1X_OUTPUT_CONTROL_PS_ALLOCATION DFP1X_OUTPUT_CONTROL_PARAMETERS |
| #define DFP1I_OUTPUT_CONTROL_PARAMETERS DFP1_OUTPUT_CONTROL_PARAMETERS |
| #define DFP1I_OUTPUT_CONTROL_PS_ALLOCATION DFP1_OUTPUT_CONTROL_PS_ALLOCATION |
| #define ATOM_DEVICE_DFP1I_SUPPORT ATOM_DEVICE_DFP1_SUPPORT |
| #define ATOM_DEVICE_DFP1X_SUPPORT ATOM_DEVICE_DFP2_SUPPORT |
| #define ATOM_DEVICE_DFP1I_INDEX ATOM_DEVICE_DFP1_INDEX |
| #define ATOM_DEVICE_DFP1X_INDEX ATOM_DEVICE_DFP2_INDEX |
| #define ATOM_DEVICE_DFP2I_INDEX 0x00000009 |
| #define ATOM_DEVICE_DFP2I_SUPPORT (0x1L << ATOM_DEVICE_DFP2I_INDEX) |
| #define ATOM_S0_DFP1I ATOM_S0_DFP1 |
| #define ATOM_S0_DFP1X ATOM_S0_DFP2 |
| #define ATOM_S0_DFP2I 0x00200000L |
| #define ATOM_S0_DFP2Ib2 0x20 |
| #define ATOM_S2_DFP1I_DPMS_STATE ATOM_S2_DFP1_DPMS_STATE |
| #define ATOM_S2_DFP1X_DPMS_STATE ATOM_S2_DFP2_DPMS_STATE |
| #define ATOM_S2_DFP2I_DPMS_STATE 0x02000000L |
| #define ATOM_S2_DFP2I_DPMS_STATEb3 0x02 |
| #define ATOM_S3_DFP2I_ACTIVEb1 0x02 |
| #define ATOM_S3_DFP1I_ACTIVE ATOM_S3_DFP1_ACTIVE |
| #define ATOM_S3_DFP1X_ACTIVE ATOM_S3_DFP2_ACTIVE |
| #define ATOM_S3_DFP2I_ACTIVE 0x00000200L |
| #define ATOM_S3_DFP1I_CRTC_ACTIVE ATOM_S3_DFP1_CRTC_ACTIVE |
| #define ATOM_S3_DFP1X_CRTC_ACTIVE ATOM_S3_DFP2_CRTC_ACTIVE |
| #define ATOM_S3_DFP2I_CRTC_ACTIVE 0x02000000L |
| #define ATOM_S3_DFP2I_CRTC_ACTIVEb3 0x02 |
| #define ATOM_S5_DOS_REQ_DFP2Ib1 0x02 |
| #define ATOM_S5_DOS_REQ_DFP2I 0x0200 |
| #define ATOM_S6_ACC_REQ_DFP1I ATOM_S6_ACC_REQ_DFP1 |
| #define ATOM_S6_ACC_REQ_DFP1X ATOM_S6_ACC_REQ_DFP2 |
| #define ATOM_S6_ACC_REQ_DFP2Ib3 0x02 |
| #define ATOM_S6_ACC_REQ_DFP2I 0x02000000L |
| #define TMDS1XEncoderControl DVOEncoderControl |
| #define DFP1XOutputControl DVOOutputControl |
| #define ExternalDFPOutputControl DFP1XOutputControl |
| #define EnableExternalTMDS_Encoder TMDS1XEncoderControl |
| #define DFP1IOutputControl TMDSAOutputControl |
| #define DFP2IOutputControl LVTMAOutputControl |
| #define DAC1_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS |
| #define DAC1_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION |
| #define DAC2_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS |
| #define DAC2_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION |
| #define ucDac1Standard ucDacStandard |
| #define ucDac2Standard ucDacStandard |
| #define TMDS1EncoderControl TMDSAEncoderControl |
| #define TMDS2EncoderControl LVTMAEncoderControl |
| #define DFP1OutputControl TMDSAOutputControl |
| #define DFP2OutputControl LVTMAOutputControl |
| #define CRT1OutputControl DAC1OutputControl |
| #define CRT2OutputControl DAC2OutputControl |
| /* These two lines will be removed for sure in a few days, will follow up with Michael V. */ |
| #define EnableLVDS_SS EnableSpreadSpectrumOnPPLL |
| #define ENABLE_LVDS_SS_PARAMETERS_V3 ENABLE_SPREAD_SPECTRUM_ON_PPLL |
| /*********************************************************************************/ |
| #pragma pack() /* BIOS data must use byte aligment */ |
| #endif /* _ATOMBIOS_H */ |
| /drivers/video/drm/radeon/pci.c |
|---|
| 0,0 → 1,795 |
| #include <pci.h> |
| #include <errno-base.h> |
| #include <syscall.h> |
| link_t devices; |
| static dev_t* pci_scan_device(u32_t bus, int devfn); |
| /* PCI control bits. Shares IORESOURCE_BITS with above PCI ROM. */ |
| #define IORESOURCE_PCI_FIXED (1<<4) /* Do not move resource */ |
| #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED) |
| /* |
| * Translate the low bits of the PCI base |
| * to the resource type |
| */ |
| static inline unsigned int pci_calc_resource_flags(unsigned int flags) |
| { |
| if (flags & PCI_BASE_ADDRESS_SPACE_IO) |
| return IORESOURCE_IO; |
| if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH) |
| return IORESOURCE_MEM | IORESOURCE_PREFETCH; |
| return IORESOURCE_MEM; |
| } |
| static u32_t pci_size(u32_t base, u32_t maxbase, u32_t mask) |
| { |
| u32_t size = mask & maxbase; /* Find the significant bits */ |
| if (!size) |
| return 0; |
| /* Get the lowest of them to find the decode size, and |
| from that the extent. */ |
| size = (size & ~(size-1)) - 1; |
| /* base == maxbase can be valid only if the BAR has |
| already been programmed with all 1s. */ |
| if (base == maxbase && ((base | size) & mask) != mask) |
| return 0; |
| return size; |
| } |
| static u64_t pci_size64(u64_t base, u64_t maxbase, u64_t mask) |
| { |
| u64_t size = mask & maxbase; /* Find the significant bits */ |
| if (!size) |
| return 0; |
| /* Get the lowest of them to find the decode size, and |
| from that the extent. */ |
| size = (size & ~(size-1)) - 1; |
| /* base == maxbase can be valid only if the BAR has |
| already been programmed with all 1s. */ |
| if (base == maxbase && ((base | size) & mask) != mask) |
| return 0; |
| return size; |
| } |
| static inline int is_64bit_memory(u32_t mask) |
| { |
| if ((mask & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) == |
| (PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64)) |
| return 1; |
| return 0; |
| } |
| static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) |
| { |
| u32_t pos, reg, next; |
| u32_t l, sz; |
| struct resource *res; |
| for(pos=0; pos < howmany; pos = next) |
| { |
| u64_t l64; |
| u64_t sz64; |
| u32_t raw_sz; |
| next = pos + 1; |
| res = &dev->resource[pos]; |
| reg = PCI_BASE_ADDRESS_0 + (pos << 2); |
| l = PciRead32(dev->bus, dev->devfn, reg); |
| PciWrite32(dev->bus, dev->devfn, reg, ~0); |
| sz = PciRead32(dev->bus, dev->devfn, reg); |
| PciWrite32(dev->bus, dev->devfn, reg, l); |
| if (!sz || sz == 0xffffffff) |
| continue; |
| if (l == 0xffffffff) |
| l = 0; |
| raw_sz = sz; |
| if ((l & PCI_BASE_ADDRESS_SPACE) == |
| PCI_BASE_ADDRESS_SPACE_MEMORY) |
| { |
| sz = pci_size(l, sz, (u32_t)PCI_BASE_ADDRESS_MEM_MASK); |
| /* |
| * For 64bit prefetchable memory sz could be 0, if the |
| * real size is bigger than 4G, so we need to check |
| * szhi for that. |
| */ |
| if (!is_64bit_memory(l) && !sz) |
| continue; |
| res->start = l & PCI_BASE_ADDRESS_MEM_MASK; |
| res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK; |
| } |
| else { |
| sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff); |
| if (!sz) |
| continue; |
| res->start = l & PCI_BASE_ADDRESS_IO_MASK; |
| res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK; |
| } |
| res->end = res->start + (unsigned long) sz; |
| res->flags |= pci_calc_resource_flags(l); |
| if (is_64bit_memory(l)) |
| { |
| u32_t szhi, lhi; |
| lhi = PciRead32(dev->bus, dev->devfn, reg+4); |
| PciWrite32(dev->bus, dev->devfn, reg+4, ~0); |
| szhi = PciRead32(dev->bus, dev->devfn, reg+4); |
| PciWrite32(dev->bus, dev->devfn, reg+4, lhi); |
| sz64 = ((u64_t)szhi << 32) | raw_sz; |
| l64 = ((u64_t)lhi << 32) | l; |
| sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK); |
| next++; |
| #if BITS_PER_LONG == 64 |
| if (!sz64) { |
| res->start = 0; |
| res->end = 0; |
| res->flags = 0; |
| continue; |
| } |
| res->start = l64 & PCI_BASE_ADDRESS_MEM_MASK; |
| res->end = res->start + sz64; |
| #else |
| if (sz64 > 0x100000000ULL) { |
| printk(KERN_ERR "PCI: Unable to handle 64-bit " |
| "BAR for device %s\n", pci_name(dev)); |
| res->start = 0; |
| res->flags = 0; |
| } |
| else if (lhi) |
| { |
| /* 64-bit wide address, treat as disabled */ |
| PciWrite32(dev->bus, dev->devfn, reg, |
| l & ~(u32_t)PCI_BASE_ADDRESS_MEM_MASK); |
| PciWrite32(dev->bus, dev->devfn, reg+4, 0); |
| res->start = 0; |
| res->end = sz; |
| } |
| #endif |
| } |
| } |
| if ( rom ) |
| { |
| dev->rom_base_reg = rom; |
| res = &dev->resource[PCI_ROM_RESOURCE]; |
| l = PciRead32(dev->bus, dev->devfn, rom); |
| PciWrite32(dev->bus, dev->devfn, rom, ~PCI_ROM_ADDRESS_ENABLE); |
| sz = PciRead32(dev->bus, dev->devfn, rom); |
| PciWrite32(dev->bus, dev->devfn, rom, l); |
| if (l == 0xffffffff) |
| l = 0; |
| if (sz && sz != 0xffffffff) |
| { |
| sz = pci_size(l, sz, (u32_t)PCI_ROM_ADDRESS_MASK); |
| if (sz) |
| { |
| res->flags = (l & IORESOURCE_ROM_ENABLE) | |
| IORESOURCE_MEM | IORESOURCE_PREFETCH | |
| IORESOURCE_READONLY | IORESOURCE_CACHEABLE; |
| res->start = l & PCI_ROM_ADDRESS_MASK; |
| res->end = res->start + (unsigned long) sz; |
| } |
| } |
| } |
| } |
| static void pci_read_irq(struct pci_dev *dev) |
| { |
| u8_t irq; |
| irq = PciRead8(dev->bus, dev->devfn, PCI_INTERRUPT_PIN); |
| dev->pin = irq; |
| if (irq) |
| PciRead8(dev->bus, dev->devfn, PCI_INTERRUPT_LINE); |
| dev->irq = irq; |
| }; |
| static int pci_setup_device(struct pci_dev *dev) |
| { |
| u32_t class; |
| class = PciRead32(dev->bus, dev->devfn, PCI_CLASS_REVISION); |
| dev->revision = class & 0xff; |
| class >>= 8; /* upper 3 bytes */ |
| dev->class = class; |
| /* "Unknown power state" */ |
| // dev->current_state = PCI_UNKNOWN; |
| /* Early fixups, before probing the BARs */ |
| // pci_fixup_device(pci_fixup_early, dev); |
| class = dev->class >> 8; |
| switch (dev->hdr_type) |
| { |
| case PCI_HEADER_TYPE_NORMAL: /* standard header */ |
| if (class == PCI_CLASS_BRIDGE_PCI) |
| goto bad; |
| pci_read_irq(dev); |
| pci_read_bases(dev, 6, PCI_ROM_ADDRESS); |
| dev->subsystem_vendor = PciRead16(dev->bus, dev->devfn,PCI_SUBSYSTEM_VENDOR_ID); |
| dev->subsystem_device = PciRead16(dev->bus, dev->devfn, PCI_SUBSYSTEM_ID); |
| /* |
| * Do the ugly legacy mode stuff here rather than broken chip |
| * quirk code. Legacy mode ATA controllers have fixed |
| * addresses. These are not always echoed in BAR0-3, and |
| * BAR0-3 in a few cases contain junk! |
| */ |
| if (class == PCI_CLASS_STORAGE_IDE) |
| { |
| u8_t progif; |
| progif = PciRead8(dev->bus, dev->devfn,PCI_CLASS_PROG); |
| if ((progif & 1) == 0) |
| { |
| dev->resource[0].start = 0x1F0; |
| dev->resource[0].end = 0x1F7; |
| dev->resource[0].flags = LEGACY_IO_RESOURCE; |
| dev->resource[1].start = 0x3F6; |
| dev->resource[1].end = 0x3F6; |
| dev->resource[1].flags = LEGACY_IO_RESOURCE; |
| } |
| if ((progif & 4) == 0) |
| { |
| dev->resource[2].start = 0x170; |
| dev->resource[2].end = 0x177; |
| dev->resource[2].flags = LEGACY_IO_RESOURCE; |
| dev->resource[3].start = 0x376; |
| dev->resource[3].end = 0x376; |
| dev->resource[3].flags = LEGACY_IO_RESOURCE; |
| }; |
| } |
| break; |
| case PCI_HEADER_TYPE_BRIDGE: /* bridge header */ |
| if (class != PCI_CLASS_BRIDGE_PCI) |
| goto bad; |
| /* The PCI-to-PCI bridge spec requires that subtractive |
| decoding (i.e. transparent) bridge must have programming |
| interface code of 0x01. */ |
| pci_read_irq(dev); |
| dev->transparent = ((dev->class & 0xff) == 1); |
| pci_read_bases(dev, 2, PCI_ROM_ADDRESS1); |
| break; |
| case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */ |
| if (class != PCI_CLASS_BRIDGE_CARDBUS) |
| goto bad; |
| pci_read_irq(dev); |
| pci_read_bases(dev, 1, 0); |
| dev->subsystem_vendor = PciRead16(dev->bus, |
| dev->devfn, |
| PCI_CB_SUBSYSTEM_VENDOR_ID); |
| dev->subsystem_device = PciRead16(dev->bus, |
| dev->devfn, |
| PCI_CB_SUBSYSTEM_ID); |
| break; |
| default: /* unknown header */ |
| printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n", |
| pci_name(dev), dev->hdr_type); |
| return -1; |
| bad: |
| printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n", |
| pci_name(dev), class, dev->hdr_type); |
| dev->class = PCI_CLASS_NOT_DEFINED; |
| } |
| /* We found a fine healthy device, go go go... */ |
| return 0; |
| }; |
| static dev_t* pci_scan_device(u32_t bus, int devfn) |
| { |
| dev_t *dev; |
| u32_t id; |
| u8_t hdr; |
| int timeout = 10; |
| id = PciRead32(bus,devfn, PCI_VENDOR_ID); |
| /* some broken boards return 0 or ~0 if a slot is empty: */ |
| if (id == 0xffffffff || id == 0x00000000 || |
| id == 0x0000ffff || id == 0xffff0000) |
| return NULL; |
| while (id == 0xffff0001) |
| { |
| delay(timeout/10); |
| timeout *= 2; |
| id = PciRead32(bus, devfn, PCI_VENDOR_ID); |
| /* Card hasn't responded in 60 seconds? Must be stuck. */ |
| if (timeout > 60 * 100) |
| { |
| printk(KERN_WARNING "Device %04x:%02x:%02x.%d not " |
| "responding\n", bus,PCI_SLOT(devfn),PCI_FUNC(devfn)); |
| return NULL; |
| } |
| }; |
| hdr = PciRead8(bus, devfn, PCI_HEADER_TYPE); |
| dev = (dev_t*)malloc(sizeof(dev_t)); |
| link_initialize(&dev->link); |
| if(unlikely(dev == NULL)) |
| return NULL; |
| dev->pci_dev.bus = bus; |
| dev->pci_dev.devfn = devfn; |
| dev->pci_dev.hdr_type = hdr & 0x7f; |
| dev->pci_dev.multifunction = !!(hdr & 0x80); |
| dev->pci_dev.vendor = id & 0xffff; |
| dev->pci_dev.device = (id >> 16) & 0xffff; |
| pci_setup_device(&dev->pci_dev); |
| return dev; |
| }; |
| int pci_scan_slot(u32_t bus, int devfn) |
| { |
| int func, nr = 0; |
| for (func = 0; func < 8; func++, devfn++) |
| { |
| dev_t *dev; |
| dev = pci_scan_device(bus, devfn); |
| if( dev ) |
| { |
| list_append(&dev->link, &devices); |
| nr++; |
| /* |
| * If this is a single function device, |
| * don't scan past the first function. |
| */ |
| if (!dev->pci_dev.multifunction) |
| { |
| if (func > 0) { |
| dev->pci_dev.multifunction = 1; |
| } |
| else { |
| break; |
| } |
| } |
| } |
| else { |
| if (func == 0) |
| break; |
| } |
| }; |
| return nr; |
| }; |
| void pci_scan_bus(u32_t bus) |
| { |
| u32_t devfn; |
| dev_t *dev; |
| for (devfn = 0; devfn < 0x100; devfn += 8) |
| pci_scan_slot(bus, devfn); |
| } |
| int enum_pci_devices() |
| { |
| dev_t *dev; |
| u32_t last_bus; |
| u32_t bus = 0 , devfn = 0; |
| list_initialize(&devices); |
| last_bus = PciApi(1); |
| if( unlikely(last_bus == -1)) |
| return -1; |
| for(;bus <= last_bus; bus++) |
| pci_scan_bus(bus); |
| // for(dev = (dev_t*)devices.next; |
| // &dev->link != &devices; |
| // dev = (dev_t*)dev->link.next) |
| // { |
| // dbgprintf("PCI device %x:%x bus:%x devfn:%x\n", |
| // dev->pci_dev.vendor, |
| // dev->pci_dev.device, |
| // dev->pci_dev.bus, |
| // dev->pci_dev.devfn); |
| // |
| // } |
| return 0; |
| } |
| #if 0 |
| /** |
| * pci_set_power_state - Set the power state of a PCI device |
| * @dev: PCI device to be suspended |
| * @state: PCI power state (D0, D1, D2, D3hot, D3cold) we're entering |
| * |
| * Transition a device to a new power state, using the Power Management |
| * Capabilities in the device's config space. |
| * |
| * RETURN VALUE: |
| * -EINVAL if trying to enter a lower state than we're already in. |
| * 0 if we're already in the requested state. |
| * -EIO if device does not support PCI PM. |
| * 0 if we can successfully change the power state. |
| */ |
| int |
| pci_set_power_state(struct pci_dev *dev, pci_power_t state) |
| { |
| int pm, need_restore = 0; |
| u16 pmcsr, pmc; |
| /* bound the state we're entering */ |
| if (state > PCI_D3hot) |
| state = PCI_D3hot; |
| /* |
| * If the device or the parent bridge can't support PCI PM, ignore |
| * the request if we're doing anything besides putting it into D0 |
| * (which would only happen on boot). |
| */ |
| if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev)) |
| return 0; |
| /* find PCI PM capability in list */ |
| pm = pci_find_capability(dev, PCI_CAP_ID_PM); |
| /* abort if the device doesn't support PM capabilities */ |
| if (!pm) |
| return -EIO; |
| /* Validate current state: |
| * Can enter D0 from any state, but if we can only go deeper |
| * to sleep if we're already in a low power state |
| */ |
| if (state != PCI_D0 && dev->current_state > state) { |
| printk(KERN_ERR "%s(): %s: state=%d, current state=%d\n", |
| __FUNCTION__, pci_name(dev), state, dev->current_state); |
| return -EINVAL; |
| } else if (dev->current_state == state) |
| return 0; /* we're already there */ |
| pci_read_config_word(dev,pm + PCI_PM_PMC,&pmc); |
| if ((pmc & PCI_PM_CAP_VER_MASK) > 3) { |
| printk(KERN_DEBUG |
| "PCI: %s has unsupported PM cap regs version (%u)\n", |
| pci_name(dev), pmc & PCI_PM_CAP_VER_MASK); |
| return -EIO; |
| } |
| /* check if this device supports the desired state */ |
| if (state == PCI_D1 && !(pmc & PCI_PM_CAP_D1)) |
| return -EIO; |
| else if (state == PCI_D2 && !(pmc & PCI_PM_CAP_D2)) |
| return -EIO; |
| pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr); |
| /* If we're (effectively) in D3, force entire word to 0. |
| * This doesn't affect PME_Status, disables PME_En, and |
| * sets PowerState to 0. |
| */ |
| switch (dev->current_state) { |
| case PCI_D0: |
| case PCI_D1: |
| case PCI_D2: |
| pmcsr &= ~PCI_PM_CTRL_STATE_MASK; |
| pmcsr |= state; |
| break; |
| case PCI_UNKNOWN: /* Boot-up */ |
| if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot |
| && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET)) |
| need_restore = 1; |
| /* Fall-through: force to D0 */ |
| default: |
| pmcsr = 0; |
| break; |
| } |
| /* enter specified state */ |
| pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr); |
| /* Mandatory power management transition delays */ |
| /* see PCI PM 1.1 5.6.1 table 18 */ |
| if (state == PCI_D3hot || dev->current_state == PCI_D3hot) |
| msleep(pci_pm_d3_delay); |
| else if (state == PCI_D2 || dev->current_state == PCI_D2) |
| udelay(200); |
| /* |
| * Give firmware a chance to be called, such as ACPI _PRx, _PSx |
| * Firmware method after native method ? |
| */ |
| if (platform_pci_set_power_state) |
| platform_pci_set_power_state(dev, state); |
| dev->current_state = state; |
| /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT |
| * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning |
| * from D3hot to D0 _may_ perform an internal reset, thereby |
| * going to "D0 Uninitialized" rather than "D0 Initialized". |
| * For example, at least some versions of the 3c905B and the |
| * 3c556B exhibit this behaviour. |
| * |
| * At least some laptop BIOSen (e.g. the Thinkpad T21) leave |
| * devices in a D3hot state at boot. Consequently, we need to |
| * restore at least the BARs so that the device will be |
| * accessible to its driver. |
| */ |
| if (need_restore) |
| pci_restore_bars(dev); |
| return 0; |
| } |
| #endif |
| int pcibios_enable_resources(struct pci_dev *dev, int mask) |
| { |
| u16_t cmd, old_cmd; |
| int idx; |
| struct resource *r; |
| cmd = PciRead16(dev->bus, dev->devfn, PCI_COMMAND); |
| old_cmd = cmd; |
| for (idx = 0; idx < PCI_NUM_RESOURCES; idx++) |
| { |
| /* Only set up the requested stuff */ |
| if (!(mask & (1 << idx))) |
| continue; |
| r = &dev->resource[idx]; |
| if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM))) |
| continue; |
| if ((idx == PCI_ROM_RESOURCE) && |
| (!(r->flags & IORESOURCE_ROM_ENABLE))) |
| continue; |
| if (!r->start && r->end) { |
| printk(KERN_ERR "PCI: Device %s not available " |
| "because of resource %d collisions\n", |
| pci_name(dev), idx); |
| return -EINVAL; |
| } |
| if (r->flags & IORESOURCE_IO) |
| cmd |= PCI_COMMAND_IO; |
| if (r->flags & IORESOURCE_MEM) |
| cmd |= PCI_COMMAND_MEMORY; |
| } |
| if (cmd != old_cmd) { |
| printk("PCI: Enabling device %s (%04x -> %04x)\n", |
| pci_name(dev), old_cmd, cmd); |
| PciWrite16(dev->bus, dev->devfn, PCI_COMMAND, cmd); |
| } |
| return 0; |
| } |
| int pcibios_enable_device(struct pci_dev *dev, int mask) |
| { |
| int err; |
| if ((err = pcibios_enable_resources(dev, mask)) < 0) |
| return err; |
| // if (!dev->msi_enabled) |
| // return pcibios_enable_irq(dev); |
| return 0; |
| } |
| static int do_pci_enable_device(struct pci_dev *dev, int bars) |
| { |
| int err; |
| // err = pci_set_power_state(dev, PCI_D0); |
| // if (err < 0 && err != -EIO) |
| // return err; |
| err = pcibios_enable_device(dev, bars); |
| // if (err < 0) |
| // return err; |
| // pci_fixup_device(pci_fixup_enable, dev); |
| return 0; |
| } |
| static int __pci_enable_device_flags(struct pci_dev *dev, |
| resource_size_t flags) |
| { |
| int err; |
| int i, bars = 0; |
| // if (atomic_add_return(1, &dev->enable_cnt) > 1) |
| // return 0; /* already enabled */ |
| for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) |
| if (dev->resource[i].flags & flags) |
| bars |= (1 << i); |
| err = do_pci_enable_device(dev, bars); |
| // if (err < 0) |
| // atomic_dec(&dev->enable_cnt); |
| return err; |
| } |
| /** |
| * pci_enable_device - Initialize device before it's used by a driver. |
| * @dev: PCI device to be initialized |
| * |
| * Initialize device before it's used by a driver. Ask low-level code |
| * to enable I/O and memory. Wake up the device if it was suspended. |
| * Beware, this function can fail. |
| * |
| * Note we don't actually enable the device many times if we call |
| * this function repeatedly (we just increment the count). |
| */ |
| int pci_enable_device(struct pci_dev *dev) |
| { |
| return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO); |
| } |
| struct pci_device_id* find_pci_device(dev_t* pdev, struct pci_device_id *idlist) |
| { |
| dev_t *dev; |
| struct pci_device_id *ent; |
| for(dev = (dev_t*)devices.next; |
| &dev->link != &devices; |
| dev = (dev_t*)dev->link.next) |
| { |
| if( dev->pci_dev.vendor != idlist->vendor ) |
| continue; |
| for(ent = idlist; ent->vendor != 0; ent++) |
| { |
| if(unlikely(ent->device == dev->pci_dev.device)) |
| { |
| pdev->pci_dev = dev->pci_dev; |
| return ent; |
| } |
| }; |
| } |
| return NULL; |
| }; |
| /** |
| * pci_map_rom - map a PCI ROM to kernel space |
| * @pdev: pointer to pci device struct |
| * @size: pointer to receive size of pci window over ROM |
| * @return: kernel virtual pointer to image of ROM |
| * |
| * Map a PCI ROM into kernel space. If ROM is boot video ROM, |
| * the shadow BIOS copy will be returned instead of the |
| * actual ROM. |
| */ |
| #define legacyBIOSLocation 0xC0000 |
| #define OS_BASE 0x80000000 |
| void *pci_map_rom(struct pci_dev *pdev, size_t *size) |
| { |
| struct resource *res = &pdev->resource[PCI_ROM_RESOURCE]; |
| u32_t start; |
| void *rom; |
| #if 0 |
| /* |
| * IORESOURCE_ROM_SHADOW set on x86, x86_64 and IA64 supports legacy |
| * memory map if the VGA enable bit of the Bridge Control register is |
| * set for embedded VGA. |
| */ |
| if (res->flags & IORESOURCE_ROM_SHADOW) { |
| /* primary video rom always starts here */ |
| start = (u32_t)0xC0000; |
| *size = 0x20000; /* cover C000:0 through E000:0 */ |
| } else { |
| if (res->flags & (IORESOURCE_ROM_COPY | IORESOURCE_ROM_BIOS_COPY)) { |
| *size = pci_resource_len(pdev, PCI_ROM_RESOURCE); |
| return (void *)(unsigned long) |
| pci_resource_start(pdev, PCI_ROM_RESOURCE); |
| } else { |
| /* assign the ROM an address if it doesn't have one */ |
| //if (res->parent == NULL && |
| // pci_assign_resource(pdev,PCI_ROM_RESOURCE)) |
| // return NULL; |
| start = pci_resource_start(pdev, PCI_ROM_RESOURCE); |
| *size = pci_resource_len(pdev, PCI_ROM_RESOURCE); |
| if (*size == 0) |
| return NULL; |
| /* Enable ROM space decodes */ |
| if (pci_enable_rom(pdev)) |
| return NULL; |
| } |
| } |
| rom = ioremap(start, *size); |
| if (!rom) { |
| /* restore enable if ioremap fails */ |
| if (!(res->flags & (IORESOURCE_ROM_ENABLE | |
| IORESOURCE_ROM_SHADOW | |
| IORESOURCE_ROM_COPY))) |
| pci_disable_rom(pdev); |
| return NULL; |
| } |
| /* |
| * Try to find the true size of the ROM since sometimes the PCI window |
| * size is much larger than the actual size of the ROM. |
| * True size is important if the ROM is going to be copied. |
| */ |
| *size = pci_get_rom_size(rom, *size); |
| #endif |
| unsigned char tmp[32]; |
| rom = NULL; |
| dbgprintf("Getting BIOS copy from legacy VBIOS location\n"); |
| memcpy(tmp,(char*)(OS_BASE+legacyBIOSLocation), 32); |
| *size = tmp[2] * 512; |
| if (*size > 0x10000 ) |
| { |
| *size = 0; |
| dbgprintf("Invalid BIOS length field\n"); |
| } |
| else |
| rom = (void*)( OS_BASE+legacyBIOSLocation); |
| return rom; |
| } |
| /drivers/video/drm/radeon/r100.c |
|---|
| 0,0 → 1,1394 |
| /* |
| * Copyright 2008 Advanced Micro Devices, Inc. |
| * Copyright 2008 Red Hat Inc. |
| * Copyright 2009 Jerome Glisse. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice shall be included in |
| * all copies or substantial portions of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| * OTHER DEALINGS IN THE SOFTWARE. |
| * |
| * Authors: Dave Airlie |
| * Alex Deucher |
| * Jerome Glisse |
| */ |
| //#include <linux/seq_file.h> |
| //#include "drmP.h" |
| //#include "drm.h" |
| #include "radeon_drm.h" |
| #include "radeon_microcode.h" |
| #include "radeon_reg.h" |
| #include "radeon.h" |
| /* This files gather functions specifics to: |
| * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 |
| * |
| * Some of these functions might be used by newer ASICs. |
| */ |
| void r100_hdp_reset(struct radeon_device *rdev); |
| void r100_gpu_init(struct radeon_device *rdev); |
| int r100_gui_wait_for_idle(struct radeon_device *rdev); |
| int r100_mc_wait_for_idle(struct radeon_device *rdev); |
| void r100_gpu_wait_for_vsync(struct radeon_device *rdev); |
| void r100_gpu_wait_for_vsync2(struct radeon_device *rdev); |
| int r100_debugfs_mc_info_init(struct radeon_device *rdev); |
| #if 0 |
| /* |
| * PCI GART |
| */ |
| void r100_pci_gart_tlb_flush(struct radeon_device *rdev) |
| { |
| /* TODO: can we do somethings here ? */ |
| /* It seems hw only cache one entry so we should discard this |
| * entry otherwise if first GPU GART read hit this entry it |
| * could end up in wrong address. */ |
| } |
| int r100_pci_gart_enable(struct radeon_device *rdev) |
| { |
| uint32_t tmp; |
| int r; |
| /* Initialize common gart structure */ |
| r = radeon_gart_init(rdev); |
| if (r) { |
| return r; |
| } |
| if (rdev->gart.table.ram.ptr == NULL) { |
| rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; |
| r = radeon_gart_table_ram_alloc(rdev); |
| if (r) { |
| return r; |
| } |
| } |
| /* discard memory request outside of configured range */ |
| tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; |
| WREG32(RADEON_AIC_CNTL, tmp); |
| /* set address range for PCI address translate */ |
| WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_location); |
| tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; |
| WREG32(RADEON_AIC_HI_ADDR, tmp); |
| /* Enable bus mastering */ |
| tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; |
| WREG32(RADEON_BUS_CNTL, tmp); |
| /* set PCI GART page-table base address */ |
| WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr); |
| tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN; |
| WREG32(RADEON_AIC_CNTL, tmp); |
| r100_pci_gart_tlb_flush(rdev); |
| rdev->gart.ready = true; |
| return 0; |
| } |
| void r100_pci_gart_disable(struct radeon_device *rdev) |
| { |
| uint32_t tmp; |
| /* discard memory request outside of configured range */ |
| tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; |
| WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN); |
| WREG32(RADEON_AIC_LO_ADDR, 0); |
| WREG32(RADEON_AIC_HI_ADDR, 0); |
| } |
| int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) |
| { |
| if (i < 0 || i > rdev->gart.num_gpu_pages) { |
| return -EINVAL; |
| } |
| rdev->gart.table.ram.ptr[i] = cpu_to_le32((uint32_t)addr); |
| return 0; |
| } |
| int r100_gart_enable(struct radeon_device *rdev) |
| { |
| if (rdev->flags & RADEON_IS_AGP) { |
| r100_pci_gart_disable(rdev); |
| return 0; |
| } |
| return r100_pci_gart_enable(rdev); |
| } |
| /* |
| * MC |
| */ |
| void r100_mc_disable_clients(struct radeon_device *rdev) |
| { |
| uint32_t ov0_scale_cntl, crtc_ext_cntl, crtc_gen_cntl, crtc2_gen_cntl; |
| /* FIXME: is this function correct for rs100,rs200,rs300 ? */ |
| // if (r100_gui_wait_for_idle(rdev)) { |
| // printk(KERN_WARNING "Failed to wait GUI idle while " |
| // "programming pipes. Bad things might happen.\n"); |
| // } |
| /* stop display and memory access */ |
| ov0_scale_cntl = RREG32(RADEON_OV0_SCALE_CNTL); |
| WREG32(RADEON_OV0_SCALE_CNTL, ov0_scale_cntl & ~RADEON_SCALER_ENABLE); |
| crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); |
| WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl | RADEON_CRTC_DISPLAY_DIS); |
| crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL); |
| r100_gpu_wait_for_vsync(rdev); |
| WREG32(RADEON_CRTC_GEN_CNTL, |
| (crtc_gen_cntl & ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_ICON_EN)) | |
| RADEON_CRTC_DISP_REQ_EN_B | RADEON_CRTC_EXT_DISP_EN); |
| if (!(rdev->flags & RADEON_SINGLE_CRTC)) { |
| crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); |
| r100_gpu_wait_for_vsync2(rdev); |
| WREG32(RADEON_CRTC2_GEN_CNTL, |
| (crtc2_gen_cntl & |
| ~(RADEON_CRTC2_CUR_EN | RADEON_CRTC2_ICON_EN)) | |
| RADEON_CRTC2_DISP_REQ_EN_B); |
| } |
| udelay(500); |
| } |
| void r100_mc_setup(struct radeon_device *rdev) |
| { |
| uint32_t tmp; |
| int r; |
| r = r100_debugfs_mc_info_init(rdev); |
| if (r) { |
| DRM_ERROR("Failed to register debugfs file for R100 MC !\n"); |
| } |
| /* Write VRAM size in case we are limiting it */ |
| WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size); |
| tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1; |
| tmp = REG_SET(RADEON_MC_FB_TOP, tmp >> 16); |
| tmp |= REG_SET(RADEON_MC_FB_START, rdev->mc.vram_location >> 16); |
| WREG32(RADEON_MC_FB_LOCATION, tmp); |
| /* Enable bus mastering */ |
| tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; |
| WREG32(RADEON_BUS_CNTL, tmp); |
| if (rdev->flags & RADEON_IS_AGP) { |
| tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; |
| tmp = REG_SET(RADEON_MC_AGP_TOP, tmp >> 16); |
| tmp |= REG_SET(RADEON_MC_AGP_START, rdev->mc.gtt_location >> 16); |
| WREG32(RADEON_MC_AGP_LOCATION, tmp); |
| WREG32(RADEON_AGP_BASE, rdev->mc.agp_base); |
| } else { |
| WREG32(RADEON_MC_AGP_LOCATION, 0x0FFFFFFF); |
| WREG32(RADEON_AGP_BASE, 0); |
| } |
| tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL; |
| tmp |= (7 << 28); |
| WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE); |
| (void)RREG32(RADEON_HOST_PATH_CNTL); |
| WREG32(RADEON_HOST_PATH_CNTL, tmp); |
| (void)RREG32(RADEON_HOST_PATH_CNTL); |
| } |
| int r100_mc_init(struct radeon_device *rdev) |
| { |
| int r; |
| if (r100_debugfs_rbbm_init(rdev)) { |
| DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
| } |
| r100_gpu_init(rdev); |
| /* Disable gart which also disable out of gart access */ |
| r100_pci_gart_disable(rdev); |
| /* Setup GPU memory space */ |
| rdev->mc.vram_location = 0xFFFFFFFFUL; |
| rdev->mc.gtt_location = 0xFFFFFFFFUL; |
| if (rdev->flags & RADEON_IS_AGP) { |
| r = radeon_agp_init(rdev); |
| if (r) { |
| printk(KERN_WARNING "[drm] Disabling AGP\n"); |
| rdev->flags &= ~RADEON_IS_AGP; |
| rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; |
| } else { |
| rdev->mc.gtt_location = rdev->mc.agp_base; |
| } |
| } |
| r = radeon_mc_setup(rdev); |
| if (r) { |
| return r; |
| } |
| r100_mc_disable_clients(rdev); |
| if (r100_mc_wait_for_idle(rdev)) { |
| printk(KERN_WARNING "Failed to wait MC idle while " |
| "programming pipes. Bad things might happen.\n"); |
| } |
| r100_mc_setup(rdev); |
| return 0; |
| } |
| void r100_mc_fini(struct radeon_device *rdev) |
| { |
| r100_pci_gart_disable(rdev); |
| radeon_gart_table_ram_free(rdev); |
| radeon_gart_fini(rdev); |
| } |
| /* |
| * Fence emission |
| */ |
| void r100_fence_ring_emit(struct radeon_device *rdev, |
| struct radeon_fence *fence) |
| { |
| /* Who ever call radeon_fence_emit should call ring_lock and ask |
| * for enough space (today caller are ib schedule and buffer move) */ |
| /* Wait until IDLE & CLEAN */ |
| radeon_ring_write(rdev, PACKET0(0x1720, 0)); |
| radeon_ring_write(rdev, (1 << 16) | (1 << 17)); |
| /* Emit fence sequence & fire IRQ */ |
| radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0)); |
| radeon_ring_write(rdev, fence->seq); |
| radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0)); |
| radeon_ring_write(rdev, RADEON_SW_INT_FIRE); |
| } |
| /* |
| * Writeback |
| */ |
| int r100_wb_init(struct radeon_device *rdev) |
| { |
| int r; |
| if (rdev->wb.wb_obj == NULL) { |
| r = radeon_object_create(rdev, NULL, 4096, |
| true, |
| RADEON_GEM_DOMAIN_GTT, |
| false, &rdev->wb.wb_obj); |
| if (r) { |
| DRM_ERROR("radeon: failed to create WB buffer (%d).\n", r); |
| return r; |
| } |
| r = radeon_object_pin(rdev->wb.wb_obj, |
| RADEON_GEM_DOMAIN_GTT, |
| &rdev->wb.gpu_addr); |
| if (r) { |
| DRM_ERROR("radeon: failed to pin WB buffer (%d).\n", r); |
| return r; |
| } |
| r = radeon_object_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb); |
| if (r) { |
| DRM_ERROR("radeon: failed to map WB buffer (%d).\n", r); |
| return r; |
| } |
| } |
| WREG32(0x774, rdev->wb.gpu_addr); |
| WREG32(0x70C, rdev->wb.gpu_addr + 1024); |
| WREG32(0x770, 0xff); |
| return 0; |
| } |
| void r100_wb_fini(struct radeon_device *rdev) |
| { |
| if (rdev->wb.wb_obj) { |
| radeon_object_kunmap(rdev->wb.wb_obj); |
| radeon_object_unpin(rdev->wb.wb_obj); |
| radeon_object_unref(&rdev->wb.wb_obj); |
| rdev->wb.wb = NULL; |
| rdev->wb.wb_obj = NULL; |
| } |
| } |
| int r100_copy_blit(struct radeon_device *rdev, |
| uint64_t src_offset, |
| uint64_t dst_offset, |
| unsigned num_pages, |
| struct radeon_fence *fence) |
| { |
| uint32_t cur_pages; |
| uint32_t stride_bytes = PAGE_SIZE; |
| uint32_t pitch; |
| uint32_t stride_pixels; |
| unsigned ndw; |
| int num_loops; |
| int r = 0; |
| /* radeon limited to 16k stride */ |
| stride_bytes &= 0x3fff; |
| /* radeon pitch is /64 */ |
| pitch = stride_bytes / 64; |
| stride_pixels = stride_bytes / 4; |
| num_loops = DIV_ROUND_UP(num_pages, 8191); |
| /* Ask for enough room for blit + flush + fence */ |
| ndw = 64 + (10 * num_loops); |
| r = radeon_ring_lock(rdev, ndw); |
| if (r) { |
| DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw); |
| return -EINVAL; |
| } |
| while (num_pages > 0) { |
| cur_pages = num_pages; |
| if (cur_pages > 8191) { |
| cur_pages = 8191; |
| } |
| num_pages -= cur_pages; |
| /* pages are in Y direction - height |
| page width in X direction - width */ |
| radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8)); |
| radeon_ring_write(rdev, |
| RADEON_GMC_SRC_PITCH_OFFSET_CNTL | |
| RADEON_GMC_DST_PITCH_OFFSET_CNTL | |
| RADEON_GMC_SRC_CLIPPING | |
| RADEON_GMC_DST_CLIPPING | |
| RADEON_GMC_BRUSH_NONE | |
| (RADEON_COLOR_FORMAT_ARGB8888 << 8) | |
| RADEON_GMC_SRC_DATATYPE_COLOR | |
| RADEON_ROP3_S | |
| RADEON_DP_SRC_SOURCE_MEMORY | |
| RADEON_GMC_CLR_CMP_CNTL_DIS | |
| RADEON_GMC_WR_MSK_DIS); |
| radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10)); |
| radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10)); |
| radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16)); |
| radeon_ring_write(rdev, 0); |
| radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16)); |
| radeon_ring_write(rdev, num_pages); |
| radeon_ring_write(rdev, num_pages); |
| radeon_ring_write(rdev, cur_pages | (stride_pixels << 16)); |
| } |
| radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0)); |
| radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL); |
| radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); |
| radeon_ring_write(rdev, |
| RADEON_WAIT_2D_IDLECLEAN | |
| RADEON_WAIT_HOST_IDLECLEAN | |
| RADEON_WAIT_DMA_GUI_IDLE); |
| if (fence) { |
| r = radeon_fence_emit(rdev, fence); |
| } |
| radeon_ring_unlock_commit(rdev); |
| return r; |
| } |
| /* |
| * CP |
| */ |
| void r100_ring_start(struct radeon_device *rdev) |
| { |
| int r; |
| r = radeon_ring_lock(rdev, 2); |
| if (r) { |
| return; |
| } |
| radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0)); |
| radeon_ring_write(rdev, |
| RADEON_ISYNC_ANY2D_IDLE3D | |
| RADEON_ISYNC_ANY3D_IDLE2D | |
| RADEON_ISYNC_WAIT_IDLEGUI | |
| RADEON_ISYNC_CPSCRATCH_IDLEGUI); |
| radeon_ring_unlock_commit(rdev); |
| } |
| #endif |
| static void r100_cp_load_microcode(struct radeon_device *rdev) |
| { |
| int i; |
| dbgprintf("%s\n\r",__FUNCTION__); |
| if (r100_gui_wait_for_idle(rdev)) { |
| printk(KERN_WARNING "Failed to wait GUI idle while " |
| "programming pipes. Bad things might happen.\n"); |
| } |
| WREG32(RADEON_CP_ME_RAM_ADDR, 0); |
| if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) || |
| (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) || |
| (rdev->family == CHIP_RS200)) { |
| DRM_INFO("Loading R100 Microcode\n"); |
| for (i = 0; i < 256; i++) { |
| WREG32(RADEON_CP_ME_RAM_DATAH, R100_cp_microcode[i][1]); |
| WREG32(RADEON_CP_ME_RAM_DATAL, R100_cp_microcode[i][0]); |
| } |
| } else if ((rdev->family == CHIP_R200) || |
| (rdev->family == CHIP_RV250) || |
| (rdev->family == CHIP_RV280) || |
| (rdev->family == CHIP_RS300)) { |
| DRM_INFO("Loading R200 Microcode\n"); |
| for (i = 0; i < 256; i++) { |
| WREG32(RADEON_CP_ME_RAM_DATAH, R200_cp_microcode[i][1]); |
| WREG32(RADEON_CP_ME_RAM_DATAL, R200_cp_microcode[i][0]); |
| } |
| } else if ((rdev->family == CHIP_R300) || |
| (rdev->family == CHIP_R350) || |
| (rdev->family == CHIP_RV350) || |
| (rdev->family == CHIP_RV380) || |
| (rdev->family == CHIP_RS400) || |
| (rdev->family == CHIP_RS480)) { |
| DRM_INFO("Loading R300 Microcode\n"); |
| for (i = 0; i < 256; i++) { |
| WREG32(RADEON_CP_ME_RAM_DATAH, R300_cp_microcode[i][1]); |
| WREG32(RADEON_CP_ME_RAM_DATAL, R300_cp_microcode[i][0]); |
| } |
| } else if ((rdev->family == CHIP_R420) || |
| (rdev->family == CHIP_R423) || |
| (rdev->family == CHIP_RV410)) { |
| DRM_INFO("Loading R400 Microcode\n"); |
| for (i = 0; i < 256; i++) { |
| WREG32(RADEON_CP_ME_RAM_DATAH, R420_cp_microcode[i][1]); |
| WREG32(RADEON_CP_ME_RAM_DATAL, R420_cp_microcode[i][0]); |
| } |
| } else if ((rdev->family == CHIP_RS690) || |
| (rdev->family == CHIP_RS740)) { |
| DRM_INFO("Loading RS690/RS740 Microcode\n"); |
| for (i = 0; i < 256; i++) { |
| WREG32(RADEON_CP_ME_RAM_DATAH, RS690_cp_microcode[i][1]); |
| WREG32(RADEON_CP_ME_RAM_DATAL, RS690_cp_microcode[i][0]); |
| } |
| } else if (rdev->family == CHIP_RS600) { |
| DRM_INFO("Loading RS600 Microcode\n"); |
| for (i = 0; i < 256; i++) { |
| WREG32(RADEON_CP_ME_RAM_DATAH, RS600_cp_microcode[i][1]); |
| WREG32(RADEON_CP_ME_RAM_DATAL, RS600_cp_microcode[i][0]); |
| } |
| } else if ((rdev->family == CHIP_RV515) || |
| (rdev->family == CHIP_R520) || |
| (rdev->family == CHIP_RV530) || |
| (rdev->family == CHIP_R580) || |
| (rdev->family == CHIP_RV560) || |
| (rdev->family == CHIP_RV570)) { |
| DRM_INFO("Loading R500 Microcode\n"); |
| for (i = 0; i < 256; i++) { |
| WREG32(RADEON_CP_ME_RAM_DATAH, R520_cp_microcode[i][1]); |
| WREG32(RADEON_CP_ME_RAM_DATAL, R520_cp_microcode[i][0]); |
| } |
| } |
| } |
| int r100_cp_init(struct radeon_device *rdev, unsigned ring_size) |
| { |
| unsigned rb_bufsz; |
| unsigned rb_blksz; |
| unsigned max_fetch; |
| unsigned pre_write_timer; |
| unsigned pre_write_limit; |
| unsigned indirect2_start; |
| unsigned indirect1_start; |
| uint32_t tmp; |
| int r; |
| dbgprintf("%s\n\r",__FUNCTION__); |
| // if (r100_debugfs_cp_init(rdev)) { |
| // DRM_ERROR("Failed to register debugfs file for CP !\n"); |
| // } |
| /* Reset CP */ |
| tmp = RREG32(RADEON_CP_CSQ_STAT); |
| if ((tmp & (1 << 31))) { |
| DRM_INFO("radeon: cp busy (0x%08X) resetting\n", tmp); |
| WREG32(RADEON_CP_CSQ_MODE, 0); |
| WREG32(RADEON_CP_CSQ_CNTL, 0); |
| WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP); |
| tmp = RREG32(RADEON_RBBM_SOFT_RESET); |
| mdelay(2); |
| WREG32(RADEON_RBBM_SOFT_RESET, 0); |
| tmp = RREG32(RADEON_RBBM_SOFT_RESET); |
| mdelay(2); |
| tmp = RREG32(RADEON_CP_CSQ_STAT); |
| if ((tmp & (1 << 31))) { |
| DRM_INFO("radeon: cp reset failed (0x%08X)\n", tmp); |
| } |
| } else { |
| DRM_INFO("radeon: cp idle (0x%08X)\n", tmp); |
| } |
| /* Align ring size */ |
| rb_bufsz = drm_order(ring_size / 8); |
| ring_size = (1 << (rb_bufsz + 1)) * 4; |
| r100_cp_load_microcode(rdev); |
| r = radeon_ring_init(rdev, ring_size); |
| if (r) { |
| return r; |
| } |
| /* Each time the cp read 1024 bytes (16 dword/quadword) update |
| * the rptr copy in system ram */ |
| rb_blksz = 9; |
| /* cp will read 128bytes at a time (4 dwords) */ |
| max_fetch = 1; |
| rdev->cp.align_mask = 16 - 1; |
| /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */ |
| pre_write_timer = 64; |
| /* Force CP_RB_WPTR write if written more than one time before the |
| * delay expire |
| */ |
| pre_write_limit = 0; |
| /* Setup the cp cache like this (cache size is 96 dwords) : |
| * RING 0 to 15 |
| * INDIRECT1 16 to 79 |
| * INDIRECT2 80 to 95 |
| * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) |
| * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords)) |
| * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords)) |
| * Idea being that most of the gpu cmd will be through indirect1 buffer |
| * so it gets the bigger cache. |
| */ |
| indirect2_start = 80; |
| indirect1_start = 16; |
| /* cp setup */ |
| WREG32(0x718, pre_write_timer | (pre_write_limit << 28)); |
| WREG32(RADEON_CP_RB_CNTL, |
| #ifdef __BIG_ENDIAN |
| RADEON_BUF_SWAP_32BIT | |
| #endif |
| REG_SET(RADEON_RB_BUFSZ, rb_bufsz) | |
| REG_SET(RADEON_RB_BLKSZ, rb_blksz) | |
| REG_SET(RADEON_MAX_FETCH, max_fetch) | |
| RADEON_RB_NO_UPDATE); |
| /* Set ring address */ |
| DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr); |
| WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr); |
| /* Force read & write ptr to 0 */ |
| tmp = RREG32(RADEON_CP_RB_CNTL); |
| WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); |
| WREG32(RADEON_CP_RB_RPTR_WR, 0); |
| WREG32(RADEON_CP_RB_WPTR, 0); |
| WREG32(RADEON_CP_RB_CNTL, tmp); |
| udelay(10); |
| rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR); |
| rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR); |
| /* Set cp mode to bus mastering & enable cp*/ |
| WREG32(RADEON_CP_CSQ_MODE, |
| REG_SET(RADEON_INDIRECT2_START, indirect2_start) | |
| REG_SET(RADEON_INDIRECT1_START, indirect1_start)); |
| WREG32(0x718, 0); |
| WREG32(0x744, 0x00004D4D); |
| WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM); |
| radeon_ring_start(rdev); |
| r = radeon_ring_test(rdev); |
| if (r) { |
| DRM_ERROR("radeon: cp isn't working (%d).\n", r); |
| return r; |
| } |
| rdev->cp.ready = true; |
| return 0; |
| } |
| #if 0 |
| void r100_cp_fini(struct radeon_device *rdev) |
| { |
| /* Disable ring */ |
| rdev->cp.ready = false; |
| WREG32(RADEON_CP_CSQ_CNTL, 0); |
| radeon_ring_fini(rdev); |
| DRM_INFO("radeon: cp finalized\n"); |
| } |
| void r100_cp_disable(struct radeon_device *rdev) |
| { |
| /* Disable ring */ |
| rdev->cp.ready = false; |
| WREG32(RADEON_CP_CSQ_MODE, 0); |
| WREG32(RADEON_CP_CSQ_CNTL, 0); |
| if (r100_gui_wait_for_idle(rdev)) { |
| printk(KERN_WARNING "Failed to wait GUI idle while " |
| "programming pipes. Bad things might happen.\n"); |
| } |
| } |
| #endif |
| int r100_cp_reset(struct radeon_device *rdev) |
| { |
| uint32_t tmp; |
| bool reinit_cp; |
| int i; |
| dbgprintf("%s\n\r",__FUNCTION__); |
| reinit_cp = rdev->cp.ready; |
| rdev->cp.ready = false; |
| WREG32(RADEON_CP_CSQ_MODE, 0); |
| WREG32(RADEON_CP_CSQ_CNTL, 0); |
| WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP); |
| (void)RREG32(RADEON_RBBM_SOFT_RESET); |
| udelay(200); |
| WREG32(RADEON_RBBM_SOFT_RESET, 0); |
| /* Wait to prevent race in RBBM_STATUS */ |
| mdelay(1); |
| for (i = 0; i < rdev->usec_timeout; i++) { |
| tmp = RREG32(RADEON_RBBM_STATUS); |
| if (!(tmp & (1 << 16))) { |
| DRM_INFO("CP reset succeed (RBBM_STATUS=0x%08X)\n", |
| tmp); |
| if (reinit_cp) { |
| return r100_cp_init(rdev, rdev->cp.ring_size); |
| } |
| return 0; |
| } |
| DRM_UDELAY(1); |
| } |
| tmp = RREG32(RADEON_RBBM_STATUS); |
| DRM_ERROR("Failed to reset CP (RBBM_STATUS=0x%08X)!\n", tmp); |
| return -1; |
| } |
| #if 0 |
| /* |
| * CS functions |
| */ |
| int r100_cs_parse_packet0(struct radeon_cs_parser *p, |
| struct radeon_cs_packet *pkt, |
| const unsigned *auth, unsigned n, |
| radeon_packet0_check_t check) |
| { |
| unsigned reg; |
| unsigned i, j, m; |
| unsigned idx; |
| int r; |
| idx = pkt->idx + 1; |
| reg = pkt->reg; |
| /* Check that register fall into register range |
| * determined by the number of entry (n) in the |
| * safe register bitmap. |
| */ |
| if (pkt->one_reg_wr) { |
| if ((reg >> 7) > n) { |
| return -EINVAL; |
| } |
| } else { |
| if (((reg + (pkt->count << 2)) >> 7) > n) { |
| return -EINVAL; |
| } |
| } |
| for (i = 0; i <= pkt->count; i++, idx++) { |
| j = (reg >> 7); |
| m = 1 << ((reg >> 2) & 31); |
| if (auth[j] & m) { |
| r = check(p, pkt, idx, reg); |
| if (r) { |
| return r; |
| } |
| } |
| if (pkt->one_reg_wr) { |
| if (!(auth[j] & m)) { |
| break; |
| } |
| } else { |
| reg += 4; |
| } |
| } |
| return 0; |
| } |
| void r100_cs_dump_packet(struct radeon_cs_parser *p, |
| struct radeon_cs_packet *pkt) |
| { |
| struct radeon_cs_chunk *ib_chunk; |
| volatile uint32_t *ib; |
| unsigned i; |
| unsigned idx; |
| ib = p->ib->ptr; |
| ib_chunk = &p->chunks[p->chunk_ib_idx]; |
| idx = pkt->idx; |
| for (i = 0; i <= (pkt->count + 1); i++, idx++) { |
| DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]); |
| } |
| } |
| /** |
| * r100_cs_packet_parse() - parse cp packet and point ib index to next packet |
| * @parser: parser structure holding parsing context. |
| * @pkt: where to store packet informations |
| * |
| * Assume that chunk_ib_index is properly set. Will return -EINVAL |
| * if packet is bigger than remaining ib size. or if packets is unknown. |
| **/ |
| int r100_cs_packet_parse(struct radeon_cs_parser *p, |
| struct radeon_cs_packet *pkt, |
| unsigned idx) |
| { |
| struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx]; |
| uint32_t header = ib_chunk->kdata[idx]; |
| if (idx >= ib_chunk->length_dw) { |
| DRM_ERROR("Can not parse packet at %d after CS end %d !\n", |
| idx, ib_chunk->length_dw); |
| return -EINVAL; |
| } |
| pkt->idx = idx; |
| pkt->type = CP_PACKET_GET_TYPE(header); |
| pkt->count = CP_PACKET_GET_COUNT(header); |
| switch (pkt->type) { |
| case PACKET_TYPE0: |
| pkt->reg = CP_PACKET0_GET_REG(header); |
| pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header); |
| break; |
| case PACKET_TYPE3: |
| pkt->opcode = CP_PACKET3_GET_OPCODE(header); |
| break; |
| case PACKET_TYPE2: |
| pkt->count = -1; |
| break; |
| default: |
| DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx); |
| return -EINVAL; |
| } |
| if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) { |
| DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n", |
| pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw); |
| return -EINVAL; |
| } |
| return 0; |
| } |
| /** |
| * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3 |
| * @parser: parser structure holding parsing context. |
| * @data: pointer to relocation data |
| * @offset_start: starting offset |
| * @offset_mask: offset mask (to align start offset on) |
| * @reloc: reloc informations |
| * |
| * Check next packet is relocation packet3, do bo validation and compute |
| * GPU offset using the provided start. |
| **/ |
| int r100_cs_packet_next_reloc(struct radeon_cs_parser *p, |
| struct radeon_cs_reloc **cs_reloc) |
| { |
| struct radeon_cs_chunk *ib_chunk; |
| struct radeon_cs_chunk *relocs_chunk; |
| struct radeon_cs_packet p3reloc; |
| unsigned idx; |
| int r; |
| if (p->chunk_relocs_idx == -1) { |
| DRM_ERROR("No relocation chunk !\n"); |
| return -EINVAL; |
| } |
| *cs_reloc = NULL; |
| ib_chunk = &p->chunks[p->chunk_ib_idx]; |
| relocs_chunk = &p->chunks[p->chunk_relocs_idx]; |
| r = r100_cs_packet_parse(p, &p3reloc, p->idx); |
| if (r) { |
| return r; |
| } |
| p->idx += p3reloc.count + 2; |
| if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) { |
| DRM_ERROR("No packet3 for relocation for packet at %d.\n", |
| p3reloc.idx); |
| r100_cs_dump_packet(p, &p3reloc); |
| return -EINVAL; |
| } |
| idx = ib_chunk->kdata[p3reloc.idx + 1]; |
| if (idx >= relocs_chunk->length_dw) { |
| DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", |
| idx, relocs_chunk->length_dw); |
| r100_cs_dump_packet(p, &p3reloc); |
| return -EINVAL; |
| } |
| /* FIXME: we assume reloc size is 4 dwords */ |
| *cs_reloc = p->relocs_ptr[(idx / 4)]; |
| return 0; |
| } |
| static int r100_packet0_check(struct radeon_cs_parser *p, |
| struct radeon_cs_packet *pkt) |
| { |
| struct radeon_cs_chunk *ib_chunk; |
| struct radeon_cs_reloc *reloc; |
| volatile uint32_t *ib; |
| uint32_t tmp; |
| unsigned reg; |
| unsigned i; |
| unsigned idx; |
| bool onereg; |
| int r; |
| ib = p->ib->ptr; |
| ib_chunk = &p->chunks[p->chunk_ib_idx]; |
| idx = pkt->idx + 1; |
| reg = pkt->reg; |
| onereg = false; |
| if (CP_PACKET0_GET_ONE_REG_WR(ib_chunk->kdata[pkt->idx])) { |
| onereg = true; |
| } |
| for (i = 0; i <= pkt->count; i++, idx++, reg += 4) { |
| switch (reg) { |
| /* FIXME: only allow PACKET3 blit? easier to check for out of |
| * range access */ |
| case RADEON_DST_PITCH_OFFSET: |
| case RADEON_SRC_PITCH_OFFSET: |
| r = r100_cs_packet_next_reloc(p, &reloc); |
| if (r) { |
| DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
| idx, reg); |
| r100_cs_dump_packet(p, pkt); |
| return r; |
| } |
| tmp = ib_chunk->kdata[idx] & 0x003fffff; |
| tmp += (((u32)reloc->lobj.gpu_offset) >> 10); |
| ib[idx] = (ib_chunk->kdata[idx] & 0xffc00000) | tmp; |
| break; |
| case RADEON_RB3D_DEPTHOFFSET: |
| case RADEON_RB3D_COLOROFFSET: |
| case R300_RB3D_COLOROFFSET0: |
| case R300_ZB_DEPTHOFFSET: |
| case R200_PP_TXOFFSET_0: |
| case R200_PP_TXOFFSET_1: |
| case R200_PP_TXOFFSET_2: |
| case R200_PP_TXOFFSET_3: |
| case R200_PP_TXOFFSET_4: |
| case R200_PP_TXOFFSET_5: |
| case RADEON_PP_TXOFFSET_0: |
| case RADEON_PP_TXOFFSET_1: |
| case RADEON_PP_TXOFFSET_2: |
| case R300_TX_OFFSET_0: |
| case R300_TX_OFFSET_0+4: |
| case R300_TX_OFFSET_0+8: |
| case R300_TX_OFFSET_0+12: |
| case R300_TX_OFFSET_0+16: |
| case R300_TX_OFFSET_0+20: |
| case R300_TX_OFFSET_0+24: |
| case R300_TX_OFFSET_0+28: |
| case R300_TX_OFFSET_0+32: |
| case R300_TX_OFFSET_0+36: |
| case R300_TX_OFFSET_0+40: |
| case R300_TX_OFFSET_0+44: |
| case R300_TX_OFFSET_0+48: |
| case R300_TX_OFFSET_0+52: |
| case R300_TX_OFFSET_0+56: |
| case R300_TX_OFFSET_0+60: |
| r = r100_cs_packet_next_reloc(p, &reloc); |
| if (r) { |
| DRM_ERROR("No reloc for ib[%d]=0x%04X\n", |
| idx, reg); |
| r100_cs_dump_packet(p, pkt); |
| return r; |
| } |
| ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); |
| break; |
| default: |
| /* FIXME: we don't want to allow anyothers packet */ |
| break; |
| } |
| if (onereg) { |
| /* FIXME: forbid onereg write to register on relocate */ |
| break; |
| } |
| } |
| return 0; |
| } |
| int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, |
| struct radeon_cs_packet *pkt, |
| struct radeon_object *robj) |
| { |
| struct radeon_cs_chunk *ib_chunk; |
| unsigned idx; |
| ib_chunk = &p->chunks[p->chunk_ib_idx]; |
| idx = pkt->idx + 1; |
| if ((ib_chunk->kdata[idx+2] + 1) > radeon_object_size(robj)) { |
| DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER " |
| "(need %u have %lu) !\n", |
| ib_chunk->kdata[idx+2] + 1, |
| radeon_object_size(robj)); |
| return -EINVAL; |
| } |
| return 0; |
| } |
| static int r100_packet3_check(struct radeon_cs_parser *p, |
| struct radeon_cs_packet *pkt) |
| { |
| struct radeon_cs_chunk *ib_chunk; |
| struct radeon_cs_reloc *reloc; |
| unsigned idx; |
| unsigned i, c; |
| volatile uint32_t *ib; |
| int r; |
| ib = p->ib->ptr; |
| ib_chunk = &p->chunks[p->chunk_ib_idx]; |
| idx = pkt->idx + 1; |
| switch (pkt->opcode) { |
| case PACKET3_3D_LOAD_VBPNTR: |
| c = ib_chunk->kdata[idx++]; |
| for (i = 0; i < (c - 1); i += 2, idx += 3) { |
| r = r100_cs_packet_next_reloc(p, &reloc); |
| if (r) { |
| DRM_ERROR("No reloc for packet3 %d\n", |
| pkt->opcode); |
| r100_cs_dump_packet(p, pkt); |
| return r; |
| } |
| ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset); |
| r = r100_cs_packet_next_reloc(p, &reloc); |
| if (r) { |
| DRM_ERROR("No reloc for packet3 %d\n", |
| pkt->opcode); |
| r100_cs_dump_packet(p, pkt); |
| return r; |
| } |
| ib[idx+2] = ib_chunk->kdata[idx+2] + ((u32)reloc->lobj.gpu_offset); |
| } |
| if (c & 1) { |
| r = r100_cs_packet_next_reloc(p, &reloc); |
| if (r) { |
| DRM_ERROR("No reloc for packet3 %d\n", |
| pkt->opcode); |
| r100_cs_dump_packet(p, pkt); |
| return r; |
| } |
| ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset); |
| } |
| break; |
| case PACKET3_INDX_BUFFER: |
| r = r100_cs_packet_next_reloc(p, &reloc); |
| if (r) { |
| DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); |
| r100_cs_dump_packet(p, pkt); |
| return r; |
| } |
| ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset); |
| r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); |
| if (r) { |
| return r; |
| } |
| break; |
| case 0x23: |
| /* FIXME: cleanup */ |
| /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */ |
| r = r100_cs_packet_next_reloc(p, &reloc); |
| if (r) { |
| DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); |
| r100_cs_dump_packet(p, pkt); |
| return r; |
| } |
| ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset); |
| break; |
| case PACKET3_3D_DRAW_IMMD: |
| /* triggers drawing using in-packet vertex data */ |
| case PACKET3_3D_DRAW_IMMD_2: |
| /* triggers drawing using in-packet vertex data */ |
| case PACKET3_3D_DRAW_VBUF_2: |
| /* triggers drawing of vertex buffers setup elsewhere */ |
| case PACKET3_3D_DRAW_INDX_2: |
| /* triggers drawing using indices to vertex buffer */ |
| case PACKET3_3D_DRAW_VBUF: |
| /* triggers drawing of vertex buffers setup elsewhere */ |
| case PACKET3_3D_DRAW_INDX: |
| /* triggers drawing using indices to vertex buffer */ |
| case PACKET3_NOP: |
| break; |
| default: |
| DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode); |
| return -EINVAL; |
| } |
| return 0; |
| } |
| int r100_cs_parse(struct radeon_cs_parser *p) |
| { |
| struct radeon_cs_packet pkt; |
| int r; |
| do { |
| r = r100_cs_packet_parse(p, &pkt, p->idx); |
| if (r) { |
| return r; |
| } |
| p->idx += pkt.count + 2; |
| switch (pkt.type) { |
| case PACKET_TYPE0: |
| r = r100_packet0_check(p, &pkt); |
| break; |
| case PACKET_TYPE2: |
| break; |
| case PACKET_TYPE3: |
| r = r100_packet3_check(p, &pkt); |
| break; |
| default: |
| DRM_ERROR("Unknown packet type %d !\n", |
| pkt.type); |
| return -EINVAL; |
| } |
| if (r) { |
| return r; |
| } |
| } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw); |
| return 0; |
| } |
| /* |
| * Global GPU functions |
| */ |
| void r100_errata(struct radeon_device *rdev) |
| { |
| rdev->pll_errata = 0; |
| if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) { |
| rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS; |
| } |
| if (rdev->family == CHIP_RV100 || |
| rdev->family == CHIP_RS100 || |
| rdev->family == CHIP_RS200) { |
| rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY; |
| } |
| } |
| #endif |
| /* Wait for vertical sync on primary CRTC */ |
| void r100_gpu_wait_for_vsync(struct radeon_device *rdev) |
| { |
| uint32_t crtc_gen_cntl, tmp; |
| int i; |
| crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL); |
| if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) || |
| !(crtc_gen_cntl & RADEON_CRTC_EN)) { |
| return; |
| } |
| /* Clear the CRTC_VBLANK_SAVE bit */ |
| WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR); |
| for (i = 0; i < rdev->usec_timeout; i++) { |
| tmp = RREG32(RADEON_CRTC_STATUS); |
| if (tmp & RADEON_CRTC_VBLANK_SAVE) { |
| return; |
| } |
| DRM_UDELAY(1); |
| } |
| } |
| /* Wait for vertical sync on secondary CRTC */ |
| void r100_gpu_wait_for_vsync2(struct radeon_device *rdev) |
| { |
| uint32_t crtc2_gen_cntl, tmp; |
| int i; |
| crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); |
| if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) || |
| !(crtc2_gen_cntl & RADEON_CRTC2_EN)) |
| return; |
| /* Clear the CRTC_VBLANK_SAVE bit */ |
| WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR); |
| for (i = 0; i < rdev->usec_timeout; i++) { |
| tmp = RREG32(RADEON_CRTC2_STATUS); |
| if (tmp & RADEON_CRTC2_VBLANK_SAVE) { |
| return; |
| } |
| DRM_UDELAY(1); |
| } |
| } |
| int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n) |
| { |
| unsigned i; |
| uint32_t tmp; |
| for (i = 0; i < rdev->usec_timeout; i++) { |
| tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK; |
| if (tmp >= n) { |
| return 0; |
| } |
| DRM_UDELAY(1); |
| } |
| return -1; |
| } |
| int r100_gui_wait_for_idle(struct radeon_device *rdev) |
| { |
| unsigned i; |
| uint32_t tmp; |
| if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) { |
| printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !" |
| " Bad things might happen.\n"); |
| } |
| for (i = 0; i < rdev->usec_timeout; i++) { |
| tmp = RREG32(RADEON_RBBM_STATUS); |
| if (!(tmp & (1 << 31))) { |
| return 0; |
| } |
| DRM_UDELAY(1); |
| } |
| return -1; |
| } |
| int r100_mc_wait_for_idle(struct radeon_device *rdev) |
| { |
| unsigned i; |
| uint32_t tmp; |
| for (i = 0; i < rdev->usec_timeout; i++) { |
| /* read MC_STATUS */ |
| tmp = RREG32(0x0150); |
| if (tmp & (1 << 2)) { |
| return 0; |
| } |
| DRM_UDELAY(1); |
| } |
| return -1; |
| } |
| void r100_gpu_init(struct radeon_device *rdev) |
| { |
| /* TODO: anythings to do here ? pipes ? */ |
| r100_hdp_reset(rdev); |
| } |
| void r100_hdp_reset(struct radeon_device *rdev) |
| { |
| uint32_t tmp; |
| dbgprintf("%s\n\r",__FUNCTION__); |
| tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL; |
| tmp |= (7 << 28); |
| WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE); |
| (void)RREG32(RADEON_HOST_PATH_CNTL); |
| udelay(200); |
| WREG32(RADEON_RBBM_SOFT_RESET, 0); |
| WREG32(RADEON_HOST_PATH_CNTL, tmp); |
| (void)RREG32(RADEON_HOST_PATH_CNTL); |
| } |
| int r100_rb2d_reset(struct radeon_device *rdev) |
| { |
| uint32_t tmp; |
| int i; |
| dbgprintf("%s\n\r",__FUNCTION__); |
| WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_E2); |
| (void)RREG32(RADEON_RBBM_SOFT_RESET); |
| udelay(200); |
| WREG32(RADEON_RBBM_SOFT_RESET, 0); |
| /* Wait to prevent race in RBBM_STATUS */ |
| mdelay(1); |
| for (i = 0; i < rdev->usec_timeout; i++) { |
| tmp = RREG32(RADEON_RBBM_STATUS); |
| if (!(tmp & (1 << 26))) { |
| DRM_INFO("RB2D reset succeed (RBBM_STATUS=0x%08X)\n", |
| tmp); |
| return 0; |
| } |
| DRM_UDELAY(1); |
| } |
| tmp = RREG32(RADEON_RBBM_STATUS); |
| DRM_ERROR("Failed to reset RB2D (RBBM_STATUS=0x%08X)!\n", tmp); |
| return -1; |
| } |
| #if 0 |
| int r100_gpu_reset(struct radeon_device *rdev) |
| { |
| uint32_t status; |
| /* reset order likely matter */ |
| status = RREG32(RADEON_RBBM_STATUS); |
| /* reset HDP */ |
| r100_hdp_reset(rdev); |
| /* reset rb2d */ |
| if (status & ((1 << 17) | (1 << 18) | (1 << 27))) { |
| r100_rb2d_reset(rdev); |
| } |
| /* TODO: reset 3D engine */ |
| /* reset CP */ |
| status = RREG32(RADEON_RBBM_STATUS); |
| if (status & (1 << 16)) { |
| r100_cp_reset(rdev); |
| } |
| /* Check if GPU is idle */ |
| status = RREG32(RADEON_RBBM_STATUS); |
| if (status & (1 << 31)) { |
| DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status); |
| return -1; |
| } |
| DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status); |
| return 0; |
| } |
| /* |
| * VRAM info |
| */ |
| static void r100_vram_get_type(struct radeon_device *rdev) |
| { |
| uint32_t tmp; |
| rdev->mc.vram_is_ddr = false; |
| if (rdev->flags & RADEON_IS_IGP) |
| rdev->mc.vram_is_ddr = true; |
| else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR) |
| rdev->mc.vram_is_ddr = true; |
| if ((rdev->family == CHIP_RV100) || |
| (rdev->family == CHIP_RS100) || |
| (rdev->family == CHIP_RS200)) { |
| tmp = RREG32(RADEON_MEM_CNTL); |
| if (tmp & RV100_HALF_MODE) { |
| rdev->mc.vram_width = 32; |
| } else { |
| rdev->mc.vram_width = 64; |
| } |
| if (rdev->flags & RADEON_SINGLE_CRTC) { |
| rdev->mc.vram_width /= 4; |
| rdev->mc.vram_is_ddr = true; |
| } |
| } else if (rdev->family <= CHIP_RV280) { |
| tmp = RREG32(RADEON_MEM_CNTL); |
| if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) { |
| rdev->mc.vram_width = 128; |
| } else { |
| rdev->mc.vram_width = 64; |
| } |
| } else { |
| /* newer IGPs */ |
| rdev->mc.vram_width = 128; |
| } |
| } |
| void r100_vram_info(struct radeon_device *rdev) |
| { |
| r100_vram_get_type(rdev); |
| if (rdev->flags & RADEON_IS_IGP) { |
| uint32_t tom; |
| /* read NB_TOM to get the amount of ram stolen for the GPU */ |
| tom = RREG32(RADEON_NB_TOM); |
| rdev->mc.vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16); |
| WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size); |
| } else { |
| rdev->mc.vram_size = RREG32(RADEON_CONFIG_MEMSIZE); |
| /* Some production boards of m6 will report 0 |
| * if it's 8 MB |
| */ |
| if (rdev->mc.vram_size == 0) { |
| rdev->mc.vram_size = 8192 * 1024; |
| WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size); |
| } |
| } |
| rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); |
| rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); |
| } |
| /* |
| * Indirect registers accessor |
| */ |
| void r100_pll_errata_after_index(struct radeon_device *rdev) |
| { |
| if (!(rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS)) { |
| return; |
| } |
| (void)RREG32(RADEON_CLOCK_CNTL_DATA); |
| (void)RREG32(RADEON_CRTC_GEN_CNTL); |
| } |
| static void r100_pll_errata_after_data(struct radeon_device *rdev) |
| { |
| /* This workarounds is necessary on RV100, RS100 and RS200 chips |
| * or the chip could hang on a subsequent access |
| */ |
| if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) { |
| udelay(5000); |
| } |
| /* This function is required to workaround a hardware bug in some (all?) |
| * revisions of the R300. This workaround should be called after every |
| * CLOCK_CNTL_INDEX register access. If not, register reads afterward |
| * may not be correct. |
| */ |
| if (rdev->pll_errata & CHIP_ERRATA_R300_CG) { |
| uint32_t save, tmp; |
| save = RREG32(RADEON_CLOCK_CNTL_INDEX); |
| tmp = save & ~(0x3f | RADEON_PLL_WR_EN); |
| WREG32(RADEON_CLOCK_CNTL_INDEX, tmp); |
| tmp = RREG32(RADEON_CLOCK_CNTL_DATA); |
| WREG32(RADEON_CLOCK_CNTL_INDEX, save); |
| } |
| } |
| uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg) |
| { |
| uint32_t data; |
| WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f); |
| r100_pll_errata_after_index(rdev); |
| data = RREG32(RADEON_CLOCK_CNTL_DATA); |
| r100_pll_errata_after_data(rdev); |
| return data; |
| } |
| void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
| { |
| WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN)); |
| r100_pll_errata_after_index(rdev); |
| WREG32(RADEON_CLOCK_CNTL_DATA, v); |
| r100_pll_errata_after_data(rdev); |
| } |
| #endif |
| uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg) |
| { |
| if (reg < 0x10000) |
| return readl(((void __iomem *)rdev->rmmio) + reg); |
| else { |
| writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); |
| return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); |
| } |
| } |
| void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
| { |
| if (reg < 0x10000) |
| writel(v, ((void __iomem *)rdev->rmmio) + reg); |
| else { |
| writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); |
| writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); |
| } |
| } |
| int r100_init(struct radeon_device *rdev) |
| { |
| return 0; |
| } |
| /drivers/video/drm/radeon/r300.h |
|---|
| 0,0 → 1,36 |
| /* |
| * Copyright 2008 Advanced Micro Devices, Inc. |
| * Copyright 2008 Red Hat Inc. |
| * Copyright 2009 Jerome Glisse. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice shall be included in |
| * all copies or substantial portions of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| * OTHER DEALINGS IN THE SOFTWARE. |
| * |
| * Authors: Dave Airlie |
| * Alex Deucher |
| * Jerome Glisse |
| */ |
| #ifndef R300_H |
| #define R300_H |
| struct r300_asic { |
| const unsigned *reg_safe_bm; |
| unsigned reg_safe_bm_size; |
| }; |
| #endif |
| /drivers/video/drm/radeon/r300_reg.h |
|---|
| 0,0 → 1,1782 |
| /* |
| * Copyright 2005 Nicolai Haehnle et al. |
| * Copyright 2008 Advanced Micro Devices, Inc. |
| * Copyright 2009 Jerome Glisse. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice shall be included in |
| * all copies or substantial portions of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| * OTHER DEALINGS IN THE SOFTWARE. |
| * |
| * Authors: Nicolai Haehnle |
| * Jerome Glisse |
| */ |
| #ifndef _R300_REG_H_ |
| #define _R300_REG_H_ |
| #define R300_MC_INIT_MISC_LAT_TIMER 0x180 |
| # define R300_MC_MISC__MC_CPR_INIT_LAT_SHIFT 0 |
| # define R300_MC_MISC__MC_VF_INIT_LAT_SHIFT 4 |
| # define R300_MC_MISC__MC_DISP0R_INIT_LAT_SHIFT 8 |
| # define R300_MC_MISC__MC_DISP1R_INIT_LAT_SHIFT 12 |
| # define R300_MC_MISC__MC_FIXED_INIT_LAT_SHIFT 16 |
| # define R300_MC_MISC__MC_E2R_INIT_LAT_SHIFT 20 |
| # define R300_MC_MISC__MC_SAME_PAGE_PRIO_SHIFT 24 |
| # define R300_MC_MISC__MC_GLOBW_INIT_LAT_SHIFT 28 |
| #define R300_MC_INIT_GFX_LAT_TIMER 0x154 |
| # define R300_MC_MISC__MC_G3D0R_INIT_LAT_SHIFT 0 |
| # define R300_MC_MISC__MC_G3D1R_INIT_LAT_SHIFT 4 |
| # define R300_MC_MISC__MC_G3D2R_INIT_LAT_SHIFT 8 |
| # define R300_MC_MISC__MC_G3D3R_INIT_LAT_SHIFT 12 |
| # define R300_MC_MISC__MC_TX0R_INIT_LAT_SHIFT 16 |
| # define R300_MC_MISC__MC_TX1R_INIT_LAT_SHIFT 20 |
| # define R300_MC_MISC__MC_GLOBR_INIT_LAT_SHIFT 24 |
| # define R300_MC_MISC__MC_GLOBW_FULL_LAT_SHIFT 28 |
| /* |
| * This file contains registers and constants for the R300. They have been |
| * found mostly by examining command buffers captured using glxtest, as well |
| * as by extrapolating some known registers and constants from the R200. |
| * I am fairly certain that they are correct unless stated otherwise |
| * in comments. |
| */ |
| #define R300_SE_VPORT_XSCALE 0x1D98 |
| #define R300_SE_VPORT_XOFFSET 0x1D9C |
| #define R300_SE_VPORT_YSCALE 0x1DA0 |
| #define R300_SE_VPORT_YOFFSET 0x1DA4 |
| #define R300_SE_VPORT_ZSCALE 0x1DA8 |
| #define R300_SE_VPORT_ZOFFSET 0x1DAC |
| /* |
| * Vertex Array Processing (VAP) Control |
| * Stolen from r200 code from Christoph Brill (It's a guess!) |
| */ |
| #define R300_VAP_CNTL 0x2080 |
| /* This register is written directly and also starts data section |
| * in many 3d CP_PACKET3's |
| */ |
| #define R300_VAP_VF_CNTL 0x2084 |
| # define R300_VAP_VF_CNTL__PRIM_TYPE__SHIFT 0 |
| # define R300_VAP_VF_CNTL__PRIM_NONE (0<<0) |
| # define R300_VAP_VF_CNTL__PRIM_POINTS (1<<0) |
| # define R300_VAP_VF_CNTL__PRIM_LINES (2<<0) |
| # define R300_VAP_VF_CNTL__PRIM_LINE_STRIP (3<<0) |
| # define R300_VAP_VF_CNTL__PRIM_TRIANGLES (4<<0) |
| # define R300_VAP_VF_CNTL__PRIM_TRIANGLE_FAN (5<<0) |
| # define R300_VAP_VF_CNTL__PRIM_TRIANGLE_STRIP (6<<0) |
| # define R300_VAP_VF_CNTL__PRIM_LINE_LOOP (12<<0) |
| # define R300_VAP_VF_CNTL__PRIM_QUADS (13<<0) |
| # define R300_VAP_VF_CNTL__PRIM_QUAD_STRIP (14<<0) |
| # define R300_VAP_VF_CNTL__PRIM_POLYGON (15<<0) |
| # define R300_VAP_VF_CNTL__PRIM_WALK__SHIFT 4 |
| /* State based - direct writes to registers trigger vertex |
| generation */ |
| # define R300_VAP_VF_CNTL__PRIM_WALK_STATE_BASED (0<<4) |
| # define R300_VAP_VF_CNTL__PRIM_WALK_INDICES (1<<4) |
| # define R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST (2<<4) |
| # define R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_EMBEDDED (3<<4) |
| /* I don't think I saw these three used.. */ |
| # define R300_VAP_VF_CNTL__COLOR_ORDER__SHIFT 6 |
| # define R300_VAP_VF_CNTL__TCL_OUTPUT_CTL_ENA__SHIFT 9 |
| # define R300_VAP_VF_CNTL__PROG_STREAM_ENA__SHIFT 10 |
| /* index size - when not set the indices are assumed to be 16 bit */ |
| # define R300_VAP_VF_CNTL__INDEX_SIZE_32bit (1<<11) |
| /* number of vertices */ |
| # define R300_VAP_VF_CNTL__NUM_VERTICES__SHIFT 16 |
| /* BEGIN: Wild guesses */ |
| #define R300_VAP_OUTPUT_VTX_FMT_0 0x2090 |
| # define R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT (1<<0) |
| # define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_PRESENT (1<<1) |
| # define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT (1<<2) /* GUESS */ |
| # define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_2_PRESENT (1<<3) /* GUESS */ |
| # define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_3_PRESENT (1<<4) /* GUESS */ |
| # define R300_VAP_OUTPUT_VTX_FMT_0__PT_SIZE_PRESENT (1<<16) /* GUESS */ |
| #define R300_VAP_OUTPUT_VTX_FMT_1 0x2094 |
| /* each of the following is 3 bits wide, specifies number |
| of components */ |
| # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_0_COMP_CNT_SHIFT 0 |
| # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_1_COMP_CNT_SHIFT 3 |
| # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_2_COMP_CNT_SHIFT 6 |
| # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_3_COMP_CNT_SHIFT 9 |
| # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_4_COMP_CNT_SHIFT 12 |
| # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_5_COMP_CNT_SHIFT 15 |
| # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_6_COMP_CNT_SHIFT 18 |
| # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_7_COMP_CNT_SHIFT 21 |
| /* END: Wild guesses */ |
| #define R300_SE_VTE_CNTL 0x20b0 |
| # define R300_VPORT_X_SCALE_ENA 0x00000001 |
| # define R300_VPORT_X_OFFSET_ENA 0x00000002 |
| # define R300_VPORT_Y_SCALE_ENA 0x00000004 |
| # define R300_VPORT_Y_OFFSET_ENA 0x00000008 |
| # define R300_VPORT_Z_SCALE_ENA 0x00000010 |
| # define R300_VPORT_Z_OFFSET_ENA 0x00000020 |
| # define R300_VTX_XY_FMT 0x00000100 |
| # define R300_VTX_Z_FMT 0x00000200 |
| # define R300_VTX_W0_FMT 0x00000400 |
| # define R300_VTX_W0_NORMALIZE 0x00000800 |
| # define R300_VTX_ST_DENORMALIZED 0x00001000 |
| /* BEGIN: Vertex data assembly - lots of uncertainties */ |
| /* gap */ |
| #define R300_VAP_CNTL_STATUS 0x2140 |
| # define R300_VC_NO_SWAP (0 << 0) |
| # define R300_VC_16BIT_SWAP (1 << 0) |
| # define R300_VC_32BIT_SWAP (2 << 0) |
| # define R300_VAP_TCL_BYPASS (1 << 8) |
| /* gap */ |
| /* Where do we get our vertex data? |
| * |
| * Vertex data either comes either from immediate mode registers or from |
| * vertex arrays. |
| * There appears to be no mixed mode (though we can force the pitch of |
| * vertex arrays to 0, effectively reusing the same element over and over |
| * again). |
| * |
| * Immediate mode is controlled by the INPUT_CNTL registers. I am not sure |
| * if these registers influence vertex array processing. |
| * |
| * Vertex arrays are controlled via the 3D_LOAD_VBPNTR packet3. |
| * |
| * In both cases, vertex attributes are then passed through INPUT_ROUTE. |
| * |
| * Beginning with INPUT_ROUTE_0_0 is a list of WORDs that route vertex data |
| * into the vertex processor's input registers. |
| * The first word routes the first input, the second word the second, etc. |
| * The corresponding input is routed into the register with the given index. |
| * The list is ended by a word with INPUT_ROUTE_END set. |
| * |
| * Always set COMPONENTS_4 in immediate mode. |
| */ |
| #define R300_VAP_INPUT_ROUTE_0_0 0x2150 |
| # define R300_INPUT_ROUTE_COMPONENTS_1 (0 << 0) |
| # define R300_INPUT_ROUTE_COMPONENTS_2 (1 << 0) |
| # define R300_INPUT_ROUTE_COMPONENTS_3 (2 << 0) |
| # define R300_INPUT_ROUTE_COMPONENTS_4 (3 << 0) |
| # define R300_INPUT_ROUTE_COMPONENTS_RGBA (4 << 0) /* GUESS */ |
| # define R300_VAP_INPUT_ROUTE_IDX_SHIFT 8 |
| # define R300_VAP_INPUT_ROUTE_IDX_MASK (31 << 8) /* GUESS */ |
| # define R300_VAP_INPUT_ROUTE_END (1 << 13) |
| # define R300_INPUT_ROUTE_IMMEDIATE_MODE (0 << 14) /* GUESS */ |
| # define R300_INPUT_ROUTE_FLOAT (1 << 14) /* GUESS */ |
| # define R300_INPUT_ROUTE_UNSIGNED_BYTE (2 << 14) /* GUESS */ |
| # define R300_INPUT_ROUTE_FLOAT_COLOR (3 << 14) /* GUESS */ |
| #define R300_VAP_INPUT_ROUTE_0_1 0x2154 |
| #define R300_VAP_INPUT_ROUTE_0_2 0x2158 |
| #define R300_VAP_INPUT_ROUTE_0_3 0x215C |
| #define R300_VAP_INPUT_ROUTE_0_4 0x2160 |
| #define R300_VAP_INPUT_ROUTE_0_5 0x2164 |
| #define R300_VAP_INPUT_ROUTE_0_6 0x2168 |
| #define R300_VAP_INPUT_ROUTE_0_7 0x216C |
| /* gap */ |
| /* Notes: |
| * - always set up to produce at least two attributes: |
| * if vertex program uses only position, fglrx will set normal, too |
| * - INPUT_CNTL_0_COLOR and INPUT_CNTL_COLOR bits are always equal. |
| */ |
| #define R300_VAP_INPUT_CNTL_0 0x2180 |
| # define R300_INPUT_CNTL_0_COLOR 0x00000001 |
| #define R300_VAP_INPUT_CNTL_1 0x2184 |
| # define R300_INPUT_CNTL_POS 0x00000001 |
| # define R300_INPUT_CNTL_NORMAL 0x00000002 |
| # define R300_INPUT_CNTL_COLOR 0x00000004 |
| # define R300_INPUT_CNTL_TC0 0x00000400 |
| # define R300_INPUT_CNTL_TC1 0x00000800 |
| # define R300_INPUT_CNTL_TC2 0x00001000 /* GUESS */ |
| # define R300_INPUT_CNTL_TC3 0x00002000 /* GUESS */ |
| # define R300_INPUT_CNTL_TC4 0x00004000 /* GUESS */ |
| # define R300_INPUT_CNTL_TC5 0x00008000 /* GUESS */ |
| # define R300_INPUT_CNTL_TC6 0x00010000 /* GUESS */ |
| # define R300_INPUT_CNTL_TC7 0x00020000 /* GUESS */ |
| /* gap */ |
| /* Words parallel to INPUT_ROUTE_0; All words that are active in INPUT_ROUTE_0 |
| * are set to a swizzling bit pattern, other words are 0. |
| * |
| * In immediate mode, the pattern is always set to xyzw. In vertex array |
| * mode, the swizzling pattern is e.g. used to set zw components in texture |
| * coordinates with only tweo components. |
| */ |
| #define R300_VAP_INPUT_ROUTE_1_0 0x21E0 |
| # define R300_INPUT_ROUTE_SELECT_X 0 |
| # define R300_INPUT_ROUTE_SELECT_Y 1 |
| # define R300_INPUT_ROUTE_SELECT_Z 2 |
| # define R300_INPUT_ROUTE_SELECT_W 3 |
| # define R300_INPUT_ROUTE_SELECT_ZERO 4 |
| # define R300_INPUT_ROUTE_SELECT_ONE 5 |
| # define R300_INPUT_ROUTE_SELECT_MASK 7 |
| # define R300_INPUT_ROUTE_X_SHIFT 0 |
| # define R300_INPUT_ROUTE_Y_SHIFT 3 |
| # define R300_INPUT_ROUTE_Z_SHIFT 6 |
| # define R300_INPUT_ROUTE_W_SHIFT 9 |
| # define R300_INPUT_ROUTE_ENABLE (15 << 12) |
| #define R300_VAP_INPUT_ROUTE_1_1 0x21E4 |
| #define R300_VAP_INPUT_ROUTE_1_2 0x21E8 |
| #define R300_VAP_INPUT_ROUTE_1_3 0x21EC |
| #define R300_VAP_INPUT_ROUTE_1_4 0x21F0 |
| #define R300_VAP_INPUT_ROUTE_1_5 0x21F4 |
| #define R300_VAP_INPUT_ROUTE_1_6 0x21F8 |
| #define R300_VAP_INPUT_ROUTE_1_7 0x21FC |
| /* END: Vertex data assembly */ |
| /* gap */ |
| /* BEGIN: Upload vertex program and data */ |
| /* |
| * The programmable vertex shader unit has a memory bank of unknown size |
| * that can be written to in 16 byte units by writing the address into |
| * UPLOAD_ADDRESS, followed by data in UPLOAD_DATA (multiples of 4 DWORDs). |
| * |
| * Pointers into the memory bank are always in multiples of 16 bytes. |
| * |
| * The memory bank is divided into areas with fixed meaning. |
| * |
| * Starting at address UPLOAD_PROGRAM: Vertex program instructions. |
| * Native limits reported by drivers from ATI suggest size 256 (i.e. 4KB), |
| * whereas the difference between known addresses suggests size 512. |
| * |
| * Starting at address UPLOAD_PARAMETERS: Vertex program parameters. |
| * Native reported limits and the VPI layout suggest size 256, whereas |
| * difference between known addresses suggests size 512. |
| * |
| * At address UPLOAD_POINTSIZE is a vector (0, 0, ps, 0), where ps is the |
| * floating point pointsize. The exact purpose of this state is uncertain, |
| * as there is also the R300_RE_POINTSIZE register. |
| * |
| * Multiple vertex programs and parameter sets can be loaded at once, |
| * which could explain the size discrepancy. |
| */ |
| #define R300_VAP_PVS_UPLOAD_ADDRESS 0x2200 |
| # define R300_PVS_UPLOAD_PROGRAM 0x00000000 |
| # define R300_PVS_UPLOAD_PARAMETERS 0x00000200 |
| # define R300_PVS_UPLOAD_POINTSIZE 0x00000406 |
| /* gap */ |
| #define R300_VAP_PVS_UPLOAD_DATA 0x2208 |
| /* END: Upload vertex program and data */ |
| /* gap */ |
| /* I do not know the purpose of this register. However, I do know that |
| * it is set to 221C_CLEAR for clear operations and to 221C_NORMAL |
| * for normal rendering. |
| */ |
| #define R300_VAP_UNKNOWN_221C 0x221C |
| # define R300_221C_NORMAL 0x00000000 |
| # define R300_221C_CLEAR 0x0001C000 |
| /* These seem to be per-pixel and per-vertex X and Y clipping planes. The first |
| * plane is per-pixel and the second plane is per-vertex. |
| * |
| * This was determined by experimentation alone but I believe it is correct. |
| * |
| * These registers are called X_QUAD0_1_FL to X_QUAD0_4_FL by glxtest. |
| */ |
| #define R300_VAP_CLIP_X_0 0x2220 |
| #define R300_VAP_CLIP_X_1 0x2224 |
| #define R300_VAP_CLIP_Y_0 0x2228 |
| #define R300_VAP_CLIP_Y_1 0x2230 |
| /* gap */ |
| /* Sometimes, END_OF_PKT and 0x2284=0 are the only commands sent between |
| * rendering commands and overwriting vertex program parameters. |
| * Therefore, I suspect writing zero to 0x2284 synchronizes the engine and |
| * avoids bugs caused by still running shaders reading bad data from memory. |
| */ |
| #define R300_VAP_PVS_STATE_FLUSH_REG 0x2284 |
| /* Absolutely no clue what this register is about. */ |
| #define R300_VAP_UNKNOWN_2288 0x2288 |
| # define R300_2288_R300 0x00750000 /* -- nh */ |
| # define R300_2288_RV350 0x0000FFFF /* -- Vladimir */ |
| /* gap */ |
| /* Addresses are relative to the vertex program instruction area of the |
| * memory bank. PROGRAM_END points to the last instruction of the active |
| * program |
| * |
| * The meaning of the two UNKNOWN fields is obviously not known. However, |
| * experiments so far have shown that both *must* point to an instruction |
| * inside the vertex program, otherwise the GPU locks up. |
| * |
| * fglrx usually sets CNTL_3_UNKNOWN to the end of the program and |
| * R300_PVS_CNTL_1_POS_END_SHIFT points to instruction where last write to |
| * position takes place. |
| * |
| * Most likely this is used to ignore rest of the program in cases |
| * where group of verts arent visible. For some reason this "section" |
| * is sometimes accepted other instruction that have no relationship with |
| * position calculations. |
| */ |
| #define R300_VAP_PVS_CNTL_1 0x22D0 |
| # define R300_PVS_CNTL_1_PROGRAM_START_SHIFT 0 |
| # define R300_PVS_CNTL_1_POS_END_SHIFT 10 |
| # define R300_PVS_CNTL_1_PROGRAM_END_SHIFT 20 |
| /* Addresses are relative the the vertex program parameters area. */ |
| #define R300_VAP_PVS_CNTL_2 0x22D4 |
| # define R300_PVS_CNTL_2_PARAM_OFFSET_SHIFT 0 |
| # define R300_PVS_CNTL_2_PARAM_COUNT_SHIFT 16 |
| #define R300_VAP_PVS_CNTL_3 0x22D8 |
| # define R300_PVS_CNTL_3_PROGRAM_UNKNOWN_SHIFT 10 |
| # define R300_PVS_CNTL_3_PROGRAM_UNKNOWN2_SHIFT 0 |
| /* The entire range from 0x2300 to 0x2AC inclusive seems to be used for |
| * immediate vertices |
| */ |
| #define R300_VAP_VTX_COLOR_R 0x2464 |
| #define R300_VAP_VTX_COLOR_G 0x2468 |
| #define R300_VAP_VTX_COLOR_B 0x246C |
| #define R300_VAP_VTX_POS_0_X_1 0x2490 /* used for glVertex2*() */ |
| #define R300_VAP_VTX_POS_0_Y_1 0x2494 |
| #define R300_VAP_VTX_COLOR_PKD 0x249C /* RGBA */ |
| #define R300_VAP_VTX_POS_0_X_2 0x24A0 /* used for glVertex3*() */ |
| #define R300_VAP_VTX_POS_0_Y_2 0x24A4 |
| #define R300_VAP_VTX_POS_0_Z_2 0x24A8 |
| /* write 0 to indicate end of packet? */ |
| #define R300_VAP_VTX_END_OF_PKT 0x24AC |
| /* gap */ |
| /* These are values from r300_reg/r300_reg.h - they are known to be correct |
| * and are here so we can use one register file instead of several |
| * - Vladimir |
| */ |
| #define R300_GB_VAP_RASTER_VTX_FMT_0 0x4000 |
| # define R300_GB_VAP_RASTER_VTX_FMT_0__POS_PRESENT (1<<0) |
| # define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_0_PRESENT (1<<1) |
| # define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_1_PRESENT (1<<2) |
| # define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_2_PRESENT (1<<3) |
| # define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_3_PRESENT (1<<4) |
| # define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_SPACE (0xf<<5) |
| # define R300_GB_VAP_RASTER_VTX_FMT_0__PT_SIZE_PRESENT (0x1<<16) |
| #define R300_GB_VAP_RASTER_VTX_FMT_1 0x4004 |
| /* each of the following is 3 bits wide, specifies number |
| of components */ |
| # define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_0_COMP_CNT_SHIFT 0 |
| # define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_1_COMP_CNT_SHIFT 3 |
| # define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_2_COMP_CNT_SHIFT 6 |
| # define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_3_COMP_CNT_SHIFT 9 |
| # define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_4_COMP_CNT_SHIFT 12 |
| # define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_5_COMP_CNT_SHIFT 15 |
| # define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_6_COMP_CNT_SHIFT 18 |
| # define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_7_COMP_CNT_SHIFT 21 |
| /* UNK30 seems to enables point to quad transformation on textures |
| * (or something closely related to that). |
| * This bit is rather fatal at the time being due to lackings at pixel |
| * shader side |
| */ |
| #define R300_GB_ENABLE 0x4008 |
| # define R300_GB_POINT_STUFF_ENABLE (1<<0) |
| # define R300_GB_LINE_STUFF_ENABLE (1<<1) |
| # define R300_GB_TRIANGLE_STUFF_ENABLE (1<<2) |
| # define R300_GB_STENCIL_AUTO_ENABLE (1<<4) |
| # define R300_GB_UNK31 (1<<31) |
| /* each of the following is 2 bits wide */ |
| #define R300_GB_TEX_REPLICATE 0 |
| #define R300_GB_TEX_ST 1 |
| #define R300_GB_TEX_STR 2 |
| # define R300_GB_TEX0_SOURCE_SHIFT 16 |
| # define R300_GB_TEX1_SOURCE_SHIFT 18 |
| # define R300_GB_TEX2_SOURCE_SHIFT 20 |
| # define R300_GB_TEX3_SOURCE_SHIFT 22 |
| # define R300_GB_TEX4_SOURCE_SHIFT 24 |
| # define R300_GB_TEX5_SOURCE_SHIFT 26 |
| # define R300_GB_TEX6_SOURCE_SHIFT 28 |
| # define R300_GB_TEX7_SOURCE_SHIFT 30 |
| /* MSPOS - positions for multisample antialiasing (?) */ |
| #define R300_GB_MSPOS0 0x4010 |
| /* shifts - each of the fields is 4 bits */ |
| # define R300_GB_MSPOS0__MS_X0_SHIFT 0 |
| # define R300_GB_MSPOS0__MS_Y0_SHIFT 4 |
| # define R300_GB_MSPOS0__MS_X1_SHIFT 8 |
| # define R300_GB_MSPOS0__MS_Y1_SHIFT 12 |
| # define R300_GB_MSPOS0__MS_X2_SHIFT 16 |
| # define R300_GB_MSPOS0__MS_Y2_SHIFT 20 |
| # define R300_GB_MSPOS0__MSBD0_Y 24 |
| # define R300_GB_MSPOS0__MSBD0_X 28 |
| #define R300_GB_MSPOS1 0x4014 |
| # define R300_GB_MSPOS1__MS_X3_SHIFT 0 |
| # define R300_GB_MSPOS1__MS_Y3_SHIFT 4 |
| # define R300_GB_MSPOS1__MS_X4_SHIFT 8 |
| # define R300_GB_MSPOS1__MS_Y4_SHIFT 12 |
| # define R300_GB_MSPOS1__MS_X5_SHIFT 16 |
| # define R300_GB_MSPOS1__MS_Y5_SHIFT 20 |
| # define R300_GB_MSPOS1__MSBD1 24 |
| #define R300_GB_TILE_CONFIG 0x4018 |
| # define R300_GB_TILE_ENABLE (1<<0) |
| # define R300_GB_TILE_PIPE_COUNT_RV300 0 |
| # define R300_GB_TILE_PIPE_COUNT_R300 (3<<1) |
| # define R300_GB_TILE_PIPE_COUNT_R420 (7<<1) |
| # define R300_GB_TILE_PIPE_COUNT_RV410 (3<<1) |
| # define R300_GB_TILE_SIZE_8 0 |
| # define R300_GB_TILE_SIZE_16 (1<<4) |
| # define R300_GB_TILE_SIZE_32 (2<<4) |
| # define R300_GB_SUPER_SIZE_1 (0<<6) |
| # define R300_GB_SUPER_SIZE_2 (1<<6) |
| # define R300_GB_SUPER_SIZE_4 (2<<6) |
| # define R300_GB_SUPER_SIZE_8 (3<<6) |
| # define R300_GB_SUPER_SIZE_16 (4<<6) |
| # define R300_GB_SUPER_SIZE_32 (5<<6) |
| # define R300_GB_SUPER_SIZE_64 (6<<6) |
| # define R300_GB_SUPER_SIZE_128 (7<<6) |
| # define R300_GB_SUPER_X_SHIFT 9 /* 3 bits wide */ |
| # define R300_GB_SUPER_Y_SHIFT 12 /* 3 bits wide */ |
| # define R300_GB_SUPER_TILE_A 0 |
| # define R300_GB_SUPER_TILE_B (1<<15) |
| # define R300_GB_SUBPIXEL_1_12 0 |
| # define R300_GB_SUBPIXEL_1_16 (1<<16) |
| #define R300_GB_FIFO_SIZE 0x4024 |
| /* each of the following is 2 bits wide */ |
| #define R300_GB_FIFO_SIZE_32 0 |
| #define R300_GB_FIFO_SIZE_64 1 |
| #define R300_GB_FIFO_SIZE_128 2 |
| #define R300_GB_FIFO_SIZE_256 3 |
| # define R300_SC_IFIFO_SIZE_SHIFT 0 |
| # define R300_SC_TZFIFO_SIZE_SHIFT 2 |
| # define R300_SC_BFIFO_SIZE_SHIFT 4 |
| # define R300_US_OFIFO_SIZE_SHIFT 12 |
| # define R300_US_WFIFO_SIZE_SHIFT 14 |
| /* the following use the same constants as above, but meaning is |
| is times 2 (i.e. instead of 32 words it means 64 */ |
| # define R300_RS_TFIFO_SIZE_SHIFT 6 |
| # define R300_RS_CFIFO_SIZE_SHIFT 8 |
| # define R300_US_RAM_SIZE_SHIFT 10 |
| /* watermarks, 3 bits wide */ |
| # define R300_RS_HIGHWATER_COL_SHIFT 16 |
| # define R300_RS_HIGHWATER_TEX_SHIFT 19 |
| # define R300_OFIFO_HIGHWATER_SHIFT 22 /* two bits only */ |
| # define R300_CUBE_FIFO_HIGHWATER_COL_SHIFT 24 |
| #define R300_GB_SELECT 0x401C |
| # define R300_GB_FOG_SELECT_C0A 0 |
| # define R300_GB_FOG_SELECT_C1A 1 |
| # define R300_GB_FOG_SELECT_C2A 2 |
| # define R300_GB_FOG_SELECT_C3A 3 |
| # define R300_GB_FOG_SELECT_1_1_W 4 |
| # define R300_GB_FOG_SELECT_Z 5 |
| # define R300_GB_DEPTH_SELECT_Z 0 |
| # define R300_GB_DEPTH_SELECT_1_1_W (1<<3) |
| # define R300_GB_W_SELECT_1_W 0 |
| # define R300_GB_W_SELECT_1 (1<<4) |
| #define R300_GB_AA_CONFIG 0x4020 |
| # define R300_AA_DISABLE 0x00 |
| # define R300_AA_ENABLE 0x01 |
| # define R300_AA_SUBSAMPLES_2 0 |
| # define R300_AA_SUBSAMPLES_3 (1<<1) |
| # define R300_AA_SUBSAMPLES_4 (2<<1) |
| # define R300_AA_SUBSAMPLES_6 (3<<1) |
| /* gap */ |
| /* Zero to flush caches. */ |
| #define R300_TX_INVALTAGS 0x4100 |
| #define R300_TX_FLUSH 0x0 |
| /* The upper enable bits are guessed, based on fglrx reported limits. */ |
| #define R300_TX_ENABLE 0x4104 |
| # define R300_TX_ENABLE_0 (1 << 0) |
| # define R300_TX_ENABLE_1 (1 << 1) |
| # define R300_TX_ENABLE_2 (1 << 2) |
| # define R300_TX_ENABLE_3 (1 << 3) |
| # define R300_TX_ENABLE_4 (1 << 4) |
| # define R300_TX_ENABLE_5 (1 << 5) |
| # define R300_TX_ENABLE_6 (1 << 6) |
| # define R300_TX_ENABLE_7 (1 << 7) |
| # define R300_TX_ENABLE_8 (1 << 8) |
| # define R300_TX_ENABLE_9 (1 << 9) |
| # define R300_TX_ENABLE_10 (1 << 10) |
| # define R300_TX_ENABLE_11 (1 << 11) |
| # define R300_TX_ENABLE_12 (1 << 12) |
| # define R300_TX_ENABLE_13 (1 << 13) |
| # define R300_TX_ENABLE_14 (1 << 14) |
| # define R300_TX_ENABLE_15 (1 << 15) |
| /* The pointsize is given in multiples of 6. The pointsize can be |
| * enormous: Clear() renders a single point that fills the entire |
| * framebuffer. |
| */ |
| #define R300_RE_POINTSIZE 0x421C |
| # define R300_POINTSIZE_Y_SHIFT 0 |
| # define R300_POINTSIZE_Y_MASK (0xFFFF << 0) /* GUESS */ |
| # define R300_POINTSIZE_X_SHIFT 16 |
| # define R300_POINTSIZE_X_MASK (0xFFFF << 16) /* GUESS */ |
| # define R300_POINTSIZE_MAX (R300_POINTSIZE_Y_MASK / 6) |
| /* The line width is given in multiples of 6. |
| * In default mode lines are classified as vertical lines. |
| * HO: horizontal |
| * VE: vertical or horizontal |
| * HO & VE: no classification |
| */ |
| #define R300_RE_LINE_CNT 0x4234 |
| # define R300_LINESIZE_SHIFT 0 |
| # define R300_LINESIZE_MASK (0xFFFF << 0) /* GUESS */ |
| # define R300_LINESIZE_MAX (R300_LINESIZE_MASK / 6) |
| # define R300_LINE_CNT_HO (1 << 16) |
| # define R300_LINE_CNT_VE (1 << 17) |
| /* Some sort of scale or clamp value for texcoordless textures. */ |
| #define R300_RE_UNK4238 0x4238 |
| /* Something shade related */ |
| #define R300_RE_SHADE 0x4274 |
| #define R300_RE_SHADE_MODEL 0x4278 |
| # define R300_RE_SHADE_MODEL_SMOOTH 0x3aaaa |
| # define R300_RE_SHADE_MODEL_FLAT 0x39595 |
| /* Dangerous */ |
| #define R300_RE_POLYGON_MODE 0x4288 |
| # define R300_PM_ENABLED (1 << 0) |
| # define R300_PM_FRONT_POINT (0 << 0) |
| # define R300_PM_BACK_POINT (0 << 0) |
| # define R300_PM_FRONT_LINE (1 << 4) |
| # define R300_PM_FRONT_FILL (1 << 5) |
| # define R300_PM_BACK_LINE (1 << 7) |
| # define R300_PM_BACK_FILL (1 << 8) |
| /* Fog parameters */ |
| #define R300_RE_FOG_SCALE 0x4294 |
| #define R300_RE_FOG_START 0x4298 |
| /* Not sure why there are duplicate of factor and constant values. |
| * My best guess so far is that there are separate zbiases for test and write. |
| * Ordering might be wrong. |
| * Some of the tests indicate that fgl has a fallback implementation of zbias |
| * via pixel shaders. |
| */ |
| #define R300_RE_ZBIAS_CNTL 0x42A0 /* GUESS */ |
| #define R300_RE_ZBIAS_T_FACTOR 0x42A4 |
| #define R300_RE_ZBIAS_T_CONSTANT 0x42A8 |
| #define R300_RE_ZBIAS_W_FACTOR 0x42AC |
| #define R300_RE_ZBIAS_W_CONSTANT 0x42B0 |
| /* This register needs to be set to (1<<1) for RV350 to correctly |
| * perform depth test (see --vb-triangles in r300_demo) |
| * Don't know about other chips. - Vladimir |
| * This is set to 3 when GL_POLYGON_OFFSET_FILL is on. |
| * My guess is that there are two bits for each zbias primitive |
| * (FILL, LINE, POINT). |
| * One to enable depth test and one for depth write. |
| * Yet this doesnt explain why depth writes work ... |
| */ |
| #define R300_RE_OCCLUSION_CNTL 0x42B4 |
| # define R300_OCCLUSION_ON (1<<1) |
| #define R300_RE_CULL_CNTL 0x42B8 |
| # define R300_CULL_FRONT (1 << 0) |
| # define R300_CULL_BACK (1 << 1) |
| # define R300_FRONT_FACE_CCW (0 << 2) |
| # define R300_FRONT_FACE_CW (1 << 2) |
| /* BEGIN: Rasterization / Interpolators - many guesses */ |
| /* 0_UNKNOWN_18 has always been set except for clear operations. |
| * TC_CNT is the number of incoming texture coordinate sets (i.e. it depends |
| * on the vertex program, *not* the fragment program) |
| */ |
| #define R300_RS_CNTL_0 0x4300 |
| # define R300_RS_CNTL_TC_CNT_SHIFT 2 |
| # define R300_RS_CNTL_TC_CNT_MASK (7 << 2) |
| /* number of color interpolators used */ |
| # define R300_RS_CNTL_CI_CNT_SHIFT 7 |
| # define R300_RS_CNTL_0_UNKNOWN_18 (1 << 18) |
| /* Guess: RS_CNTL_1 holds the index of the highest used RS_ROUTE_n |
| register. */ |
| #define R300_RS_CNTL_1 0x4304 |
| /* gap */ |
| /* Only used for texture coordinates. |
| * Use the source field to route texture coordinate input from the |
| * vertex program to the desired interpolator. Note that the source |
| * field is relative to the outputs the vertex program *actually* |
| * writes. If a vertex program only writes texcoord[1], this will |
| * be source index 0. |
| * Set INTERP_USED on all interpolators that produce data used by |
| * the fragment program. INTERP_USED looks like a swizzling mask, |
| * but I haven't seen it used that way. |
| * |
| * Note: The _UNKNOWN constants are always set in their respective |
| * register. I don't know if this is necessary. |
| */ |
| #define R300_RS_INTERP_0 0x4310 |
| #define R300_RS_INTERP_1 0x4314 |
| # define R300_RS_INTERP_1_UNKNOWN 0x40 |
| #define R300_RS_INTERP_2 0x4318 |
| # define R300_RS_INTERP_2_UNKNOWN 0x80 |
| #define R300_RS_INTERP_3 0x431C |
| # define R300_RS_INTERP_3_UNKNOWN 0xC0 |
| #define R300_RS_INTERP_4 0x4320 |
| #define R300_RS_INTERP_5 0x4324 |
| #define R300_RS_INTERP_6 0x4328 |
| #define R300_RS_INTERP_7 0x432C |
| # define R300_RS_INTERP_SRC_SHIFT 2 |
| # define R300_RS_INTERP_SRC_MASK (7 << 2) |
| # define R300_RS_INTERP_USED 0x00D10000 |
| /* These DWORDs control how vertex data is routed into fragment program |
| * registers, after interpolators. |
| */ |
| #define R300_RS_ROUTE_0 0x4330 |
| #define R300_RS_ROUTE_1 0x4334 |
| #define R300_RS_ROUTE_2 0x4338 |
| #define R300_RS_ROUTE_3 0x433C /* GUESS */ |
| #define R300_RS_ROUTE_4 0x4340 /* GUESS */ |
| #define R300_RS_ROUTE_5 0x4344 /* GUESS */ |
| #define R300_RS_ROUTE_6 0x4348 /* GUESS */ |
| #define R300_RS_ROUTE_7 0x434C /* GUESS */ |
| # define R300_RS_ROUTE_SOURCE_INTERP_0 0 |
| # define R300_RS_ROUTE_SOURCE_INTERP_1 1 |
| # define R300_RS_ROUTE_SOURCE_INTERP_2 2 |
| # define R300_RS_ROUTE_SOURCE_INTERP_3 3 |
| # define R300_RS_ROUTE_SOURCE_INTERP_4 4 |
| # define R300_RS_ROUTE_SOURCE_INTERP_5 5 /* GUESS */ |
| # define R300_RS_ROUTE_SOURCE_INTERP_6 6 /* GUESS */ |
| # define R300_RS_ROUTE_SOURCE_INTERP_7 7 /* GUESS */ |
| # define R300_RS_ROUTE_ENABLE (1 << 3) /* GUESS */ |
| # define R300_RS_ROUTE_DEST_SHIFT 6 |
| # define R300_RS_ROUTE_DEST_MASK (31 << 6) /* GUESS */ |
| /* Special handling for color: When the fragment program uses color, |
| * the ROUTE_0_COLOR bit is set and ROUTE_0_COLOR_DEST contains the |
| * color register index. |
| * |
| * Apperently you may set the R300_RS_ROUTE_0_COLOR bit, but not provide any |
| * R300_RS_ROUTE_0_COLOR_DEST value; this setup is used for clearing the state. |
| * See r300_ioctl.c:r300EmitClearState. I'm not sure if this setup is strictly |
| * correct or not. - Oliver. |
| */ |
| # define R300_RS_ROUTE_0_COLOR (1 << 14) |
| # define R300_RS_ROUTE_0_COLOR_DEST_SHIFT 17 |
| # define R300_RS_ROUTE_0_COLOR_DEST_MASK (31 << 17) /* GUESS */ |
| /* As above, but for secondary color */ |
| # define R300_RS_ROUTE_1_COLOR1 (1 << 14) |
| # define R300_RS_ROUTE_1_COLOR1_DEST_SHIFT 17 |
| # define R300_RS_ROUTE_1_COLOR1_DEST_MASK (31 << 17) |
| # define R300_RS_ROUTE_1_UNKNOWN11 (1 << 11) |
| /* END: Rasterization / Interpolators - many guesses */ |
| /* Hierarchical Z Enable */ |
| #define R300_SC_HYPERZ 0x43a4 |
| # define R300_SC_HYPERZ_DISABLE (0 << 0) |
| # define R300_SC_HYPERZ_ENABLE (1 << 0) |
| # define R300_SC_HYPERZ_MIN (0 << 1) |
| # define R300_SC_HYPERZ_MAX (1 << 1) |
| # define R300_SC_HYPERZ_ADJ_256 (0 << 2) |
| # define R300_SC_HYPERZ_ADJ_128 (1 << 2) |
| # define R300_SC_HYPERZ_ADJ_64 (2 << 2) |
| # define R300_SC_HYPERZ_ADJ_32 (3 << 2) |
| # define R300_SC_HYPERZ_ADJ_16 (4 << 2) |
| # define R300_SC_HYPERZ_ADJ_8 (5 << 2) |
| # define R300_SC_HYPERZ_ADJ_4 (6 << 2) |
| # define R300_SC_HYPERZ_ADJ_2 (7 << 2) |
| # define R300_SC_HYPERZ_HZ_Z0MIN_NO (0 << 5) |
| # define R300_SC_HYPERZ_HZ_Z0MIN (1 << 5) |
| # define R300_SC_HYPERZ_HZ_Z0MAX_NO (0 << 6) |
| # define R300_SC_HYPERZ_HZ_Z0MAX (1 << 6) |
| #define R300_SC_EDGERULE 0x43a8 |
| /* BEGIN: Scissors and cliprects */ |
| /* There are four clipping rectangles. Their corner coordinates are inclusive. |
| * Every pixel is assigned a number from 0 and 15 by setting bits 0-3 depending |
| * on whether the pixel is inside cliprects 0-3, respectively. For example, |
| * if a pixel is inside cliprects 0 and 1, but outside 2 and 3, it is assigned |
| * the number 3 (binary 0011). |
| * Iff the bit corresponding to the pixel's number in RE_CLIPRECT_CNTL is set, |
| * the pixel is rasterized. |
| * |
| * In addition to this, there is a scissors rectangle. Only pixels inside the |
| * scissors rectangle are drawn. (coordinates are inclusive) |
| * |
| * For some reason, the top-left corner of the framebuffer is at (1440, 1440) |
| * for the purpose of clipping and scissors. |
| */ |
| #define R300_RE_CLIPRECT_TL_0 0x43B0 |
| #define R300_RE_CLIPRECT_BR_0 0x43B4 |
| #define R300_RE_CLIPRECT_TL_1 0x43B8 |
| #define R300_RE_CLIPRECT_BR_1 0x43BC |
| #define R300_RE_CLIPRECT_TL_2 0x43C0 |
| #define R300_RE_CLIPRECT_BR_2 0x43C4 |
| #define R300_RE_CLIPRECT_TL_3 0x43C8 |
| #define R300_RE_CLIPRECT_BR_3 0x43CC |
| # define R300_CLIPRECT_OFFSET 1440 |
| # define R300_CLIPRECT_MASK 0x1FFF |
| # define R300_CLIPRECT_X_SHIFT 0 |
| # define R300_CLIPRECT_X_MASK (0x1FFF << 0) |
| # define R300_CLIPRECT_Y_SHIFT 13 |
| # define R300_CLIPRECT_Y_MASK (0x1FFF << 13) |
| #define R300_RE_CLIPRECT_CNTL 0x43D0 |
| # define R300_CLIP_OUT (1 << 0) |
| # define R300_CLIP_0 (1 << 1) |
| # define R300_CLIP_1 (1 << 2) |
| # define R300_CLIP_10 (1 << 3) |
| # define R300_CLIP_2 (1 << 4) |
| # define R300_CLIP_20 (1 << 5) |
| # define R300_CLIP_21 (1 << 6) |
| # define R300_CLIP_210 (1 << 7) |
| # define R300_CLIP_3 (1 << 8) |
| # define R300_CLIP_30 (1 << 9) |
| # define R300_CLIP_31 (1 << 10) |
| # define R300_CLIP_310 (1 << 11) |
| # define R300_CLIP_32 (1 << 12) |
| # define R300_CLIP_320 (1 << 13) |
| # define R300_CLIP_321 (1 << 14) |
| # define R300_CLIP_3210 (1 << 15) |
| /* gap */ |
| #define R300_RE_SCISSORS_TL 0x43E0 |
| #define R300_RE_SCISSORS_BR 0x43E4 |
| # define R300_SCISSORS_OFFSET 1440 |
| # define R300_SCISSORS_X_SHIFT 0 |
| # define R300_SCISSORS_X_MASK (0x1FFF << 0) |
| # define R300_SCISSORS_Y_SHIFT 13 |
| # define R300_SCISSORS_Y_MASK (0x1FFF << 13) |
| /* END: Scissors and cliprects */ |
| /* BEGIN: Texture specification */ |
| /* |
| * The texture specification dwords are grouped by meaning and not by texture |
| * unit. This means that e.g. the offset for texture image unit N is found in |
| * register TX_OFFSET_0 + (4*N) |
| */ |
| #define R300_TX_FILTER_0 0x4400 |
| # define R300_TX_REPEAT 0 |
| # define R300_TX_MIRRORED 1 |
| # define R300_TX_CLAMP 4 |
| # define R300_TX_CLAMP_TO_EDGE 2 |
| # define R300_TX_CLAMP_TO_BORDER 6 |
| # define R300_TX_WRAP_S_SHIFT 0 |
| # define R300_TX_WRAP_S_MASK (7 << 0) |
| # define R300_TX_WRAP_T_SHIFT 3 |
| # define R300_TX_WRAP_T_MASK (7 << 3) |
| # define R300_TX_WRAP_Q_SHIFT 6 |
| # define R300_TX_WRAP_Q_MASK (7 << 6) |
| # define R300_TX_MAG_FILTER_NEAREST (1 << 9) |
| # define R300_TX_MAG_FILTER_LINEAR (2 << 9) |
| # define R300_TX_MAG_FILTER_MASK (3 << 9) |
| # define R300_TX_MIN_FILTER_NEAREST (1 << 11) |
| # define R300_TX_MIN_FILTER_LINEAR (2 << 11) |
| # define R300_TX_MIN_FILTER_NEAREST_MIP_NEAREST (5 << 11) |
| # define R300_TX_MIN_FILTER_NEAREST_MIP_LINEAR (9 << 11) |
| # define R300_TX_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 11) |
| # define R300_TX_MIN_FILTER_LINEAR_MIP_LINEAR (10 << 11) |
| /* NOTE: NEAREST doesnt seem to exist. |
| * Im not seting MAG_FILTER_MASK and (3 << 11) on for all |
| * anisotropy modes because that would void selected mag filter |
| */ |
| # define R300_TX_MIN_FILTER_ANISO_NEAREST (0 << 13) |
| # define R300_TX_MIN_FILTER_ANISO_LINEAR (0 << 13) |
| # define R300_TX_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (1 << 13) |
| # define R300_TX_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (2 << 13) |
| # define R300_TX_MIN_FILTER_MASK ( (15 << 11) | (3 << 13) ) |
| # define R300_TX_MAX_ANISO_1_TO_1 (0 << 21) |
| # define R300_TX_MAX_ANISO_2_TO_1 (2 << 21) |
| # define R300_TX_MAX_ANISO_4_TO_1 (4 << 21) |
| # define R300_TX_MAX_ANISO_8_TO_1 (6 << 21) |
| # define R300_TX_MAX_ANISO_16_TO_1 (8 << 21) |
| # define R300_TX_MAX_ANISO_MASK (14 << 21) |
| #define R300_TX_FILTER1_0 0x4440 |
| # define R300_CHROMA_KEY_MODE_DISABLE 0 |
| # define R300_CHROMA_KEY_FORCE 1 |
| # define R300_CHROMA_KEY_BLEND 2 |
| # define R300_MC_ROUND_NORMAL (0<<2) |
| # define R300_MC_ROUND_MPEG4 (1<<2) |
| # define R300_LOD_BIAS_MASK 0x1fff |
| # define R300_EDGE_ANISO_EDGE_DIAG (0<<13) |
| # define R300_EDGE_ANISO_EDGE_ONLY (1<<13) |
| # define R300_MC_COORD_TRUNCATE_DISABLE (0<<14) |
| # define R300_MC_COORD_TRUNCATE_MPEG (1<<14) |
| # define R300_TX_TRI_PERF_0_8 (0<<15) |
| # define R300_TX_TRI_PERF_1_8 (1<<15) |
| # define R300_TX_TRI_PERF_1_4 (2<<15) |
| # define R300_TX_TRI_PERF_3_8 (3<<15) |
| # define R300_ANISO_THRESHOLD_MASK (7<<17) |
| #define R300_TX_SIZE_0 0x4480 |
| # define R300_TX_WIDTHMASK_SHIFT 0 |
| # define R300_TX_WIDTHMASK_MASK (2047 << 0) |
| # define R300_TX_HEIGHTMASK_SHIFT 11 |
| # define R300_TX_HEIGHTMASK_MASK (2047 << 11) |
| # define R300_TX_UNK23 (1 << 23) |
| # define R300_TX_MAX_MIP_LEVEL_SHIFT 26 |
| # define R300_TX_MAX_MIP_LEVEL_MASK (0xf << 26) |
| # define R300_TX_SIZE_PROJECTED (1<<30) |
| # define R300_TX_SIZE_TXPITCH_EN (1<<31) |
| #define R300_TX_FORMAT_0 0x44C0 |
| /* The interpretation of the format word by Wladimir van der Laan */ |
| /* The X, Y, Z and W refer to the layout of the components. |
| They are given meanings as R, G, B and Alpha by the swizzle |
| specification */ |
| # define R300_TX_FORMAT_X8 0x0 |
| # define R300_TX_FORMAT_X16 0x1 |
| # define R300_TX_FORMAT_Y4X4 0x2 |
| # define R300_TX_FORMAT_Y8X8 0x3 |
| # define R300_TX_FORMAT_Y16X16 0x4 |
| # define R300_TX_FORMAT_Z3Y3X2 0x5 |
| # define R300_TX_FORMAT_Z5Y6X5 0x6 |
| # define R300_TX_FORMAT_Z6Y5X5 0x7 |
| # define R300_TX_FORMAT_Z11Y11X10 0x8 |
| # define R300_TX_FORMAT_Z10Y11X11 0x9 |
| # define R300_TX_FORMAT_W4Z4Y4X4 0xA |
| # define R300_TX_FORMAT_W1Z5Y5X5 0xB |
| # define R300_TX_FORMAT_W8Z8Y8X8 0xC |
| # define R300_TX_FORMAT_W2Z10Y10X10 0xD |
| # define R300_TX_FORMAT_W16Z16Y16X16 0xE |
| # define R300_TX_FORMAT_DXT1 0xF |
| # define R300_TX_FORMAT_DXT3 0x10 |
| # define R300_TX_FORMAT_DXT5 0x11 |
| # define R300_TX_FORMAT_D3DMFT_CxV8U8 0x12 /* no swizzle */ |
| # define R300_TX_FORMAT_A8R8G8B8 0x13 /* no swizzle */ |
| # define R300_TX_FORMAT_B8G8_B8G8 0x14 /* no swizzle */ |
| # define R300_TX_FORMAT_G8R8_G8B8 0x15 /* no swizzle */ |
| /* 0x16 - some 16 bit green format.. ?? */ |
| # define R300_TX_FORMAT_UNK25 (1 << 25) /* no swizzle */ |
| # define R300_TX_FORMAT_CUBIC_MAP (1 << 26) |
| /* gap */ |
| /* Floating point formats */ |
| /* Note - hardware supports both 16 and 32 bit floating point */ |
| # define R300_TX_FORMAT_FL_I16 0x18 |
| # define R300_TX_FORMAT_FL_I16A16 0x19 |
| # define R300_TX_FORMAT_FL_R16G16B16A16 0x1A |
| # define R300_TX_FORMAT_FL_I32 0x1B |
| # define R300_TX_FORMAT_FL_I32A32 0x1C |
| # define R300_TX_FORMAT_FL_R32G32B32A32 0x1D |
| /* alpha modes, convenience mostly */ |
| /* if you have alpha, pick constant appropriate to the |
| number of channels (1 for I8, 2 for I8A8, 4 for R8G8B8A8, etc */ |
| # define R300_TX_FORMAT_ALPHA_1CH 0x000 |
| # define R300_TX_FORMAT_ALPHA_2CH 0x200 |
| # define R300_TX_FORMAT_ALPHA_4CH 0x600 |
| # define R300_TX_FORMAT_ALPHA_NONE 0xA00 |
| /* Swizzling */ |
| /* constants */ |
| # define R300_TX_FORMAT_X 0 |
| # define R300_TX_FORMAT_Y 1 |
| # define R300_TX_FORMAT_Z 2 |
| # define R300_TX_FORMAT_W 3 |
| # define R300_TX_FORMAT_ZERO 4 |
| # define R300_TX_FORMAT_ONE 5 |
| /* 2.0*Z, everything above 1.0 is set to 0.0 */ |
| # define R300_TX_FORMAT_CUT_Z 6 |
| /* 2.0*W, everything above 1.0 is set to 0.0 */ |
| # define R300_TX_FORMAT_CUT_W 7 |
| # define R300_TX_FORMAT_B_SHIFT 18 |
| # define R300_TX_FORMAT_G_SHIFT 15 |
| # define R300_TX_FORMAT_R_SHIFT 12 |
| # define R300_TX_FORMAT_A_SHIFT 9 |
| /* Convenience macro to take care of layout and swizzling */ |
| # define R300_EASY_TX_FORMAT(B, G, R, A, FMT) ( \ |
| ((R300_TX_FORMAT_##B)<<R300_TX_FORMAT_B_SHIFT) \ |
| | ((R300_TX_FORMAT_##G)<<R300_TX_FORMAT_G_SHIFT) \ |
| | ((R300_TX_FORMAT_##R)<<R300_TX_FORMAT_R_SHIFT) \ |
| | ((R300_TX_FORMAT_##A)<<R300_TX_FORMAT_A_SHIFT) \ |
| | (R300_TX_FORMAT_##FMT) \ |
| ) |
| /* These can be ORed with result of R300_EASY_TX_FORMAT() |
| We don't really know what they do. Take values from a |
| constant color ? */ |
| # define R300_TX_FORMAT_CONST_X (1<<5) |
| # define R300_TX_FORMAT_CONST_Y (2<<5) |
| # define R300_TX_FORMAT_CONST_Z (4<<5) |
| # define R300_TX_FORMAT_CONST_W (8<<5) |
| # define R300_TX_FORMAT_YUV_MODE 0x00800000 |
| #define R300_TX_PITCH_0 0x4500 /* obvious missing in gap */ |
| #define R300_TX_OFFSET_0 0x4540 |
| /* BEGIN: Guess from R200 */ |
| # define R300_TXO_ENDIAN_NO_SWAP (0 << 0) |
| # define R300_TXO_ENDIAN_BYTE_SWAP (1 << 0) |
| # define R300_TXO_ENDIAN_WORD_SWAP (2 << 0) |
| # define R300_TXO_ENDIAN_HALFDW_SWAP (3 << 0) |
| # define R300_TXO_MACRO_TILE (1 << 2) |
| # define R300_TXO_MICRO_TILE (1 << 3) |
| # define R300_TXO_OFFSET_MASK 0xffffffe0 |
| # define R300_TXO_OFFSET_SHIFT 5 |
| /* END: Guess from R200 */ |
| /* 32 bit chroma key */ |
| #define R300_TX_CHROMA_KEY_0 0x4580 |
| /* ff00ff00 == { 0, 1.0, 0, 1.0 } */ |
| #define R300_TX_BORDER_COLOR_0 0x45C0 |
| /* END: Texture specification */ |
| /* BEGIN: Fragment program instruction set */ |
| /* Fragment programs are written directly into register space. |
| * There are separate instruction streams for texture instructions and ALU |
| * instructions. |
| * In order to synchronize these streams, the program is divided into up |
| * to 4 nodes. Each node begins with a number of TEX operations, followed |
| * by a number of ALU operations. |
| * The first node can have zero TEX ops, all subsequent nodes must have at |
| * least |
| * one TEX ops. |
| * All nodes must have at least one ALU op. |
| * |
| * The index of the last node is stored in PFS_CNTL_0: A value of 0 means |
| * 1 node, a value of 3 means 4 nodes. |
| * The total amount of instructions is defined in PFS_CNTL_2. The offsets are |
| * offsets into the respective instruction streams, while *_END points to the |
| * last instruction relative to this offset. |
| */ |
| #define R300_PFS_CNTL_0 0x4600 |
| # define R300_PFS_CNTL_LAST_NODES_SHIFT 0 |
| # define R300_PFS_CNTL_LAST_NODES_MASK (3 << 0) |
| # define R300_PFS_CNTL_FIRST_NODE_HAS_TEX (1 << 3) |
| #define R300_PFS_CNTL_1 0x4604 |
| /* There is an unshifted value here which has so far always been equal to the |
| * index of the highest used temporary register. |
| */ |
| #define R300_PFS_CNTL_2 0x4608 |
| # define R300_PFS_CNTL_ALU_OFFSET_SHIFT 0 |
| # define R300_PFS_CNTL_ALU_OFFSET_MASK (63 << 0) |
| # define R300_PFS_CNTL_ALU_END_SHIFT 6 |
| # define R300_PFS_CNTL_ALU_END_MASK (63 << 6) |
| # define R300_PFS_CNTL_TEX_OFFSET_SHIFT 12 |
| # define R300_PFS_CNTL_TEX_OFFSET_MASK (31 << 12) /* GUESS */ |
| # define R300_PFS_CNTL_TEX_END_SHIFT 18 |
| # define R300_PFS_CNTL_TEX_END_MASK (31 << 18) /* GUESS */ |
| /* gap */ |
| /* Nodes are stored backwards. The last active node is always stored in |
| * PFS_NODE_3. |
| * Example: In a 2-node program, NODE_0 and NODE_1 are set to 0. The |
| * first node is stored in NODE_2, the second node is stored in NODE_3. |
| * |
| * Offsets are relative to the master offset from PFS_CNTL_2. |
| */ |
| #define R300_PFS_NODE_0 0x4610 |
| #define R300_PFS_NODE_1 0x4614 |
| #define R300_PFS_NODE_2 0x4618 |
| #define R300_PFS_NODE_3 0x461C |
| # define R300_PFS_NODE_ALU_OFFSET_SHIFT 0 |
| # define R300_PFS_NODE_ALU_OFFSET_MASK (63 << 0) |
| # define R300_PFS_NODE_ALU_END_SHIFT 6 |
| # define R300_PFS_NODE_ALU_END_MASK (63 << 6) |
| # define R300_PFS_NODE_TEX_OFFSET_SHIFT 12 |
| # define R300_PFS_NODE_TEX_OFFSET_MASK (31 << 12) |
| # define R300_PFS_NODE_TEX_END_SHIFT 17 |
| # define R300_PFS_NODE_TEX_END_MASK (31 << 17) |
| # define R300_PFS_NODE_OUTPUT_COLOR (1 << 22) |
| # define R300_PFS_NODE_OUTPUT_DEPTH (1 << 23) |
| /* TEX |
| * As far as I can tell, texture instructions cannot write into output |
| * registers directly. A subsequent ALU instruction is always necessary, |
| * even if it's just MAD o0, r0, 1, 0 |
| */ |
| #define R300_PFS_TEXI_0 0x4620 |
| # define R300_FPITX_SRC_SHIFT 0 |
| # define R300_FPITX_SRC_MASK (31 << 0) |
| /* GUESS */ |
| # define R300_FPITX_SRC_CONST (1 << 5) |
| # define R300_FPITX_DST_SHIFT 6 |
| # define R300_FPITX_DST_MASK (31 << 6) |
| # define R300_FPITX_IMAGE_SHIFT 11 |
| /* GUESS based on layout and native limits */ |
| # define R300_FPITX_IMAGE_MASK (15 << 11) |
| /* Unsure if these are opcodes, or some kind of bitfield, but this is how |
| * they were set when I checked |
| */ |
| # define R300_FPITX_OPCODE_SHIFT 15 |
| # define R300_FPITX_OP_TEX 1 |
| # define R300_FPITX_OP_KIL 2 |
| # define R300_FPITX_OP_TXP 3 |
| # define R300_FPITX_OP_TXB 4 |
| # define R300_FPITX_OPCODE_MASK (7 << 15) |
| /* ALU |
| * The ALU instructions register blocks are enumerated according to the order |
| * in which fglrx. I assume there is space for 64 instructions, since |
| * each block has space for a maximum of 64 DWORDs, and this matches reported |
| * native limits. |
| * |
| * The basic functional block seems to be one MAD for each color and alpha, |
| * and an adder that adds all components after the MUL. |
| * - ADD, MUL, MAD etc.: use MAD with appropriate neutral operands |
| * - DP4: Use OUTC_DP4, OUTA_DP4 |
| * - DP3: Use OUTC_DP3, OUTA_DP4, appropriate alpha operands |
| * - DPH: Use OUTC_DP4, OUTA_DP4, appropriate alpha operands |
| * - CMPH: If ARG2 > 0.5, return ARG0, else return ARG1 |
| * - CMP: If ARG2 < 0, return ARG1, else return ARG0 |
| * - FLR: use FRC+MAD |
| * - XPD: use MAD+MAD |
| * - SGE, SLT: use MAD+CMP |
| * - RSQ: use ABS modifier for argument |
| * - Use OUTC_REPL_ALPHA to write results of an alpha-only operation |
| * (e.g. RCP) into color register |
| * - apparently, there's no quick DST operation |
| * - fglrx set FPI2_UNKNOWN_31 on a "MAD fragment.color, tmp0, tmp1, tmp2" |
| * - fglrx set FPI2_UNKNOWN_31 on a "MAX r2, r1, c0" |
| * - fglrx once set FPI0_UNKNOWN_31 on a "FRC r1, r1" |
| * |
| * Operand selection |
| * First stage selects three sources from the available registers and |
| * constant parameters. This is defined in INSTR1 (color) and INSTR3 (alpha). |
| * fglrx sorts the three source fields: Registers before constants, |
| * lower indices before higher indices; I do not know whether this is |
| * necessary. |
| * |
| * fglrx fills unused sources with "read constant 0" |
| * According to specs, you cannot select more than two different constants. |
| * |
| * Second stage selects the operands from the sources. This is defined in |
| * INSTR0 (color) and INSTR2 (alpha). You can also select the special constants |
| * zero and one. |
| * Swizzling and negation happens in this stage, as well. |
| * |
| * Important: Color and alpha seem to be mostly separate, i.e. their sources |
| * selection appears to be fully independent (the register storage is probably |
| * physically split into a color and an alpha section). |
| * However (because of the apparent physical split), there is some interaction |
| * WRT swizzling. If, for example, you want to load an R component into an |
| * Alpha operand, this R component is taken from a *color* source, not from |
| * an alpha source. The corresponding register doesn't even have to appear in |
| * the alpha sources list. (I hope this all makes sense to you) |
| * |
| * Destination selection |
| * The destination register index is in FPI1 (color) and FPI3 (alpha) |
| * together with enable bits. |
| * There are separate enable bits for writing into temporary registers |
| * (DSTC_REG_* /DSTA_REG) and and program output registers (DSTC_OUTPUT_* |
| * /DSTA_OUTPUT). You can write to both at once, or not write at all (the |
| * same index must be used for both). |
| * |
| * Note: There is a special form for LRP |
| * - Argument order is the same as in ARB_fragment_program. |
| * - Operation is MAD |
| * - ARG1 is set to ARGC_SRC1C_LRP/ARGC_SRC1A_LRP |
| * - Set FPI0/FPI2_SPECIAL_LRP |
| * Arbitrary LRP (including support for swizzling) requires vanilla MAD+MAD |
| */ |
| #define R300_PFS_INSTR1_0 0x46C0 |
| # define R300_FPI1_SRC0C_SHIFT 0 |
| # define R300_FPI1_SRC0C_MASK (31 << 0) |
| # define R300_FPI1_SRC0C_CONST (1 << 5) |
| # define R300_FPI1_SRC1C_SHIFT 6 |
| # define R300_FPI1_SRC1C_MASK (31 << 6) |
| # define R300_FPI1_SRC1C_CONST (1 << 11) |
| # define R300_FPI1_SRC2C_SHIFT 12 |
| # define R300_FPI1_SRC2C_MASK (31 << 12) |
| # define R300_FPI1_SRC2C_CONST (1 << 17) |
| # define R300_FPI1_SRC_MASK 0x0003ffff |
| # define R300_FPI1_DSTC_SHIFT 18 |
| # define R300_FPI1_DSTC_MASK (31 << 18) |
| # define R300_FPI1_DSTC_REG_MASK_SHIFT 23 |
| # define R300_FPI1_DSTC_REG_X (1 << 23) |
| # define R300_FPI1_DSTC_REG_Y (1 << 24) |
| # define R300_FPI1_DSTC_REG_Z (1 << 25) |
| # define R300_FPI1_DSTC_OUTPUT_MASK_SHIFT 26 |
| # define R300_FPI1_DSTC_OUTPUT_X (1 << 26) |
| # define R300_FPI1_DSTC_OUTPUT_Y (1 << 27) |
| # define R300_FPI1_DSTC_OUTPUT_Z (1 << 28) |
| #define R300_PFS_INSTR3_0 0x47C0 |
| # define R300_FPI3_SRC0A_SHIFT 0 |
| # define R300_FPI3_SRC0A_MASK (31 << 0) |
| # define R300_FPI3_SRC0A_CONST (1 << 5) |
| # define R300_FPI3_SRC1A_SHIFT 6 |
| # define R300_FPI3_SRC1A_MASK (31 << 6) |
| # define R300_FPI3_SRC1A_CONST (1 << 11) |
| # define R300_FPI3_SRC2A_SHIFT 12 |
| # define R300_FPI3_SRC2A_MASK (31 << 12) |
| # define R300_FPI3_SRC2A_CONST (1 << 17) |
| # define R300_FPI3_SRC_MASK 0x0003ffff |
| # define R300_FPI3_DSTA_SHIFT 18 |
| # define R300_FPI3_DSTA_MASK (31 << 18) |
| # define R300_FPI3_DSTA_REG (1 << 23) |
| # define R300_FPI3_DSTA_OUTPUT (1 << 24) |
| # define R300_FPI3_DSTA_DEPTH (1 << 27) |
| #define R300_PFS_INSTR0_0 0x48C0 |
| # define R300_FPI0_ARGC_SRC0C_XYZ 0 |
| # define R300_FPI0_ARGC_SRC0C_XXX 1 |
| # define R300_FPI0_ARGC_SRC0C_YYY 2 |
| # define R300_FPI0_ARGC_SRC0C_ZZZ 3 |
| # define R300_FPI0_ARGC_SRC1C_XYZ 4 |
| # define R300_FPI0_ARGC_SRC1C_XXX 5 |
| # define R300_FPI0_ARGC_SRC1C_YYY 6 |
| # define R300_FPI0_ARGC_SRC1C_ZZZ 7 |
| # define R300_FPI0_ARGC_SRC2C_XYZ 8 |
| # define R300_FPI0_ARGC_SRC2C_XXX 9 |
| # define R300_FPI0_ARGC_SRC2C_YYY 10 |
| # define R300_FPI0_ARGC_SRC2C_ZZZ 11 |
| # define R300_FPI0_ARGC_SRC0A 12 |
| # define R300_FPI0_ARGC_SRC1A 13 |
| # define R300_FPI0_ARGC_SRC2A 14 |
| # define R300_FPI0_ARGC_SRC1C_LRP 15 |
| # define R300_FPI0_ARGC_ZERO 20 |
| # define R300_FPI0_ARGC_ONE 21 |
| /* GUESS */ |
| # define R300_FPI0_ARGC_HALF 22 |
| # define R300_FPI0_ARGC_SRC0C_YZX 23 |
| # define R300_FPI0_ARGC_SRC1C_YZX 24 |
| # define R300_FPI0_ARGC_SRC2C_YZX 25 |
| # define R300_FPI0_ARGC_SRC0C_ZXY 26 |
| # define R300_FPI0_ARGC_SRC1C_ZXY 27 |
| # define R300_FPI0_ARGC_SRC2C_ZXY 28 |
| # define R300_FPI0_ARGC_SRC0CA_WZY 29 |
| # define R300_FPI0_ARGC_SRC1CA_WZY 30 |
| # define R300_FPI0_ARGC_SRC2CA_WZY 31 |
| # define R300_FPI0_ARG0C_SHIFT 0 |
| # define R300_FPI0_ARG0C_MASK (31 << 0) |
| # define R300_FPI0_ARG0C_NEG (1 << 5) |
| # define R300_FPI0_ARG0C_ABS (1 << 6) |
| # define R300_FPI0_ARG1C_SHIFT 7 |
| # define R300_FPI0_ARG1C_MASK (31 << 7) |
| # define R300_FPI0_ARG1C_NEG (1 << 12) |
| # define R300_FPI0_ARG1C_ABS (1 << 13) |
| # define R300_FPI0_ARG2C_SHIFT 14 |
| # define R300_FPI0_ARG2C_MASK (31 << 14) |
| # define R300_FPI0_ARG2C_NEG (1 << 19) |
| # define R300_FPI0_ARG2C_ABS (1 << 20) |
| # define R300_FPI0_SPECIAL_LRP (1 << 21) |
| # define R300_FPI0_OUTC_MAD (0 << 23) |
| # define R300_FPI0_OUTC_DP3 (1 << 23) |
| # define R300_FPI0_OUTC_DP4 (2 << 23) |
| # define R300_FPI0_OUTC_MIN (4 << 23) |
| # define R300_FPI0_OUTC_MAX (5 << 23) |
| # define R300_FPI0_OUTC_CMPH (7 << 23) |
| # define R300_FPI0_OUTC_CMP (8 << 23) |
| # define R300_FPI0_OUTC_FRC (9 << 23) |
| # define R300_FPI0_OUTC_REPL_ALPHA (10 << 23) |
| # define R300_FPI0_OUTC_SAT (1 << 30) |
| # define R300_FPI0_INSERT_NOP (1 << 31) |
| #define R300_PFS_INSTR2_0 0x49C0 |
| # define R300_FPI2_ARGA_SRC0C_X 0 |
| # define R300_FPI2_ARGA_SRC0C_Y 1 |
| # define R300_FPI2_ARGA_SRC0C_Z 2 |
| # define R300_FPI2_ARGA_SRC1C_X 3 |
| # define R300_FPI2_ARGA_SRC1C_Y 4 |
| # define R300_FPI2_ARGA_SRC1C_Z 5 |
| # define R300_FPI2_ARGA_SRC2C_X 6 |
| # define R300_FPI2_ARGA_SRC2C_Y 7 |
| # define R300_FPI2_ARGA_SRC2C_Z 8 |
| # define R300_FPI2_ARGA_SRC0A 9 |
| # define R300_FPI2_ARGA_SRC1A 10 |
| # define R300_FPI2_ARGA_SRC2A 11 |
| # define R300_FPI2_ARGA_SRC1A_LRP 15 |
| # define R300_FPI2_ARGA_ZERO 16 |
| # define R300_FPI2_ARGA_ONE 17 |
| /* GUESS */ |
| # define R300_FPI2_ARGA_HALF 18 |
| # define R300_FPI2_ARG0A_SHIFT 0 |
| # define R300_FPI2_ARG0A_MASK (31 << 0) |
| # define R300_FPI2_ARG0A_NEG (1 << 5) |
| /* GUESS */ |
| # define R300_FPI2_ARG0A_ABS (1 << 6) |
| # define R300_FPI2_ARG1A_SHIFT 7 |
| # define R300_FPI2_ARG1A_MASK (31 << 7) |
| # define R300_FPI2_ARG1A_NEG (1 << 12) |
| /* GUESS */ |
| # define R300_FPI2_ARG1A_ABS (1 << 13) |
| # define R300_FPI2_ARG2A_SHIFT 14 |
| # define R300_FPI2_ARG2A_MASK (31 << 14) |
| # define R300_FPI2_ARG2A_NEG (1 << 19) |
| /* GUESS */ |
| # define R300_FPI2_ARG2A_ABS (1 << 20) |
| # define R300_FPI2_SPECIAL_LRP (1 << 21) |
| # define R300_FPI2_OUTA_MAD (0 << 23) |
| # define R300_FPI2_OUTA_DP4 (1 << 23) |
| # define R300_FPI2_OUTA_MIN (2 << 23) |
| # define R300_FPI2_OUTA_MAX (3 << 23) |
| # define R300_FPI2_OUTA_CMP (6 << 23) |
| # define R300_FPI2_OUTA_FRC (7 << 23) |
| # define R300_FPI2_OUTA_EX2 (8 << 23) |
| # define R300_FPI2_OUTA_LG2 (9 << 23) |
| # define R300_FPI2_OUTA_RCP (10 << 23) |
| # define R300_FPI2_OUTA_RSQ (11 << 23) |
| # define R300_FPI2_OUTA_SAT (1 << 30) |
| # define R300_FPI2_UNKNOWN_31 (1 << 31) |
| /* END: Fragment program instruction set */ |
| /* Fog state and color */ |
| #define R300_RE_FOG_STATE 0x4BC0 |
| # define R300_FOG_ENABLE (1 << 0) |
| # define R300_FOG_MODE_LINEAR (0 << 1) |
| # define R300_FOG_MODE_EXP (1 << 1) |
| # define R300_FOG_MODE_EXP2 (2 << 1) |
| # define R300_FOG_MODE_MASK (3 << 1) |
| #define R300_FOG_COLOR_R 0x4BC8 |
| #define R300_FOG_COLOR_G 0x4BCC |
| #define R300_FOG_COLOR_B 0x4BD0 |
| #define R300_PP_ALPHA_TEST 0x4BD4 |
| # define R300_REF_ALPHA_MASK 0x000000ff |
| # define R300_ALPHA_TEST_FAIL (0 << 8) |
| # define R300_ALPHA_TEST_LESS (1 << 8) |
| # define R300_ALPHA_TEST_LEQUAL (3 << 8) |
| # define R300_ALPHA_TEST_EQUAL (2 << 8) |
| # define R300_ALPHA_TEST_GEQUAL (6 << 8) |
| # define R300_ALPHA_TEST_GREATER (4 << 8) |
| # define R300_ALPHA_TEST_NEQUAL (5 << 8) |
| # define R300_ALPHA_TEST_PASS (7 << 8) |
| # define R300_ALPHA_TEST_OP_MASK (7 << 8) |
| # define R300_ALPHA_TEST_ENABLE (1 << 11) |
| /* gap */ |
| /* Fragment program parameters in 7.16 floating point */ |
| #define R300_PFS_PARAM_0_X 0x4C00 |
| #define R300_PFS_PARAM_0_Y 0x4C04 |
| #define R300_PFS_PARAM_0_Z 0x4C08 |
| #define R300_PFS_PARAM_0_W 0x4C0C |
| /* GUESS: PARAM_31 is last, based on native limits reported by fglrx */ |
| #define R300_PFS_PARAM_31_X 0x4DF0 |
| #define R300_PFS_PARAM_31_Y 0x4DF4 |
| #define R300_PFS_PARAM_31_Z 0x4DF8 |
| #define R300_PFS_PARAM_31_W 0x4DFC |
| /* Notes: |
| * - AFAIK fglrx always sets BLEND_UNKNOWN when blending is used in |
| * the application |
| * - AFAIK fglrx always sets BLEND_NO_SEPARATE when CBLEND and ABLEND |
| * are set to the same |
| * function (both registers are always set up completely in any case) |
| * - Most blend flags are simply copied from R200 and not tested yet |
| */ |
| #define R300_RB3D_CBLEND 0x4E04 |
| #define R300_RB3D_ABLEND 0x4E08 |
| /* the following only appear in CBLEND */ |
| # define R300_BLEND_ENABLE (1 << 0) |
| # define R300_BLEND_UNKNOWN (3 << 1) |
| # define R300_BLEND_NO_SEPARATE (1 << 3) |
| /* the following are shared between CBLEND and ABLEND */ |
| # define R300_FCN_MASK (3 << 12) |
| # define R300_COMB_FCN_ADD_CLAMP (0 << 12) |
| # define R300_COMB_FCN_ADD_NOCLAMP (1 << 12) |
| # define R300_COMB_FCN_SUB_CLAMP (2 << 12) |
| # define R300_COMB_FCN_SUB_NOCLAMP (3 << 12) |
| # define R300_COMB_FCN_MIN (4 << 12) |
| # define R300_COMB_FCN_MAX (5 << 12) |
| # define R300_COMB_FCN_RSUB_CLAMP (6 << 12) |
| # define R300_COMB_FCN_RSUB_NOCLAMP (7 << 12) |
| # define R300_BLEND_GL_ZERO (32) |
| # define R300_BLEND_GL_ONE (33) |
| # define R300_BLEND_GL_SRC_COLOR (34) |
| # define R300_BLEND_GL_ONE_MINUS_SRC_COLOR (35) |
| # define R300_BLEND_GL_DST_COLOR (36) |
| # define R300_BLEND_GL_ONE_MINUS_DST_COLOR (37) |
| # define R300_BLEND_GL_SRC_ALPHA (38) |
| # define R300_BLEND_GL_ONE_MINUS_SRC_ALPHA (39) |
| # define R300_BLEND_GL_DST_ALPHA (40) |
| # define R300_BLEND_GL_ONE_MINUS_DST_ALPHA (41) |
| # define R300_BLEND_GL_SRC_ALPHA_SATURATE (42) |
| # define R300_BLEND_GL_CONST_COLOR (43) |
| # define R300_BLEND_GL_ONE_MINUS_CONST_COLOR (44) |
| # define R300_BLEND_GL_CONST_ALPHA (45) |
| # define R300_BLEND_GL_ONE_MINUS_CONST_ALPHA (46) |
| # define R300_BLEND_MASK (63) |
| # define R300_SRC_BLEND_SHIFT (16) |
| # define R300_DST_BLEND_SHIFT (24) |
| #define R300_RB3D_BLEND_COLOR 0x4E10 |
| #define R300_RB3D_COLORMASK 0x4E0C |
| # define R300_COLORMASK0_B (1<<0) |
| # define R300_COLORMASK0_G (1<<1) |
| # define R300_COLORMASK0_R (1<<2) |
| # define R300_COLORMASK0_A (1<<3) |
| /* gap */ |
| #define R300_RB3D_COLOROFFSET0 0x4E28 |
| # define R300_COLOROFFSET_MASK 0xFFFFFFF0 /* GUESS */ |
| #define R300_RB3D_COLOROFFSET1 0x4E2C /* GUESS */ |
| #define R300_RB3D_COLOROFFSET2 0x4E30 /* GUESS */ |
| #define R300_RB3D_COLOROFFSET3 0x4E34 /* GUESS */ |
| /* gap */ |
| /* Bit 16: Larger tiles |
| * Bit 17: 4x2 tiles |
| * Bit 18: Extremely weird tile like, but some pixels duplicated? |
| */ |
| #define R300_RB3D_COLORPITCH0 0x4E38 |
| # define R300_COLORPITCH_MASK 0x00001FF8 /* GUESS */ |
| # define R300_COLOR_TILE_ENABLE (1 << 16) /* GUESS */ |
| # define R300_COLOR_MICROTILE_ENABLE (1 << 17) /* GUESS */ |
| # define R300_COLOR_ENDIAN_NO_SWAP (0 << 18) /* GUESS */ |
| # define R300_COLOR_ENDIAN_WORD_SWAP (1 << 18) /* GUESS */ |
| # define R300_COLOR_ENDIAN_DWORD_SWAP (2 << 18) /* GUESS */ |
| # define R300_COLOR_FORMAT_RGB565 (2 << 22) |
| # define R300_COLOR_FORMAT_ARGB8888 (3 << 22) |
| #define R300_RB3D_COLORPITCH1 0x4E3C /* GUESS */ |
| #define R300_RB3D_COLORPITCH2 0x4E40 /* GUESS */ |
| #define R300_RB3D_COLORPITCH3 0x4E44 /* GUESS */ |
| #define R300_RB3D_AARESOLVE_CTL 0x4E88 |
| /* gap */ |
| /* Guess by Vladimir. |
| * Set to 0A before 3D operations, set to 02 afterwards. |
| */ |
| /*#define R300_RB3D_DSTCACHE_CTLSTAT 0x4E4C*/ |
| # define R300_RB3D_DSTCACHE_UNKNOWN_02 0x00000002 |
| # define R300_RB3D_DSTCACHE_UNKNOWN_0A 0x0000000A |
| /* gap */ |
| /* There seems to be no "write only" setting, so use Z-test = ALWAYS |
| * for this. |
| * Bit (1<<8) is the "test" bit. so plain write is 6 - vd |
| */ |
| #define R300_ZB_CNTL 0x4F00 |
| # define R300_STENCIL_ENABLE (1 << 0) |
| # define R300_Z_ENABLE (1 << 1) |
| # define R300_Z_WRITE_ENABLE (1 << 2) |
| # define R300_Z_SIGNED_COMPARE (1 << 3) |
| # define R300_STENCIL_FRONT_BACK (1 << 4) |
| #define R300_ZB_ZSTENCILCNTL 0x4f04 |
| /* functions */ |
| # define R300_ZS_NEVER 0 |
| # define R300_ZS_LESS 1 |
| # define R300_ZS_LEQUAL 2 |
| # define R300_ZS_EQUAL 3 |
| # define R300_ZS_GEQUAL 4 |
| # define R300_ZS_GREATER 5 |
| # define R300_ZS_NOTEQUAL 6 |
| # define R300_ZS_ALWAYS 7 |
| # define R300_ZS_MASK 7 |
| /* operations */ |
| # define R300_ZS_KEEP 0 |
| # define R300_ZS_ZERO 1 |
| # define R300_ZS_REPLACE 2 |
| # define R300_ZS_INCR 3 |
| # define R300_ZS_DECR 4 |
| # define R300_ZS_INVERT 5 |
| # define R300_ZS_INCR_WRAP 6 |
| # define R300_ZS_DECR_WRAP 7 |
| # define R300_Z_FUNC_SHIFT 0 |
| /* front and back refer to operations done for front |
| and back faces, i.e. separate stencil function support */ |
| # define R300_S_FRONT_FUNC_SHIFT 3 |
| # define R300_S_FRONT_SFAIL_OP_SHIFT 6 |
| # define R300_S_FRONT_ZPASS_OP_SHIFT 9 |
| # define R300_S_FRONT_ZFAIL_OP_SHIFT 12 |
| # define R300_S_BACK_FUNC_SHIFT 15 |
| # define R300_S_BACK_SFAIL_OP_SHIFT 18 |
| # define R300_S_BACK_ZPASS_OP_SHIFT 21 |
| # define R300_S_BACK_ZFAIL_OP_SHIFT 24 |
| #define R300_ZB_STENCILREFMASK 0x4f08 |
| # define R300_STENCILREF_SHIFT 0 |
| # define R300_STENCILREF_MASK 0x000000ff |
| # define R300_STENCILMASK_SHIFT 8 |
| # define R300_STENCILMASK_MASK 0x0000ff00 |
| # define R300_STENCILWRITEMASK_SHIFT 16 |
| # define R300_STENCILWRITEMASK_MASK 0x00ff0000 |
| /* gap */ |
| #define R300_ZB_FORMAT 0x4f10 |
| # define R300_DEPTHFORMAT_16BIT_INT_Z (0 << 0) |
| # define R300_DEPTHFORMAT_16BIT_13E3 (1 << 0) |
| # define R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL (2 << 0) |
| /* reserved up to (15 << 0) */ |
| # define R300_INVERT_13E3_LEADING_ONES (0 << 4) |
| # define R300_INVERT_13E3_LEADING_ZEROS (1 << 4) |
| #define R300_ZB_ZTOP 0x4F14 |
| # define R300_ZTOP_DISABLE (0 << 0) |
| # define R300_ZTOP_ENABLE (1 << 0) |
| /* gap */ |
| #define R300_ZB_ZCACHE_CTLSTAT 0x4f18 |
| # define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_NO_EFFECT (0 << 0) |
| # define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE (1 << 0) |
| # define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_NO_EFFECT (0 << 1) |
| # define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE (1 << 1) |
| # define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_IDLE (0 << 31) |
| # define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_BUSY (1 << 31) |
| #define R300_ZB_BW_CNTL 0x4f1c |
| # define R300_HIZ_DISABLE (0 << 0) |
| # define R300_HIZ_ENABLE (1 << 0) |
| # define R300_HIZ_MIN (0 << 1) |
| # define R300_HIZ_MAX (1 << 1) |
| # define R300_FAST_FILL_DISABLE (0 << 2) |
| # define R300_FAST_FILL_ENABLE (1 << 2) |
| # define R300_RD_COMP_DISABLE (0 << 3) |
| # define R300_RD_COMP_ENABLE (1 << 3) |
| # define R300_WR_COMP_DISABLE (0 << 4) |
| # define R300_WR_COMP_ENABLE (1 << 4) |
| # define R300_ZB_CB_CLEAR_RMW (0 << 5) |
| # define R300_ZB_CB_CLEAR_CACHE_LINEAR (1 << 5) |
| # define R300_FORCE_COMPRESSED_STENCIL_VALUE_DISABLE (0 << 6) |
| # define R300_FORCE_COMPRESSED_STENCIL_VALUE_ENABLE (1 << 6) |
| # define R500_ZEQUAL_OPTIMIZE_ENABLE (0 << 7) |
| # define R500_ZEQUAL_OPTIMIZE_DISABLE (1 << 7) |
| # define R500_SEQUAL_OPTIMIZE_ENABLE (0 << 8) |
| # define R500_SEQUAL_OPTIMIZE_DISABLE (1 << 8) |
| # define R500_BMASK_ENABLE (0 << 10) |
| # define R500_BMASK_DISABLE (1 << 10) |
| # define R500_HIZ_EQUAL_REJECT_DISABLE (0 << 11) |
| # define R500_HIZ_EQUAL_REJECT_ENABLE (1 << 11) |
| # define R500_HIZ_FP_EXP_BITS_DISABLE (0 << 12) |
| # define R500_HIZ_FP_EXP_BITS_1 (1 << 12) |
| # define R500_HIZ_FP_EXP_BITS_2 (2 << 12) |
| # define R500_HIZ_FP_EXP_BITS_3 (3 << 12) |
| # define R500_HIZ_FP_EXP_BITS_4 (4 << 12) |
| # define R500_HIZ_FP_EXP_BITS_5 (5 << 12) |
| # define R500_HIZ_FP_INVERT_LEADING_ONES (0 << 15) |
| # define R500_HIZ_FP_INVERT_LEADING_ZEROS (1 << 15) |
| # define R500_TILE_OVERWRITE_RECOMPRESSION_ENABLE (0 << 16) |
| # define R500_TILE_OVERWRITE_RECOMPRESSION_DISABLE (1 << 16) |
| # define R500_CONTIGUOUS_6XAA_SAMPLES_ENABLE (0 << 17) |
| # define R500_CONTIGUOUS_6XAA_SAMPLES_DISABLE (1 << 17) |
| # define R500_PEQ_PACKING_DISABLE (0 << 18) |
| # define R500_PEQ_PACKING_ENABLE (1 << 18) |
| # define R500_COVERED_PTR_MASKING_DISABLE (0 << 18) |
| # define R500_COVERED_PTR_MASKING_ENABLE (1 << 18) |
| /* gap */ |
| /* Z Buffer Address Offset. |
| * Bits 31 to 5 are used for aligned Z buffer address offset for macro tiles. |
| */ |
| #define R300_ZB_DEPTHOFFSET 0x4f20 |
| /* Z Buffer Pitch and Endian Control */ |
| #define R300_ZB_DEPTHPITCH 0x4f24 |
| # define R300_DEPTHPITCH_MASK 0x00003FFC |
| # define R300_DEPTHMACROTILE_DISABLE (0 << 16) |
| # define R300_DEPTHMACROTILE_ENABLE (1 << 16) |
| # define R300_DEPTHMICROTILE_LINEAR (0 << 17) |
| # define R300_DEPTHMICROTILE_TILED (1 << 17) |
| # define R300_DEPTHMICROTILE_TILED_SQUARE (2 << 17) |
| # define R300_DEPTHENDIAN_NO_SWAP (0 << 18) |
| # define R300_DEPTHENDIAN_WORD_SWAP (1 << 18) |
| # define R300_DEPTHENDIAN_DWORD_SWAP (2 << 18) |
| # define R300_DEPTHENDIAN_HALF_DWORD_SWAP (3 << 18) |
| /* Z Buffer Clear Value */ |
| #define R300_ZB_DEPTHCLEARVALUE 0x4f28 |
| #define R300_ZB_ZMASK_OFFSET 0x4f30 |
| #define R300_ZB_ZMASK_PITCH 0x4f34 |
| #define R300_ZB_ZMASK_WRINDEX 0x4f38 |
| #define R300_ZB_ZMASK_DWORD 0x4f3c |
| #define R300_ZB_ZMASK_RDINDEX 0x4f40 |
| /* Hierarchical Z Memory Offset */ |
| #define R300_ZB_HIZ_OFFSET 0x4f44 |
| /* Hierarchical Z Write Index */ |
| #define R300_ZB_HIZ_WRINDEX 0x4f48 |
| /* Hierarchical Z Data */ |
| #define R300_ZB_HIZ_DWORD 0x4f4c |
| /* Hierarchical Z Read Index */ |
| #define R300_ZB_HIZ_RDINDEX 0x4f50 |
| /* Hierarchical Z Pitch */ |
| #define R300_ZB_HIZ_PITCH 0x4f54 |
| /* Z Buffer Z Pass Counter Data */ |
| #define R300_ZB_ZPASS_DATA 0x4f58 |
| /* Z Buffer Z Pass Counter Address */ |
| #define R300_ZB_ZPASS_ADDR 0x4f5c |
| /* Depth buffer X and Y coordinate offset */ |
| #define R300_ZB_DEPTHXY_OFFSET 0x4f60 |
| # define R300_DEPTHX_OFFSET_SHIFT 1 |
| # define R300_DEPTHX_OFFSET_MASK 0x000007FE |
| # define R300_DEPTHY_OFFSET_SHIFT 17 |
| # define R300_DEPTHY_OFFSET_MASK 0x07FE0000 |
| /* Sets the fifo sizes */ |
| #define R500_ZB_FIFO_SIZE 0x4fd0 |
| # define R500_OP_FIFO_SIZE_FULL (0 << 0) |
| # define R500_OP_FIFO_SIZE_HALF (1 << 0) |
| # define R500_OP_FIFO_SIZE_QUATER (2 << 0) |
| # define R500_OP_FIFO_SIZE_EIGTHS (4 << 0) |
| /* Stencil Reference Value and Mask for backfacing quads */ |
| /* R300_ZB_STENCILREFMASK handles front face */ |
| #define R500_ZB_STENCILREFMASK_BF 0x4fd4 |
| # define R500_STENCILREF_SHIFT 0 |
| # define R500_STENCILREF_MASK 0x000000ff |
| # define R500_STENCILMASK_SHIFT 8 |
| # define R500_STENCILMASK_MASK 0x0000ff00 |
| # define R500_STENCILWRITEMASK_SHIFT 16 |
| # define R500_STENCILWRITEMASK_MASK 0x00ff0000 |
| /* BEGIN: Vertex program instruction set */ |
| /* Every instruction is four dwords long: |
| * DWORD 0: output and opcode |
| * DWORD 1: first argument |
| * DWORD 2: second argument |
| * DWORD 3: third argument |
| * |
| * Notes: |
| * - ABS r, a is implemented as MAX r, a, -a |
| * - MOV is implemented as ADD to zero |
| * - XPD is implemented as MUL + MAD |
| * - FLR is implemented as FRC + ADD |
| * - apparently, fglrx tries to schedule instructions so that there is at |
| * least one instruction between the write to a temporary and the first |
| * read from said temporary; however, violations of this scheduling are |
| * allowed |
| * - register indices seem to be unrelated with OpenGL aliasing to |
| * conventional state |
| * - only one attribute and one parameter can be loaded at a time; however, |
| * the same attribute/parameter can be used for more than one argument |
| * - the second software argument for POW is the third hardware argument |
| * (no idea why) |
| * - MAD with only temporaries as input seems to use VPI_OUT_SELECT_MAD_2 |
| * |
| * There is some magic surrounding LIT: |
| * The single argument is replicated across all three inputs, but swizzled: |
| * First argument: xyzy |
| * Second argument: xyzx |
| * Third argument: xyzw |
| * Whenever the result is used later in the fragment program, fglrx forces |
| * x and w to be 1.0 in the input selection; I don't know whether this is |
| * strictly necessary |
| */ |
| #define R300_VPI_OUT_OP_DOT (1 << 0) |
| #define R300_VPI_OUT_OP_MUL (2 << 0) |
| #define R300_VPI_OUT_OP_ADD (3 << 0) |
| #define R300_VPI_OUT_OP_MAD (4 << 0) |
| #define R300_VPI_OUT_OP_DST (5 << 0) |
| #define R300_VPI_OUT_OP_FRC (6 << 0) |
| #define R300_VPI_OUT_OP_MAX (7 << 0) |
| #define R300_VPI_OUT_OP_MIN (8 << 0) |
| #define R300_VPI_OUT_OP_SGE (9 << 0) |
| #define R300_VPI_OUT_OP_SLT (10 << 0) |
| /* Used in GL_POINT_DISTANCE_ATTENUATION_ARB, vector(scalar, vector) */ |
| #define R300_VPI_OUT_OP_UNK12 (12 << 0) |
| #define R300_VPI_OUT_OP_ARL (13 << 0) |
| #define R300_VPI_OUT_OP_EXP (65 << 0) |
| #define R300_VPI_OUT_OP_LOG (66 << 0) |
| /* Used in fog computations, scalar(scalar) */ |
| #define R300_VPI_OUT_OP_UNK67 (67 << 0) |
| #define R300_VPI_OUT_OP_LIT (68 << 0) |
| #define R300_VPI_OUT_OP_POW (69 << 0) |
| #define R300_VPI_OUT_OP_RCP (70 << 0) |
| #define R300_VPI_OUT_OP_RSQ (72 << 0) |
| /* Used in GL_POINT_DISTANCE_ATTENUATION_ARB, scalar(scalar) */ |
| #define R300_VPI_OUT_OP_UNK73 (73 << 0) |
| #define R300_VPI_OUT_OP_EX2 (75 << 0) |
| #define R300_VPI_OUT_OP_LG2 (76 << 0) |
| #define R300_VPI_OUT_OP_MAD_2 (128 << 0) |
| /* all temps, vector(scalar, vector, vector) */ |
| #define R300_VPI_OUT_OP_UNK129 (129 << 0) |
| #define R300_VPI_OUT_REG_CLASS_TEMPORARY (0 << 8) |
| #define R300_VPI_OUT_REG_CLASS_ADDR (1 << 8) |
| #define R300_VPI_OUT_REG_CLASS_RESULT (2 << 8) |
| #define R300_VPI_OUT_REG_CLASS_MASK (31 << 8) |
| #define R300_VPI_OUT_REG_INDEX_SHIFT 13 |
| /* GUESS based on fglrx native limits */ |
| #define R300_VPI_OUT_REG_INDEX_MASK (31 << 13) |
| #define R300_VPI_OUT_WRITE_X (1 << 20) |
| #define R300_VPI_OUT_WRITE_Y (1 << 21) |
| #define R300_VPI_OUT_WRITE_Z (1 << 22) |
| #define R300_VPI_OUT_WRITE_W (1 << 23) |
| #define R300_VPI_IN_REG_CLASS_TEMPORARY (0 << 0) |
| #define R300_VPI_IN_REG_CLASS_ATTRIBUTE (1 << 0) |
| #define R300_VPI_IN_REG_CLASS_PARAMETER (2 << 0) |
| #define R300_VPI_IN_REG_CLASS_NONE (9 << 0) |
| #define R300_VPI_IN_REG_CLASS_MASK (31 << 0) |
| #define R300_VPI_IN_REG_INDEX_SHIFT 5 |
| /* GUESS based on fglrx native limits */ |
| #define R300_VPI_IN_REG_INDEX_MASK (255 << 5) |
| /* The R300 can select components from the input register arbitrarily. |
| * Use the following constants, shifted by the component shift you |
| * want to select |
| */ |
| #define R300_VPI_IN_SELECT_X 0 |
| #define R300_VPI_IN_SELECT_Y 1 |
| #define R300_VPI_IN_SELECT_Z 2 |
| #define R300_VPI_IN_SELECT_W 3 |
| #define R300_VPI_IN_SELECT_ZERO 4 |
| #define R300_VPI_IN_SELECT_ONE 5 |
| #define R300_VPI_IN_SELECT_MASK 7 |
| #define R300_VPI_IN_X_SHIFT 13 |
| #define R300_VPI_IN_Y_SHIFT 16 |
| #define R300_VPI_IN_Z_SHIFT 19 |
| #define R300_VPI_IN_W_SHIFT 22 |
| #define R300_VPI_IN_NEG_X (1 << 25) |
| #define R300_VPI_IN_NEG_Y (1 << 26) |
| #define R300_VPI_IN_NEG_Z (1 << 27) |
| #define R300_VPI_IN_NEG_W (1 << 28) |
| /* END: Vertex program instruction set */ |
| /* BEGIN: Packet 3 commands */ |
| /* A primitive emission dword. */ |
| #define R300_PRIM_TYPE_NONE (0 << 0) |
| #define R300_PRIM_TYPE_POINT (1 << 0) |
| #define R300_PRIM_TYPE_LINE (2 << 0) |
| #define R300_PRIM_TYPE_LINE_STRIP (3 << 0) |
| #define R300_PRIM_TYPE_TRI_LIST (4 << 0) |
| #define R300_PRIM_TYPE_TRI_FAN (5 << 0) |
| #define R300_PRIM_TYPE_TRI_STRIP (6 << 0) |
| #define R300_PRIM_TYPE_TRI_TYPE2 (7 << 0) |
| #define R300_PRIM_TYPE_RECT_LIST (8 << 0) |
| #define R300_PRIM_TYPE_3VRT_POINT_LIST (9 << 0) |
| #define R300_PRIM_TYPE_3VRT_LINE_LIST (10 << 0) |
| /* GUESS (based on r200) */ |
| #define R300_PRIM_TYPE_POINT_SPRITES (11 << 0) |
| #define R300_PRIM_TYPE_LINE_LOOP (12 << 0) |
| #define R300_PRIM_TYPE_QUADS (13 << 0) |
| #define R300_PRIM_TYPE_QUAD_STRIP (14 << 0) |
| #define R300_PRIM_TYPE_POLYGON (15 << 0) |
| #define R300_PRIM_TYPE_MASK 0xF |
| #define R300_PRIM_WALK_IND (1 << 4) |
| #define R300_PRIM_WALK_LIST (2 << 4) |
| #define R300_PRIM_WALK_RING (3 << 4) |
| #define R300_PRIM_WALK_MASK (3 << 4) |
| /* GUESS (based on r200) */ |
| #define R300_PRIM_COLOR_ORDER_BGRA (0 << 6) |
| #define R300_PRIM_COLOR_ORDER_RGBA (1 << 6) |
| #define R300_PRIM_NUM_VERTICES_SHIFT 16 |
| #define R300_PRIM_NUM_VERTICES_MASK 0xffff |
| /* Draw a primitive from vertex data in arrays loaded via 3D_LOAD_VBPNTR. |
| * Two parameter dwords: |
| * 0. The first parameter appears to be always 0 |
| * 1. The second parameter is a standard primitive emission dword. |
| */ |
| #define R300_PACKET3_3D_DRAW_VBUF 0x00002800 |
| /* Specify the full set of vertex arrays as (address, stride). |
| * The first parameter is the number of vertex arrays specified. |
| * The rest of the command is a variable length list of blocks, where |
| * each block is three dwords long and specifies two arrays. |
| * The first dword of a block is split into two words, the lower significant |
| * word refers to the first array, the more significant word to the second |
| * array in the block. |
| * The low byte of each word contains the size of an array entry in dwords, |
| * the high byte contains the stride of the array. |
| * The second dword of a block contains the pointer to the first array, |
| * the third dword of a block contains the pointer to the second array. |
| * Note that if the total number of arrays is odd, the third dword of |
| * the last block is omitted. |
| */ |
| #define R300_PACKET3_3D_LOAD_VBPNTR 0x00002F00 |
| #define R300_PACKET3_INDX_BUFFER 0x00003300 |
| # define R300_EB_UNK1_SHIFT 24 |
| # define R300_EB_UNK1 (0x80<<24) |
| # define R300_EB_UNK2 0x0810 |
| #define R300_PACKET3_3D_DRAW_VBUF_2 0x00003400 |
| #define R300_PACKET3_3D_DRAW_INDX_2 0x00003600 |
| /* END: Packet 3 commands */ |
| /* Color formats for 2d packets |
| */ |
| #define R300_CP_COLOR_FORMAT_CI8 2 |
| #define R300_CP_COLOR_FORMAT_ARGB1555 3 |
| #define R300_CP_COLOR_FORMAT_RGB565 4 |
| #define R300_CP_COLOR_FORMAT_ARGB8888 6 |
| #define R300_CP_COLOR_FORMAT_RGB332 7 |
| #define R300_CP_COLOR_FORMAT_RGB8 9 |
| #define R300_CP_COLOR_FORMAT_ARGB4444 15 |
| /* |
| * CP type-3 packets |
| */ |
| #define R300_CP_CMD_BITBLT_MULTI 0xC0009B00 |
| #define R500_VAP_INDEX_OFFSET 0x208c |
| #define R500_GA_US_VECTOR_INDEX 0x4250 |
| #define R500_GA_US_VECTOR_DATA 0x4254 |
| #define R500_RS_IP_0 0x4074 |
| #define R500_RS_INST_0 0x4320 |
| #define R500_US_CONFIG 0x4600 |
| #define R500_US_FC_CTRL 0x4624 |
| #define R500_US_CODE_ADDR 0x4630 |
| #define R500_RB3D_COLOR_CLEAR_VALUE_AR 0x46c0 |
| #define R500_RB3D_CONSTANT_COLOR_AR 0x4ef8 |
| #define R300_SU_REG_DEST 0x42c8 |
| #define RV530_FG_ZBREG_DEST 0x4be8 |
| #define R300_ZB_ZPASS_DATA 0x4f58 |
| #define R300_ZB_ZPASS_ADDR 0x4f5c |
| #endif /* _R300_REG_H */ |
| /drivers/video/drm/radeon/r500_reg.h |
|---|
| 0,0 → 1,749 |
| /* |
| * Copyright 2008 Advanced Micro Devices, Inc. |
| * Copyright 2008 Red Hat Inc. |
| * Copyright 2009 Jerome Glisse. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice shall be included in |
| * all copies or substantial portions of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| * OTHER DEALINGS IN THE SOFTWARE. |
| * |
| * Authors: Dave Airlie |
| * Alex Deucher |
| * Jerome Glisse |
| */ |
| #ifndef __R500_REG_H__ |
| #define __R500_REG_H__ |
| /* pipe config regs */ |
| #define R300_GA_POLY_MODE 0x4288 |
| # define R300_FRONT_PTYPE_POINT (0 << 4) |
| # define R300_FRONT_PTYPE_LINE (1 << 4) |
| # define R300_FRONT_PTYPE_TRIANGE (2 << 4) |
| # define R300_BACK_PTYPE_POINT (0 << 7) |
| # define R300_BACK_PTYPE_LINE (1 << 7) |
| # define R300_BACK_PTYPE_TRIANGE (2 << 7) |
| #define R300_GA_ROUND_MODE 0x428c |
| # define R300_GEOMETRY_ROUND_TRUNC (0 << 0) |
| # define R300_GEOMETRY_ROUND_NEAREST (1 << 0) |
| # define R300_COLOR_ROUND_TRUNC (0 << 2) |
| # define R300_COLOR_ROUND_NEAREST (1 << 2) |
| #define R300_GB_MSPOS0 0x4010 |
| # define R300_MS_X0_SHIFT 0 |
| # define R300_MS_Y0_SHIFT 4 |
| # define R300_MS_X1_SHIFT 8 |
| # define R300_MS_Y1_SHIFT 12 |
| # define R300_MS_X2_SHIFT 16 |
| # define R300_MS_Y2_SHIFT 20 |
| # define R300_MSBD0_Y_SHIFT 24 |
| # define R300_MSBD0_X_SHIFT 28 |
| #define R300_GB_MSPOS1 0x4014 |
| # define R300_MS_X3_SHIFT 0 |
| # define R300_MS_Y3_SHIFT 4 |
| # define R300_MS_X4_SHIFT 8 |
| # define R300_MS_Y4_SHIFT 12 |
| # define R300_MS_X5_SHIFT 16 |
| # define R300_MS_Y5_SHIFT 20 |
| # define R300_MSBD1_SHIFT 24 |
| #define R300_GA_ENHANCE 0x4274 |
| # define R300_GA_DEADLOCK_CNTL (1 << 0) |
| # define R300_GA_FASTSYNC_CNTL (1 << 1) |
| #define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c |
| # define R300_RB3D_DC_FLUSH (2 << 0) |
| # define R300_RB3D_DC_FREE (2 << 2) |
| # define R300_RB3D_DC_FINISH (1 << 4) |
| #define R300_RB3D_ZCACHE_CTLSTAT 0x4f18 |
| # define R300_ZC_FLUSH (1 << 0) |
| # define R300_ZC_FREE (1 << 1) |
| # define R300_ZC_FLUSH_ALL 0x3 |
| #define R400_GB_PIPE_SELECT 0x402c |
| #define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */ |
| #define R500_SU_REG_DEST 0x42c8 |
| #define R300_GB_TILE_CONFIG 0x4018 |
| # define R300_ENABLE_TILING (1 << 0) |
| # define R300_PIPE_COUNT_RV350 (0 << 1) |
| # define R300_PIPE_COUNT_R300 (3 << 1) |
| # define R300_PIPE_COUNT_R420_3P (6 << 1) |
| # define R300_PIPE_COUNT_R420 (7 << 1) |
| # define R300_TILE_SIZE_8 (0 << 4) |
| # define R300_TILE_SIZE_16 (1 << 4) |
| # define R300_TILE_SIZE_32 (2 << 4) |
| # define R300_SUBPIXEL_1_12 (0 << 16) |
| # define R300_SUBPIXEL_1_16 (1 << 16) |
| #define R300_DST_PIPE_CONFIG 0x170c |
| # define R300_PIPE_AUTO_CONFIG (1 << 31) |
| #define R300_RB2D_DSTCACHE_MODE 0x3428 |
| # define R300_DC_AUTOFLUSH_ENABLE (1 << 8) |
| # define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17) |
| #define RADEON_CP_STAT 0x7C0 |
| #define RADEON_RBBM_CMDFIFO_ADDR 0xE70 |
| #define RADEON_RBBM_CMDFIFO_DATA 0xE74 |
| #define RADEON_ISYNC_CNTL 0x1724 |
| # define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0) |
| # define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1) |
| # define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2) |
| # define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3) |
| # define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4) |
| # define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5) |
| #define RS480_NB_MC_INDEX 0x168 |
| # define RS480_NB_MC_IND_WR_EN (1 << 8) |
| #define RS480_NB_MC_DATA 0x16c |
| /* |
| * RS690 |
| */ |
| #define RS690_MCCFG_FB_LOCATION 0x100 |
| #define RS690_MC_FB_START_MASK 0x0000FFFF |
| #define RS690_MC_FB_START_SHIFT 0 |
| #define RS690_MC_FB_TOP_MASK 0xFFFF0000 |
| #define RS690_MC_FB_TOP_SHIFT 16 |
| #define RS690_MCCFG_AGP_LOCATION 0x101 |
| #define RS690_MC_AGP_START_MASK 0x0000FFFF |
| #define RS690_MC_AGP_START_SHIFT 0 |
| #define RS690_MC_AGP_TOP_MASK 0xFFFF0000 |
| #define RS690_MC_AGP_TOP_SHIFT 16 |
| #define RS690_MCCFG_AGP_BASE 0x102 |
| #define RS690_MCCFG_AGP_BASE_2 0x103 |
| #define RS690_MC_INIT_MISC_LAT_TIMER 0x104 |
| #define RS690_HDP_FB_LOCATION 0x0134 |
| #define RS690_MC_INDEX 0x78 |
| # define RS690_MC_INDEX_MASK 0x1ff |
| # define RS690_MC_INDEX_WR_EN (1 << 9) |
| # define RS690_MC_INDEX_WR_ACK 0x7f |
| #define RS690_MC_DATA 0x7c |
| #define RS690_MC_STATUS 0x90 |
| #define RS690_MC_STATUS_IDLE (1 << 0) |
| #define RS480_AGP_BASE_2 0x0164 |
| #define RS480_MC_MISC_CNTL 0x18 |
| # define RS480_DISABLE_GTW (1 << 1) |
| # define RS480_GART_INDEX_REG_EN (1 << 12) |
| # define RS690_BLOCK_GFX_D3_EN (1 << 14) |
| #define RS480_GART_FEATURE_ID 0x2b |
| # define RS480_HANG_EN (1 << 11) |
| # define RS480_TLB_ENABLE (1 << 18) |
| # define RS480_P2P_ENABLE (1 << 19) |
| # define RS480_GTW_LAC_EN (1 << 25) |
| # define RS480_2LEVEL_GART (0 << 30) |
| # define RS480_1LEVEL_GART (1 << 30) |
| # define RS480_PDC_EN (1 << 31) |
| #define RS480_GART_BASE 0x2c |
| #define RS480_GART_CACHE_CNTRL 0x2e |
| # define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */ |
| #define RS480_AGP_ADDRESS_SPACE_SIZE 0x38 |
| # define RS480_GART_EN (1 << 0) |
| # define RS480_VA_SIZE_32MB (0 << 1) |
| # define RS480_VA_SIZE_64MB (1 << 1) |
| # define RS480_VA_SIZE_128MB (2 << 1) |
| # define RS480_VA_SIZE_256MB (3 << 1) |
| # define RS480_VA_SIZE_512MB (4 << 1) |
| # define RS480_VA_SIZE_1GB (5 << 1) |
| # define RS480_VA_SIZE_2GB (6 << 1) |
| #define RS480_AGP_MODE_CNTL 0x39 |
| # define RS480_POST_GART_Q_SIZE (1 << 18) |
| # define RS480_NONGART_SNOOP (1 << 19) |
| # define RS480_AGP_RD_BUF_SIZE (1 << 20) |
| # define RS480_REQ_TYPE_SNOOP_SHIFT 22 |
| # define RS480_REQ_TYPE_SNOOP_MASK 0x3 |
| # define RS480_REQ_TYPE_SNOOP_DIS (1 << 24) |
| #define RS690_AIC_CTRL_SCRATCH 0x3A |
| # define RS690_DIS_OUT_OF_PCI_GART_ACCESS (1 << 1) |
| /* |
| * RS600 |
| */ |
| #define RS600_MC_STATUS 0x0 |
| #define RS600_MC_STATUS_IDLE (1 << 0) |
| #define RS600_MC_INDEX 0x70 |
| # define RS600_MC_ADDR_MASK 0xffff |
| # define RS600_MC_IND_SEQ_RBS_0 (1 << 16) |
| # define RS600_MC_IND_SEQ_RBS_1 (1 << 17) |
| # define RS600_MC_IND_SEQ_RBS_2 (1 << 18) |
| # define RS600_MC_IND_SEQ_RBS_3 (1 << 19) |
| # define RS600_MC_IND_AIC_RBS (1 << 20) |
| # define RS600_MC_IND_CITF_ARB0 (1 << 21) |
| # define RS600_MC_IND_CITF_ARB1 (1 << 22) |
| # define RS600_MC_IND_WR_EN (1 << 23) |
| #define RS600_MC_DATA 0x74 |
| #define RS600_MC_STATUS 0x0 |
| # define RS600_MC_IDLE (1 << 1) |
| #define RS600_MC_FB_LOCATION 0x4 |
| #define RS600_MC_FB_START_MASK 0x0000FFFF |
| #define RS600_MC_FB_START_SHIFT 0 |
| #define RS600_MC_FB_TOP_MASK 0xFFFF0000 |
| #define RS600_MC_FB_TOP_SHIFT 16 |
| #define RS600_MC_AGP_LOCATION 0x5 |
| #define RS600_MC_AGP_START_MASK 0x0000FFFF |
| #define RS600_MC_AGP_START_SHIFT 0 |
| #define RS600_MC_AGP_TOP_MASK 0xFFFF0000 |
| #define RS600_MC_AGP_TOP_SHIFT 16 |
| #define RS600_MC_AGP_BASE 0x6 |
| #define RS600_MC_AGP_BASE_2 0x7 |
| #define RS600_MC_CNTL1 0x9 |
| # define RS600_ENABLE_PAGE_TABLES (1 << 26) |
| #define RS600_MC_PT0_CNTL 0x100 |
| # define RS600_ENABLE_PT (1 << 0) |
| # define RS600_EFFECTIVE_L2_CACHE_SIZE(x) ((x) << 15) |
| # define RS600_EFFECTIVE_L2_QUEUE_SIZE(x) ((x) << 21) |
| # define RS600_INVALIDATE_ALL_L1_TLBS (1 << 28) |
| # define RS600_INVALIDATE_L2_CACHE (1 << 29) |
| #define RS600_MC_PT0_CONTEXT0_CNTL 0x102 |
| # define RS600_ENABLE_PAGE_TABLE (1 << 0) |
| # define RS600_PAGE_TABLE_TYPE_FLAT (0 << 1) |
| #define RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR 0x112 |
| #define RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR 0x114 |
| #define RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR 0x11c |
| #define RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR 0x12c |
| #define RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR 0x13c |
| #define RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR 0x14c |
| #define RS600_MC_PT0_CLIENT0_CNTL 0x16c |
| # define RS600_ENABLE_TRANSLATION_MODE_OVERRIDE (1 << 0) |
| # define RS600_TRANSLATION_MODE_OVERRIDE (1 << 1) |
| # define RS600_SYSTEM_ACCESS_MODE_MASK (3 << 8) |
| # define RS600_SYSTEM_ACCESS_MODE_PA_ONLY (0 << 8) |
| # define RS600_SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 8) |
| # define RS600_SYSTEM_ACCESS_MODE_IN_SYS (2 << 8) |
| # define RS600_SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 8) |
| # define RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH (0 << 10) |
| # define RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 10) |
| # define RS600_EFFECTIVE_L1_CACHE_SIZE(x) ((x) << 11) |
| # define RS600_ENABLE_FRAGMENT_PROCESSING (1 << 14) |
| # define RS600_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 15) |
| # define RS600_INVALIDATE_L1_TLB (1 << 20) |
| /* rs600/rs690/rs740 */ |
| # define RS600_BUS_MASTER_DIS (1 << 14) |
| # define RS600_MSI_REARM (1 << 20) |
| /* see RS400_MSI_REARM in AIC_CNTL for rs480 */ |
| #define RV515_MC_FB_LOCATION 0x01 |
| #define RV515_MC_FB_START_MASK 0x0000FFFF |
| #define RV515_MC_FB_START_SHIFT 0 |
| #define RV515_MC_FB_TOP_MASK 0xFFFF0000 |
| #define RV515_MC_FB_TOP_SHIFT 16 |
| #define RV515_MC_AGP_LOCATION 0x02 |
| #define RV515_MC_AGP_START_MASK 0x0000FFFF |
| #define RV515_MC_AGP_START_SHIFT 0 |
| #define RV515_MC_AGP_TOP_MASK 0xFFFF0000 |
| #define RV515_MC_AGP_TOP_SHIFT 16 |
| #define RV515_MC_AGP_BASE 0x03 |
| #define RV515_MC_AGP_BASE_2 0x04 |
| #define R520_MC_FB_LOCATION 0x04 |
| #define R520_MC_FB_START_MASK 0x0000FFFF |
| #define R520_MC_FB_START_SHIFT 0 |
| #define R520_MC_FB_TOP_MASK 0xFFFF0000 |
| #define R520_MC_FB_TOP_SHIFT 16 |
| #define R520_MC_AGP_LOCATION 0x05 |
| #define R520_MC_AGP_START_MASK 0x0000FFFF |
| #define R520_MC_AGP_START_SHIFT 0 |
| #define R520_MC_AGP_TOP_MASK 0xFFFF0000 |
| #define R520_MC_AGP_TOP_SHIFT 16 |
| #define R520_MC_AGP_BASE 0x06 |
| #define R520_MC_AGP_BASE_2 0x07 |
| #define AVIVO_MC_INDEX 0x0070 |
| #define R520_MC_STATUS 0x00 |
| #define R520_MC_STATUS_IDLE (1<<1) |
| #define RV515_MC_STATUS 0x08 |
| #define RV515_MC_STATUS_IDLE (1<<4) |
| #define RV515_MC_INIT_MISC_LAT_TIMER 0x09 |
| #define AVIVO_MC_DATA 0x0074 |
| #define R520_MC_IND_INDEX 0x70 |
| #define R520_MC_IND_WR_EN (1 << 24) |
| #define R520_MC_IND_DATA 0x74 |
| #define RV515_MC_CNTL 0x5 |
| # define RV515_MEM_NUM_CHANNELS_MASK 0x3 |
| #define R520_MC_CNTL0 0x8 |
| # define R520_MEM_NUM_CHANNELS_MASK (0x3 << 24) |
| # define R520_MEM_NUM_CHANNELS_SHIFT 24 |
| # define R520_MC_CHANNEL_SIZE (1 << 23) |
| #define AVIVO_CP_DYN_CNTL 0x000f /* PLL */ |
| # define AVIVO_CP_FORCEON (1 << 0) |
| #define AVIVO_E2_DYN_CNTL 0x0011 /* PLL */ |
| # define AVIVO_E2_FORCEON (1 << 0) |
| #define AVIVO_IDCT_DYN_CNTL 0x0013 /* PLL */ |
| # define AVIVO_IDCT_FORCEON (1 << 0) |
| #define AVIVO_HDP_FB_LOCATION 0x134 |
| #define AVIVO_VGA_RENDER_CONTROL 0x0300 |
| # define AVIVO_VGA_VSTATUS_CNTL_MASK (3 << 16) |
| #define AVIVO_D1VGA_CONTROL 0x0330 |
| # define AVIVO_DVGA_CONTROL_MODE_ENABLE (1<<0) |
| # define AVIVO_DVGA_CONTROL_TIMING_SELECT (1<<8) |
| # define AVIVO_DVGA_CONTROL_SYNC_POLARITY_SELECT (1<<9) |
| # define AVIVO_DVGA_CONTROL_OVERSCAN_TIMING_SELECT (1<<10) |
| # define AVIVO_DVGA_CONTROL_OVERSCAN_COLOR_EN (1<<16) |
| # define AVIVO_DVGA_CONTROL_ROTATE (1<<24) |
| #define AVIVO_D2VGA_CONTROL 0x0338 |
| #define AVIVO_EXT1_PPLL_REF_DIV_SRC 0x400 |
| #define AVIVO_EXT1_PPLL_REF_DIV 0x404 |
| #define AVIVO_EXT1_PPLL_UPDATE_LOCK 0x408 |
| #define AVIVO_EXT1_PPLL_UPDATE_CNTL 0x40c |
| #define AVIVO_EXT2_PPLL_REF_DIV_SRC 0x410 |
| #define AVIVO_EXT2_PPLL_REF_DIV 0x414 |
| #define AVIVO_EXT2_PPLL_UPDATE_LOCK 0x418 |
| #define AVIVO_EXT2_PPLL_UPDATE_CNTL 0x41c |
| #define AVIVO_EXT1_PPLL_FB_DIV 0x430 |
| #define AVIVO_EXT2_PPLL_FB_DIV 0x434 |
| #define AVIVO_EXT1_PPLL_POST_DIV_SRC 0x438 |
| #define AVIVO_EXT1_PPLL_POST_DIV 0x43c |
| #define AVIVO_EXT2_PPLL_POST_DIV_SRC 0x440 |
| #define AVIVO_EXT2_PPLL_POST_DIV 0x444 |
| #define AVIVO_EXT1_PPLL_CNTL 0x448 |
| #define AVIVO_EXT2_PPLL_CNTL 0x44c |
| #define AVIVO_P1PLL_CNTL 0x450 |
| #define AVIVO_P2PLL_CNTL 0x454 |
| #define AVIVO_P1PLL_INT_SS_CNTL 0x458 |
| #define AVIVO_P2PLL_INT_SS_CNTL 0x45c |
| #define AVIVO_P1PLL_TMDSA_CNTL 0x460 |
| #define AVIVO_P2PLL_LVTMA_CNTL 0x464 |
| #define AVIVO_PCLK_CRTC1_CNTL 0x480 |
| #define AVIVO_PCLK_CRTC2_CNTL 0x484 |
| #define AVIVO_D1CRTC_H_TOTAL 0x6000 |
| #define AVIVO_D1CRTC_H_BLANK_START_END 0x6004 |
| #define AVIVO_D1CRTC_H_SYNC_A 0x6008 |
| #define AVIVO_D1CRTC_H_SYNC_A_CNTL 0x600c |
| #define AVIVO_D1CRTC_H_SYNC_B 0x6010 |
| #define AVIVO_D1CRTC_H_SYNC_B_CNTL 0x6014 |
| #define AVIVO_D1CRTC_V_TOTAL 0x6020 |
| #define AVIVO_D1CRTC_V_BLANK_START_END 0x6024 |
| #define AVIVO_D1CRTC_V_SYNC_A 0x6028 |
| #define AVIVO_D1CRTC_V_SYNC_A_CNTL 0x602c |
| #define AVIVO_D1CRTC_V_SYNC_B 0x6030 |
| #define AVIVO_D1CRTC_V_SYNC_B_CNTL 0x6034 |
| #define AVIVO_D1CRTC_CONTROL 0x6080 |
| # define AVIVO_CRTC_EN (1 << 0) |
| #define AVIVO_D1CRTC_BLANK_CONTROL 0x6084 |
| #define AVIVO_D1CRTC_INTERLACE_CONTROL 0x6088 |
| #define AVIVO_D1CRTC_INTERLACE_STATUS 0x608c |
| #define AVIVO_D1CRTC_STEREO_CONTROL 0x60c4 |
| /* master controls */ |
| #define AVIVO_DC_CRTC_MASTER_EN 0x60f8 |
| #define AVIVO_DC_CRTC_TV_CONTROL 0x60fc |
| #define AVIVO_D1GRPH_ENABLE 0x6100 |
| #define AVIVO_D1GRPH_CONTROL 0x6104 |
| # define AVIVO_D1GRPH_CONTROL_DEPTH_8BPP (0 << 0) |
| # define AVIVO_D1GRPH_CONTROL_DEPTH_16BPP (1 << 0) |
| # define AVIVO_D1GRPH_CONTROL_DEPTH_32BPP (2 << 0) |
| # define AVIVO_D1GRPH_CONTROL_DEPTH_64BPP (3 << 0) |
| # define AVIVO_D1GRPH_CONTROL_8BPP_INDEXED (0 << 8) |
| # define AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555 (0 << 8) |
| # define AVIVO_D1GRPH_CONTROL_16BPP_RGB565 (1 << 8) |
| # define AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444 (2 << 8) |
| # define AVIVO_D1GRPH_CONTROL_16BPP_AI88 (3 << 8) |
| # define AVIVO_D1GRPH_CONTROL_16BPP_MONO16 (4 << 8) |
| # define AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888 (0 << 8) |
| # define AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010 (1 << 8) |
| # define AVIVO_D1GRPH_CONTROL_32BPP_DIGITAL (2 << 8) |
| # define AVIVO_D1GRPH_CONTROL_32BPP_8B_ARGB2101010 (3 << 8) |
| # define AVIVO_D1GRPH_CONTROL_64BPP_ARGB16161616 (0 << 8) |
| # define AVIVO_D1GRPH_SWAP_RB (1 << 16) |
| # define AVIVO_D1GRPH_TILED (1 << 20) |
| # define AVIVO_D1GRPH_MACRO_ADDRESS_MODE (1 << 21) |
| #define AVIVO_D1GRPH_LUT_SEL 0x6108 |
| #define AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110 |
| #define AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118 |
| #define AVIVO_D1GRPH_PITCH 0x6120 |
| #define AVIVO_D1GRPH_SURFACE_OFFSET_X 0x6124 |
| #define AVIVO_D1GRPH_SURFACE_OFFSET_Y 0x6128 |
| #define AVIVO_D1GRPH_X_START 0x612c |
| #define AVIVO_D1GRPH_Y_START 0x6130 |
| #define AVIVO_D1GRPH_X_END 0x6134 |
| #define AVIVO_D1GRPH_Y_END 0x6138 |
| #define AVIVO_D1GRPH_UPDATE 0x6144 |
| # define AVIVO_D1GRPH_UPDATE_LOCK (1 << 16) |
| #define AVIVO_D1GRPH_FLIP_CONTROL 0x6148 |
| #define AVIVO_D1CUR_CONTROL 0x6400 |
| # define AVIVO_D1CURSOR_EN (1 << 0) |
| # define AVIVO_D1CURSOR_MODE_SHIFT 8 |
| # define AVIVO_D1CURSOR_MODE_MASK (3 << 8) |
| # define AVIVO_D1CURSOR_MODE_24BPP 2 |
| #define AVIVO_D1CUR_SURFACE_ADDRESS 0x6408 |
| #define AVIVO_D1CUR_SIZE 0x6410 |
| #define AVIVO_D1CUR_POSITION 0x6414 |
| #define AVIVO_D1CUR_HOT_SPOT 0x6418 |
| #define AVIVO_D1CUR_UPDATE 0x6424 |
| # define AVIVO_D1CURSOR_UPDATE_LOCK (1 << 16) |
| #define AVIVO_DC_LUT_RW_SELECT 0x6480 |
| #define AVIVO_DC_LUT_RW_MODE 0x6484 |
| #define AVIVO_DC_LUT_RW_INDEX 0x6488 |
| #define AVIVO_DC_LUT_SEQ_COLOR 0x648c |
| #define AVIVO_DC_LUT_PWL_DATA 0x6490 |
| #define AVIVO_DC_LUT_30_COLOR 0x6494 |
| #define AVIVO_DC_LUT_READ_PIPE_SELECT 0x6498 |
| #define AVIVO_DC_LUT_WRITE_EN_MASK 0x649c |
| #define AVIVO_DC_LUT_AUTOFILL 0x64a0 |
| #define AVIVO_DC_LUTA_CONTROL 0x64c0 |
| #define AVIVO_DC_LUTA_BLACK_OFFSET_BLUE 0x64c4 |
| #define AVIVO_DC_LUTA_BLACK_OFFSET_GREEN 0x64c8 |
| #define AVIVO_DC_LUTA_BLACK_OFFSET_RED 0x64cc |
| #define AVIVO_DC_LUTA_WHITE_OFFSET_BLUE 0x64d0 |
| #define AVIVO_DC_LUTA_WHITE_OFFSET_GREEN 0x64d4 |
| #define AVIVO_DC_LUTA_WHITE_OFFSET_RED 0x64d8 |
| #define AVIVO_DC_LB_MEMORY_SPLIT 0x6520 |
| # define AVIVO_DC_LB_MEMORY_SPLIT_MASK 0x3 |
| # define AVIVO_DC_LB_MEMORY_SPLIT_SHIFT 0 |
| # define AVIVO_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF 0 |
| # define AVIVO_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q 1 |
| # define AVIVO_DC_LB_MEMORY_SPLIT_D1_ONLY 2 |
| # define AVIVO_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q 3 |
| # define AVIVO_DC_LB_MEMORY_SPLIT_SHIFT_MODE (1 << 2) |
| # define AVIVO_DC_LB_DISP1_END_ADR_SHIFT 4 |
| # define AVIVO_DC_LB_DISP1_END_ADR_MASK 0x7ff |
| #define R500_DxMODE_INT_MASK 0x6540 |
| #define R500_D1MODE_INT_MASK (1<<0) |
| #define R500_D2MODE_INT_MASK (1<<8) |
| #define AVIVO_D1MODE_DATA_FORMAT 0x6528 |
| # define AVIVO_D1MODE_INTERLEAVE_EN (1 << 0) |
| #define AVIVO_D1MODE_DESKTOP_HEIGHT 0x652C |
| #define AVIVO_D1MODE_VIEWPORT_START 0x6580 |
| #define AVIVO_D1MODE_VIEWPORT_SIZE 0x6584 |
| #define AVIVO_D1MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6588 |
| #define AVIVO_D1MODE_EXT_OVERSCAN_TOP_BOTTOM 0x658c |
| #define AVIVO_D1SCL_SCALER_ENABLE 0x6590 |
| #define AVIVO_D1SCL_SCALER_TAP_CONTROL 0x6594 |
| #define AVIVO_D1SCL_UPDATE 0x65cc |
| # define AVIVO_D1SCL_UPDATE_LOCK (1 << 16) |
| /* second crtc */ |
| #define AVIVO_D2CRTC_H_TOTAL 0x6800 |
| #define AVIVO_D2CRTC_H_BLANK_START_END 0x6804 |
| #define AVIVO_D2CRTC_H_SYNC_A 0x6808 |
| #define AVIVO_D2CRTC_H_SYNC_A_CNTL 0x680c |
| #define AVIVO_D2CRTC_H_SYNC_B 0x6810 |
| #define AVIVO_D2CRTC_H_SYNC_B_CNTL 0x6814 |
| #define AVIVO_D2CRTC_V_TOTAL 0x6820 |
| #define AVIVO_D2CRTC_V_BLANK_START_END 0x6824 |
| #define AVIVO_D2CRTC_V_SYNC_A 0x6828 |
| #define AVIVO_D2CRTC_V_SYNC_A_CNTL 0x682c |
| #define AVIVO_D2CRTC_V_SYNC_B 0x6830 |
| #define AVIVO_D2CRTC_V_SYNC_B_CNTL 0x6834 |
| #define AVIVO_D2CRTC_CONTROL 0x6880 |
| #define AVIVO_D2CRTC_BLANK_CONTROL 0x6884 |
| #define AVIVO_D2CRTC_INTERLACE_CONTROL 0x6888 |
| #define AVIVO_D2CRTC_INTERLACE_STATUS 0x688c |
| #define AVIVO_D2CRTC_STEREO_CONTROL 0x68c4 |
| #define AVIVO_D2GRPH_ENABLE 0x6900 |
| #define AVIVO_D2GRPH_CONTROL 0x6904 |
| #define AVIVO_D2GRPH_LUT_SEL 0x6908 |
| #define AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS 0x6910 |
| #define AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS 0x6918 |
| #define AVIVO_D2GRPH_PITCH 0x6920 |
| #define AVIVO_D2GRPH_SURFACE_OFFSET_X 0x6924 |
| #define AVIVO_D2GRPH_SURFACE_OFFSET_Y 0x6928 |
| #define AVIVO_D2GRPH_X_START 0x692c |
| #define AVIVO_D2GRPH_Y_START 0x6930 |
| #define AVIVO_D2GRPH_X_END 0x6934 |
| #define AVIVO_D2GRPH_Y_END 0x6938 |
| #define AVIVO_D2GRPH_UPDATE 0x6944 |
| #define AVIVO_D2GRPH_FLIP_CONTROL 0x6948 |
| #define AVIVO_D2CUR_CONTROL 0x6c00 |
| #define AVIVO_D2CUR_SURFACE_ADDRESS 0x6c08 |
| #define AVIVO_D2CUR_SIZE 0x6c10 |
| #define AVIVO_D2CUR_POSITION 0x6c14 |
| #define AVIVO_D2MODE_VIEWPORT_START 0x6d80 |
| #define AVIVO_D2MODE_VIEWPORT_SIZE 0x6d84 |
| #define AVIVO_D2MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6d88 |
| #define AVIVO_D2MODE_EXT_OVERSCAN_TOP_BOTTOM 0x6d8c |
| #define AVIVO_D2SCL_SCALER_ENABLE 0x6d90 |
| #define AVIVO_D2SCL_SCALER_TAP_CONTROL 0x6d94 |
| #define AVIVO_DDIA_BIT_DEPTH_CONTROL 0x7214 |
| #define AVIVO_DACA_ENABLE 0x7800 |
| # define AVIVO_DAC_ENABLE (1 << 0) |
| #define AVIVO_DACA_SOURCE_SELECT 0x7804 |
| # define AVIVO_DAC_SOURCE_CRTC1 (0 << 0) |
| # define AVIVO_DAC_SOURCE_CRTC2 (1 << 0) |
| # define AVIVO_DAC_SOURCE_TV (2 << 0) |
| #define AVIVO_DACA_FORCE_OUTPUT_CNTL 0x783c |
| # define AVIVO_DACA_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0) |
| # define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8) |
| # define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0) |
| # define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1) |
| # define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2) |
| # define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24) |
| #define AVIVO_DACA_POWERDOWN 0x7850 |
| # define AVIVO_DACA_POWERDOWN_POWERDOWN (1 << 0) |
| # define AVIVO_DACA_POWERDOWN_BLUE (1 << 8) |
| # define AVIVO_DACA_POWERDOWN_GREEN (1 << 16) |
| # define AVIVO_DACA_POWERDOWN_RED (1 << 24) |
| #define AVIVO_DACB_ENABLE 0x7a00 |
| #define AVIVO_DACB_SOURCE_SELECT 0x7a04 |
| #define AVIVO_DACB_FORCE_OUTPUT_CNTL 0x7a3c |
| # define AVIVO_DACB_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0) |
| # define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8) |
| # define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0) |
| # define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1) |
| # define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2) |
| # define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24) |
| #define AVIVO_DACB_POWERDOWN 0x7a50 |
| # define AVIVO_DACB_POWERDOWN_POWERDOWN (1 << 0) |
| # define AVIVO_DACB_POWERDOWN_BLUE (1 << 8) |
| # define AVIVO_DACB_POWERDOWN_GREEN (1 << 16) |
| # define AVIVO_DACB_POWERDOWN_RED |
| #define AVIVO_TMDSA_CNTL 0x7880 |
| # define AVIVO_TMDSA_CNTL_ENABLE (1 << 0) |
| # define AVIVO_TMDSA_CNTL_HPD_MASK (1 << 4) |
| # define AVIVO_TMDSA_CNTL_HPD_SELECT (1 << 8) |
| # define AVIVO_TMDSA_CNTL_SYNC_PHASE (1 << 12) |
| # define AVIVO_TMDSA_CNTL_PIXEL_ENCODING (1 << 16) |
| # define AVIVO_TMDSA_CNTL_DUAL_LINK_ENABLE (1 << 24) |
| # define AVIVO_TMDSA_CNTL_SWAP (1 << 28) |
| #define AVIVO_TMDSA_SOURCE_SELECT 0x7884 |
| /* 78a8 appears to be some kind of (reasonably tolerant) clock? |
| * 78d0 definitely hits the transmitter, definitely clock. */ |
| /* MYSTERY1 This appears to control dithering? */ |
| #define AVIVO_TMDSA_BIT_DEPTH_CONTROL 0x7894 |
| # define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0) |
| # define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4) |
| # define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8) |
| # define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12) |
| # define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16) |
| # define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20) |
| # define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24) |
| # define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26) |
| #define AVIVO_TMDSA_DCBALANCER_CONTROL 0x78d0 |
| # define AVIVO_TMDSA_DCBALANCER_CONTROL_EN (1 << 0) |
| # define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_EN (1 << 8) |
| # define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16) |
| # define AVIVO_TMDSA_DCBALANCER_CONTROL_FORCE (1 << 24) |
| #define AVIVO_TMDSA_DATA_SYNCHRONIZATION 0x78d8 |
| # define AVIVO_TMDSA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0) |
| # define AVIVO_TMDSA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8) |
| #define AVIVO_TMDSA_CLOCK_ENABLE 0x7900 |
| #define AVIVO_TMDSA_TRANSMITTER_ENABLE 0x7904 |
| # define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX0_ENABLE (1 << 0) |
| # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1) |
| # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2) |
| # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3) |
| # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4) |
| # define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX1_ENABLE (1 << 8) |
| # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10) |
| # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11) |
| # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12) |
| # define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX_ENABLE_HPD_MASK (1 << 16) |
| # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17) |
| # define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18) |
| #define AVIVO_TMDSA_TRANSMITTER_CONTROL 0x7910 |
| # define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0) |
| # define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1) |
| # define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2) |
| # define AVIVO_TMDSA_TRANSMITTER_CONTROL_IDSCKSEL (1 << 4) |
| # define AVIVO_TMDSA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5) |
| # define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN (1 << 6) |
| # define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK (1 << 8) |
| # define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS (1 << 13) |
| # define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK (1 << 14) |
| # define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS (1 << 15) |
| # define AVIVO_TMDSA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16) |
| # define AVIVO_TMDSA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28) |
| # define AVIVO_TMDSA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29) |
| # define AVIVO_TMDSA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31) |
| #define AVIVO_LVTMA_CNTL 0x7a80 |
| # define AVIVO_LVTMA_CNTL_ENABLE (1 << 0) |
| # define AVIVO_LVTMA_CNTL_HPD_MASK (1 << 4) |
| # define AVIVO_LVTMA_CNTL_HPD_SELECT (1 << 8) |
| # define AVIVO_LVTMA_CNTL_SYNC_PHASE (1 << 12) |
| # define AVIVO_LVTMA_CNTL_PIXEL_ENCODING (1 << 16) |
| # define AVIVO_LVTMA_CNTL_DUAL_LINK_ENABLE (1 << 24) |
| # define AVIVO_LVTMA_CNTL_SWAP (1 << 28) |
| #define AVIVO_LVTMA_SOURCE_SELECT 0x7a84 |
| #define AVIVO_LVTMA_COLOR_FORMAT 0x7a88 |
| #define AVIVO_LVTMA_BIT_DEPTH_CONTROL 0x7a94 |
| # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0) |
| # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4) |
| # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8) |
| # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12) |
| # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16) |
| # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20) |
| # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24) |
| # define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26) |
| #define AVIVO_LVTMA_DCBALANCER_CONTROL 0x7ad0 |
| # define AVIVO_LVTMA_DCBALANCER_CONTROL_EN (1 << 0) |
| # define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_EN (1 << 8) |
| # define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16) |
| # define AVIVO_LVTMA_DCBALANCER_CONTROL_FORCE (1 << 24) |
| #define AVIVO_LVTMA_DATA_SYNCHRONIZATION 0x78d8 |
| # define AVIVO_LVTMA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0) |
| # define AVIVO_LVTMA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8) |
| #define R500_LVTMA_CLOCK_ENABLE 0x7b00 |
| #define R600_LVTMA_CLOCK_ENABLE 0x7b04 |
| #define R500_LVTMA_TRANSMITTER_ENABLE 0x7b04 |
| #define R600_LVTMA_TRANSMITTER_ENABLE 0x7b08 |
| # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1) |
| # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2) |
| # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3) |
| # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4) |
| # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD03EN (1 << 5) |
| # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC1EN (1 << 9) |
| # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10) |
| # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11) |
| # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12) |
| # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17) |
| # define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18) |
| #define R500_LVTMA_TRANSMITTER_CONTROL 0x7b10 |
| #define R600_LVTMA_TRANSMITTER_CONTROL 0x7b14 |
| # define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0) |
| # define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1) |
| # define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2) |
| # define AVIVO_LVTMA_TRANSMITTER_CONTROL_IDSCKSEL (1 << 4) |
| # define AVIVO_LVTMA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5) |
| # define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN (1 << 6) |
| # define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK (1 << 8) |
| # define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS (1 << 13) |
| # define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK (1 << 14) |
| # define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS (1 << 15) |
| # define AVIVO_LVTMA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16) |
| # define AVIVO_LVTMA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28) |
| # define AVIVO_LVTMA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29) |
| # define AVIVO_LVTMA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31) |
| #define R500_LVTMA_PWRSEQ_CNTL 0x7af0 |
| #define R600_LVTMA_PWRSEQ_CNTL 0x7af4 |
| # define AVIVO_LVTMA_PWRSEQ_EN (1 << 0) |
| # define AVIVO_LVTMA_PWRSEQ_PLL_ENABLE_MASK (1 << 2) |
| # define AVIVO_LVTMA_PWRSEQ_PLL_RESET_MASK (1 << 3) |
| # define AVIVO_LVTMA_PWRSEQ_TARGET_STATE (1 << 4) |
| # define AVIVO_LVTMA_SYNCEN (1 << 8) |
| # define AVIVO_LVTMA_SYNCEN_OVRD (1 << 9) |
| # define AVIVO_LVTMA_SYNCEN_POL (1 << 10) |
| # define AVIVO_LVTMA_DIGON (1 << 16) |
| # define AVIVO_LVTMA_DIGON_OVRD (1 << 17) |
| # define AVIVO_LVTMA_DIGON_POL (1 << 18) |
| # define AVIVO_LVTMA_BLON (1 << 24) |
| # define AVIVO_LVTMA_BLON_OVRD (1 << 25) |
| # define AVIVO_LVTMA_BLON_POL (1 << 26) |
| #define R500_LVTMA_PWRSEQ_STATE 0x7af4 |
| #define R600_LVTMA_PWRSEQ_STATE 0x7af8 |
| # define AVIVO_LVTMA_PWRSEQ_STATE_TARGET_STATE_R (1 << 0) |
| # define AVIVO_LVTMA_PWRSEQ_STATE_DIGON (1 << 1) |
| # define AVIVO_LVTMA_PWRSEQ_STATE_SYNCEN (1 << 2) |
| # define AVIVO_LVTMA_PWRSEQ_STATE_BLON (1 << 3) |
| # define AVIVO_LVTMA_PWRSEQ_STATE_DONE (1 << 4) |
| # define AVIVO_LVTMA_PWRSEQ_STATE_STATUS_SHIFT (8) |
| #define AVIVO_LVDS_BACKLIGHT_CNTL 0x7af8 |
| # define AVIVO_LVDS_BACKLIGHT_CNTL_EN (1 << 0) |
| # define AVIVO_LVDS_BACKLIGHT_LEVEL_MASK 0x0000ff00 |
| # define AVIVO_LVDS_BACKLIGHT_LEVEL_SHIFT 8 |
| #define AVIVO_DVOA_BIT_DEPTH_CONTROL 0x7988 |
| #define AVIVO_GPIO_0 0x7e30 |
| #define AVIVO_GPIO_1 0x7e40 |
| #define AVIVO_GPIO_2 0x7e50 |
| #define AVIVO_GPIO_3 0x7e60 |
| #define AVIVO_DC_GPIO_HPD_Y 0x7e9c |
| #define AVIVO_I2C_STATUS 0x7d30 |
| # define AVIVO_I2C_STATUS_DONE (1 << 0) |
| # define AVIVO_I2C_STATUS_NACK (1 << 1) |
| # define AVIVO_I2C_STATUS_HALT (1 << 2) |
| # define AVIVO_I2C_STATUS_GO (1 << 3) |
| # define AVIVO_I2C_STATUS_MASK 0x7 |
| /* If radeon_mm_i2c is to be believed, this is HALT, NACK, and maybe |
| * DONE? */ |
| # define AVIVO_I2C_STATUS_CMD_RESET 0x7 |
| # define AVIVO_I2C_STATUS_CMD_WAIT (1 << 3) |
| #define AVIVO_I2C_STOP 0x7d34 |
| #define AVIVO_I2C_START_CNTL 0x7d38 |
| # define AVIVO_I2C_START (1 << 8) |
| # define AVIVO_I2C_CONNECTOR0 (0 << 16) |
| # define AVIVO_I2C_CONNECTOR1 (1 << 16) |
| #define R520_I2C_START (1<<0) |
| #define R520_I2C_STOP (1<<1) |
| #define R520_I2C_RX (1<<2) |
| #define R520_I2C_EN (1<<8) |
| #define R520_I2C_DDC1 (0<<16) |
| #define R520_I2C_DDC2 (1<<16) |
| #define R520_I2C_DDC3 (2<<16) |
| #define R520_I2C_DDC_MASK (3<<16) |
| #define AVIVO_I2C_CONTROL2 0x7d3c |
| # define AVIVO_I2C_7D3C_SIZE_SHIFT 8 |
| # define AVIVO_I2C_7D3C_SIZE_MASK (0xf << 8) |
| #define AVIVO_I2C_CONTROL3 0x7d40 |
| /* Reading is done 4 bytes at a time: read the bottom 8 bits from |
| * 7d44, four times in a row. |
| * Writing is a little more complex. First write DATA with |
| * 0xnnnnnnzz, then 0xnnnnnnyy, where nnnnnn is some non-deterministic |
| * magic number, zz is, I think, the slave address, and yy is the byte |
| * you want to write. */ |
| #define AVIVO_I2C_DATA 0x7d44 |
| #define R520_I2C_ADDR_COUNT_MASK (0x7) |
| #define R520_I2C_DATA_COUNT_SHIFT (8) |
| #define R520_I2C_DATA_COUNT_MASK (0xF00) |
| #define AVIVO_I2C_CNTL 0x7d50 |
| # define AVIVO_I2C_EN (1 << 0) |
| # define AVIVO_I2C_RESET (1 << 8) |
| #endif |
| /drivers/video/drm/radeon/r520.c |
|---|
| 0,0 → 1,239 |
| /* |
| * Copyright 2008 Advanced Micro Devices, Inc. |
| * Copyright 2008 Red Hat Inc. |
| * Copyright 2009 Jerome Glisse. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice shall be included in |
| * all copies or substantial portions of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| * OTHER DEALINGS IN THE SOFTWARE. |
| * |
| * Authors: Dave Airlie |
| * Alex Deucher |
| * Jerome Glisse |
| */ |
| //#include "drmP.h" |
| #include "radeon_reg.h" |
| #include "radeon.h" |
| /* r520,rv530,rv560,rv570,r580 depends on : */ |
| void r100_hdp_reset(struct radeon_device *rdev); |
| int rv370_pcie_gart_enable(struct radeon_device *rdev); |
| void rv370_pcie_gart_disable(struct radeon_device *rdev); |
| void r420_pipes_init(struct radeon_device *rdev); |
| void rs600_mc_disable_clients(struct radeon_device *rdev); |
| void rs600_disable_vga(struct radeon_device *rdev); |
| int rv515_debugfs_pipes_info_init(struct radeon_device *rdev); |
| int rv515_debugfs_ga_info_init(struct radeon_device *rdev); |
| /* This files gather functions specifics to: |
| * r520,rv530,rv560,rv570,r580 |
| * |
| * Some of these functions might be used by newer ASICs. |
| */ |
| void r520_gpu_init(struct radeon_device *rdev); |
| int r520_mc_wait_for_idle(struct radeon_device *rdev); |
| #if 0 |
| /* |
| * MC |
| */ |
| int r520_mc_init(struct radeon_device *rdev) |
| { |
| uint32_t tmp; |
| int r; |
| if (r100_debugfs_rbbm_init(rdev)) { |
| DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
| } |
| if (rv515_debugfs_pipes_info_init(rdev)) { |
| DRM_ERROR("Failed to register debugfs file for pipes !\n"); |
| } |
| if (rv515_debugfs_ga_info_init(rdev)) { |
| DRM_ERROR("Failed to register debugfs file for pipes !\n"); |
| } |
| r520_gpu_init(rdev); |
| rv370_pcie_gart_disable(rdev); |
| /* Setup GPU memory space */ |
| rdev->mc.vram_location = 0xFFFFFFFFUL; |
| rdev->mc.gtt_location = 0xFFFFFFFFUL; |
| if (rdev->flags & RADEON_IS_AGP) { |
| r = radeon_agp_init(rdev); |
| if (r) { |
| printk(KERN_WARNING "[drm] Disabling AGP\n"); |
| rdev->flags &= ~RADEON_IS_AGP; |
| rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; |
| } else { |
| rdev->mc.gtt_location = rdev->mc.agp_base; |
| } |
| } |
| r = radeon_mc_setup(rdev); |
| if (r) { |
| return r; |
| } |
| /* Program GPU memory space */ |
| rs600_mc_disable_clients(rdev); |
| if (r520_mc_wait_for_idle(rdev)) { |
| printk(KERN_WARNING "Failed to wait MC idle while " |
| "programming pipes. Bad things might happen.\n"); |
| } |
| /* Write VRAM size in case we are limiting it */ |
| WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size); |
| tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1; |
| tmp = REG_SET(R520_MC_FB_TOP, tmp >> 16); |
| tmp |= REG_SET(R520_MC_FB_START, rdev->mc.vram_location >> 16); |
| WREG32_MC(R520_MC_FB_LOCATION, tmp); |
| WREG32(RS690_HDP_FB_LOCATION, rdev->mc.vram_location >> 16); |
| WREG32(0x310, rdev->mc.vram_location); |
| if (rdev->flags & RADEON_IS_AGP) { |
| tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; |
| tmp = REG_SET(R520_MC_AGP_TOP, tmp >> 16); |
| tmp |= REG_SET(R520_MC_AGP_START, rdev->mc.gtt_location >> 16); |
| WREG32_MC(R520_MC_AGP_LOCATION, tmp); |
| WREG32_MC(R520_MC_AGP_BASE, rdev->mc.agp_base); |
| WREG32_MC(R520_MC_AGP_BASE_2, 0); |
| } else { |
| WREG32_MC(R520_MC_AGP_LOCATION, 0x0FFFFFFF); |
| WREG32_MC(R520_MC_AGP_BASE, 0); |
| WREG32_MC(R520_MC_AGP_BASE_2, 0); |
| } |
| return 0; |
| } |
| void r520_mc_fini(struct radeon_device *rdev) |
| { |
| rv370_pcie_gart_disable(rdev); |
| radeon_gart_table_vram_free(rdev); |
| radeon_gart_fini(rdev); |
| } |
| #endif |
| /* |
| * Global GPU functions |
| */ |
| void r520_errata(struct radeon_device *rdev) |
| { |
| rdev->pll_errata = 0; |
| } |
| #if 0 |
| int r520_mc_wait_for_idle(struct radeon_device *rdev) |
| { |
| unsigned i; |
| uint32_t tmp; |
| for (i = 0; i < rdev->usec_timeout; i++) { |
| /* read MC_STATUS */ |
| tmp = RREG32_MC(R520_MC_STATUS); |
| if (tmp & R520_MC_STATUS_IDLE) { |
| return 0; |
| } |
| DRM_UDELAY(1); |
| } |
| return -1; |
| } |
| void r520_gpu_init(struct radeon_device *rdev) |
| { |
| unsigned pipe_select_current, gb_pipe_select, tmp; |
| r100_hdp_reset(rdev); |
| rs600_disable_vga(rdev); |
| /* |
| * DST_PIPE_CONFIG 0x170C |
| * GB_TILE_CONFIG 0x4018 |
| * GB_FIFO_SIZE 0x4024 |
| * GB_PIPE_SELECT 0x402C |
| * GB_PIPE_SELECT2 0x4124 |
| * Z_PIPE_SHIFT 0 |
| * Z_PIPE_MASK 0x000000003 |
| * GB_FIFO_SIZE2 0x4128 |
| * SC_SFIFO_SIZE_SHIFT 0 |
| * SC_SFIFO_SIZE_MASK 0x000000003 |
| * SC_MFIFO_SIZE_SHIFT 2 |
| * SC_MFIFO_SIZE_MASK 0x00000000C |
| * FG_SFIFO_SIZE_SHIFT 4 |
| * FG_SFIFO_SIZE_MASK 0x000000030 |
| * ZB_MFIFO_SIZE_SHIFT 6 |
| * ZB_MFIFO_SIZE_MASK 0x0000000C0 |
| * GA_ENHANCE 0x4274 |
| * SU_REG_DEST 0x42C8 |
| */ |
| /* workaround for RV530 */ |
| if (rdev->family == CHIP_RV530) { |
| WREG32(0x4124, 1); |
| WREG32(0x4128, 0xFF); |
| } |
| r420_pipes_init(rdev); |
| gb_pipe_select = RREG32(0x402C); |
| tmp = RREG32(0x170C); |
| pipe_select_current = (tmp >> 2) & 3; |
| tmp = (1 << pipe_select_current) | |
| (((gb_pipe_select >> 8) & 0xF) << 4); |
| WREG32_PLL(0x000D, tmp); |
| if (r520_mc_wait_for_idle(rdev)) { |
| printk(KERN_WARNING "Failed to wait MC idle while " |
| "programming pipes. Bad things might happen.\n"); |
| } |
| } |
| #endif |
| /* |
| * VRAM info |
| */ |
| static void r520_vram_get_type(struct radeon_device *rdev) |
| { |
| uint32_t tmp; |
| rdev->mc.vram_width = 128; |
| rdev->mc.vram_is_ddr = true; |
| tmp = RREG32_MC(R520_MC_CNTL0); |
| switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) { |
| case 0: |
| rdev->mc.vram_width = 32; |
| break; |
| case 1: |
| rdev->mc.vram_width = 64; |
| break; |
| case 2: |
| rdev->mc.vram_width = 128; |
| break; |
| case 3: |
| rdev->mc.vram_width = 256; |
| break; |
| default: |
| rdev->mc.vram_width = 128; |
| break; |
| } |
| if (tmp & R520_MC_CHANNEL_SIZE) |
| rdev->mc.vram_width *= 2; |
| } |
| void r520_vram_info(struct radeon_device *rdev) |
| { |
| r520_vram_get_type(rdev); |
| rdev->mc.vram_size = RREG32(RADEON_CONFIG_MEMSIZE); |
| rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); |
| rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); |
| } |
| /drivers/video/drm/radeon/r600_reg.h |
|---|
| 0,0 → 1,114 |
| /* |
| * Copyright 2008 Advanced Micro Devices, Inc. |
| * Copyright 2008 Red Hat Inc. |
| * Copyright 2009 Jerome Glisse. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice shall be included in |
| * all copies or substantial portions of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| * OTHER DEALINGS IN THE SOFTWARE. |
| * |
| * Authors: Dave Airlie |
| * Alex Deucher |
| * Jerome Glisse |
| */ |
| #ifndef __R600_REG_H__ |
| #define __R600_REG_H__ |
| #define R600_PCIE_PORT_INDEX 0x0038 |
| #define R600_PCIE_PORT_DATA 0x003c |
| #define R600_MC_VM_FB_LOCATION 0x2180 |
| #define R600_MC_FB_BASE_MASK 0x0000FFFF |
| #define R600_MC_FB_BASE_SHIFT 0 |
| #define R600_MC_FB_TOP_MASK 0xFFFF0000 |
| #define R600_MC_FB_TOP_SHIFT 16 |
| #define R600_MC_VM_AGP_TOP 0x2184 |
| #define R600_MC_AGP_TOP_MASK 0x0003FFFF |
| #define R600_MC_AGP_TOP_SHIFT 0 |
| #define R600_MC_VM_AGP_BOT 0x2188 |
| #define R600_MC_AGP_BOT_MASK 0x0003FFFF |
| #define R600_MC_AGP_BOT_SHIFT 0 |
| #define R600_MC_VM_AGP_BASE 0x218c |
| #define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190 |
| #define R600_LOGICAL_PAGE_NUMBER_MASK 0x000FFFFF |
| #define R600_LOGICAL_PAGE_NUMBER_SHIFT 0 |
| #define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194 |
| #define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198 |
| #define R700_MC_VM_FB_LOCATION 0x2024 |
| #define R700_MC_FB_BASE_MASK 0x0000FFFF |
| #define R700_MC_FB_BASE_SHIFT 0 |
| #define R700_MC_FB_TOP_MASK 0xFFFF0000 |
| #define R700_MC_FB_TOP_SHIFT 16 |
| #define R700_MC_VM_AGP_TOP 0x2028 |
| #define R700_MC_AGP_TOP_MASK 0x0003FFFF |
| #define R700_MC_AGP_TOP_SHIFT 0 |
| #define R700_MC_VM_AGP_BOT 0x202c |
| #define R700_MC_AGP_BOT_MASK 0x0003FFFF |
| #define R700_MC_AGP_BOT_SHIFT 0 |
| #define R700_MC_VM_AGP_BASE 0x2030 |
| #define R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 |
| #define R700_LOGICAL_PAGE_NUMBER_MASK 0x000FFFFF |
| #define R700_LOGICAL_PAGE_NUMBER_SHIFT 0 |
| #define R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 |
| #define R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203c |
| #define R600_RAMCFG 0x2408 |
| # define R600_CHANSIZE (1 << 7) |
| # define R600_CHANSIZE_OVERRIDE (1 << 10) |
| #define R600_GENERAL_PWRMGT 0x618 |
| # define R600_OPEN_DRAIN_PADS (1 << 11) |
| #define R600_LOWER_GPIO_ENABLE 0x710 |
| #define R600_CTXSW_VID_LOWER_GPIO_CNTL 0x718 |
| #define R600_HIGH_VID_LOWER_GPIO_CNTL 0x71c |
| #define R600_MEDIUM_VID_LOWER_GPIO_CNTL 0x720 |
| #define R600_LOW_VID_LOWER_GPIO_CNTL 0x724 |
| #define R600_HDP_NONSURFACE_BASE 0x2c04 |
| #define R600_BUS_CNTL 0x5420 |
| #define R600_CONFIG_CNTL 0x5424 |
| #define R600_CONFIG_MEMSIZE 0x5428 |
| #define R600_CONFIG_F0_BASE 0x542C |
| #define R600_CONFIG_APER_SIZE 0x5430 |
| #define R600_ROM_CNTL 0x1600 |
| # define R600_SCK_OVERWRITE (1 << 1) |
| # define R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT 28 |
| # define R600_SCK_PRESCALE_CRYSTAL_CLK_MASK (0xf << 28) |
| #define R600_CG_SPLL_FUNC_CNTL 0x600 |
| # define R600_SPLL_BYPASS_EN (1 << 3) |
| #define R600_CG_SPLL_STATUS 0x60c |
| # define R600_SPLL_CHG_STATUS (1 << 1) |
| #define R600_BIOS_0_SCRATCH 0x1724 |
| #define R600_BIOS_1_SCRATCH 0x1728 |
| #define R600_BIOS_2_SCRATCH 0x172c |
| #define R600_BIOS_3_SCRATCH 0x1730 |
| #define R600_BIOS_4_SCRATCH 0x1734 |
| #define R600_BIOS_5_SCRATCH 0x1738 |
| #define R600_BIOS_6_SCRATCH 0x173c |
| #define R600_BIOS_7_SCRATCH 0x1740 |
| #endif |
| /drivers/video/drm/radeon/radeon.h |
|---|
| 0,0 → 1,1217 |
| /* |
| * Copyright 2008 Advanced Micro Devices, Inc. |
| * Copyright 2008 Red Hat Inc. |
| * Copyright 2009 Jerome Glisse. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice shall be included in |
| * all copies or substantial portions of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| * OTHER DEALINGS IN THE SOFTWARE. |
| * |
| * Authors: Dave Airlie |
| * Alex Deucher |
| * Jerome Glisse |
| */ |
| #ifndef __RADEON_H__ |
| #define __RADEON_H__ |
| //#include "radeon_object.h" |
| /* TODO: Here are things that needs to be done : |
| * - surface allocator & initializer : (bit like scratch reg) should |
| * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings |
| * related to surface |
| * - WB : write back stuff (do it bit like scratch reg things) |
| * - Vblank : look at Jesse's rework and what we should do |
| * - r600/r700: gart & cp |
| * - cs : clean cs ioctl use bitmap & things like that. |
| * - power management stuff |
| * - Barrier in gart code |
| * - Unmappabled vram ? |
| * - TESTING, TESTING, TESTING |
| */ |
| #include "types.h" |
| #include "pci.h" |
| #include "errno-base.h" |
| #include "radeon_mode.h" |
| #include "radeon_reg.h" |
| #include "r300.h" |
| #include <syscall.h> |
| extern int radeon_dynclks; |
| extern int radeon_gart_size; |
| extern int radeon_r4xx_atom; |
| /* |
| * Copy from radeon_drv.h so we don't have to include both and have conflicting |
| * symbol; |
| */ |
| #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ |
| #define RADEON_IB_POOL_SIZE 16 |
| #define RADEON_DEBUGFS_MAX_NUM_FILES 32 |
| #define RADEONFB_CONN_LIMIT 4 |
| enum radeon_family { |
| CHIP_R100, |
| CHIP_RV100, |
| CHIP_RS100, |
| CHIP_RV200, |
| CHIP_RS200, |
| CHIP_R200, |
| CHIP_RV250, |
| CHIP_RS300, |
| CHIP_RV280, |
| CHIP_R300, |
| CHIP_R350, |
| CHIP_RV350, |
| CHIP_RV380, |
| CHIP_R420, |
| CHIP_R423, |
| CHIP_RV410, |
| CHIP_RS400, |
| CHIP_RS480, |
| CHIP_RS600, |
| CHIP_RS690, |
| CHIP_RS740, |
| CHIP_RV515, |
| CHIP_R520, |
| CHIP_RV530, |
| CHIP_RV560, |
| CHIP_RV570, |
| CHIP_R580, |
| CHIP_R600, |
| CHIP_RV610, |
| CHIP_RV630, |
| CHIP_RV620, |
| CHIP_RV635, |
| CHIP_RV670, |
| CHIP_RS780, |
| CHIP_RV770, |
| CHIP_RV730, |
| CHIP_RV710, |
| CHIP_RV740, |
| CHIP_LAST, |
| }; |
| enum radeon_chip_flags { |
| RADEON_FAMILY_MASK = 0x0000ffffUL, |
| RADEON_FLAGS_MASK = 0xffff0000UL, |
| RADEON_IS_MOBILITY = 0x00010000UL, |
| RADEON_IS_IGP = 0x00020000UL, |
| RADEON_SINGLE_CRTC = 0x00040000UL, |
| RADEON_IS_AGP = 0x00080000UL, |
| RADEON_HAS_HIERZ = 0x00100000UL, |
| RADEON_IS_PCIE = 0x00200000UL, |
| RADEON_NEW_MEMMAP = 0x00400000UL, |
| RADEON_IS_PCI = 0x00800000UL, |
| RADEON_IS_IGPGART = 0x01000000UL, |
| }; |
| /* |
| * Errata workarounds. |
| */ |
| enum radeon_pll_errata { |
| CHIP_ERRATA_R300_CG = 0x00000001, |
| CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, |
| CHIP_ERRATA_PLL_DELAY = 0x00000004 |
| }; |
| struct radeon_device; |
| /* |
| * BIOS. |
| */ |
| bool radeon_get_bios(struct radeon_device *rdev); |
| /* |
| * Clocks |
| */ |
| struct radeon_clock { |
| struct radeon_pll p1pll; |
| struct radeon_pll p2pll; |
| struct radeon_pll spll; |
| struct radeon_pll mpll; |
| /* 10 Khz units */ |
| uint32_t default_mclk; |
| uint32_t default_sclk; |
| }; |
| /* |
| * Fences. |
| */ |
| struct radeon_fence_driver { |
| uint32_t scratch_reg; |
| // atomic_t seq; |
| uint32_t last_seq; |
| unsigned long count_timeout; |
| // wait_queue_head_t queue; |
| // rwlock_t lock; |
| // struct list_head created; |
| // struct list_head emited; |
| // struct list_head signaled; |
| }; |
| struct radeon_fence { |
| struct radeon_device *rdev; |
| // struct kref kref; |
| // struct list_head list; |
| /* protected by radeon_fence.lock */ |
| uint32_t seq; |
| unsigned long timeout; |
| bool emited; |
| bool signaled; |
| }; |
| int radeon_fence_driver_init(struct radeon_device *rdev); |
| void radeon_fence_driver_fini(struct radeon_device *rdev); |
| int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence); |
| int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence); |
| void radeon_fence_process(struct radeon_device *rdev); |
| bool radeon_fence_signaled(struct radeon_fence *fence); |
| int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); |
| int radeon_fence_wait_next(struct radeon_device *rdev); |
| int radeon_fence_wait_last(struct radeon_device *rdev); |
| struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); |
| void radeon_fence_unref(struct radeon_fence **fence); |
| /* |
| * Radeon buffer. |
| */ |
| struct radeon_object; |
| struct radeon_object_list { |
| // struct list_head list; |
| struct radeon_object *robj; |
| uint64_t gpu_offset; |
| unsigned rdomain; |
| unsigned wdomain; |
| }; |
| /* |
| * GART structures, functions & helpers |
| */ |
| struct radeon_mc; |
| struct radeon_gart_table_ram { |
| volatile uint32_t *ptr; |
| }; |
| struct radeon_gart_table_vram { |
| struct radeon_object *robj; |
| volatile uint32_t *ptr; |
| }; |
| union radeon_gart_table { |
| struct radeon_gart_table_ram ram; |
| struct radeon_gart_table_vram vram; |
| }; |
| struct radeon_gart { |
| dma_addr_t table_addr; |
| unsigned num_gpu_pages; |
| unsigned num_cpu_pages; |
| unsigned table_size; |
| union radeon_gart_table table; |
| struct page **pages; |
| dma_addr_t *pages_addr; |
| bool ready; |
| }; |
| int radeon_gart_table_ram_alloc(struct radeon_device *rdev); |
| void radeon_gart_table_ram_free(struct radeon_device *rdev); |
| int radeon_gart_table_vram_alloc(struct radeon_device *rdev); |
| void radeon_gart_table_vram_free(struct radeon_device *rdev); |
| int radeon_gart_init(struct radeon_device *rdev); |
| void radeon_gart_fini(struct radeon_device *rdev); |
| void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, |
| int pages); |
| int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, |
| int pages, struct page **pagelist); |
| /* |
| * GPU MC structures, functions & helpers |
| */ |
| struct radeon_mc { |
| resource_size_t aper_size; |
| resource_size_t aper_base; |
| resource_size_t agp_base; |
| unsigned gtt_location; |
| unsigned gtt_size; |
| unsigned vram_location; |
| unsigned vram_size; |
| unsigned vram_width; |
| int vram_mtrr; |
| bool vram_is_ddr; |
| }; |
| int radeon_mc_setup(struct radeon_device *rdev); |
| /* |
| * GPU scratch registers structures, functions & helpers |
| */ |
| struct radeon_scratch { |
| unsigned num_reg; |
| bool free[32]; |
| uint32_t reg[32]; |
| }; |
| int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); |
| void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); |
| /* |
| * IRQS. |
| */ |
| struct radeon_irq { |
| bool installed; |
| bool sw_int; |
| /* FIXME: use a define max crtc rather than hardcode it */ |
| bool crtc_vblank_int[2]; |
| }; |
| int radeon_irq_kms_init(struct radeon_device *rdev); |
| void radeon_irq_kms_fini(struct radeon_device *rdev); |
| /* |
| * CP & ring. |
| */ |
| struct radeon_ib { |
| // struct list_head list; |
| unsigned long idx; |
| uint64_t gpu_addr; |
| struct radeon_fence *fence; |
| volatile uint32_t *ptr; |
| uint32_t length_dw; |
| }; |
| struct radeon_ib_pool { |
| // struct mutex mutex; |
| struct radeon_object *robj; |
| // struct list_head scheduled_ibs; |
| struct radeon_ib ibs[RADEON_IB_POOL_SIZE]; |
| bool ready; |
| // DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE); |
| }; |
| struct radeon_cp { |
| struct radeon_object *ring_obj; |
| volatile uint32_t *ring; |
| unsigned rptr; |
| unsigned wptr; |
| unsigned wptr_old; |
| unsigned ring_size; |
| unsigned ring_free_dw; |
| int count_dw; |
| uint64_t gpu_addr; |
| uint32_t align_mask; |
| uint32_t ptr_mask; |
| // struct mutex mutex; |
| bool ready; |
| }; |
| int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib); |
| void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib); |
| int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib); |
| int radeon_ib_pool_init(struct radeon_device *rdev); |
| void radeon_ib_pool_fini(struct radeon_device *rdev); |
| int radeon_ib_test(struct radeon_device *rdev); |
| /* Ring access between begin & end cannot sleep */ |
| void radeon_ring_free_size(struct radeon_device *rdev); |
| int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw); |
| void radeon_ring_unlock_commit(struct radeon_device *rdev); |
| void radeon_ring_unlock_undo(struct radeon_device *rdev); |
| int radeon_ring_test(struct radeon_device *rdev); |
| int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size); |
| void radeon_ring_fini(struct radeon_device *rdev); |
| /* |
| * CS. |
| */ |
| struct radeon_cs_reloc { |
| // struct drm_gem_object *gobj; |
| struct radeon_object *robj; |
| // struct radeon_object_list lobj; |
| uint32_t handle; |
| uint32_t flags; |
| }; |
| struct radeon_cs_chunk { |
| uint32_t chunk_id; |
| uint32_t length_dw; |
| uint32_t *kdata; |
| }; |
| struct radeon_cs_parser { |
| struct radeon_device *rdev; |
| // struct drm_file *filp; |
| /* chunks */ |
| unsigned nchunks; |
| struct radeon_cs_chunk *chunks; |
| uint64_t *chunks_array; |
| /* IB */ |
| unsigned idx; |
| /* relocations */ |
| unsigned nrelocs; |
| struct radeon_cs_reloc *relocs; |
| struct radeon_cs_reloc **relocs_ptr; |
| // struct list_head validated; |
| /* indices of various chunks */ |
| int chunk_ib_idx; |
| int chunk_relocs_idx; |
| struct radeon_ib *ib; |
| void *track; |
| }; |
| struct radeon_cs_packet { |
| unsigned idx; |
| unsigned type; |
| unsigned reg; |
| unsigned opcode; |
| int count; |
| unsigned one_reg_wr; |
| }; |
| typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, |
| struct radeon_cs_packet *pkt, |
| unsigned idx, unsigned reg); |
| typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, |
| struct radeon_cs_packet *pkt); |
| /* |
| * AGP |
| */ |
| int radeon_agp_init(struct radeon_device *rdev); |
| void radeon_agp_fini(struct radeon_device *rdev); |
| /* |
| * Writeback |
| */ |
| struct radeon_wb { |
| struct radeon_object *wb_obj; |
| volatile uint32_t *wb; |
| uint64_t gpu_addr; |
| }; |
| /* |
| * ASIC specific functions. |
| */ |
| struct radeon_asic { |
| int (*init)(struct radeon_device *rdev); |
| void (*errata)(struct radeon_device *rdev); |
| void (*vram_info)(struct radeon_device *rdev); |
| int (*gpu_reset)(struct radeon_device *rdev); |
| int (*mc_init)(struct radeon_device *rdev); |
| void (*mc_fini)(struct radeon_device *rdev); |
| int (*wb_init)(struct radeon_device *rdev); |
| void (*wb_fini)(struct radeon_device *rdev); |
| int (*gart_enable)(struct radeon_device *rdev); |
| void (*gart_disable)(struct radeon_device *rdev); |
| void (*gart_tlb_flush)(struct radeon_device *rdev); |
| int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr); |
| int (*cp_init)(struct radeon_device *rdev, unsigned ring_size); |
| void (*cp_fini)(struct radeon_device *rdev); |
| void (*cp_disable)(struct radeon_device *rdev); |
| void (*ring_start)(struct radeon_device *rdev); |
| int (*irq_set)(struct radeon_device *rdev); |
| int (*irq_process)(struct radeon_device *rdev); |
| void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence); |
| int (*cs_parse)(struct radeon_cs_parser *p); |
| int (*copy_blit)(struct radeon_device *rdev, |
| uint64_t src_offset, |
| uint64_t dst_offset, |
| unsigned num_pages, |
| struct radeon_fence *fence); |
| int (*copy_dma)(struct radeon_device *rdev, |
| uint64_t src_offset, |
| uint64_t dst_offset, |
| unsigned num_pages, |
| struct radeon_fence *fence); |
| int (*copy)(struct radeon_device *rdev, |
| uint64_t src_offset, |
| uint64_t dst_offset, |
| unsigned num_pages, |
| struct radeon_fence *fence); |
| void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); |
| void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); |
| void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); |
| void (*set_clock_gating)(struct radeon_device *rdev, int enable); |
| }; |
| union radeon_asic_config { |
| struct r300_asic r300; |
| }; |
| /* |
| /* |
| * Core structure, functions and helpers. |
| */ |
| typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); |
| typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); |
| struct radeon_device { |
| struct drm_device *ddev; |
| struct pci_dev *pdev; |
| /* ASIC */ |
| union radeon_asic_config config; |
| enum radeon_family family; |
| unsigned long flags; |
| int usec_timeout; |
| enum radeon_pll_errata pll_errata; |
| int num_gb_pipes; |
| int disp_priority; |
| /* BIOS */ |
| uint8_t *bios; |
| bool is_atom_bios; |
| uint16_t bios_header_start; |
| // struct radeon_object *stollen_vga_memory; |
| // struct fb_info *fbdev_info; |
| struct radeon_object *fbdev_robj; |
| struct radeon_framebuffer *fbdev_rfb; |
| /* Register mmio */ |
| unsigned long rmmio_base; |
| unsigned long rmmio_size; |
| void *rmmio; |
| radeon_rreg_t mm_rreg; |
| radeon_wreg_t mm_wreg; |
| radeon_rreg_t mc_rreg; |
| radeon_wreg_t mc_wreg; |
| radeon_rreg_t pll_rreg; |
| radeon_wreg_t pll_wreg; |
| radeon_rreg_t pcie_rreg; |
| radeon_wreg_t pcie_wreg; |
| radeon_rreg_t pciep_rreg; |
| radeon_wreg_t pciep_wreg; |
| struct radeon_clock clock; |
| struct radeon_mc mc; |
| struct radeon_gart gart; |
| struct radeon_mode_info mode_info; |
| struct radeon_scratch scratch; |
| // struct radeon_mman mman; |
| struct radeon_fence_driver fence_drv; |
| struct radeon_cp cp; |
| struct radeon_ib_pool ib_pool; |
| // struct radeon_irq irq; |
| struct radeon_asic *asic; |
| // struct radeon_gem gem; |
| // struct mutex cs_mutex; |
| struct radeon_wb wb; |
| bool gpu_lockup; |
| bool shutdown; |
| bool suspend; |
| }; |
| int radeon_device_init(struct radeon_device *rdev, |
| struct drm_device *ddev, |
| struct pci_dev *pdev, |
| uint32_t flags); |
| void radeon_device_fini(struct radeon_device *rdev); |
| int radeon_gpu_wait_for_idle(struct radeon_device *rdev); |
| #define __iomem |
| #define __force |
| static inline uint8_t __raw_readb(const volatile void __iomem *addr) |
| { |
| return *(const volatile uint8_t __force *) addr; |
| } |
| static inline uint16_t __raw_readw(const volatile void __iomem *addr) |
| { |
| return *(const volatile uint16_t __force *) addr; |
| } |
| static inline uint32_t __raw_readl(const volatile void __iomem *addr) |
| { |
| return *(const volatile uint32_t __force *) addr; |
| } |
| #define readb __raw_readb |
| #define readw __raw_readw |
| #define readl __raw_readl |
| static inline void __raw_writeb(uint8_t b, volatile void __iomem *addr) |
| { |
| *(volatile uint8_t __force *) addr = b; |
| } |
| static inline void __raw_writew(uint16_t b, volatile void __iomem *addr) |
| { |
| *(volatile uint16_t __force *) addr = b; |
| } |
| static inline void __raw_writel(uint32_t b, volatile void __iomem *addr) |
| { |
| *(volatile uint32_t __force *) addr = b; |
| } |
| #define writeb __raw_writeb |
| #define writew __raw_writew |
| #define writel __raw_writel |
| //#define writeb(b,addr) *(volatile uint8_t* ) addr = (uint8_t)b |
| //#define writew(b,addr) *(volatile uint16_t*) addr = (uint16_t)b |
| //#define writel(b,addr) *(volatile uint32_t*) addr = (uint32_t)b |
| /* |
| * Registers read & write functions. |
| */ |
| #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg)) |
| #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg)) |
| #define RREG32(reg) rdev->mm_rreg(rdev, (reg)) |
| #define WREG32(reg, v) rdev->mm_wreg(rdev, (reg), (v)) |
| #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
| #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
| #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) |
| #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) |
| #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) |
| #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) |
| #define RREG32_PCIE(reg) rdev->pcie_rreg(rdev, (reg)) |
| #define WREG32_PCIE(reg, v) rdev->pcie_wreg(rdev, (reg), (v)) |
| #define WREG32_P(reg, val, mask) \ |
| do { \ |
| uint32_t tmp_ = RREG32(reg); \ |
| tmp_ &= (mask); \ |
| tmp_ |= ((val) & ~(mask)); \ |
| WREG32(reg, tmp_); \ |
| } while (0) |
| #define WREG32_PLL_P(reg, val, mask) \ |
| do { \ |
| uint32_t tmp_ = RREG32_PLL(reg); \ |
| tmp_ &= (mask); \ |
| tmp_ |= ((val) & ~(mask)); \ |
| WREG32_PLL(reg, tmp_); \ |
| } while (0) |
| #define radeon_PCI_IDS \ |
| {0x1002, 0x3150, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \ |
| {0x1002, 0x3152, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x3154, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x3E50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x3E54, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x4136, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS100|RADEON_IS_IGP}, \ |
| {0x1002, 0x4137, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS200|RADEON_IS_IGP}, \ |
| {0x1002, 0x4144, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \ |
| {0x1002, 0x4145, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \ |
| {0x1002, 0x4146, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \ |
| {0x1002, 0x4147, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \ |
| {0x1002, 0x4148, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \ |
| {0x1002, 0x4149, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \ |
| {0x1002, 0x414A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \ |
| {0x1002, 0x414B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \ |
| {0x1002, 0x4150, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \ |
| {0x1002, 0x4151, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \ |
| {0x1002, 0x4152, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \ |
| {0x1002, 0x4153, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \ |
| {0x1002, 0x4154, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \ |
| {0x1002, 0x4155, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \ |
| {0x1002, 0x4156, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \ |
| {0x1002, 0x4237, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS200|RADEON_IS_IGP}, \ |
| {0x1002, 0x4242, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \ |
| {0x1002, 0x4243, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \ |
| {0x1002, 0x4336, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS100|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \ |
| {0x1002, 0x4337, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS200|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \ |
| {0x1002, 0x4437, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS200|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \ |
| {0x1002, 0x4966, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250}, \ |
| {0x1002, 0x4967, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250}, \ |
| {0x1002, 0x4A48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x4A49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x4A4A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x4A4B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x4A4C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x4A4D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x4A4E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x4A4F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x4A50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x4A54, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x4B49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x4B4A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x4B4B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x4B4C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x4C57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV200|RADEON_IS_MOBILITY}, \ |
| {0x1002, 0x4C58, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV200|RADEON_IS_MOBILITY}, \ |
| {0x1002, 0x4C59, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100|RADEON_IS_MOBILITY}, \ |
| {0x1002, 0x4C5A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100|RADEON_IS_MOBILITY}, \ |
| {0x1002, 0x4C64, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250|RADEON_IS_MOBILITY}, \ |
| {0x1002, 0x4C66, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250|RADEON_IS_MOBILITY}, \ |
| {0x1002, 0x4C67, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250|RADEON_IS_MOBILITY}, \ |
| {0x1002, 0x4E44, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \ |
| {0x1002, 0x4E45, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \ |
| {0x1002, 0x4E46, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \ |
| {0x1002, 0x4E47, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \ |
| {0x1002, 0x4E48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \ |
| {0x1002, 0x4E49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \ |
| {0x1002, 0x4E4A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \ |
| {0x1002, 0x4E4B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \ |
| {0x1002, 0x4E50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350|RADEON_IS_MOBILITY}, \ |
| {0x1002, 0x4E51, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350|RADEON_IS_MOBILITY}, \ |
| {0x1002, 0x4E52, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350|RADEON_IS_MOBILITY}, \ |
| {0x1002, 0x4E53, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350|RADEON_IS_MOBILITY}, \ |
| {0x1002, 0x4E54, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350|RADEON_IS_MOBILITY}, \ |
| {0x1002, 0x4E56, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350|RADEON_IS_MOBILITY}, \ |
| {0x1002, 0x5144, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R100|RADEON_SINGLE_CRTC}, \ |
| {0x1002, 0x5145, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R100|RADEON_SINGLE_CRTC}, \ |
| {0x1002, 0x5146, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R100|RADEON_SINGLE_CRTC}, \ |
| {0x1002, 0x5147, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R100|RADEON_SINGLE_CRTC}, \ |
| {0x1002, 0x5148, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \ |
| {0x1002, 0x514C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \ |
| {0x1002, 0x514D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \ |
| {0x1002, 0x5157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV200}, \ |
| {0x1002, 0x5158, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV200}, \ |
| {0x1002, 0x5159, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \ |
| {0x1002, 0x515A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \ |
| {0x1002, 0x515E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \ |
| {0x1002, 0x5460, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \ |
| {0x1002, 0x5462, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \ |
| {0x1002, 0x5464, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \ |
| {0x1002, 0x5657, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x5548, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x5549, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x554A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x554B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x554C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x554D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x554E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x554F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x5550, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x5551, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x5552, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x5554, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x564A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x564B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x564F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x5652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x5653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x5834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP}, \ |
| {0x1002, 0x5835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \ |
| {0x1002, 0x5954, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ |
| {0x1002, 0x5955, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ |
| {0x1002, 0x5974, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ |
| {0x1002, 0x5975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ |
| {0x1002, 0x5960, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ |
| {0x1002, 0x5961, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ |
| {0x1002, 0x5962, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ |
| {0x1002, 0x5964, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ |
| {0x1002, 0x5965, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \ |
| {0x1002, 0x5969, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \ |
| {0x1002, 0x5a41, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_IGPGART}, \ |
| {0x1002, 0x5a42, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ |
| {0x1002, 0x5a61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_IGPGART}, \ |
| {0x1002, 0x5a62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \ |
| {0x1002, 0x5b60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x5b62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x5b63, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x5b64, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x5b65, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x5c61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280|RADEON_IS_MOBILITY}, \ |
| {0x1002, 0x5c63, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280|RADEON_IS_MOBILITY}, \ |
| {0x1002, 0x5d48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x5d49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x5d4a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x5d4c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x5d4d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x5d4e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x5d4f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x5d50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x5d52, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x5d57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x5e48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x5e4a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x5e4b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x5e4c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x5e4d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x5e4f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7101, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7103, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7104, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7105, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7108, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7109, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x710A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x710B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x710C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x710E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x710F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7140, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7141, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7142, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7143, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7144, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7145, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7146, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7147, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7149, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x714A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x714B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x714C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x714D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x714E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x714F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7151, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7152, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7153, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x715E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x715F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7180, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7181, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7183, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7186, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7187, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7188, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x718A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x718B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x718C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x718D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x718F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7193, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7196, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x719B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x719F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x71C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x71C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x71C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x71C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x71C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x71C5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x71C6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x71C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x71CD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x71CE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x71D2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x71D4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x71D5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x71D6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x71DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x71DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7210, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7240, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7243, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7244, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7245, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7246, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7247, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7248, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7249, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x724A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x724B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x724C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x724D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x724E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x724F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7280, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV570|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7281, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7283, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7284, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7287, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7288, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV570|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7289, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV570|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x728B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV570|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x728C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV570|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7290, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7291, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7293, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7297, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x791e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS690|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \ |
| {0x1002, 0x791f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS690|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \ |
| {0x1002, 0x793f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS600|RADEON_IS_IGP|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7941, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS600|RADEON_IS_IGP|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x7942, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS600|RADEON_IS_IGP|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x796c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \ |
| {0x1002, 0x796d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \ |
| {0x1002, 0x796e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \ |
| {0x1002, 0x796f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \ |
| {0x1002, 0x9400, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9401, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9402, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9403, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x940A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x940B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x940F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x94A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV740|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x94A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV740|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x94B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV740|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x94B3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV740|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x94B5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV740|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9440, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9441, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9442, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9444, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9446, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x944A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x944B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x944C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x944E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9450, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9452, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9456, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x945A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x945B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9460, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9462, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x946A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x946B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x947A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x947B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9480, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9487, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9488, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9489, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x948F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9490, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9491, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9498, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x949C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x949E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x949F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x94C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x94C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x94C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x94C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x94C5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x94C6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x94C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x94C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x94C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x94CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x94CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x94CD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9500, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9501, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9504, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9505, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9506, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9507, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9508, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9509, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x950F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9511, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9515, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9517, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9519, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9540, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9541, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9542, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x954E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x954F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9552, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9553, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9555, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9580, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9581, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9583, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9586, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9587, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9588, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9589, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x958A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x958B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x958C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x958D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x958E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x958F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9590, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9591, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9593, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9595, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9596, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9597, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9598, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9599, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x959B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x95C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x95C5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x95C6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x95C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x95C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x95C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x95C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x95CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x95CD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x95CE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x95CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \ |
| {0x1002, 0x9610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
| {0x1002, 0x9611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
| {0x1002, 0x9612, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
| {0x1002, 0x9613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
| {0x1002, 0x9614, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
| {0x1002, 0x9615, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
| {0x1002, 0x9616, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ |
| {0, 0, 0} |
| enum chipset_type { |
| NOT_SUPPORTED, |
| SUPPORTED, |
| }; |
| struct agp_version { |
| u16_t major; |
| u16_t minor; |
| }; |
| struct agp_bridge_data; |
| struct agp_kern_info { |
| struct agp_version version; |
| struct pci_dev *device; |
| enum chipset_type chipset; |
| unsigned long mode; |
| unsigned long aper_base; |
| size_t aper_size; |
| int max_memory; /* In pages */ |
| int current_memory; |
| bool cant_use_aperture; |
| unsigned long page_mask; |
| // struct vm_operations_struct *vm_ops; |
| }; |
| /** |
| * AGP data. |
| * |
| * \sa drm_agp_init() and drm_device::agp. |
| */ |
| struct drm_agp_head { |
| struct agp_kern_info agp_info; /**< AGP device information */ |
| // struct list_head memory; |
| unsigned long mode; /**< AGP mode */ |
| struct agp_bridge_data *bridge; |
| int enabled; /**< whether the AGP bus as been enabled */ |
| int acquired; /**< whether the AGP device has been acquired */ |
| unsigned long base; |
| int agp_mtrr; |
| int cant_use_aperture; |
| unsigned long page_mask; |
| }; |
| /** |
| * DRM device structure. This structure represent a complete card that |
| * may contain multiple heads. |
| */ |
| struct drm_device { |
| int irq_enabled; /**< True if irq handler is enabled */ |
| __volatile__ long context_flag; /**< Context swapping flag */ |
| __volatile__ long interrupt_flag; /**< Interruption handler flag */ |
| __volatile__ long dma_flag; /**< DMA dispatch flag */ |
| int last_checked; /**< Last context checked for DMA */ |
| int last_context; /**< Last current context */ |
| unsigned long last_switch; /**< jiffies at last context switch */ |
| struct drm_agp_head *agp; /**< AGP data */ |
| struct pci_dev *pdev; /**< PCI device structure */ |
| int pci_vendor; /**< PCI vendor id */ |
| int pci_device; /** PCI device id */ |
| int num_crtcs; /**< Number of CRTCs on this device */ |
| void *dev_private; /**< device private data */ |
| void *mm_private; |
| struct drm_mode_config mode_config; /**< Current mode config */ |
| }; |
| #define radeon_errata(rdev) (rdev)->asic->errata((rdev)) |
| /* |
| * ASICs helpers. |
| */ |
| #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ |
| (rdev->family == CHIP_RV200) || \ |
| (rdev->family == CHIP_RS100) || \ |
| (rdev->family == CHIP_RS200) || \ |
| (rdev->family == CHIP_RV250) || \ |
| (rdev->family == CHIP_RV280) || \ |
| (rdev->family == CHIP_RS300)) |
| #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ |
| (rdev->family == CHIP_RV350) || \ |
| (rdev->family == CHIP_R350) || \ |
| (rdev->family == CHIP_RV380) || \ |
| (rdev->family == CHIP_R420) || \ |
| (rdev->family == CHIP_R423) || \ |
| (rdev->family == CHIP_RV410) || \ |
| (rdev->family == CHIP_RS400) || \ |
| (rdev->family == CHIP_RS480)) |
| #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) |
| #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) |
| #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) |
| /* |
| * BIOS helpers. |
| */ |
| #define RBIOS8(i) (rdev->bios[i]) |
| #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) |
| #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) |
| int radeon_combios_init(struct radeon_device *rdev); |
| void radeon_combios_fini(struct radeon_device *rdev); |
| int radeon_atombios_init(struct radeon_device *rdev); |
| void radeon_atombios_fini(struct radeon_device *rdev); |
| /* |
| * RING helpers. |
| */ |
| #define CP_PACKET0 0x00000000 |
| #define PACKET0_BASE_INDEX_SHIFT 0 |
| #define PACKET0_BASE_INDEX_MASK (0x1ffff << 0) |
| #define PACKET0_COUNT_SHIFT 16 |
| #define PACKET0_COUNT_MASK (0x3fff << 16) |
| #define CP_PACKET1 0x40000000 |
| #define CP_PACKET2 0x80000000 |
| #define PACKET2_PAD_SHIFT 0 |
| #define PACKET2_PAD_MASK (0x3fffffff << 0) |
| #define CP_PACKET3 0xC0000000 |
| #define PACKET3_IT_OPCODE_SHIFT 8 |
| #define PACKET3_IT_OPCODE_MASK (0xff << 8) |
| #define PACKET3_COUNT_SHIFT 16 |
| #define PACKET3_COUNT_MASK (0x3fff << 16) |
| /* PACKET3 op code */ |
| #define PACKET3_NOP 0x10 |
| #define PACKET3_3D_DRAW_VBUF 0x28 |
| #define PACKET3_3D_DRAW_IMMD 0x29 |
| #define PACKET3_3D_DRAW_INDX 0x2A |
| #define PACKET3_3D_LOAD_VBPNTR 0x2F |
| #define PACKET3_INDX_BUFFER 0x33 |
| #define PACKET3_3D_DRAW_VBUF_2 0x34 |
| #define PACKET3_3D_DRAW_IMMD_2 0x35 |
| #define PACKET3_3D_DRAW_INDX_2 0x36 |
| #define PACKET3_BITBLT_MULTI 0x9B |
| #define PACKET0(reg, n) (CP_PACKET0 | \ |
| REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \ |
| REG_SET(PACKET0_COUNT, (n))) |
| #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) |
| #define PACKET3(op, n) (CP_PACKET3 | \ |
| REG_SET(PACKET3_IT_OPCODE, (op)) | \ |
| REG_SET(PACKET3_COUNT, (n))) |
| #define PACKET_TYPE0 0 |
| #define PACKET_TYPE1 1 |
| #define PACKET_TYPE2 2 |
| #define PACKET_TYPE3 3 |
| #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) |
| #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) |
| #define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2) |
| #define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1) |
| #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) |
| static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v) |
| { |
| #if DRM_DEBUG_CODE |
| if (rdev->cp.count_dw <= 0) { |
| DRM_ERROR("radeon: writting more dword to ring than expected !\n"); |
| } |
| #endif |
| rdev->cp.ring[rdev->cp.wptr++] = v; |
| rdev->cp.wptr &= rdev->cp.ptr_mask; |
| rdev->cp.count_dw--; |
| rdev->cp.ring_free_dw--; |
| } |
| /* |
| * ASICs macro. |
| */ |
| #define radeon_init(rdev) (rdev)->asic->init((rdev)) |
| #define radeon_cs_parse(p) rdev->asic->cs_parse((p)) |
| #define radeon_errata(rdev) (rdev)->asic->errata((rdev)) |
| #define radeon_vram_info(rdev) (rdev)->asic->vram_info((rdev)) |
| #define radeon_gpu_reset(rdev) (rdev)->asic->gpu_reset((rdev)) |
| #define radeon_mc_init(rdev) (rdev)->asic->mc_init((rdev)) |
| #define radeon_mc_fini(rdev) (rdev)->asic->mc_fini((rdev)) |
| #define radeon_wb_init(rdev) (rdev)->asic->wb_init((rdev)) |
| #define radeon_wb_fini(rdev) (rdev)->asic->wb_fini((rdev)) |
| #define radeon_gart_enable(rdev) (rdev)->asic->gart_enable((rdev)) |
| #define radeon_gart_disable(rdev) (rdev)->asic->gart_disable((rdev)) |
| #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev)) |
| #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p)) |
| #define radeon_cp_init(rdev,rsize) (rdev)->asic->cp_init((rdev), (rsize)) |
| #define radeon_cp_fini(rdev) (rdev)->asic->cp_fini((rdev)) |
| #define radeon_cp_disable(rdev) (rdev)->asic->cp_disable((rdev)) |
| #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev)) |
| #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev)) |
| #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev)) |
| #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence)) |
| #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f)) |
| #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f)) |
| #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f)) |
| #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e)) |
| #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e)) |
| #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l)) |
| #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e)) |
| #define DRM_UDELAY(d) udelay(d) |
| resource_size_t |
| drm_get_resource_start(struct drm_device *dev, unsigned int resource); |
| resource_size_t |
| drm_get_resource_len(struct drm_device *dev, unsigned int resource); |
| #endif |
| /drivers/video/drm/radeon/radeon_asic.h |
|---|
| 0,0 → 1,435 |
| /* |
| * Copyright 2008 Advanced Micro Devices, Inc. |
| * Copyright 2008 Red Hat Inc. |
| * Copyright 2009 Jerome Glisse. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice shall be included in |
| * all copies or substantial portions of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| * OTHER DEALINGS IN THE SOFTWARE. |
| * |
| * Authors: Dave Airlie |
| * Alex Deucher |
| * Jerome Glisse |
| */ |
| #ifndef __RADEON_ASIC_H__ |
| #define __RADEON_ASIC_H__ |
| /* |
| * common functions |
| */ |
| void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); |
| void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
| void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); |
| void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock); |
| void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); |
| /* |
| * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 |
| */ |
| int r100_init(struct radeon_device *rdev); |
| uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg); |
| void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
| void r100_errata(struct radeon_device *rdev); |
| void r100_vram_info(struct radeon_device *rdev); |
| int r100_gpu_reset(struct radeon_device *rdev); |
| int r100_mc_init(struct radeon_device *rdev); |
| void r100_mc_fini(struct radeon_device *rdev); |
| int r100_wb_init(struct radeon_device *rdev); |
| void r100_wb_fini(struct radeon_device *rdev); |
| int r100_gart_enable(struct radeon_device *rdev); |
| void r100_pci_gart_disable(struct radeon_device *rdev); |
| void r100_pci_gart_tlb_flush(struct radeon_device *rdev); |
| int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); |
| int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); |
| void r100_cp_fini(struct radeon_device *rdev); |
| void r100_cp_disable(struct radeon_device *rdev); |
| void r100_ring_start(struct radeon_device *rdev); |
| int r100_irq_set(struct radeon_device *rdev); |
| int r100_irq_process(struct radeon_device *rdev); |
| //void r100_fence_ring_emit(struct radeon_device *rdev, |
| // struct radeon_fence *fence); |
| //int r100_cs_parse(struct radeon_cs_parser *p); |
| void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
| uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg); |
| //int r100_copy_blit(struct radeon_device *rdev, |
| // uint64_t src_offset, |
| // uint64_t dst_offset, |
| // unsigned num_pages, |
| // struct radeon_fence *fence); |
| #if 0 |
| static struct radeon_asic r100_asic = { |
| .init = &r100_init, |
| .errata = &r100_errata, |
| .vram_info = &r100_vram_info, |
| .gpu_reset = &r100_gpu_reset, |
| .mc_init = &r100_mc_init, |
| .mc_fini = &r100_mc_fini, |
| .wb_init = &r100_wb_init, |
| .wb_fini = &r100_wb_fini, |
| .gart_enable = &r100_gart_enable, |
| .gart_disable = &r100_pci_gart_disable, |
| .gart_tlb_flush = &r100_pci_gart_tlb_flush, |
| .gart_set_page = &r100_pci_gart_set_page, |
| .cp_init = &r100_cp_init, |
| .cp_fini = &r100_cp_fini, |
| .cp_disable = &r100_cp_disable, |
| .ring_start = &r100_ring_start, |
| .irq_set = &r100_irq_set, |
| .irq_process = &r100_irq_process, |
| // .fence_ring_emit = &r100_fence_ring_emit, |
| // .cs_parse = &r100_cs_parse, |
| // .copy_blit = &r100_copy_blit, |
| // .copy_dma = NULL, |
| // .copy = &r100_copy_blit, |
| .set_engine_clock = &radeon_legacy_set_engine_clock, |
| .set_memory_clock = NULL, |
| .set_pcie_lanes = NULL, |
| .set_clock_gating = &radeon_legacy_set_clock_gating, |
| }; |
| /* |
| * r300,r350,rv350,rv380 |
| */ |
| int r300_init(struct radeon_device *rdev); |
| void r300_errata(struct radeon_device *rdev); |
| void r300_vram_info(struct radeon_device *rdev); |
| int r300_gpu_reset(struct radeon_device *rdev); |
| int r300_mc_init(struct radeon_device *rdev); |
| void r300_mc_fini(struct radeon_device *rdev); |
| void r300_ring_start(struct radeon_device *rdev); |
| //void r300_fence_ring_emit(struct radeon_device *rdev, |
| // struct radeon_fence *fence); |
| //int r300_cs_parse(struct radeon_cs_parser *p); |
| int r300_gart_enable(struct radeon_device *rdev); |
| void rv370_pcie_gart_disable(struct radeon_device *rdev); |
| void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev); |
| int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); |
| uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg); |
| void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
| void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes); |
| //int r300_copy_dma(struct radeon_device *rdev, |
| // uint64_t src_offset, |
| // uint64_t dst_offset, |
| // unsigned num_pages, |
| // struct radeon_fence *fence); |
| static struct radeon_asic r300_asic = { |
| .init = &r300_init, |
| .errata = &r300_errata, |
| .vram_info = &r300_vram_info, |
| .gpu_reset = &r300_gpu_reset, |
| .mc_init = &r300_mc_init, |
| .mc_fini = &r300_mc_fini, |
| .wb_init = &r100_wb_init, |
| .wb_fini = &r100_wb_fini, |
| .gart_enable = &r300_gart_enable, |
| .gart_disable = &r100_pci_gart_disable, |
| .gart_tlb_flush = &r100_pci_gart_tlb_flush, |
| .gart_set_page = &r100_pci_gart_set_page, |
| .cp_init = &r100_cp_init, |
| .cp_fini = &r100_cp_fini, |
| .cp_disable = &r100_cp_disable, |
| .ring_start = &r300_ring_start, |
| .irq_set = &r100_irq_set, |
| .irq_process = &r100_irq_process, |
| // .fence_ring_emit = &r300_fence_ring_emit, |
| // .cs_parse = &r300_cs_parse, |
| // .copy_blit = &r100_copy_blit, |
| // .copy_dma = &r300_copy_dma, |
| // .copy = &r100_copy_blit, |
| .set_engine_clock = &radeon_legacy_set_engine_clock, |
| .set_memory_clock = NULL, |
| .set_pcie_lanes = &rv370_set_pcie_lanes, |
| .set_clock_gating = &radeon_legacy_set_clock_gating, |
| }; |
| /* |
| * r420,r423,rv410 |
| */ |
| void r420_errata(struct radeon_device *rdev); |
| void r420_vram_info(struct radeon_device *rdev); |
| int r420_mc_init(struct radeon_device *rdev); |
| void r420_mc_fini(struct radeon_device *rdev); |
| static struct radeon_asic r420_asic = { |
| .init = &r300_init, |
| .errata = &r420_errata, |
| .vram_info = &r420_vram_info, |
| .gpu_reset = &r300_gpu_reset, |
| .mc_init = &r420_mc_init, |
| .mc_fini = &r420_mc_fini, |
| .wb_init = &r100_wb_init, |
| .wb_fini = &r100_wb_fini, |
| .gart_enable = &r300_gart_enable, |
| .gart_disable = &rv370_pcie_gart_disable, |
| .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
| .gart_set_page = &rv370_pcie_gart_set_page, |
| .cp_init = &r100_cp_init, |
| .cp_fini = &r100_cp_fini, |
| .cp_disable = &r100_cp_disable, |
| .ring_start = &r300_ring_start, |
| .irq_set = &r100_irq_set, |
| .irq_process = &r100_irq_process, |
| // .fence_ring_emit = &r300_fence_ring_emit, |
| // .cs_parse = &r300_cs_parse, |
| // .copy_blit = &r100_copy_blit, |
| // .copy_dma = &r300_copy_dma, |
| // .copy = &r100_copy_blit, |
| .set_engine_clock = &radeon_atom_set_engine_clock, |
| .set_memory_clock = &radeon_atom_set_memory_clock, |
| .set_pcie_lanes = &rv370_set_pcie_lanes, |
| .set_clock_gating = &radeon_atom_set_clock_gating, |
| }; |
| /* |
| * rs400,rs480 |
| */ |
| void rs400_errata(struct radeon_device *rdev); |
| void rs400_vram_info(struct radeon_device *rdev); |
| int rs400_mc_init(struct radeon_device *rdev); |
| void rs400_mc_fini(struct radeon_device *rdev); |
| int rs400_gart_enable(struct radeon_device *rdev); |
| void rs400_gart_disable(struct radeon_device *rdev); |
| void rs400_gart_tlb_flush(struct radeon_device *rdev); |
| int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); |
| uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
| void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
| static struct radeon_asic rs400_asic = { |
| .init = &r300_init, |
| .errata = &rs400_errata, |
| .vram_info = &rs400_vram_info, |
| .gpu_reset = &r300_gpu_reset, |
| .mc_init = &rs400_mc_init, |
| .mc_fini = &rs400_mc_fini, |
| .wb_init = &r100_wb_init, |
| .wb_fini = &r100_wb_fini, |
| .gart_enable = &rs400_gart_enable, |
| .gart_disable = &rs400_gart_disable, |
| .gart_tlb_flush = &rs400_gart_tlb_flush, |
| .gart_set_page = &rs400_gart_set_page, |
| .cp_init = &r100_cp_init, |
| .cp_fini = &r100_cp_fini, |
| .cp_disable = &r100_cp_disable, |
| .ring_start = &r300_ring_start, |
| .irq_set = &r100_irq_set, |
| .irq_process = &r100_irq_process, |
| // .fence_ring_emit = &r300_fence_ring_emit, |
| // .cs_parse = &r300_cs_parse, |
| // .copy_blit = &r100_copy_blit, |
| // .copy_dma = &r300_copy_dma, |
| // .copy = &r100_copy_blit, |
| .set_engine_clock = &radeon_legacy_set_engine_clock, |
| .set_memory_clock = NULL, |
| .set_pcie_lanes = NULL, |
| .set_clock_gating = &radeon_legacy_set_clock_gating, |
| }; |
| /* |
| * rs600. |
| */ |
| void rs600_errata(struct radeon_device *rdev); |
| void rs600_vram_info(struct radeon_device *rdev); |
| int rs600_mc_init(struct radeon_device *rdev); |
| void rs600_mc_fini(struct radeon_device *rdev); |
| int rs600_irq_set(struct radeon_device *rdev); |
| int rs600_gart_enable(struct radeon_device *rdev); |
| void rs600_gart_disable(struct radeon_device *rdev); |
| void rs600_gart_tlb_flush(struct radeon_device *rdev); |
| int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); |
| uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
| void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
| static struct radeon_asic rs600_asic = { |
| .init = &r300_init, |
| .errata = &rs600_errata, |
| .vram_info = &rs600_vram_info, |
| .gpu_reset = &r300_gpu_reset, |
| .mc_init = &rs600_mc_init, |
| .mc_fini = &rs600_mc_fini, |
| .wb_init = &r100_wb_init, |
| .wb_fini = &r100_wb_fini, |
| .gart_enable = &rs600_gart_enable, |
| .gart_disable = &rs600_gart_disable, |
| .gart_tlb_flush = &rs600_gart_tlb_flush, |
| .gart_set_page = &rs600_gart_set_page, |
| .cp_init = &r100_cp_init, |
| .cp_fini = &r100_cp_fini, |
| .cp_disable = &r100_cp_disable, |
| .ring_start = &r300_ring_start, |
| .irq_set = &rs600_irq_set, |
| .irq_process = &r100_irq_process, |
| // .fence_ring_emit = &r300_fence_ring_emit, |
| // .cs_parse = &r300_cs_parse, |
| // .copy_blit = &r100_copy_blit, |
| // .copy_dma = &r300_copy_dma, |
| // .copy = &r100_copy_blit, |
| .set_engine_clock = &radeon_atom_set_engine_clock, |
| .set_memory_clock = &radeon_atom_set_memory_clock, |
| .set_pcie_lanes = NULL, |
| .set_clock_gating = &radeon_atom_set_clock_gating, |
| }; |
| /* |
| * rs690,rs740 |
| */ |
| void rs690_errata(struct radeon_device *rdev); |
| void rs690_vram_info(struct radeon_device *rdev); |
| int rs690_mc_init(struct radeon_device *rdev); |
| void rs690_mc_fini(struct radeon_device *rdev); |
| uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
| void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
| static struct radeon_asic rs690_asic = { |
| .init = &r300_init, |
| .errata = &rs690_errata, |
| .vram_info = &rs690_vram_info, |
| .gpu_reset = &r300_gpu_reset, |
| .mc_init = &rs690_mc_init, |
| .mc_fini = &rs690_mc_fini, |
| .wb_init = &r100_wb_init, |
| .wb_fini = &r100_wb_fini, |
| .gart_enable = &rs400_gart_enable, |
| .gart_disable = &rs400_gart_disable, |
| .gart_tlb_flush = &rs400_gart_tlb_flush, |
| .gart_set_page = &rs400_gart_set_page, |
| .cp_init = &r100_cp_init, |
| .cp_fini = &r100_cp_fini, |
| .cp_disable = &r100_cp_disable, |
| .ring_start = &r300_ring_start, |
| .irq_set = &rs600_irq_set, |
| .irq_process = &r100_irq_process, |
| // .fence_ring_emit = &r300_fence_ring_emit, |
| // .cs_parse = &r300_cs_parse, |
| // .copy_blit = &r100_copy_blit, |
| // .copy_dma = &r300_copy_dma, |
| // .copy = &r300_copy_dma, |
| .set_engine_clock = &radeon_atom_set_engine_clock, |
| .set_memory_clock = &radeon_atom_set_memory_clock, |
| .set_pcie_lanes = NULL, |
| .set_clock_gating = &radeon_atom_set_clock_gating, |
| }; |
| #endif |
| /* |
| * rv515 |
| */ |
| int rv515_init(struct radeon_device *rdev); |
| void rv515_errata(struct radeon_device *rdev); |
| void rv515_vram_info(struct radeon_device *rdev); |
| int rv515_gpu_reset(struct radeon_device *rdev); |
| int rv515_mc_init(struct radeon_device *rdev); |
| void rv515_mc_fini(struct radeon_device *rdev); |
| uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg); |
| void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
| void rv515_ring_start(struct radeon_device *rdev); |
| uint32_t rv515_pcie_rreg(struct radeon_device *rdev, uint32_t reg); |
| void rv515_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
| /* |
| static struct radeon_asic rv515_asic = { |
| .init = &rv515_init, |
| .errata = &rv515_errata, |
| .vram_info = &rv515_vram_info, |
| .gpu_reset = &rv515_gpu_reset, |
| .mc_init = &rv515_mc_init, |
| .mc_fini = &rv515_mc_fini, |
| .wb_init = &r100_wb_init, |
| .wb_fini = &r100_wb_fini, |
| .gart_enable = &r300_gart_enable, |
| .gart_disable = &rv370_pcie_gart_disable, |
| .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
| .gart_set_page = &rv370_pcie_gart_set_page, |
| .cp_init = &r100_cp_init, |
| .cp_fini = &r100_cp_fini, |
| .cp_disable = &r100_cp_disable, |
| .ring_start = &rv515_ring_start, |
| .irq_set = &r100_irq_set, |
| .irq_process = &r100_irq_process, |
| // .fence_ring_emit = &r300_fence_ring_emit, |
| // .cs_parse = &r300_cs_parse, |
| // .copy_blit = &r100_copy_blit, |
| // .copy_dma = &r300_copy_dma, |
| // .copy = &r100_copy_blit, |
| .set_engine_clock = &radeon_atom_set_engine_clock, |
| .set_memory_clock = &radeon_atom_set_memory_clock, |
| .set_pcie_lanes = &rv370_set_pcie_lanes, |
| .set_clock_gating = &radeon_atom_set_clock_gating, |
| }; |
| */ |
| int r300_gart_enable(struct radeon_device *rdev); |
| void rv370_pcie_gart_disable(struct radeon_device *rdev); |
| void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev); |
| int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); |
| uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg); |
| void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
| void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes); |
| /* |
| * r520,rv530,rv560,rv570,r580 |
| */ |
| void r520_errata(struct radeon_device *rdev); |
| void r520_vram_info(struct radeon_device *rdev); |
| int r520_mc_init(struct radeon_device *rdev); |
| void r520_mc_fini(struct radeon_device *rdev); |
| static struct radeon_asic r520_asic = { |
| .init = &rv515_init, |
| .errata = &r520_errata, |
| .vram_info = &r520_vram_info, |
| .gpu_reset = &rv515_gpu_reset, |
| // .mc_init = &r520_mc_init, |
| // .mc_fini = &r520_mc_fini, |
| // .wb_init = &r100_wb_init, |
| // .wb_fini = &r100_wb_fini, |
| // .gart_enable = &r300_gart_enable, |
| // .gart_disable = &rv370_pcie_gart_disable, |
| // .gart_tlb_flush = &rv370_pcie_gart_tlb_flush, |
| // .gart_set_page = &rv370_pcie_gart_set_page, |
| // .cp_init = &r100_cp_init, |
| // .cp_fini = &r100_cp_fini, |
| // .cp_disable = &r100_cp_disable, |
| // .ring_start = &rv515_ring_start, |
| // .irq_set = &r100_irq_set, |
| // .irq_process = &r100_irq_process, |
| // .fence_ring_emit = &r300_fence_ring_emit, |
| // .cs_parse = &r300_cs_parse, |
| // .copy_blit = &r100_copy_blit, |
| // .copy_dma = &r300_copy_dma, |
| // .copy = &r100_copy_blit, |
| // .set_engine_clock = &radeon_atom_set_engine_clock, |
| // .set_memory_clock = &radeon_atom_set_memory_clock, |
| // .set_pcie_lanes = &rv370_set_pcie_lanes, |
| // .set_clock_gating = &radeon_atom_set_clock_gating, |
| }; |
| /* |
| * r600,rv610,rv630,rv620,rv635,rv670,rs780,rv770,rv730,rv710 |
| */ |
| uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg); |
| void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
| #endif |
| /drivers/video/drm/radeon/radeon_atombios.c |
|---|
| 0,0 → 1,1298 |
| /* |
| * Copyright 2007-8 Advanced Micro Devices, Inc. |
| * Copyright 2008 Red Hat Inc. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice shall be included in |
| * all copies or substantial portions of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| * OTHER DEALINGS IN THE SOFTWARE. |
| * |
| * Authors: Dave Airlie |
| * Alex Deucher |
| */ |
| //#include "drmP.h" |
| #include "radeon_drm.h" |
| #include "radeon.h" |
| #include "atom.h" |
| #include "atom-bits.h" |
| /* from radeon_encoder.c */ |
| extern uint32_t |
| radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, |
| uint8_t dac); |
| extern void radeon_link_encoder_connector(struct drm_device *dev); |
| extern void |
| radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, |
| uint32_t supported_device); |
| /* from radeon_connector.c */ |
| extern void |
| radeon_add_atom_connector(struct drm_device *dev, |
| uint32_t connector_id, |
| uint32_t supported_device, |
| int connector_type, |
| struct radeon_i2c_bus_rec *i2c_bus, |
| bool linkb, uint32_t igp_lane_info); |
| /* from radeon_legacy_encoder.c */ |
| extern void |
| radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id, |
| uint32_t supported_device); |
| union atom_supported_devices { |
| struct _ATOM_SUPPORTED_DEVICES_INFO info; |
| struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2; |
| struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1; |
| }; |
| static inline struct radeon_i2c_bus_rec radeon_lookup_gpio(struct drm_device |
| *dev, uint8_t id) |
| { |
| struct radeon_device *rdev = dev->dev_private; |
| struct atom_context *ctx = rdev->mode_info.atom_context; |
| ATOM_GPIO_I2C_ASSIGMENT gpio; |
| struct radeon_i2c_bus_rec i2c; |
| int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info); |
| struct _ATOM_GPIO_I2C_INFO *i2c_info; |
| uint16_t data_offset; |
| memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec)); |
| i2c.valid = false; |
| atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset); |
| i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset); |
| gpio = i2c_info->asGPIO_Info[id]; |
| i2c.mask_clk_reg = le16_to_cpu(gpio.usClkMaskRegisterIndex) * 4; |
| i2c.mask_data_reg = le16_to_cpu(gpio.usDataMaskRegisterIndex) * 4; |
| i2c.put_clk_reg = le16_to_cpu(gpio.usClkEnRegisterIndex) * 4; |
| i2c.put_data_reg = le16_to_cpu(gpio.usDataEnRegisterIndex) * 4; |
| i2c.get_clk_reg = le16_to_cpu(gpio.usClkY_RegisterIndex) * 4; |
| i2c.get_data_reg = le16_to_cpu(gpio.usDataY_RegisterIndex) * 4; |
| i2c.a_clk_reg = le16_to_cpu(gpio.usClkA_RegisterIndex) * 4; |
| i2c.a_data_reg = le16_to_cpu(gpio.usDataA_RegisterIndex) * 4; |
| i2c.mask_clk_mask = (1 << gpio.ucClkMaskShift); |
| i2c.mask_data_mask = (1 << gpio.ucDataMaskShift); |
| i2c.put_clk_mask = (1 << gpio.ucClkEnShift); |
| i2c.put_data_mask = (1 << gpio.ucDataEnShift); |
| i2c.get_clk_mask = (1 << gpio.ucClkY_Shift); |
| i2c.get_data_mask = (1 << gpio.ucDataY_Shift); |
| i2c.a_clk_mask = (1 << gpio.ucClkA_Shift); |
| i2c.a_data_mask = (1 << gpio.ucDataA_Shift); |
| i2c.valid = true; |
| return i2c; |
| } |
| static bool radeon_atom_apply_quirks(struct drm_device *dev, |
| uint32_t supported_device, |
| int *connector_type, |
| struct radeon_i2c_bus_rec *i2c_bus) |
| { |
| /* Asus M2A-VM HDMI board lists the DVI port as HDMI */ |
| if ((dev->pdev->device == 0x791e) && |
| (dev->pdev->subsystem_vendor == 0x1043) && |
| (dev->pdev->subsystem_device == 0x826d)) { |
| if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) && |
| (supported_device == ATOM_DEVICE_DFP3_SUPPORT)) |
| *connector_type = DRM_MODE_CONNECTOR_DVID; |
| } |
| /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */ |
| if ((dev->pdev->device == 0x7941) && |
| (dev->pdev->subsystem_vendor == 0x147b) && |
| (dev->pdev->subsystem_device == 0x2412)) { |
| if (*connector_type == DRM_MODE_CONNECTOR_DVII) |
| return false; |
| } |
| /* Falcon NW laptop lists vga ddc line for LVDS */ |
| if ((dev->pdev->device == 0x5653) && |
| (dev->pdev->subsystem_vendor == 0x1462) && |
| (dev->pdev->subsystem_device == 0x0291)) { |
| if (*connector_type == DRM_MODE_CONNECTOR_LVDS) |
| i2c_bus->valid = false; |
| } |
| /* Funky macbooks */ |
| if ((dev->pdev->device == 0x71C5) && |
| (dev->pdev->subsystem_vendor == 0x106b) && |
| (dev->pdev->subsystem_device == 0x0080)) { |
| if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) || |
| (supported_device == ATOM_DEVICE_DFP2_SUPPORT)) |
| return false; |
| } |
| /* some BIOSes seem to report DAC on HDMI - they hurt me with their lies */ |
| if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) || |
| (*connector_type == DRM_MODE_CONNECTOR_HDMIB)) { |
| if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) { |
| return false; |
| } |
| } |
| /* ASUS HD 3600 XT board lists the DVI port as HDMI */ |
| if ((dev->pdev->device == 0x9598) && |
| (dev->pdev->subsystem_vendor == 0x1043) && |
| (dev->pdev->subsystem_device == 0x01da)) { |
| if (*connector_type == DRM_MODE_CONNECTOR_HDMIB) { |
| *connector_type = DRM_MODE_CONNECTOR_DVID; |
| } |
| } |
| return true; |
| } |
| const int supported_devices_connector_convert[] = { |
| DRM_MODE_CONNECTOR_Unknown, |
| DRM_MODE_CONNECTOR_VGA, |
| DRM_MODE_CONNECTOR_DVII, |
| DRM_MODE_CONNECTOR_DVID, |
| DRM_MODE_CONNECTOR_DVIA, |
| DRM_MODE_CONNECTOR_SVIDEO, |
| DRM_MODE_CONNECTOR_Composite, |
| DRM_MODE_CONNECTOR_LVDS, |
| DRM_MODE_CONNECTOR_Unknown, |
| DRM_MODE_CONNECTOR_Unknown, |
| DRM_MODE_CONNECTOR_HDMIA, |
| DRM_MODE_CONNECTOR_HDMIB, |
| DRM_MODE_CONNECTOR_Unknown, |
| DRM_MODE_CONNECTOR_Unknown, |
| DRM_MODE_CONNECTOR_9PinDIN, |
| DRM_MODE_CONNECTOR_DisplayPort |
| }; |
| const int object_connector_convert[] = { |
| DRM_MODE_CONNECTOR_Unknown, |
| DRM_MODE_CONNECTOR_DVII, |
| DRM_MODE_CONNECTOR_DVII, |
| DRM_MODE_CONNECTOR_DVID, |
| DRM_MODE_CONNECTOR_DVID, |
| DRM_MODE_CONNECTOR_VGA, |
| DRM_MODE_CONNECTOR_Composite, |
| DRM_MODE_CONNECTOR_SVIDEO, |
| DRM_MODE_CONNECTOR_Unknown, |
| DRM_MODE_CONNECTOR_9PinDIN, |
| DRM_MODE_CONNECTOR_Unknown, |
| DRM_MODE_CONNECTOR_HDMIA, |
| DRM_MODE_CONNECTOR_HDMIB, |
| DRM_MODE_CONNECTOR_HDMIB, |
| DRM_MODE_CONNECTOR_LVDS, |
| DRM_MODE_CONNECTOR_9PinDIN, |
| DRM_MODE_CONNECTOR_Unknown, |
| DRM_MODE_CONNECTOR_Unknown, |
| DRM_MODE_CONNECTOR_Unknown, |
| DRM_MODE_CONNECTOR_DisplayPort |
| }; |
| bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev) |
| { |
| struct radeon_device *rdev = dev->dev_private; |
| struct radeon_mode_info *mode_info = &rdev->mode_info; |
| struct atom_context *ctx = mode_info->atom_context; |
| int index = GetIndexIntoMasterTable(DATA, Object_Header); |
| uint16_t size, data_offset; |
| uint8_t frev, crev, line_mux = 0; |
| ATOM_CONNECTOR_OBJECT_TABLE *con_obj; |
| ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj; |
| ATOM_OBJECT_HEADER *obj_header; |
| int i, j, path_size, device_support; |
| int connector_type; |
| uint16_t igp_lane_info; |
| bool linkb; |
| struct radeon_i2c_bus_rec ddc_bus; |
| atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset); |
| if (data_offset == 0) |
| return false; |
| if (crev < 2) |
| return false; |
| obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset); |
| path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *) |
| (ctx->bios + data_offset + |
| le16_to_cpu(obj_header->usDisplayPathTableOffset)); |
| con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *) |
| (ctx->bios + data_offset + |
| le16_to_cpu(obj_header->usConnectorObjectTableOffset)); |
| device_support = le16_to_cpu(obj_header->usDeviceSupport); |
| path_size = 0; |
| for (i = 0; i < path_obj->ucNumOfDispPath; i++) { |
| uint8_t *addr = (uint8_t *) path_obj->asDispPath; |
| ATOM_DISPLAY_OBJECT_PATH *path; |
| addr += path_size; |
| path = (ATOM_DISPLAY_OBJECT_PATH *) addr; |
| path_size += le16_to_cpu(path->usSize); |
| linkb = false; |
| if (device_support & le16_to_cpu(path->usDeviceTag)) { |
| uint8_t con_obj_id, con_obj_num, con_obj_type; |
| con_obj_id = |
| (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK) |
| >> OBJECT_ID_SHIFT; |
| con_obj_num = |
| (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK) |
| >> ENUM_ID_SHIFT; |
| con_obj_type = |
| (le16_to_cpu(path->usConnObjectId) & |
| OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; |
| if ((le16_to_cpu(path->usDeviceTag) == |
| ATOM_DEVICE_TV1_SUPPORT) |
| || (le16_to_cpu(path->usDeviceTag) == |
| ATOM_DEVICE_TV2_SUPPORT) |
| || (le16_to_cpu(path->usDeviceTag) == |
| ATOM_DEVICE_CV_SUPPORT)) |
| continue; |
| if ((rdev->family == CHIP_RS780) && |
| (con_obj_id == |
| CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) { |
| uint16_t igp_offset = 0; |
| ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj; |
| index = |
| GetIndexIntoMasterTable(DATA, |
| IntegratedSystemInfo); |
| atom_parse_data_header(ctx, index, &size, &frev, |
| &crev, &igp_offset); |
| if (crev >= 2) { |
| igp_obj = |
| (ATOM_INTEGRATED_SYSTEM_INFO_V2 |
| *) (ctx->bios + igp_offset); |
| if (igp_obj) { |
| uint32_t slot_config, ct; |
| if (con_obj_num == 1) |
| slot_config = |
| igp_obj-> |
| ulDDISlot1Config; |
| else |
| slot_config = |
| igp_obj-> |
| ulDDISlot2Config; |
| ct = (slot_config >> 16) & 0xff; |
| connector_type = |
| object_connector_convert |
| [ct]; |
| igp_lane_info = |
| slot_config & 0xffff; |
| } else |
| continue; |
| } else |
| continue; |
| } else { |
| igp_lane_info = 0; |
| connector_type = |
| object_connector_convert[con_obj_id]; |
| } |
| if (connector_type == DRM_MODE_CONNECTOR_Unknown) |
| continue; |
| for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); |
| j++) { |
| uint8_t enc_obj_id, enc_obj_num, enc_obj_type; |
| enc_obj_id = |
| (le16_to_cpu(path->usGraphicObjIds[j]) & |
| OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; |
| enc_obj_num = |
| (le16_to_cpu(path->usGraphicObjIds[j]) & |
| ENUM_ID_MASK) >> ENUM_ID_SHIFT; |
| enc_obj_type = |
| (le16_to_cpu(path->usGraphicObjIds[j]) & |
| OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; |
| /* FIXME: add support for router objects */ |
| if (enc_obj_type == GRAPH_OBJECT_TYPE_ENCODER) { |
| if (enc_obj_num == 2) |
| linkb = true; |
| else |
| linkb = false; |
| // radeon_add_atom_encoder(dev, |
| // enc_obj_id, |
| // le16_to_cpu |
| // (path-> |
| // usDeviceTag)); |
| } |
| } |
| /* look up gpio for ddc */ |
| if ((le16_to_cpu(path->usDeviceTag) & |
| (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) |
| == 0) { |
| for (j = 0; j < con_obj->ucNumberOfObjects; j++) { |
| if (le16_to_cpu(path->usConnObjectId) == |
| le16_to_cpu(con_obj->asObjects[j]. |
| usObjectID)) { |
| ATOM_COMMON_RECORD_HEADER |
| *record = |
| (ATOM_COMMON_RECORD_HEADER |
| *) |
| (ctx->bios + data_offset + |
| le16_to_cpu(con_obj-> |
| asObjects[j]. |
| usRecordOffset)); |
| ATOM_I2C_RECORD *i2c_record; |
| while (record->ucRecordType > 0 |
| && record-> |
| ucRecordType <= |
| ATOM_MAX_OBJECT_RECORD_NUMBER) { |
| DRM_ERROR |
| ("record type %d\n", |
| record-> |
| ucRecordType); |
| switch (record-> |
| ucRecordType) { |
| case ATOM_I2C_RECORD_TYPE: |
| i2c_record = |
| (ATOM_I2C_RECORD |
| *) record; |
| line_mux = |
| i2c_record-> |
| sucI2cId. |
| bfI2C_LineMux; |
| break; |
| } |
| record = |
| (ATOM_COMMON_RECORD_HEADER |
| *) ((char *)record |
| + |
| record-> |
| ucRecordSize); |
| } |
| break; |
| } |
| } |
| } else |
| line_mux = 0; |
| if ((le16_to_cpu(path->usDeviceTag) == |
| ATOM_DEVICE_TV1_SUPPORT) |
| || (le16_to_cpu(path->usDeviceTag) == |
| ATOM_DEVICE_TV2_SUPPORT) |
| || (le16_to_cpu(path->usDeviceTag) == |
| ATOM_DEVICE_CV_SUPPORT)) |
| ddc_bus.valid = false; |
| else |
| ddc_bus = radeon_lookup_gpio(dev, line_mux); |
| // radeon_add_atom_connector(dev, |
| // le16_to_cpu(path-> |
| // usConnObjectId), |
| // le16_to_cpu(path-> |
| // usDeviceTag), |
| // connector_type, &ddc_bus, |
| // linkb, igp_lane_info); |
| } |
| } |
| // radeon_link_encoder_connector(dev); |
| return true; |
| } |
| struct bios_connector { |
| bool valid; |
| uint8_t line_mux; |
| uint16_t devices; |
| int connector_type; |
| struct radeon_i2c_bus_rec ddc_bus; |
| }; |
| bool radeon_get_atom_connector_info_from_supported_devices_table(struct |
| drm_device |
| *dev) |
| { |
| struct radeon_device *rdev = dev->dev_private; |
| struct radeon_mode_info *mode_info = &rdev->mode_info; |
| struct atom_context *ctx = mode_info->atom_context; |
| int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo); |
| uint16_t size, data_offset; |
| uint8_t frev, crev; |
| uint16_t device_support; |
| uint8_t dac; |
| union atom_supported_devices *supported_devices; |
| int i, j; |
| struct bios_connector bios_connectors[ATOM_MAX_SUPPORTED_DEVICE]; |
| atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset); |
| supported_devices = |
| (union atom_supported_devices *)(ctx->bios + data_offset); |
| device_support = le16_to_cpu(supported_devices->info.usDeviceSupport); |
| for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) { |
| ATOM_CONNECTOR_INFO_I2C ci = |
| supported_devices->info.asConnInfo[i]; |
| bios_connectors[i].valid = false; |
| if (!(device_support & (1 << i))) { |
| continue; |
| } |
| if (i == ATOM_DEVICE_CV_INDEX) { |
| DRM_DEBUG("Skipping Component Video\n"); |
| continue; |
| } |
| if (i == ATOM_DEVICE_TV1_INDEX) { |
| DRM_DEBUG("Skipping TV Out\n"); |
| continue; |
| } |
| bios_connectors[i].connector_type = |
| supported_devices_connector_convert[ci.sucConnectorInfo. |
| sbfAccess. |
| bfConnectorType]; |
| if (bios_connectors[i].connector_type == |
| DRM_MODE_CONNECTOR_Unknown) |
| continue; |
| dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC; |
| if ((rdev->family == CHIP_RS690) || |
| (rdev->family == CHIP_RS740)) { |
| if ((i == ATOM_DEVICE_DFP2_INDEX) |
| && (ci.sucI2cId.sbfAccess.bfI2C_LineMux == 2)) |
| bios_connectors[i].line_mux = |
| ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1; |
| else if ((i == ATOM_DEVICE_DFP3_INDEX) |
| && (ci.sucI2cId.sbfAccess.bfI2C_LineMux == 1)) |
| bios_connectors[i].line_mux = |
| ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1; |
| else |
| bios_connectors[i].line_mux = |
| ci.sucI2cId.sbfAccess.bfI2C_LineMux; |
| } else |
| bios_connectors[i].line_mux = |
| ci.sucI2cId.sbfAccess.bfI2C_LineMux; |
| /* give tv unique connector ids */ |
| if (i == ATOM_DEVICE_TV1_INDEX) { |
| bios_connectors[i].ddc_bus.valid = false; |
| bios_connectors[i].line_mux = 50; |
| } else if (i == ATOM_DEVICE_TV2_INDEX) { |
| bios_connectors[i].ddc_bus.valid = false; |
| bios_connectors[i].line_mux = 51; |
| } else if (i == ATOM_DEVICE_CV_INDEX) { |
| bios_connectors[i].ddc_bus.valid = false; |
| bios_connectors[i].line_mux = 52; |
| } else |
| bios_connectors[i].ddc_bus = |
| radeon_lookup_gpio(dev, |
| bios_connectors[i].line_mux); |
| /* Always set the connector type to VGA for CRT1/CRT2. if they are |
| * shared with a DVI port, we'll pick up the DVI connector when we |
| * merge the outputs. Some bioses incorrectly list VGA ports as DVI. |
| */ |
| if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX) |
| bios_connectors[i].connector_type = |
| DRM_MODE_CONNECTOR_VGA; |
| if (!radeon_atom_apply_quirks |
| (dev, (1 << i), &bios_connectors[i].connector_type, |
| &bios_connectors[i].ddc_bus)) |
| continue; |
| bios_connectors[i].valid = true; |
| bios_connectors[i].devices = (1 << i); |
| // if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom) |
| // radeon_add_atom_encoder(dev, |
| // radeon_get_encoder_id(dev, |
| // (1 << i), |
| // dac), |
| // (1 << i)); |
| // else |
| // radeon_add_legacy_encoder(dev, |
| // radeon_get_encoder_id(dev, |
| // (1 << |
| // i), |
| // dac), |
| // (1 << i)); |
| } |
| /* combine shared connectors */ |
| for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) { |
| if (bios_connectors[i].valid) { |
| for (j = 0; j < ATOM_MAX_SUPPORTED_DEVICE; j++) { |
| if (bios_connectors[j].valid && (i != j)) { |
| if (bios_connectors[i].line_mux == |
| bios_connectors[j].line_mux) { |
| if (((bios_connectors[i]. |
| devices & |
| (ATOM_DEVICE_DFP_SUPPORT)) |
| && (bios_connectors[j]. |
| devices & |
| (ATOM_DEVICE_CRT_SUPPORT))) |
| || |
| ((bios_connectors[j]. |
| devices & |
| (ATOM_DEVICE_DFP_SUPPORT)) |
| && (bios_connectors[i]. |
| devices & |
| (ATOM_DEVICE_CRT_SUPPORT)))) { |
| bios_connectors[i]. |
| devices |= |
| bios_connectors[j]. |
| devices; |
| bios_connectors[i]. |
| connector_type = |
| DRM_MODE_CONNECTOR_DVII; |
| bios_connectors[j]. |
| valid = false; |
| } |
| } |
| } |
| } |
| } |
| } |
| /* add the connectors */ |
| // for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) { |
| // if (bios_connectors[i].valid) |
| // radeon_add_atom_connector(dev, |
| // bios_connectors[i].line_mux, |
| // bios_connectors[i].devices, |
| // bios_connectors[i]. |
| // connector_type, |
| // &bios_connectors[i].ddc_bus, |
| // false, 0); |
| // } |
| // radeon_link_encoder_connector(dev); |
| return true; |
| } |
| union firmware_info { |
| ATOM_FIRMWARE_INFO info; |
| ATOM_FIRMWARE_INFO_V1_2 info_12; |
| ATOM_FIRMWARE_INFO_V1_3 info_13; |
| ATOM_FIRMWARE_INFO_V1_4 info_14; |
| }; |
| bool radeon_atom_get_clock_info(struct drm_device *dev) |
| { |
| struct radeon_device *rdev = dev->dev_private; |
| struct radeon_mode_info *mode_info = &rdev->mode_info; |
| int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); |
| union firmware_info *firmware_info; |
| uint8_t frev, crev; |
| struct radeon_pll *p1pll = &rdev->clock.p1pll; |
| struct radeon_pll *p2pll = &rdev->clock.p2pll; |
| struct radeon_pll *spll = &rdev->clock.spll; |
| struct radeon_pll *mpll = &rdev->clock.mpll; |
| uint16_t data_offset; |
| atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, |
| &crev, &data_offset); |
| firmware_info = |
| (union firmware_info *)(mode_info->atom_context->bios + |
| data_offset); |
| if (firmware_info) { |
| /* pixel clocks */ |
| p1pll->reference_freq = |
| le16_to_cpu(firmware_info->info.usReferenceClock); |
| p1pll->reference_div = 0; |
| p1pll->pll_out_min = |
| le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output); |
| p1pll->pll_out_max = |
| le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output); |
| if (p1pll->pll_out_min == 0) { |
| if (ASIC_IS_AVIVO(rdev)) |
| p1pll->pll_out_min = 64800; |
| else |
| p1pll->pll_out_min = 20000; |
| } |
| p1pll->pll_in_min = |
| le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input); |
| p1pll->pll_in_max = |
| le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input); |
| *p2pll = *p1pll; |
| /* system clock */ |
| spll->reference_freq = |
| le16_to_cpu(firmware_info->info.usReferenceClock); |
| spll->reference_div = 0; |
| spll->pll_out_min = |
| le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output); |
| spll->pll_out_max = |
| le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output); |
| /* ??? */ |
| if (spll->pll_out_min == 0) { |
| if (ASIC_IS_AVIVO(rdev)) |
| spll->pll_out_min = 64800; |
| else |
| spll->pll_out_min = 20000; |
| } |
| spll->pll_in_min = |
| le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input); |
| spll->pll_in_max = |
| le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input); |
| /* memory clock */ |
| mpll->reference_freq = |
| le16_to_cpu(firmware_info->info.usReferenceClock); |
| mpll->reference_div = 0; |
| mpll->pll_out_min = |
| le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output); |
| mpll->pll_out_max = |
| le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output); |
| /* ??? */ |
| if (mpll->pll_out_min == 0) { |
| if (ASIC_IS_AVIVO(rdev)) |
| mpll->pll_out_min = 64800; |
| else |
| mpll->pll_out_min = 20000; |
| } |
| mpll->pll_in_min = |
| le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input); |
| mpll->pll_in_max = |
| le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input); |
| rdev->clock.default_sclk = |
| le32_to_cpu(firmware_info->info.ulDefaultEngineClock); |
| rdev->clock.default_mclk = |
| le32_to_cpu(firmware_info->info.ulDefaultMemoryClock); |
| return true; |
| } |
| return false; |
| } |
| struct radeon_encoder_int_tmds *radeon_atombios_get_tmds_info(struct |
| radeon_encoder |
| *encoder) |
| { |
| struct drm_device *dev = encoder->base.dev; |
| struct radeon_device *rdev = dev->dev_private; |
| struct radeon_mode_info *mode_info = &rdev->mode_info; |
| int index = GetIndexIntoMasterTable(DATA, TMDS_Info); |
| uint16_t data_offset; |
| struct _ATOM_TMDS_INFO *tmds_info; |
| uint8_t frev, crev; |
| uint16_t maxfreq; |
| int i; |
| struct radeon_encoder_int_tmds *tmds = NULL; |
| atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, |
| &crev, &data_offset); |
| tmds_info = |
| (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios + |
| data_offset); |
| if (tmds_info) { |
| tmds = |
| kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL); |
| if (!tmds) |
| return NULL; |
| maxfreq = le16_to_cpu(tmds_info->usMaxFrequency); |
| for (i = 0; i < 4; i++) { |
| tmds->tmds_pll[i].freq = |
| le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency); |
| tmds->tmds_pll[i].value = |
| tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f; |
| tmds->tmds_pll[i].value |= |
| (tmds_info->asMiscInfo[i]. |
| ucPLL_VCO_Gain & 0x3f) << 6; |
| tmds->tmds_pll[i].value |= |
| (tmds_info->asMiscInfo[i]. |
| ucPLL_DutyCycle & 0xf) << 12; |
| tmds->tmds_pll[i].value |= |
| (tmds_info->asMiscInfo[i]. |
| ucPLL_VoltageSwing & 0xf) << 16; |
| DRM_DEBUG("TMDS PLL From ATOMBIOS %u %x\n", |
| tmds->tmds_pll[i].freq, |
| tmds->tmds_pll[i].value); |
| if (maxfreq == tmds->tmds_pll[i].freq) { |
| tmds->tmds_pll[i].freq = 0xffffffff; |
| break; |
| } |
| } |
| } |
| return tmds; |
| } |
| union lvds_info { |
| struct _ATOM_LVDS_INFO info; |
| struct _ATOM_LVDS_INFO_V12 info_12; |
| }; |
| struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct |
| radeon_encoder |
| *encoder) |
| { |
| struct drm_device *dev = encoder->base.dev; |
| struct radeon_device *rdev = dev->dev_private; |
| struct radeon_mode_info *mode_info = &rdev->mode_info; |
| int index = GetIndexIntoMasterTable(DATA, LVDS_Info); |
| uint16_t data_offset; |
| union lvds_info *lvds_info; |
| uint8_t frev, crev; |
| struct radeon_encoder_atom_dig *lvds = NULL; |
| atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, |
| &crev, &data_offset); |
| lvds_info = |
| (union lvds_info *)(mode_info->atom_context->bios + data_offset); |
| if (lvds_info) { |
| lvds = |
| kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL); |
| if (!lvds) |
| return NULL; |
| lvds->native_mode.dotclock = |
| le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10; |
| lvds->native_mode.panel_xres = |
| le16_to_cpu(lvds_info->info.sLCDTiming.usHActive); |
| lvds->native_mode.panel_yres = |
| le16_to_cpu(lvds_info->info.sLCDTiming.usVActive); |
| lvds->native_mode.hblank = |
| le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time); |
| lvds->native_mode.hoverplus = |
| le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset); |
| lvds->native_mode.hsync_width = |
| le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth); |
| lvds->native_mode.vblank = |
| le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time); |
| lvds->native_mode.voverplus = |
| le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset); |
| lvds->native_mode.vsync_width = |
| le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth); |
| lvds->panel_pwr_delay = |
| le16_to_cpu(lvds_info->info.usOffDelayInMs); |
| lvds->lvds_misc = lvds_info->info.ucLVDS_Misc; |
| encoder->native_mode = lvds->native_mode; |
| } |
| return lvds; |
| } |
| struct radeon_encoder_primary_dac * |
| radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder) |
| { |
| struct drm_device *dev = encoder->base.dev; |
| struct radeon_device *rdev = dev->dev_private; |
| struct radeon_mode_info *mode_info = &rdev->mode_info; |
| int index = GetIndexIntoMasterTable(DATA, CompassionateData); |
| uint16_t data_offset; |
| struct _COMPASSIONATE_DATA *dac_info; |
| uint8_t frev, crev; |
| uint8_t bg, dac; |
| struct radeon_encoder_primary_dac *p_dac = NULL; |
| atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset); |
| dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset); |
| if (dac_info) { |
| p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL); |
| if (!p_dac) |
| return NULL; |
| bg = dac_info->ucDAC1_BG_Adjustment; |
| dac = dac_info->ucDAC1_DAC_Adjustment; |
| p_dac->ps2_pdac_adj = (bg << 8) | (dac); |
| } |
| return p_dac; |
| } |
| struct radeon_encoder_tv_dac * |
| radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder) |
| { |
| struct drm_device *dev = encoder->base.dev; |
| struct radeon_device *rdev = dev->dev_private; |
| struct radeon_mode_info *mode_info = &rdev->mode_info; |
| int index = GetIndexIntoMasterTable(DATA, CompassionateData); |
| uint16_t data_offset; |
| struct _COMPASSIONATE_DATA *dac_info; |
| uint8_t frev, crev; |
| uint8_t bg, dac; |
| struct radeon_encoder_tv_dac *tv_dac = NULL; |
| atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset); |
| dac_info = (struct _COMPASSIONATE_DATA *)(mode_info->atom_context->bios + data_offset); |
| if (dac_info) { |
| tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL); |
| if (!tv_dac) |
| return NULL; |
| bg = dac_info->ucDAC2_CRT2_BG_Adjustment; |
| dac = dac_info->ucDAC2_CRT2_DAC_Adjustment; |
| tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20); |
| bg = dac_info->ucDAC2_PAL_BG_Adjustment; |
| dac = dac_info->ucDAC2_PAL_DAC_Adjustment; |
| tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); |
| bg = dac_info->ucDAC2_NTSC_BG_Adjustment; |
| dac = dac_info->ucDAC2_NTSC_DAC_Adjustment; |
| tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); |
| } |
| return tv_dac; |
| } |
| void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable) |
| { |
| DYNAMIC_CLOCK_GATING_PS_ALLOCATION args; |
| int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating); |
| args.ucEnable = enable; |
| atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| } |
| void radeon_atom_static_pwrmgt_setup(struct radeon_device *rdev, int enable) |
| { |
| ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION args; |
| int index = GetIndexIntoMasterTable(COMMAND, EnableASIC_StaticPwrMgt); |
| args.ucEnable = enable; |
| atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| } |
| void radeon_atom_set_engine_clock(struct radeon_device *rdev, |
| uint32_t eng_clock) |
| { |
| SET_ENGINE_CLOCK_PS_ALLOCATION args; |
| int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock); |
| args.ulTargetEngineClock = eng_clock; /* 10 khz */ |
| atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| } |
| void radeon_atom_set_memory_clock(struct radeon_device *rdev, |
| uint32_t mem_clock) |
| { |
| SET_MEMORY_CLOCK_PS_ALLOCATION args; |
| int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock); |
| if (rdev->flags & RADEON_IS_IGP) |
| return; |
| args.ulTargetMemoryClock = mem_clock; /* 10 khz */ |
| atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| } |
| void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev) |
| { |
| struct radeon_device *rdev = dev->dev_private; |
| uint32_t bios_2_scratch, bios_6_scratch; |
| dbgprintf("%s\n\r",__FUNCTION__); |
| if (rdev->family >= CHIP_R600) { |
| bios_2_scratch = RREG32(R600_BIOS_0_SCRATCH); |
| bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); |
| } else { |
| bios_2_scratch = RREG32(RADEON_BIOS_0_SCRATCH); |
| bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); |
| } |
| /* let the bios control the backlight */ |
| bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE; |
| /* tell the bios not to handle mode switching */ |
| bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE); |
| if (rdev->family >= CHIP_R600) { |
| WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); |
| WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); |
| } else { |
| WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); |
| WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); |
| } |
| } |
| void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock) |
| { |
| struct drm_device *dev = encoder->dev; |
| struct radeon_device *rdev = dev->dev_private; |
| uint32_t bios_6_scratch; |
| if (rdev->family >= CHIP_R600) |
| bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); |
| else |
| bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); |
| if (lock) |
| bios_6_scratch |= ATOM_S6_CRITICAL_STATE; |
| else |
| bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE; |
| if (rdev->family >= CHIP_R600) |
| WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); |
| else |
| WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); |
| } |
| /* at some point we may want to break this out into individual functions */ |
| void |
| radeon_atombios_connected_scratch_regs(struct drm_connector *connector, |
| struct drm_encoder *encoder, |
| bool connected) |
| { |
| struct drm_device *dev = connector->dev; |
| struct radeon_device *rdev = dev->dev_private; |
| struct radeon_connector *radeon_connector = |
| to_radeon_connector(connector); |
| struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch; |
| if (rdev->family >= CHIP_R600) { |
| bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH); |
| bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH); |
| bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH); |
| } else { |
| bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); |
| bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH); |
| bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); |
| } |
| if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) && |
| (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) { |
| if (connected) { |
| DRM_DEBUG("TV1 connected\n"); |
| bios_3_scratch |= ATOM_S3_TV1_ACTIVE; |
| bios_6_scratch |= ATOM_S6_ACC_REQ_TV1; |
| } else { |
| DRM_DEBUG("TV1 disconnected\n"); |
| bios_0_scratch &= ~ATOM_S0_TV1_MASK; |
| bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE; |
| bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1; |
| } |
| } |
| if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) && |
| (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) { |
| if (connected) { |
| DRM_DEBUG("CV connected\n"); |
| bios_3_scratch |= ATOM_S3_CV_ACTIVE; |
| bios_6_scratch |= ATOM_S6_ACC_REQ_CV; |
| } else { |
| DRM_DEBUG("CV disconnected\n"); |
| bios_0_scratch &= ~ATOM_S0_CV_MASK; |
| bios_3_scratch &= ~ATOM_S3_CV_ACTIVE; |
| bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV; |
| } |
| } |
| if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) && |
| (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) { |
| if (connected) { |
| DRM_DEBUG("LCD1 connected\n"); |
| bios_0_scratch |= ATOM_S0_LCD1; |
| bios_3_scratch |= ATOM_S3_LCD1_ACTIVE; |
| bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1; |
| } else { |
| DRM_DEBUG("LCD1 disconnected\n"); |
| bios_0_scratch &= ~ATOM_S0_LCD1; |
| bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE; |
| bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1; |
| } |
| } |
| if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) && |
| (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) { |
| if (connected) { |
| DRM_DEBUG("CRT1 connected\n"); |
| bios_0_scratch |= ATOM_S0_CRT1_COLOR; |
| bios_3_scratch |= ATOM_S3_CRT1_ACTIVE; |
| bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1; |
| } else { |
| DRM_DEBUG("CRT1 disconnected\n"); |
| bios_0_scratch &= ~ATOM_S0_CRT1_MASK; |
| bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE; |
| bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1; |
| } |
| } |
| if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) && |
| (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) { |
| if (connected) { |
| DRM_DEBUG("CRT2 connected\n"); |
| bios_0_scratch |= ATOM_S0_CRT2_COLOR; |
| bios_3_scratch |= ATOM_S3_CRT2_ACTIVE; |
| bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2; |
| } else { |
| DRM_DEBUG("CRT2 disconnected\n"); |
| bios_0_scratch &= ~ATOM_S0_CRT2_MASK; |
| bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE; |
| bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2; |
| } |
| } |
| if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) && |
| (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) { |
| if (connected) { |
| DRM_DEBUG("DFP1 connected\n"); |
| bios_0_scratch |= ATOM_S0_DFP1; |
| bios_3_scratch |= ATOM_S3_DFP1_ACTIVE; |
| bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1; |
| } else { |
| DRM_DEBUG("DFP1 disconnected\n"); |
| bios_0_scratch &= ~ATOM_S0_DFP1; |
| bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE; |
| bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1; |
| } |
| } |
| if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) && |
| (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) { |
| if (connected) { |
| DRM_DEBUG("DFP2 connected\n"); |
| bios_0_scratch |= ATOM_S0_DFP2; |
| bios_3_scratch |= ATOM_S3_DFP2_ACTIVE; |
| bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2; |
| } else { |
| DRM_DEBUG("DFP2 disconnected\n"); |
| bios_0_scratch &= ~ATOM_S0_DFP2; |
| bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE; |
| bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2; |
| } |
| } |
| if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) && |
| (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) { |
| if (connected) { |
| DRM_DEBUG("DFP3 connected\n"); |
| bios_0_scratch |= ATOM_S0_DFP3; |
| bios_3_scratch |= ATOM_S3_DFP3_ACTIVE; |
| bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3; |
| } else { |
| DRM_DEBUG("DFP3 disconnected\n"); |
| bios_0_scratch &= ~ATOM_S0_DFP3; |
| bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE; |
| bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3; |
| } |
| } |
| if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) && |
| (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) { |
| if (connected) { |
| DRM_DEBUG("DFP4 connected\n"); |
| bios_0_scratch |= ATOM_S0_DFP4; |
| bios_3_scratch |= ATOM_S3_DFP4_ACTIVE; |
| bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4; |
| } else { |
| DRM_DEBUG("DFP4 disconnected\n"); |
| bios_0_scratch &= ~ATOM_S0_DFP4; |
| bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE; |
| bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4; |
| } |
| } |
| if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) && |
| (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) { |
| if (connected) { |
| DRM_DEBUG("DFP5 connected\n"); |
| bios_0_scratch |= ATOM_S0_DFP5; |
| bios_3_scratch |= ATOM_S3_DFP5_ACTIVE; |
| bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5; |
| } else { |
| DRM_DEBUG("DFP5 disconnected\n"); |
| bios_0_scratch &= ~ATOM_S0_DFP5; |
| bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE; |
| bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5; |
| } |
| } |
| if (rdev->family >= CHIP_R600) { |
| WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch); |
| WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch); |
| WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch); |
| } else { |
| WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch); |
| WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch); |
| WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); |
| } |
| } |
| void |
| radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc) |
| { |
| struct drm_device *dev = encoder->dev; |
| struct radeon_device *rdev = dev->dev_private; |
| struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| uint32_t bios_3_scratch; |
| if (rdev->family >= CHIP_R600) |
| bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH); |
| else |
| bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH); |
| if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { |
| bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE; |
| bios_3_scratch |= (crtc << 18); |
| } |
| if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) { |
| bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE; |
| bios_3_scratch |= (crtc << 24); |
| } |
| if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { |
| bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE; |
| bios_3_scratch |= (crtc << 16); |
| } |
| if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { |
| bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE; |
| bios_3_scratch |= (crtc << 20); |
| } |
| if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { |
| bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE; |
| bios_3_scratch |= (crtc << 17); |
| } |
| if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) { |
| bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE; |
| bios_3_scratch |= (crtc << 19); |
| } |
| if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) { |
| bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE; |
| bios_3_scratch |= (crtc << 23); |
| } |
| if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) { |
| bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE; |
| bios_3_scratch |= (crtc << 25); |
| } |
| if (rdev->family >= CHIP_R600) |
| WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch); |
| else |
| WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch); |
| } |
| void |
| radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on) |
| { |
| struct drm_device *dev = encoder->dev; |
| struct radeon_device *rdev = dev->dev_private; |
| struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| uint32_t bios_2_scratch; |
| if (rdev->family >= CHIP_R600) |
| bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); |
| else |
| bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH); |
| if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { |
| if (on) |
| bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE; |
| else |
| bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE; |
| } |
| if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) { |
| if (on) |
| bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE; |
| else |
| bios_2_scratch |= ATOM_S2_CV_DPMS_STATE; |
| } |
| if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { |
| if (on) |
| bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE; |
| else |
| bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE; |
| } |
| if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { |
| if (on) |
| bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE; |
| else |
| bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE; |
| } |
| if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { |
| if (on) |
| bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE; |
| else |
| bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE; |
| } |
| if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) { |
| if (on) |
| bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE; |
| else |
| bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE; |
| } |
| if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) { |
| if (on) |
| bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE; |
| else |
| bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE; |
| } |
| if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) { |
| if (on) |
| bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE; |
| else |
| bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE; |
| } |
| if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) { |
| if (on) |
| bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE; |
| else |
| bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE; |
| } |
| if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) { |
| if (on) |
| bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE; |
| else |
| bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE; |
| } |
| if (rdev->family >= CHIP_R600) |
| WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); |
| else |
| WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); |
| } |
| /drivers/video/drm/radeon/radeon_bios.c |
|---|
| 0,0 → 1,397 |
| /* |
| * Copyright 2008 Advanced Micro Devices, Inc. |
| * Copyright 2008 Red Hat Inc. |
| * Copyright 2009 Jerome Glisse. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice shall be included in |
| * all copies or substantial portions of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| * OTHER DEALINGS IN THE SOFTWARE. |
| * |
| * Authors: Dave Airlie |
| * Alex Deucher |
| * Jerome Glisse |
| */ |
| //#include "drmP.h" |
| #include "radeon_reg.h" |
| #include "radeon.h" |
| #include "atom.h" |
| /* |
| * BIOS. |
| */ |
| static bool radeon_read_bios(struct radeon_device *rdev) |
| { |
| uint8_t *bios; |
| size_t size; |
| rdev->bios = NULL; |
| bios = pci_map_rom(rdev->pdev, &size); |
| if (!bios) { |
| return false; |
| } |
| if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { |
| // pci_unmap_rom(rdev->pdev, bios); |
| return false; |
| } |
| rdev->bios = malloc(size); |
| if (rdev->bios == NULL) { |
| // pci_unmap_rom(rdev->pdev, bios); |
| return false; |
| } |
| memcpy(rdev->bios, bios, size); |
| // pci_unmap_rom(rdev->pdev, bios); |
| return true; |
| } |
| #if 0 |
| static bool r700_read_disabled_bios(struct radeon_device *rdev) |
| { |
| uint32_t viph_control; |
| uint32_t bus_cntl; |
| uint32_t d1vga_control; |
| uint32_t d2vga_control; |
| uint32_t vga_render_control; |
| uint32_t rom_cntl; |
| uint32_t cg_spll_func_cntl = 0; |
| uint32_t cg_spll_status; |
| bool r; |
| viph_control = RREG32(RADEON_VIPH_CONTROL); |
| bus_cntl = RREG32(RADEON_BUS_CNTL); |
| d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); |
| d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); |
| vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); |
| rom_cntl = RREG32(R600_ROM_CNTL); |
| /* disable VIP */ |
| WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); |
| /* enable the rom */ |
| WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); |
| /* Disable VGA mode */ |
| WREG32(AVIVO_D1VGA_CONTROL, |
| (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | |
| AVIVO_DVGA_CONTROL_TIMING_SELECT))); |
| WREG32(AVIVO_D2VGA_CONTROL, |
| (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | |
| AVIVO_DVGA_CONTROL_TIMING_SELECT))); |
| WREG32(AVIVO_VGA_RENDER_CONTROL, |
| (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); |
| if (rdev->family == CHIP_RV730) { |
| cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL); |
| /* enable bypass mode */ |
| WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl | |
| R600_SPLL_BYPASS_EN)); |
| /* wait for SPLL_CHG_STATUS to change to 1 */ |
| cg_spll_status = 0; |
| while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) |
| cg_spll_status = RREG32(R600_CG_SPLL_STATUS); |
| WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE)); |
| } else |
| WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE)); |
| r = radeon_read_bios(rdev); |
| /* restore regs */ |
| if (rdev->family == CHIP_RV730) { |
| WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl); |
| /* wait for SPLL_CHG_STATUS to change to 1 */ |
| cg_spll_status = 0; |
| while (!(cg_spll_status & R600_SPLL_CHG_STATUS)) |
| cg_spll_status = RREG32(R600_CG_SPLL_STATUS); |
| } |
| WREG32(RADEON_VIPH_CONTROL, viph_control); |
| WREG32(RADEON_BUS_CNTL, bus_cntl); |
| WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); |
| WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); |
| WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); |
| WREG32(R600_ROM_CNTL, rom_cntl); |
| return r; |
| } |
| static bool r600_read_disabled_bios(struct radeon_device *rdev) |
| { |
| uint32_t viph_control; |
| uint32_t bus_cntl; |
| uint32_t d1vga_control; |
| uint32_t d2vga_control; |
| uint32_t vga_render_control; |
| uint32_t rom_cntl; |
| uint32_t general_pwrmgt; |
| uint32_t low_vid_lower_gpio_cntl; |
| uint32_t medium_vid_lower_gpio_cntl; |
| uint32_t high_vid_lower_gpio_cntl; |
| uint32_t ctxsw_vid_lower_gpio_cntl; |
| uint32_t lower_gpio_enable; |
| bool r; |
| viph_control = RREG32(RADEON_VIPH_CONTROL); |
| bus_cntl = RREG32(RADEON_BUS_CNTL); |
| d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); |
| d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); |
| vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); |
| rom_cntl = RREG32(R600_ROM_CNTL); |
| general_pwrmgt = RREG32(R600_GENERAL_PWRMGT); |
| low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL); |
| medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL); |
| high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL); |
| ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL); |
| lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE); |
| /* disable VIP */ |
| WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); |
| /* enable the rom */ |
| WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); |
| /* Disable VGA mode */ |
| WREG32(AVIVO_D1VGA_CONTROL, |
| (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | |
| AVIVO_DVGA_CONTROL_TIMING_SELECT))); |
| WREG32(AVIVO_D2VGA_CONTROL, |
| (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | |
| AVIVO_DVGA_CONTROL_TIMING_SELECT))); |
| WREG32(AVIVO_VGA_RENDER_CONTROL, |
| (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); |
| WREG32(R600_ROM_CNTL, |
| ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) | |
| (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) | |
| R600_SCK_OVERWRITE)); |
| WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS)); |
| WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, |
| (low_vid_lower_gpio_cntl & ~0x400)); |
| WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, |
| (medium_vid_lower_gpio_cntl & ~0x400)); |
| WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, |
| (high_vid_lower_gpio_cntl & ~0x400)); |
| WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, |
| (ctxsw_vid_lower_gpio_cntl & ~0x400)); |
| WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400)); |
| r = radeon_read_bios(rdev); |
| /* restore regs */ |
| WREG32(RADEON_VIPH_CONTROL, viph_control); |
| WREG32(RADEON_BUS_CNTL, bus_cntl); |
| WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); |
| WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); |
| WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); |
| WREG32(R600_ROM_CNTL, rom_cntl); |
| WREG32(R600_GENERAL_PWRMGT, general_pwrmgt); |
| WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl); |
| WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl); |
| WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl); |
| WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl); |
| WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable); |
| return r; |
| } |
| static bool avivo_read_disabled_bios(struct radeon_device *rdev) |
| { |
| uint32_t seprom_cntl1; |
| uint32_t viph_control; |
| uint32_t bus_cntl; |
| uint32_t d1vga_control; |
| uint32_t d2vga_control; |
| uint32_t vga_render_control; |
| uint32_t gpiopad_a; |
| uint32_t gpiopad_en; |
| uint32_t gpiopad_mask; |
| bool r; |
| seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); |
| viph_control = RREG32(RADEON_VIPH_CONTROL); |
| bus_cntl = RREG32(RADEON_BUS_CNTL); |
| d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); |
| d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); |
| vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL); |
| gpiopad_a = RREG32(RADEON_GPIOPAD_A); |
| gpiopad_en = RREG32(RADEON_GPIOPAD_EN); |
| gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK); |
| WREG32(RADEON_SEPROM_CNTL1, |
| ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | |
| (0xc << RADEON_SCK_PRESCALE_SHIFT))); |
| WREG32(RADEON_GPIOPAD_A, 0); |
| WREG32(RADEON_GPIOPAD_EN, 0); |
| WREG32(RADEON_GPIOPAD_MASK, 0); |
| /* disable VIP */ |
| WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); |
| /* enable the rom */ |
| WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); |
| /* Disable VGA mode */ |
| WREG32(AVIVO_D1VGA_CONTROL, |
| (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | |
| AVIVO_DVGA_CONTROL_TIMING_SELECT))); |
| WREG32(AVIVO_D2VGA_CONTROL, |
| (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | |
| AVIVO_DVGA_CONTROL_TIMING_SELECT))); |
| WREG32(AVIVO_VGA_RENDER_CONTROL, |
| (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK)); |
| r = radeon_read_bios(rdev); |
| /* restore regs */ |
| WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); |
| WREG32(RADEON_VIPH_CONTROL, viph_control); |
| WREG32(RADEON_BUS_CNTL, bus_cntl); |
| WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); |
| WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); |
| WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control); |
| WREG32(RADEON_GPIOPAD_A, gpiopad_a); |
| WREG32(RADEON_GPIOPAD_EN, gpiopad_en); |
| WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask); |
| return r; |
| } |
| static bool legacy_read_disabled_bios(struct radeon_device *rdev) |
| { |
| uint32_t seprom_cntl1; |
| uint32_t viph_control; |
| uint32_t bus_cntl; |
| uint32_t crtc_gen_cntl; |
| uint32_t crtc2_gen_cntl; |
| uint32_t crtc_ext_cntl; |
| uint32_t fp2_gen_cntl; |
| bool r; |
| seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1); |
| viph_control = RREG32(RADEON_VIPH_CONTROL); |
| bus_cntl = RREG32(RADEON_BUS_CNTL); |
| crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL); |
| crtc2_gen_cntl = 0; |
| crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); |
| fp2_gen_cntl = 0; |
| if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) { |
| fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); |
| } |
| if (!(rdev->flags & RADEON_SINGLE_CRTC)) { |
| crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); |
| } |
| WREG32(RADEON_SEPROM_CNTL1, |
| ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) | |
| (0xc << RADEON_SCK_PRESCALE_SHIFT))); |
| /* disable VIP */ |
| WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN)); |
| /* enable the rom */ |
| WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM)); |
| /* Turn off mem requests and CRTC for both controllers */ |
| WREG32(RADEON_CRTC_GEN_CNTL, |
| ((crtc_gen_cntl & ~RADEON_CRTC_EN) | |
| (RADEON_CRTC_DISP_REQ_EN_B | |
| RADEON_CRTC_EXT_DISP_EN))); |
| if (!(rdev->flags & RADEON_SINGLE_CRTC)) { |
| WREG32(RADEON_CRTC2_GEN_CNTL, |
| ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) | |
| RADEON_CRTC2_DISP_REQ_EN_B)); |
| } |
| /* Turn off CRTC */ |
| WREG32(RADEON_CRTC_EXT_CNTL, |
| ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) | |
| (RADEON_CRTC_SYNC_TRISTAT | |
| RADEON_CRTC_DISPLAY_DIS))); |
| if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) { |
| WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON)); |
| } |
| r = radeon_read_bios(rdev); |
| /* restore regs */ |
| WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1); |
| WREG32(RADEON_VIPH_CONTROL, viph_control); |
| WREG32(RADEON_BUS_CNTL, bus_cntl); |
| WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl); |
| if (!(rdev->flags & RADEON_SINGLE_CRTC)) { |
| WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); |
| } |
| WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); |
| if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) { |
| WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); |
| } |
| return r; |
| } |
| static bool radeon_read_disabled_bios(struct radeon_device *rdev) |
| { |
| if (rdev->family >= CHIP_RV770) |
| return r700_read_disabled_bios(rdev); |
| else if (rdev->family >= CHIP_R600) |
| return r600_read_disabled_bios(rdev); |
| else if (rdev->family >= CHIP_RS600) |
| return avivo_read_disabled_bios(rdev); |
| else |
| return legacy_read_disabled_bios(rdev); |
| } |
| #endif |
| bool radeon_get_bios(struct radeon_device *rdev) |
| { |
| bool r; |
| uint16_t tmp; |
| dbgprintf("%s\n\r",__FUNCTION__); |
| r = radeon_read_bios(rdev); |
| // if (r == false) { |
| // r = radeon_read_disabled_bios(rdev); |
| // } |
| if (r == false || rdev->bios == NULL) { |
| DRM_ERROR("Unable to locate a BIOS ROM\n"); |
| rdev->bios = NULL; |
| return false; |
| } |
| if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) { |
| goto free_bios; |
| } |
| rdev->bios_header_start = RBIOS16(0x48); |
| if (!rdev->bios_header_start) { |
| goto free_bios; |
| } |
| tmp = rdev->bios_header_start + 4; |
| if (!memcmp(rdev->bios + tmp, "ATOM", 4) || |
| !memcmp(rdev->bios + tmp, "MOTA", 4)) { |
| rdev->is_atom_bios = true; |
| } else { |
| rdev->is_atom_bios = false; |
| } |
| dbgprintf("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM"); |
| return true; |
| free_bios: |
| kfree(rdev->bios); |
| rdev->bios = NULL; |
| return false; |
| } |
| /drivers/video/drm/radeon/radeon_clocks.c |
|---|
| 0,0 → 1,833 |
| /* |
| * Copyright 2008 Advanced Micro Devices, Inc. |
| * Copyright 2008 Red Hat Inc. |
| * Copyright 2009 Jerome Glisse. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice shall be included in |
| * all copies or substantial portions of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| * OTHER DEALINGS IN THE SOFTWARE. |
| * |
| * Authors: Dave Airlie |
| * Alex Deucher |
| * Jerome Glisse |
| */ |
| //#include "drmP.h" |
| #include "radeon_drm.h" |
| #include "radeon_reg.h" |
| #include "radeon.h" |
| #include "atom.h" |
| /* 10 khz */ |
| static uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev) |
| { |
| struct radeon_pll *spll = &rdev->clock.spll; |
| uint32_t fb_div, ref_div, post_div, sclk; |
| fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV); |
| fb_div = (fb_div >> RADEON_SPLL_FB_DIV_SHIFT) & RADEON_SPLL_FB_DIV_MASK; |
| fb_div <<= 1; |
| fb_div *= spll->reference_freq; |
| ref_div = |
| RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK; |
| sclk = fb_div / ref_div; |
| post_div = RREG32_PLL(RADEON_SCLK_CNTL) & RADEON_SCLK_SRC_SEL_MASK; |
| if (post_div == 2) |
| sclk >>= 1; |
| else if (post_div == 3) |
| sclk >>= 2; |
| else if (post_div == 4) |
| sclk >>= 4; |
| return sclk; |
| } |
| /* 10 khz */ |
| static uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev) |
| { |
| struct radeon_pll *mpll = &rdev->clock.mpll; |
| uint32_t fb_div, ref_div, post_div, mclk; |
| fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV); |
| fb_div = (fb_div >> RADEON_MPLL_FB_DIV_SHIFT) & RADEON_MPLL_FB_DIV_MASK; |
| fb_div <<= 1; |
| fb_div *= mpll->reference_freq; |
| ref_div = |
| RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & RADEON_M_SPLL_REF_DIV_MASK; |
| mclk = fb_div / ref_div; |
| post_div = RREG32_PLL(RADEON_MCLK_CNTL) & 0x7; |
| if (post_div == 2) |
| mclk >>= 1; |
| else if (post_div == 3) |
| mclk >>= 2; |
| else if (post_div == 4) |
| mclk >>= 4; |
| return mclk; |
| } |
| void radeon_get_clock_info(struct drm_device *dev) |
| { |
| struct radeon_device *rdev = dev->dev_private; |
| struct radeon_pll *p1pll = &rdev->clock.p1pll; |
| struct radeon_pll *p2pll = &rdev->clock.p2pll; |
| struct radeon_pll *spll = &rdev->clock.spll; |
| struct radeon_pll *mpll = &rdev->clock.mpll; |
| int ret; |
| if (rdev->is_atom_bios) |
| ret = radeon_atom_get_clock_info(dev); |
| // else |
| // ret = radeon_combios_get_clock_info(dev); |
| if (ret) { |
| if (p1pll->reference_div < 2) |
| p1pll->reference_div = 12; |
| if (p2pll->reference_div < 2) |
| p2pll->reference_div = 12; |
| if (spll->reference_div < 2) |
| spll->reference_div = |
| RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & |
| RADEON_M_SPLL_REF_DIV_MASK; |
| if (mpll->reference_div < 2) |
| mpll->reference_div = spll->reference_div; |
| } else { |
| if (ASIC_IS_AVIVO(rdev)) { |
| /* TODO FALLBACK */ |
| } else { |
| DRM_INFO("Using generic clock info\n"); |
| if (rdev->flags & RADEON_IS_IGP) { |
| p1pll->reference_freq = 1432; |
| p2pll->reference_freq = 1432; |
| spll->reference_freq = 1432; |
| mpll->reference_freq = 1432; |
| } else { |
| p1pll->reference_freq = 2700; |
| p2pll->reference_freq = 2700; |
| spll->reference_freq = 2700; |
| mpll->reference_freq = 2700; |
| } |
| p1pll->reference_div = |
| RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff; |
| if (p1pll->reference_div < 2) |
| p1pll->reference_div = 12; |
| p2pll->reference_div = p1pll->reference_div; |
| if (rdev->family >= CHIP_R420) { |
| p1pll->pll_in_min = 100; |
| p1pll->pll_in_max = 1350; |
| p1pll->pll_out_min = 20000; |
| p1pll->pll_out_max = 50000; |
| p2pll->pll_in_min = 100; |
| p2pll->pll_in_max = 1350; |
| p2pll->pll_out_min = 20000; |
| p2pll->pll_out_max = 50000; |
| } else { |
| p1pll->pll_in_min = 40; |
| p1pll->pll_in_max = 500; |
| p1pll->pll_out_min = 12500; |
| p1pll->pll_out_max = 35000; |
| p2pll->pll_in_min = 40; |
| p2pll->pll_in_max = 500; |
| p2pll->pll_out_min = 12500; |
| p2pll->pll_out_max = 35000; |
| } |
| spll->reference_div = |
| RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & |
| RADEON_M_SPLL_REF_DIV_MASK; |
| mpll->reference_div = spll->reference_div; |
| rdev->clock.default_sclk = |
| radeon_legacy_get_engine_clock(rdev); |
| rdev->clock.default_mclk = |
| radeon_legacy_get_memory_clock(rdev); |
| } |
| } |
| /* pixel clocks */ |
| if (ASIC_IS_AVIVO(rdev)) { |
| p1pll->min_post_div = 2; |
| p1pll->max_post_div = 0x7f; |
| p1pll->min_frac_feedback_div = 0; |
| p1pll->max_frac_feedback_div = 9; |
| p2pll->min_post_div = 2; |
| p2pll->max_post_div = 0x7f; |
| p2pll->min_frac_feedback_div = 0; |
| p2pll->max_frac_feedback_div = 9; |
| } else { |
| p1pll->min_post_div = 1; |
| p1pll->max_post_div = 16; |
| p1pll->min_frac_feedback_div = 0; |
| p1pll->max_frac_feedback_div = 0; |
| p2pll->min_post_div = 1; |
| p2pll->max_post_div = 12; |
| p2pll->min_frac_feedback_div = 0; |
| p2pll->max_frac_feedback_div = 0; |
| } |
| p1pll->min_ref_div = 2; |
| p1pll->max_ref_div = 0x3ff; |
| p1pll->min_feedback_div = 4; |
| p1pll->max_feedback_div = 0x7ff; |
| p1pll->best_vco = 0; |
| p2pll->min_ref_div = 2; |
| p2pll->max_ref_div = 0x3ff; |
| p2pll->min_feedback_div = 4; |
| p2pll->max_feedback_div = 0x7ff; |
| p2pll->best_vco = 0; |
| /* system clock */ |
| spll->min_post_div = 1; |
| spll->max_post_div = 1; |
| spll->min_ref_div = 2; |
| spll->max_ref_div = 0xff; |
| spll->min_feedback_div = 4; |
| spll->max_feedback_div = 0xff; |
| spll->best_vco = 0; |
| /* memory clock */ |
| mpll->min_post_div = 1; |
| mpll->max_post_div = 1; |
| mpll->min_ref_div = 2; |
| mpll->max_ref_div = 0xff; |
| mpll->min_feedback_div = 4; |
| mpll->max_feedback_div = 0xff; |
| mpll->best_vco = 0; |
| } |
| /* 10 khz */ |
| static uint32_t calc_eng_mem_clock(struct radeon_device *rdev, |
| uint32_t req_clock, |
| int *fb_div, int *post_div) |
| { |
| struct radeon_pll *spll = &rdev->clock.spll; |
| int ref_div = spll->reference_div; |
| if (!ref_div) |
| ref_div = |
| RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV) & |
| RADEON_M_SPLL_REF_DIV_MASK; |
| if (req_clock < 15000) { |
| *post_div = 8; |
| req_clock *= 8; |
| } else if (req_clock < 30000) { |
| *post_div = 4; |
| req_clock *= 4; |
| } else if (req_clock < 60000) { |
| *post_div = 2; |
| req_clock *= 2; |
| } else |
| *post_div = 1; |
| req_clock *= ref_div; |
| req_clock += spll->reference_freq; |
| req_clock /= (2 * spll->reference_freq); |
| *fb_div = req_clock & 0xff; |
| req_clock = (req_clock & 0xffff) << 1; |
| req_clock *= spll->reference_freq; |
| req_clock /= ref_div; |
| req_clock /= *post_div; |
| return req_clock; |
| } |
| /* 10 khz */ |
| void radeon_legacy_set_engine_clock(struct radeon_device *rdev, |
| uint32_t eng_clock) |
| { |
| uint32_t tmp; |
| int fb_div, post_div; |
| /* XXX: wait for idle */ |
| eng_clock = calc_eng_mem_clock(rdev, eng_clock, &fb_div, &post_div); |
| tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL); |
| tmp &= ~RADEON_DONT_USE_XTALIN; |
| WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp); |
| tmp = RREG32_PLL(RADEON_SCLK_CNTL); |
| tmp &= ~RADEON_SCLK_SRC_SEL_MASK; |
| WREG32_PLL(RADEON_SCLK_CNTL, tmp); |
| udelay(10); |
| tmp = RREG32_PLL(RADEON_SPLL_CNTL); |
| tmp |= RADEON_SPLL_SLEEP; |
| WREG32_PLL(RADEON_SPLL_CNTL, tmp); |
| udelay(2); |
| tmp = RREG32_PLL(RADEON_SPLL_CNTL); |
| tmp |= RADEON_SPLL_RESET; |
| WREG32_PLL(RADEON_SPLL_CNTL, tmp); |
| udelay(200); |
| tmp = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV); |
| tmp &= ~(RADEON_SPLL_FB_DIV_MASK << RADEON_SPLL_FB_DIV_SHIFT); |
| tmp |= (fb_div & RADEON_SPLL_FB_DIV_MASK) << RADEON_SPLL_FB_DIV_SHIFT; |
| WREG32_PLL(RADEON_M_SPLL_REF_FB_DIV, tmp); |
| /* XXX: verify on different asics */ |
| tmp = RREG32_PLL(RADEON_SPLL_CNTL); |
| tmp &= ~RADEON_SPLL_PVG_MASK; |
| if ((eng_clock * post_div) >= 90000) |
| tmp |= (0x7 << RADEON_SPLL_PVG_SHIFT); |
| else |
| tmp |= (0x4 << RADEON_SPLL_PVG_SHIFT); |
| WREG32_PLL(RADEON_SPLL_CNTL, tmp); |
| tmp = RREG32_PLL(RADEON_SPLL_CNTL); |
| tmp &= ~RADEON_SPLL_SLEEP; |
| WREG32_PLL(RADEON_SPLL_CNTL, tmp); |
| udelay(2); |
| tmp = RREG32_PLL(RADEON_SPLL_CNTL); |
| tmp &= ~RADEON_SPLL_RESET; |
| WREG32_PLL(RADEON_SPLL_CNTL, tmp); |
| udelay(200); |
| tmp = RREG32_PLL(RADEON_SCLK_CNTL); |
| tmp &= ~RADEON_SCLK_SRC_SEL_MASK; |
| switch (post_div) { |
| case 1: |
| default: |
| tmp |= 1; |
| break; |
| case 2: |
| tmp |= 2; |
| break; |
| case 4: |
| tmp |= 3; |
| break; |
| case 8: |
| tmp |= 4; |
| break; |
| } |
| WREG32_PLL(RADEON_SCLK_CNTL, tmp); |
| udelay(20); |
| tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL); |
| tmp |= RADEON_DONT_USE_XTALIN; |
| WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp); |
| udelay(10); |
| } |
| void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable) |
| { |
| uint32_t tmp; |
| if (enable) { |
| if (rdev->flags & RADEON_SINGLE_CRTC) { |
| tmp = RREG32_PLL(RADEON_SCLK_CNTL); |
| if ((RREG32(RADEON_CONFIG_CNTL) & |
| RADEON_CFG_ATI_REV_ID_MASK) > |
| RADEON_CFG_ATI_REV_A13) { |
| tmp &= |
| ~(RADEON_SCLK_FORCE_CP | |
| RADEON_SCLK_FORCE_RB); |
| } |
| tmp &= |
| ~(RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1 | |
| RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_SE | |
| RADEON_SCLK_FORCE_IDCT | RADEON_SCLK_FORCE_RE | |
| RADEON_SCLK_FORCE_PB | RADEON_SCLK_FORCE_TAM | |
| RADEON_SCLK_FORCE_TDM); |
| WREG32_PLL(RADEON_SCLK_CNTL, tmp); |
| } else if (ASIC_IS_R300(rdev)) { |
| if ((rdev->family == CHIP_RS400) || |
| (rdev->family == CHIP_RS480)) { |
| tmp = RREG32_PLL(RADEON_SCLK_CNTL); |
| tmp &= |
| ~(RADEON_SCLK_FORCE_DISP2 | |
| RADEON_SCLK_FORCE_CP | |
| RADEON_SCLK_FORCE_HDP | |
| RADEON_SCLK_FORCE_DISP1 | |
| RADEON_SCLK_FORCE_TOP | |
| RADEON_SCLK_FORCE_E2 | R300_SCLK_FORCE_VAP |
| | RADEON_SCLK_FORCE_IDCT | |
| RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR |
| | R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX |
| | R300_SCLK_FORCE_US | |
| RADEON_SCLK_FORCE_TV_SCLK | |
| R300_SCLK_FORCE_SU | |
| RADEON_SCLK_FORCE_OV0); |
| tmp |= RADEON_DYN_STOP_LAT_MASK; |
| tmp |= |
| RADEON_SCLK_FORCE_TOP | |
| RADEON_SCLK_FORCE_VIP; |
| WREG32_PLL(RADEON_SCLK_CNTL, tmp); |
| tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); |
| tmp &= ~RADEON_SCLK_MORE_FORCEON; |
| tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT; |
| WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); |
| tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); |
| tmp |= (RADEON_PIXCLK_ALWAYS_ONb | |
| RADEON_PIXCLK_DAC_ALWAYS_ONb); |
| WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); |
| tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); |
| tmp |= (RADEON_PIX2CLK_ALWAYS_ONb | |
| RADEON_PIX2CLK_DAC_ALWAYS_ONb | |
| RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb | |
| R300_DVOCLK_ALWAYS_ONb | |
| RADEON_PIXCLK_BLEND_ALWAYS_ONb | |
| RADEON_PIXCLK_GV_ALWAYS_ONb | |
| R300_PIXCLK_DVO_ALWAYS_ONb | |
| RADEON_PIXCLK_LVDS_ALWAYS_ONb | |
| RADEON_PIXCLK_TMDS_ALWAYS_ONb | |
| R300_PIXCLK_TRANS_ALWAYS_ONb | |
| R300_PIXCLK_TVO_ALWAYS_ONb | |
| R300_P2G2CLK_ALWAYS_ONb | |
| R300_P2G2CLK_ALWAYS_ONb); |
| WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); |
| } else if (rdev->family >= CHIP_RV350) { |
| tmp = RREG32_PLL(R300_SCLK_CNTL2); |
| tmp &= ~(R300_SCLK_FORCE_TCL | |
| R300_SCLK_FORCE_GA | |
| R300_SCLK_FORCE_CBA); |
| tmp |= (R300_SCLK_TCL_MAX_DYN_STOP_LAT | |
| R300_SCLK_GA_MAX_DYN_STOP_LAT | |
| R300_SCLK_CBA_MAX_DYN_STOP_LAT); |
| WREG32_PLL(R300_SCLK_CNTL2, tmp); |
| tmp = RREG32_PLL(RADEON_SCLK_CNTL); |
| tmp &= |
| ~(RADEON_SCLK_FORCE_DISP2 | |
| RADEON_SCLK_FORCE_CP | |
| RADEON_SCLK_FORCE_HDP | |
| RADEON_SCLK_FORCE_DISP1 | |
| RADEON_SCLK_FORCE_TOP | |
| RADEON_SCLK_FORCE_E2 | R300_SCLK_FORCE_VAP |
| | RADEON_SCLK_FORCE_IDCT | |
| RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR |
| | R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX |
| | R300_SCLK_FORCE_US | |
| RADEON_SCLK_FORCE_TV_SCLK | |
| R300_SCLK_FORCE_SU | |
| RADEON_SCLK_FORCE_OV0); |
| tmp |= RADEON_DYN_STOP_LAT_MASK; |
| WREG32_PLL(RADEON_SCLK_CNTL, tmp); |
| tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); |
| tmp &= ~RADEON_SCLK_MORE_FORCEON; |
| tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT; |
| WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); |
| tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); |
| tmp |= (RADEON_PIXCLK_ALWAYS_ONb | |
| RADEON_PIXCLK_DAC_ALWAYS_ONb); |
| WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); |
| tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); |
| tmp |= (RADEON_PIX2CLK_ALWAYS_ONb | |
| RADEON_PIX2CLK_DAC_ALWAYS_ONb | |
| RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb | |
| R300_DVOCLK_ALWAYS_ONb | |
| RADEON_PIXCLK_BLEND_ALWAYS_ONb | |
| RADEON_PIXCLK_GV_ALWAYS_ONb | |
| R300_PIXCLK_DVO_ALWAYS_ONb | |
| RADEON_PIXCLK_LVDS_ALWAYS_ONb | |
| RADEON_PIXCLK_TMDS_ALWAYS_ONb | |
| R300_PIXCLK_TRANS_ALWAYS_ONb | |
| R300_PIXCLK_TVO_ALWAYS_ONb | |
| R300_P2G2CLK_ALWAYS_ONb | |
| R300_P2G2CLK_ALWAYS_ONb); |
| WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); |
| tmp = RREG32_PLL(RADEON_MCLK_MISC); |
| tmp |= (RADEON_MC_MCLK_DYN_ENABLE | |
| RADEON_IO_MCLK_DYN_ENABLE); |
| WREG32_PLL(RADEON_MCLK_MISC, tmp); |
| tmp = RREG32_PLL(RADEON_MCLK_CNTL); |
| tmp |= (RADEON_FORCEON_MCLKA | |
| RADEON_FORCEON_MCLKB); |
| tmp &= ~(RADEON_FORCEON_YCLKA | |
| RADEON_FORCEON_YCLKB | |
| RADEON_FORCEON_MC); |
| /* Some releases of vbios have set DISABLE_MC_MCLKA |
| and DISABLE_MC_MCLKB bits in the vbios table. Setting these |
| bits will cause H/W hang when reading video memory with dynamic clocking |
| enabled. */ |
| if ((tmp & R300_DISABLE_MC_MCLKA) && |
| (tmp & R300_DISABLE_MC_MCLKB)) { |
| /* If both bits are set, then check the active channels */ |
| tmp = RREG32_PLL(RADEON_MCLK_CNTL); |
| if (rdev->mc.vram_width == 64) { |
| if (RREG32(RADEON_MEM_CNTL) & |
| R300_MEM_USE_CD_CH_ONLY) |
| tmp &= |
| ~R300_DISABLE_MC_MCLKB; |
| else |
| tmp &= |
| ~R300_DISABLE_MC_MCLKA; |
| } else { |
| tmp &= ~(R300_DISABLE_MC_MCLKA | |
| R300_DISABLE_MC_MCLKB); |
| } |
| } |
| WREG32_PLL(RADEON_MCLK_CNTL, tmp); |
| } else { |
| tmp = RREG32_PLL(RADEON_SCLK_CNTL); |
| tmp &= ~(R300_SCLK_FORCE_VAP); |
| tmp |= RADEON_SCLK_FORCE_CP; |
| WREG32_PLL(RADEON_SCLK_CNTL, tmp); |
| udelay(15000); |
| tmp = RREG32_PLL(R300_SCLK_CNTL2); |
| tmp &= ~(R300_SCLK_FORCE_TCL | |
| R300_SCLK_FORCE_GA | |
| R300_SCLK_FORCE_CBA); |
| WREG32_PLL(R300_SCLK_CNTL2, tmp); |
| } |
| } else { |
| tmp = RREG32_PLL(RADEON_CLK_PWRMGT_CNTL); |
| tmp &= ~(RADEON_ACTIVE_HILO_LAT_MASK | |
| RADEON_DISP_DYN_STOP_LAT_MASK | |
| RADEON_DYN_STOP_MODE_MASK); |
| tmp |= (RADEON_ENGIN_DYNCLK_MODE | |
| (0x01 << RADEON_ACTIVE_HILO_LAT_SHIFT)); |
| WREG32_PLL(RADEON_CLK_PWRMGT_CNTL, tmp); |
| udelay(15000); |
| tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL); |
| tmp |= RADEON_SCLK_DYN_START_CNTL; |
| WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp); |
| udelay(15000); |
| /* When DRI is enabled, setting DYN_STOP_LAT to zero can cause some R200 |
| to lockup randomly, leave them as set by BIOS. |
| */ |
| tmp = RREG32_PLL(RADEON_SCLK_CNTL); |
| /*tmp &= RADEON_SCLK_SRC_SEL_MASK; */ |
| tmp &= ~RADEON_SCLK_FORCEON_MASK; |
| /*RAGE_6::A11 A12 A12N1 A13, RV250::A11 A12, R300 */ |
| if (((rdev->family == CHIP_RV250) && |
| ((RREG32(RADEON_CONFIG_CNTL) & |
| RADEON_CFG_ATI_REV_ID_MASK) < |
| RADEON_CFG_ATI_REV_A13)) |
| || ((rdev->family == CHIP_RV100) |
| && |
| ((RREG32(RADEON_CONFIG_CNTL) & |
| RADEON_CFG_ATI_REV_ID_MASK) <= |
| RADEON_CFG_ATI_REV_A13))) { |
| tmp |= RADEON_SCLK_FORCE_CP; |
| tmp |= RADEON_SCLK_FORCE_VIP; |
| } |
| WREG32_PLL(RADEON_SCLK_CNTL, tmp); |
| if ((rdev->family == CHIP_RV200) || |
| (rdev->family == CHIP_RV250) || |
| (rdev->family == CHIP_RV280)) { |
| tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); |
| tmp &= ~RADEON_SCLK_MORE_FORCEON; |
| /* RV200::A11 A12 RV250::A11 A12 */ |
| if (((rdev->family == CHIP_RV200) || |
| (rdev->family == CHIP_RV250)) && |
| ((RREG32(RADEON_CONFIG_CNTL) & |
| RADEON_CFG_ATI_REV_ID_MASK) < |
| RADEON_CFG_ATI_REV_A13)) { |
| tmp |= RADEON_SCLK_MORE_FORCEON; |
| } |
| WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); |
| udelay(15000); |
| } |
| /* RV200::A11 A12, RV250::A11 A12 */ |
| if (((rdev->family == CHIP_RV200) || |
| (rdev->family == CHIP_RV250)) && |
| ((RREG32(RADEON_CONFIG_CNTL) & |
| RADEON_CFG_ATI_REV_ID_MASK) < |
| RADEON_CFG_ATI_REV_A13)) { |
| tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL); |
| tmp |= RADEON_TCL_BYPASS_DISABLE; |
| WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp); |
| } |
| udelay(15000); |
| /*enable dynamic mode for display clocks (PIXCLK and PIX2CLK) */ |
| tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); |
| tmp |= (RADEON_PIX2CLK_ALWAYS_ONb | |
| RADEON_PIX2CLK_DAC_ALWAYS_ONb | |
| RADEON_PIXCLK_BLEND_ALWAYS_ONb | |
| RADEON_PIXCLK_GV_ALWAYS_ONb | |
| RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb | |
| RADEON_PIXCLK_LVDS_ALWAYS_ONb | |
| RADEON_PIXCLK_TMDS_ALWAYS_ONb); |
| WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); |
| udelay(15000); |
| tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); |
| tmp |= (RADEON_PIXCLK_ALWAYS_ONb | |
| RADEON_PIXCLK_DAC_ALWAYS_ONb); |
| WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); |
| udelay(15000); |
| } |
| } else { |
| /* Turn everything OFF (ForceON to everything) */ |
| if (rdev->flags & RADEON_SINGLE_CRTC) { |
| tmp = RREG32_PLL(RADEON_SCLK_CNTL); |
| tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_HDP | |
| RADEON_SCLK_FORCE_DISP1 | RADEON_SCLK_FORCE_TOP |
| | RADEON_SCLK_FORCE_E2 | RADEON_SCLK_FORCE_SE | |
| RADEON_SCLK_FORCE_IDCT | RADEON_SCLK_FORCE_VIP | |
| RADEON_SCLK_FORCE_RE | RADEON_SCLK_FORCE_PB | |
| RADEON_SCLK_FORCE_TAM | RADEON_SCLK_FORCE_TDM | |
| RADEON_SCLK_FORCE_RB); |
| WREG32_PLL(RADEON_SCLK_CNTL, tmp); |
| } else if ((rdev->family == CHIP_RS400) || |
| (rdev->family == CHIP_RS480)) { |
| tmp = RREG32_PLL(RADEON_SCLK_CNTL); |
| tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP | |
| RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1 |
| | RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_E2 | |
| R300_SCLK_FORCE_VAP | RADEON_SCLK_FORCE_IDCT | |
| RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR | |
| R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX | |
| R300_SCLK_FORCE_US | RADEON_SCLK_FORCE_TV_SCLK | |
| R300_SCLK_FORCE_SU | RADEON_SCLK_FORCE_OV0); |
| WREG32_PLL(RADEON_SCLK_CNTL, tmp); |
| tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); |
| tmp |= RADEON_SCLK_MORE_FORCEON; |
| WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); |
| tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); |
| tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb | |
| RADEON_PIXCLK_DAC_ALWAYS_ONb | |
| R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF); |
| WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); |
| tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); |
| tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb | |
| RADEON_PIX2CLK_DAC_ALWAYS_ONb | |
| RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb | |
| R300_DVOCLK_ALWAYS_ONb | |
| RADEON_PIXCLK_BLEND_ALWAYS_ONb | |
| RADEON_PIXCLK_GV_ALWAYS_ONb | |
| R300_PIXCLK_DVO_ALWAYS_ONb | |
| RADEON_PIXCLK_LVDS_ALWAYS_ONb | |
| RADEON_PIXCLK_TMDS_ALWAYS_ONb | |
| R300_PIXCLK_TRANS_ALWAYS_ONb | |
| R300_PIXCLK_TVO_ALWAYS_ONb | |
| R300_P2G2CLK_ALWAYS_ONb | |
| R300_P2G2CLK_ALWAYS_ONb | |
| R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF); |
| WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); |
| } else if (rdev->family >= CHIP_RV350) { |
| /* for RV350/M10, no delays are required. */ |
| tmp = RREG32_PLL(R300_SCLK_CNTL2); |
| tmp |= (R300_SCLK_FORCE_TCL | |
| R300_SCLK_FORCE_GA | R300_SCLK_FORCE_CBA); |
| WREG32_PLL(R300_SCLK_CNTL2, tmp); |
| tmp = RREG32_PLL(RADEON_SCLK_CNTL); |
| tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP | |
| RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1 |
| | RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_E2 | |
| R300_SCLK_FORCE_VAP | RADEON_SCLK_FORCE_IDCT | |
| RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR | |
| R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX | |
| R300_SCLK_FORCE_US | RADEON_SCLK_FORCE_TV_SCLK | |
| R300_SCLK_FORCE_SU | RADEON_SCLK_FORCE_OV0); |
| WREG32_PLL(RADEON_SCLK_CNTL, tmp); |
| tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); |
| tmp |= RADEON_SCLK_MORE_FORCEON; |
| WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); |
| tmp = RREG32_PLL(RADEON_MCLK_CNTL); |
| tmp |= (RADEON_FORCEON_MCLKA | |
| RADEON_FORCEON_MCLKB | |
| RADEON_FORCEON_YCLKA | |
| RADEON_FORCEON_YCLKB | RADEON_FORCEON_MC); |
| WREG32_PLL(RADEON_MCLK_CNTL, tmp); |
| tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); |
| tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb | |
| RADEON_PIXCLK_DAC_ALWAYS_ONb | |
| R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF); |
| WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); |
| tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); |
| tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb | |
| RADEON_PIX2CLK_DAC_ALWAYS_ONb | |
| RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb | |
| R300_DVOCLK_ALWAYS_ONb | |
| RADEON_PIXCLK_BLEND_ALWAYS_ONb | |
| RADEON_PIXCLK_GV_ALWAYS_ONb | |
| R300_PIXCLK_DVO_ALWAYS_ONb | |
| RADEON_PIXCLK_LVDS_ALWAYS_ONb | |
| RADEON_PIXCLK_TMDS_ALWAYS_ONb | |
| R300_PIXCLK_TRANS_ALWAYS_ONb | |
| R300_PIXCLK_TVO_ALWAYS_ONb | |
| R300_P2G2CLK_ALWAYS_ONb | |
| R300_P2G2CLK_ALWAYS_ONb | |
| R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF); |
| WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); |
| } else { |
| tmp = RREG32_PLL(RADEON_SCLK_CNTL); |
| tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_E2); |
| tmp |= RADEON_SCLK_FORCE_SE; |
| if (rdev->flags & RADEON_SINGLE_CRTC) { |
| tmp |= (RADEON_SCLK_FORCE_RB | |
| RADEON_SCLK_FORCE_TDM | |
| RADEON_SCLK_FORCE_TAM | |
| RADEON_SCLK_FORCE_PB | |
| RADEON_SCLK_FORCE_RE | |
| RADEON_SCLK_FORCE_VIP | |
| RADEON_SCLK_FORCE_IDCT | |
| RADEON_SCLK_FORCE_TOP | |
| RADEON_SCLK_FORCE_DISP1 | |
| RADEON_SCLK_FORCE_DISP2 | |
| RADEON_SCLK_FORCE_HDP); |
| } else if ((rdev->family == CHIP_R300) || |
| (rdev->family == CHIP_R350)) { |
| tmp |= (RADEON_SCLK_FORCE_HDP | |
| RADEON_SCLK_FORCE_DISP1 | |
| RADEON_SCLK_FORCE_DISP2 | |
| RADEON_SCLK_FORCE_TOP | |
| RADEON_SCLK_FORCE_IDCT | |
| RADEON_SCLK_FORCE_VIP); |
| } |
| WREG32_PLL(RADEON_SCLK_CNTL, tmp); |
| udelay(16000); |
| if ((rdev->family == CHIP_R300) || |
| (rdev->family == CHIP_R350)) { |
| tmp = RREG32_PLL(R300_SCLK_CNTL2); |
| tmp |= (R300_SCLK_FORCE_TCL | |
| R300_SCLK_FORCE_GA | |
| R300_SCLK_FORCE_CBA); |
| WREG32_PLL(R300_SCLK_CNTL2, tmp); |
| udelay(16000); |
| } |
| if (rdev->flags & RADEON_IS_IGP) { |
| tmp = RREG32_PLL(RADEON_MCLK_CNTL); |
| tmp &= ~(RADEON_FORCEON_MCLKA | |
| RADEON_FORCEON_YCLKA); |
| WREG32_PLL(RADEON_MCLK_CNTL, tmp); |
| udelay(16000); |
| } |
| if ((rdev->family == CHIP_RV200) || |
| (rdev->family == CHIP_RV250) || |
| (rdev->family == CHIP_RV280)) { |
| tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); |
| tmp |= RADEON_SCLK_MORE_FORCEON; |
| WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); |
| udelay(16000); |
| } |
| tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); |
| tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb | |
| RADEON_PIX2CLK_DAC_ALWAYS_ONb | |
| RADEON_PIXCLK_BLEND_ALWAYS_ONb | |
| RADEON_PIXCLK_GV_ALWAYS_ONb | |
| RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb | |
| RADEON_PIXCLK_LVDS_ALWAYS_ONb | |
| RADEON_PIXCLK_TMDS_ALWAYS_ONb); |
| WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); |
| udelay(16000); |
| tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); |
| tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb | |
| RADEON_PIXCLK_DAC_ALWAYS_ONb); |
| WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); |
| } |
| } |
| } |
| static void radeon_apply_clock_quirks(struct radeon_device *rdev) |
| { |
| uint32_t tmp; |
| /* XXX make sure engine is idle */ |
| if (rdev->family < CHIP_RS600) { |
| tmp = RREG32_PLL(RADEON_SCLK_CNTL); |
| if (ASIC_IS_R300(rdev) || ASIC_IS_RV100(rdev)) |
| tmp |= RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_VIP; |
| if ((rdev->family == CHIP_RV250) |
| || (rdev->family == CHIP_RV280)) |
| tmp |= |
| RADEON_SCLK_FORCE_DISP1 | RADEON_SCLK_FORCE_DISP2; |
| if ((rdev->family == CHIP_RV350) |
| || (rdev->family == CHIP_RV380)) |
| tmp |= R300_SCLK_FORCE_VAP; |
| if (rdev->family == CHIP_R420) |
| tmp |= R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX; |
| WREG32_PLL(RADEON_SCLK_CNTL, tmp); |
| } else if (rdev->family < CHIP_R600) { |
| tmp = RREG32_PLL(AVIVO_CP_DYN_CNTL); |
| tmp |= AVIVO_CP_FORCEON; |
| WREG32_PLL(AVIVO_CP_DYN_CNTL, tmp); |
| tmp = RREG32_PLL(AVIVO_E2_DYN_CNTL); |
| tmp |= AVIVO_E2_FORCEON; |
| WREG32_PLL(AVIVO_E2_DYN_CNTL, tmp); |
| tmp = RREG32_PLL(AVIVO_IDCT_DYN_CNTL); |
| tmp |= AVIVO_IDCT_FORCEON; |
| WREG32_PLL(AVIVO_IDCT_DYN_CNTL, tmp); |
| } |
| } |
| int radeon_static_clocks_init(struct drm_device *dev) |
| { |
| struct radeon_device *rdev = dev->dev_private; |
| /* XXX make sure engine is idle */ |
| if (radeon_dynclks != -1) { |
| if (radeon_dynclks) |
| radeon_set_clock_gating(rdev, 1); |
| } |
| radeon_apply_clock_quirks(rdev); |
| return 0; |
| } |
| /drivers/video/drm/radeon/radeon_device.c |
|---|
| 0,0 → 1,899 |
| /* |
| * Copyright 2008 Advanced Micro Devices, Inc. |
| * Copyright 2008 Red Hat Inc. |
| * Copyright 2009 Jerome Glisse. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice shall be included in |
| * all copies or substantial portions of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| * OTHER DEALINGS IN THE SOFTWARE. |
| * |
| * Authors: Dave Airlie |
| * Alex Deucher |
| * Jerome Glisse |
| */ |
| //#include <linux/console.h> |
| //#include <drm/drmP.h> |
| //#include <drm/drm_crtc_helper.h> |
| #include "radeon_drm.h" |
| #include "radeon_reg.h" |
| #include "radeon.h" |
| #include "radeon_asic.h" |
| #include "atom.h" |
| #include <syscall.h> |
| int radeon_dynclks = -1; |
| int radeon_agpmode = -1; |
| int radeon_gart_size = 512; /* default gart size */ |
| /* |
| * Clear GPU surface registers. |
| */ |
| static void radeon_surface_init(struct radeon_device *rdev) |
| { |
| dbgprintf("%s\n\r",__FUNCTION__); |
| /* FIXME: check this out */ |
| if (rdev->family < CHIP_R600) { |
| int i; |
| for (i = 0; i < 8; i++) { |
| WREG32(RADEON_SURFACE0_INFO + |
| i * (RADEON_SURFACE1_INFO - RADEON_SURFACE0_INFO), |
| 0); |
| } |
| } |
| } |
| /* |
| * GPU scratch registers helpers function. |
| */ |
| static void radeon_scratch_init(struct radeon_device *rdev) |
| { |
| int i; |
| /* FIXME: check this out */ |
| if (rdev->family < CHIP_R300) { |
| rdev->scratch.num_reg = 5; |
| } else { |
| rdev->scratch.num_reg = 7; |
| } |
| for (i = 0; i < rdev->scratch.num_reg; i++) { |
| rdev->scratch.free[i] = true; |
| rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4); |
| } |
| } |
| int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg) |
| { |
| int i; |
| for (i = 0; i < rdev->scratch.num_reg; i++) { |
| if (rdev->scratch.free[i]) { |
| rdev->scratch.free[i] = false; |
| *reg = rdev->scratch.reg[i]; |
| return 0; |
| } |
| } |
| return -EINVAL; |
| } |
| void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg) |
| { |
| int i; |
| for (i = 0; i < rdev->scratch.num_reg; i++) { |
| if (rdev->scratch.reg[i] == reg) { |
| rdev->scratch.free[i] = true; |
| return; |
| } |
| } |
| } |
| /* |
| * MC common functions |
| */ |
| int radeon_mc_setup(struct radeon_device *rdev) |
| { |
| uint32_t tmp; |
| /* Some chips have an "issue" with the memory controller, the |
| * location must be aligned to the size. We just align it down, |
| * too bad if we walk over the top of system memory, we don't |
| * use DMA without a remapped anyway. |
| * Affected chips are rv280, all r3xx, and all r4xx, but not IGP |
| */ |
| /* FGLRX seems to setup like this, VRAM a 0, then GART. |
| */ |
| /* |
| * Note: from R6xx the address space is 40bits but here we only |
| * use 32bits (still have to see a card which would exhaust 4G |
| * address space). |
| */ |
| if (rdev->mc.vram_location != 0xFFFFFFFFUL) { |
| /* vram location was already setup try to put gtt after |
| * if it fits */ |
| tmp = rdev->mc.vram_location + rdev->mc.vram_size; |
| tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1); |
| if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) { |
| rdev->mc.gtt_location = tmp; |
| } else { |
| if (rdev->mc.gtt_size >= rdev->mc.vram_location) { |
| printk(KERN_ERR "[drm] GTT too big to fit " |
| "before or after vram location.\n"); |
| return -EINVAL; |
| } |
| rdev->mc.gtt_location = 0; |
| } |
| } else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) { |
| /* gtt location was already setup try to put vram before |
| * if it fits */ |
| if (rdev->mc.vram_size < rdev->mc.gtt_location) { |
| rdev->mc.vram_location = 0; |
| } else { |
| tmp = rdev->mc.gtt_location + rdev->mc.gtt_size; |
| tmp += (rdev->mc.vram_size - 1); |
| tmp &= ~(rdev->mc.vram_size - 1); |
| if ((0xFFFFFFFFUL - tmp) >= rdev->mc.vram_size) { |
| rdev->mc.vram_location = tmp; |
| } else { |
| printk(KERN_ERR "[drm] vram too big to fit " |
| "before or after GTT location.\n"); |
| return -EINVAL; |
| } |
| } |
| } else { |
| rdev->mc.vram_location = 0; |
| rdev->mc.gtt_location = rdev->mc.vram_size; |
| } |
| DRM_INFO("radeon: VRAM %uM\n", rdev->mc.vram_size >> 20); |
| DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n", |
| rdev->mc.vram_location, |
| rdev->mc.vram_location + rdev->mc.vram_size - 1); |
| DRM_INFO("radeon: GTT %uM\n", rdev->mc.gtt_size >> 20); |
| DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n", |
| rdev->mc.gtt_location, |
| rdev->mc.gtt_location + rdev->mc.gtt_size - 1); |
| return 0; |
| } |
| /* |
| * GPU helpers function. |
| */ |
| static bool radeon_card_posted(struct radeon_device *rdev) |
| { |
| uint32_t reg; |
| dbgprintf("%s\n\r",__FUNCTION__); |
| /* first check CRTCs */ |
| if (ASIC_IS_AVIVO(rdev)) { |
| reg = RREG32(AVIVO_D1CRTC_CONTROL) | |
| RREG32(AVIVO_D2CRTC_CONTROL); |
| if (reg & AVIVO_CRTC_EN) { |
| return true; |
| } |
| } else { |
| reg = RREG32(RADEON_CRTC_GEN_CNTL) | |
| RREG32(RADEON_CRTC2_GEN_CNTL); |
| if (reg & RADEON_CRTC_EN) { |
| return true; |
| } |
| } |
| /* then check MEM_SIZE, in case the crtcs are off */ |
| if (rdev->family >= CHIP_R600) |
| reg = RREG32(R600_CONFIG_MEMSIZE); |
| else |
| reg = RREG32(RADEON_CONFIG_MEMSIZE); |
| if (reg) |
| return true; |
| return false; |
| } |
| /* |
| * Registers accessors functions. |
| */ |
| uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg) |
| { |
| DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); |
| BUG_ON(1); |
| return 0; |
| } |
| void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
| { |
| DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", |
| reg, v); |
| BUG_ON(1); |
| } |
| void radeon_register_accessor_init(struct radeon_device *rdev) |
| { |
| dbgprintf("%s\n\r",__FUNCTION__); |
| rdev->mm_rreg = &r100_mm_rreg; |
| rdev->mm_wreg = &r100_mm_wreg; |
| rdev->mc_rreg = &radeon_invalid_rreg; |
| rdev->mc_wreg = &radeon_invalid_wreg; |
| rdev->pll_rreg = &radeon_invalid_rreg; |
| rdev->pll_wreg = &radeon_invalid_wreg; |
| rdev->pcie_rreg = &radeon_invalid_rreg; |
| rdev->pcie_wreg = &radeon_invalid_wreg; |
| rdev->pciep_rreg = &radeon_invalid_rreg; |
| rdev->pciep_wreg = &radeon_invalid_wreg; |
| /* Don't change order as we are overridding accessor. */ |
| if (rdev->family < CHIP_RV515) { |
| // rdev->pcie_rreg = &rv370_pcie_rreg; |
| // rdev->pcie_wreg = &rv370_pcie_wreg; |
| } |
| if (rdev->family >= CHIP_RV515) { |
| // rdev->pcie_rreg = &rv515_pcie_rreg; |
| // rdev->pcie_wreg = &rv515_pcie_wreg; |
| } |
| /* FIXME: not sure here */ |
| if (rdev->family <= CHIP_R580) { |
| // rdev->pll_rreg = &r100_pll_rreg; |
| // rdev->pll_wreg = &r100_pll_wreg; |
| } |
| if (rdev->family >= CHIP_RV515) { |
| rdev->mc_rreg = &rv515_mc_rreg; |
| rdev->mc_wreg = &rv515_mc_wreg; |
| } |
| if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) { |
| // rdev->mc_rreg = &rs400_mc_rreg; |
| // rdev->mc_wreg = &rs400_mc_wreg; |
| } |
| if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { |
| // rdev->mc_rreg = &rs690_mc_rreg; |
| // rdev->mc_wreg = &rs690_mc_wreg; |
| } |
| if (rdev->family == CHIP_RS600) { |
| // rdev->mc_rreg = &rs600_mc_rreg; |
| // rdev->mc_wreg = &rs600_mc_wreg; |
| } |
| if (rdev->family >= CHIP_R600) { |
| // rdev->pciep_rreg = &r600_pciep_rreg; |
| // rdev->pciep_wreg = &r600_pciep_wreg; |
| } |
| } |
| /* |
| * ASIC |
| */ |
| int radeon_asic_init(struct radeon_device *rdev) |
| { |
| dbgprintf("%s\n\r",__FUNCTION__); |
| radeon_register_accessor_init(rdev); |
| switch (rdev->family) { |
| case CHIP_R100: |
| case CHIP_RV100: |
| case CHIP_RS100: |
| case CHIP_RV200: |
| case CHIP_RS200: |
| case CHIP_R200: |
| case CHIP_RV250: |
| case CHIP_RS300: |
| case CHIP_RV280: |
| // rdev->asic = &r100_asic; |
| break; |
| case CHIP_R300: |
| case CHIP_R350: |
| case CHIP_RV350: |
| case CHIP_RV380: |
| // rdev->asic = &r300_asic; |
| break; |
| case CHIP_R420: |
| case CHIP_R423: |
| case CHIP_RV410: |
| // rdev->asic = &r420_asic; |
| break; |
| case CHIP_RS400: |
| case CHIP_RS480: |
| // rdev->asic = &rs400_asic; |
| break; |
| case CHIP_RS600: |
| // rdev->asic = &rs600_asic; |
| break; |
| case CHIP_RS690: |
| case CHIP_RS740: |
| // rdev->asic = &rs690_asic; |
| break; |
| case CHIP_RV515: |
| // rdev->asic = &rv515_asic; |
| break; |
| case CHIP_R520: |
| case CHIP_RV530: |
| case CHIP_RV560: |
| case CHIP_RV570: |
| case CHIP_R580: |
| rdev->asic = &r520_asic; |
| break; |
| case CHIP_R600: |
| case CHIP_RV610: |
| case CHIP_RV630: |
| case CHIP_RV620: |
| case CHIP_RV635: |
| case CHIP_RV670: |
| case CHIP_RS780: |
| case CHIP_RV770: |
| case CHIP_RV730: |
| case CHIP_RV710: |
| default: |
| /* FIXME: not supported yet */ |
| return -EINVAL; |
| } |
| return 0; |
| } |
| /* |
| * Wrapper around modesetting bits. |
| */ |
| int radeon_clocks_init(struct radeon_device *rdev) |
| { |
| int r; |
| dbgprintf("%s\n\r",__FUNCTION__); |
| radeon_get_clock_info(rdev->ddev); |
| r = radeon_static_clocks_init(rdev->ddev); |
| if (r) { |
| return r; |
| } |
| DRM_INFO("Clocks initialized !\n"); |
| return 0; |
| } |
| void radeon_clocks_fini(struct radeon_device *rdev) |
| { |
| } |
| /* ATOM accessor methods */ |
| static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) |
| { |
| struct radeon_device *rdev = info->dev->dev_private; |
| uint32_t r; |
| r = rdev->pll_rreg(rdev, reg); |
| return r; |
| } |
| static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) |
| { |
| struct radeon_device *rdev = info->dev->dev_private; |
| rdev->pll_wreg(rdev, reg, val); |
| } |
| static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) |
| { |
| struct radeon_device *rdev = info->dev->dev_private; |
| uint32_t r; |
| r = rdev->mc_rreg(rdev, reg); |
| return r; |
| } |
| static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) |
| { |
| struct radeon_device *rdev = info->dev->dev_private; |
| rdev->mc_wreg(rdev, reg, val); |
| } |
| static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) |
| { |
| struct radeon_device *rdev = info->dev->dev_private; |
| WREG32(reg*4, val); |
| } |
| static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) |
| { |
| struct radeon_device *rdev = info->dev->dev_private; |
| uint32_t r; |
| r = RREG32(reg*4); |
| return r; |
| } |
| static struct card_info atom_card_info = { |
| .dev = NULL, |
| .reg_read = cail_reg_read, |
| .reg_write = cail_reg_write, |
| .mc_read = cail_mc_read, |
| .mc_write = cail_mc_write, |
| .pll_read = cail_pll_read, |
| .pll_write = cail_pll_write, |
| }; |
| int radeon_atombios_init(struct radeon_device *rdev) |
| { |
| dbgprintf("%s\n\r",__FUNCTION__); |
| atom_card_info.dev = rdev->ddev; |
| rdev->mode_info.atom_context = atom_parse(&atom_card_info, rdev->bios); |
| radeon_atom_initialize_bios_scratch_regs(rdev->ddev); |
| return 0; |
| } |
| void radeon_atombios_fini(struct radeon_device *rdev) |
| { |
| free(rdev->mode_info.atom_context); |
| } |
| int radeon_combios_init(struct radeon_device *rdev) |
| { |
| // radeon_combios_initialize_bios_scratch_regs(rdev->ddev); |
| return 0; |
| } |
| void radeon_combios_fini(struct radeon_device *rdev) |
| { |
| } |
| int radeon_modeset_init(struct radeon_device *rdev); |
| void radeon_modeset_fini(struct radeon_device *rdev); |
| /* |
| * Radeon device. |
| */ |
| int radeon_device_init(struct radeon_device *rdev, |
| struct drm_device *ddev, |
| struct pci_dev *pdev, |
| uint32_t flags) |
| { |
| int r, ret = -1; |
| dbgprintf("%s\n\r",__FUNCTION__); |
| DRM_INFO("radeon: Initializing kernel modesetting.\n"); |
| rdev->shutdown = false; |
| rdev->ddev = ddev; |
| rdev->pdev = pdev; |
| rdev->flags = flags; |
| rdev->family = flags & RADEON_FAMILY_MASK; |
| rdev->is_atom_bios = false; |
| rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT; |
| rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; |
| rdev->gpu_lockup = false; |
| /* mutex initialization are all done here so we |
| * can recall function without having locking issues */ |
| // mutex_init(&rdev->cs_mutex); |
| // mutex_init(&rdev->ib_pool.mutex); |
| // mutex_init(&rdev->cp.mutex); |
| // rwlock_init(&rdev->fence_drv.lock); |
| if (radeon_agpmode == -1) { |
| rdev->flags &= ~RADEON_IS_AGP; |
| if (rdev->family > CHIP_RV515 || |
| rdev->family == CHIP_RV380 || |
| rdev->family == CHIP_RV410 || |
| rdev->family == CHIP_R423) { |
| DRM_INFO("Forcing AGP to PCIE mode\n"); |
| rdev->flags |= RADEON_IS_PCIE; |
| } else { |
| DRM_INFO("Forcing AGP to PCI mode\n"); |
| rdev->flags |= RADEON_IS_PCI; |
| } |
| } |
| /* Set asic functions */ |
| r = radeon_asic_init(rdev); |
| if (r) { |
| return r; |
| } |
| // r = radeon_init(rdev); |
| r = rdev->asic->init(rdev); |
| if (r) { |
| return r; |
| } |
| /* Report DMA addressing limitation */ |
| // r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(32)); |
| // if (r) { |
| // printk(KERN_WARNING "radeon: No suitable DMA available.\n"); |
| // } |
| /* Registers mapping */ |
| /* TODO: block userspace mapping of io register */ |
| rdev->rmmio_base = pci_resource_start(rdev->pdev, 2); |
| rdev->rmmio_size = pci_resource_len(rdev->pdev, 2); |
| rdev->rmmio = (void*)MapIoMem(rdev->rmmio_base, rdev->rmmio_size, |
| PG_SW+PG_NOCACHE); |
| if (rdev->rmmio == NULL) { |
| return -ENOMEM; |
| } |
| DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base); |
| DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size); |
| /* Setup errata flags */ |
| radeon_errata(rdev); |
| /* Initialize scratch registers */ |
| radeon_scratch_init(rdev); |
| /* Initialize surface registers */ |
| radeon_surface_init(rdev); |
| /* TODO: disable VGA need to use VGA request */ |
| /* BIOS*/ |
| if (!radeon_get_bios(rdev)) { |
| if (ASIC_IS_AVIVO(rdev)) |
| return -EINVAL; |
| } |
| if (rdev->is_atom_bios) { |
| r = radeon_atombios_init(rdev); |
| if (r) { |
| return r; |
| } |
| } else { |
| r = radeon_combios_init(rdev); |
| if (r) { |
| return r; |
| } |
| } |
| /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
| if (radeon_gpu_reset(rdev)) { |
| /* FIXME: what do we want to do here ? */ |
| } |
| /* check if cards are posted or not */ |
| if (!radeon_card_posted(rdev) && rdev->bios) { |
| DRM_INFO("GPU not posted. posting now...\n"); |
| if (rdev->is_atom_bios) { |
| atom_asic_init(rdev->mode_info.atom_context); |
| } else { |
| // radeon_combios_asic_init(rdev->ddev); |
| } |
| } |
| /* Get vram informations */ |
| radeon_vram_info(rdev); |
| /* Device is severly broken if aper size > vram size. |
| * for RN50/M6/M7 - Novell bug 204882 ? |
| */ |
| if (rdev->mc.vram_size < rdev->mc.aper_size) { |
| rdev->mc.aper_size = rdev->mc.vram_size; |
| } |
| /* Add an MTRR for the VRAM */ |
| // rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size, |
| // MTRR_TYPE_WRCOMB, 1); |
| DRM_INFO("Detected VRAM RAM=%uM, BAR=%uM\n", |
| rdev->mc.vram_size >> 20, |
| (unsigned)rdev->mc.aper_size >> 20); |
| DRM_INFO("RAM width %dbits %cDR\n", |
| rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S'); |
| /* Initialize clocks */ |
| r = radeon_clocks_init(rdev); |
| if (r) { |
| return r; |
| } |
| #if 0 |
| /* Initialize memory controller (also test AGP) */ |
| r = radeon_mc_init(rdev); |
| if (r) { |
| return r; |
| } |
| /* Fence driver */ |
| r = radeon_fence_driver_init(rdev); |
| if (r) { |
| return r; |
| } |
| r = radeon_irq_kms_init(rdev); |
| if (r) { |
| return r; |
| } |
| /* Memory manager */ |
| r = radeon_object_init(rdev); |
| if (r) { |
| return r; |
| } |
| /* Initialize GART (initialize after TTM so we can allocate |
| * memory through TTM but finalize after TTM) */ |
| r = radeon_gart_enable(rdev); |
| if (!r) { |
| r = radeon_gem_init(rdev); |
| } |
| /* 1M ring buffer */ |
| if (!r) { |
| r = radeon_cp_init(rdev, 1024 * 1024); |
| } |
| if (!r) { |
| r = radeon_wb_init(rdev); |
| if (r) { |
| DRM_ERROR("radeon: failled initializing WB (%d).\n", r); |
| return r; |
| } |
| } |
| if (!r) { |
| r = radeon_ib_pool_init(rdev); |
| if (r) { |
| DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r); |
| return r; |
| } |
| } |
| if (!r) { |
| r = radeon_ib_test(rdev); |
| if (r) { |
| DRM_ERROR("radeon: failled testing IB (%d).\n", r); |
| return r; |
| } |
| } |
| ret = r; |
| r = radeon_modeset_init(rdev); |
| if (r) { |
| return r; |
| } |
| if (rdev->fbdev_rfb && rdev->fbdev_rfb->obj) { |
| rdev->fbdev_robj = rdev->fbdev_rfb->obj->driver_private; |
| } |
| if (!ret) { |
| DRM_INFO("radeon: kernel modesetting successfully initialized.\n"); |
| } |
| // if (radeon_benchmarking) { |
| // radeon_benchmark(rdev); |
| // } |
| #endif |
| return ret; |
| } |
| static struct pci_device_id pciidlist[] = { |
| radeon_PCI_IDS |
| }; |
| u32_t __stdcall drvEntry(int action) |
| { |
| struct pci_device_id *ent; |
| dev_t device; |
| int err; |
| u32_t retval = 0; |
| if(action != 1) |
| return 0; |
| if(!dbg_open("/rd/1/drivers/atikms.log")) |
| { |
| printf("Can't open /rd/1/drivers/ati2d.log\nExit\n"); |
| return 0; |
| } |
| enum_pci_devices(); |
| ent = find_pci_device(&device, pciidlist); |
| if( unlikely(ent == NULL) ) |
| { |
| dbgprintf("device not found\n"); |
| return 0; |
| }; |
| dbgprintf("device %x:%x\n", device.pci_dev.vendor, |
| device.pci_dev.device); |
| err = drm_get_dev(&device.pci_dev, ent); |
| return retval; |
| }; |
| /* |
| static struct drm_driver kms_driver = { |
| .driver_features = |
| DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_PCI_DMA | DRIVER_SG | |
| DRIVER_HAVE_IRQ | DRIVER_HAVE_DMA | DRIVER_IRQ_SHARED | DRIVER_GEM, |
| .dev_priv_size = 0, |
| .load = radeon_driver_load_kms, |
| .firstopen = radeon_driver_firstopen_kms, |
| .open = radeon_driver_open_kms, |
| .preclose = radeon_driver_preclose_kms, |
| .postclose = radeon_driver_postclose_kms, |
| .lastclose = radeon_driver_lastclose_kms, |
| .unload = radeon_driver_unload_kms, |
| .suspend = radeon_suspend_kms, |
| .resume = radeon_resume_kms, |
| .get_vblank_counter = radeon_get_vblank_counter_kms, |
| .enable_vblank = radeon_enable_vblank_kms, |
| .disable_vblank = radeon_disable_vblank_kms, |
| .master_create = radeon_master_create_kms, |
| .master_destroy = radeon_master_destroy_kms, |
| #if defined(CONFIG_DEBUG_FS) |
| .debugfs_init = radeon_debugfs_init, |
| .debugfs_cleanup = radeon_debugfs_cleanup, |
| #endif |
| .irq_preinstall = radeon_driver_irq_preinstall_kms, |
| .irq_postinstall = radeon_driver_irq_postinstall_kms, |
| .irq_uninstall = radeon_driver_irq_uninstall_kms, |
| .irq_handler = radeon_driver_irq_handler_kms, |
| .reclaim_buffers = drm_core_reclaim_buffers, |
| .get_map_ofs = drm_core_get_map_ofs, |
| .get_reg_ofs = drm_core_get_reg_ofs, |
| .ioctls = radeon_ioctls_kms, |
| .gem_init_object = radeon_gem_object_init, |
| .gem_free_object = radeon_gem_object_free, |
| .dma_ioctl = radeon_dma_ioctl_kms, |
| .fops = { |
| .owner = THIS_MODULE, |
| .open = drm_open, |
| .release = drm_release, |
| .ioctl = drm_ioctl, |
| .mmap = radeon_mmap, |
| .poll = drm_poll, |
| .fasync = drm_fasync, |
| #ifdef CONFIG_COMPAT |
| .compat_ioctl = NULL, |
| #endif |
| }, |
| .pci_driver = { |
| .name = DRIVER_NAME, |
| .id_table = pciidlist, |
| .probe = radeon_pci_probe, |
| .remove = radeon_pci_remove, |
| .suspend = radeon_pci_suspend, |
| .resume = radeon_pci_resume, |
| }, |
| .name = DRIVER_NAME, |
| .desc = DRIVER_DESC, |
| .date = DRIVER_DATE, |
| .major = KMS_DRIVER_MAJOR, |
| .minor = KMS_DRIVER_MINOR, |
| .patchlevel = KMS_DRIVER_PATCHLEVEL, |
| }; |
| */ |
| /* |
| * Driver load/unload |
| */ |
| int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags) |
| { |
| struct radeon_device *rdev; |
| int r; |
| dbgprintf("%s\n\r",__FUNCTION__); |
| rdev = malloc(sizeof(struct radeon_device)); |
| if (rdev == NULL) { |
| return -ENOMEM; |
| }; |
| dev->dev_private = (void *)rdev; |
| /* update BUS flag */ |
| // if (drm_device_is_agp(dev)) { |
| flags |= RADEON_IS_AGP; |
| // } else if (drm_device_is_pcie(dev)) { |
| // flags |= RADEON_IS_PCIE; |
| // } else { |
| // flags |= RADEON_IS_PCI; |
| // } |
| r = radeon_device_init(rdev, dev, dev->pdev, flags); |
| if (r) { |
| dbgprintf("Failed to initialize Radeon, disabling IOCTL\n"); |
| // radeon_device_fini(rdev); |
| return r; |
| } |
| return 0; |
| } |
| int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent) |
| { |
| struct drm_device *dev; |
| int ret; |
| dbgprintf("%s\n\r",__FUNCTION__); |
| dev = malloc(sizeof(*dev)); |
| if (!dev) |
| return -ENOMEM; |
| // ret = pci_enable_device(pdev); |
| // if (ret) |
| // goto err_g1; |
| // pci_set_master(pdev); |
| // if ((ret = drm_fill_in_dev(dev, pdev, ent, driver))) { |
| // printk(KERN_ERR "DRM: Fill_in_dev failed.\n"); |
| // goto err_g2; |
| // } |
| dev->pdev = pdev; |
| dev->pci_device = pdev->device; |
| dev->pci_vendor = pdev->vendor; |
| // if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
| // pci_set_drvdata(pdev, dev); |
| // ret = drm_get_minor(dev, &dev->control, DRM_MINOR_CONTROL); |
| // if (ret) |
| // goto err_g2; |
| // } |
| // if ((ret = drm_get_minor(dev, &dev->primary, DRM_MINOR_LEGACY))) |
| // goto err_g3; |
| // if (dev->driver->load) { |
| // ret = dev->driver->load(dev, ent->driver_data); |
| // if (ret) |
| // goto err_g4; |
| // } |
| ret = radeon_driver_load_kms(dev, ent->driver_data ); |
| if (ret) |
| goto err_g4; |
| // list_add_tail(&dev->driver_item, &driver->device_list); |
| // DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n", |
| // driver->name, driver->major, driver->minor, driver->patchlevel, |
| // driver->date, pci_name(pdev), dev->primary->index); |
| return 0; |
| err_g4: |
| // drm_put_minor(&dev->primary); |
| //err_g3: |
| // if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| // drm_put_minor(&dev->control); |
| //err_g2: |
| // pci_disable_device(pdev); |
| //err_g1: |
| free(dev); |
| return ret; |
| } |
| resource_size_t drm_get_resource_start(struct drm_device *dev, unsigned int resource) |
| { |
| return pci_resource_start(dev->pdev, resource); |
| } |
| resource_size_t drm_get_resource_len(struct drm_device *dev, unsigned int resource) |
| { |
| return pci_resource_len(dev->pdev, resource); |
| } |
| /drivers/video/drm/radeon/radeon_drm.h |
|---|
| 0,0 → 1,884 |
| /* radeon_drm.h -- Public header for the radeon driver -*- linux-c -*- |
| * |
| * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. |
| * Copyright 2000 VA Linux Systems, Inc., Fremont, California. |
| * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. |
| * All rights reserved. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice (including the next |
| * paragraph) shall be included in all copies or substantial portions of the |
| * Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| * DEALINGS IN THE SOFTWARE. |
| * |
| * Authors: |
| * Kevin E. Martin <martin@valinux.com> |
| * Gareth Hughes <gareth@valinux.com> |
| * Keith Whitwell <keith@tungstengraphics.com> |
| */ |
| #ifndef __RADEON_DRM_H__ |
| #define __RADEON_DRM_H__ |
| #include "types.h" |
| /* WARNING: If you change any of these defines, make sure to change the |
| * defines in the X server file (radeon_sarea.h) |
| */ |
| #ifndef __RADEON_SAREA_DEFINES__ |
| #define __RADEON_SAREA_DEFINES__ |
| /* Old style state flags, required for sarea interface (1.1 and 1.2 |
| * clears) and 1.2 drm_vertex2 ioctl. |
| */ |
| #define RADEON_UPLOAD_CONTEXT 0x00000001 |
| #define RADEON_UPLOAD_VERTFMT 0x00000002 |
| #define RADEON_UPLOAD_LINE 0x00000004 |
| #define RADEON_UPLOAD_BUMPMAP 0x00000008 |
| #define RADEON_UPLOAD_MASKS 0x00000010 |
| #define RADEON_UPLOAD_VIEWPORT 0x00000020 |
| #define RADEON_UPLOAD_SETUP 0x00000040 |
| #define RADEON_UPLOAD_TCL 0x00000080 |
| #define RADEON_UPLOAD_MISC 0x00000100 |
| #define RADEON_UPLOAD_TEX0 0x00000200 |
| #define RADEON_UPLOAD_TEX1 0x00000400 |
| #define RADEON_UPLOAD_TEX2 0x00000800 |
| #define RADEON_UPLOAD_TEX0IMAGES 0x00001000 |
| #define RADEON_UPLOAD_TEX1IMAGES 0x00002000 |
| #define RADEON_UPLOAD_TEX2IMAGES 0x00004000 |
| #define RADEON_UPLOAD_CLIPRECTS 0x00008000 /* handled client-side */ |
| #define RADEON_REQUIRE_QUIESCENCE 0x00010000 |
| #define RADEON_UPLOAD_ZBIAS 0x00020000 /* version 1.2 and newer */ |
| #define RADEON_UPLOAD_ALL 0x003effff |
| #define RADEON_UPLOAD_CONTEXT_ALL 0x003e01ff |
| /* New style per-packet identifiers for use in cmd_buffer ioctl with |
| * the RADEON_EMIT_PACKET command. Comments relate new packets to old |
| * state bits and the packet size: |
| */ |
| #define RADEON_EMIT_PP_MISC 0 /* context/7 */ |
| #define RADEON_EMIT_PP_CNTL 1 /* context/3 */ |
| #define RADEON_EMIT_RB3D_COLORPITCH 2 /* context/1 */ |
| #define RADEON_EMIT_RE_LINE_PATTERN 3 /* line/2 */ |
| #define RADEON_EMIT_SE_LINE_WIDTH 4 /* line/1 */ |
| #define RADEON_EMIT_PP_LUM_MATRIX 5 /* bumpmap/1 */ |
| #define RADEON_EMIT_PP_ROT_MATRIX_0 6 /* bumpmap/2 */ |
| #define RADEON_EMIT_RB3D_STENCILREFMASK 7 /* masks/3 */ |
| #define RADEON_EMIT_SE_VPORT_XSCALE 8 /* viewport/6 */ |
| #define RADEON_EMIT_SE_CNTL 9 /* setup/2 */ |
| #define RADEON_EMIT_SE_CNTL_STATUS 10 /* setup/1 */ |
| #define RADEON_EMIT_RE_MISC 11 /* misc/1 */ |
| #define RADEON_EMIT_PP_TXFILTER_0 12 /* tex0/6 */ |
| #define RADEON_EMIT_PP_BORDER_COLOR_0 13 /* tex0/1 */ |
| #define RADEON_EMIT_PP_TXFILTER_1 14 /* tex1/6 */ |
| #define RADEON_EMIT_PP_BORDER_COLOR_1 15 /* tex1/1 */ |
| #define RADEON_EMIT_PP_TXFILTER_2 16 /* tex2/6 */ |
| #define RADEON_EMIT_PP_BORDER_COLOR_2 17 /* tex2/1 */ |
| #define RADEON_EMIT_SE_ZBIAS_FACTOR 18 /* zbias/2 */ |
| #define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19 /* tcl/11 */ |
| #define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20 /* material/17 */ |
| #define R200_EMIT_PP_TXCBLEND_0 21 /* tex0/4 */ |
| #define R200_EMIT_PP_TXCBLEND_1 22 /* tex1/4 */ |
| #define R200_EMIT_PP_TXCBLEND_2 23 /* tex2/4 */ |
| #define R200_EMIT_PP_TXCBLEND_3 24 /* tex3/4 */ |
| #define R200_EMIT_PP_TXCBLEND_4 25 /* tex4/4 */ |
| #define R200_EMIT_PP_TXCBLEND_5 26 /* tex5/4 */ |
| #define R200_EMIT_PP_TXCBLEND_6 27 /* /4 */ |
| #define R200_EMIT_PP_TXCBLEND_7 28 /* /4 */ |
| #define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29 /* tcl/7 */ |
| #define R200_EMIT_TFACTOR_0 30 /* tf/7 */ |
| #define R200_EMIT_VTX_FMT_0 31 /* vtx/5 */ |
| #define R200_EMIT_VAP_CTL 32 /* vap/1 */ |
| #define R200_EMIT_MATRIX_SELECT_0 33 /* msl/5 */ |
| #define R200_EMIT_TEX_PROC_CTL_2 34 /* tcg/5 */ |
| #define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35 /* tcl/1 */ |
| #define R200_EMIT_PP_TXFILTER_0 36 /* tex0/6 */ |
| #define R200_EMIT_PP_TXFILTER_1 37 /* tex1/6 */ |
| #define R200_EMIT_PP_TXFILTER_2 38 /* tex2/6 */ |
| #define R200_EMIT_PP_TXFILTER_3 39 /* tex3/6 */ |
| #define R200_EMIT_PP_TXFILTER_4 40 /* tex4/6 */ |
| #define R200_EMIT_PP_TXFILTER_5 41 /* tex5/6 */ |
| #define R200_EMIT_PP_TXOFFSET_0 42 /* tex0/1 */ |
| #define R200_EMIT_PP_TXOFFSET_1 43 /* tex1/1 */ |
| #define R200_EMIT_PP_TXOFFSET_2 44 /* tex2/1 */ |
| #define R200_EMIT_PP_TXOFFSET_3 45 /* tex3/1 */ |
| #define R200_EMIT_PP_TXOFFSET_4 46 /* tex4/1 */ |
| #define R200_EMIT_PP_TXOFFSET_5 47 /* tex5/1 */ |
| #define R200_EMIT_VTE_CNTL 48 /* vte/1 */ |
| #define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 /* vtx/1 */ |
| #define R200_EMIT_PP_TAM_DEBUG3 50 /* tam/1 */ |
| #define R200_EMIT_PP_CNTL_X 51 /* cst/1 */ |
| #define R200_EMIT_RB3D_DEPTHXY_OFFSET 52 /* cst/1 */ |
| #define R200_EMIT_RE_AUX_SCISSOR_CNTL 53 /* cst/1 */ |
| #define R200_EMIT_RE_SCISSOR_TL_0 54 /* cst/2 */ |
| #define R200_EMIT_RE_SCISSOR_TL_1 55 /* cst/2 */ |
| #define R200_EMIT_RE_SCISSOR_TL_2 56 /* cst/2 */ |
| #define R200_EMIT_SE_VAP_CNTL_STATUS 57 /* cst/1 */ |
| #define R200_EMIT_SE_VTX_STATE_CNTL 58 /* cst/1 */ |
| #define R200_EMIT_RE_POINTSIZE 59 /* cst/1 */ |
| #define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60 /* cst/4 */ |
| #define R200_EMIT_PP_CUBIC_FACES_0 61 |
| #define R200_EMIT_PP_CUBIC_OFFSETS_0 62 |
| #define R200_EMIT_PP_CUBIC_FACES_1 63 |
| #define R200_EMIT_PP_CUBIC_OFFSETS_1 64 |
| #define R200_EMIT_PP_CUBIC_FACES_2 65 |
| #define R200_EMIT_PP_CUBIC_OFFSETS_2 66 |
| #define R200_EMIT_PP_CUBIC_FACES_3 67 |
| #define R200_EMIT_PP_CUBIC_OFFSETS_3 68 |
| #define R200_EMIT_PP_CUBIC_FACES_4 69 |
| #define R200_EMIT_PP_CUBIC_OFFSETS_4 70 |
| #define R200_EMIT_PP_CUBIC_FACES_5 71 |
| #define R200_EMIT_PP_CUBIC_OFFSETS_5 72 |
| #define RADEON_EMIT_PP_TEX_SIZE_0 73 |
| #define RADEON_EMIT_PP_TEX_SIZE_1 74 |
| #define RADEON_EMIT_PP_TEX_SIZE_2 75 |
| #define R200_EMIT_RB3D_BLENDCOLOR 76 |
| #define R200_EMIT_TCL_POINT_SPRITE_CNTL 77 |
| #define RADEON_EMIT_PP_CUBIC_FACES_0 78 |
| #define RADEON_EMIT_PP_CUBIC_OFFSETS_T0 79 |
| #define RADEON_EMIT_PP_CUBIC_FACES_1 80 |
| #define RADEON_EMIT_PP_CUBIC_OFFSETS_T1 81 |
| #define RADEON_EMIT_PP_CUBIC_FACES_2 82 |
| #define RADEON_EMIT_PP_CUBIC_OFFSETS_T2 83 |
| #define R200_EMIT_PP_TRI_PERF_CNTL 84 |
| #define R200_EMIT_PP_AFS_0 85 |
| #define R200_EMIT_PP_AFS_1 86 |
| #define R200_EMIT_ATF_TFACTOR 87 |
| #define R200_EMIT_PP_TXCTLALL_0 88 |
| #define R200_EMIT_PP_TXCTLALL_1 89 |
| #define R200_EMIT_PP_TXCTLALL_2 90 |
| #define R200_EMIT_PP_TXCTLALL_3 91 |
| #define R200_EMIT_PP_TXCTLALL_4 92 |
| #define R200_EMIT_PP_TXCTLALL_5 93 |
| #define R200_EMIT_VAP_PVS_CNTL 94 |
| #define RADEON_MAX_STATE_PACKETS 95 |
| /* Commands understood by cmd_buffer ioctl. More can be added but |
| * obviously these can't be removed or changed: |
| */ |
| #define RADEON_CMD_PACKET 1 /* emit one of the register packets above */ |
| #define RADEON_CMD_SCALARS 2 /* emit scalar data */ |
| #define RADEON_CMD_VECTORS 3 /* emit vector data */ |
| #define RADEON_CMD_DMA_DISCARD 4 /* discard current dma buf */ |
| #define RADEON_CMD_PACKET3 5 /* emit hw packet */ |
| #define RADEON_CMD_PACKET3_CLIP 6 /* emit hw packet wrapped in cliprects */ |
| #define RADEON_CMD_SCALARS2 7 /* r200 stopgap */ |
| #define RADEON_CMD_WAIT 8 /* emit hw wait commands -- note: |
| * doesn't make the cpu wait, just |
| * the graphics hardware */ |
| #define RADEON_CMD_VECLINEAR 9 /* another r200 stopgap */ |
| typedef union { |
| int i; |
| struct { |
| unsigned char cmd_type, pad0, pad1, pad2; |
| } header; |
| struct { |
| unsigned char cmd_type, packet_id, pad0, pad1; |
| } packet; |
| struct { |
| unsigned char cmd_type, offset, stride, count; |
| } scalars; |
| struct { |
| unsigned char cmd_type, offset, stride, count; |
| } vectors; |
| struct { |
| unsigned char cmd_type, addr_lo, addr_hi, count; |
| } veclinear; |
| struct { |
| unsigned char cmd_type, buf_idx, pad0, pad1; |
| } dma; |
| struct { |
| unsigned char cmd_type, flags, pad0, pad1; |
| } wait; |
| } drm_radeon_cmd_header_t; |
| #define RADEON_WAIT_2D 0x1 |
| #define RADEON_WAIT_3D 0x2 |
| /* Allowed parameters for R300_CMD_PACKET3 |
| */ |
| #define R300_CMD_PACKET3_CLEAR 0 |
| #define R300_CMD_PACKET3_RAW 1 |
| /* Commands understood by cmd_buffer ioctl for R300. |
| * The interface has not been stabilized, so some of these may be removed |
| * and eventually reordered before stabilization. |
| */ |
| #define R300_CMD_PACKET0 1 |
| #define R300_CMD_VPU 2 /* emit vertex program upload */ |
| #define R300_CMD_PACKET3 3 /* emit a packet3 */ |
| #define R300_CMD_END3D 4 /* emit sequence ending 3d rendering */ |
| #define R300_CMD_CP_DELAY 5 |
| #define R300_CMD_DMA_DISCARD 6 |
| #define R300_CMD_WAIT 7 |
| # define R300_WAIT_2D 0x1 |
| # define R300_WAIT_3D 0x2 |
| /* these two defines are DOING IT WRONG - however |
| * we have userspace which relies on using these. |
| * The wait interface is backwards compat new |
| * code should use the NEW_WAIT defines below |
| * THESE ARE NOT BIT FIELDS |
| */ |
| # define R300_WAIT_2D_CLEAN 0x3 |
| # define R300_WAIT_3D_CLEAN 0x4 |
| # define R300_NEW_WAIT_2D_3D 0x3 |
| # define R300_NEW_WAIT_2D_2D_CLEAN 0x4 |
| # define R300_NEW_WAIT_3D_3D_CLEAN 0x6 |
| # define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN 0x8 |
| #define R300_CMD_SCRATCH 8 |
| #define R300_CMD_R500FP 9 |
| typedef union { |
| unsigned int u; |
| struct { |
| unsigned char cmd_type, pad0, pad1, pad2; |
| } header; |
| struct { |
| unsigned char cmd_type, count, reglo, reghi; |
| } packet0; |
| struct { |
| unsigned char cmd_type, count, adrlo, adrhi; |
| } vpu; |
| struct { |
| unsigned char cmd_type, packet, pad0, pad1; |
| } packet3; |
| struct { |
| unsigned char cmd_type, packet; |
| unsigned short count; /* amount of packet2 to emit */ |
| } delay; |
| struct { |
| unsigned char cmd_type, buf_idx, pad0, pad1; |
| } dma; |
| struct { |
| unsigned char cmd_type, flags, pad0, pad1; |
| } wait; |
| struct { |
| unsigned char cmd_type, reg, n_bufs, flags; |
| } scratch; |
| struct { |
| unsigned char cmd_type, count, adrlo, adrhi_flags; |
| } r500fp; |
| } drm_r300_cmd_header_t; |
| #define RADEON_FRONT 0x1 |
| #define RADEON_BACK 0x2 |
| #define RADEON_DEPTH 0x4 |
| #define RADEON_STENCIL 0x8 |
| #define RADEON_CLEAR_FASTZ 0x80000000 |
| #define RADEON_USE_HIERZ 0x40000000 |
| #define RADEON_USE_COMP_ZBUF 0x20000000 |
| #define R500FP_CONSTANT_TYPE (1 << 1) |
| #define R500FP_CONSTANT_CLAMP (1 << 2) |
| /* Primitive types |
| */ |
| #define RADEON_POINTS 0x1 |
| #define RADEON_LINES 0x2 |
| #define RADEON_LINE_STRIP 0x3 |
| #define RADEON_TRIANGLES 0x4 |
| #define RADEON_TRIANGLE_FAN 0x5 |
| #define RADEON_TRIANGLE_STRIP 0x6 |
| /* Vertex/indirect buffer size |
| */ |
| #define RADEON_BUFFER_SIZE 65536 |
| /* Byte offsets for indirect buffer data |
| */ |
| #define RADEON_INDEX_PRIM_OFFSET 20 |
| #define RADEON_SCRATCH_REG_OFFSET 32 |
| #define R600_SCRATCH_REG_OFFSET 256 |
| #define RADEON_NR_SAREA_CLIPRECTS 12 |
| /* There are 2 heaps (local/GART). Each region within a heap is a |
| * minimum of 64k, and there are at most 64 of them per heap. |
| */ |
| #define RADEON_LOCAL_TEX_HEAP 0 |
| #define RADEON_GART_TEX_HEAP 1 |
| #define RADEON_NR_TEX_HEAPS 2 |
| #define RADEON_NR_TEX_REGIONS 64 |
| #define RADEON_LOG_TEX_GRANULARITY 16 |
| #define RADEON_MAX_TEXTURE_LEVELS 12 |
| #define RADEON_MAX_TEXTURE_UNITS 3 |
| #define RADEON_MAX_SURFACES 8 |
| /* Blits have strict offset rules. All blit offset must be aligned on |
| * a 1K-byte boundary. |
| */ |
| #define RADEON_OFFSET_SHIFT 10 |
| #define RADEON_OFFSET_ALIGN (1 << RADEON_OFFSET_SHIFT) |
| #define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1) |
| #endif /* __RADEON_SAREA_DEFINES__ */ |
| typedef struct { |
| unsigned int red; |
| unsigned int green; |
| unsigned int blue; |
| unsigned int alpha; |
| } radeon_color_regs_t; |
| typedef struct { |
| /* Context state */ |
| unsigned int pp_misc; /* 0x1c14 */ |
| unsigned int pp_fog_color; |
| unsigned int re_solid_color; |
| unsigned int rb3d_blendcntl; |
| unsigned int rb3d_depthoffset; |
| unsigned int rb3d_depthpitch; |
| unsigned int rb3d_zstencilcntl; |
| unsigned int pp_cntl; /* 0x1c38 */ |
| unsigned int rb3d_cntl; |
| unsigned int rb3d_coloroffset; |
| unsigned int re_width_height; |
| unsigned int rb3d_colorpitch; |
| unsigned int se_cntl; |
| /* Vertex format state */ |
| unsigned int se_coord_fmt; /* 0x1c50 */ |
| /* Line state */ |
| unsigned int re_line_pattern; /* 0x1cd0 */ |
| unsigned int re_line_state; |
| unsigned int se_line_width; /* 0x1db8 */ |
| /* Bumpmap state */ |
| unsigned int pp_lum_matrix; /* 0x1d00 */ |
| unsigned int pp_rot_matrix_0; /* 0x1d58 */ |
| unsigned int pp_rot_matrix_1; |
| /* Mask state */ |
| unsigned int rb3d_stencilrefmask; /* 0x1d7c */ |
| unsigned int rb3d_ropcntl; |
| unsigned int rb3d_planemask; |
| /* Viewport state */ |
| unsigned int se_vport_xscale; /* 0x1d98 */ |
| unsigned int se_vport_xoffset; |
| unsigned int se_vport_yscale; |
| unsigned int se_vport_yoffset; |
| unsigned int se_vport_zscale; |
| unsigned int se_vport_zoffset; |
| /* Setup state */ |
| unsigned int se_cntl_status; /* 0x2140 */ |
| /* Misc state */ |
| unsigned int re_top_left; /* 0x26c0 */ |
| unsigned int re_misc; |
| } drm_radeon_context_regs_t; |
| typedef struct { |
| /* Zbias state */ |
| unsigned int se_zbias_factor; /* 0x1dac */ |
| unsigned int se_zbias_constant; |
| } drm_radeon_context2_regs_t; |
| /* Setup registers for each texture unit |
| */ |
| typedef struct { |
| unsigned int pp_txfilter; |
| unsigned int pp_txformat; |
| unsigned int pp_txoffset; |
| unsigned int pp_txcblend; |
| unsigned int pp_txablend; |
| unsigned int pp_tfactor; |
| unsigned int pp_border_color; |
| } drm_radeon_texture_regs_t; |
| typedef struct { |
| unsigned int start; |
| unsigned int finish; |
| unsigned int prim:8; |
| unsigned int stateidx:8; |
| unsigned int numverts:16; /* overloaded as offset/64 for elt prims */ |
| unsigned int vc_format; /* vertex format */ |
| } drm_radeon_prim_t; |
| typedef struct { |
| drm_radeon_context_regs_t context; |
| drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS]; |
| drm_radeon_context2_regs_t context2; |
| unsigned int dirty; |
| } drm_radeon_state_t; |
| typedef struct { |
| /* The channel for communication of state information to the |
| * kernel on firing a vertex buffer with either of the |
| * obsoleted vertex/index ioctls. |
| */ |
| drm_radeon_context_regs_t context_state; |
| drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS]; |
| unsigned int dirty; |
| unsigned int vertsize; |
| unsigned int vc_format; |
| /* The current cliprects, or a subset thereof. |
| */ |
| // struct drm_clip_rect boxes[RADEON_NR_SAREA_CLIPRECTS]; |
| unsigned int nbox; |
| /* Counters for client-side throttling of rendering clients. |
| */ |
| unsigned int last_frame; |
| unsigned int last_dispatch; |
| unsigned int last_clear; |
| // struct drm_tex_region tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS + |
| // 1]; |
| unsigned int tex_age[RADEON_NR_TEX_HEAPS]; |
| int ctx_owner; |
| int pfState; /* number of 3d windows (0,1,2ormore) */ |
| int pfCurrentPage; /* which buffer is being displayed? */ |
| int crtc2_base; /* CRTC2 frame offset */ |
| int tiling_enabled; /* set by drm, read by 2d + 3d clients */ |
| } drm_radeon_sarea_t; |
| /* WARNING: If you change any of these defines, make sure to change the |
| * defines in the Xserver file (xf86drmRadeon.h) |
| * |
| * KW: actually it's illegal to change any of this (backwards compatibility). |
| */ |
| /* Radeon specific ioctls |
| * The device specific ioctl range is 0x40 to 0x79. |
| */ |
| #define DRM_RADEON_CP_INIT 0x00 |
| #define DRM_RADEON_CP_START 0x01 |
| #define DRM_RADEON_CP_STOP 0x02 |
| #define DRM_RADEON_CP_RESET 0x03 |
| #define DRM_RADEON_CP_IDLE 0x04 |
| #define DRM_RADEON_RESET 0x05 |
| #define DRM_RADEON_FULLSCREEN 0x06 |
| #define DRM_RADEON_SWAP 0x07 |
| #define DRM_RADEON_CLEAR 0x08 |
| #define DRM_RADEON_VERTEX 0x09 |
| #define DRM_RADEON_INDICES 0x0A |
| #define DRM_RADEON_NOT_USED |
| #define DRM_RADEON_STIPPLE 0x0C |
| #define DRM_RADEON_INDIRECT 0x0D |
| #define DRM_RADEON_TEXTURE 0x0E |
| #define DRM_RADEON_VERTEX2 0x0F |
| #define DRM_RADEON_CMDBUF 0x10 |
| #define DRM_RADEON_GETPARAM 0x11 |
| #define DRM_RADEON_FLIP 0x12 |
| #define DRM_RADEON_ALLOC 0x13 |
| #define DRM_RADEON_FREE 0x14 |
| #define DRM_RADEON_INIT_HEAP 0x15 |
| #define DRM_RADEON_IRQ_EMIT 0x16 |
| #define DRM_RADEON_IRQ_WAIT 0x17 |
| #define DRM_RADEON_CP_RESUME 0x18 |
| #define DRM_RADEON_SETPARAM 0x19 |
| #define DRM_RADEON_SURF_ALLOC 0x1a |
| #define DRM_RADEON_SURF_FREE 0x1b |
| /* KMS ioctl */ |
| #define DRM_RADEON_GEM_INFO 0x1c |
| #define DRM_RADEON_GEM_CREATE 0x1d |
| #define DRM_RADEON_GEM_MMAP 0x1e |
| #define DRM_RADEON_GEM_PREAD 0x21 |
| #define DRM_RADEON_GEM_PWRITE 0x22 |
| #define DRM_RADEON_GEM_SET_DOMAIN 0x23 |
| #define DRM_RADEON_GEM_WAIT_IDLE 0x24 |
| #define DRM_RADEON_CS 0x26 |
| #define DRM_RADEON_INFO 0x27 |
| #define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t) |
| #define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START) |
| #define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t) |
| #define DRM_IOCTL_RADEON_CP_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESET) |
| #define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE) |
| #define DRM_IOCTL_RADEON_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_RESET) |
| #define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t) |
| #define DRM_IOCTL_RADEON_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_SWAP) |
| #define DRM_IOCTL_RADEON_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t) |
| #define DRM_IOCTL_RADEON_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t) |
| #define DRM_IOCTL_RADEON_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t) |
| #define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t) |
| #define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t) |
| #define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t) |
| #define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t) |
| #define DRM_IOCTL_RADEON_CMDBUF DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t) |
| #define DRM_IOCTL_RADEON_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t) |
| #define DRM_IOCTL_RADEON_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_FLIP) |
| #define DRM_IOCTL_RADEON_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t) |
| #define DRM_IOCTL_RADEON_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t) |
| #define DRM_IOCTL_RADEON_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t) |
| #define DRM_IOCTL_RADEON_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t) |
| #define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t) |
| #define DRM_IOCTL_RADEON_CP_RESUME DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME) |
| #define DRM_IOCTL_RADEON_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t) |
| #define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t) |
| #define DRM_IOCTL_RADEON_SURF_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t) |
| /* KMS */ |
| #define DRM_IOCTL_RADEON_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_INFO, struct drm_radeon_gem_info) |
| #define DRM_IOCTL_RADEON_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_CREATE, struct drm_radeon_gem_create) |
| #define DRM_IOCTL_RADEON_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_MMAP, struct drm_radeon_gem_mmap) |
| #define DRM_IOCTL_RADEON_GEM_PREAD DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PREAD, struct drm_radeon_gem_pread) |
| #define DRM_IOCTL_RADEON_GEM_PWRITE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PWRITE, struct drm_radeon_gem_pwrite) |
| #define DRM_IOCTL_RADEON_GEM_SET_DOMAIN DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_DOMAIN, struct drm_radeon_gem_set_domain) |
| #define DRM_IOCTL_RADEON_GEM_WAIT_IDLE DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_GEM_WAIT_IDLE, struct drm_radeon_gem_wait_idle) |
| #define DRM_IOCTL_RADEON_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS, struct drm_radeon_cs) |
| #define DRM_IOCTL_RADEON_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INFO, struct drm_radeon_info) |
| typedef struct drm_radeon_init { |
| enum { |
| RADEON_INIT_CP = 0x01, |
| RADEON_CLEANUP_CP = 0x02, |
| RADEON_INIT_R200_CP = 0x03, |
| RADEON_INIT_R300_CP = 0x04, |
| RADEON_INIT_R600_CP = 0x05 |
| } func; |
| unsigned long sarea_priv_offset; |
| int is_pci; |
| int cp_mode; |
| int gart_size; |
| int ring_size; |
| int usec_timeout; |
| unsigned int fb_bpp; |
| unsigned int front_offset, front_pitch; |
| unsigned int back_offset, back_pitch; |
| unsigned int depth_bpp; |
| unsigned int depth_offset, depth_pitch; |
| unsigned long fb_offset; |
| unsigned long mmio_offset; |
| unsigned long ring_offset; |
| unsigned long ring_rptr_offset; |
| unsigned long buffers_offset; |
| unsigned long gart_textures_offset; |
| } drm_radeon_init_t; |
| typedef struct drm_radeon_cp_stop { |
| int flush; |
| int idle; |
| } drm_radeon_cp_stop_t; |
| typedef struct drm_radeon_fullscreen { |
| enum { |
| RADEON_INIT_FULLSCREEN = 0x01, |
| RADEON_CLEANUP_FULLSCREEN = 0x02 |
| } func; |
| } drm_radeon_fullscreen_t; |
| #define CLEAR_X1 0 |
| #define CLEAR_Y1 1 |
| #define CLEAR_X2 2 |
| #define CLEAR_Y2 3 |
| #define CLEAR_DEPTH 4 |
| typedef union drm_radeon_clear_rect { |
| float f[5]; |
| unsigned int ui[5]; |
| } drm_radeon_clear_rect_t; |
| typedef struct drm_radeon_clear { |
| unsigned int flags; |
| unsigned int clear_color; |
| unsigned int clear_depth; |
| unsigned int color_mask; |
| unsigned int depth_mask; /* misnamed field: should be stencil */ |
| // drm_radeon_clear_rect_t __user *depth_boxes; |
| } drm_radeon_clear_t; |
| typedef struct drm_radeon_vertex { |
| int prim; |
| int idx; /* Index of vertex buffer */ |
| int count; /* Number of vertices in buffer */ |
| int discard; /* Client finished with buffer? */ |
| } drm_radeon_vertex_t; |
| typedef struct drm_radeon_indices { |
| int prim; |
| int idx; |
| int start; |
| int end; |
| int discard; /* Client finished with buffer? */ |
| } drm_radeon_indices_t; |
| /* v1.2 - obsoletes drm_radeon_vertex and drm_radeon_indices |
| * - allows multiple primitives and state changes in a single ioctl |
| * - supports driver change to emit native primitives |
| */ |
| typedef struct drm_radeon_vertex2 { |
| int idx; /* Index of vertex buffer */ |
| int discard; /* Client finished with buffer? */ |
| int nr_states; |
| // drm_radeon_state_t __user *state; |
| int nr_prims; |
| // drm_radeon_prim_t __user *prim; |
| } drm_radeon_vertex2_t; |
| /* v1.3 - obsoletes drm_radeon_vertex2 |
| * - allows arbitarily large cliprect list |
| * - allows updating of tcl packet, vector and scalar state |
| * - allows memory-efficient description of state updates |
| * - allows state to be emitted without a primitive |
| * (for clears, ctx switches) |
| * - allows more than one dma buffer to be referenced per ioctl |
| * - supports tcl driver |
| * - may be extended in future versions with new cmd types, packets |
| */ |
| typedef struct drm_radeon_cmd_buffer { |
| int bufsz; |
| char __user *buf; |
| int nbox; |
| struct drm_clip_rect __user *boxes; |
| } drm_radeon_cmd_buffer_t; |
| typedef struct drm_radeon_tex_image { |
| unsigned int x, y; /* Blit coordinates */ |
| unsigned int width, height; |
| const void __user *data; |
| } drm_radeon_tex_image_t; |
| typedef struct drm_radeon_texture { |
| unsigned int offset; |
| int pitch; |
| int format; |
| int width; /* Texture image coordinates */ |
| int height; |
| drm_radeon_tex_image_t __user *image; |
| } drm_radeon_texture_t; |
| typedef struct drm_radeon_stipple { |
| unsigned int __user *mask; |
| } drm_radeon_stipple_t; |
| typedef struct drm_radeon_indirect { |
| int idx; |
| int start; |
| int end; |
| int discard; |
| } drm_radeon_indirect_t; |
| /* enum for card type parameters */ |
| #define RADEON_CARD_PCI 0 |
| #define RADEON_CARD_AGP 1 |
| #define RADEON_CARD_PCIE 2 |
| /* 1.3: An ioctl to get parameters that aren't available to the 3d |
| * client any other way. |
| */ |
| #define RADEON_PARAM_GART_BUFFER_OFFSET 1 /* card offset of 1st GART buffer */ |
| #define RADEON_PARAM_LAST_FRAME 2 |
| #define RADEON_PARAM_LAST_DISPATCH 3 |
| #define RADEON_PARAM_LAST_CLEAR 4 |
| /* Added with DRM version 1.6. */ |
| #define RADEON_PARAM_IRQ_NR 5 |
| #define RADEON_PARAM_GART_BASE 6 /* card offset of GART base */ |
| /* Added with DRM version 1.8. */ |
| #define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */ |
| #define RADEON_PARAM_STATUS_HANDLE 8 |
| #define RADEON_PARAM_SAREA_HANDLE 9 |
| #define RADEON_PARAM_GART_TEX_HANDLE 10 |
| #define RADEON_PARAM_SCRATCH_OFFSET 11 |
| #define RADEON_PARAM_CARD_TYPE 12 |
| #define RADEON_PARAM_VBLANK_CRTC 13 /* VBLANK CRTC */ |
| #define RADEON_PARAM_FB_LOCATION 14 /* FB location */ |
| #define RADEON_PARAM_NUM_GB_PIPES 15 /* num GB pipes */ |
| #define RADEON_PARAM_DEVICE_ID 16 |
| typedef struct drm_radeon_getparam { |
| int param; |
| void __user *value; |
| } drm_radeon_getparam_t; |
| /* 1.6: Set up a memory manager for regions of shared memory: |
| */ |
| #define RADEON_MEM_REGION_GART 1 |
| #define RADEON_MEM_REGION_FB 2 |
| typedef struct drm_radeon_mem_alloc { |
| int region; |
| int alignment; |
| int size; |
| int __user *region_offset; /* offset from start of fb or GART */ |
| } drm_radeon_mem_alloc_t; |
| typedef struct drm_radeon_mem_free { |
| int region; |
| int region_offset; |
| } drm_radeon_mem_free_t; |
| typedef struct drm_radeon_mem_init_heap { |
| int region; |
| int size; |
| int start; |
| } drm_radeon_mem_init_heap_t; |
| /* 1.6: Userspace can request & wait on irq's: |
| */ |
| typedef struct drm_radeon_irq_emit { |
| int __user *irq_seq; |
| } drm_radeon_irq_emit_t; |
| typedef struct drm_radeon_irq_wait { |
| int irq_seq; |
| } drm_radeon_irq_wait_t; |
| /* 1.10: Clients tell the DRM where they think the framebuffer is located in |
| * the card's address space, via a new generic ioctl to set parameters |
| */ |
| typedef struct drm_radeon_setparam { |
| unsigned int param; |
| __s64 value; |
| } drm_radeon_setparam_t; |
| #define RADEON_SETPARAM_FB_LOCATION 1 /* determined framebuffer location */ |
| #define RADEON_SETPARAM_SWITCH_TILING 2 /* enable/disable color tiling */ |
| #define RADEON_SETPARAM_PCIGART_LOCATION 3 /* PCI Gart Location */ |
| #define RADEON_SETPARAM_NEW_MEMMAP 4 /* Use new memory map */ |
| #define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5 /* PCI GART Table Size */ |
| #define RADEON_SETPARAM_VBLANK_CRTC 6 /* VBLANK CRTC */ |
| /* 1.14: Clients can allocate/free a surface |
| */ |
| typedef struct drm_radeon_surface_alloc { |
| unsigned int address; |
| unsigned int size; |
| unsigned int flags; |
| } drm_radeon_surface_alloc_t; |
| typedef struct drm_radeon_surface_free { |
| unsigned int address; |
| } drm_radeon_surface_free_t; |
| #define DRM_RADEON_VBLANK_CRTC1 1 |
| #define DRM_RADEON_VBLANK_CRTC2 2 |
| /* |
| * Kernel modesetting world below. |
| */ |
| #define RADEON_GEM_DOMAIN_CPU 0x1 |
| #define RADEON_GEM_DOMAIN_GTT 0x2 |
| #define RADEON_GEM_DOMAIN_VRAM 0x4 |
| struct drm_radeon_gem_info { |
| uint64_t gart_size; |
| uint64_t vram_size; |
| uint64_t vram_visible; |
| }; |
| #define RADEON_GEM_NO_BACKING_STORE 1 |
| struct drm_radeon_gem_create { |
| uint64_t size; |
| uint64_t alignment; |
| uint32_t handle; |
| uint32_t initial_domain; |
| uint32_t flags; |
| }; |
| struct drm_radeon_gem_mmap { |
| uint32_t handle; |
| uint32_t pad; |
| uint64_t offset; |
| uint64_t size; |
| uint64_t addr_ptr; |
| }; |
| struct drm_radeon_gem_set_domain { |
| uint32_t handle; |
| uint32_t read_domains; |
| uint32_t write_domain; |
| }; |
| struct drm_radeon_gem_wait_idle { |
| uint32_t handle; |
| uint32_t pad; |
| }; |
| struct drm_radeon_gem_busy { |
| uint32_t handle; |
| uint32_t busy; |
| }; |
| struct drm_radeon_gem_pread { |
| /** Handle for the object being read. */ |
| uint32_t handle; |
| uint32_t pad; |
| /** Offset into the object to read from */ |
| uint64_t offset; |
| /** Length of data to read */ |
| uint64_t size; |
| /** Pointer to write the data into. */ |
| /* void *, but pointers are not 32/64 compatible */ |
| uint64_t data_ptr; |
| }; |
| struct drm_radeon_gem_pwrite { |
| /** Handle for the object being written to. */ |
| uint32_t handle; |
| uint32_t pad; |
| /** Offset into the object to write to */ |
| uint64_t offset; |
| /** Length of data to write */ |
| uint64_t size; |
| /** Pointer to read the data from. */ |
| /* void *, but pointers are not 32/64 compatible */ |
| uint64_t data_ptr; |
| }; |
| #define RADEON_CHUNK_ID_RELOCS 0x01 |
| #define RADEON_CHUNK_ID_IB 0x02 |
| struct drm_radeon_cs_chunk { |
| uint32_t chunk_id; |
| uint32_t length_dw; |
| uint64_t chunk_data; |
| }; |
| struct drm_radeon_cs_reloc { |
| uint32_t handle; |
| uint32_t read_domains; |
| uint32_t write_domain; |
| uint32_t flags; |
| }; |
| struct drm_radeon_cs { |
| uint32_t num_chunks; |
| uint32_t cs_id; |
| /* this points to uint64_t * which point to cs chunks */ |
| uint64_t chunks; |
| /* updates to the limits after this CS ioctl */ |
| uint64_t gart_limit; |
| uint64_t vram_limit; |
| }; |
| #define RADEON_INFO_DEVICE_ID 0x00 |
| #define RADEON_INFO_NUM_GB_PIPES 0x01 |
| struct drm_radeon_info { |
| uint32_t request; |
| uint32_t pad; |
| uint64_t value; |
| }; |
| #endif |
| /drivers/video/drm/radeon/radeon_microcode.h |
|---|
| 0,0 → 1,1844 |
| /* |
| * Copyright 2007 Advanced Micro Devices, Inc. |
| * All Rights Reserved. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice (including the next |
| * paragraph) shall be included in all copies or substantial portions of the |
| * Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE |
| * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION |
| * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION |
| * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| * |
| */ |
| #ifndef RADEON_MICROCODE_H |
| #define RADEON_MICROCODE_H |
| /* production radeon ucode r1xx-r6xx */ |
| static const u32 R100_cp_microcode[][2] = { |
| { 0x21007000, 0000000000 }, |
| { 0x20007000, 0000000000 }, |
| { 0x000000b4, 0x00000004 }, |
| { 0x000000b8, 0x00000004 }, |
| { 0x6f5b4d4c, 0000000000 }, |
| { 0x4c4c427f, 0000000000 }, |
| { 0x5b568a92, 0000000000 }, |
| { 0x4ca09c6d, 0000000000 }, |
| { 0xad4c4c4c, 0000000000 }, |
| { 0x4ce1af3d, 0000000000 }, |
| { 0xd8afafaf, 0000000000 }, |
| { 0xd64c4cdc, 0000000000 }, |
| { 0x4cd10d10, 0000000000 }, |
| { 0x000f0000, 0x00000016 }, |
| { 0x362f242d, 0000000000 }, |
| { 0x00000012, 0x00000004 }, |
| { 0x000f0000, 0x00000016 }, |
| { 0x362f282d, 0000000000 }, |
| { 0x000380e7, 0x00000002 }, |
| { 0x04002c97, 0x00000002 }, |
| { 0x000f0001, 0x00000016 }, |
| { 0x333a3730, 0000000000 }, |
| { 0x000077ef, 0x00000002 }, |
| { 0x00061000, 0x00000002 }, |
| { 0x00000021, 0x0000001a }, |
| { 0x00004000, 0x0000001e }, |
| { 0x00061000, 0x00000002 }, |
| { 0x00000021, 0x0000001a }, |
| { 0x00004000, 0x0000001e }, |
| { 0x00061000, 0x00000002 }, |
| { 0x00000021, 0x0000001a }, |
| { 0x00004000, 0x0000001e }, |
| { 0x00000017, 0x00000004 }, |
| { 0x0003802b, 0x00000002 }, |
| { 0x040067e0, 0x00000002 }, |
| { 0x00000017, 0x00000004 }, |
| { 0x000077e0, 0x00000002 }, |
| { 0x00065000, 0x00000002 }, |
| { 0x000037e1, 0x00000002 }, |
| { 0x040067e1, 0x00000006 }, |
| { 0x000077e0, 0x00000002 }, |
| { 0x000077e1, 0x00000002 }, |
| { 0x000077e1, 0x00000006 }, |
| { 0xffffffff, 0000000000 }, |
| { 0x10000000, 0000000000 }, |
| { 0x0003802b, 0x00000002 }, |
| { 0x040067e0, 0x00000006 }, |
| { 0x00007675, 0x00000002 }, |
| { 0x00007676, 0x00000002 }, |
| { 0x00007677, 0x00000002 }, |
| { 0x00007678, 0x00000006 }, |
| { 0x0003802c, 0x00000002 }, |
| { 0x04002676, 0x00000002 }, |
| { 0x00007677, 0x00000002 }, |
| { 0x00007678, 0x00000006 }, |
| { 0x0000002f, 0x00000018 }, |
| { 0x0000002f, 0x00000018 }, |
| { 0000000000, 0x00000006 }, |
| { 0x00000030, 0x00000018 }, |
| { 0x00000030, 0x00000018 }, |
| { 0000000000, 0x00000006 }, |
| { 0x01605000, 0x00000002 }, |
| { 0x00065000, 0x00000002 }, |
| { 0x00098000, 0x00000002 }, |
| { 0x00061000, 0x00000002 }, |
| { 0x64c0603e, 0x00000004 }, |
| { 0x000380e6, 0x00000002 }, |
| { 0x040025c5, 0x00000002 }, |
| { 0x00080000, 0x00000016 }, |
| { 0000000000, 0000000000 }, |
| { 0x0400251d, 0x00000002 }, |
| { 0x00007580, 0x00000002 }, |
| { 0x00067581, 0x00000002 }, |
| { 0x04002580, 0x00000002 }, |
| { 0x00067581, 0x00000002 }, |
| { 0x00000049, 0x00000004 }, |
| { 0x00005000, 0000000000 }, |
| { 0x000380e6, 0x00000002 }, |
| { 0x040025c5, 0x00000002 }, |
| { 0x00061000, 0x00000002 }, |
| { 0x0000750e, 0x00000002 }, |
| { 0x00019000, 0x00000002 }, |
| { 0x00011055, 0x00000014 }, |
| { 0x00000055, 0x00000012 }, |
| { 0x0400250f, 0x00000002 }, |
| { 0x0000504f, 0x00000004 }, |
| { 0x000380e6, 0x00000002 }, |
| { 0x040025c5, 0x00000002 }, |
| { 0x00007565, 0x00000002 }, |
| { 0x00007566, 0x00000002 }, |
| { 0x00000058, 0x00000004 }, |
| { 0x000380e6, 0x00000002 }, |
| { 0x040025c5, 0x00000002 }, |
| { 0x01e655b4, 0x00000002 }, |
| { 0x4401b0e4, 0x00000002 }, |
| { 0x01c110e4, 0x00000002 }, |
| { 0x26667066, 0x00000018 }, |
| { 0x040c2565, 0x00000002 }, |
| { 0x00000066, 0x00000018 }, |
| { 0x04002564, 0x00000002 }, |
| { 0x00007566, 0x00000002 }, |
| { 0x0000005d, 0x00000004 }, |
| { 0x00401069, 0x00000008 }, |
| { 0x00101000, 0x00000002 }, |
| { 0x000d80ff, 0x00000002 }, |
| { 0x0080006c, 0x00000008 }, |
| { 0x000f9000, 0x00000002 }, |
| { 0x000e00ff, 0x00000002 }, |
| { 0000000000, 0x00000006 }, |
| { 0x0000008f, 0x00000018 }, |
| { 0x0000005b, 0x00000004 }, |
| { 0x000380e6, 0x00000002 }, |
| { 0x040025c5, 0x00000002 }, |
| { 0x00007576, 0x00000002 }, |
| { 0x00065000, 0x00000002 }, |
| { 0x00009000, 0x00000002 }, |
| { 0x00041000, 0x00000002 }, |
| { 0x0c00350e, 0x00000002 }, |
| { 0x00049000, 0x00000002 }, |
| { 0x00051000, 0x00000002 }, |
| { 0x01e785f8, 0x00000002 }, |
| { 0x00200000, 0x00000002 }, |
| { 0x0060007e, 0x0000000c }, |
| { 0x00007563, 0x00000002 }, |
| { 0x006075f0, 0x00000021 }, |
| { 0x20007073, 0x00000004 }, |
| { 0x00005073, 0x00000004 }, |
| { 0x000380e6, 0x00000002 }, |
| { 0x040025c5, 0x00000002 }, |
| { 0x00007576, 0x00000002 }, |
| { 0x00007577, 0x00000002 }, |
| { 0x0000750e, 0x00000002 }, |
| { 0x0000750f, 0x00000002 }, |
| { 0x00a05000, 0x00000002 }, |
| { 0x00600083, 0x0000000c }, |
| { 0x006075f0, 0x00000021 }, |
| { 0x000075f8, 0x00000002 }, |
| { 0x00000083, 0x00000004 }, |
| { 0x000a750e, 0x00000002 }, |
| { 0x000380e6, 0x00000002 }, |
| { 0x040025c5, 0x00000002 }, |
| { 0x0020750f, 0x00000002 }, |
| { 0x00600086, 0x00000004 }, |
| { 0x00007570, 0x00000002 }, |
| { 0x00007571, 0x00000002 }, |
| { 0x00007572, 0x00000006 }, |
| { 0x000380e6, 0x00000002 }, |
| { 0x040025c5, 0x00000002 }, |
| { 0x00005000, 0x00000002 }, |
| { 0x00a05000, 0x00000002 }, |
| { 0x00007568, 0x00000002 }, |
| { 0x00061000, 0x00000002 }, |
| { 0x00000095, 0x0000000c }, |
| { 0x00058000, 0x00000002 }, |
| { 0x0c607562, 0x00000002 }, |
| { 0x00000097, 0x00000004 }, |
| { 0x000380e6, 0x00000002 }, |
| { 0x040025c5, 0x00000002 }, |
| { 0x00600096, 0x00000004 }, |
| { 0x400070e5, 0000000000 }, |
| { 0x000380e6, 0x00000002 }, |
| { 0x040025c5, 0x00000002 }, |
| { 0x000380e5, 0x00000002 }, |
| { 0x000000a8, 0x0000001c }, |
| { 0x000650aa, 0x00000018 }, |
| { 0x040025bb, 0x00000002 }, |
| { 0x000610ab, 0x00000018 }, |
| { 0x040075bc, 0000000000 }, |
| { 0x000075bb, 0x00000002 }, |
| { 0x000075bc, 0000000000 }, |
| { 0x00090000, 0x00000006 }, |
| { 0x00090000, 0x00000002 }, |
| { 0x000d8002, 0x00000006 }, |
| { 0x00007832, 0x00000002 }, |
| { 0x00005000, 0x00000002 }, |
| { 0x000380e7, 0x00000002 }, |
| { 0x04002c97, 0x00000002 }, |
| { 0x00007820, 0x00000002 }, |
| { 0x00007821, 0x00000002 }, |
| { 0x00007800, 0000000000 }, |
| { 0x01200000, 0x00000002 }, |
| { 0x20077000, 0x00000002 }, |
| { 0x01200000, 0x00000002 }, |
| { 0x20007000, 0x00000002 }, |
| { 0x00061000, 0x00000002 }, |
| { 0x0120751b, 0x00000002 }, |
| { 0x8040750a, 0x00000002 }, |
| { 0x8040750b, 0x00000002 }, |
| { 0x00110000, 0x00000002 }, |
| { 0x000380e5, 0x00000002 }, |
| { 0x000000c6, 0x0000001c }, |
| { 0x000610ab, 0x00000018 }, |
| { 0x844075bd, 0x00000002 }, |
| { 0x000610aa, 0x00000018 }, |
| { 0x840075bb, 0x00000002 }, |
| { 0x000610ab, 0x00000018 }, |
| { 0x844075bc, 0x00000002 }, |
| { 0x000000c9, 0x00000004 }, |
| { 0x804075bd, 0x00000002 }, |
| { 0x800075bb, 0x00000002 }, |
| { 0x804075bc, 0x00000002 }, |
| { 0x00108000, 0x00000002 }, |
| { 0x01400000, 0x00000002 }, |
| { 0x006000cd, 0x0000000c }, |
| { 0x20c07000, 0x00000020 }, |
| { 0x000000cf, 0x00000012 }, |
| { 0x00800000, 0x00000006 }, |
| { 0x0080751d, 0x00000006 }, |
| { 0000000000, 0000000000 }, |
| { 0x0000775c, 0x00000002 }, |
| { 0x00a05000, 0x00000002 }, |
| { 0x00661000, 0x00000002 }, |
| { 0x0460275d, 0x00000020 }, |
| { 0x00004000, 0000000000 }, |
| { 0x01e00830, 0x00000002 }, |
| { 0x21007000, 0000000000 }, |
| { 0x6464614d, 0000000000 }, |
| { 0x69687420, 0000000000 }, |
| { 0x00000073, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0x00005000, 0x00000002 }, |
| { 0x000380d0, 0x00000002 }, |
| { 0x040025e0, 0x00000002 }, |
| { 0x000075e1, 0000000000 }, |
| { 0x00000001, 0000000000 }, |
| { 0x000380e0, 0x00000002 }, |
| { 0x04002394, 0x00000002 }, |
| { 0x00005000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0x00000008, 0000000000 }, |
| { 0x00000004, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| }; |
| static const u32 R200_cp_microcode[][2] = { |
| { 0x21007000, 0000000000 }, |
| { 0x20007000, 0000000000 }, |
| { 0x000000bf, 0x00000004 }, |
| { 0x000000c3, 0x00000004 }, |
| { 0x7a685e5d, 0000000000 }, |
| { 0x5d5d5588, 0000000000 }, |
| { 0x68659197, 0000000000 }, |
| { 0x5da19f78, 0000000000 }, |
| { 0x5d5d5d5d, 0000000000 }, |
| { 0x5dee5d50, 0000000000 }, |
| { 0xf2acacac, 0000000000 }, |
| { 0xe75df9e9, 0000000000 }, |
| { 0xb1dd0e11, 0000000000 }, |
| { 0xe2afafaf, 0000000000 }, |
| { 0x000f0000, 0x00000016 }, |
| { 0x452f232d, 0000000000 }, |
| { 0x00000013, 0x00000004 }, |
| { 0x000f0000, 0x00000016 }, |
| { 0x452f272d, 0000000000 }, |
| { 0x000f0001, 0x00000016 }, |
| { 0x3e4d4a37, 0000000000 }, |
| { 0x000077ef, 0x00000002 }, |
| { 0x00061000, 0x00000002 }, |
| { 0x00000020, 0x0000001a }, |
| { 0x00004000, 0x0000001e }, |
| { 0x00061000, 0x00000002 }, |
| { 0x00000020, 0x0000001a }, |
| { 0x00004000, 0x0000001e }, |
| { 0x00061000, 0x00000002 }, |
| { 0x00000020, 0x0000001a }, |
| { 0x00004000, 0x0000001e }, |
| { 0x00000016, 0x00000004 }, |
| { 0x0003802a, 0x00000002 }, |
| { 0x040067e0, 0x00000002 }, |
| { 0x00000016, 0x00000004 }, |
| { 0x000077e0, 0x00000002 }, |
| { 0x00065000, 0x00000002 }, |
| { 0x000037e1, 0x00000002 }, |
| { 0x040067e1, 0x00000006 }, |
| { 0x000077e0, 0x00000002 }, |
| { 0x000077e1, 0x00000002 }, |
| { 0x000077e1, 0x00000006 }, |
| { 0xffffffff, 0000000000 }, |
| { 0x10000000, 0000000000 }, |
| { 0x07f007f0, 0000000000 }, |
| { 0x0003802a, 0x00000002 }, |
| { 0x040067e0, 0x00000006 }, |
| { 0x0003802c, 0x00000002 }, |
| { 0x04002741, 0x00000002 }, |
| { 0x04002741, 0x00000002 }, |
| { 0x04002743, 0x00000002 }, |
| { 0x00007675, 0x00000002 }, |
| { 0x00007676, 0x00000002 }, |
| { 0x00007677, 0x00000002 }, |
| { 0x00007678, 0x00000006 }, |
| { 0x0003802c, 0x00000002 }, |
| { 0x04002741, 0x00000002 }, |
| { 0x04002741, 0x00000002 }, |
| { 0x04002743, 0x00000002 }, |
| { 0x00007676, 0x00000002 }, |
| { 0x00007677, 0x00000002 }, |
| { 0x00007678, 0x00000006 }, |
| { 0x0003802b, 0x00000002 }, |
| { 0x04002676, 0x00000002 }, |
| { 0x00007677, 0x00000002 }, |
| { 0x0003802c, 0x00000002 }, |
| { 0x04002741, 0x00000002 }, |
| { 0x04002743, 0x00000002 }, |
| { 0x00007678, 0x00000006 }, |
| { 0x0003802c, 0x00000002 }, |
| { 0x04002741, 0x00000002 }, |
| { 0x04002741, 0x00000002 }, |
| { 0x04002743, 0x00000002 }, |
| { 0x00007678, 0x00000006 }, |
| { 0x0000002f, 0x00000018 }, |
| { 0x0000002f, 0x00000018 }, |
| { 0000000000, 0x00000006 }, |
| { 0x00000037, 0x00000018 }, |
| { 0x00000037, 0x00000018 }, |
| { 0000000000, 0x00000006 }, |
| { 0x01605000, 0x00000002 }, |
| { 0x00065000, 0x00000002 }, |
| { 0x00098000, 0x00000002 }, |
| { 0x00061000, 0x00000002 }, |
| { 0x64c06051, 0x00000004 }, |
| { 0x00080000, 0x00000016 }, |
| { 0000000000, 0000000000 }, |
| { 0x0400251d, 0x00000002 }, |
| { 0x00007580, 0x00000002 }, |
| { 0x00067581, 0x00000002 }, |
| { 0x04002580, 0x00000002 }, |
| { 0x00067581, 0x00000002 }, |
| { 0x0000005a, 0x00000004 }, |
| { 0x00005000, 0000000000 }, |
| { 0x00061000, 0x00000002 }, |
| { 0x0000750e, 0x00000002 }, |
| { 0x00019000, 0x00000002 }, |
| { 0x00011064, 0x00000014 }, |
| { 0x00000064, 0x00000012 }, |
| { 0x0400250f, 0x00000002 }, |
| { 0x0000505e, 0x00000004 }, |
| { 0x00007565, 0x00000002 }, |
| { 0x00007566, 0x00000002 }, |
| { 0x00000065, 0x00000004 }, |
| { 0x01e655b4, 0x00000002 }, |
| { 0x4401b0f0, 0x00000002 }, |
| { 0x01c110f0, 0x00000002 }, |
| { 0x26667071, 0x00000018 }, |
| { 0x040c2565, 0x00000002 }, |
| { 0x00000071, 0x00000018 }, |
| { 0x04002564, 0x00000002 }, |
| { 0x00007566, 0x00000002 }, |
| { 0x00000068, 0x00000004 }, |
| { 0x00401074, 0x00000008 }, |
| { 0x00101000, 0x00000002 }, |
| { 0x000d80ff, 0x00000002 }, |
| { 0x00800077, 0x00000008 }, |
| { 0x000f9000, 0x00000002 }, |
| { 0x000e00ff, 0x00000002 }, |
| { 0000000000, 0x00000006 }, |
| { 0x00000094, 0x00000018 }, |
| { 0x00000068, 0x00000004 }, |
| { 0x00007576, 0x00000002 }, |
| { 0x00065000, 0x00000002 }, |
| { 0x00009000, 0x00000002 }, |
| { 0x00041000, 0x00000002 }, |
| { 0x0c00350e, 0x00000002 }, |
| { 0x00049000, 0x00000002 }, |
| { 0x00051000, 0x00000002 }, |
| { 0x01e785f8, 0x00000002 }, |
| { 0x00200000, 0x00000002 }, |
| { 0x00600087, 0x0000000c }, |
| { 0x00007563, 0x00000002 }, |
| { 0x006075f0, 0x00000021 }, |
| { 0x2000707c, 0x00000004 }, |
| { 0x0000507c, 0x00000004 }, |
| { 0x00007576, 0x00000002 }, |
| { 0x00007577, 0x00000002 }, |
| { 0x0000750e, 0x00000002 }, |
| { 0x0000750f, 0x00000002 }, |
| { 0x00a05000, 0x00000002 }, |
| { 0x0060008a, 0x0000000c }, |
| { 0x006075f0, 0x00000021 }, |
| { 0x000075f8, 0x00000002 }, |
| { 0x0000008a, 0x00000004 }, |
| { 0x000a750e, 0x00000002 }, |
| { 0x0020750f, 0x00000002 }, |
| { 0x0060008d, 0x00000004 }, |
| { 0x00007570, 0x00000002 }, |
| { 0x00007571, 0x00000002 }, |
| { 0x00007572, 0x00000006 }, |
| { 0x00005000, 0x00000002 }, |
| { 0x00a05000, 0x00000002 }, |
| { 0x00007568, 0x00000002 }, |
| { 0x00061000, 0x00000002 }, |
| { 0x00000098, 0x0000000c }, |
| { 0x00058000, 0x00000002 }, |
| { 0x0c607562, 0x00000002 }, |
| { 0x0000009a, 0x00000004 }, |
| { 0x00600099, 0x00000004 }, |
| { 0x400070f1, 0000000000 }, |
| { 0x000380f1, 0x00000002 }, |
| { 0x000000a7, 0x0000001c }, |
| { 0x000650a9, 0x00000018 }, |
| { 0x040025bb, 0x00000002 }, |
| { 0x000610aa, 0x00000018 }, |
| { 0x040075bc, 0000000000 }, |
| { 0x000075bb, 0x00000002 }, |
| { 0x000075bc, 0000000000 }, |
| { 0x00090000, 0x00000006 }, |
| { 0x00090000, 0x00000002 }, |
| { 0x000d8002, 0x00000006 }, |
| { 0x00005000, 0x00000002 }, |
| { 0x00007821, 0x00000002 }, |
| { 0x00007800, 0000000000 }, |
| { 0x00007821, 0x00000002 }, |
| { 0x00007800, 0000000000 }, |
| { 0x01665000, 0x00000002 }, |
| { 0x000a0000, 0x00000002 }, |
| { 0x000671cc, 0x00000002 }, |
| { 0x0286f1cd, 0x00000002 }, |
| { 0x000000b7, 0x00000010 }, |
| { 0x21007000, 0000000000 }, |
| { 0x000000be, 0x0000001c }, |
| { 0x00065000, 0x00000002 }, |
| { 0x000a0000, 0x00000002 }, |
| { 0x00061000, 0x00000002 }, |
| { 0x000b0000, 0x00000002 }, |
| { 0x38067000, 0x00000002 }, |
| { 0x000a00ba, 0x00000004 }, |
| { 0x20007000, 0000000000 }, |
| { 0x01200000, 0x00000002 }, |
| { 0x20077000, 0x00000002 }, |
| { 0x01200000, 0x00000002 }, |
| { 0x20007000, 0000000000 }, |
| { 0x00061000, 0x00000002 }, |
| { 0x0120751b, 0x00000002 }, |
| { 0x8040750a, 0x00000002 }, |
| { 0x8040750b, 0x00000002 }, |
| { 0x00110000, 0x00000002 }, |
| { 0x000380f1, 0x00000002 }, |
| { 0x000000d1, 0x0000001c }, |
| { 0x000610aa, 0x00000018 }, |
| { 0x844075bd, 0x00000002 }, |
| { 0x000610a9, 0x00000018 }, |
| { 0x840075bb, 0x00000002 }, |
| { 0x000610aa, 0x00000018 }, |
| { 0x844075bc, 0x00000002 }, |
| { 0x000000d4, 0x00000004 }, |
| { 0x804075bd, 0x00000002 }, |
| { 0x800075bb, 0x00000002 }, |
| { 0x804075bc, 0x00000002 }, |
| { 0x00108000, 0x00000002 }, |
| { 0x01400000, 0x00000002 }, |
| { 0x006000d8, 0x0000000c }, |
| { 0x20c07000, 0x00000020 }, |
| { 0x000000da, 0x00000012 }, |
| { 0x00800000, 0x00000006 }, |
| { 0x0080751d, 0x00000006 }, |
| { 0x000025bb, 0x00000002 }, |
| { 0x000040d4, 0x00000004 }, |
| { 0x0000775c, 0x00000002 }, |
| { 0x00a05000, 0x00000002 }, |
| { 0x00661000, 0x00000002 }, |
| { 0x0460275d, 0x00000020 }, |
| { 0x00004000, 0000000000 }, |
| { 0x00007999, 0x00000002 }, |
| { 0x00a05000, 0x00000002 }, |
| { 0x00661000, 0x00000002 }, |
| { 0x0460299b, 0x00000020 }, |
| { 0x00004000, 0000000000 }, |
| { 0x01e00830, 0x00000002 }, |
| { 0x21007000, 0000000000 }, |
| { 0x00005000, 0x00000002 }, |
| { 0x00038056, 0x00000002 }, |
| { 0x040025e0, 0x00000002 }, |
| { 0x000075e1, 0000000000 }, |
| { 0x00000001, 0000000000 }, |
| { 0x000380ed, 0x00000002 }, |
| { 0x04007394, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0x000078c4, 0x00000002 }, |
| { 0x000078c5, 0x00000002 }, |
| { 0x000078c6, 0x00000002 }, |
| { 0x00007924, 0x00000002 }, |
| { 0x00007925, 0x00000002 }, |
| { 0x00007926, 0x00000002 }, |
| { 0x000000f2, 0x00000004 }, |
| { 0x00007924, 0x00000002 }, |
| { 0x00007925, 0x00000002 }, |
| { 0x00007926, 0x00000002 }, |
| { 0x000000f9, 0x00000004 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| }; |
| static const u32 R300_cp_microcode[][2] = { |
| { 0x4200e000, 0000000000 }, |
| { 0x4000e000, 0000000000 }, |
| { 0x000000ae, 0x00000008 }, |
| { 0x000000b2, 0x00000008 }, |
| { 0x67554b4a, 0000000000 }, |
| { 0x4a4a4475, 0000000000 }, |
| { 0x55527d83, 0000000000 }, |
| { 0x4a8c8b65, 0000000000 }, |
| { 0x4aef4af6, 0000000000 }, |
| { 0x4ae14a4a, 0000000000 }, |
| { 0xe4979797, 0000000000 }, |
| { 0xdb4aebdd, 0000000000 }, |
| { 0x9ccc4a4a, 0000000000 }, |
| { 0xd1989898, 0000000000 }, |
| { 0x4a0f9ad6, 0000000000 }, |
| { 0x000ca000, 0x00000004 }, |
| { 0x000d0012, 0x00000038 }, |
| { 0x0000e8b4, 0x00000004 }, |
| { 0x000d0014, 0x00000038 }, |
| { 0x0000e8b6, 0x00000004 }, |
| { 0x000d0016, 0x00000038 }, |
| { 0x0000e854, 0x00000004 }, |
| { 0x000d0018, 0x00000038 }, |
| { 0x0000e855, 0x00000004 }, |
| { 0x000d001a, 0x00000038 }, |
| { 0x0000e856, 0x00000004 }, |
| { 0x000d001c, 0x00000038 }, |
| { 0x0000e857, 0x00000004 }, |
| { 0x000d001e, 0x00000038 }, |
| { 0x0000e824, 0x00000004 }, |
| { 0x000d0020, 0x00000038 }, |
| { 0x0000e825, 0x00000004 }, |
| { 0x000d0022, 0x00000038 }, |
| { 0x0000e830, 0x00000004 }, |
| { 0x000d0024, 0x00000038 }, |
| { 0x0000f0c0, 0x00000004 }, |
| { 0x000d0026, 0x00000038 }, |
| { 0x0000f0c1, 0x00000004 }, |
| { 0x000d0028, 0x00000038 }, |
| { 0x0000f041, 0x00000004 }, |
| { 0x000d002a, 0x00000038 }, |
| { 0x0000f184, 0x00000004 }, |
| { 0x000d002c, 0x00000038 }, |
| { 0x0000f185, 0x00000004 }, |
| { 0x000d002e, 0x00000038 }, |
| { 0x0000f186, 0x00000004 }, |
| { 0x000d0030, 0x00000038 }, |
| { 0x0000f187, 0x00000004 }, |
| { 0x000d0032, 0x00000038 }, |
| { 0x0000f180, 0x00000004 }, |
| { 0x000d0034, 0x00000038 }, |
| { 0x0000f393, 0x00000004 }, |
| { 0x000d0036, 0x00000038 }, |
| { 0x0000f38a, 0x00000004 }, |
| { 0x000d0038, 0x00000038 }, |
| { 0x0000f38e, 0x00000004 }, |
| { 0x0000e821, 0x00000004 }, |
| { 0x0140a000, 0x00000004 }, |
| { 0x00000043, 0x00000018 }, |
| { 0x00cce800, 0x00000004 }, |
| { 0x001b0001, 0x00000004 }, |
| { 0x08004800, 0x00000004 }, |
| { 0x001b0001, 0x00000004 }, |
| { 0x08004800, 0x00000004 }, |
| { 0x001b0001, 0x00000004 }, |
| { 0x08004800, 0x00000004 }, |
| { 0x0000003a, 0x00000008 }, |
| { 0x0000a000, 0000000000 }, |
| { 0x2000451d, 0x00000004 }, |
| { 0x0000e580, 0x00000004 }, |
| { 0x000ce581, 0x00000004 }, |
| { 0x08004580, 0x00000004 }, |
| { 0x000ce581, 0x00000004 }, |
| { 0x00000047, 0x00000008 }, |
| { 0x0000a000, 0000000000 }, |
| { 0x000c2000, 0x00000004 }, |
| { 0x0000e50e, 0x00000004 }, |
| { 0x00032000, 0x00000004 }, |
| { 0x00022051, 0x00000028 }, |
| { 0x00000051, 0x00000024 }, |
| { 0x0800450f, 0x00000004 }, |
| { 0x0000a04b, 0x00000008 }, |
| { 0x0000e565, 0x00000004 }, |
| { 0x0000e566, 0x00000004 }, |
| { 0x00000052, 0x00000008 }, |
| { 0x03cca5b4, 0x00000004 }, |
| { 0x05432000, 0x00000004 }, |
| { 0x00022000, 0x00000004 }, |
| { 0x4ccce05e, 0x00000030 }, |
| { 0x08274565, 0x00000004 }, |
| { 0x0000005e, 0x00000030 }, |
| { 0x08004564, 0x00000004 }, |
| { 0x0000e566, 0x00000004 }, |
| { 0x00000055, 0x00000008 }, |
| { 0x00802061, 0x00000010 }, |
| { 0x00202000, 0x00000004 }, |
| { 0x001b00ff, 0x00000004 }, |
| { 0x01000064, 0x00000010 }, |
| { 0x001f2000, 0x00000004 }, |
| { 0x001c00ff, 0x00000004 }, |
| { 0000000000, 0x0000000c }, |
| { 0x00000080, 0x00000030 }, |
| { 0x00000055, 0x00000008 }, |
| { 0x0000e576, 0x00000004 }, |
| { 0x000ca000, 0x00000004 }, |
| { 0x00012000, 0x00000004 }, |
| { 0x00082000, 0x00000004 }, |
| { 0x1800650e, 0x00000004 }, |
| { 0x00092000, 0x00000004 }, |
| { 0x000a2000, 0x00000004 }, |
| { 0x000f0000, 0x00000004 }, |
| { 0x00400000, 0x00000004 }, |
| { 0x00000074, 0x00000018 }, |
| { 0x0000e563, 0x00000004 }, |
| { 0x00c0e5f9, 0x000000c2 }, |
| { 0x00000069, 0x00000008 }, |
| { 0x0000a069, 0x00000008 }, |
| { 0x0000e576, 0x00000004 }, |
| { 0x0000e577, 0x00000004 }, |
| { 0x0000e50e, 0x00000004 }, |
| { 0x0000e50f, 0x00000004 }, |
| { 0x0140a000, 0x00000004 }, |
| { 0x00000077, 0x00000018 }, |
| { 0x00c0e5f9, 0x000000c2 }, |
| { 0x00000077, 0x00000008 }, |
| { 0x0014e50e, 0x00000004 }, |
| { 0x0040e50f, 0x00000004 }, |
| { 0x00c0007a, 0x00000008 }, |
| { 0x0000e570, 0x00000004 }, |
| { 0x0000e571, 0x00000004 }, |
| { 0x0000e572, 0x0000000c }, |
| { 0x0000a000, 0x00000004 }, |
| { 0x0140a000, 0x00000004 }, |
| { 0x0000e568, 0x00000004 }, |
| { 0x000c2000, 0x00000004 }, |
| { 0x00000084, 0x00000018 }, |
| { 0x000b0000, 0x00000004 }, |
| { 0x18c0e562, 0x00000004 }, |
| { 0x00000086, 0x00000008 }, |
| { 0x00c00085, 0x00000008 }, |
| { 0x000700e3, 0x00000004 }, |
| { 0x00000092, 0x00000038 }, |
| { 0x000ca094, 0x00000030 }, |
| { 0x080045bb, 0x00000004 }, |
| { 0x000c2095, 0x00000030 }, |
| { 0x0800e5bc, 0000000000 }, |
| { 0x0000e5bb, 0x00000004 }, |
| { 0x0000e5bc, 0000000000 }, |
| { 0x00120000, 0x0000000c }, |
| { 0x00120000, 0x00000004 }, |
| { 0x001b0002, 0x0000000c }, |
| { 0x0000a000, 0x00000004 }, |
| { 0x0000e821, 0x00000004 }, |
| { 0x0000e800, 0000000000 }, |
| { 0x0000e821, 0x00000004 }, |
| { 0x0000e82e, 0000000000 }, |
| { 0x02cca000, 0x00000004 }, |
| { 0x00140000, 0x00000004 }, |
| { 0x000ce1cc, 0x00000004 }, |
| { 0x050de1cd, 0x00000004 }, |
| { 0x00400000, 0x00000004 }, |
| { 0x000000a4, 0x00000018 }, |
| { 0x00c0a000, 0x00000004 }, |
| { 0x000000a1, 0x00000008 }, |
| { 0x000000a6, 0x00000020 }, |
| { 0x4200e000, 0000000000 }, |
| { 0x000000ad, 0x00000038 }, |
| { 0x000ca000, 0x00000004 }, |
| { 0x00140000, 0x00000004 }, |
| { 0x000c2000, 0x00000004 }, |
| { 0x00160000, 0x00000004 }, |
| { 0x700ce000, 0x00000004 }, |
| { 0x001400a9, 0x00000008 }, |
| { 0x4000e000, 0000000000 }, |
| { 0x02400000, 0x00000004 }, |
| { 0x400ee000, 0x00000004 }, |
| { 0x02400000, 0x00000004 }, |
| { 0x4000e000, 0000000000 }, |
| { 0x000c2000, 0x00000004 }, |
| { 0x0240e51b, 0x00000004 }, |
| { 0x0080e50a, 0x00000005 }, |
| { 0x0080e50b, 0x00000005 }, |
| { 0x00220000, 0x00000004 }, |
| { 0x000700e3, 0x00000004 }, |
| { 0x000000c0, 0x00000038 }, |
| { 0x000c2095, 0x00000030 }, |
| { 0x0880e5bd, 0x00000005 }, |
| { 0x000c2094, 0x00000030 }, |
| { 0x0800e5bb, 0x00000005 }, |
| { 0x000c2095, 0x00000030 }, |
| { 0x0880e5bc, 0x00000005 }, |
| { 0x000000c3, 0x00000008 }, |
| { 0x0080e5bd, 0x00000005 }, |
| { 0x0000e5bb, 0x00000005 }, |
| { 0x0080e5bc, 0x00000005 }, |
| { 0x00210000, 0x00000004 }, |
| { 0x02800000, 0x00000004 }, |
| { 0x00c000c7, 0x00000018 }, |
| { 0x4180e000, 0x00000040 }, |
| { 0x000000c9, 0x00000024 }, |
| { 0x01000000, 0x0000000c }, |
| { 0x0100e51d, 0x0000000c }, |
| { 0x000045bb, 0x00000004 }, |
| { 0x000080c3, 0x00000008 }, |
| { 0x0000f3ce, 0x00000004 }, |
| { 0x0140a000, 0x00000004 }, |
| { 0x00cc2000, 0x00000004 }, |
| { 0x08c053cf, 0x00000040 }, |
| { 0x00008000, 0000000000 }, |
| { 0x0000f3d2, 0x00000004 }, |
| { 0x0140a000, 0x00000004 }, |
| { 0x00cc2000, 0x00000004 }, |
| { 0x08c053d3, 0x00000040 }, |
| { 0x00008000, 0000000000 }, |
| { 0x0000f39d, 0x00000004 }, |
| { 0x0140a000, 0x00000004 }, |
| { 0x00cc2000, 0x00000004 }, |
| { 0x08c0539e, 0x00000040 }, |
| { 0x00008000, 0000000000 }, |
| { 0x03c00830, 0x00000004 }, |
| { 0x4200e000, 0000000000 }, |
| { 0x0000a000, 0x00000004 }, |
| { 0x200045e0, 0x00000004 }, |
| { 0x0000e5e1, 0000000000 }, |
| { 0x00000001, 0000000000 }, |
| { 0x000700e0, 0x00000004 }, |
| { 0x0800e394, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0x0000e8c4, 0x00000004 }, |
| { 0x0000e8c5, 0x00000004 }, |
| { 0x0000e8c6, 0x00000004 }, |
| { 0x0000e928, 0x00000004 }, |
| { 0x0000e929, 0x00000004 }, |
| { 0x0000e92a, 0x00000004 }, |
| { 0x000000e4, 0x00000008 }, |
| { 0x0000e928, 0x00000004 }, |
| { 0x0000e929, 0x00000004 }, |
| { 0x0000e92a, 0x00000004 }, |
| { 0x000000eb, 0x00000008 }, |
| { 0x02c02000, 0x00000004 }, |
| { 0x00060000, 0x00000004 }, |
| { 0x000000f3, 0x00000034 }, |
| { 0x000000f0, 0x00000008 }, |
| { 0x00008000, 0x00000004 }, |
| { 0xc000e000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0x000c2000, 0x00000004 }, |
| { 0x001d0018, 0x00000004 }, |
| { 0x001a0001, 0x00000004 }, |
| { 0x000000fb, 0x00000034 }, |
| { 0x0000004a, 0x00000008 }, |
| { 0x0500a04a, 0x00000008 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| }; |
| static const u32 R420_cp_microcode[][2] = { |
| { 0x4200e000, 0000000000 }, |
| { 0x4000e000, 0000000000 }, |
| { 0x00000099, 0x00000008 }, |
| { 0x0000009d, 0x00000008 }, |
| { 0x4a554b4a, 0000000000 }, |
| { 0x4a4a4467, 0000000000 }, |
| { 0x55526f75, 0000000000 }, |
| { 0x4a7e7d65, 0000000000 }, |
| { 0xd9d3dff6, 0000000000 }, |
| { 0x4ac54a4a, 0000000000 }, |
| { 0xc8828282, 0000000000 }, |
| { 0xbf4acfc1, 0000000000 }, |
| { 0x87b04a4a, 0000000000 }, |
| { 0xb5838383, 0000000000 }, |
| { 0x4a0f85ba, 0000000000 }, |
| { 0x000ca000, 0x00000004 }, |
| { 0x000d0012, 0x00000038 }, |
| { 0x0000e8b4, 0x00000004 }, |
| { 0x000d0014, 0x00000038 }, |
| { 0x0000e8b6, 0x00000004 }, |
| { 0x000d0016, 0x00000038 }, |
| { 0x0000e854, 0x00000004 }, |
| { 0x000d0018, 0x00000038 }, |
| { 0x0000e855, 0x00000004 }, |
| { 0x000d001a, 0x00000038 }, |
| { 0x0000e856, 0x00000004 }, |
| { 0x000d001c, 0x00000038 }, |
| { 0x0000e857, 0x00000004 }, |
| { 0x000d001e, 0x00000038 }, |
| { 0x0000e824, 0x00000004 }, |
| { 0x000d0020, 0x00000038 }, |
| { 0x0000e825, 0x00000004 }, |
| { 0x000d0022, 0x00000038 }, |
| { 0x0000e830, 0x00000004 }, |
| { 0x000d0024, 0x00000038 }, |
| { 0x0000f0c0, 0x00000004 }, |
| { 0x000d0026, 0x00000038 }, |
| { 0x0000f0c1, 0x00000004 }, |
| { 0x000d0028, 0x00000038 }, |
| { 0x0000f041, 0x00000004 }, |
| { 0x000d002a, 0x00000038 }, |
| { 0x0000f184, 0x00000004 }, |
| { 0x000d002c, 0x00000038 }, |
| { 0x0000f185, 0x00000004 }, |
| { 0x000d002e, 0x00000038 }, |
| { 0x0000f186, 0x00000004 }, |
| { 0x000d0030, 0x00000038 }, |
| { 0x0000f187, 0x00000004 }, |
| { 0x000d0032, 0x00000038 }, |
| { 0x0000f180, 0x00000004 }, |
| { 0x000d0034, 0x00000038 }, |
| { 0x0000f393, 0x00000004 }, |
| { 0x000d0036, 0x00000038 }, |
| { 0x0000f38a, 0x00000004 }, |
| { 0x000d0038, 0x00000038 }, |
| { 0x0000f38e, 0x00000004 }, |
| { 0x0000e821, 0x00000004 }, |
| { 0x0140a000, 0x00000004 }, |
| { 0x00000043, 0x00000018 }, |
| { 0x00cce800, 0x00000004 }, |
| { 0x001b0001, 0x00000004 }, |
| { 0x08004800, 0x00000004 }, |
| { 0x001b0001, 0x00000004 }, |
| { 0x08004800, 0x00000004 }, |
| { 0x001b0001, 0x00000004 }, |
| { 0x08004800, 0x00000004 }, |
| { 0x0000003a, 0x00000008 }, |
| { 0x0000a000, 0000000000 }, |
| { 0x2000451d, 0x00000004 }, |
| { 0x0000e580, 0x00000004 }, |
| { 0x000ce581, 0x00000004 }, |
| { 0x08004580, 0x00000004 }, |
| { 0x000ce581, 0x00000004 }, |
| { 0x00000047, 0x00000008 }, |
| { 0x0000a000, 0000000000 }, |
| { 0x000c2000, 0x00000004 }, |
| { 0x0000e50e, 0x00000004 }, |
| { 0x00032000, 0x00000004 }, |
| { 0x00022051, 0x00000028 }, |
| { 0x00000051, 0x00000024 }, |
| { 0x0800450f, 0x00000004 }, |
| { 0x0000a04b, 0x00000008 }, |
| { 0x0000e565, 0x00000004 }, |
| { 0x0000e566, 0x00000004 }, |
| { 0x00000052, 0x00000008 }, |
| { 0x03cca5b4, 0x00000004 }, |
| { 0x05432000, 0x00000004 }, |
| { 0x00022000, 0x00000004 }, |
| { 0x4ccce05e, 0x00000030 }, |
| { 0x08274565, 0x00000004 }, |
| { 0x0000005e, 0x00000030 }, |
| { 0x08004564, 0x00000004 }, |
| { 0x0000e566, 0x00000004 }, |
| { 0x00000055, 0x00000008 }, |
| { 0x00802061, 0x00000010 }, |
| { 0x00202000, 0x00000004 }, |
| { 0x001b00ff, 0x00000004 }, |
| { 0x01000064, 0x00000010 }, |
| { 0x001f2000, 0x00000004 }, |
| { 0x001c00ff, 0x00000004 }, |
| { 0000000000, 0x0000000c }, |
| { 0x00000072, 0x00000030 }, |
| { 0x00000055, 0x00000008 }, |
| { 0x0000e576, 0x00000004 }, |
| { 0x0000e577, 0x00000004 }, |
| { 0x0000e50e, 0x00000004 }, |
| { 0x0000e50f, 0x00000004 }, |
| { 0x0140a000, 0x00000004 }, |
| { 0x00000069, 0x00000018 }, |
| { 0x00c0e5f9, 0x000000c2 }, |
| { 0x00000069, 0x00000008 }, |
| { 0x0014e50e, 0x00000004 }, |
| { 0x0040e50f, 0x00000004 }, |
| { 0x00c0006c, 0x00000008 }, |
| { 0x0000e570, 0x00000004 }, |
| { 0x0000e571, 0x00000004 }, |
| { 0x0000e572, 0x0000000c }, |
| { 0x0000a000, 0x00000004 }, |
| { 0x0140a000, 0x00000004 }, |
| { 0x0000e568, 0x00000004 }, |
| { 0x000c2000, 0x00000004 }, |
| { 0x00000076, 0x00000018 }, |
| { 0x000b0000, 0x00000004 }, |
| { 0x18c0e562, 0x00000004 }, |
| { 0x00000078, 0x00000008 }, |
| { 0x00c00077, 0x00000008 }, |
| { 0x000700c7, 0x00000004 }, |
| { 0x00000080, 0x00000038 }, |
| { 0x0000e5bb, 0x00000004 }, |
| { 0x0000e5bc, 0000000000 }, |
| { 0x0000a000, 0x00000004 }, |
| { 0x0000e821, 0x00000004 }, |
| { 0x0000e800, 0000000000 }, |
| { 0x0000e821, 0x00000004 }, |
| { 0x0000e82e, 0000000000 }, |
| { 0x02cca000, 0x00000004 }, |
| { 0x00140000, 0x00000004 }, |
| { 0x000ce1cc, 0x00000004 }, |
| { 0x050de1cd, 0x00000004 }, |
| { 0x00400000, 0x00000004 }, |
| { 0x0000008f, 0x00000018 }, |
| { 0x00c0a000, 0x00000004 }, |
| { 0x0000008c, 0x00000008 }, |
| { 0x00000091, 0x00000020 }, |
| { 0x4200e000, 0000000000 }, |
| { 0x00000098, 0x00000038 }, |
| { 0x000ca000, 0x00000004 }, |
| { 0x00140000, 0x00000004 }, |
| { 0x000c2000, 0x00000004 }, |
| { 0x00160000, 0x00000004 }, |
| { 0x700ce000, 0x00000004 }, |
| { 0x00140094, 0x00000008 }, |
| { 0x4000e000, 0000000000 }, |
| { 0x02400000, 0x00000004 }, |
| { 0x400ee000, 0x00000004 }, |
| { 0x02400000, 0x00000004 }, |
| { 0x4000e000, 0000000000 }, |
| { 0x000c2000, 0x00000004 }, |
| { 0x0240e51b, 0x00000004 }, |
| { 0x0080e50a, 0x00000005 }, |
| { 0x0080e50b, 0x00000005 }, |
| { 0x00220000, 0x00000004 }, |
| { 0x000700c7, 0x00000004 }, |
| { 0x000000a4, 0x00000038 }, |
| { 0x0080e5bd, 0x00000005 }, |
| { 0x0000e5bb, 0x00000005 }, |
| { 0x0080e5bc, 0x00000005 }, |
| { 0x00210000, 0x00000004 }, |
| { 0x02800000, 0x00000004 }, |
| { 0x00c000ab, 0x00000018 }, |
| { 0x4180e000, 0x00000040 }, |
| { 0x000000ad, 0x00000024 }, |
| { 0x01000000, 0x0000000c }, |
| { 0x0100e51d, 0x0000000c }, |
| { 0x000045bb, 0x00000004 }, |
| { 0x000080a7, 0x00000008 }, |
| { 0x0000f3ce, 0x00000004 }, |
| { 0x0140a000, 0x00000004 }, |
| { 0x00cc2000, 0x00000004 }, |
| { 0x08c053cf, 0x00000040 }, |
| { 0x00008000, 0000000000 }, |
| { 0x0000f3d2, 0x00000004 }, |
| { 0x0140a000, 0x00000004 }, |
| { 0x00cc2000, 0x00000004 }, |
| { 0x08c053d3, 0x00000040 }, |
| { 0x00008000, 0000000000 }, |
| { 0x0000f39d, 0x00000004 }, |
| { 0x0140a000, 0x00000004 }, |
| { 0x00cc2000, 0x00000004 }, |
| { 0x08c0539e, 0x00000040 }, |
| { 0x00008000, 0000000000 }, |
| { 0x03c00830, 0x00000004 }, |
| { 0x4200e000, 0000000000 }, |
| { 0x0000a000, 0x00000004 }, |
| { 0x200045e0, 0x00000004 }, |
| { 0x0000e5e1, 0000000000 }, |
| { 0x00000001, 0000000000 }, |
| { 0x000700c4, 0x00000004 }, |
| { 0x0800e394, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0x0000e8c4, 0x00000004 }, |
| { 0x0000e8c5, 0x00000004 }, |
| { 0x0000e8c6, 0x00000004 }, |
| { 0x0000e928, 0x00000004 }, |
| { 0x0000e929, 0x00000004 }, |
| { 0x0000e92a, 0x00000004 }, |
| { 0x000000c8, 0x00000008 }, |
| { 0x0000e928, 0x00000004 }, |
| { 0x0000e929, 0x00000004 }, |
| { 0x0000e92a, 0x00000004 }, |
| { 0x000000cf, 0x00000008 }, |
| { 0x02c02000, 0x00000004 }, |
| { 0x00060000, 0x00000004 }, |
| { 0x000000d7, 0x00000034 }, |
| { 0x000000d4, 0x00000008 }, |
| { 0x00008000, 0x00000004 }, |
| { 0xc000e000, 0000000000 }, |
| { 0x0000e1cc, 0x00000004 }, |
| { 0x0500e1cd, 0x00000004 }, |
| { 0x000ca000, 0x00000004 }, |
| { 0x000000de, 0x00000034 }, |
| { 0x000000da, 0x00000008 }, |
| { 0x0000a000, 0000000000 }, |
| { 0x0019e1cc, 0x00000004 }, |
| { 0x001b0001, 0x00000004 }, |
| { 0x0500a000, 0x00000004 }, |
| { 0x080041cd, 0x00000004 }, |
| { 0x000ca000, 0x00000004 }, |
| { 0x000000fb, 0x00000034 }, |
| { 0x0000004a, 0x00000008 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0x000c2000, 0x00000004 }, |
| { 0x001d0018, 0x00000004 }, |
| { 0x001a0001, 0x00000004 }, |
| { 0x000000fb, 0x00000034 }, |
| { 0x0000004a, 0x00000008 }, |
| { 0x0500a04a, 0x00000008 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| }; |
| static const u32 RS600_cp_microcode[][2] = { |
| { 0x4200e000, 0000000000 }, |
| { 0x4000e000, 0000000000 }, |
| { 0x000000a0, 0x00000008 }, |
| { 0x000000a4, 0x00000008 }, |
| { 0x4a554b4a, 0000000000 }, |
| { 0x4a4a4467, 0000000000 }, |
| { 0x55526f75, 0000000000 }, |
| { 0x4a7e7d65, 0000000000 }, |
| { 0x4ae74af6, 0000000000 }, |
| { 0x4ad34a4a, 0000000000 }, |
| { 0xd6898989, 0000000000 }, |
| { 0xcd4addcf, 0000000000 }, |
| { 0x8ebe4ae2, 0000000000 }, |
| { 0xc38a8a8a, 0000000000 }, |
| { 0x4a0f8cc8, 0000000000 }, |
| { 0x000ca000, 0x00000004 }, |
| { 0x000d0012, 0x00000038 }, |
| { 0x0000e8b4, 0x00000004 }, |
| { 0x000d0014, 0x00000038 }, |
| { 0x0000e8b6, 0x00000004 }, |
| { 0x000d0016, 0x00000038 }, |
| { 0x0000e854, 0x00000004 }, |
| { 0x000d0018, 0x00000038 }, |
| { 0x0000e855, 0x00000004 }, |
| { 0x000d001a, 0x00000038 }, |
| { 0x0000e856, 0x00000004 }, |
| { 0x000d001c, 0x00000038 }, |
| { 0x0000e857, 0x00000004 }, |
| { 0x000d001e, 0x00000038 }, |
| { 0x0000e824, 0x00000004 }, |
| { 0x000d0020, 0x00000038 }, |
| { 0x0000e825, 0x00000004 }, |
| { 0x000d0022, 0x00000038 }, |
| { 0x0000e830, 0x00000004 }, |
| { 0x000d0024, 0x00000038 }, |
| { 0x0000f0c0, 0x00000004 }, |
| { 0x000d0026, 0x00000038 }, |
| { 0x0000f0c1, 0x00000004 }, |
| { 0x000d0028, 0x00000038 }, |
| { 0x0000f041, 0x00000004 }, |
| { 0x000d002a, 0x00000038 }, |
| { 0x0000f184, 0x00000004 }, |
| { 0x000d002c, 0x00000038 }, |
| { 0x0000f185, 0x00000004 }, |
| { 0x000d002e, 0x00000038 }, |
| { 0x0000f186, 0x00000004 }, |
| { 0x000d0030, 0x00000038 }, |
| { 0x0000f187, 0x00000004 }, |
| { 0x000d0032, 0x00000038 }, |
| { 0x0000f180, 0x00000004 }, |
| { 0x000d0034, 0x00000038 }, |
| { 0x0000f393, 0x00000004 }, |
| { 0x000d0036, 0x00000038 }, |
| { 0x0000f38a, 0x00000004 }, |
| { 0x000d0038, 0x00000038 }, |
| { 0x0000f38e, 0x00000004 }, |
| { 0x0000e821, 0x00000004 }, |
| { 0x0140a000, 0x00000004 }, |
| { 0x00000043, 0x00000018 }, |
| { 0x00cce800, 0x00000004 }, |
| { 0x001b0001, 0x00000004 }, |
| { 0x08004800, 0x00000004 }, |
| { 0x001b0001, 0x00000004 }, |
| { 0x08004800, 0x00000004 }, |
| { 0x001b0001, 0x00000004 }, |
| { 0x08004800, 0x00000004 }, |
| { 0x0000003a, 0x00000008 }, |
| { 0x0000a000, 0000000000 }, |
| { 0x2000451d, 0x00000004 }, |
| { 0x0000e580, 0x00000004 }, |
| { 0x000ce581, 0x00000004 }, |
| { 0x08004580, 0x00000004 }, |
| { 0x000ce581, 0x00000004 }, |
| { 0x00000047, 0x00000008 }, |
| { 0x0000a000, 0000000000 }, |
| { 0x000c2000, 0x00000004 }, |
| { 0x0000e50e, 0x00000004 }, |
| { 0x00032000, 0x00000004 }, |
| { 0x00022051, 0x00000028 }, |
| { 0x00000051, 0x00000024 }, |
| { 0x0800450f, 0x00000004 }, |
| { 0x0000a04b, 0x00000008 }, |
| { 0x0000e565, 0x00000004 }, |
| { 0x0000e566, 0x00000004 }, |
| { 0x00000052, 0x00000008 }, |
| { 0x03cca5b4, 0x00000004 }, |
| { 0x05432000, 0x00000004 }, |
| { 0x00022000, 0x00000004 }, |
| { 0x4ccce05e, 0x00000030 }, |
| { 0x08274565, 0x00000004 }, |
| { 0x0000005e, 0x00000030 }, |
| { 0x08004564, 0x00000004 }, |
| { 0x0000e566, 0x00000004 }, |
| { 0x00000055, 0x00000008 }, |
| { 0x00802061, 0x00000010 }, |
| { 0x00202000, 0x00000004 }, |
| { 0x001b00ff, 0x00000004 }, |
| { 0x01000064, 0x00000010 }, |
| { 0x001f2000, 0x00000004 }, |
| { 0x001c00ff, 0x00000004 }, |
| { 0000000000, 0x0000000c }, |
| { 0x00000072, 0x00000030 }, |
| { 0x00000055, 0x00000008 }, |
| { 0x0000e576, 0x00000004 }, |
| { 0x0000e577, 0x00000004 }, |
| { 0x0000e50e, 0x00000004 }, |
| { 0x0000e50f, 0x00000004 }, |
| { 0x0140a000, 0x00000004 }, |
| { 0x00000069, 0x00000018 }, |
| { 0x00c0e5f9, 0x000000c2 }, |
| { 0x00000069, 0x00000008 }, |
| { 0x0014e50e, 0x00000004 }, |
| { 0x0040e50f, 0x00000004 }, |
| { 0x00c0006c, 0x00000008 }, |
| { 0x0000e570, 0x00000004 }, |
| { 0x0000e571, 0x00000004 }, |
| { 0x0000e572, 0x0000000c }, |
| { 0x0000a000, 0x00000004 }, |
| { 0x0140a000, 0x00000004 }, |
| { 0x0000e568, 0x00000004 }, |
| { 0x000c2000, 0x00000004 }, |
| { 0x00000076, 0x00000018 }, |
| { 0x000b0000, 0x00000004 }, |
| { 0x18c0e562, 0x00000004 }, |
| { 0x00000078, 0x00000008 }, |
| { 0x00c00077, 0x00000008 }, |
| { 0x000700d5, 0x00000004 }, |
| { 0x00000084, 0x00000038 }, |
| { 0x000ca086, 0x00000030 }, |
| { 0x080045bb, 0x00000004 }, |
| { 0x000c2087, 0x00000030 }, |
| { 0x0800e5bc, 0000000000 }, |
| { 0x0000e5bb, 0x00000004 }, |
| { 0x0000e5bc, 0000000000 }, |
| { 0x00120000, 0x0000000c }, |
| { 0x00120000, 0x00000004 }, |
| { 0x001b0002, 0x0000000c }, |
| { 0x0000a000, 0x00000004 }, |
| { 0x0000e821, 0x00000004 }, |
| { 0x0000e800, 0000000000 }, |
| { 0x0000e821, 0x00000004 }, |
| { 0x0000e82e, 0000000000 }, |
| { 0x02cca000, 0x00000004 }, |
| { 0x00140000, 0x00000004 }, |
| { 0x000ce1cc, 0x00000004 }, |
| { 0x050de1cd, 0x00000004 }, |
| { 0x00400000, 0x00000004 }, |
| { 0x00000096, 0x00000018 }, |
| { 0x00c0a000, 0x00000004 }, |
| { 0x00000093, 0x00000008 }, |
| { 0x00000098, 0x00000020 }, |
| { 0x4200e000, 0000000000 }, |
| { 0x0000009f, 0x00000038 }, |
| { 0x000ca000, 0x00000004 }, |
| { 0x00140000, 0x00000004 }, |
| { 0x000c2000, 0x00000004 }, |
| { 0x00160000, 0x00000004 }, |
| { 0x700ce000, 0x00000004 }, |
| { 0x0014009b, 0x00000008 }, |
| { 0x4000e000, 0000000000 }, |
| { 0x02400000, 0x00000004 }, |
| { 0x400ee000, 0x00000004 }, |
| { 0x02400000, 0x00000004 }, |
| { 0x4000e000, 0000000000 }, |
| { 0x000c2000, 0x00000004 }, |
| { 0x0240e51b, 0x00000004 }, |
| { 0x0080e50a, 0x00000005 }, |
| { 0x0080e50b, 0x00000005 }, |
| { 0x00220000, 0x00000004 }, |
| { 0x000700d5, 0x00000004 }, |
| { 0x000000b2, 0x00000038 }, |
| { 0x000c2087, 0x00000030 }, |
| { 0x0880e5bd, 0x00000005 }, |
| { 0x000c2086, 0x00000030 }, |
| { 0x0800e5bb, 0x00000005 }, |
| { 0x000c2087, 0x00000030 }, |
| { 0x0880e5bc, 0x00000005 }, |
| { 0x000000b5, 0x00000008 }, |
| { 0x0080e5bd, 0x00000005 }, |
| { 0x0000e5bb, 0x00000005 }, |
| { 0x0080e5bc, 0x00000005 }, |
| { 0x00210000, 0x00000004 }, |
| { 0x02800000, 0x00000004 }, |
| { 0x00c000b9, 0x00000018 }, |
| { 0x4180e000, 0x00000040 }, |
| { 0x000000bb, 0x00000024 }, |
| { 0x01000000, 0x0000000c }, |
| { 0x0100e51d, 0x0000000c }, |
| { 0x000045bb, 0x00000004 }, |
| { 0x000080b5, 0x00000008 }, |
| { 0x0000f3ce, 0x00000004 }, |
| { 0x0140a000, 0x00000004 }, |
| { 0x00cc2000, 0x00000004 }, |
| { 0x08c053cf, 0x00000040 }, |
| { 0x00008000, 0000000000 }, |
| { 0x0000f3d2, 0x00000004 }, |
| { 0x0140a000, 0x00000004 }, |
| { 0x00cc2000, 0x00000004 }, |
| { 0x08c053d3, 0x00000040 }, |
| { 0x00008000, 0000000000 }, |
| { 0x0000f39d, 0x00000004 }, |
| { 0x0140a000, 0x00000004 }, |
| { 0x00cc2000, 0x00000004 }, |
| { 0x08c0539e, 0x00000040 }, |
| { 0x00008000, 0000000000 }, |
| { 0x03c00830, 0x00000004 }, |
| { 0x4200e000, 0000000000 }, |
| { 0x0000a000, 0x00000004 }, |
| { 0x200045e0, 0x00000004 }, |
| { 0x0000e5e1, 0000000000 }, |
| { 0x00000001, 0000000000 }, |
| { 0x000700d2, 0x00000004 }, |
| { 0x0800e394, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0x0000e8c4, 0x00000004 }, |
| { 0x0000e8c5, 0x00000004 }, |
| { 0x0000e8c6, 0x00000004 }, |
| { 0x0000e928, 0x00000004 }, |
| { 0x0000e929, 0x00000004 }, |
| { 0x0000e92a, 0x00000004 }, |
| { 0x000000d6, 0x00000008 }, |
| { 0x0000e928, 0x00000004 }, |
| { 0x0000e929, 0x00000004 }, |
| { 0x0000e92a, 0x00000004 }, |
| { 0x000000dd, 0x00000008 }, |
| { 0x00e00116, 0000000000 }, |
| { 0x000700e1, 0x00000004 }, |
| { 0x0800401c, 0x00000004 }, |
| { 0x200050e7, 0x00000004 }, |
| { 0x0000e01d, 0x00000004 }, |
| { 0x000000e4, 0x00000008 }, |
| { 0x02c02000, 0x00000004 }, |
| { 0x00060000, 0x00000004 }, |
| { 0x000000eb, 0x00000034 }, |
| { 0x000000e8, 0x00000008 }, |
| { 0x00008000, 0x00000004 }, |
| { 0xc000e000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0x000c2000, 0x00000004 }, |
| { 0x001d0018, 0x00000004 }, |
| { 0x001a0001, 0x00000004 }, |
| { 0x000000fb, 0x00000034 }, |
| { 0x0000004a, 0x00000008 }, |
| { 0x0500a04a, 0x00000008 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| }; |
| static const u32 RS690_cp_microcode[][2] = { |
| { 0x000000dd, 0x00000008 }, |
| { 0x000000df, 0x00000008 }, |
| { 0x000000a0, 0x00000008 }, |
| { 0x000000a4, 0x00000008 }, |
| { 0x4a554b4a, 0000000000 }, |
| { 0x4a4a4467, 0000000000 }, |
| { 0x55526f75, 0000000000 }, |
| { 0x4a7e7d65, 0000000000 }, |
| { 0x4ad74af6, 0000000000 }, |
| { 0x4ac94a4a, 0000000000 }, |
| { 0xcc898989, 0000000000 }, |
| { 0xc34ad3c5, 0000000000 }, |
| { 0x8e4a4a4a, 0000000000 }, |
| { 0x4a8a8a8a, 0000000000 }, |
| { 0x4a0f8c4a, 0000000000 }, |
| { 0x000ca000, 0x00000004 }, |
| { 0x000d0012, 0x00000038 }, |
| { 0x0000e8b4, 0x00000004 }, |
| { 0x000d0014, 0x00000038 }, |
| { 0x0000e8b6, 0x00000004 }, |
| { 0x000d0016, 0x00000038 }, |
| { 0x0000e854, 0x00000004 }, |
| { 0x000d0018, 0x00000038 }, |
| { 0x0000e855, 0x00000004 }, |
| { 0x000d001a, 0x00000038 }, |
| { 0x0000e856, 0x00000004 }, |
| { 0x000d001c, 0x00000038 }, |
| { 0x0000e857, 0x00000004 }, |
| { 0x000d001e, 0x00000038 }, |
| { 0x0000e824, 0x00000004 }, |
| { 0x000d0020, 0x00000038 }, |
| { 0x0000e825, 0x00000004 }, |
| { 0x000d0022, 0x00000038 }, |
| { 0x0000e830, 0x00000004 }, |
| { 0x000d0024, 0x00000038 }, |
| { 0x0000f0c0, 0x00000004 }, |
| { 0x000d0026, 0x00000038 }, |
| { 0x0000f0c1, 0x00000004 }, |
| { 0x000d0028, 0x00000038 }, |
| { 0x0000f041, 0x00000004 }, |
| { 0x000d002a, 0x00000038 }, |
| { 0x0000f184, 0x00000004 }, |
| { 0x000d002c, 0x00000038 }, |
| { 0x0000f185, 0x00000004 }, |
| { 0x000d002e, 0x00000038 }, |
| { 0x0000f186, 0x00000004 }, |
| { 0x000d0030, 0x00000038 }, |
| { 0x0000f187, 0x00000004 }, |
| { 0x000d0032, 0x00000038 }, |
| { 0x0000f180, 0x00000004 }, |
| { 0x000d0034, 0x00000038 }, |
| { 0x0000f393, 0x00000004 }, |
| { 0x000d0036, 0x00000038 }, |
| { 0x0000f38a, 0x00000004 }, |
| { 0x000d0038, 0x00000038 }, |
| { 0x0000f38e, 0x00000004 }, |
| { 0x0000e821, 0x00000004 }, |
| { 0x0140a000, 0x00000004 }, |
| { 0x00000043, 0x00000018 }, |
| { 0x00cce800, 0x00000004 }, |
| { 0x001b0001, 0x00000004 }, |
| { 0x08004800, 0x00000004 }, |
| { 0x001b0001, 0x00000004 }, |
| { 0x08004800, 0x00000004 }, |
| { 0x001b0001, 0x00000004 }, |
| { 0x08004800, 0x00000004 }, |
| { 0x0000003a, 0x00000008 }, |
| { 0x0000a000, 0000000000 }, |
| { 0x2000451d, 0x00000004 }, |
| { 0x0000e580, 0x00000004 }, |
| { 0x000ce581, 0x00000004 }, |
| { 0x08004580, 0x00000004 }, |
| { 0x000ce581, 0x00000004 }, |
| { 0x00000047, 0x00000008 }, |
| { 0x0000a000, 0000000000 }, |
| { 0x000c2000, 0x00000004 }, |
| { 0x0000e50e, 0x00000004 }, |
| { 0x00032000, 0x00000004 }, |
| { 0x00022051, 0x00000028 }, |
| { 0x00000051, 0x00000024 }, |
| { 0x0800450f, 0x00000004 }, |
| { 0x0000a04b, 0x00000008 }, |
| { 0x0000e565, 0x00000004 }, |
| { 0x0000e566, 0x00000004 }, |
| { 0x00000052, 0x00000008 }, |
| { 0x03cca5b4, 0x00000004 }, |
| { 0x05432000, 0x00000004 }, |
| { 0x00022000, 0x00000004 }, |
| { 0x4ccce05e, 0x00000030 }, |
| { 0x08274565, 0x00000004 }, |
| { 0x0000005e, 0x00000030 }, |
| { 0x08004564, 0x00000004 }, |
| { 0x0000e566, 0x00000004 }, |
| { 0x00000055, 0x00000008 }, |
| { 0x00802061, 0x00000010 }, |
| { 0x00202000, 0x00000004 }, |
| { 0x001b00ff, 0x00000004 }, |
| { 0x01000064, 0x00000010 }, |
| { 0x001f2000, 0x00000004 }, |
| { 0x001c00ff, 0x00000004 }, |
| { 0000000000, 0x0000000c }, |
| { 0x00000072, 0x00000030 }, |
| { 0x00000055, 0x00000008 }, |
| { 0x0000e576, 0x00000004 }, |
| { 0x0000e577, 0x00000004 }, |
| { 0x0000e50e, 0x00000004 }, |
| { 0x0000e50f, 0x00000004 }, |
| { 0x0140a000, 0x00000004 }, |
| { 0x00000069, 0x00000018 }, |
| { 0x00c0e5f9, 0x000000c2 }, |
| { 0x00000069, 0x00000008 }, |
| { 0x0014e50e, 0x00000004 }, |
| { 0x0040e50f, 0x00000004 }, |
| { 0x00c0006c, 0x00000008 }, |
| { 0x0000e570, 0x00000004 }, |
| { 0x0000e571, 0x00000004 }, |
| { 0x0000e572, 0x0000000c }, |
| { 0x0000a000, 0x00000004 }, |
| { 0x0140a000, 0x00000004 }, |
| { 0x0000e568, 0x00000004 }, |
| { 0x000c2000, 0x00000004 }, |
| { 0x00000076, 0x00000018 }, |
| { 0x000b0000, 0x00000004 }, |
| { 0x18c0e562, 0x00000004 }, |
| { 0x00000078, 0x00000008 }, |
| { 0x00c00077, 0x00000008 }, |
| { 0x000700cb, 0x00000004 }, |
| { 0x00000084, 0x00000038 }, |
| { 0x000ca086, 0x00000030 }, |
| { 0x080045bb, 0x00000004 }, |
| { 0x000c2087, 0x00000030 }, |
| { 0x0800e5bc, 0000000000 }, |
| { 0x0000e5bb, 0x00000004 }, |
| { 0x0000e5bc, 0000000000 }, |
| { 0x00120000, 0x0000000c }, |
| { 0x00120000, 0x00000004 }, |
| { 0x001b0002, 0x0000000c }, |
| { 0x0000a000, 0x00000004 }, |
| { 0x0000e821, 0x00000004 }, |
| { 0x0000e800, 0000000000 }, |
| { 0x0000e821, 0x00000004 }, |
| { 0x0000e82e, 0000000000 }, |
| { 0x02cca000, 0x00000004 }, |
| { 0x00140000, 0x00000004 }, |
| { 0x000ce1cc, 0x00000004 }, |
| { 0x050de1cd, 0x00000004 }, |
| { 0x00400000, 0x00000004 }, |
| { 0x00000096, 0x00000018 }, |
| { 0x00c0a000, 0x00000004 }, |
| { 0x00000093, 0x00000008 }, |
| { 0x00000098, 0x00000020 }, |
| { 0x4200e000, 0000000000 }, |
| { 0x0000009f, 0x00000038 }, |
| { 0x000ca000, 0x00000004 }, |
| { 0x00140000, 0x00000004 }, |
| { 0x000c2000, 0x00000004 }, |
| { 0x00160000, 0x00000004 }, |
| { 0x700ce000, 0x00000004 }, |
| { 0x0014009b, 0x00000008 }, |
| { 0x4000e000, 0000000000 }, |
| { 0x02400000, 0x00000004 }, |
| { 0x400ee000, 0x00000004 }, |
| { 0x02400000, 0x00000004 }, |
| { 0x4000e000, 0000000000 }, |
| { 0x00100000, 0x0000002c }, |
| { 0x00004000, 0000000000 }, |
| { 0x080045c8, 0x00000004 }, |
| { 0x00240005, 0x00000004 }, |
| { 0x08004d0b, 0x00000004 }, |
| { 0x000c2000, 0x00000004 }, |
| { 0x0240e51b, 0x00000004 }, |
| { 0x0080e50a, 0x00000005 }, |
| { 0x0080e50b, 0x00000005 }, |
| { 0x00220000, 0x00000004 }, |
| { 0x000700cb, 0x00000004 }, |
| { 0x000000b7, 0x00000038 }, |
| { 0x000c2087, 0x00000030 }, |
| { 0x0880e5bd, 0x00000005 }, |
| { 0x000c2086, 0x00000030 }, |
| { 0x0800e5bb, 0x00000005 }, |
| { 0x000c2087, 0x00000030 }, |
| { 0x0880e5bc, 0x00000005 }, |
| { 0x000000ba, 0x00000008 }, |
| { 0x0080e5bd, 0x00000005 }, |
| { 0x0000e5bb, 0x00000005 }, |
| { 0x0080e5bc, 0x00000005 }, |
| { 0x00210000, 0x00000004 }, |
| { 0x02800000, 0x00000004 }, |
| { 0x00c000be, 0x00000018 }, |
| { 0x4180e000, 0x00000040 }, |
| { 0x000000c0, 0x00000024 }, |
| { 0x01000000, 0x0000000c }, |
| { 0x0100e51d, 0x0000000c }, |
| { 0x000045bb, 0x00000004 }, |
| { 0x000080ba, 0x00000008 }, |
| { 0x03c00830, 0x00000004 }, |
| { 0x4200e000, 0000000000 }, |
| { 0x0000a000, 0x00000004 }, |
| { 0x200045e0, 0x00000004 }, |
| { 0x0000e5e1, 0000000000 }, |
| { 0x00000001, 0000000000 }, |
| { 0x000700c8, 0x00000004 }, |
| { 0x0800e394, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0x0000e8c4, 0x00000004 }, |
| { 0x0000e8c5, 0x00000004 }, |
| { 0x0000e8c6, 0x00000004 }, |
| { 0x0000e928, 0x00000004 }, |
| { 0x0000e929, 0x00000004 }, |
| { 0x0000e92a, 0x00000004 }, |
| { 0x000000cc, 0x00000008 }, |
| { 0x0000e928, 0x00000004 }, |
| { 0x0000e929, 0x00000004 }, |
| { 0x0000e92a, 0x00000004 }, |
| { 0x000000d3, 0x00000008 }, |
| { 0x02c02000, 0x00000004 }, |
| { 0x00060000, 0x00000004 }, |
| { 0x000000db, 0x00000034 }, |
| { 0x000000d8, 0x00000008 }, |
| { 0x00008000, 0x00000004 }, |
| { 0xc000e000, 0000000000 }, |
| { 0x000000e1, 0x00000030 }, |
| { 0x4200e000, 0000000000 }, |
| { 0x000000e1, 0x00000030 }, |
| { 0x4000e000, 0000000000 }, |
| { 0x0025001b, 0x00000004 }, |
| { 0x00230000, 0x00000004 }, |
| { 0x00250005, 0x00000004 }, |
| { 0x000000e6, 0x00000034 }, |
| { 0000000000, 0x0000000c }, |
| { 0x00244000, 0x00000004 }, |
| { 0x080045c8, 0x00000004 }, |
| { 0x00240005, 0x00000004 }, |
| { 0x08004d0b, 0x0000000c }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0x000c2000, 0x00000004 }, |
| { 0x001d0018, 0x00000004 }, |
| { 0x001a0001, 0x00000004 }, |
| { 0x000000fb, 0x00000034 }, |
| { 0x0000004a, 0x00000008 }, |
| { 0x0500a04a, 0x00000008 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| }; |
| static const u32 R520_cp_microcode[][2] = { |
| { 0x4200e000, 0000000000 }, |
| { 0x4000e000, 0000000000 }, |
| { 0x00000099, 0x00000008 }, |
| { 0x0000009d, 0x00000008 }, |
| { 0x4a554b4a, 0000000000 }, |
| { 0x4a4a4467, 0000000000 }, |
| { 0x55526f75, 0000000000 }, |
| { 0x4a7e7d65, 0000000000 }, |
| { 0xe0dae6f6, 0000000000 }, |
| { 0x4ac54a4a, 0000000000 }, |
| { 0xc8828282, 0000000000 }, |
| { 0xbf4acfc1, 0000000000 }, |
| { 0x87b04ad5, 0000000000 }, |
| { 0xb5838383, 0000000000 }, |
| { 0x4a0f85ba, 0000000000 }, |
| { 0x000ca000, 0x00000004 }, |
| { 0x000d0012, 0x00000038 }, |
| { 0x0000e8b4, 0x00000004 }, |
| { 0x000d0014, 0x00000038 }, |
| { 0x0000e8b6, 0x00000004 }, |
| { 0x000d0016, 0x00000038 }, |
| { 0x0000e854, 0x00000004 }, |
| { 0x000d0018, 0x00000038 }, |
| { 0x0000e855, 0x00000004 }, |
| { 0x000d001a, 0x00000038 }, |
| { 0x0000e856, 0x00000004 }, |
| { 0x000d001c, 0x00000038 }, |
| { 0x0000e857, 0x00000004 }, |
| { 0x000d001e, 0x00000038 }, |
| { 0x0000e824, 0x00000004 }, |
| { 0x000d0020, 0x00000038 }, |
| { 0x0000e825, 0x00000004 }, |
| { 0x000d0022, 0x00000038 }, |
| { 0x0000e830, 0x00000004 }, |
| { 0x000d0024, 0x00000038 }, |
| { 0x0000f0c0, 0x00000004 }, |
| { 0x000d0026, 0x00000038 }, |
| { 0x0000f0c1, 0x00000004 }, |
| { 0x000d0028, 0x00000038 }, |
| { 0x0000e000, 0x00000004 }, |
| { 0x000d002a, 0x00000038 }, |
| { 0x0000e000, 0x00000004 }, |
| { 0x000d002c, 0x00000038 }, |
| { 0x0000e000, 0x00000004 }, |
| { 0x000d002e, 0x00000038 }, |
| { 0x0000e000, 0x00000004 }, |
| { 0x000d0030, 0x00000038 }, |
| { 0x0000e000, 0x00000004 }, |
| { 0x000d0032, 0x00000038 }, |
| { 0x0000f180, 0x00000004 }, |
| { 0x000d0034, 0x00000038 }, |
| { 0x0000f393, 0x00000004 }, |
| { 0x000d0036, 0x00000038 }, |
| { 0x0000f38a, 0x00000004 }, |
| { 0x000d0038, 0x00000038 }, |
| { 0x0000f38e, 0x00000004 }, |
| { 0x0000e821, 0x00000004 }, |
| { 0x0140a000, 0x00000004 }, |
| { 0x00000043, 0x00000018 }, |
| { 0x00cce800, 0x00000004 }, |
| { 0x001b0001, 0x00000004 }, |
| { 0x08004800, 0x00000004 }, |
| { 0x001b0001, 0x00000004 }, |
| { 0x08004800, 0x00000004 }, |
| { 0x001b0001, 0x00000004 }, |
| { 0x08004800, 0x00000004 }, |
| { 0x0000003a, 0x00000008 }, |
| { 0x0000a000, 0000000000 }, |
| { 0x2000451d, 0x00000004 }, |
| { 0x0000e580, 0x00000004 }, |
| { 0x000ce581, 0x00000004 }, |
| { 0x08004580, 0x00000004 }, |
| { 0x000ce581, 0x00000004 }, |
| { 0x00000047, 0x00000008 }, |
| { 0x0000a000, 0000000000 }, |
| { 0x000c2000, 0x00000004 }, |
| { 0x0000e50e, 0x00000004 }, |
| { 0x00032000, 0x00000004 }, |
| { 0x00022051, 0x00000028 }, |
| { 0x00000051, 0x00000024 }, |
| { 0x0800450f, 0x00000004 }, |
| { 0x0000a04b, 0x00000008 }, |
| { 0x0000e565, 0x00000004 }, |
| { 0x0000e566, 0x00000004 }, |
| { 0x00000052, 0x00000008 }, |
| { 0x03cca5b4, 0x00000004 }, |
| { 0x05432000, 0x00000004 }, |
| { 0x00022000, 0x00000004 }, |
| { 0x4ccce05e, 0x00000030 }, |
| { 0x08274565, 0x00000004 }, |
| { 0x0000005e, 0x00000030 }, |
| { 0x08004564, 0x00000004 }, |
| { 0x0000e566, 0x00000004 }, |
| { 0x00000055, 0x00000008 }, |
| { 0x00802061, 0x00000010 }, |
| { 0x00202000, 0x00000004 }, |
| { 0x001b00ff, 0x00000004 }, |
| { 0x01000064, 0x00000010 }, |
| { 0x001f2000, 0x00000004 }, |
| { 0x001c00ff, 0x00000004 }, |
| { 0000000000, 0x0000000c }, |
| { 0x00000072, 0x00000030 }, |
| { 0x00000055, 0x00000008 }, |
| { 0x0000e576, 0x00000004 }, |
| { 0x0000e577, 0x00000004 }, |
| { 0x0000e50e, 0x00000004 }, |
| { 0x0000e50f, 0x00000004 }, |
| { 0x0140a000, 0x00000004 }, |
| { 0x00000069, 0x00000018 }, |
| { 0x00c0e5f9, 0x000000c2 }, |
| { 0x00000069, 0x00000008 }, |
| { 0x0014e50e, 0x00000004 }, |
| { 0x0040e50f, 0x00000004 }, |
| { 0x00c0006c, 0x00000008 }, |
| { 0x0000e570, 0x00000004 }, |
| { 0x0000e571, 0x00000004 }, |
| { 0x0000e572, 0x0000000c }, |
| { 0x0000a000, 0x00000004 }, |
| { 0x0140a000, 0x00000004 }, |
| { 0x0000e568, 0x00000004 }, |
| { 0x000c2000, 0x00000004 }, |
| { 0x00000076, 0x00000018 }, |
| { 0x000b0000, 0x00000004 }, |
| { 0x18c0e562, 0x00000004 }, |
| { 0x00000078, 0x00000008 }, |
| { 0x00c00077, 0x00000008 }, |
| { 0x000700c7, 0x00000004 }, |
| { 0x00000080, 0x00000038 }, |
| { 0x0000e5bb, 0x00000004 }, |
| { 0x0000e5bc, 0000000000 }, |
| { 0x0000a000, 0x00000004 }, |
| { 0x0000e821, 0x00000004 }, |
| { 0x0000e800, 0000000000 }, |
| { 0x0000e821, 0x00000004 }, |
| { 0x0000e82e, 0000000000 }, |
| { 0x02cca000, 0x00000004 }, |
| { 0x00140000, 0x00000004 }, |
| { 0x000ce1cc, 0x00000004 }, |
| { 0x050de1cd, 0x00000004 }, |
| { 0x00400000, 0x00000004 }, |
| { 0x0000008f, 0x00000018 }, |
| { 0x00c0a000, 0x00000004 }, |
| { 0x0000008c, 0x00000008 }, |
| { 0x00000091, 0x00000020 }, |
| { 0x4200e000, 0000000000 }, |
| { 0x00000098, 0x00000038 }, |
| { 0x000ca000, 0x00000004 }, |
| { 0x00140000, 0x00000004 }, |
| { 0x000c2000, 0x00000004 }, |
| { 0x00160000, 0x00000004 }, |
| { 0x700ce000, 0x00000004 }, |
| { 0x00140094, 0x00000008 }, |
| { 0x4000e000, 0000000000 }, |
| { 0x02400000, 0x00000004 }, |
| { 0x400ee000, 0x00000004 }, |
| { 0x02400000, 0x00000004 }, |
| { 0x4000e000, 0000000000 }, |
| { 0x000c2000, 0x00000004 }, |
| { 0x0240e51b, 0x00000004 }, |
| { 0x0080e50a, 0x00000005 }, |
| { 0x0080e50b, 0x00000005 }, |
| { 0x00220000, 0x00000004 }, |
| { 0x000700c7, 0x00000004 }, |
| { 0x000000a4, 0x00000038 }, |
| { 0x0080e5bd, 0x00000005 }, |
| { 0x0000e5bb, 0x00000005 }, |
| { 0x0080e5bc, 0x00000005 }, |
| { 0x00210000, 0x00000004 }, |
| { 0x02800000, 0x00000004 }, |
| { 0x00c000ab, 0x00000018 }, |
| { 0x4180e000, 0x00000040 }, |
| { 0x000000ad, 0x00000024 }, |
| { 0x01000000, 0x0000000c }, |
| { 0x0100e51d, 0x0000000c }, |
| { 0x000045bb, 0x00000004 }, |
| { 0x000080a7, 0x00000008 }, |
| { 0x0000f3ce, 0x00000004 }, |
| { 0x0140a000, 0x00000004 }, |
| { 0x00cc2000, 0x00000004 }, |
| { 0x08c053cf, 0x00000040 }, |
| { 0x00008000, 0000000000 }, |
| { 0x0000f3d2, 0x00000004 }, |
| { 0x0140a000, 0x00000004 }, |
| { 0x00cc2000, 0x00000004 }, |
| { 0x08c053d3, 0x00000040 }, |
| { 0x00008000, 0000000000 }, |
| { 0x0000f39d, 0x00000004 }, |
| { 0x0140a000, 0x00000004 }, |
| { 0x00cc2000, 0x00000004 }, |
| { 0x08c0539e, 0x00000040 }, |
| { 0x00008000, 0000000000 }, |
| { 0x03c00830, 0x00000004 }, |
| { 0x4200e000, 0000000000 }, |
| { 0x0000a000, 0x00000004 }, |
| { 0x200045e0, 0x00000004 }, |
| { 0x0000e5e1, 0000000000 }, |
| { 0x00000001, 0000000000 }, |
| { 0x000700c4, 0x00000004 }, |
| { 0x0800e394, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0x0000e8c4, 0x00000004 }, |
| { 0x0000e8c5, 0x00000004 }, |
| { 0x0000e8c6, 0x00000004 }, |
| { 0x0000e928, 0x00000004 }, |
| { 0x0000e929, 0x00000004 }, |
| { 0x0000e92a, 0x00000004 }, |
| { 0x000000c8, 0x00000008 }, |
| { 0x0000e928, 0x00000004 }, |
| { 0x0000e929, 0x00000004 }, |
| { 0x0000e92a, 0x00000004 }, |
| { 0x000000cf, 0x00000008 }, |
| { 0xdeadbeef, 0000000000 }, |
| { 0x00000116, 0000000000 }, |
| { 0x000700d3, 0x00000004 }, |
| { 0x080050e7, 0x00000004 }, |
| { 0x000700d4, 0x00000004 }, |
| { 0x0800401c, 0x00000004 }, |
| { 0x0000e01d, 0000000000 }, |
| { 0x02c02000, 0x00000004 }, |
| { 0x00060000, 0x00000004 }, |
| { 0x000000de, 0x00000034 }, |
| { 0x000000db, 0x00000008 }, |
| { 0x00008000, 0x00000004 }, |
| { 0xc000e000, 0000000000 }, |
| { 0x0000e1cc, 0x00000004 }, |
| { 0x0500e1cd, 0x00000004 }, |
| { 0x000ca000, 0x00000004 }, |
| { 0x000000e5, 0x00000034 }, |
| { 0x000000e1, 0x00000008 }, |
| { 0x0000a000, 0000000000 }, |
| { 0x0019e1cc, 0x00000004 }, |
| { 0x001b0001, 0x00000004 }, |
| { 0x0500a000, 0x00000004 }, |
| { 0x080041cd, 0x00000004 }, |
| { 0x000ca000, 0x00000004 }, |
| { 0x000000fb, 0x00000034 }, |
| { 0x0000004a, 0x00000008 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0x000c2000, 0x00000004 }, |
| { 0x001d0018, 0x00000004 }, |
| { 0x001a0001, 0x00000004 }, |
| { 0x000000fb, 0x00000034 }, |
| { 0x0000004a, 0x00000008 }, |
| { 0x0500a04a, 0x00000008 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| { 0000000000, 0000000000 }, |
| }; |
| #endif |
| /drivers/video/drm/radeon/radeon_mode.h |
|---|
| 0,0 → 1,400 |
| /* |
| * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and |
| * VA Linux Systems Inc., Fremont, California. |
| * Copyright 2008 Red Hat Inc. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice shall be included in |
| * all copies or substantial portions of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| * OTHER DEALINGS IN THE SOFTWARE. |
| * |
| * Original Authors: |
| * Kevin E. Martin, Rickard E. Faith, Alan Hourihane |
| * |
| * Kernel port Author: Dave Airlie |
| */ |
| #ifndef RADEON_MODE_H |
| #define RADEON_MODE_H |
| #include "drm_mode.h" |
| #include "drm_crtc.h" |
| //#include <drm_edid.h> |
| //#include <linux/i2c.h> |
| //#include <linux/i2c-id.h> |
| //#include <linux/i2c-algo-bit.h> |
| #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base) |
| #define to_radeon_connector(x) container_of(x, struct radeon_connector, base) |
| #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base) |
| #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base) |
| enum radeon_connector_type { |
| CONNECTOR_NONE, |
| CONNECTOR_VGA, |
| CONNECTOR_DVI_I, |
| CONNECTOR_DVI_D, |
| CONNECTOR_DVI_A, |
| CONNECTOR_STV, |
| CONNECTOR_CTV, |
| CONNECTOR_LVDS, |
| CONNECTOR_DIGITAL, |
| CONNECTOR_SCART, |
| CONNECTOR_HDMI_TYPE_A, |
| CONNECTOR_HDMI_TYPE_B, |
| CONNECTOR_0XC, |
| CONNECTOR_0XD, |
| CONNECTOR_DIN, |
| CONNECTOR_DISPLAY_PORT, |
| CONNECTOR_UNSUPPORTED |
| }; |
| enum radeon_dvi_type { |
| DVI_AUTO, |
| DVI_DIGITAL, |
| DVI_ANALOG |
| }; |
| enum radeon_rmx_type { |
| RMX_OFF, |
| RMX_FULL, |
| RMX_CENTER, |
| RMX_ASPECT |
| }; |
| enum radeon_tv_std { |
| TV_STD_NTSC, |
| TV_STD_PAL, |
| TV_STD_PAL_M, |
| TV_STD_PAL_60, |
| TV_STD_NTSC_J, |
| TV_STD_SCART_PAL, |
| TV_STD_SECAM, |
| TV_STD_PAL_CN, |
| }; |
| struct radeon_i2c_bus_rec { |
| bool valid; |
| uint32_t mask_clk_reg; |
| uint32_t mask_data_reg; |
| uint32_t a_clk_reg; |
| uint32_t a_data_reg; |
| uint32_t put_clk_reg; |
| uint32_t put_data_reg; |
| uint32_t get_clk_reg; |
| uint32_t get_data_reg; |
| uint32_t mask_clk_mask; |
| uint32_t mask_data_mask; |
| uint32_t put_clk_mask; |
| uint32_t put_data_mask; |
| uint32_t get_clk_mask; |
| uint32_t get_data_mask; |
| uint32_t a_clk_mask; |
| uint32_t a_data_mask; |
| }; |
| struct radeon_tmds_pll { |
| uint32_t freq; |
| uint32_t value; |
| }; |
| #define RADEON_MAX_BIOS_CONNECTOR 16 |
| #define RADEON_PLL_USE_BIOS_DIVS (1 << 0) |
| #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) |
| #define RADEON_PLL_USE_REF_DIV (1 << 2) |
| #define RADEON_PLL_LEGACY (1 << 3) |
| #define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) |
| #define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5) |
| #define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6) |
| #define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7) |
| #define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8) |
| #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) |
| #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) |
| struct radeon_pll { |
| uint16_t reference_freq; |
| uint16_t reference_div; |
| uint32_t pll_in_min; |
| uint32_t pll_in_max; |
| uint32_t pll_out_min; |
| uint32_t pll_out_max; |
| uint16_t xclk; |
| uint32_t min_ref_div; |
| uint32_t max_ref_div; |
| uint32_t min_post_div; |
| uint32_t max_post_div; |
| uint32_t min_feedback_div; |
| uint32_t max_feedback_div; |
| uint32_t min_frac_feedback_div; |
| uint32_t max_frac_feedback_div; |
| uint32_t best_vco; |
| }; |
| struct radeon_i2c_chan { |
| struct drm_device *dev; |
| // struct i2c_adapter adapter; |
| // struct i2c_algo_bit_data algo; |
| struct radeon_i2c_bus_rec rec; |
| }; |
| /* mostly for macs, but really any system without connector tables */ |
| enum radeon_connector_table { |
| CT_NONE, |
| CT_GENERIC, |
| CT_IBOOK, |
| CT_POWERBOOK_EXTERNAL, |
| CT_POWERBOOK_INTERNAL, |
| CT_POWERBOOK_VGA, |
| CT_MINI_EXTERNAL, |
| CT_MINI_INTERNAL, |
| CT_IMAC_G5_ISIGHT, |
| CT_EMAC, |
| }; |
| struct radeon_mode_info { |
| struct atom_context *atom_context; |
| enum radeon_connector_table connector_table; |
| bool mode_config_initialized; |
| }; |
| struct radeon_crtc { |
| // struct drm_crtc base; |
| int crtc_id; |
| u16_t lut_r[256], lut_g[256], lut_b[256]; |
| bool enabled; |
| bool can_tile; |
| uint32_t crtc_offset; |
| struct radeon_framebuffer *fbdev_fb; |
| // struct drm_mode_set mode_set; |
| // struct drm_gem_object *cursor_bo; |
| uint64_t cursor_addr; |
| int cursor_width; |
| int cursor_height; |
| }; |
| #define RADEON_USE_RMX 1 |
| struct radeon_native_mode { |
| /* preferred mode */ |
| uint32_t panel_xres, panel_yres; |
| uint32_t hoverplus, hsync_width; |
| uint32_t hblank; |
| uint32_t voverplus, vsync_width; |
| uint32_t vblank; |
| uint32_t dotclock; |
| uint32_t flags; |
| }; |
| struct radeon_encoder_primary_dac { |
| /* legacy primary dac */ |
| uint32_t ps2_pdac_adj; |
| }; |
| struct radeon_encoder_lvds { |
| /* legacy lvds */ |
| uint16_t panel_vcc_delay; |
| uint8_t panel_pwr_delay; |
| uint8_t panel_digon_delay; |
| uint8_t panel_blon_delay; |
| uint16_t panel_ref_divider; |
| uint8_t panel_post_divider; |
| uint16_t panel_fb_divider; |
| bool use_bios_dividers; |
| uint32_t lvds_gen_cntl; |
| /* panel mode */ |
| struct radeon_native_mode native_mode; |
| }; |
| struct radeon_encoder_tv_dac { |
| /* legacy tv dac */ |
| uint32_t ps2_tvdac_adj; |
| uint32_t ntsc_tvdac_adj; |
| uint32_t pal_tvdac_adj; |
| enum radeon_tv_std tv_std; |
| }; |
| struct radeon_encoder_int_tmds { |
| /* legacy int tmds */ |
| struct radeon_tmds_pll tmds_pll[4]; |
| }; |
| struct radeon_encoder_atom_dig { |
| /* atom dig */ |
| bool coherent_mode; |
| int dig_block; |
| /* atom lvds */ |
| uint32_t lvds_misc; |
| uint16_t panel_pwr_delay; |
| /* panel mode */ |
| struct radeon_native_mode native_mode; |
| }; |
| struct radeon_encoder { |
| struct drm_encoder base; |
| uint32_t encoder_id; |
| uint32_t devices; |
| uint32_t flags; |
| uint32_t pixel_clock; |
| enum radeon_rmx_type rmx_type; |
| struct radeon_native_mode native_mode; |
| void *enc_priv; |
| }; |
| struct radeon_connector_atom_dig { |
| uint32_t igp_lane_info; |
| bool linkb; |
| }; |
| struct radeon_connector { |
| struct drm_connector base; |
| uint32_t connector_id; |
| uint32_t devices; |
| struct radeon_i2c_chan *ddc_bus; |
| int use_digital; |
| void *con_priv; |
| }; |
| struct radeon_framebuffer { |
| // struct drm_framebuffer base; |
| // struct drm_gem_object *obj; |
| }; |
| extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, |
| struct radeon_i2c_bus_rec *rec, |
| const char *name); |
| extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c); |
| extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector); |
| extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector); |
| //extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector); |
| extern void radeon_compute_pll(struct radeon_pll *pll, |
| uint64_t freq, |
| uint32_t *dot_clock_p, |
| uint32_t *fb_div_p, |
| uint32_t *frac_fb_div_p, |
| uint32_t *ref_div_p, |
| uint32_t *post_div_p, |
| int flags); |
| struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index); |
| struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv); |
| struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv); |
| struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index); |
| struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index); |
| extern void atombios_external_tmds_setup(struct drm_encoder *encoder, int action); |
| extern int atombios_get_encoder_mode(struct drm_encoder *encoder); |
| /* |
| extern void radeon_crtc_load_lut(struct drm_crtc *crtc); |
| extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
| struct drm_framebuffer *old_fb); |
| extern int atombios_crtc_mode_set(struct drm_crtc *crtc, |
| struct drm_display_mode *mode, |
| struct drm_display_mode *adjusted_mode, |
| int x, int y, |
| struct drm_framebuffer *old_fb); |
| extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode); |
| extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
| struct drm_framebuffer *old_fb); |
| extern void radeon_legacy_atom_set_surface(struct drm_crtc *crtc); |
| extern int radeon_crtc_cursor_set(struct drm_crtc *crtc, |
| struct drm_file *file_priv, |
| uint32_t handle, |
| uint32_t width, |
| uint32_t height); |
| extern int radeon_crtc_cursor_move(struct drm_crtc *crtc, |
| int x, int y); |
| extern bool radeon_atom_get_clock_info(struct drm_device *dev); |
| extern bool radeon_combios_get_clock_info(struct drm_device *dev); |
| extern struct radeon_encoder_atom_dig * |
| radeon_atombios_get_lvds_info(struct radeon_encoder *encoder); |
| extern struct radeon_encoder_int_tmds * |
| radeon_atombios_get_tmds_info(struct radeon_encoder *encoder); |
| extern struct radeon_encoder_primary_dac * |
| radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder); |
| extern struct radeon_encoder_tv_dac * |
| radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder); |
| extern struct radeon_encoder_lvds * |
| radeon_combios_get_lvds_info(struct radeon_encoder *encoder); |
| extern struct radeon_encoder_int_tmds * |
| radeon_combios_get_tmds_info(struct radeon_encoder *encoder); |
| extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder); |
| extern struct radeon_encoder_tv_dac * |
| radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder); |
| extern struct radeon_encoder_primary_dac * |
| radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder); |
| extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock); |
| extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev); |
| extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock); |
| extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev); |
| extern void |
| radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); |
| extern void |
| radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); |
| extern void |
| radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc); |
| extern void |
| radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on); |
| extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, |
| u16 blue, int regno); |
| struct drm_framebuffer *radeon_framebuffer_create(struct drm_device *dev, |
| struct drm_mode_fb_cmd *mode_cmd, |
| struct drm_gem_object *obj); |
| int radeonfb_probe(struct drm_device *dev); |
| int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb); |
| bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev); |
| bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev); |
| void radeon_atombios_init_crtc(struct drm_device *dev, |
| struct radeon_crtc *radeon_crtc); |
| void radeon_legacy_init_crtc(struct drm_device *dev, |
| struct radeon_crtc *radeon_crtc); |
| void radeon_i2c_do_lock(struct radeon_connector *radeon_connector, int lock_state); |
| void radeon_get_clock_info(struct drm_device *dev); |
| extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev); |
| extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev); |
| void radeon_rmx_mode_fixup(struct drm_encoder *encoder, |
| struct drm_display_mode *mode, |
| struct drm_display_mode *adjusted_mode); |
| void radeon_enc_destroy(struct drm_encoder *encoder); |
| void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); |
| void radeon_combios_asic_init(struct drm_device *dev); |
| extern int radeon_static_clocks_init(struct drm_device *dev); |
| void radeon_init_disp_bw_legacy(struct drm_device *dev, |
| struct drm_display_mode *mode1, |
| uint32_t pixel_bytes1, |
| struct drm_display_mode *mode2, |
| uint32_t pixel_bytes2); |
| void radeon_init_disp_bw_avivo(struct drm_device *dev, |
| struct drm_display_mode *mode1, |
| uint32_t pixel_bytes1, |
| struct drm_display_mode *mode2, |
| uint32_t pixel_bytes2); |
| void radeon_init_disp_bandwidth(struct drm_device *dev); |
| */ |
| #endif |
| /drivers/video/drm/radeon/radeon_reg.h |
|---|
| 0,0 → 1,3571 |
| /* |
| * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and |
| * VA Linux Systems Inc., Fremont, California. |
| * |
| * All Rights Reserved. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining |
| * a copy of this software and associated documentation files (the |
| * "Software"), to deal in the Software without restriction, including |
| * without limitation on the rights to use, copy, modify, merge, |
| * publish, distribute, sublicense, and/or sell copies of the Software, |
| * and to permit persons to whom the Software is furnished to do so, |
| * subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice (including the |
| * next paragraph) shall be included in all copies or substantial |
| * portions of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR |
| * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
| * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| * DEALINGS IN THE SOFTWARE. |
| */ |
| /* |
| * Authors: |
| * Kevin E. Martin <martin@xfree86.org> |
| * Rickard E. Faith <faith@valinux.com> |
| * Alan Hourihane <alanh@fairlite.demon.co.uk> |
| * |
| * References: |
| * |
| * !!!! FIXME !!!! |
| * RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical |
| * Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April |
| * 1999. |
| * |
| * !!!! FIXME !!!! |
| * RAGE 128 Software Development Manual (Technical Reference Manual P/N |
| * SDK-G04000 Rev. 0.01), ATI Technologies: June 1999. |
| * |
| */ |
| /* !!!! FIXME !!!! NOTE: THIS FILE HAS BEEN CONVERTED FROM r128_reg.h |
| * AND CONTAINS REGISTERS AND REGISTER DEFINITIONS THAT ARE NOT CORRECT |
| * ON THE RADEON. A FULL AUDIT OF THIS CODE IS NEEDED! */ |
| #ifndef _RADEON_REG_H_ |
| #define _RADEON_REG_H_ |
| #include "r300_reg.h" |
| #include "r500_reg.h" |
| #include "r600_reg.h" |
| #define RADEON_MC_AGP_LOCATION 0x014c |
| #define RADEON_MC_AGP_START_MASK 0x0000FFFF |
| #define RADEON_MC_AGP_START_SHIFT 0 |
| #define RADEON_MC_AGP_TOP_MASK 0xFFFF0000 |
| #define RADEON_MC_AGP_TOP_SHIFT 16 |
| #define RADEON_MC_FB_LOCATION 0x0148 |
| #define RADEON_MC_FB_START_MASK 0x0000FFFF |
| #define RADEON_MC_FB_START_SHIFT 0 |
| #define RADEON_MC_FB_TOP_MASK 0xFFFF0000 |
| #define RADEON_MC_FB_TOP_SHIFT 16 |
| #define RADEON_AGP_BASE_2 0x015c /* r200+ only */ |
| #define RADEON_AGP_BASE 0x0170 |
| #define ATI_DATATYPE_VQ 0 |
| #define ATI_DATATYPE_CI4 1 |
| #define ATI_DATATYPE_CI8 2 |
| #define ATI_DATATYPE_ARGB1555 3 |
| #define ATI_DATATYPE_RGB565 4 |
| #define ATI_DATATYPE_RGB888 5 |
| #define ATI_DATATYPE_ARGB8888 6 |
| #define ATI_DATATYPE_RGB332 7 |
| #define ATI_DATATYPE_Y8 8 |
| #define ATI_DATATYPE_RGB8 9 |
| #define ATI_DATATYPE_CI16 10 |
| #define ATI_DATATYPE_VYUY_422 11 |
| #define ATI_DATATYPE_YVYU_422 12 |
| #define ATI_DATATYPE_AYUV_444 14 |
| #define ATI_DATATYPE_ARGB4444 15 |
| /* Registers for 2D/Video/Overlay */ |
| #define RADEON_ADAPTER_ID 0x0f2c /* PCI */ |
| #define RADEON_AGP_BASE 0x0170 |
| #define RADEON_AGP_CNTL 0x0174 |
| # define RADEON_AGP_APER_SIZE_256MB (0x00 << 0) |
| # define RADEON_AGP_APER_SIZE_128MB (0x20 << 0) |
| # define RADEON_AGP_APER_SIZE_64MB (0x30 << 0) |
| # define RADEON_AGP_APER_SIZE_32MB (0x38 << 0) |
| # define RADEON_AGP_APER_SIZE_16MB (0x3c << 0) |
| # define RADEON_AGP_APER_SIZE_8MB (0x3e << 0) |
| # define RADEON_AGP_APER_SIZE_4MB (0x3f << 0) |
| # define RADEON_AGP_APER_SIZE_MASK (0x3f << 0) |
| #define RADEON_STATUS_PCI_CONFIG 0x06 |
| # define RADEON_CAP_LIST 0x100000 |
| #define RADEON_CAPABILITIES_PTR_PCI_CONFIG 0x34 /* offset in PCI config*/ |
| # define RADEON_CAP_PTR_MASK 0xfc /* mask off reserved bits of CAP_PTR */ |
| # define RADEON_CAP_ID_NULL 0x00 /* End of capability list */ |
| # define RADEON_CAP_ID_AGP 0x02 /* AGP capability ID */ |
| # define RADEON_CAP_ID_EXP 0x10 /* PCI Express */ |
| #define RADEON_AGP_COMMAND 0x0f60 /* PCI */ |
| #define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config*/ |
| # define RADEON_AGP_ENABLE (1<<8) |
| #define RADEON_AGP_PLL_CNTL 0x000b /* PLL */ |
| #define RADEON_AGP_STATUS 0x0f5c /* PCI */ |
| # define RADEON_AGP_1X_MODE 0x01 |
| # define RADEON_AGP_2X_MODE 0x02 |
| # define RADEON_AGP_4X_MODE 0x04 |
| # define RADEON_AGP_FW_MODE 0x10 |
| # define RADEON_AGP_MODE_MASK 0x17 |
| # define RADEON_AGPv3_MODE 0x08 |
| # define RADEON_AGPv3_4X_MODE 0x01 |
| # define RADEON_AGPv3_8X_MODE 0x02 |
| #define RADEON_ATTRDR 0x03c1 /* VGA */ |
| #define RADEON_ATTRDW 0x03c0 /* VGA */ |
| #define RADEON_ATTRX 0x03c0 /* VGA */ |
| #define RADEON_AUX_SC_CNTL 0x1660 |
| # define RADEON_AUX1_SC_EN (1 << 0) |
| # define RADEON_AUX1_SC_MODE_OR (0 << 1) |
| # define RADEON_AUX1_SC_MODE_NAND (1 << 1) |
| # define RADEON_AUX2_SC_EN (1 << 2) |
| # define RADEON_AUX2_SC_MODE_OR (0 << 3) |
| # define RADEON_AUX2_SC_MODE_NAND (1 << 3) |
| # define RADEON_AUX3_SC_EN (1 << 4) |
| # define RADEON_AUX3_SC_MODE_OR (0 << 5) |
| # define RADEON_AUX3_SC_MODE_NAND (1 << 5) |
| #define RADEON_AUX1_SC_BOTTOM 0x1670 |
| #define RADEON_AUX1_SC_LEFT 0x1664 |
| #define RADEON_AUX1_SC_RIGHT 0x1668 |
| #define RADEON_AUX1_SC_TOP 0x166c |
| #define RADEON_AUX2_SC_BOTTOM 0x1680 |
| #define RADEON_AUX2_SC_LEFT 0x1674 |
| #define RADEON_AUX2_SC_RIGHT 0x1678 |
| #define RADEON_AUX2_SC_TOP 0x167c |
| #define RADEON_AUX3_SC_BOTTOM 0x1690 |
| #define RADEON_AUX3_SC_LEFT 0x1684 |
| #define RADEON_AUX3_SC_RIGHT 0x1688 |
| #define RADEON_AUX3_SC_TOP 0x168c |
| #define RADEON_AUX_WINDOW_HORZ_CNTL 0x02d8 |
| #define RADEON_AUX_WINDOW_VERT_CNTL 0x02dc |
| #define RADEON_BASE_CODE 0x0f0b |
| #define RADEON_BIOS_0_SCRATCH 0x0010 |
| # define RADEON_FP_PANEL_SCALABLE (1 << 16) |
| # define RADEON_FP_PANEL_SCALE_EN (1 << 17) |
| # define RADEON_FP_CHIP_SCALE_EN (1 << 18) |
| # define RADEON_DRIVER_BRIGHTNESS_EN (1 << 26) |
| # define RADEON_DISPLAY_ROT_MASK (3 << 28) |
| # define RADEON_DISPLAY_ROT_00 (0 << 28) |
| # define RADEON_DISPLAY_ROT_90 (1 << 28) |
| # define RADEON_DISPLAY_ROT_180 (2 << 28) |
| # define RADEON_DISPLAY_ROT_270 (3 << 28) |
| #define RADEON_BIOS_1_SCRATCH 0x0014 |
| #define RADEON_BIOS_2_SCRATCH 0x0018 |
| #define RADEON_BIOS_3_SCRATCH 0x001c |
| #define RADEON_BIOS_4_SCRATCH 0x0020 |
| # define RADEON_CRT1_ATTACHED_MASK (3 << 0) |
| # define RADEON_CRT1_ATTACHED_MONO (1 << 0) |
| # define RADEON_CRT1_ATTACHED_COLOR (2 << 0) |
| # define RADEON_LCD1_ATTACHED (1 << 2) |
| # define RADEON_DFP1_ATTACHED (1 << 3) |
| # define RADEON_TV1_ATTACHED_MASK (3 << 4) |
| # define RADEON_TV1_ATTACHED_COMP (1 << 4) |
| # define RADEON_TV1_ATTACHED_SVIDEO (2 << 4) |
| # define RADEON_CRT2_ATTACHED_MASK (3 << 8) |
| # define RADEON_CRT2_ATTACHED_MONO (1 << 8) |
| # define RADEON_CRT2_ATTACHED_COLOR (2 << 8) |
| # define RADEON_DFP2_ATTACHED (1 << 11) |
| #define RADEON_BIOS_5_SCRATCH 0x0024 |
| # define RADEON_LCD1_ON (1 << 0) |
| # define RADEON_CRT1_ON (1 << 1) |
| # define RADEON_TV1_ON (1 << 2) |
| # define RADEON_DFP1_ON (1 << 3) |
| # define RADEON_CRT2_ON (1 << 5) |
| # define RADEON_CV1_ON (1 << 6) |
| # define RADEON_DFP2_ON (1 << 7) |
| # define RADEON_LCD1_CRTC_MASK (1 << 8) |
| # define RADEON_LCD1_CRTC_SHIFT 8 |
| # define RADEON_CRT1_CRTC_MASK (1 << 9) |
| # define RADEON_CRT1_CRTC_SHIFT 9 |
| # define RADEON_TV1_CRTC_MASK (1 << 10) |
| # define RADEON_TV1_CRTC_SHIFT 10 |
| # define RADEON_DFP1_CRTC_MASK (1 << 11) |
| # define RADEON_DFP1_CRTC_SHIFT 11 |
| # define RADEON_CRT2_CRTC_MASK (1 << 12) |
| # define RADEON_CRT2_CRTC_SHIFT 12 |
| # define RADEON_CV1_CRTC_MASK (1 << 13) |
| # define RADEON_CV1_CRTC_SHIFT 13 |
| # define RADEON_DFP2_CRTC_MASK (1 << 14) |
| # define RADEON_DFP2_CRTC_SHIFT 14 |
| # define RADEON_ACC_REQ_LCD1 (1 << 16) |
| # define RADEON_ACC_REQ_CRT1 (1 << 17) |
| # define RADEON_ACC_REQ_TV1 (1 << 18) |
| # define RADEON_ACC_REQ_DFP1 (1 << 19) |
| # define RADEON_ACC_REQ_CRT2 (1 << 21) |
| # define RADEON_ACC_REQ_TV2 (1 << 22) |
| # define RADEON_ACC_REQ_DFP2 (1 << 23) |
| #define RADEON_BIOS_6_SCRATCH 0x0028 |
| # define RADEON_ACC_MODE_CHANGE (1 << 2) |
| # define RADEON_EXT_DESKTOP_MODE (1 << 3) |
| # define RADEON_LCD_DPMS_ON (1 << 20) |
| # define RADEON_CRT_DPMS_ON (1 << 21) |
| # define RADEON_TV_DPMS_ON (1 << 22) |
| # define RADEON_DFP_DPMS_ON (1 << 23) |
| # define RADEON_DPMS_MASK (3 << 24) |
| # define RADEON_DPMS_ON (0 << 24) |
| # define RADEON_DPMS_STANDBY (1 << 24) |
| # define RADEON_DPMS_SUSPEND (2 << 24) |
| # define RADEON_DPMS_OFF (3 << 24) |
| # define RADEON_SCREEN_BLANKING (1 << 26) |
| # define RADEON_DRIVER_CRITICAL (1 << 27) |
| # define RADEON_DISPLAY_SWITCHING_DIS (1 << 30) |
| #define RADEON_BIOS_7_SCRATCH 0x002c |
| # define RADEON_SYS_HOTKEY (1 << 10) |
| # define RADEON_DRV_LOADED (1 << 12) |
| #define RADEON_BIOS_ROM 0x0f30 /* PCI */ |
| #define RADEON_BIST 0x0f0f /* PCI */ |
| #define RADEON_BRUSH_DATA0 0x1480 |
| #define RADEON_BRUSH_DATA1 0x1484 |
| #define RADEON_BRUSH_DATA10 0x14a8 |
| #define RADEON_BRUSH_DATA11 0x14ac |
| #define RADEON_BRUSH_DATA12 0x14b0 |
| #define RADEON_BRUSH_DATA13 0x14b4 |
| #define RADEON_BRUSH_DATA14 0x14b8 |
| #define RADEON_BRUSH_DATA15 0x14bc |
| #define RADEON_BRUSH_DATA16 0x14c0 |
| #define RADEON_BRUSH_DATA17 0x14c4 |
| #define RADEON_BRUSH_DATA18 0x14c8 |
| #define RADEON_BRUSH_DATA19 0x14cc |
| #define RADEON_BRUSH_DATA2 0x1488 |
| #define RADEON_BRUSH_DATA20 0x14d0 |
| #define RADEON_BRUSH_DATA21 0x14d4 |
| #define RADEON_BRUSH_DATA22 0x14d8 |
| #define RADEON_BRUSH_DATA23 0x14dc |
| #define RADEON_BRUSH_DATA24 0x14e0 |
| #define RADEON_BRUSH_DATA25 0x14e4 |
| #define RADEON_BRUSH_DATA26 0x14e8 |
| #define RADEON_BRUSH_DATA27 0x14ec |
| #define RADEON_BRUSH_DATA28 0x14f0 |
| #define RADEON_BRUSH_DATA29 0x14f4 |
| #define RADEON_BRUSH_DATA3 0x148c |
| #define RADEON_BRUSH_DATA30 0x14f8 |
| #define RADEON_BRUSH_DATA31 0x14fc |
| #define RADEON_BRUSH_DATA32 0x1500 |
| #define RADEON_BRUSH_DATA33 0x1504 |
| #define RADEON_BRUSH_DATA34 0x1508 |
| #define RADEON_BRUSH_DATA35 0x150c |
| #define RADEON_BRUSH_DATA36 0x1510 |
| #define RADEON_BRUSH_DATA37 0x1514 |
| #define RADEON_BRUSH_DATA38 0x1518 |
| #define RADEON_BRUSH_DATA39 0x151c |
| #define RADEON_BRUSH_DATA4 0x1490 |
| #define RADEON_BRUSH_DATA40 0x1520 |
| #define RADEON_BRUSH_DATA41 0x1524 |
| #define RADEON_BRUSH_DATA42 0x1528 |
| #define RADEON_BRUSH_DATA43 0x152c |
| #define RADEON_BRUSH_DATA44 0x1530 |
| #define RADEON_BRUSH_DATA45 0x1534 |
| #define RADEON_BRUSH_DATA46 0x1538 |
| #define RADEON_BRUSH_DATA47 0x153c |
| #define RADEON_BRUSH_DATA48 0x1540 |
| #define RADEON_BRUSH_DATA49 0x1544 |
| #define RADEON_BRUSH_DATA5 0x1494 |
| #define RADEON_BRUSH_DATA50 0x1548 |
| #define RADEON_BRUSH_DATA51 0x154c |
| #define RADEON_BRUSH_DATA52 0x1550 |
| #define RADEON_BRUSH_DATA53 0x1554 |
| #define RADEON_BRUSH_DATA54 0x1558 |
| #define RADEON_BRUSH_DATA55 0x155c |
| #define RADEON_BRUSH_DATA56 0x1560 |
| #define RADEON_BRUSH_DATA57 0x1564 |
| #define RADEON_BRUSH_DATA58 0x1568 |
| #define RADEON_BRUSH_DATA59 0x156c |
| #define RADEON_BRUSH_DATA6 0x1498 |
| #define RADEON_BRUSH_DATA60 0x1570 |
| #define RADEON_BRUSH_DATA61 0x1574 |
| #define RADEON_BRUSH_DATA62 0x1578 |
| #define RADEON_BRUSH_DATA63 0x157c |
| #define RADEON_BRUSH_DATA7 0x149c |
| #define RADEON_BRUSH_DATA8 0x14a0 |
| #define RADEON_BRUSH_DATA9 0x14a4 |
| #define RADEON_BRUSH_SCALE 0x1470 |
| #define RADEON_BRUSH_Y_X 0x1474 |
| #define RADEON_BUS_CNTL 0x0030 |
| # define RADEON_BUS_MASTER_DIS (1 << 6) |
| # define RADEON_BUS_BIOS_DIS_ROM (1 << 12) |
| # define RADEON_BUS_RD_DISCARD_EN (1 << 24) |
| # define RADEON_BUS_RD_ABORT_EN (1 << 25) |
| # define RADEON_BUS_MSTR_DISCONNECT_EN (1 << 28) |
| # define RADEON_BUS_WRT_BURST (1 << 29) |
| # define RADEON_BUS_READ_BURST (1 << 30) |
| #define RADEON_BUS_CNTL1 0x0034 |
| # define RADEON_BUS_WAIT_ON_LOCK_EN (1 << 4) |
| /* #define RADEON_PCIE_INDEX 0x0030 */ |
| /* #define RADEON_PCIE_DATA 0x0034 */ |
| #define RADEON_PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE */ |
| # define RADEON_PCIE_LC_LINK_WIDTH_SHIFT 0 |
| # define RADEON_PCIE_LC_LINK_WIDTH_MASK 0x7 |
| # define RADEON_PCIE_LC_LINK_WIDTH_X0 0 |
| # define RADEON_PCIE_LC_LINK_WIDTH_X1 1 |
| # define RADEON_PCIE_LC_LINK_WIDTH_X2 2 |
| # define RADEON_PCIE_LC_LINK_WIDTH_X4 3 |
| # define RADEON_PCIE_LC_LINK_WIDTH_X8 4 |
| # define RADEON_PCIE_LC_LINK_WIDTH_X12 5 |
| # define RADEON_PCIE_LC_LINK_WIDTH_X16 6 |
| # define RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT 4 |
| # define RADEON_PCIE_LC_LINK_WIDTH_RD_MASK 0x70 |
| # define RADEON_PCIE_LC_RECONFIG_NOW (1 << 8) |
| # define RADEON_PCIE_LC_RECONFIG_LATER (1 << 9) |
| # define RADEON_PCIE_LC_SHORT_RECONFIG_EN (1 << 10) |
| #define RADEON_CACHE_CNTL 0x1724 |
| #define RADEON_CACHE_LINE 0x0f0c /* PCI */ |
| #define RADEON_CAPABILITIES_ID 0x0f50 /* PCI */ |
| #define RADEON_CAPABILITIES_PTR 0x0f34 /* PCI */ |
| #define RADEON_CLK_PIN_CNTL 0x0001 /* PLL */ |
| # define RADEON_DONT_USE_XTALIN (1 << 4) |
| # define RADEON_SCLK_DYN_START_CNTL (1 << 15) |
| #define RADEON_CLOCK_CNTL_DATA 0x000c |
| #define RADEON_CLOCK_CNTL_INDEX 0x0008 |
| # define RADEON_PLL_WR_EN (1 << 7) |
| # define RADEON_PLL_DIV_SEL (3 << 8) |
| # define RADEON_PLL2_DIV_SEL_MASK (~(3 << 8)) |
| #define RADEON_CLK_PWRMGT_CNTL 0x0014 |
| # define RADEON_ENGIN_DYNCLK_MODE (1 << 12) |
| # define RADEON_ACTIVE_HILO_LAT_MASK (3 << 13) |
| # define RADEON_ACTIVE_HILO_LAT_SHIFT 13 |
| # define RADEON_DISP_DYN_STOP_LAT_MASK (1 << 12) |
| # define RADEON_MC_BUSY (1 << 16) |
| # define RADEON_DLL_READY (1 << 19) |
| # define RADEON_CG_NO1_DEBUG_0 (1 << 24) |
| # define RADEON_CG_NO1_DEBUG_MASK (0x1f << 24) |
| # define RADEON_DYN_STOP_MODE_MASK (7 << 21) |
| # define RADEON_TVPLL_PWRMGT_OFF (1 << 30) |
| # define RADEON_TVCLK_TURNOFF (1 << 31) |
| #define RADEON_PLL_PWRMGT_CNTL 0x0015 /* PLL */ |
| # define RADEON_TCL_BYPASS_DISABLE (1 << 20) |
| #define RADEON_CLR_CMP_CLR_3D 0x1a24 |
| #define RADEON_CLR_CMP_CLR_DST 0x15c8 |
| #define RADEON_CLR_CMP_CLR_SRC 0x15c4 |
| #define RADEON_CLR_CMP_CNTL 0x15c0 |
| # define RADEON_SRC_CMP_EQ_COLOR (4 << 0) |
| # define RADEON_SRC_CMP_NEQ_COLOR (5 << 0) |
| # define RADEON_CLR_CMP_SRC_SOURCE (1 << 24) |
| #define RADEON_CLR_CMP_MASK 0x15cc |
| # define RADEON_CLR_CMP_MSK 0xffffffff |
| #define RADEON_CLR_CMP_MASK_3D 0x1A28 |
| #define RADEON_COMMAND 0x0f04 /* PCI */ |
| #define RADEON_COMPOSITE_SHADOW_ID 0x1a0c |
| #define RADEON_CONFIG_APER_0_BASE 0x0100 |
| #define RADEON_CONFIG_APER_1_BASE 0x0104 |
| #define RADEON_CONFIG_APER_SIZE 0x0108 |
| #define RADEON_CONFIG_BONDS 0x00e8 |
| #define RADEON_CONFIG_CNTL 0x00e0 |
| # define RADEON_CFG_ATI_REV_A11 (0 << 16) |
| # define RADEON_CFG_ATI_REV_A12 (1 << 16) |
| # define RADEON_CFG_ATI_REV_A13 (2 << 16) |
| # define RADEON_CFG_ATI_REV_ID_MASK (0xf << 16) |
| #define RADEON_CONFIG_MEMSIZE 0x00f8 |
| #define RADEON_CONFIG_MEMSIZE_EMBEDDED 0x0114 |
| #define RADEON_CONFIG_REG_1_BASE 0x010c |
| #define RADEON_CONFIG_REG_APER_SIZE 0x0110 |
| #define RADEON_CONFIG_XSTRAP 0x00e4 |
| #define RADEON_CONSTANT_COLOR_C 0x1d34 |
| # define RADEON_CONSTANT_COLOR_MASK 0x00ffffff |
| # define RADEON_CONSTANT_COLOR_ONE 0x00ffffff |
| # define RADEON_CONSTANT_COLOR_ZERO 0x00000000 |
| #define RADEON_CRC_CMDFIFO_ADDR 0x0740 |
| #define RADEON_CRC_CMDFIFO_DOUT 0x0744 |
| #define RADEON_GRPH_BUFFER_CNTL 0x02f0 |
| # define RADEON_GRPH_START_REQ_MASK (0x7f) |
| # define RADEON_GRPH_START_REQ_SHIFT 0 |
| # define RADEON_GRPH_STOP_REQ_MASK (0x7f<<8) |
| # define RADEON_GRPH_STOP_REQ_SHIFT 8 |
| # define RADEON_GRPH_CRITICAL_POINT_MASK (0x7f<<16) |
| # define RADEON_GRPH_CRITICAL_POINT_SHIFT 16 |
| # define RADEON_GRPH_CRITICAL_CNTL (1<<28) |
| # define RADEON_GRPH_BUFFER_SIZE (1<<29) |
| # define RADEON_GRPH_CRITICAL_AT_SOF (1<<30) |
| # define RADEON_GRPH_STOP_CNTL (1<<31) |
| #define RADEON_GRPH2_BUFFER_CNTL 0x03f0 |
| # define RADEON_GRPH2_START_REQ_MASK (0x7f) |
| # define RADEON_GRPH2_START_REQ_SHIFT 0 |
| # define RADEON_GRPH2_STOP_REQ_MASK (0x7f<<8) |
| # define RADEON_GRPH2_STOP_REQ_SHIFT 8 |
| # define RADEON_GRPH2_CRITICAL_POINT_MASK (0x7f<<16) |
| # define RADEON_GRPH2_CRITICAL_POINT_SHIFT 16 |
| # define RADEON_GRPH2_CRITICAL_CNTL (1<<28) |
| # define RADEON_GRPH2_BUFFER_SIZE (1<<29) |
| # define RADEON_GRPH2_CRITICAL_AT_SOF (1<<30) |
| # define RADEON_GRPH2_STOP_CNTL (1<<31) |
| #define RADEON_CRTC_CRNT_FRAME 0x0214 |
| #define RADEON_CRTC_EXT_CNTL 0x0054 |
| # define RADEON_CRTC_VGA_XOVERSCAN (1 << 0) |
| # define RADEON_VGA_ATI_LINEAR (1 << 3) |
| # define RADEON_XCRT_CNT_EN (1 << 6) |
| # define RADEON_CRTC_HSYNC_DIS (1 << 8) |
| # define RADEON_CRTC_VSYNC_DIS (1 << 9) |
| # define RADEON_CRTC_DISPLAY_DIS (1 << 10) |
| # define RADEON_CRTC_SYNC_TRISTAT (1 << 11) |
| # define RADEON_CRTC_CRT_ON (1 << 15) |
| #define RADEON_CRTC_EXT_CNTL_DPMS_BYTE 0x0055 |
| # define RADEON_CRTC_HSYNC_DIS_BYTE (1 << 0) |
| # define RADEON_CRTC_VSYNC_DIS_BYTE (1 << 1) |
| # define RADEON_CRTC_DISPLAY_DIS_BYTE (1 << 2) |
| #define RADEON_CRTC_GEN_CNTL 0x0050 |
| # define RADEON_CRTC_DBL_SCAN_EN (1 << 0) |
| # define RADEON_CRTC_INTERLACE_EN (1 << 1) |
| # define RADEON_CRTC_CSYNC_EN (1 << 4) |
| # define RADEON_CRTC_ICON_EN (1 << 15) |
| # define RADEON_CRTC_CUR_EN (1 << 16) |
| # define RADEON_CRTC_CUR_MODE_MASK (7 << 20) |
| # define RADEON_CRTC_CUR_MODE_SHIFT 20 |
| # define RADEON_CRTC_CUR_MODE_MONO 0 |
| # define RADEON_CRTC_CUR_MODE_24BPP 2 |
| # define RADEON_CRTC_EXT_DISP_EN (1 << 24) |
| # define RADEON_CRTC_EN (1 << 25) |
| # define RADEON_CRTC_DISP_REQ_EN_B (1 << 26) |
| #define RADEON_CRTC2_GEN_CNTL 0x03f8 |
| # define RADEON_CRTC2_DBL_SCAN_EN (1 << 0) |
| # define RADEON_CRTC2_INTERLACE_EN (1 << 1) |
| # define RADEON_CRTC2_SYNC_TRISTAT (1 << 4) |
| # define RADEON_CRTC2_HSYNC_TRISTAT (1 << 5) |
| # define RADEON_CRTC2_VSYNC_TRISTAT (1 << 6) |
| # define RADEON_CRTC2_CRT2_ON (1 << 7) |
| # define RADEON_CRTC2_PIX_WIDTH_SHIFT 8 |
| # define RADEON_CRTC2_PIX_WIDTH_MASK (0xf << 8) |
| # define RADEON_CRTC2_ICON_EN (1 << 15) |
| # define RADEON_CRTC2_CUR_EN (1 << 16) |
| # define RADEON_CRTC2_CUR_MODE_MASK (7 << 20) |
| # define RADEON_CRTC2_DISP_DIS (1 << 23) |
| # define RADEON_CRTC2_EN (1 << 25) |
| # define RADEON_CRTC2_DISP_REQ_EN_B (1 << 26) |
| # define RADEON_CRTC2_CSYNC_EN (1 << 27) |
| # define RADEON_CRTC2_HSYNC_DIS (1 << 28) |
| # define RADEON_CRTC2_VSYNC_DIS (1 << 29) |
| #define RADEON_CRTC_MORE_CNTL 0x27c |
| # define RADEON_CRTC_AUTO_HORZ_CENTER_EN (1<<2) |
| # define RADEON_CRTC_AUTO_VERT_CENTER_EN (1<<3) |
| # define RADEON_CRTC_H_CUTOFF_ACTIVE_EN (1<<4) |
| # define RADEON_CRTC_V_CUTOFF_ACTIVE_EN (1<<5) |
| #define RADEON_CRTC_GUI_TRIG_VLINE 0x0218 |
| #define RADEON_CRTC_H_SYNC_STRT_WID 0x0204 |
| # define RADEON_CRTC_H_SYNC_STRT_PIX (0x07 << 0) |
| # define RADEON_CRTC_H_SYNC_STRT_CHAR (0x3ff << 3) |
| # define RADEON_CRTC_H_SYNC_STRT_CHAR_SHIFT 3 |
| # define RADEON_CRTC_H_SYNC_WID (0x3f << 16) |
| # define RADEON_CRTC_H_SYNC_WID_SHIFT 16 |
| # define RADEON_CRTC_H_SYNC_POL (1 << 23) |
| #define RADEON_CRTC2_H_SYNC_STRT_WID 0x0304 |
| # define RADEON_CRTC2_H_SYNC_STRT_PIX (0x07 << 0) |
| # define RADEON_CRTC2_H_SYNC_STRT_CHAR (0x3ff << 3) |
| # define RADEON_CRTC2_H_SYNC_STRT_CHAR_SHIFT 3 |
| # define RADEON_CRTC2_H_SYNC_WID (0x3f << 16) |
| # define RADEON_CRTC2_H_SYNC_WID_SHIFT 16 |
| # define RADEON_CRTC2_H_SYNC_POL (1 << 23) |
| #define RADEON_CRTC_H_TOTAL_DISP 0x0200 |
| # define RADEON_CRTC_H_TOTAL (0x03ff << 0) |
| # define RADEON_CRTC_H_TOTAL_SHIFT 0 |
| # define RADEON_CRTC_H_DISP (0x01ff << 16) |
| # define RADEON_CRTC_H_DISP_SHIFT 16 |
| #define RADEON_CRTC2_H_TOTAL_DISP 0x0300 |
| # define RADEON_CRTC2_H_TOTAL (0x03ff << 0) |
| # define RADEON_CRTC2_H_TOTAL_SHIFT 0 |
| # define RADEON_CRTC2_H_DISP (0x01ff << 16) |
| # define RADEON_CRTC2_H_DISP_SHIFT 16 |
| #define RADEON_CRTC_OFFSET_RIGHT 0x0220 |
| #define RADEON_CRTC_OFFSET 0x0224 |
| # define RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET (1<<30) |
| # define RADEON_CRTC_OFFSET__OFFSET_LOCK (1<<31) |
| #define RADEON_CRTC2_OFFSET 0x0324 |
| # define RADEON_CRTC2_OFFSET__GUI_TRIG_OFFSET (1<<30) |
| # define RADEON_CRTC2_OFFSET__OFFSET_LOCK (1<<31) |
| #define RADEON_CRTC_OFFSET_CNTL 0x0228 |
| # define RADEON_CRTC_TILE_LINE_SHIFT 0 |
| # define RADEON_CRTC_TILE_LINE_RIGHT_SHIFT 4 |
| # define R300_CRTC_X_Y_MODE_EN_RIGHT (1 << 6) |
| # define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_MASK (3 << 7) |
| # define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_AUTO (0 << 7) |
| # define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_SINGLE (1 << 7) |
| # define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DOUBLE (2 << 7) |
| # define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DIS (3 << 7) |
| # define R300_CRTC_X_Y_MODE_EN (1 << 9) |
| # define R300_CRTC_MICRO_TILE_BUFFER_MASK (3 << 10) |
| # define R300_CRTC_MICRO_TILE_BUFFER_AUTO (0 << 10) |
| # define R300_CRTC_MICRO_TILE_BUFFER_SINGLE (1 << 10) |
| # define R300_CRTC_MICRO_TILE_BUFFER_DOUBLE (2 << 10) |
| # define R300_CRTC_MICRO_TILE_BUFFER_DIS (3 << 10) |
| # define R300_CRTC_MICRO_TILE_EN_RIGHT (1 << 12) |
| # define R300_CRTC_MICRO_TILE_EN (1 << 13) |
| # define R300_CRTC_MACRO_TILE_EN_RIGHT (1 << 14) |
| # define R300_CRTC_MACRO_TILE_EN (1 << 15) |
| # define RADEON_CRTC_TILE_EN_RIGHT (1 << 14) |
| # define RADEON_CRTC_TILE_EN (1 << 15) |
| # define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16) |
| # define RADEON_CRTC_STEREO_OFFSET_EN (1 << 17) |
| #define R300_CRTC_TILE_X0_Y0 0x0350 |
| #define R300_CRTC2_TILE_X0_Y0 0x0358 |
| #define RADEON_CRTC2_OFFSET_CNTL 0x0328 |
| # define RADEON_CRTC2_OFFSET_FLIP_CNTL (1 << 16) |
| # define RADEON_CRTC2_TILE_EN (1 << 15) |
| #define RADEON_CRTC_PITCH 0x022c |
| # define RADEON_CRTC_PITCH__SHIFT 0 |
| # define RADEON_CRTC_PITCH__RIGHT_SHIFT 16 |
| #define RADEON_CRTC2_PITCH 0x032c |
| #define RADEON_CRTC_STATUS 0x005c |
| # define RADEON_CRTC_VBLANK_SAVE (1 << 1) |
| # define RADEON_CRTC_VBLANK_SAVE_CLEAR (1 << 1) |
| #define RADEON_CRTC2_STATUS 0x03fc |
| # define RADEON_CRTC2_VBLANK_SAVE (1 << 1) |
| # define RADEON_CRTC2_VBLANK_SAVE_CLEAR (1 << 1) |
| #define RADEON_CRTC_V_SYNC_STRT_WID 0x020c |
| # define RADEON_CRTC_V_SYNC_STRT (0x7ff << 0) |
| # define RADEON_CRTC_V_SYNC_STRT_SHIFT 0 |
| # define RADEON_CRTC_V_SYNC_WID (0x1f << 16) |
| # define RADEON_CRTC_V_SYNC_WID_SHIFT 16 |
| # define RADEON_CRTC_V_SYNC_POL (1 << 23) |
| #define RADEON_CRTC2_V_SYNC_STRT_WID 0x030c |
| # define RADEON_CRTC2_V_SYNC_STRT (0x7ff << 0) |
| # define RADEON_CRTC2_V_SYNC_STRT_SHIFT 0 |
| # define RADEON_CRTC2_V_SYNC_WID (0x1f << 16) |
| # define RADEON_CRTC2_V_SYNC_WID_SHIFT 16 |
| # define RADEON_CRTC2_V_SYNC_POL (1 << 23) |
| #define RADEON_CRTC_V_TOTAL_DISP 0x0208 |
| # define RADEON_CRTC_V_TOTAL (0x07ff << 0) |
| # define RADEON_CRTC_V_TOTAL_SHIFT 0 |
| # define RADEON_CRTC_V_DISP (0x07ff << 16) |
| # define RADEON_CRTC_V_DISP_SHIFT 16 |
| #define RADEON_CRTC2_V_TOTAL_DISP 0x0308 |
| # define RADEON_CRTC2_V_TOTAL (0x07ff << 0) |
| # define RADEON_CRTC2_V_TOTAL_SHIFT 0 |
| # define RADEON_CRTC2_V_DISP (0x07ff << 16) |
| # define RADEON_CRTC2_V_DISP_SHIFT 16 |
| #define RADEON_CRTC_VLINE_CRNT_VLINE 0x0210 |
| # define RADEON_CRTC_CRNT_VLINE_MASK (0x7ff << 16) |
| #define RADEON_CRTC2_CRNT_FRAME 0x0314 |
| #define RADEON_CRTC2_GUI_TRIG_VLINE 0x0318 |
| #define RADEON_CRTC2_STATUS 0x03fc |
| #define RADEON_CRTC2_VLINE_CRNT_VLINE 0x0310 |
| #define RADEON_CRTC8_DATA 0x03d5 /* VGA, 0x3b5 */ |
| #define RADEON_CRTC8_IDX 0x03d4 /* VGA, 0x3b4 */ |
| #define RADEON_CUR_CLR0 0x026c |
| #define RADEON_CUR_CLR1 0x0270 |
| #define RADEON_CUR_HORZ_VERT_OFF 0x0268 |
| #define RADEON_CUR_HORZ_VERT_POSN 0x0264 |
| #define RADEON_CUR_OFFSET 0x0260 |
| # define RADEON_CUR_LOCK (1 << 31) |
| #define RADEON_CUR2_CLR0 0x036c |
| #define RADEON_CUR2_CLR1 0x0370 |
| #define RADEON_CUR2_HORZ_VERT_OFF 0x0368 |
| #define RADEON_CUR2_HORZ_VERT_POSN 0x0364 |
| #define RADEON_CUR2_OFFSET 0x0360 |
| # define RADEON_CUR2_LOCK (1 << 31) |
| #define RADEON_DAC_CNTL 0x0058 |
| # define RADEON_DAC_RANGE_CNTL (3 << 0) |
| # define RADEON_DAC_RANGE_CNTL_PS2 (2 << 0) |
| # define RADEON_DAC_RANGE_CNTL_MASK 0x03 |
| # define RADEON_DAC_BLANKING (1 << 2) |
| # define RADEON_DAC_CMP_EN (1 << 3) |
| # define RADEON_DAC_CMP_OUTPUT (1 << 7) |
| # define RADEON_DAC_8BIT_EN (1 << 8) |
| # define RADEON_DAC_TVO_EN (1 << 10) |
| # define RADEON_DAC_VGA_ADR_EN (1 << 13) |
| # define RADEON_DAC_PDWN (1 << 15) |
| # define RADEON_DAC_MASK_ALL (0xff << 24) |
| #define RADEON_DAC_CNTL2 0x007c |
| # define RADEON_DAC2_TV_CLK_SEL (0 << 1) |
| # define RADEON_DAC2_DAC_CLK_SEL (1 << 0) |
| # define RADEON_DAC2_DAC2_CLK_SEL (1 << 1) |
| # define RADEON_DAC2_PALETTE_ACC_CTL (1 << 5) |
| # define RADEON_DAC2_CMP_EN (1 << 7) |
| # define RADEON_DAC2_CMP_OUT_R (1 << 8) |
| # define RADEON_DAC2_CMP_OUT_G (1 << 9) |
| # define RADEON_DAC2_CMP_OUT_B (1 << 10) |
| # define RADEON_DAC2_CMP_OUTPUT (1 << 11) |
| #define RADEON_DAC_EXT_CNTL 0x0280 |
| # define RADEON_DAC2_FORCE_BLANK_OFF_EN (1 << 0) |
| # define RADEON_DAC2_FORCE_DATA_EN (1 << 1) |
| # define RADEON_DAC_FORCE_BLANK_OFF_EN (1 << 4) |
| # define RADEON_DAC_FORCE_DATA_EN (1 << 5) |
| # define RADEON_DAC_FORCE_DATA_SEL_MASK (3 << 6) |
| # define RADEON_DAC_FORCE_DATA_SEL_R (0 << 6) |
| # define RADEON_DAC_FORCE_DATA_SEL_G (1 << 6) |
| # define RADEON_DAC_FORCE_DATA_SEL_B (2 << 6) |
| # define RADEON_DAC_FORCE_DATA_SEL_RGB (3 << 6) |
| # define RADEON_DAC_FORCE_DATA_MASK 0x0003ff00 |
| # define RADEON_DAC_FORCE_DATA_SHIFT 8 |
| #define RADEON_DAC_MACRO_CNTL 0x0d04 |
| # define RADEON_DAC_PDWN_R (1 << 16) |
| # define RADEON_DAC_PDWN_G (1 << 17) |
| # define RADEON_DAC_PDWN_B (1 << 18) |
| #define RADEON_DISP_PWR_MAN 0x0d08 |
| # define RADEON_DISP_PWR_MAN_D3_CRTC_EN (1 << 0) |
| # define RADEON_DISP_PWR_MAN_D3_CRTC2_EN (1 << 4) |
| # define RADEON_DISP_PWR_MAN_DPMS_ON (0 << 8) |
| # define RADEON_DISP_PWR_MAN_DPMS_STANDBY (1 << 8) |
| # define RADEON_DISP_PWR_MAN_DPMS_SUSPEND (2 << 8) |
| # define RADEON_DISP_PWR_MAN_DPMS_OFF (3 << 8) |
| # define RADEON_DISP_D3_RST (1 << 16) |
| # define RADEON_DISP_D3_REG_RST (1 << 17) |
| # define RADEON_DISP_D3_GRPH_RST (1 << 18) |
| # define RADEON_DISP_D3_SUBPIC_RST (1 << 19) |
| # define RADEON_DISP_D3_OV0_RST (1 << 20) |
| # define RADEON_DISP_D1D2_GRPH_RST (1 << 21) |
| # define RADEON_DISP_D1D2_SUBPIC_RST (1 << 22) |
| # define RADEON_DISP_D1D2_OV0_RST (1 << 23) |
| # define RADEON_DIG_TMDS_ENABLE_RST (1 << 24) |
| # define RADEON_TV_ENABLE_RST (1 << 25) |
| # define RADEON_AUTO_PWRUP_EN (1 << 26) |
| #define RADEON_TV_DAC_CNTL 0x088c |
| # define RADEON_TV_DAC_NBLANK (1 << 0) |
| # define RADEON_TV_DAC_NHOLD (1 << 1) |
| # define RADEON_TV_DAC_PEDESTAL (1 << 2) |
| # define RADEON_TV_MONITOR_DETECT_EN (1 << 4) |
| # define RADEON_TV_DAC_CMPOUT (1 << 5) |
| # define RADEON_TV_DAC_STD_MASK (3 << 8) |
| # define RADEON_TV_DAC_STD_PAL (0 << 8) |
| # define RADEON_TV_DAC_STD_NTSC (1 << 8) |
| # define RADEON_TV_DAC_STD_PS2 (2 << 8) |
| # define RADEON_TV_DAC_STD_RS343 (3 << 8) |
| # define RADEON_TV_DAC_BGSLEEP (1 << 6) |
| # define RADEON_TV_DAC_BGADJ_MASK (0xf << 16) |
| # define RADEON_TV_DAC_BGADJ_SHIFT 16 |
| # define RADEON_TV_DAC_DACADJ_MASK (0xf << 20) |
| # define RADEON_TV_DAC_DACADJ_SHIFT 20 |
| # define RADEON_TV_DAC_RDACPD (1 << 24) |
| # define RADEON_TV_DAC_GDACPD (1 << 25) |
| # define RADEON_TV_DAC_BDACPD (1 << 26) |
| # define RADEON_TV_DAC_RDACDET (1 << 29) |
| # define RADEON_TV_DAC_GDACDET (1 << 30) |
| # define RADEON_TV_DAC_BDACDET (1 << 31) |
| # define R420_TV_DAC_DACADJ_MASK (0x1f << 20) |
| # define R420_TV_DAC_RDACPD (1 << 25) |
| # define R420_TV_DAC_GDACPD (1 << 26) |
| # define R420_TV_DAC_BDACPD (1 << 27) |
| # define R420_TV_DAC_TVENABLE (1 << 28) |
| #define RADEON_DISP_HW_DEBUG 0x0d14 |
| # define RADEON_CRT2_DISP1_SEL (1 << 5) |
| #define RADEON_DISP_OUTPUT_CNTL 0x0d64 |
| # define RADEON_DISP_DAC_SOURCE_MASK 0x03 |
| # define RADEON_DISP_DAC2_SOURCE_MASK 0x0c |
| # define RADEON_DISP_DAC_SOURCE_CRTC2 0x01 |
| # define RADEON_DISP_DAC_SOURCE_RMX 0x02 |
| # define RADEON_DISP_DAC_SOURCE_LTU 0x03 |
| # define RADEON_DISP_DAC2_SOURCE_CRTC2 0x04 |
| # define RADEON_DISP_TVDAC_SOURCE_MASK (0x03 << 2) |
| # define RADEON_DISP_TVDAC_SOURCE_CRTC 0x0 |
| # define RADEON_DISP_TVDAC_SOURCE_CRTC2 (0x01 << 2) |
| # define RADEON_DISP_TVDAC_SOURCE_RMX (0x02 << 2) |
| # define RADEON_DISP_TVDAC_SOURCE_LTU (0x03 << 2) |
| # define RADEON_DISP_TRANS_MATRIX_MASK (0x03 << 4) |
| # define RADEON_DISP_TRANS_MATRIX_ALPHA_MSB (0x00 << 4) |
| # define RADEON_DISP_TRANS_MATRIX_GRAPHICS (0x01 << 4) |
| # define RADEON_DISP_TRANS_MATRIX_VIDEO (0x02 << 4) |
| # define RADEON_DISP_TV_SOURCE_CRTC (1 << 16) /* crtc1 or crtc2 */ |
| # define RADEON_DISP_TV_SOURCE_LTU (0 << 16) /* linear transform unit */ |
| #define RADEON_DISP_TV_OUT_CNTL 0x0d6c |
| # define RADEON_DISP_TV_PATH_SRC_CRTC2 (1 << 16) |
| # define RADEON_DISP_TV_PATH_SRC_CRTC1 (0 << 16) |
| #define RADEON_DAC_CRC_SIG 0x02cc |
| #define RADEON_DAC_DATA 0x03c9 /* VGA */ |
| #define RADEON_DAC_MASK 0x03c6 /* VGA */ |
| #define RADEON_DAC_R_INDEX 0x03c7 /* VGA */ |
| #define RADEON_DAC_W_INDEX 0x03c8 /* VGA */ |
| #define RADEON_DDA_CONFIG 0x02e0 |
| #define RADEON_DDA_ON_OFF 0x02e4 |
| #define RADEON_DEFAULT_OFFSET 0x16e0 |
| #define RADEON_DEFAULT_PITCH 0x16e4 |
| #define RADEON_DEFAULT_SC_BOTTOM_RIGHT 0x16e8 |
| # define RADEON_DEFAULT_SC_RIGHT_MAX (0x1fff << 0) |
| # define RADEON_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16) |
| #define RADEON_DESTINATION_3D_CLR_CMP_VAL 0x1820 |
| #define RADEON_DESTINATION_3D_CLR_CMP_MSK 0x1824 |
| #define RADEON_DEVICE_ID 0x0f02 /* PCI */ |
| #define RADEON_DISP_MISC_CNTL 0x0d00 |
| # define RADEON_SOFT_RESET_GRPH_PP (1 << 0) |
| #define RADEON_DISP_MERGE_CNTL 0x0d60 |
| # define RADEON_DISP_ALPHA_MODE_MASK 0x03 |
| # define RADEON_DISP_ALPHA_MODE_KEY 0 |
| # define RADEON_DISP_ALPHA_MODE_PER_PIXEL 1 |
| # define RADEON_DISP_ALPHA_MODE_GLOBAL 2 |
| # define RADEON_DISP_RGB_OFFSET_EN (1 << 8) |
| # define RADEON_DISP_GRPH_ALPHA_MASK (0xff << 16) |
| # define RADEON_DISP_OV0_ALPHA_MASK (0xff << 24) |
| # define RADEON_DISP_LIN_TRANS_BYPASS (0x01 << 9) |
| #define RADEON_DISP2_MERGE_CNTL 0x0d68 |
| # define RADEON_DISP2_RGB_OFFSET_EN (1 << 8) |
| #define RADEON_DISP_LIN_TRANS_GRPH_A 0x0d80 |
| #define RADEON_DISP_LIN_TRANS_GRPH_B 0x0d84 |
| #define RADEON_DISP_LIN_TRANS_GRPH_C 0x0d88 |
| #define RADEON_DISP_LIN_TRANS_GRPH_D 0x0d8c |
| #define RADEON_DISP_LIN_TRANS_GRPH_E 0x0d90 |
| #define RADEON_DISP_LIN_TRANS_GRPH_F 0x0d98 |
| #define RADEON_DP_BRUSH_BKGD_CLR 0x1478 |
| #define RADEON_DP_BRUSH_FRGD_CLR 0x147c |
| #define RADEON_DP_CNTL 0x16c0 |
| # define RADEON_DST_X_LEFT_TO_RIGHT (1 << 0) |
| # define RADEON_DST_Y_TOP_TO_BOTTOM (1 << 1) |
| # define RADEON_DP_DST_TILE_LINEAR (0 << 3) |
| # define RADEON_DP_DST_TILE_MACRO (1 << 3) |
| # define RADEON_DP_DST_TILE_MICRO (2 << 3) |
| # define RADEON_DP_DST_TILE_BOTH (3 << 3) |
| #define RADEON_DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0 |
| # define RADEON_DST_Y_MAJOR (1 << 2) |
| # define RADEON_DST_Y_DIR_TOP_TO_BOTTOM (1 << 15) |
| # define RADEON_DST_X_DIR_LEFT_TO_RIGHT (1 << 31) |
| #define RADEON_DP_DATATYPE 0x16c4 |
| # define RADEON_HOST_BIG_ENDIAN_EN (1 << 29) |
| #define RADEON_DP_GUI_MASTER_CNTL 0x146c |
| # define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) |
| # define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) |
| # define RADEON_GMC_SRC_CLIPPING (1 << 2) |
| # define RADEON_GMC_DST_CLIPPING (1 << 3) |
| # define RADEON_GMC_BRUSH_DATATYPE_MASK (0x0f << 4) |
| # define RADEON_GMC_BRUSH_8X8_MONO_FG_BG (0 << 4) |
| # define RADEON_GMC_BRUSH_8X8_MONO_FG_LA (1 << 4) |
| # define RADEON_GMC_BRUSH_1X8_MONO_FG_BG (4 << 4) |
| # define RADEON_GMC_BRUSH_1X8_MONO_FG_LA (5 << 4) |
| # define RADEON_GMC_BRUSH_32x1_MONO_FG_BG (6 << 4) |
| # define RADEON_GMC_BRUSH_32x1_MONO_FG_LA (7 << 4) |
| # define RADEON_GMC_BRUSH_32x32_MONO_FG_BG (8 << 4) |
| # define RADEON_GMC_BRUSH_32x32_MONO_FG_LA (9 << 4) |
| # define RADEON_GMC_BRUSH_8x8_COLOR (10 << 4) |
| # define RADEON_GMC_BRUSH_1X8_COLOR (12 << 4) |
| # define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4) |
| # define RADEON_GMC_BRUSH_NONE (15 << 4) |
| # define RADEON_GMC_DST_8BPP_CI (2 << 8) |
| # define RADEON_GMC_DST_15BPP (3 << 8) |
| # define RADEON_GMC_DST_16BPP (4 << 8) |
| # define RADEON_GMC_DST_24BPP (5 << 8) |
| # define RADEON_GMC_DST_32BPP (6 << 8) |
| # define RADEON_GMC_DST_8BPP_RGB (7 << 8) |
| # define RADEON_GMC_DST_Y8 (8 << 8) |
| # define RADEON_GMC_DST_RGB8 (9 << 8) |
| # define RADEON_GMC_DST_VYUY (11 << 8) |
| # define RADEON_GMC_DST_YVYU (12 << 8) |
| # define RADEON_GMC_DST_AYUV444 (14 << 8) |
| # define RADEON_GMC_DST_ARGB4444 (15 << 8) |
| # define RADEON_GMC_DST_DATATYPE_MASK (0x0f << 8) |
| # define RADEON_GMC_DST_DATATYPE_SHIFT 8 |
| # define RADEON_GMC_SRC_DATATYPE_MASK (3 << 12) |
| # define RADEON_GMC_SRC_DATATYPE_MONO_FG_BG (0 << 12) |
| # define RADEON_GMC_SRC_DATATYPE_MONO_FG_LA (1 << 12) |
| # define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12) |
| # define RADEON_GMC_BYTE_PIX_ORDER (1 << 14) |
| # define RADEON_GMC_BYTE_MSB_TO_LSB (0 << 14) |
| # define RADEON_GMC_BYTE_LSB_TO_MSB (1 << 14) |
| # define RADEON_GMC_CONVERSION_TEMP (1 << 15) |
| # define RADEON_GMC_CONVERSION_TEMP_6500 (0 << 15) |
| # define RADEON_GMC_CONVERSION_TEMP_9300 (1 << 15) |
| # define RADEON_GMC_ROP3_MASK (0xff << 16) |
| # define RADEON_DP_SRC_SOURCE_MASK (7 << 24) |
| # define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24) |
| # define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24) |
| # define RADEON_GMC_3D_FCN_EN (1 << 27) |
| # define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28) |
| # define RADEON_GMC_AUX_CLIP_DIS (1 << 29) |
| # define RADEON_GMC_WR_MSK_DIS (1 << 30) |
| # define RADEON_GMC_LD_BRUSH_Y_X (1 << 31) |
| # define RADEON_ROP3_ZERO 0x00000000 |
| # define RADEON_ROP3_DSa 0x00880000 |
| # define RADEON_ROP3_SDna 0x00440000 |
| # define RADEON_ROP3_S 0x00cc0000 |
| # define RADEON_ROP3_DSna 0x00220000 |
| # define RADEON_ROP3_D 0x00aa0000 |
| # define RADEON_ROP3_DSx 0x00660000 |
| # define RADEON_ROP3_DSo 0x00ee0000 |
| # define RADEON_ROP3_DSon 0x00110000 |
| # define RADEON_ROP3_DSxn 0x00990000 |
| # define RADEON_ROP3_Dn 0x00550000 |
| # define RADEON_ROP3_SDno 0x00dd0000 |
| # define RADEON_ROP3_Sn 0x00330000 |
| # define RADEON_ROP3_DSno 0x00bb0000 |
| # define RADEON_ROP3_DSan 0x00770000 |
| # define RADEON_ROP3_ONE 0x00ff0000 |
| # define RADEON_ROP3_DPa 0x00a00000 |
| # define RADEON_ROP3_PDna 0x00500000 |
| # define RADEON_ROP3_P 0x00f00000 |
| # define RADEON_ROP3_DPna 0x000a0000 |
| # define RADEON_ROP3_D 0x00aa0000 |
| # define RADEON_ROP3_DPx 0x005a0000 |
| # define RADEON_ROP3_DPo 0x00fa0000 |
| # define RADEON_ROP3_DPon 0x00050000 |
| # define RADEON_ROP3_PDxn 0x00a50000 |
| # define RADEON_ROP3_PDno 0x00f50000 |
| # define RADEON_ROP3_Pn 0x000f0000 |
| # define RADEON_ROP3_DPno 0x00af0000 |
| # define RADEON_ROP3_DPan 0x005f0000 |
| #define RADEON_DP_GUI_MASTER_CNTL_C 0x1c84 |
| #define RADEON_DP_MIX 0x16c8 |
| #define RADEON_DP_SRC_BKGD_CLR 0x15dc |
| #define RADEON_DP_SRC_FRGD_CLR 0x15d8 |
| #define RADEON_DP_WRITE_MASK 0x16cc |
| #define RADEON_DST_BRES_DEC 0x1630 |
| #define RADEON_DST_BRES_ERR 0x1628 |
| #define RADEON_DST_BRES_INC 0x162c |
| #define RADEON_DST_BRES_LNTH 0x1634 |
| #define RADEON_DST_BRES_LNTH_SUB 0x1638 |
| #define RADEON_DST_HEIGHT 0x1410 |
| #define RADEON_DST_HEIGHT_WIDTH 0x143c |
| #define RADEON_DST_HEIGHT_WIDTH_8 0x158c |
| #define RADEON_DST_HEIGHT_WIDTH_BW 0x15b4 |
| #define RADEON_DST_HEIGHT_Y 0x15a0 |
| #define RADEON_DST_LINE_START 0x1600 |
| #define RADEON_DST_LINE_END 0x1604 |
| #define RADEON_DST_LINE_PATCOUNT 0x1608 |
| # define RADEON_BRES_CNTL_SHIFT 8 |
| #define RADEON_DST_OFFSET 0x1404 |
| #define RADEON_DST_PITCH 0x1408 |
| #define RADEON_DST_PITCH_OFFSET 0x142c |
| #define RADEON_DST_PITCH_OFFSET_C 0x1c80 |
| # define RADEON_PITCH_SHIFT 21 |
| # define RADEON_DST_TILE_LINEAR (0 << 30) |
| # define RADEON_DST_TILE_MACRO (1 << 30) |
| # define RADEON_DST_TILE_MICRO (2 << 30) |
| # define RADEON_DST_TILE_BOTH (3 << 30) |
| #define RADEON_DST_WIDTH 0x140c |
| #define RADEON_DST_WIDTH_HEIGHT 0x1598 |
| #define RADEON_DST_WIDTH_X 0x1588 |
| #define RADEON_DST_WIDTH_X_INCY 0x159c |
| #define RADEON_DST_X 0x141c |
| #define RADEON_DST_X_SUB 0x15a4 |
| #define RADEON_DST_X_Y 0x1594 |
| #define RADEON_DST_Y 0x1420 |
| #define RADEON_DST_Y_SUB 0x15a8 |
| #define RADEON_DST_Y_X 0x1438 |
| #define RADEON_FCP_CNTL 0x0910 |
| # define RADEON_FCP0_SRC_PCICLK 0 |
| # define RADEON_FCP0_SRC_PCLK 1 |
| # define RADEON_FCP0_SRC_PCLKb 2 |
| # define RADEON_FCP0_SRC_HREF 3 |
| # define RADEON_FCP0_SRC_GND 4 |
| # define RADEON_FCP0_SRC_HREFb 5 |
| #define RADEON_FLUSH_1 0x1704 |
| #define RADEON_FLUSH_2 0x1708 |
| #define RADEON_FLUSH_3 0x170c |
| #define RADEON_FLUSH_4 0x1710 |
| #define RADEON_FLUSH_5 0x1714 |
| #define RADEON_FLUSH_6 0x1718 |
| #define RADEON_FLUSH_7 0x171c |
| #define RADEON_FOG_3D_TABLE_START 0x1810 |
| #define RADEON_FOG_3D_TABLE_END 0x1814 |
| #define RADEON_FOG_3D_TABLE_DENSITY 0x181c |
| #define RADEON_FOG_TABLE_INDEX 0x1a14 |
| #define RADEON_FOG_TABLE_DATA 0x1a18 |
| #define RADEON_FP_CRTC_H_TOTAL_DISP 0x0250 |
| #define RADEON_FP_CRTC_V_TOTAL_DISP 0x0254 |
| # define RADEON_FP_CRTC_H_TOTAL_MASK 0x000003ff |
| # define RADEON_FP_CRTC_H_DISP_MASK 0x01ff0000 |
| # define RADEON_FP_CRTC_V_TOTAL_MASK 0x00000fff |
| # define RADEON_FP_CRTC_V_DISP_MASK 0x0fff0000 |
| # define RADEON_FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8 |
| # define RADEON_FP_H_SYNC_WID_MASK 0x003f0000 |
| # define RADEON_FP_V_SYNC_STRT_MASK 0x00000fff |
| # define RADEON_FP_V_SYNC_WID_MASK 0x001f0000 |
| # define RADEON_FP_CRTC_H_TOTAL_SHIFT 0x00000000 |
| # define RADEON_FP_CRTC_H_DISP_SHIFT 0x00000010 |
| # define RADEON_FP_CRTC_V_TOTAL_SHIFT 0x00000000 |
| # define RADEON_FP_CRTC_V_DISP_SHIFT 0x00000010 |
| # define RADEON_FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003 |
| # define RADEON_FP_H_SYNC_WID_SHIFT 0x00000010 |
| # define RADEON_FP_V_SYNC_STRT_SHIFT 0x00000000 |
| # define RADEON_FP_V_SYNC_WID_SHIFT 0x00000010 |
| #define RADEON_FP_GEN_CNTL 0x0284 |
| # define RADEON_FP_FPON (1 << 0) |
| # define RADEON_FP_BLANK_EN (1 << 1) |
| # define RADEON_FP_TMDS_EN (1 << 2) |
| # define RADEON_FP_PANEL_FORMAT (1 << 3) |
| # define RADEON_FP_EN_TMDS (1 << 7) |
| # define RADEON_FP_DETECT_SENSE (1 << 8) |
| # define R200_FP_SOURCE_SEL_MASK (3 << 10) |
| # define R200_FP_SOURCE_SEL_CRTC1 (0 << 10) |
| # define R200_FP_SOURCE_SEL_CRTC2 (1 << 10) |
| # define R200_FP_SOURCE_SEL_RMX (2 << 10) |
| # define R200_FP_SOURCE_SEL_TRANS (3 << 10) |
| # define RADEON_FP_SEL_CRTC1 (0 << 13) |
| # define RADEON_FP_SEL_CRTC2 (1 << 13) |
| # define RADEON_FP_CRTC_DONT_SHADOW_HPAR (1 << 15) |
| # define RADEON_FP_CRTC_DONT_SHADOW_VPAR (1 << 16) |
| # define RADEON_FP_CRTC_DONT_SHADOW_HEND (1 << 17) |
| # define RADEON_FP_CRTC_USE_SHADOW_VEND (1 << 18) |
| # define RADEON_FP_RMX_HVSYNC_CONTROL_EN (1 << 20) |
| # define RADEON_FP_DFP_SYNC_SEL (1 << 21) |
| # define RADEON_FP_CRTC_LOCK_8DOT (1 << 22) |
| # define RADEON_FP_CRT_SYNC_SEL (1 << 23) |
| # define RADEON_FP_USE_SHADOW_EN (1 << 24) |
| # define RADEON_FP_CRT_SYNC_ALT (1 << 26) |
| #define RADEON_FP2_GEN_CNTL 0x0288 |
| # define RADEON_FP2_BLANK_EN (1 << 1) |
| # define RADEON_FP2_ON (1 << 2) |
| # define RADEON_FP2_PANEL_FORMAT (1 << 3) |
| # define RADEON_FP2_DETECT_SENSE (1 << 8) |
| # define R200_FP2_SOURCE_SEL_MASK (3 << 10) |
| # define R200_FP2_SOURCE_SEL_CRTC1 (0 << 10) |
| # define R200_FP2_SOURCE_SEL_CRTC2 (1 << 10) |
| # define R200_FP2_SOURCE_SEL_RMX (2 << 10) |
| # define R200_FP2_SOURCE_SEL_TRANS_UNIT (3 << 10) |
| # define RADEON_FP2_SRC_SEL_MASK (3 << 13) |
| # define RADEON_FP2_SRC_SEL_CRTC2 (1 << 13) |
| # define RADEON_FP2_FP_POL (1 << 16) |
| # define RADEON_FP2_LP_POL (1 << 17) |
| # define RADEON_FP2_SCK_POL (1 << 18) |
| # define RADEON_FP2_LCD_CNTL_MASK (7 << 19) |
| # define RADEON_FP2_PAD_FLOP_EN (1 << 22) |
| # define RADEON_FP2_CRC_EN (1 << 23) |
| # define RADEON_FP2_CRC_READ_EN (1 << 24) |
| # define RADEON_FP2_DVO_EN (1 << 25) |
| # define RADEON_FP2_DVO_RATE_SEL_SDR (1 << 26) |
| # define R200_FP2_DVO_RATE_SEL_SDR (1 << 27) |
| # define R300_FP2_DVO_CLOCK_MODE_SINGLE (1 << 28) |
| # define R300_FP2_DVO_DUAL_CHANNEL_EN (1 << 29) |
| #define RADEON_FP_H_SYNC_STRT_WID 0x02c4 |
| #define RADEON_FP_H2_SYNC_STRT_WID 0x03c4 |
| #define RADEON_FP_HORZ_STRETCH 0x028c |
| #define RADEON_FP_HORZ2_STRETCH 0x038c |
| # define RADEON_HORZ_STRETCH_RATIO_MASK 0xffff |
| # define RADEON_HORZ_STRETCH_RATIO_MAX 4096 |
| # define RADEON_HORZ_PANEL_SIZE (0x1ff << 16) |
| # define RADEON_HORZ_PANEL_SHIFT 16 |
| # define RADEON_HORZ_STRETCH_PIXREP (0 << 25) |
| # define RADEON_HORZ_STRETCH_BLEND (1 << 26) |
| # define RADEON_HORZ_STRETCH_ENABLE (1 << 25) |
| # define RADEON_HORZ_AUTO_RATIO (1 << 27) |
| # define RADEON_HORZ_FP_LOOP_STRETCH (0x7 << 28) |
| # define RADEON_HORZ_AUTO_RATIO_INC (1 << 31) |
| #define RADEON_FP_HORZ_VERT_ACTIVE 0x0278 |
| #define RADEON_FP_V_SYNC_STRT_WID 0x02c8 |
| #define RADEON_FP_VERT_STRETCH 0x0290 |
| #define RADEON_FP_V2_SYNC_STRT_WID 0x03c8 |
| #define RADEON_FP_VERT2_STRETCH 0x0390 |
| # define RADEON_VERT_PANEL_SIZE (0xfff << 12) |
| # define RADEON_VERT_PANEL_SHIFT 12 |
| # define RADEON_VERT_STRETCH_RATIO_MASK 0xfff |
| # define RADEON_VERT_STRETCH_RATIO_SHIFT 0 |
| # define RADEON_VERT_STRETCH_RATIO_MAX 4096 |
| # define RADEON_VERT_STRETCH_ENABLE (1 << 25) |
| # define RADEON_VERT_STRETCH_LINEREP (0 << 26) |
| # define RADEON_VERT_STRETCH_BLEND (1 << 26) |
| # define RADEON_VERT_AUTO_RATIO_EN (1 << 27) |
| # define RADEON_VERT_AUTO_RATIO_INC (1 << 31) |
| # define RADEON_VERT_STRETCH_RESERVED 0x71000000 |
| #define RS400_FP_2ND_GEN_CNTL 0x0384 |
| # define RS400_FP_2ND_ON (1 << 0) |
| # define RS400_FP_2ND_BLANK_EN (1 << 1) |
| # define RS400_TMDS_2ND_EN (1 << 2) |
| # define RS400_PANEL_FORMAT_2ND (1 << 3) |
| # define RS400_FP_2ND_EN_TMDS (1 << 7) |
| # define RS400_FP_2ND_DETECT_SENSE (1 << 8) |
| # define RS400_FP_2ND_SOURCE_SEL_MASK (3 << 10) |
| # define RS400_FP_2ND_SOURCE_SEL_CRTC1 (0 << 10) |
| # define RS400_FP_2ND_SOURCE_SEL_CRTC2 (1 << 10) |
| # define RS400_FP_2ND_SOURCE_SEL_RMX (2 << 10) |
| # define RS400_FP_2ND_DETECT_EN (1 << 12) |
| # define RS400_HPD_2ND_SEL (1 << 13) |
| #define RS400_FP2_2_GEN_CNTL 0x0388 |
| # define RS400_FP2_2_BLANK_EN (1 << 1) |
| # define RS400_FP2_2_ON (1 << 2) |
| # define RS400_FP2_2_PANEL_FORMAT (1 << 3) |
| # define RS400_FP2_2_DETECT_SENSE (1 << 8) |
| # define RS400_FP2_2_SOURCE_SEL_MASK (3 << 10) |
| # define RS400_FP2_2_SOURCE_SEL_CRTC1 (0 << 10) |
| # define RS400_FP2_2_SOURCE_SEL_CRTC2 (1 << 10) |
| # define RS400_FP2_2_SOURCE_SEL_RMX (2 << 10) |
| # define RS400_FP2_2_DVO2_EN (1 << 25) |
| #define RS400_TMDS2_CNTL 0x0394 |
| #define RS400_TMDS2_TRANSMITTER_CNTL 0x03a4 |
| # define RS400_TMDS2_PLLEN (1 << 0) |
| # define RS400_TMDS2_PLLRST (1 << 1) |
| #define RADEON_GEN_INT_CNTL 0x0040 |
| # define RADEON_SW_INT_ENABLE (1 << 25) |
| #define RADEON_GEN_INT_STATUS 0x0044 |
| # define RADEON_VSYNC_INT_AK (1 << 2) |
| # define RADEON_VSYNC_INT (1 << 2) |
| # define RADEON_VSYNC2_INT_AK (1 << 6) |
| # define RADEON_VSYNC2_INT (1 << 6) |
| # define RADEON_SW_INT_FIRE (1 << 26) |
| # define RADEON_SW_INT_TEST (1 << 25) |
| # define RADEON_SW_INT_TEST_ACK (1 << 25) |
| #define RADEON_GENENB 0x03c3 /* VGA */ |
| #define RADEON_GENFC_RD 0x03ca /* VGA */ |
| #define RADEON_GENFC_WT 0x03da /* VGA, 0x03ba */ |
| #define RADEON_GENMO_RD 0x03cc /* VGA */ |
| #define RADEON_GENMO_WT 0x03c2 /* VGA */ |
| #define RADEON_GENS0 0x03c2 /* VGA */ |
| #define RADEON_GENS1 0x03da /* VGA, 0x03ba */ |
| #define RADEON_GPIO_MONID 0x0068 /* DDC interface via I2C */ /* DDC3 */ |
| #define RADEON_GPIO_MONIDB 0x006c |
| #define RADEON_GPIO_CRT2_DDC 0x006c |
| #define RADEON_GPIO_DVI_DDC 0x0064 /* DDC2 */ |
| #define RADEON_GPIO_VGA_DDC 0x0060 /* DDC1 */ |
| # define RADEON_GPIO_A_0 (1 << 0) |
| # define RADEON_GPIO_A_1 (1 << 1) |
| # define RADEON_GPIO_Y_0 (1 << 8) |
| # define RADEON_GPIO_Y_1 (1 << 9) |
| # define RADEON_GPIO_Y_SHIFT_0 8 |
| # define RADEON_GPIO_Y_SHIFT_1 9 |
| # define RADEON_GPIO_EN_0 (1 << 16) |
| # define RADEON_GPIO_EN_1 (1 << 17) |
| # define RADEON_GPIO_MASK_0 (1 << 24) /*??*/ |
| # define RADEON_GPIO_MASK_1 (1 << 25) /*??*/ |
| #define RADEON_GRPH8_DATA 0x03cf /* VGA */ |
| #define RADEON_GRPH8_IDX 0x03ce /* VGA */ |
| #define RADEON_GUI_SCRATCH_REG0 0x15e0 |
| #define RADEON_GUI_SCRATCH_REG1 0x15e4 |
| #define RADEON_GUI_SCRATCH_REG2 0x15e8 |
| #define RADEON_GUI_SCRATCH_REG3 0x15ec |
| #define RADEON_GUI_SCRATCH_REG4 0x15f0 |
| #define RADEON_GUI_SCRATCH_REG5 0x15f4 |
| #define RADEON_HEADER 0x0f0e /* PCI */ |
| #define RADEON_HOST_DATA0 0x17c0 |
| #define RADEON_HOST_DATA1 0x17c4 |
| #define RADEON_HOST_DATA2 0x17c8 |
| #define RADEON_HOST_DATA3 0x17cc |
| #define RADEON_HOST_DATA4 0x17d0 |
| #define RADEON_HOST_DATA5 0x17d4 |
| #define RADEON_HOST_DATA6 0x17d8 |
| #define RADEON_HOST_DATA7 0x17dc |
| #define RADEON_HOST_DATA_LAST 0x17e0 |
| #define RADEON_HOST_PATH_CNTL 0x0130 |
| # define RADEON_HP_LIN_RD_CACHE_DIS (1 << 24) |
| # define RADEON_HDP_READ_BUFFER_INVALIDATE (1 << 27) |
| # define RADEON_HDP_SOFT_RESET (1 << 26) |
| # define RADEON_HDP_APER_CNTL (1 << 23) |
| #define RADEON_HTOTAL_CNTL 0x0009 /* PLL */ |
| # define RADEON_HTOT_CNTL_VGA_EN (1 << 28) |
| #define RADEON_HTOTAL2_CNTL 0x002e /* PLL */ |
| /* Multimedia I2C bus */ |
| #define RADEON_I2C_CNTL_0 0x0090 |
| #define RADEON_I2C_DONE (1<<0) |
| #define RADEON_I2C_NACK (1<<1) |
| #define RADEON_I2C_HALT (1<<2) |
| #define RADEON_I2C_SOFT_RST (1<<5) |
| #define RADEON_I2C_DRIVE_EN (1<<6) |
| #define RADEON_I2C_DRIVE_SEL (1<<7) |
| #define RADEON_I2C_START (1<<8) |
| #define RADEON_I2C_STOP (1<<9) |
| #define RADEON_I2C_RECEIVE (1<<10) |
| #define RADEON_I2C_ABORT (1<<11) |
| #define RADEON_I2C_GO (1<<12) |
| #define RADEON_I2C_CNTL_1 0x0094 |
| #define RADEON_I2C_SEL (1<<16) |
| #define RADEON_I2C_EN (1<<17) |
| #define RADEON_I2C_DATA 0x0098 |
| #define RADEON_DVI_I2C_CNTL_0 0x02e0 |
| # define R200_DVI_I2C_PIN_SEL(x) ((x) << 3) |
| # define R200_SEL_DDC1 0 /* 0x60 - VGA_DDC */ |
| # define R200_SEL_DDC2 1 /* 0x64 - DVI_DDC */ |
| # define R200_SEL_DDC3 2 /* 0x68 - MONID_DDC */ |
| #define RADEON_DVI_I2C_CNTL_1 0x02e4 /* ? */ |
| #define RADEON_DVI_I2C_DATA 0x02e8 |
| #define RADEON_INTERRUPT_LINE 0x0f3c /* PCI */ |
| #define RADEON_INTERRUPT_PIN 0x0f3d /* PCI */ |
| #define RADEON_IO_BASE 0x0f14 /* PCI */ |
| #define RADEON_LATENCY 0x0f0d /* PCI */ |
| #define RADEON_LEAD_BRES_DEC 0x1608 |
| #define RADEON_LEAD_BRES_LNTH 0x161c |
| #define RADEON_LEAD_BRES_LNTH_SUB 0x1624 |
| #define RADEON_LVDS_GEN_CNTL 0x02d0 |
| # define RADEON_LVDS_ON (1 << 0) |
| # define RADEON_LVDS_DISPLAY_DIS (1 << 1) |
| # define RADEON_LVDS_PANEL_TYPE (1 << 2) |
| # define RADEON_LVDS_PANEL_FORMAT (1 << 3) |
| # define RADEON_LVDS_NO_FM (0 << 4) |
| # define RADEON_LVDS_2_GREY (1 << 4) |
| # define RADEON_LVDS_4_GREY (2 << 4) |
| # define RADEON_LVDS_RST_FM (1 << 6) |
| # define RADEON_LVDS_EN (1 << 7) |
| # define RADEON_LVDS_BL_MOD_LEVEL_SHIFT 8 |
| # define RADEON_LVDS_BL_MOD_LEVEL_MASK (0xff << 8) |
| # define RADEON_LVDS_BL_MOD_EN (1 << 16) |
| # define RADEON_LVDS_BL_CLK_SEL (1 << 17) |
| # define RADEON_LVDS_DIGON (1 << 18) |
| # define RADEON_LVDS_BLON (1 << 19) |
| # define RADEON_LVDS_FP_POL_LOW (1 << 20) |
| # define RADEON_LVDS_LP_POL_LOW (1 << 21) |
| # define RADEON_LVDS_DTM_POL_LOW (1 << 22) |
| # define RADEON_LVDS_SEL_CRTC2 (1 << 23) |
| # define RADEON_LVDS_FPDI_EN (1 << 27) |
| # define RADEON_LVDS_HSYNC_DELAY_SHIFT 28 |
| #define RADEON_LVDS_PLL_CNTL 0x02d4 |
| # define RADEON_HSYNC_DELAY_SHIFT 28 |
| # define RADEON_HSYNC_DELAY_MASK (0xf << 28) |
| # define RADEON_LVDS_PLL_EN (1 << 16) |
| # define RADEON_LVDS_PLL_RESET (1 << 17) |
| # define R300_LVDS_SRC_SEL_MASK (3 << 18) |
| # define R300_LVDS_SRC_SEL_CRTC1 (0 << 18) |
| # define R300_LVDS_SRC_SEL_CRTC2 (1 << 18) |
| # define R300_LVDS_SRC_SEL_RMX (2 << 18) |
| #define RADEON_LVDS_SS_GEN_CNTL 0x02ec |
| # define RADEON_LVDS_PWRSEQ_DELAY1_SHIFT 16 |
| # define RADEON_LVDS_PWRSEQ_DELAY2_SHIFT 20 |
| #define RADEON_MAX_LATENCY 0x0f3f /* PCI */ |
| #define RADEON_DISPLAY_BASE_ADDR 0x23c |
| #define RADEON_DISPLAY2_BASE_ADDR 0x33c |
| #define RADEON_OV0_BASE_ADDR 0x43c |
| #define RADEON_NB_TOM 0x15c |
| #define R300_MC_INIT_MISC_LAT_TIMER 0x180 |
| # define R300_MC_DISP0R_INIT_LAT_SHIFT 8 |
| # define R300_MC_DISP0R_INIT_LAT_MASK 0xf |
| # define R300_MC_DISP1R_INIT_LAT_SHIFT 12 |
| # define R300_MC_DISP1R_INIT_LAT_MASK 0xf |
| #define RADEON_MCLK_CNTL 0x0012 /* PLL */ |
| # define RADEON_MCLKA_SRC_SEL_MASK 0x7 |
| # define RADEON_FORCEON_MCLKA (1 << 16) |
| # define RADEON_FORCEON_MCLKB (1 << 17) |
| # define RADEON_FORCEON_YCLKA (1 << 18) |
| # define RADEON_FORCEON_YCLKB (1 << 19) |
| # define RADEON_FORCEON_MC (1 << 20) |
| # define RADEON_FORCEON_AIC (1 << 21) |
| # define R300_DISABLE_MC_MCLKA (1 << 21) |
| # define R300_DISABLE_MC_MCLKB (1 << 21) |
| #define RADEON_MCLK_MISC 0x001f /* PLL */ |
| # define RADEON_MC_MCLK_MAX_DYN_STOP_LAT (1 << 12) |
| # define RADEON_IO_MCLK_MAX_DYN_STOP_LAT (1 << 13) |
| # define RADEON_MC_MCLK_DYN_ENABLE (1 << 14) |
| # define RADEON_IO_MCLK_DYN_ENABLE (1 << 15) |
| #define RADEON_LCD_GPIO_MASK 0x01a0 |
| #define RADEON_GPIOPAD_EN 0x01a0 |
| #define RADEON_LCD_GPIO_Y_REG 0x01a4 |
| #define RADEON_MDGPIO_A_REG 0x01ac |
| #define RADEON_MDGPIO_EN_REG 0x01b0 |
| #define RADEON_MDGPIO_MASK 0x0198 |
| #define RADEON_GPIOPAD_MASK 0x0198 |
| #define RADEON_GPIOPAD_A 0x019c |
| #define RADEON_MDGPIO_Y_REG 0x01b4 |
| #define RADEON_MEM_ADDR_CONFIG 0x0148 |
| #define RADEON_MEM_BASE 0x0f10 /* PCI */ |
| #define RADEON_MEM_CNTL 0x0140 |
| # define RADEON_MEM_NUM_CHANNELS_MASK 0x01 |
| # define RADEON_MEM_USE_B_CH_ONLY (1 << 1) |
| # define RV100_HALF_MODE (1 << 3) |
| # define R300_MEM_NUM_CHANNELS_MASK 0x03 |
| # define R300_MEM_USE_CD_CH_ONLY (1 << 2) |
| #define RADEON_MEM_TIMING_CNTL 0x0144 /* EXT_MEM_CNTL */ |
| #define RADEON_MEM_INIT_LAT_TIMER 0x0154 |
| #define RADEON_MEM_INTF_CNTL 0x014c |
| #define RADEON_MEM_SDRAM_MODE_REG 0x0158 |
| # define RADEON_SDRAM_MODE_MASK 0xffff0000 |
| # define RADEON_B3MEM_RESET_MASK 0x6fffffff |
| # define RADEON_MEM_CFG_TYPE_DDR (1 << 30) |
| #define RADEON_MEM_STR_CNTL 0x0150 |
| # define RADEON_MEM_PWRUP_COMPL_A (1 << 0) |
| # define RADEON_MEM_PWRUP_COMPL_B (1 << 1) |
| # define R300_MEM_PWRUP_COMPL_C (1 << 2) |
| # define R300_MEM_PWRUP_COMPL_D (1 << 3) |
| # define RADEON_MEM_PWRUP_COMPLETE 0x03 |
| # define R300_MEM_PWRUP_COMPLETE 0x0f |
| #define RADEON_MC_STATUS 0x0150 |
| # define RADEON_MC_IDLE (1 << 2) |
| # define R300_MC_IDLE (1 << 4) |
| #define RADEON_MEM_VGA_RP_SEL 0x003c |
| #define RADEON_MEM_VGA_WP_SEL 0x0038 |
| #define RADEON_MIN_GRANT 0x0f3e /* PCI */ |
| #define RADEON_MM_DATA 0x0004 |
| #define RADEON_MM_INDEX 0x0000 |
| # define RADEON_MM_APER (1 << 31) |
| #define RADEON_MPLL_CNTL 0x000e /* PLL */ |
| #define RADEON_MPP_TB_CONFIG 0x01c0 /* ? */ |
| #define RADEON_MPP_GP_CONFIG 0x01c8 /* ? */ |
| #define RADEON_SEPROM_CNTL1 0x01c0 |
| # define RADEON_SCK_PRESCALE_SHIFT 24 |
| # define RADEON_SCK_PRESCALE_MASK (0xff << 24) |
| #define R300_MC_IND_INDEX 0x01f8 |
| # define R300_MC_IND_ADDR_MASK 0x3f |
| # define R300_MC_IND_WR_EN (1 << 8) |
| #define R300_MC_IND_DATA 0x01fc |
| #define R300_MC_READ_CNTL_AB 0x017c |
| # define R300_MEM_RBS_POSITION_A_MASK 0x03 |
| #define R300_MC_READ_CNTL_CD_mcind 0x24 |
| # define R300_MEM_RBS_POSITION_C_MASK 0x03 |
| #define RADEON_N_VIF_COUNT 0x0248 |
| #define RADEON_OV0_AUTO_FLIP_CNTL 0x0470 |
| # define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_NUM 0x00000007 |
| # define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_REPEAT_FIELD 0x00000008 |
| # define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD 0x00000010 |
| # define RADEON_OV0_AUTO_FLIP_CNTL_IGNORE_REPEAT_FIELD 0x00000020 |
| # define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE 0x00000040 |
| # define RADEON_OV0_AUTO_FLIP_CNTL_VID_PORT_SELECT 0x00000300 |
| # define RADEON_OV0_AUTO_FLIP_CNTL_P1_FIRST_LINE_EVEN 0x00010000 |
| # define RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_EVEN_DOWN 0x00040000 |
| # define RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_ODD_DOWN 0x00080000 |
| # define RADEON_OV0_AUTO_FLIP_CNTL_FIELD_POL_SOURCE 0x00800000 |
| #define RADEON_OV0_COLOUR_CNTL 0x04E0 |
| #define RADEON_OV0_DEINTERLACE_PATTERN 0x0474 |
| #define RADEON_OV0_EXCLUSIVE_HORZ 0x0408 |
| # define RADEON_EXCL_HORZ_START_MASK 0x000000ff |
| # define RADEON_EXCL_HORZ_END_MASK 0x0000ff00 |
| # define RADEON_EXCL_HORZ_BACK_PORCH_MASK 0x00ff0000 |
| # define RADEON_EXCL_HORZ_EXCLUSIVE_EN 0x80000000 |
| #define RADEON_OV0_EXCLUSIVE_VERT 0x040C |
| # define RADEON_EXCL_VERT_START_MASK 0x000003ff |
| # define RADEON_EXCL_VERT_END_MASK 0x03ff0000 |
| #define RADEON_OV0_FILTER_CNTL 0x04A0 |
| # define RADEON_FILTER_PROGRAMMABLE_COEF 0x0 |
| # define RADEON_FILTER_HC_COEF_HORZ_Y 0x1 |
| # define RADEON_FILTER_HC_COEF_HORZ_UV 0x2 |
| # define RADEON_FILTER_HC_COEF_VERT_Y 0x4 |
| # define RADEON_FILTER_HC_COEF_VERT_UV 0x8 |
| # define RADEON_FILTER_HARDCODED_COEF 0xf |
| # define RADEON_FILTER_COEF_MASK 0xf |
| #define RADEON_OV0_FOUR_TAP_COEF_0 0x04B0 |
| #define RADEON_OV0_FOUR_TAP_COEF_1 0x04B4 |
| #define RADEON_OV0_FOUR_TAP_COEF_2 0x04B8 |
| #define RADEON_OV0_FOUR_TAP_COEF_3 0x04BC |
| #define RADEON_OV0_FOUR_TAP_COEF_4 0x04C0 |
| #define RADEON_OV0_FLAG_CNTL 0x04DC |
| #define RADEON_OV0_GAMMA_000_00F 0x0d40 |
| #define RADEON_OV0_GAMMA_010_01F 0x0d44 |
| #define RADEON_OV0_GAMMA_020_03F 0x0d48 |
| #define RADEON_OV0_GAMMA_040_07F 0x0d4c |
| #define RADEON_OV0_GAMMA_080_0BF 0x0e00 |
| #define RADEON_OV0_GAMMA_0C0_0FF 0x0e04 |
| #define RADEON_OV0_GAMMA_100_13F 0x0e08 |
| #define RADEON_OV0_GAMMA_140_17F 0x0e0c |
| #define RADEON_OV0_GAMMA_180_1BF 0x0e10 |
| #define RADEON_OV0_GAMMA_1C0_1FF 0x0e14 |
| #define RADEON_OV0_GAMMA_200_23F 0x0e18 |
| #define RADEON_OV0_GAMMA_240_27F 0x0e1c |
| #define RADEON_OV0_GAMMA_280_2BF 0x0e20 |
| #define RADEON_OV0_GAMMA_2C0_2FF 0x0e24 |
| #define RADEON_OV0_GAMMA_300_33F 0x0e28 |
| #define RADEON_OV0_GAMMA_340_37F 0x0e2c |
| #define RADEON_OV0_GAMMA_380_3BF 0x0d50 |
| #define RADEON_OV0_GAMMA_3C0_3FF 0x0d54 |
| #define RADEON_OV0_GRAPHICS_KEY_CLR_LOW 0x04EC |
| #define RADEON_OV0_GRAPHICS_KEY_CLR_HIGH 0x04F0 |
| #define RADEON_OV0_H_INC 0x0480 |
| #define RADEON_OV0_KEY_CNTL 0x04F4 |
| # define RADEON_VIDEO_KEY_FN_MASK 0x00000003L |
| # define RADEON_VIDEO_KEY_FN_FALSE 0x00000000L |
| # define RADEON_VIDEO_KEY_FN_TRUE 0x00000001L |
| # define RADEON_VIDEO_KEY_FN_EQ 0x00000002L |
| # define RADEON_VIDEO_KEY_FN_NE 0x00000003L |
| # define RADEON_GRAPHIC_KEY_FN_MASK 0x00000030L |
| # define RADEON_GRAPHIC_KEY_FN_FALSE 0x00000000L |
| # define RADEON_GRAPHIC_KEY_FN_TRUE 0x00000010L |
| # define RADEON_GRAPHIC_KEY_FN_EQ 0x00000020L |
| # define RADEON_GRAPHIC_KEY_FN_NE 0x00000030L |
| # define RADEON_CMP_MIX_MASK 0x00000100L |
| # define RADEON_CMP_MIX_OR 0x00000000L |
| # define RADEON_CMP_MIX_AND 0x00000100L |
| #define RADEON_OV0_LIN_TRANS_A 0x0d20 |
| #define RADEON_OV0_LIN_TRANS_B 0x0d24 |
| #define RADEON_OV0_LIN_TRANS_C 0x0d28 |
| #define RADEON_OV0_LIN_TRANS_D 0x0d2c |
| #define RADEON_OV0_LIN_TRANS_E 0x0d30 |
| #define RADEON_OV0_LIN_TRANS_F 0x0d34 |
| #define RADEON_OV0_P1_BLANK_LINES_AT_TOP 0x0430 |
| # define RADEON_P1_BLNK_LN_AT_TOP_M1_MASK 0x00000fffL |
| # define RADEON_P1_ACTIVE_LINES_M1 0x0fff0000L |
| #define RADEON_OV0_P1_H_ACCUM_INIT 0x0488 |
| #define RADEON_OV0_P1_V_ACCUM_INIT 0x0428 |
| # define RADEON_OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003L |
| # define RADEON_OV0_P1_V_ACCUM_INIT_MASK 0x01ff8000L |
| #define RADEON_OV0_P1_X_START_END 0x0494 |
| #define RADEON_OV0_P2_X_START_END 0x0498 |
| #define RADEON_OV0_P23_BLANK_LINES_AT_TOP 0x0434 |
| # define RADEON_P23_BLNK_LN_AT_TOP_M1_MASK 0x000007ffL |
| # define RADEON_P23_ACTIVE_LINES_M1 0x07ff0000L |
| #define RADEON_OV0_P23_H_ACCUM_INIT 0x048C |
| #define RADEON_OV0_P23_V_ACCUM_INIT 0x042C |
| #define RADEON_OV0_P3_X_START_END 0x049C |
| #define RADEON_OV0_REG_LOAD_CNTL 0x0410 |
| # define RADEON_REG_LD_CTL_LOCK 0x00000001L |
| # define RADEON_REG_LD_CTL_VBLANK_DURING_LOCK 0x00000002L |
| # define RADEON_REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L |
| # define RADEON_REG_LD_CTL_LOCK_READBACK 0x00000008L |
| # define RADEON_REG_LD_CTL_FLIP_READBACK 0x00000010L |
| #define RADEON_OV0_SCALE_CNTL 0x0420 |
| # define RADEON_SCALER_HORZ_PICK_NEAREST 0x00000004L |
| # define RADEON_SCALER_VERT_PICK_NEAREST 0x00000008L |
| # define RADEON_SCALER_SIGNED_UV 0x00000010L |
| # define RADEON_SCALER_GAMMA_SEL_MASK 0x00000060L |
| # define RADEON_SCALER_GAMMA_SEL_BRIGHT 0x00000000L |
| # define RADEON_SCALER_GAMMA_SEL_G22 0x00000020L |
| # define RADEON_SCALER_GAMMA_SEL_G18 0x00000040L |
| # define RADEON_SCALER_GAMMA_SEL_G14 0x00000060L |
| # define RADEON_SCALER_COMCORE_SHIFT_UP_ONE 0x00000080L |
| # define RADEON_SCALER_SURFAC_FORMAT 0x00000f00L |
| # define RADEON_SCALER_SOURCE_15BPP 0x00000300L |
| # define RADEON_SCALER_SOURCE_16BPP 0x00000400L |
| # define RADEON_SCALER_SOURCE_32BPP 0x00000600L |
| # define RADEON_SCALER_SOURCE_YUV9 0x00000900L |
| # define RADEON_SCALER_SOURCE_YUV12 0x00000A00L |
| # define RADEON_SCALER_SOURCE_VYUY422 0x00000B00L |
| # define RADEON_SCALER_SOURCE_YVYU422 0x00000C00L |
| # define RADEON_SCALER_ADAPTIVE_DEINT 0x00001000L |
| # define RADEON_SCALER_TEMPORAL_DEINT 0x00002000L |
| # define RADEON_SCALER_CRTC_SEL 0x00004000L |
| # define RADEON_SCALER_SMART_SWITCH 0x00008000L |
| # define RADEON_SCALER_BURST_PER_PLANE 0x007F0000L |
| # define RADEON_SCALER_DOUBLE_BUFFER 0x01000000L |
| # define RADEON_SCALER_DIS_LIMIT 0x08000000L |
| # define RADEON_SCALER_LIN_TRANS_BYPASS 0x10000000L |
| # define RADEON_SCALER_INT_EMU 0x20000000L |
| # define RADEON_SCALER_ENABLE 0x40000000L |
| # define RADEON_SCALER_SOFT_RESET 0x80000000L |
| #define RADEON_OV0_STEP_BY 0x0484 |
| #define RADEON_OV0_TEST 0x04F8 |
| #define RADEON_OV0_V_INC 0x0424 |
| #define RADEON_OV0_VID_BUF_PITCH0_VALUE 0x0460 |
| #define RADEON_OV0_VID_BUF_PITCH1_VALUE 0x0464 |
| #define RADEON_OV0_VID_BUF0_BASE_ADRS 0x0440 |
| # define RADEON_VIF_BUF0_PITCH_SEL 0x00000001L |
| # define RADEON_VIF_BUF0_TILE_ADRS 0x00000002L |
| # define RADEON_VIF_BUF0_BASE_ADRS_MASK 0x03fffff0L |
| # define RADEON_VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L |
| #define RADEON_OV0_VID_BUF1_BASE_ADRS 0x0444 |
| # define RADEON_VIF_BUF1_PITCH_SEL 0x00000001L |
| # define RADEON_VIF_BUF1_TILE_ADRS 0x00000002L |
| # define RADEON_VIF_BUF1_BASE_ADRS_MASK 0x03fffff0L |
| # define RADEON_VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L |
| #define RADEON_OV0_VID_BUF2_BASE_ADRS 0x0448 |
| # define RADEON_VIF_BUF2_PITCH_SEL 0x00000001L |
| # define RADEON_VIF_BUF2_TILE_ADRS 0x00000002L |
| # define RADEON_VIF_BUF2_BASE_ADRS_MASK 0x03fffff0L |
| # define RADEON_VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L |
| #define RADEON_OV0_VID_BUF3_BASE_ADRS 0x044C |
| #define RADEON_OV0_VID_BUF4_BASE_ADRS 0x0450 |
| #define RADEON_OV0_VID_BUF5_BASE_ADRS 0x0454 |
| #define RADEON_OV0_VIDEO_KEY_CLR_HIGH 0x04E8 |
| #define RADEON_OV0_VIDEO_KEY_CLR_LOW 0x04E4 |
| #define RADEON_OV0_Y_X_START 0x0400 |
| #define RADEON_OV0_Y_X_END 0x0404 |
| #define RADEON_OV1_Y_X_START 0x0600 |
| #define RADEON_OV1_Y_X_END 0x0604 |
| #define RADEON_OVR_CLR 0x0230 |
| #define RADEON_OVR_WID_LEFT_RIGHT 0x0234 |
| #define RADEON_OVR_WID_TOP_BOTTOM 0x0238 |
| /* first capture unit */ |
| #define RADEON_CAP0_BUF0_OFFSET 0x0920 |
| #define RADEON_CAP0_BUF1_OFFSET 0x0924 |
| #define RADEON_CAP0_BUF0_EVEN_OFFSET 0x0928 |
| #define RADEON_CAP0_BUF1_EVEN_OFFSET 0x092C |
| #define RADEON_CAP0_BUF_PITCH 0x0930 |
| #define RADEON_CAP0_V_WINDOW 0x0934 |
| #define RADEON_CAP0_H_WINDOW 0x0938 |
| #define RADEON_CAP0_VBI0_OFFSET 0x093C |
| #define RADEON_CAP0_VBI1_OFFSET 0x0940 |
| #define RADEON_CAP0_VBI_V_WINDOW 0x0944 |
| #define RADEON_CAP0_VBI_H_WINDOW 0x0948 |
| #define RADEON_CAP0_PORT_MODE_CNTL 0x094C |
| #define RADEON_CAP0_TRIG_CNTL 0x0950 |
| #define RADEON_CAP0_DEBUG 0x0954 |
| #define RADEON_CAP0_CONFIG 0x0958 |
| # define RADEON_CAP0_CONFIG_CONTINUOS 0x00000001 |
| # define RADEON_CAP0_CONFIG_START_FIELD_EVEN 0x00000002 |
| # define RADEON_CAP0_CONFIG_START_BUF_GET 0x00000004 |
| # define RADEON_CAP0_CONFIG_START_BUF_SET 0x00000008 |
| # define RADEON_CAP0_CONFIG_BUF_TYPE_ALT 0x00000010 |
| # define RADEON_CAP0_CONFIG_BUF_TYPE_FRAME 0x00000020 |
| # define RADEON_CAP0_CONFIG_ONESHOT_MODE_FRAME 0x00000040 |
| # define RADEON_CAP0_CONFIG_BUF_MODE_DOUBLE 0x00000080 |
| # define RADEON_CAP0_CONFIG_BUF_MODE_TRIPLE 0x00000100 |
| # define RADEON_CAP0_CONFIG_MIRROR_EN 0x00000200 |
| # define RADEON_CAP0_CONFIG_ONESHOT_MIRROR_EN 0x00000400 |
| # define RADEON_CAP0_CONFIG_VIDEO_SIGNED_UV 0x00000800 |
| # define RADEON_CAP0_CONFIG_ANC_DECODE_EN 0x00001000 |
| # define RADEON_CAP0_CONFIG_VBI_EN 0x00002000 |
| # define RADEON_CAP0_CONFIG_SOFT_PULL_DOWN_EN 0x00004000 |
| # define RADEON_CAP0_CONFIG_VIP_EXTEND_FLAG_EN 0x00008000 |
| # define RADEON_CAP0_CONFIG_FAKE_FIELD_EN 0x00010000 |
| # define RADEON_CAP0_CONFIG_ODD_ONE_MORE_LINE 0x00020000 |
| # define RADEON_CAP0_CONFIG_EVEN_ONE_MORE_LINE 0x00040000 |
| # define RADEON_CAP0_CONFIG_HORZ_DIVIDE_2 0x00080000 |
| # define RADEON_CAP0_CONFIG_HORZ_DIVIDE_4 0x00100000 |
| # define RADEON_CAP0_CONFIG_VERT_DIVIDE_2 0x00200000 |
| # define RADEON_CAP0_CONFIG_VERT_DIVIDE_4 0x00400000 |
| # define RADEON_CAP0_CONFIG_FORMAT_BROOKTREE 0x00000000 |
| # define RADEON_CAP0_CONFIG_FORMAT_CCIR656 0x00800000 |
| # define RADEON_CAP0_CONFIG_FORMAT_ZV 0x01000000 |
| # define RADEON_CAP0_CONFIG_FORMAT_VIP 0x01800000 |
| # define RADEON_CAP0_CONFIG_FORMAT_TRANSPORT 0x02000000 |
| # define RADEON_CAP0_CONFIG_HORZ_DECIMATOR 0x04000000 |
| # define RADEON_CAP0_CONFIG_VIDEO_IN_YVYU422 0x00000000 |
| # define RADEON_CAP0_CONFIG_VIDEO_IN_VYUY422 0x20000000 |
| # define RADEON_CAP0_CONFIG_VBI_DIVIDE_2 0x40000000 |
| # define RADEON_CAP0_CONFIG_VBI_DIVIDE_4 0x80000000 |
| #define RADEON_CAP0_ANC_ODD_OFFSET 0x095C |
| #define RADEON_CAP0_ANC_EVEN_OFFSET 0x0960 |
| #define RADEON_CAP0_ANC_H_WINDOW 0x0964 |
| #define RADEON_CAP0_VIDEO_SYNC_TEST 0x0968 |
| #define RADEON_CAP0_ONESHOT_BUF_OFFSET 0x096C |
| #define RADEON_CAP0_BUF_STATUS 0x0970 |
| /* #define RADEON_CAP0_DWNSC_XRATIO 0x0978 */ |
| /* #define RADEON_CAP0_XSHARPNESS 0x097C */ |
| #define RADEON_CAP0_VBI2_OFFSET 0x0980 |
| #define RADEON_CAP0_VBI3_OFFSET 0x0984 |
| #define RADEON_CAP0_ANC2_OFFSET 0x0988 |
| #define RADEON_CAP0_ANC3_OFFSET 0x098C |
| #define RADEON_VID_BUFFER_CONTROL 0x0900 |
| /* second capture unit */ |
| #define RADEON_CAP1_BUF0_OFFSET 0x0990 |
| #define RADEON_CAP1_BUF1_OFFSET 0x0994 |
| #define RADEON_CAP1_BUF0_EVEN_OFFSET 0x0998 |
| #define RADEON_CAP1_BUF1_EVEN_OFFSET 0x099C |
| #define RADEON_CAP1_BUF_PITCH 0x09A0 |
| #define RADEON_CAP1_V_WINDOW 0x09A4 |
| #define RADEON_CAP1_H_WINDOW 0x09A8 |
| #define RADEON_CAP1_VBI_ODD_OFFSET 0x09AC |
| #define RADEON_CAP1_VBI_EVEN_OFFSET 0x09B0 |
| #define RADEON_CAP1_VBI_V_WINDOW 0x09B4 |
| #define RADEON_CAP1_VBI_H_WINDOW 0x09B8 |
| #define RADEON_CAP1_PORT_MODE_CNTL 0x09BC |
| #define RADEON_CAP1_TRIG_CNTL 0x09C0 |
| #define RADEON_CAP1_DEBUG 0x09C4 |
| #define RADEON_CAP1_CONFIG 0x09C8 |
| #define RADEON_CAP1_ANC_ODD_OFFSET 0x09CC |
| #define RADEON_CAP1_ANC_EVEN_OFFSET 0x09D0 |
| #define RADEON_CAP1_ANC_H_WINDOW 0x09D4 |
| #define RADEON_CAP1_VIDEO_SYNC_TEST 0x09D8 |
| #define RADEON_CAP1_ONESHOT_BUF_OFFSET 0x09DC |
| #define RADEON_CAP1_BUF_STATUS 0x09E0 |
| #define RADEON_CAP1_DWNSC_XRATIO 0x09E8 |
| #define RADEON_CAP1_XSHARPNESS 0x09EC |
| /* misc multimedia registers */ |
| #define RADEON_IDCT_RUNS 0x1F80 |
| #define RADEON_IDCT_LEVELS 0x1F84 |
| #define RADEON_IDCT_CONTROL 0x1FBC |
| #define RADEON_IDCT_AUTH_CONTROL 0x1F88 |
| #define RADEON_IDCT_AUTH 0x1F8C |
| #define RADEON_P2PLL_CNTL 0x002a /* P2PLL */ |
| # define RADEON_P2PLL_RESET (1 << 0) |
| # define RADEON_P2PLL_SLEEP (1 << 1) |
| # define RADEON_P2PLL_PVG_MASK (7 << 11) |
| # define RADEON_P2PLL_PVG_SHIFT 11 |
| # define RADEON_P2PLL_ATOMIC_UPDATE_EN (1 << 16) |
| # define RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN (1 << 17) |
| # define RADEON_P2PLL_ATOMIC_UPDATE_VSYNC (1 << 18) |
| #define RADEON_P2PLL_DIV_0 0x002c |
| # define RADEON_P2PLL_FB0_DIV_MASK 0x07ff |
| # define RADEON_P2PLL_POST0_DIV_MASK 0x00070000 |
| #define RADEON_P2PLL_REF_DIV 0x002B /* PLL */ |
| # define RADEON_P2PLL_REF_DIV_MASK 0x03ff |
| # define RADEON_P2PLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ |
| # define RADEON_P2PLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ |
| # define R300_PPLL_REF_DIV_ACC_MASK (0x3ff << 18) |
| # define R300_PPLL_REF_DIV_ACC_SHIFT 18 |
| #define RADEON_PALETTE_DATA 0x00b4 |
| #define RADEON_PALETTE_30_DATA 0x00b8 |
| #define RADEON_PALETTE_INDEX 0x00b0 |
| #define RADEON_PCI_GART_PAGE 0x017c |
| #define RADEON_PIXCLKS_CNTL 0x002d |
| # define RADEON_PIX2CLK_SRC_SEL_MASK 0x03 |
| # define RADEON_PIX2CLK_SRC_SEL_CPUCLK 0x00 |
| # define RADEON_PIX2CLK_SRC_SEL_PSCANCLK 0x01 |
| # define RADEON_PIX2CLK_SRC_SEL_BYTECLK 0x02 |
| # define RADEON_PIX2CLK_SRC_SEL_P2PLLCLK 0x03 |
| # define RADEON_PIX2CLK_ALWAYS_ONb (1<<6) |
| # define RADEON_PIX2CLK_DAC_ALWAYS_ONb (1<<7) |
| # define RADEON_PIXCLK_TV_SRC_SEL (1 << 8) |
| # define RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb (1 << 9) |
| # define R300_DVOCLK_ALWAYS_ONb (1 << 10) |
| # define RADEON_PIXCLK_BLEND_ALWAYS_ONb (1 << 11) |
| # define RADEON_PIXCLK_GV_ALWAYS_ONb (1 << 12) |
| # define RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb (1 << 13) |
| # define R300_PIXCLK_DVO_ALWAYS_ONb (1 << 13) |
| # define RADEON_PIXCLK_LVDS_ALWAYS_ONb (1 << 14) |
| # define RADEON_PIXCLK_TMDS_ALWAYS_ONb (1 << 15) |
| # define R300_PIXCLK_TRANS_ALWAYS_ONb (1 << 16) |
| # define R300_PIXCLK_TVO_ALWAYS_ONb (1 << 17) |
| # define R300_P2G2CLK_ALWAYS_ONb (1 << 18) |
| # define R300_P2G2CLK_DAC_ALWAYS_ONb (1 << 19) |
| # define R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23) |
| #define RADEON_PLANE_3D_MASK_C 0x1d44 |
| #define RADEON_PLL_TEST_CNTL 0x0013 /* PLL */ |
| # define RADEON_PLL_MASK_READ_B (1 << 9) |
| #define RADEON_PMI_CAP_ID 0x0f5c /* PCI */ |
| #define RADEON_PMI_DATA 0x0f63 /* PCI */ |
| #define RADEON_PMI_NXT_CAP_PTR 0x0f5d /* PCI */ |
| #define RADEON_PMI_PMC_REG 0x0f5e /* PCI */ |
| #define RADEON_PMI_PMCSR_REG 0x0f60 /* PCI */ |
| #define RADEON_PMI_REGISTER 0x0f5c /* PCI */ |
| #define RADEON_PPLL_CNTL 0x0002 /* PLL */ |
| # define RADEON_PPLL_RESET (1 << 0) |
| # define RADEON_PPLL_SLEEP (1 << 1) |
| # define RADEON_PPLL_PVG_MASK (7 << 11) |
| # define RADEON_PPLL_PVG_SHIFT 11 |
| # define RADEON_PPLL_ATOMIC_UPDATE_EN (1 << 16) |
| # define RADEON_PPLL_VGA_ATOMIC_UPDATE_EN (1 << 17) |
| # define RADEON_PPLL_ATOMIC_UPDATE_VSYNC (1 << 18) |
| #define RADEON_PPLL_DIV_0 0x0004 /* PLL */ |
| #define RADEON_PPLL_DIV_1 0x0005 /* PLL */ |
| #define RADEON_PPLL_DIV_2 0x0006 /* PLL */ |
| #define RADEON_PPLL_DIV_3 0x0007 /* PLL */ |
| # define RADEON_PPLL_FB3_DIV_MASK 0x07ff |
| # define RADEON_PPLL_POST3_DIV_MASK 0x00070000 |
| #define RADEON_PPLL_REF_DIV 0x0003 /* PLL */ |
| # define RADEON_PPLL_REF_DIV_MASK 0x03ff |
| # define RADEON_PPLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ |
| # define RADEON_PPLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ |
| #define RADEON_PWR_MNGMT_CNTL_STATUS 0x0f60 /* PCI */ |
| #define RADEON_RBBM_GUICNTL 0x172c |
| # define RADEON_HOST_DATA_SWAP_NONE (0 << 0) |
| # define RADEON_HOST_DATA_SWAP_16BIT (1 << 0) |
| # define RADEON_HOST_DATA_SWAP_32BIT (2 << 0) |
| # define RADEON_HOST_DATA_SWAP_HDW (3 << 0) |
| #define RADEON_RBBM_SOFT_RESET 0x00f0 |
| # define RADEON_SOFT_RESET_CP (1 << 0) |
| # define RADEON_SOFT_RESET_HI (1 << 1) |
| # define RADEON_SOFT_RESET_SE (1 << 2) |
| # define RADEON_SOFT_RESET_RE (1 << 3) |
| # define RADEON_SOFT_RESET_PP (1 << 4) |
| # define RADEON_SOFT_RESET_E2 (1 << 5) |
| # define RADEON_SOFT_RESET_RB (1 << 6) |
| # define RADEON_SOFT_RESET_HDP (1 << 7) |
| #define RADEON_RBBM_STATUS 0x0e40 |
| # define RADEON_RBBM_FIFOCNT_MASK 0x007f |
| # define RADEON_RBBM_ACTIVE (1 << 31) |
| #define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c |
| # define RADEON_RB2D_DC_FLUSH (3 << 0) |
| # define RADEON_RB2D_DC_FREE (3 << 2) |
| # define RADEON_RB2D_DC_FLUSH_ALL 0xf |
| # define RADEON_RB2D_DC_BUSY (1 << 31) |
| #define RADEON_RB2D_DSTCACHE_MODE 0x3428 |
| #define RADEON_DSTCACHE_CTLSTAT 0x1714 |
| #define RADEON_RB3D_ZCACHE_MODE 0x3250 |
| #define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254 |
| # define RADEON_RB3D_ZC_FLUSH_ALL 0x5 |
| #define RADEON_RB3D_DSTCACHE_MODE 0x3258 |
| # define RADEON_RB3D_DC_CACHE_ENABLE (0) |
| # define RADEON_RB3D_DC_2D_CACHE_DISABLE (1) |
| # define RADEON_RB3D_DC_3D_CACHE_DISABLE (2) |
| # define RADEON_RB3D_DC_CACHE_DISABLE (3) |
| # define RADEON_RB3D_DC_2D_CACHE_LINESIZE_128 (1 << 2) |
| # define RADEON_RB3D_DC_3D_CACHE_LINESIZE_128 (2 << 2) |
| # define RADEON_RB3D_DC_2D_CACHE_AUTOFLUSH (1 << 8) |
| # define RADEON_RB3D_DC_3D_CACHE_AUTOFLUSH (2 << 8) |
| # define R200_RB3D_DC_2D_CACHE_AUTOFREE (1 << 10) |
| # define R200_RB3D_DC_3D_CACHE_AUTOFREE (2 << 10) |
| # define RADEON_RB3D_DC_FORCE_RMW (1 << 16) |
| # define RADEON_RB3D_DC_DISABLE_RI_FILL (1 << 24) |
| # define RADEON_RB3D_DC_DISABLE_RI_READ (1 << 25) |
| #define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325C |
| # define RADEON_RB3D_DC_FLUSH (3 << 0) |
| # define RADEON_RB3D_DC_FREE (3 << 2) |
| # define RADEON_RB3D_DC_FLUSH_ALL 0xf |
| # define RADEON_RB3D_DC_BUSY (1 << 31) |
| #define RADEON_REG_BASE 0x0f18 /* PCI */ |
| #define RADEON_REGPROG_INF 0x0f09 /* PCI */ |
| #define RADEON_REVISION_ID 0x0f08 /* PCI */ |
| #define RADEON_SC_BOTTOM 0x164c |
| #define RADEON_SC_BOTTOM_RIGHT 0x16f0 |
| #define RADEON_SC_BOTTOM_RIGHT_C 0x1c8c |
| #define RADEON_SC_LEFT 0x1640 |
| #define RADEON_SC_RIGHT 0x1644 |
| #define RADEON_SC_TOP 0x1648 |
| #define RADEON_SC_TOP_LEFT 0x16ec |
| #define RADEON_SC_TOP_LEFT_C 0x1c88 |
| # define RADEON_SC_SIGN_MASK_LO 0x8000 |
| # define RADEON_SC_SIGN_MASK_HI 0x80000000 |
| #define RADEON_M_SPLL_REF_FB_DIV 0x000a /* PLL */ |
| # define RADEON_M_SPLL_REF_DIV_SHIFT 0 |
| # define RADEON_M_SPLL_REF_DIV_MASK 0xff |
| # define RADEON_MPLL_FB_DIV_SHIFT 8 |
| # define RADEON_MPLL_FB_DIV_MASK 0xff |
| # define RADEON_SPLL_FB_DIV_SHIFT 16 |
| # define RADEON_SPLL_FB_DIV_MASK 0xff |
| #define RADEON_SPLL_CNTL 0x000c /* PLL */ |
| # define RADEON_SPLL_SLEEP (1 << 0) |
| # define RADEON_SPLL_RESET (1 << 1) |
| # define RADEON_SPLL_PCP_MASK 0x7 |
| # define RADEON_SPLL_PCP_SHIFT 8 |
| # define RADEON_SPLL_PVG_MASK 0x7 |
| # define RADEON_SPLL_PVG_SHIFT 11 |
| # define RADEON_SPLL_PDC_MASK 0x3 |
| # define RADEON_SPLL_PDC_SHIFT 14 |
| #define RADEON_SCLK_CNTL 0x000d /* PLL */ |
| # define RADEON_SCLK_SRC_SEL_MASK 0x0007 |
| # define RADEON_DYN_STOP_LAT_MASK 0x00007ff8 |
| # define RADEON_CP_MAX_DYN_STOP_LAT 0x0008 |
| # define RADEON_SCLK_FORCEON_MASK 0xffff8000 |
| # define RADEON_SCLK_FORCE_DISP2 (1<<15) |
| # define RADEON_SCLK_FORCE_CP (1<<16) |
| # define RADEON_SCLK_FORCE_HDP (1<<17) |
| # define RADEON_SCLK_FORCE_DISP1 (1<<18) |
| # define RADEON_SCLK_FORCE_TOP (1<<19) |
| # define RADEON_SCLK_FORCE_E2 (1<<20) |
| # define RADEON_SCLK_FORCE_SE (1<<21) |
| # define RADEON_SCLK_FORCE_IDCT (1<<22) |
| # define RADEON_SCLK_FORCE_VIP (1<<23) |
| # define RADEON_SCLK_FORCE_RE (1<<24) |
| # define RADEON_SCLK_FORCE_PB (1<<25) |
| # define RADEON_SCLK_FORCE_TAM (1<<26) |
| # define RADEON_SCLK_FORCE_TDM (1<<27) |
| # define RADEON_SCLK_FORCE_RB (1<<28) |
| # define RADEON_SCLK_FORCE_TV_SCLK (1<<29) |
| # define RADEON_SCLK_FORCE_SUBPIC (1<<30) |
| # define RADEON_SCLK_FORCE_OV0 (1<<31) |
| # define R300_SCLK_FORCE_VAP (1<<21) |
| # define R300_SCLK_FORCE_SR (1<<25) |
| # define R300_SCLK_FORCE_PX (1<<26) |
| # define R300_SCLK_FORCE_TX (1<<27) |
| # define R300_SCLK_FORCE_US (1<<28) |
| # define R300_SCLK_FORCE_SU (1<<30) |
| #define R300_SCLK_CNTL2 0x1e /* PLL */ |
| # define R300_SCLK_TCL_MAX_DYN_STOP_LAT (1<<10) |
| # define R300_SCLK_GA_MAX_DYN_STOP_LAT (1<<11) |
| # define R300_SCLK_CBA_MAX_DYN_STOP_LAT (1<<12) |
| # define R300_SCLK_FORCE_TCL (1<<13) |
| # define R300_SCLK_FORCE_CBA (1<<14) |
| # define R300_SCLK_FORCE_GA (1<<15) |
| #define RADEON_SCLK_MORE_CNTL 0x0035 /* PLL */ |
| # define RADEON_SCLK_MORE_MAX_DYN_STOP_LAT 0x0007 |
| # define RADEON_SCLK_MORE_FORCEON 0x0700 |
| #define RADEON_SDRAM_MODE_REG 0x0158 |
| #define RADEON_SEQ8_DATA 0x03c5 /* VGA */ |
| #define RADEON_SEQ8_IDX 0x03c4 /* VGA */ |
| #define RADEON_SNAPSHOT_F_COUNT 0x0244 |
| #define RADEON_SNAPSHOT_VH_COUNTS 0x0240 |
| #define RADEON_SNAPSHOT_VIF_COUNT 0x024c |
| #define RADEON_SRC_OFFSET 0x15ac |
| #define RADEON_SRC_PITCH 0x15b0 |
| #define RADEON_SRC_PITCH_OFFSET 0x1428 |
| #define RADEON_SRC_SC_BOTTOM 0x165c |
| #define RADEON_SRC_SC_BOTTOM_RIGHT 0x16f4 |
| #define RADEON_SRC_SC_RIGHT 0x1654 |
| #define RADEON_SRC_X 0x1414 |
| #define RADEON_SRC_X_Y 0x1590 |
| #define RADEON_SRC_Y 0x1418 |
| #define RADEON_SRC_Y_X 0x1434 |
| #define RADEON_STATUS 0x0f06 /* PCI */ |
| #define RADEON_SUBPIC_CNTL 0x0540 /* ? */ |
| #define RADEON_SUB_CLASS 0x0f0a /* PCI */ |
| #define RADEON_SURFACE_CNTL 0x0b00 |
| # define RADEON_SURF_TRANSLATION_DIS (1 << 8) |
| # define RADEON_NONSURF_AP0_SWP_16BPP (1 << 20) |
| # define RADEON_NONSURF_AP0_SWP_32BPP (1 << 21) |
| # define RADEON_NONSURF_AP1_SWP_16BPP (1 << 22) |
| # define RADEON_NONSURF_AP1_SWP_32BPP (1 << 23) |
| #define RADEON_SURFACE0_INFO 0x0b0c |
| # define RADEON_SURF_TILE_COLOR_MACRO (0 << 16) |
| # define RADEON_SURF_TILE_COLOR_BOTH (1 << 16) |
| # define RADEON_SURF_TILE_DEPTH_32BPP (2 << 16) |
| # define RADEON_SURF_TILE_DEPTH_16BPP (3 << 16) |
| # define R200_SURF_TILE_NONE (0 << 16) |
| # define R200_SURF_TILE_COLOR_MACRO (1 << 16) |
| # define R200_SURF_TILE_COLOR_MICRO (2 << 16) |
| # define R200_SURF_TILE_COLOR_BOTH (3 << 16) |
| # define R200_SURF_TILE_DEPTH_32BPP (4 << 16) |
| # define R200_SURF_TILE_DEPTH_16BPP (5 << 16) |
| # define R300_SURF_TILE_NONE (0 << 16) |
| # define R300_SURF_TILE_COLOR_MACRO (1 << 16) |
| # define R300_SURF_TILE_DEPTH_32BPP (2 << 16) |
| # define RADEON_SURF_AP0_SWP_16BPP (1 << 20) |
| # define RADEON_SURF_AP0_SWP_32BPP (1 << 21) |
| # define RADEON_SURF_AP1_SWP_16BPP (1 << 22) |
| # define RADEON_SURF_AP1_SWP_32BPP (1 << 23) |
| #define RADEON_SURFACE0_LOWER_BOUND 0x0b04 |
| #define RADEON_SURFACE0_UPPER_BOUND 0x0b08 |
| #define RADEON_SURFACE1_INFO 0x0b1c |
| #define RADEON_SURFACE1_LOWER_BOUND 0x0b14 |
| #define RADEON_SURFACE1_UPPER_BOUND 0x0b18 |
| #define RADEON_SURFACE2_INFO 0x0b2c |
| #define RADEON_SURFACE2_LOWER_BOUND 0x0b24 |
| #define RADEON_SURFACE2_UPPER_BOUND 0x0b28 |
| #define RADEON_SURFACE3_INFO 0x0b3c |
| #define RADEON_SURFACE3_LOWER_BOUND 0x0b34 |
| #define RADEON_SURFACE3_UPPER_BOUND 0x0b38 |
| #define RADEON_SURFACE4_INFO 0x0b4c |
| #define RADEON_SURFACE4_LOWER_BOUND 0x0b44 |
| #define RADEON_SURFACE4_UPPER_BOUND 0x0b48 |
| #define RADEON_SURFACE5_INFO 0x0b5c |
| #define RADEON_SURFACE5_LOWER_BOUND 0x0b54 |
| #define RADEON_SURFACE5_UPPER_BOUND 0x0b58 |
| #define RADEON_SURFACE6_INFO 0x0b6c |
| #define RADEON_SURFACE6_LOWER_BOUND 0x0b64 |
| #define RADEON_SURFACE6_UPPER_BOUND 0x0b68 |
| #define RADEON_SURFACE7_INFO 0x0b7c |
| #define RADEON_SURFACE7_LOWER_BOUND 0x0b74 |
| #define RADEON_SURFACE7_UPPER_BOUND 0x0b78 |
| #define RADEON_SW_SEMAPHORE 0x013c |
| #define RADEON_TEST_DEBUG_CNTL 0x0120 |
| #define RADEON_TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN 0x00000001 |
| #define RADEON_TEST_DEBUG_MUX 0x0124 |
| #define RADEON_TEST_DEBUG_OUT 0x012c |
| #define RADEON_TMDS_PLL_CNTL 0x02a8 |
| #define RADEON_TMDS_TRANSMITTER_CNTL 0x02a4 |
| # define RADEON_TMDS_TRANSMITTER_PLLEN 1 |
| # define RADEON_TMDS_TRANSMITTER_PLLRST 2 |
| #define RADEON_TRAIL_BRES_DEC 0x1614 |
| #define RADEON_TRAIL_BRES_ERR 0x160c |
| #define RADEON_TRAIL_BRES_INC 0x1610 |
| #define RADEON_TRAIL_X 0x1618 |
| #define RADEON_TRAIL_X_SUB 0x1620 |
| #define RADEON_VCLK_ECP_CNTL 0x0008 /* PLL */ |
| # define RADEON_VCLK_SRC_SEL_MASK 0x03 |
| # define RADEON_VCLK_SRC_SEL_CPUCLK 0x00 |
| # define RADEON_VCLK_SRC_SEL_PSCANCLK 0x01 |
| # define RADEON_VCLK_SRC_SEL_BYTECLK 0x02 |
| # define RADEON_VCLK_SRC_SEL_PPLLCLK 0x03 |
| # define RADEON_PIXCLK_ALWAYS_ONb (1<<6) |
| # define RADEON_PIXCLK_DAC_ALWAYS_ONb (1<<7) |
| # define R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF (1<<23) |
| #define RADEON_VENDOR_ID 0x0f00 /* PCI */ |
| #define RADEON_VGA_DDA_CONFIG 0x02e8 |
| #define RADEON_VGA_DDA_ON_OFF 0x02ec |
| #define RADEON_VID_BUFFER_CONTROL 0x0900 |
| #define RADEON_VIDEOMUX_CNTL 0x0190 |
| /* VIP bus */ |
| #define RADEON_VIPH_CH0_DATA 0x0c00 |
| #define RADEON_VIPH_CH1_DATA 0x0c04 |
| #define RADEON_VIPH_CH2_DATA 0x0c08 |
| #define RADEON_VIPH_CH3_DATA 0x0c0c |
| #define RADEON_VIPH_CH0_ADDR 0x0c10 |
| #define RADEON_VIPH_CH1_ADDR 0x0c14 |
| #define RADEON_VIPH_CH2_ADDR 0x0c18 |
| #define RADEON_VIPH_CH3_ADDR 0x0c1c |
| #define RADEON_VIPH_CH0_SBCNT 0x0c20 |
| #define RADEON_VIPH_CH1_SBCNT 0x0c24 |
| #define RADEON_VIPH_CH2_SBCNT 0x0c28 |
| #define RADEON_VIPH_CH3_SBCNT 0x0c2c |
| #define RADEON_VIPH_CH0_ABCNT 0x0c30 |
| #define RADEON_VIPH_CH1_ABCNT 0x0c34 |
| #define RADEON_VIPH_CH2_ABCNT 0x0c38 |
| #define RADEON_VIPH_CH3_ABCNT 0x0c3c |
| #define RADEON_VIPH_CONTROL 0x0c40 |
| # define RADEON_VIP_BUSY 0 |
| # define RADEON_VIP_IDLE 1 |
| # define RADEON_VIP_RESET 2 |
| # define RADEON_VIPH_EN (1 << 21) |
| #define RADEON_VIPH_DV_LAT 0x0c44 |
| #define RADEON_VIPH_BM_CHUNK 0x0c48 |
| #define RADEON_VIPH_DV_INT 0x0c4c |
| #define RADEON_VIPH_TIMEOUT_STAT 0x0c50 |
| #define RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_STAT 0x00000010 |
| #define RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_AK 0x00000010 |
| #define RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS 0x01000000 |
| #define RADEON_VIPH_REG_DATA 0x0084 |
| #define RADEON_VIPH_REG_ADDR 0x0080 |
| #define RADEON_WAIT_UNTIL 0x1720 |
| # define RADEON_WAIT_CRTC_PFLIP (1 << 0) |
| # define RADEON_WAIT_RE_CRTC_VLINE (1 << 1) |
| # define RADEON_WAIT_FE_CRTC_VLINE (1 << 2) |
| # define RADEON_WAIT_CRTC_VLINE (1 << 3) |
| # define RADEON_WAIT_DMA_VID_IDLE (1 << 8) |
| # define RADEON_WAIT_DMA_GUI_IDLE (1 << 9) |
| # define RADEON_WAIT_CMDFIFO (1 << 10) /* wait for CMDFIFO_ENTRIES */ |
| # define RADEON_WAIT_OV0_FLIP (1 << 11) |
| # define RADEON_WAIT_AGP_FLUSH (1 << 13) |
| # define RADEON_WAIT_2D_IDLE (1 << 14) |
| # define RADEON_WAIT_3D_IDLE (1 << 15) |
| # define RADEON_WAIT_2D_IDLECLEAN (1 << 16) |
| # define RADEON_WAIT_3D_IDLECLEAN (1 << 17) |
| # define RADEON_WAIT_HOST_IDLECLEAN (1 << 18) |
| # define RADEON_CMDFIFO_ENTRIES_SHIFT 10 |
| # define RADEON_CMDFIFO_ENTRIES_MASK 0x7f |
| # define RADEON_WAIT_VAP_IDLE (1 << 28) |
| # define RADEON_WAIT_BOTH_CRTC_PFLIP (1 << 30) |
| # define RADEON_ENG_DISPLAY_SELECT_CRTC0 (0 << 31) |
| # define RADEON_ENG_DISPLAY_SELECT_CRTC1 (1 << 31) |
| #define RADEON_X_MPLL_REF_FB_DIV 0x000a /* PLL */ |
| #define RADEON_XCLK_CNTL 0x000d /* PLL */ |
| #define RADEON_XDLL_CNTL 0x000c /* PLL */ |
| #define RADEON_XPLL_CNTL 0x000b /* PLL */ |
| /* Registers for 3D/TCL */ |
| #define RADEON_PP_BORDER_COLOR_0 0x1d40 |
| #define RADEON_PP_BORDER_COLOR_1 0x1d44 |
| #define RADEON_PP_BORDER_COLOR_2 0x1d48 |
| #define RADEON_PP_CNTL 0x1c38 |
| # define RADEON_STIPPLE_ENABLE (1 << 0) |
| # define RADEON_SCISSOR_ENABLE (1 << 1) |
| # define RADEON_PATTERN_ENABLE (1 << 2) |
| # define RADEON_SHADOW_ENABLE (1 << 3) |
| # define RADEON_TEX_ENABLE_MASK (0xf << 4) |
| # define RADEON_TEX_0_ENABLE (1 << 4) |
| # define RADEON_TEX_1_ENABLE (1 << 5) |
| # define RADEON_TEX_2_ENABLE (1 << 6) |
| # define RADEON_TEX_3_ENABLE (1 << 7) |
| # define RADEON_TEX_BLEND_ENABLE_MASK (0xf << 12) |
| # define RADEON_TEX_BLEND_0_ENABLE (1 << 12) |
| # define RADEON_TEX_BLEND_1_ENABLE (1 << 13) |
| # define RADEON_TEX_BLEND_2_ENABLE (1 << 14) |
| # define RADEON_TEX_BLEND_3_ENABLE (1 << 15) |
| # define RADEON_PLANAR_YUV_ENABLE (1 << 20) |
| # define RADEON_SPECULAR_ENABLE (1 << 21) |
| # define RADEON_FOG_ENABLE (1 << 22) |
| # define RADEON_ALPHA_TEST_ENABLE (1 << 23) |
| # define RADEON_ANTI_ALIAS_NONE (0 << 24) |
| # define RADEON_ANTI_ALIAS_LINE (1 << 24) |
| # define RADEON_ANTI_ALIAS_POLY (2 << 24) |
| # define RADEON_ANTI_ALIAS_LINE_POLY (3 << 24) |
| # define RADEON_BUMP_MAP_ENABLE (1 << 26) |
| # define RADEON_BUMPED_MAP_T0 (0 << 27) |
| # define RADEON_BUMPED_MAP_T1 (1 << 27) |
| # define RADEON_BUMPED_MAP_T2 (2 << 27) |
| # define RADEON_TEX_3D_ENABLE_0 (1 << 29) |
| # define RADEON_TEX_3D_ENABLE_1 (1 << 30) |
| # define RADEON_MC_ENABLE (1 << 31) |
| #define RADEON_PP_FOG_COLOR 0x1c18 |
| # define RADEON_FOG_COLOR_MASK 0x00ffffff |
| # define RADEON_FOG_VERTEX (0 << 24) |
| # define RADEON_FOG_TABLE (1 << 24) |
| # define RADEON_FOG_USE_DEPTH (0 << 25) |
| # define RADEON_FOG_USE_DIFFUSE_ALPHA (2 << 25) |
| # define RADEON_FOG_USE_SPEC_ALPHA (3 << 25) |
| #define RADEON_PP_LUM_MATRIX 0x1d00 |
| #define RADEON_PP_MISC 0x1c14 |
| # define RADEON_REF_ALPHA_MASK 0x000000ff |
| # define RADEON_ALPHA_TEST_FAIL (0 << 8) |
| # define RADEON_ALPHA_TEST_LESS (1 << 8) |
| # define RADEON_ALPHA_TEST_LEQUAL (2 << 8) |
| # define RADEON_ALPHA_TEST_EQUAL (3 << 8) |
| # define RADEON_ALPHA_TEST_GEQUAL (4 << 8) |
| # define RADEON_ALPHA_TEST_GREATER (5 << 8) |
| # define RADEON_ALPHA_TEST_NEQUAL (6 << 8) |
| # define RADEON_ALPHA_TEST_PASS (7 << 8) |
| # define RADEON_ALPHA_TEST_OP_MASK (7 << 8) |
| # define RADEON_CHROMA_FUNC_FAIL (0 << 16) |
| # define RADEON_CHROMA_FUNC_PASS (1 << 16) |
| # define RADEON_CHROMA_FUNC_NEQUAL (2 << 16) |
| # define RADEON_CHROMA_FUNC_EQUAL (3 << 16) |
| # define RADEON_CHROMA_KEY_NEAREST (0 << 18) |
| # define RADEON_CHROMA_KEY_ZERO (1 << 18) |
| # define RADEON_SHADOW_ID_AUTO_INC (1 << 20) |
| # define RADEON_SHADOW_FUNC_EQUAL (0 << 21) |
| # define RADEON_SHADOW_FUNC_NEQUAL (1 << 21) |
| # define RADEON_SHADOW_PASS_1 (0 << 22) |
| # define RADEON_SHADOW_PASS_2 (1 << 22) |
| # define RADEON_RIGHT_HAND_CUBE_D3D (0 << 24) |
| # define RADEON_RIGHT_HAND_CUBE_OGL (1 << 24) |
| #define RADEON_PP_ROT_MATRIX_0 0x1d58 |
| #define RADEON_PP_ROT_MATRIX_1 0x1d5c |
| #define RADEON_PP_TXFILTER_0 0x1c54 |
| #define RADEON_PP_TXFILTER_1 0x1c6c |
| #define RADEON_PP_TXFILTER_2 0x1c84 |
| # define RADEON_MAG_FILTER_NEAREST (0 << 0) |
| # define RADEON_MAG_FILTER_LINEAR (1 << 0) |
| # define RADEON_MAG_FILTER_MASK (1 << 0) |
| # define RADEON_MIN_FILTER_NEAREST (0 << 1) |
| # define RADEON_MIN_FILTER_LINEAR (1 << 1) |
| # define RADEON_MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1) |
| # define RADEON_MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1) |
| # define RADEON_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1) |
| # define RADEON_MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1) |
| # define RADEON_MIN_FILTER_ANISO_NEAREST (8 << 1) |
| # define RADEON_MIN_FILTER_ANISO_LINEAR (9 << 1) |
| # define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1) |
| # define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1) |
| # define RADEON_MIN_FILTER_MASK (15 << 1) |
| # define RADEON_MAX_ANISO_1_TO_1 (0 << 5) |
| # define RADEON_MAX_ANISO_2_TO_1 (1 << 5) |
| # define RADEON_MAX_ANISO_4_TO_1 (2 << 5) |
| # define RADEON_MAX_ANISO_8_TO_1 (3 << 5) |
| # define RADEON_MAX_ANISO_16_TO_1 (4 << 5) |
| # define RADEON_MAX_ANISO_MASK (7 << 5) |
| # define RADEON_LOD_BIAS_MASK (0xff << 8) |
| # define RADEON_LOD_BIAS_SHIFT 8 |
| # define RADEON_MAX_MIP_LEVEL_MASK (0x0f << 16) |
| # define RADEON_MAX_MIP_LEVEL_SHIFT 16 |
| # define RADEON_YUV_TO_RGB (1 << 20) |
| # define RADEON_YUV_TEMPERATURE_COOL (0 << 21) |
| # define RADEON_YUV_TEMPERATURE_HOT (1 << 21) |
| # define RADEON_YUV_TEMPERATURE_MASK (1 << 21) |
| # define RADEON_WRAPEN_S (1 << 22) |
| # define RADEON_CLAMP_S_WRAP (0 << 23) |
| # define RADEON_CLAMP_S_MIRROR (1 << 23) |
| # define RADEON_CLAMP_S_CLAMP_LAST (2 << 23) |
| # define RADEON_CLAMP_S_MIRROR_CLAMP_LAST (3 << 23) |
| # define RADEON_CLAMP_S_CLAMP_BORDER (4 << 23) |
| # define RADEON_CLAMP_S_MIRROR_CLAMP_BORDER (5 << 23) |
| # define RADEON_CLAMP_S_CLAMP_GL (6 << 23) |
| # define RADEON_CLAMP_S_MIRROR_CLAMP_GL (7 << 23) |
| # define RADEON_CLAMP_S_MASK (7 << 23) |
| # define RADEON_WRAPEN_T (1 << 26) |
| # define RADEON_CLAMP_T_WRAP (0 << 27) |
| # define RADEON_CLAMP_T_MIRROR (1 << 27) |
| # define RADEON_CLAMP_T_CLAMP_LAST (2 << 27) |
| # define RADEON_CLAMP_T_MIRROR_CLAMP_LAST (3 << 27) |
| # define RADEON_CLAMP_T_CLAMP_BORDER (4 << 27) |
| # define RADEON_CLAMP_T_MIRROR_CLAMP_BORDER (5 << 27) |
| # define RADEON_CLAMP_T_CLAMP_GL (6 << 27) |
| # define RADEON_CLAMP_T_MIRROR_CLAMP_GL (7 << 27) |
| # define RADEON_CLAMP_T_MASK (7 << 27) |
| # define RADEON_BORDER_MODE_OGL (0 << 31) |
| # define RADEON_BORDER_MODE_D3D (1 << 31) |
| #define RADEON_PP_TXFORMAT_0 0x1c58 |
| #define RADEON_PP_TXFORMAT_1 0x1c70 |
| #define RADEON_PP_TXFORMAT_2 0x1c88 |
| # define RADEON_TXFORMAT_I8 (0 << 0) |
| # define RADEON_TXFORMAT_AI88 (1 << 0) |
| # define RADEON_TXFORMAT_RGB332 (2 << 0) |
| # define RADEON_TXFORMAT_ARGB1555 (3 << 0) |
| # define RADEON_TXFORMAT_RGB565 (4 << 0) |
| # define RADEON_TXFORMAT_ARGB4444 (5 << 0) |
| # define RADEON_TXFORMAT_ARGB8888 (6 << 0) |
| # define RADEON_TXFORMAT_RGBA8888 (7 << 0) |
| # define RADEON_TXFORMAT_Y8 (8 << 0) |
| # define RADEON_TXFORMAT_VYUY422 (10 << 0) |
| # define RADEON_TXFORMAT_YVYU422 (11 << 0) |
| # define RADEON_TXFORMAT_DXT1 (12 << 0) |
| # define RADEON_TXFORMAT_DXT23 (14 << 0) |
| # define RADEON_TXFORMAT_DXT45 (15 << 0) |
| # define RADEON_TXFORMAT_FORMAT_MASK (31 << 0) |
| # define RADEON_TXFORMAT_FORMAT_SHIFT 0 |
| # define RADEON_TXFORMAT_APPLE_YUV_MODE (1 << 5) |
| # define RADEON_TXFORMAT_ALPHA_IN_MAP (1 << 6) |
| # define RADEON_TXFORMAT_NON_POWER2 (1 << 7) |
| # define RADEON_TXFORMAT_WIDTH_MASK (15 << 8) |
| # define RADEON_TXFORMAT_WIDTH_SHIFT 8 |
| # define RADEON_TXFORMAT_HEIGHT_MASK (15 << 12) |
| # define RADEON_TXFORMAT_HEIGHT_SHIFT 12 |
| # define RADEON_TXFORMAT_F5_WIDTH_MASK (15 << 16) |
| # define RADEON_TXFORMAT_F5_WIDTH_SHIFT 16 |
| # define RADEON_TXFORMAT_F5_HEIGHT_MASK (15 << 20) |
| # define RADEON_TXFORMAT_F5_HEIGHT_SHIFT 20 |
| # define RADEON_TXFORMAT_ST_ROUTE_STQ0 (0 << 24) |
| # define RADEON_TXFORMAT_ST_ROUTE_MASK (3 << 24) |
| # define RADEON_TXFORMAT_ST_ROUTE_STQ1 (1 << 24) |
| # define RADEON_TXFORMAT_ST_ROUTE_STQ2 (2 << 24) |
| # define RADEON_TXFORMAT_ENDIAN_NO_SWAP (0 << 26) |
| # define RADEON_TXFORMAT_ENDIAN_16BPP_SWAP (1 << 26) |
| # define RADEON_TXFORMAT_ENDIAN_32BPP_SWAP (2 << 26) |
| # define RADEON_TXFORMAT_ENDIAN_HALFDW_SWAP (3 << 26) |
| # define RADEON_TXFORMAT_ALPHA_MASK_ENABLE (1 << 28) |
| # define RADEON_TXFORMAT_CHROMA_KEY_ENABLE (1 << 29) |
| # define RADEON_TXFORMAT_CUBIC_MAP_ENABLE (1 << 30) |
| # define RADEON_TXFORMAT_PERSPECTIVE_ENABLE (1 << 31) |
| #define RADEON_PP_CUBIC_FACES_0 0x1d24 |
| #define RADEON_PP_CUBIC_FACES_1 0x1d28 |
| #define RADEON_PP_CUBIC_FACES_2 0x1d2c |
| # define RADEON_FACE_WIDTH_1_SHIFT 0 |
| # define RADEON_FACE_HEIGHT_1_SHIFT 4 |
| # define RADEON_FACE_WIDTH_1_MASK (0xf << 0) |
| # define RADEON_FACE_HEIGHT_1_MASK (0xf << 4) |
| # define RADEON_FACE_WIDTH_2_SHIFT 8 |
| # define RADEON_FACE_HEIGHT_2_SHIFT 12 |
| # define RADEON_FACE_WIDTH_2_MASK (0xf << 8) |
| # define RADEON_FACE_HEIGHT_2_MASK (0xf << 12) |
| # define RADEON_FACE_WIDTH_3_SHIFT 16 |
| # define RADEON_FACE_HEIGHT_3_SHIFT 20 |
| # define RADEON_FACE_WIDTH_3_MASK (0xf << 16) |
| # define RADEON_FACE_HEIGHT_3_MASK (0xf << 20) |
| # define RADEON_FACE_WIDTH_4_SHIFT 24 |
| # define RADEON_FACE_HEIGHT_4_SHIFT 28 |
| # define RADEON_FACE_WIDTH_4_MASK (0xf << 24) |
| # define RADEON_FACE_HEIGHT_4_MASK (0xf << 28) |
| #define RADEON_PP_TXOFFSET_0 0x1c5c |
| #define RADEON_PP_TXOFFSET_1 0x1c74 |
| #define RADEON_PP_TXOFFSET_2 0x1c8c |
| # define RADEON_TXO_ENDIAN_NO_SWAP (0 << 0) |
| # define RADEON_TXO_ENDIAN_BYTE_SWAP (1 << 0) |
| # define RADEON_TXO_ENDIAN_WORD_SWAP (2 << 0) |
| # define RADEON_TXO_ENDIAN_HALFDW_SWAP (3 << 0) |
| # define RADEON_TXO_MACRO_LINEAR (0 << 2) |
| # define RADEON_TXO_MACRO_TILE (1 << 2) |
| # define RADEON_TXO_MICRO_LINEAR (0 << 3) |
| # define RADEON_TXO_MICRO_TILE_X2 (1 << 3) |
| # define RADEON_TXO_MICRO_TILE_OPT (2 << 3) |
| # define RADEON_TXO_OFFSET_MASK 0xffffffe0 |
| # define RADEON_TXO_OFFSET_SHIFT 5 |
| #define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */ |
| #define RADEON_PP_CUBIC_OFFSET_T0_1 0x1dd4 |
| #define RADEON_PP_CUBIC_OFFSET_T0_2 0x1dd8 |
| #define RADEON_PP_CUBIC_OFFSET_T0_3 0x1ddc |
| #define RADEON_PP_CUBIC_OFFSET_T0_4 0x1de0 |
| #define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00 |
| #define RADEON_PP_CUBIC_OFFSET_T1_1 0x1e04 |
| #define RADEON_PP_CUBIC_OFFSET_T1_2 0x1e08 |
| #define RADEON_PP_CUBIC_OFFSET_T1_3 0x1e0c |
| #define RADEON_PP_CUBIC_OFFSET_T1_4 0x1e10 |
| #define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14 |
| #define RADEON_PP_CUBIC_OFFSET_T2_1 0x1e18 |
| #define RADEON_PP_CUBIC_OFFSET_T2_2 0x1e1c |
| #define RADEON_PP_CUBIC_OFFSET_T2_3 0x1e20 |
| #define RADEON_PP_CUBIC_OFFSET_T2_4 0x1e24 |
| #define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */ |
| #define RADEON_PP_TEX_SIZE_1 0x1d0c |
| #define RADEON_PP_TEX_SIZE_2 0x1d14 |
| # define RADEON_TEX_USIZE_MASK (0x7ff << 0) |
| # define RADEON_TEX_USIZE_SHIFT 0 |
| # define RADEON_TEX_VSIZE_MASK (0x7ff << 16) |
| # define RADEON_TEX_VSIZE_SHIFT 16 |
| # define RADEON_SIGNED_RGB_MASK (1 << 30) |
| # define RADEON_SIGNED_RGB_SHIFT 30 |
| # define RADEON_SIGNED_ALPHA_MASK (1 << 31) |
| # define RADEON_SIGNED_ALPHA_SHIFT 31 |
| #define RADEON_PP_TEX_PITCH_0 0x1d08 /* NPOT */ |
| #define RADEON_PP_TEX_PITCH_1 0x1d10 /* NPOT */ |
| #define RADEON_PP_TEX_PITCH_2 0x1d18 /* NPOT */ |
| /* note: bits 13-5: 32 byte aligned stride of texture map */ |
| #define RADEON_PP_TXCBLEND_0 0x1c60 |
| #define RADEON_PP_TXCBLEND_1 0x1c78 |
| #define RADEON_PP_TXCBLEND_2 0x1c90 |
| # define RADEON_COLOR_ARG_A_SHIFT 0 |
| # define RADEON_COLOR_ARG_A_MASK (0x1f << 0) |
| # define RADEON_COLOR_ARG_A_ZERO (0 << 0) |
| # define RADEON_COLOR_ARG_A_CURRENT_COLOR (2 << 0) |
| # define RADEON_COLOR_ARG_A_CURRENT_ALPHA (3 << 0) |
| # define RADEON_COLOR_ARG_A_DIFFUSE_COLOR (4 << 0) |
| # define RADEON_COLOR_ARG_A_DIFFUSE_ALPHA (5 << 0) |
| # define RADEON_COLOR_ARG_A_SPECULAR_COLOR (6 << 0) |
| # define RADEON_COLOR_ARG_A_SPECULAR_ALPHA (7 << 0) |
| # define RADEON_COLOR_ARG_A_TFACTOR_COLOR (8 << 0) |
| # define RADEON_COLOR_ARG_A_TFACTOR_ALPHA (9 << 0) |
| # define RADEON_COLOR_ARG_A_T0_COLOR (10 << 0) |
| # define RADEON_COLOR_ARG_A_T0_ALPHA (11 << 0) |
| # define RADEON_COLOR_ARG_A_T1_COLOR (12 << 0) |
| # define RADEON_COLOR_ARG_A_T1_ALPHA (13 << 0) |
| # define RADEON_COLOR_ARG_A_T2_COLOR (14 << 0) |
| # define RADEON_COLOR_ARG_A_T2_ALPHA (15 << 0) |
| # define RADEON_COLOR_ARG_A_T3_COLOR (16 << 0) |
| # define RADEON_COLOR_ARG_A_T3_ALPHA (17 << 0) |
| # define RADEON_COLOR_ARG_B_SHIFT 5 |
| # define RADEON_COLOR_ARG_B_MASK (0x1f << 5) |
| # define RADEON_COLOR_ARG_B_ZERO (0 << 5) |
| # define RADEON_COLOR_ARG_B_CURRENT_COLOR (2 << 5) |
| # define RADEON_COLOR_ARG_B_CURRENT_ALPHA (3 << 5) |
| # define RADEON_COLOR_ARG_B_DIFFUSE_COLOR (4 << 5) |
| # define RADEON_COLOR_ARG_B_DIFFUSE_ALPHA (5 << 5) |
| # define RADEON_COLOR_ARG_B_SPECULAR_COLOR (6 << 5) |
| # define RADEON_COLOR_ARG_B_SPECULAR_ALPHA (7 << 5) |
| # define RADEON_COLOR_ARG_B_TFACTOR_COLOR (8 << 5) |
| # define RADEON_COLOR_ARG_B_TFACTOR_ALPHA (9 << 5) |
| # define RADEON_COLOR_ARG_B_T0_COLOR (10 << 5) |
| # define RADEON_COLOR_ARG_B_T0_ALPHA (11 << 5) |
| # define RADEON_COLOR_ARG_B_T1_COLOR (12 << 5) |
| # define RADEON_COLOR_ARG_B_T1_ALPHA (13 << 5) |
| # define RADEON_COLOR_ARG_B_T2_COLOR (14 << 5) |
| # define RADEON_COLOR_ARG_B_T2_ALPHA (15 << 5) |
| # define RADEON_COLOR_ARG_B_T3_COLOR (16 << 5) |
| # define RADEON_COLOR_ARG_B_T3_ALPHA (17 << 5) |
| # define RADEON_COLOR_ARG_C_SHIFT 10 |
| # define RADEON_COLOR_ARG_C_MASK (0x1f << 10) |
| # define RADEON_COLOR_ARG_C_ZERO (0 << 10) |
| # define RADEON_COLOR_ARG_C_CURRENT_COLOR (2 << 10) |
| # define RADEON_COLOR_ARG_C_CURRENT_ALPHA (3 << 10) |
| # define RADEON_COLOR_ARG_C_DIFFUSE_COLOR (4 << 10) |
| # define RADEON_COLOR_ARG_C_DIFFUSE_ALPHA (5 << 10) |
| # define RADEON_COLOR_ARG_C_SPECULAR_COLOR (6 << 10) |
| # define RADEON_COLOR_ARG_C_SPECULAR_ALPHA (7 << 10) |
| # define RADEON_COLOR_ARG_C_TFACTOR_COLOR (8 << 10) |
| # define RADEON_COLOR_ARG_C_TFACTOR_ALPHA (9 << 10) |
| # define RADEON_COLOR_ARG_C_T0_COLOR (10 << 10) |
| # define RADEON_COLOR_ARG_C_T0_ALPHA (11 << 10) |
| # define RADEON_COLOR_ARG_C_T1_COLOR (12 << 10) |
| # define RADEON_COLOR_ARG_C_T1_ALPHA (13 << 10) |
| # define RADEON_COLOR_ARG_C_T2_COLOR (14 << 10) |
| # define RADEON_COLOR_ARG_C_T2_ALPHA (15 << 10) |
| # define RADEON_COLOR_ARG_C_T3_COLOR (16 << 10) |
| # define RADEON_COLOR_ARG_C_T3_ALPHA (17 << 10) |
| # define RADEON_COMP_ARG_A (1 << 15) |
| # define RADEON_COMP_ARG_A_SHIFT 15 |
| # define RADEON_COMP_ARG_B (1 << 16) |
| # define RADEON_COMP_ARG_B_SHIFT 16 |
| # define RADEON_COMP_ARG_C (1 << 17) |
| # define RADEON_COMP_ARG_C_SHIFT 17 |
| # define RADEON_BLEND_CTL_MASK (7 << 18) |
| # define RADEON_BLEND_CTL_ADD (0 << 18) |
| # define RADEON_BLEND_CTL_SUBTRACT (1 << 18) |
| # define RADEON_BLEND_CTL_ADDSIGNED (2 << 18) |
| # define RADEON_BLEND_CTL_BLEND (3 << 18) |
| # define RADEON_BLEND_CTL_DOT3 (4 << 18) |
| # define RADEON_SCALE_SHIFT 21 |
| # define RADEON_SCALE_MASK (3 << 21) |
| # define RADEON_SCALE_1X (0 << 21) |
| # define RADEON_SCALE_2X (1 << 21) |
| # define RADEON_SCALE_4X (2 << 21) |
| # define RADEON_CLAMP_TX (1 << 23) |
| # define RADEON_T0_EQ_TCUR (1 << 24) |
| # define RADEON_T1_EQ_TCUR (1 << 25) |
| # define RADEON_T2_EQ_TCUR (1 << 26) |
| # define RADEON_T3_EQ_TCUR (1 << 27) |
| # define RADEON_COLOR_ARG_MASK 0x1f |
| # define RADEON_COMP_ARG_SHIFT 15 |
| #define RADEON_PP_TXABLEND_0 0x1c64 |
| #define RADEON_PP_TXABLEND_1 0x1c7c |
| #define RADEON_PP_TXABLEND_2 0x1c94 |
| # define RADEON_ALPHA_ARG_A_SHIFT 0 |
| # define RADEON_ALPHA_ARG_A_MASK (0xf << 0) |
| # define RADEON_ALPHA_ARG_A_ZERO (0 << 0) |
| # define RADEON_ALPHA_ARG_A_CURRENT_ALPHA (1 << 0) |
| # define RADEON_ALPHA_ARG_A_DIFFUSE_ALPHA (2 << 0) |
| # define RADEON_ALPHA_ARG_A_SPECULAR_ALPHA (3 << 0) |
| # define RADEON_ALPHA_ARG_A_TFACTOR_ALPHA (4 << 0) |
| # define RADEON_ALPHA_ARG_A_T0_ALPHA (5 << 0) |
| # define RADEON_ALPHA_ARG_A_T1_ALPHA (6 << 0) |
| # define RADEON_ALPHA_ARG_A_T2_ALPHA (7 << 0) |
| # define RADEON_ALPHA_ARG_A_T3_ALPHA (8 << 0) |
| # define RADEON_ALPHA_ARG_B_SHIFT 4 |
| # define RADEON_ALPHA_ARG_B_MASK (0xf << 4) |
| # define RADEON_ALPHA_ARG_B_ZERO (0 << 4) |
| # define RADEON_ALPHA_ARG_B_CURRENT_ALPHA (1 << 4) |
| # define RADEON_ALPHA_ARG_B_DIFFUSE_ALPHA (2 << 4) |
| # define RADEON_ALPHA_ARG_B_SPECULAR_ALPHA (3 << 4) |
| # define RADEON_ALPHA_ARG_B_TFACTOR_ALPHA (4 << 4) |
| # define RADEON_ALPHA_ARG_B_T0_ALPHA (5 << 4) |
| # define RADEON_ALPHA_ARG_B_T1_ALPHA (6 << 4) |
| # define RADEON_ALPHA_ARG_B_T2_ALPHA (7 << 4) |
| # define RADEON_ALPHA_ARG_B_T3_ALPHA (8 << 4) |
| # define RADEON_ALPHA_ARG_C_SHIFT 8 |
| # define RADEON_ALPHA_ARG_C_MASK (0xf << 8) |
| # define RADEON_ALPHA_ARG_C_ZERO (0 << 8) |
| # define RADEON_ALPHA_ARG_C_CURRENT_ALPHA (1 << 8) |
| # define RADEON_ALPHA_ARG_C_DIFFUSE_ALPHA (2 << 8) |
| # define RADEON_ALPHA_ARG_C_SPECULAR_ALPHA (3 << 8) |
| # define RADEON_ALPHA_ARG_C_TFACTOR_ALPHA (4 << 8) |
| # define RADEON_ALPHA_ARG_C_T0_ALPHA (5 << 8) |
| # define RADEON_ALPHA_ARG_C_T1_ALPHA (6 << 8) |
| # define RADEON_ALPHA_ARG_C_T2_ALPHA (7 << 8) |
| # define RADEON_ALPHA_ARG_C_T3_ALPHA (8 << 8) |
| # define RADEON_DOT_ALPHA_DONT_REPLICATE (1 << 9) |
| # define RADEON_ALPHA_ARG_MASK 0xf |
| #define RADEON_PP_TFACTOR_0 0x1c68 |
| #define RADEON_PP_TFACTOR_1 0x1c80 |
| #define RADEON_PP_TFACTOR_2 0x1c98 |
| #define RADEON_RB3D_BLENDCNTL 0x1c20 |
| # define RADEON_COMB_FCN_MASK (3 << 12) |
| # define RADEON_COMB_FCN_ADD_CLAMP (0 << 12) |
| # define RADEON_COMB_FCN_ADD_NOCLAMP (1 << 12) |
| # define RADEON_COMB_FCN_SUB_CLAMP (2 << 12) |
| # define RADEON_COMB_FCN_SUB_NOCLAMP (3 << 12) |
| # define RADEON_SRC_BLEND_GL_ZERO (32 << 16) |
| # define RADEON_SRC_BLEND_GL_ONE (33 << 16) |
| # define RADEON_SRC_BLEND_GL_SRC_COLOR (34 << 16) |
| # define RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 16) |
| # define RADEON_SRC_BLEND_GL_DST_COLOR (36 << 16) |
| # define RADEON_SRC_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 16) |
| # define RADEON_SRC_BLEND_GL_SRC_ALPHA (38 << 16) |
| # define RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 16) |
| # define RADEON_SRC_BLEND_GL_DST_ALPHA (40 << 16) |
| # define RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 16) |
| # define RADEON_SRC_BLEND_GL_SRC_ALPHA_SATURATE (42 << 16) |
| # define RADEON_SRC_BLEND_MASK (63 << 16) |
| # define RADEON_DST_BLEND_GL_ZERO (32 << 24) |
| # define RADEON_DST_BLEND_GL_ONE (33 << 24) |
| # define RADEON_DST_BLEND_GL_SRC_COLOR (34 << 24) |
| # define RADEON_DST_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 24) |
| # define RADEON_DST_BLEND_GL_DST_COLOR (36 << 24) |
| # define RADEON_DST_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 24) |
| # define RADEON_DST_BLEND_GL_SRC_ALPHA (38 << 24) |
| # define RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 24) |
| # define RADEON_DST_BLEND_GL_DST_ALPHA (40 << 24) |
| # define RADEON_DST_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 24) |
| # define RADEON_DST_BLEND_MASK (63 << 24) |
| #define RADEON_RB3D_CNTL 0x1c3c |
| # define RADEON_ALPHA_BLEND_ENABLE (1 << 0) |
| # define RADEON_PLANE_MASK_ENABLE (1 << 1) |
| # define RADEON_DITHER_ENABLE (1 << 2) |
| # define RADEON_ROUND_ENABLE (1 << 3) |
| # define RADEON_SCALE_DITHER_ENABLE (1 << 4) |
| # define RADEON_DITHER_INIT (1 << 5) |
| # define RADEON_ROP_ENABLE (1 << 6) |
| # define RADEON_STENCIL_ENABLE (1 << 7) |
| # define RADEON_Z_ENABLE (1 << 8) |
| # define RADEON_DEPTH_XZ_OFFEST_ENABLE (1 << 9) |
| # define RADEON_RB3D_COLOR_FORMAT_SHIFT 10 |
| # define RADEON_COLOR_FORMAT_ARGB1555 3 |
| # define RADEON_COLOR_FORMAT_RGB565 4 |
| # define RADEON_COLOR_FORMAT_ARGB8888 6 |
| # define RADEON_COLOR_FORMAT_RGB332 7 |
| # define RADEON_COLOR_FORMAT_Y8 8 |
| # define RADEON_COLOR_FORMAT_RGB8 9 |
| # define RADEON_COLOR_FORMAT_YUV422_VYUY 11 |
| # define RADEON_COLOR_FORMAT_YUV422_YVYU 12 |
| # define RADEON_COLOR_FORMAT_aYUV444 14 |
| # define RADEON_COLOR_FORMAT_ARGB4444 15 |
| # define RADEON_CLRCMP_FLIP_ENABLE (1 << 14) |
| #define RADEON_RB3D_COLOROFFSET 0x1c40 |
| # define RADEON_COLOROFFSET_MASK 0xfffffff0 |
| #define RADEON_RB3D_COLORPITCH 0x1c48 |
| # define RADEON_COLORPITCH_MASK 0x000001ff8 |
| # define RADEON_COLOR_TILE_ENABLE (1 << 16) |
| # define RADEON_COLOR_MICROTILE_ENABLE (1 << 17) |
| # define RADEON_COLOR_ENDIAN_NO_SWAP (0 << 18) |
| # define RADEON_COLOR_ENDIAN_WORD_SWAP (1 << 18) |
| # define RADEON_COLOR_ENDIAN_DWORD_SWAP (2 << 18) |
| #define RADEON_RB3D_DEPTHOFFSET 0x1c24 |
| #define RADEON_RB3D_DEPTHPITCH 0x1c28 |
| # define RADEON_DEPTHPITCH_MASK 0x00001ff8 |
| # define RADEON_DEPTH_ENDIAN_NO_SWAP (0 << 18) |
| # define RADEON_DEPTH_ENDIAN_WORD_SWAP (1 << 18) |
| # define RADEON_DEPTH_ENDIAN_DWORD_SWAP (2 << 18) |
| #define RADEON_RB3D_PLANEMASK 0x1d84 |
| #define RADEON_RB3D_ROPCNTL 0x1d80 |
| # define RADEON_ROP_MASK (15 << 8) |
| # define RADEON_ROP_CLEAR (0 << 8) |
| # define RADEON_ROP_NOR (1 << 8) |
| # define RADEON_ROP_AND_INVERTED (2 << 8) |
| # define RADEON_ROP_COPY_INVERTED (3 << 8) |
| # define RADEON_ROP_AND_REVERSE (4 << 8) |
| # define RADEON_ROP_INVERT (5 << 8) |
| # define RADEON_ROP_XOR (6 << 8) |
| # define RADEON_ROP_NAND (7 << 8) |
| # define RADEON_ROP_AND (8 << 8) |
| # define RADEON_ROP_EQUIV (9 << 8) |
| # define RADEON_ROP_NOOP (10 << 8) |
| # define RADEON_ROP_OR_INVERTED (11 << 8) |
| # define RADEON_ROP_COPY (12 << 8) |
| # define RADEON_ROP_OR_REVERSE (13 << 8) |
| # define RADEON_ROP_OR (14 << 8) |
| # define RADEON_ROP_SET (15 << 8) |
| #define RADEON_RB3D_STENCILREFMASK 0x1d7c |
| # define RADEON_STENCIL_REF_SHIFT 0 |
| # define RADEON_STENCIL_REF_MASK (0xff << 0) |
| # define RADEON_STENCIL_MASK_SHIFT 16 |
| # define RADEON_STENCIL_VALUE_MASK (0xff << 16) |
| # define RADEON_STENCIL_WRITEMASK_SHIFT 24 |
| # define RADEON_STENCIL_WRITE_MASK (0xff << 24) |
| #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c |
| # define RADEON_DEPTH_FORMAT_MASK (0xf << 0) |
| # define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0) |
| # define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0) |
| # define RADEON_DEPTH_FORMAT_24BIT_FLOAT_Z (3 << 0) |
| # define RADEON_DEPTH_FORMAT_32BIT_INT_Z (4 << 0) |
| # define RADEON_DEPTH_FORMAT_32BIT_FLOAT_Z (5 << 0) |
| # define RADEON_DEPTH_FORMAT_16BIT_FLOAT_W (7 << 0) |
| # define RADEON_DEPTH_FORMAT_24BIT_FLOAT_W (9 << 0) |
| # define RADEON_DEPTH_FORMAT_32BIT_FLOAT_W (11 << 0) |
| # define RADEON_Z_TEST_NEVER (0 << 4) |
| # define RADEON_Z_TEST_LESS (1 << 4) |
| # define RADEON_Z_TEST_LEQUAL (2 << 4) |
| # define RADEON_Z_TEST_EQUAL (3 << 4) |
| # define RADEON_Z_TEST_GEQUAL (4 << 4) |
| # define RADEON_Z_TEST_GREATER (5 << 4) |
| # define RADEON_Z_TEST_NEQUAL (6 << 4) |
| # define RADEON_Z_TEST_ALWAYS (7 << 4) |
| # define RADEON_Z_TEST_MASK (7 << 4) |
| # define RADEON_STENCIL_TEST_NEVER (0 << 12) |
| # define RADEON_STENCIL_TEST_LESS (1 << 12) |
| # define RADEON_STENCIL_TEST_LEQUAL (2 << 12) |
| # define RADEON_STENCIL_TEST_EQUAL (3 << 12) |
| # define RADEON_STENCIL_TEST_GEQUAL (4 << 12) |
| # define RADEON_STENCIL_TEST_GREATER (5 << 12) |
| # define RADEON_STENCIL_TEST_NEQUAL (6 << 12) |
| # define RADEON_STENCIL_TEST_ALWAYS (7 << 12) |
| # define RADEON_STENCIL_TEST_MASK (0x7 << 12) |
| # define RADEON_STENCIL_FAIL_KEEP (0 << 16) |
| # define RADEON_STENCIL_FAIL_ZERO (1 << 16) |
| # define RADEON_STENCIL_FAIL_REPLACE (2 << 16) |
| # define RADEON_STENCIL_FAIL_INC (3 << 16) |
| # define RADEON_STENCIL_FAIL_DEC (4 << 16) |
| # define RADEON_STENCIL_FAIL_INVERT (5 << 16) |
| # define RADEON_STENCIL_FAIL_MASK (0x7 << 16) |
| # define RADEON_STENCIL_ZPASS_KEEP (0 << 20) |
| # define RADEON_STENCIL_ZPASS_ZERO (1 << 20) |
| # define RADEON_STENCIL_ZPASS_REPLACE (2 << 20) |
| # define RADEON_STENCIL_ZPASS_INC (3 << 20) |
| # define RADEON_STENCIL_ZPASS_DEC (4 << 20) |
| # define RADEON_STENCIL_ZPASS_INVERT (5 << 20) |
| # define RADEON_STENCIL_ZPASS_MASK (0x7 << 20) |
| # define RADEON_STENCIL_ZFAIL_KEEP (0 << 24) |
| # define RADEON_STENCIL_ZFAIL_ZERO (1 << 24) |
| # define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24) |
| # define RADEON_STENCIL_ZFAIL_INC (3 << 24) |
| # define RADEON_STENCIL_ZFAIL_DEC (4 << 24) |
| # define RADEON_STENCIL_ZFAIL_INVERT (5 << 24) |
| # define RADEON_STENCIL_ZFAIL_MASK (0x7 << 24) |
| # define RADEON_Z_COMPRESSION_ENABLE (1 << 28) |
| # define RADEON_FORCE_Z_DIRTY (1 << 29) |
| # define RADEON_Z_WRITE_ENABLE (1 << 30) |
| #define RADEON_RE_LINE_PATTERN 0x1cd0 |
| # define RADEON_LINE_PATTERN_MASK 0x0000ffff |
| # define RADEON_LINE_REPEAT_COUNT_SHIFT 16 |
| # define RADEON_LINE_PATTERN_START_SHIFT 24 |
| # define RADEON_LINE_PATTERN_LITTLE_BIT_ORDER (0 << 28) |
| # define RADEON_LINE_PATTERN_BIG_BIT_ORDER (1 << 28) |
| # define RADEON_LINE_PATTERN_AUTO_RESET (1 << 29) |
| #define RADEON_RE_LINE_STATE 0x1cd4 |
| # define RADEON_LINE_CURRENT_PTR_SHIFT 0 |
| # define RADEON_LINE_CURRENT_COUNT_SHIFT 8 |
| #define RADEON_RE_MISC 0x26c4 |
| # define RADEON_STIPPLE_COORD_MASK 0x1f |
| # define RADEON_STIPPLE_X_OFFSET_SHIFT 0 |
| # define RADEON_STIPPLE_X_OFFSET_MASK (0x1f << 0) |
| # define RADEON_STIPPLE_Y_OFFSET_SHIFT 8 |
| # define RADEON_STIPPLE_Y_OFFSET_MASK (0x1f << 8) |
| # define RADEON_STIPPLE_LITTLE_BIT_ORDER (0 << 16) |
| # define RADEON_STIPPLE_BIG_BIT_ORDER (1 << 16) |
| #define RADEON_RE_SOLID_COLOR 0x1c1c |
| #define RADEON_RE_TOP_LEFT 0x26c0 |
| # define RADEON_RE_LEFT_SHIFT 0 |
| # define RADEON_RE_TOP_SHIFT 16 |
| #define RADEON_RE_WIDTH_HEIGHT 0x1c44 |
| # define RADEON_RE_WIDTH_SHIFT 0 |
| # define RADEON_RE_HEIGHT_SHIFT 16 |
| #define RADEON_SE_CNTL 0x1c4c |
| # define RADEON_FFACE_CULL_CW (0 << 0) |
| # define RADEON_FFACE_CULL_CCW (1 << 0) |
| # define RADEON_FFACE_CULL_DIR_MASK (1 << 0) |
| # define RADEON_BFACE_CULL (0 << 1) |
| # define RADEON_BFACE_SOLID (3 << 1) |
| # define RADEON_FFACE_CULL (0 << 3) |
| # define RADEON_FFACE_SOLID (3 << 3) |
| # define RADEON_FFACE_CULL_MASK (3 << 3) |
| # define RADEON_BADVTX_CULL_DISABLE (1 << 5) |
| # define RADEON_FLAT_SHADE_VTX_0 (0 << 6) |
| # define RADEON_FLAT_SHADE_VTX_1 (1 << 6) |
| # define RADEON_FLAT_SHADE_VTX_2 (2 << 6) |
| # define RADEON_FLAT_SHADE_VTX_LAST (3 << 6) |
| # define RADEON_DIFFUSE_SHADE_SOLID (0 << 8) |
| # define RADEON_DIFFUSE_SHADE_FLAT (1 << 8) |
| # define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8) |
| # define RADEON_DIFFUSE_SHADE_MASK (3 << 8) |
| # define RADEON_ALPHA_SHADE_SOLID (0 << 10) |
| # define RADEON_ALPHA_SHADE_FLAT (1 << 10) |
| # define RADEON_ALPHA_SHADE_GOURAUD (2 << 10) |
| # define RADEON_ALPHA_SHADE_MASK (3 << 10) |
| # define RADEON_SPECULAR_SHADE_SOLID (0 << 12) |
| # define RADEON_SPECULAR_SHADE_FLAT (1 << 12) |
| # define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12) |
| # define RADEON_SPECULAR_SHADE_MASK (3 << 12) |
| # define RADEON_FOG_SHADE_SOLID (0 << 14) |
| # define RADEON_FOG_SHADE_FLAT (1 << 14) |
| # define RADEON_FOG_SHADE_GOURAUD (2 << 14) |
| # define RADEON_FOG_SHADE_MASK (3 << 14) |
| # define RADEON_ZBIAS_ENABLE_POINT (1 << 16) |
| # define RADEON_ZBIAS_ENABLE_LINE (1 << 17) |
| # define RADEON_ZBIAS_ENABLE_TRI (1 << 18) |
| # define RADEON_WIDELINE_ENABLE (1 << 20) |
| # define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24) |
| # define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25) |
| # define RADEON_VTX_PIX_CENTER_D3D (0 << 27) |
| # define RADEON_VTX_PIX_CENTER_OGL (1 << 27) |
| # define RADEON_ROUND_MODE_TRUNC (0 << 28) |
| # define RADEON_ROUND_MODE_ROUND (1 << 28) |
| # define RADEON_ROUND_MODE_ROUND_EVEN (2 << 28) |
| # define RADEON_ROUND_MODE_ROUND_ODD (3 << 28) |
| # define RADEON_ROUND_PREC_16TH_PIX (0 << 30) |
| # define RADEON_ROUND_PREC_8TH_PIX (1 << 30) |
| # define RADEON_ROUND_PREC_4TH_PIX (2 << 30) |
| # define RADEON_ROUND_PREC_HALF_PIX (3 << 30) |
| #define R200_RE_CNTL 0x1c50 |
| # define R200_STIPPLE_ENABLE 0x1 |
| # define R200_SCISSOR_ENABLE 0x2 |
| # define R200_PATTERN_ENABLE 0x4 |
| # define R200_PERSPECTIVE_ENABLE 0x8 |
| # define R200_POINT_SMOOTH 0x20 |
| # define R200_VTX_STQ0_D3D 0x00010000 |
| # define R200_VTX_STQ1_D3D 0x00040000 |
| # define R200_VTX_STQ2_D3D 0x00100000 |
| # define R200_VTX_STQ3_D3D 0x00400000 |
| # define R200_VTX_STQ4_D3D 0x01000000 |
| # define R200_VTX_STQ5_D3D 0x04000000 |
| #define RADEON_SE_CNTL_STATUS 0x2140 |
| # define RADEON_VC_NO_SWAP (0 << 0) |
| # define RADEON_VC_16BIT_SWAP (1 << 0) |
| # define RADEON_VC_32BIT_SWAP (2 << 0) |
| # define RADEON_VC_HALF_DWORD_SWAP (3 << 0) |
| # define RADEON_TCL_BYPASS (1 << 8) |
| #define RADEON_SE_COORD_FMT 0x1c50 |
| # define RADEON_VTX_XY_PRE_MULT_1_OVER_W0 (1 << 0) |
| # define RADEON_VTX_Z_PRE_MULT_1_OVER_W0 (1 << 1) |
| # define RADEON_VTX_ST0_NONPARAMETRIC (1 << 8) |
| # define RADEON_VTX_ST1_NONPARAMETRIC (1 << 9) |
| # define RADEON_VTX_ST2_NONPARAMETRIC (1 << 10) |
| # define RADEON_VTX_ST3_NONPARAMETRIC (1 << 11) |
| # define RADEON_VTX_W0_NORMALIZE (1 << 12) |
| # define RADEON_VTX_W0_IS_NOT_1_OVER_W0 (1 << 16) |
| # define RADEON_VTX_ST0_PRE_MULT_1_OVER_W0 (1 << 17) |
| # define RADEON_VTX_ST1_PRE_MULT_1_OVER_W0 (1 << 19) |
| # define RADEON_VTX_ST2_PRE_MULT_1_OVER_W0 (1 << 21) |
| # define RADEON_VTX_ST3_PRE_MULT_1_OVER_W0 (1 << 23) |
| # define RADEON_TEX1_W_ROUTING_USE_W0 (0 << 26) |
| # define RADEON_TEX1_W_ROUTING_USE_Q1 (1 << 26) |
| #define RADEON_SE_LINE_WIDTH 0x1db8 |
| #define RADEON_SE_TCL_LIGHT_MODEL_CTL 0x226c |
| # define RADEON_LIGHTING_ENABLE (1 << 0) |
| # define RADEON_LIGHT_IN_MODELSPACE (1 << 1) |
| # define RADEON_LOCAL_VIEWER (1 << 2) |
| # define RADEON_NORMALIZE_NORMALS (1 << 3) |
| # define RADEON_RESCALE_NORMALS (1 << 4) |
| # define RADEON_SPECULAR_LIGHTS (1 << 5) |
| # define RADEON_DIFFUSE_SPECULAR_COMBINE (1 << 6) |
| # define RADEON_LIGHT_ALPHA (1 << 7) |
| # define RADEON_LOCAL_LIGHT_VEC_GL (1 << 8) |
| # define RADEON_LIGHT_NO_NORMAL_AMBIENT_ONLY (1 << 9) |
| # define RADEON_LM_SOURCE_STATE_PREMULT 0 |
| # define RADEON_LM_SOURCE_STATE_MULT 1 |
| # define RADEON_LM_SOURCE_VERTEX_DIFFUSE 2 |
| # define RADEON_LM_SOURCE_VERTEX_SPECULAR 3 |
| # define RADEON_EMISSIVE_SOURCE_SHIFT 16 |
| # define RADEON_AMBIENT_SOURCE_SHIFT 18 |
| # define RADEON_DIFFUSE_SOURCE_SHIFT 20 |
| # define RADEON_SPECULAR_SOURCE_SHIFT 22 |
| #define RADEON_SE_TCL_MATERIAL_AMBIENT_RED 0x2220 |
| #define RADEON_SE_TCL_MATERIAL_AMBIENT_GREEN 0x2224 |
| #define RADEON_SE_TCL_MATERIAL_AMBIENT_BLUE 0x2228 |
| #define RADEON_SE_TCL_MATERIAL_AMBIENT_ALPHA 0x222c |
| #define RADEON_SE_TCL_MATERIAL_DIFFUSE_RED 0x2230 |
| #define RADEON_SE_TCL_MATERIAL_DIFFUSE_GREEN 0x2234 |
| #define RADEON_SE_TCL_MATERIAL_DIFFUSE_BLUE 0x2238 |
| #define RADEON_SE_TCL_MATERIAL_DIFFUSE_ALPHA 0x223c |
| #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210 |
| #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_GREEN 0x2214 |
| #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_BLUE 0x2218 |
| #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_ALPHA 0x221c |
| #define RADEON_SE_TCL_MATERIAL_SPECULAR_RED 0x2240 |
| #define RADEON_SE_TCL_MATERIAL_SPECULAR_GREEN 0x2244 |
| #define RADEON_SE_TCL_MATERIAL_SPECULAR_BLUE 0x2248 |
| #define RADEON_SE_TCL_MATERIAL_SPECULAR_ALPHA 0x224c |
| #define RADEON_SE_TCL_MATRIX_SELECT_0 0x225c |
| # define RADEON_MODELVIEW_0_SHIFT 0 |
| # define RADEON_MODELVIEW_1_SHIFT 4 |
| # define RADEON_MODELVIEW_2_SHIFT 8 |
| # define RADEON_MODELVIEW_3_SHIFT 12 |
| # define RADEON_IT_MODELVIEW_0_SHIFT 16 |
| # define RADEON_IT_MODELVIEW_1_SHIFT 20 |
| # define RADEON_IT_MODELVIEW_2_SHIFT 24 |
| # define RADEON_IT_MODELVIEW_3_SHIFT 28 |
| #define RADEON_SE_TCL_MATRIX_SELECT_1 0x2260 |
| # define RADEON_MODELPROJECT_0_SHIFT 0 |
| # define RADEON_MODELPROJECT_1_SHIFT 4 |
| # define RADEON_MODELPROJECT_2_SHIFT 8 |
| # define RADEON_MODELPROJECT_3_SHIFT 12 |
| # define RADEON_TEXMAT_0_SHIFT 16 |
| # define RADEON_TEXMAT_1_SHIFT 20 |
| # define RADEON_TEXMAT_2_SHIFT 24 |
| # define RADEON_TEXMAT_3_SHIFT 28 |
| #define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254 |
| # define RADEON_TCL_VTX_W0 (1 << 0) |
| # define RADEON_TCL_VTX_FP_DIFFUSE (1 << 1) |
| # define RADEON_TCL_VTX_FP_ALPHA (1 << 2) |
| # define RADEON_TCL_VTX_PK_DIFFUSE (1 << 3) |
| # define RADEON_TCL_VTX_FP_SPEC (1 << 4) |
| # define RADEON_TCL_VTX_FP_FOG (1 << 5) |
| # define RADEON_TCL_VTX_PK_SPEC (1 << 6) |
| # define RADEON_TCL_VTX_ST0 (1 << 7) |
| # define RADEON_TCL_VTX_ST1 (1 << 8) |
| # define RADEON_TCL_VTX_Q1 (1 << 9) |
| # define RADEON_TCL_VTX_ST2 (1 << 10) |
| # define RADEON_TCL_VTX_Q2 (1 << 11) |
| # define RADEON_TCL_VTX_ST3 (1 << 12) |
| # define RADEON_TCL_VTX_Q3 (1 << 13) |
| # define RADEON_TCL_VTX_Q0 (1 << 14) |
| # define RADEON_TCL_VTX_WEIGHT_COUNT_SHIFT 15 |
| # define RADEON_TCL_VTX_NORM0 (1 << 18) |
| # define RADEON_TCL_VTX_XY1 (1 << 27) |
| # define RADEON_TCL_VTX_Z1 (1 << 28) |
| # define RADEON_TCL_VTX_W1 (1 << 29) |
| # define RADEON_TCL_VTX_NORM1 (1 << 30) |
| # define RADEON_TCL_VTX_Z0 (1 << 31) |
| #define RADEON_SE_TCL_OUTPUT_VTX_SEL 0x2258 |
| # define RADEON_TCL_COMPUTE_XYZW (1 << 0) |
| # define RADEON_TCL_COMPUTE_DIFFUSE (1 << 1) |
| # define RADEON_TCL_COMPUTE_SPECULAR (1 << 2) |
| # define RADEON_TCL_FORCE_NAN_IF_COLOR_NAN (1 << 3) |
| # define RADEON_TCL_FORCE_INORDER_PROC (1 << 4) |
| # define RADEON_TCL_TEX_INPUT_TEX_0 0 |
| # define RADEON_TCL_TEX_INPUT_TEX_1 1 |
| # define RADEON_TCL_TEX_INPUT_TEX_2 2 |
| # define RADEON_TCL_TEX_INPUT_TEX_3 3 |
| # define RADEON_TCL_TEX_COMPUTED_TEX_0 8 |
| # define RADEON_TCL_TEX_COMPUTED_TEX_1 9 |
| # define RADEON_TCL_TEX_COMPUTED_TEX_2 10 |
| # define RADEON_TCL_TEX_COMPUTED_TEX_3 11 |
| # define RADEON_TCL_TEX_0_OUTPUT_SHIFT 16 |
| # define RADEON_TCL_TEX_1_OUTPUT_SHIFT 20 |
| # define RADEON_TCL_TEX_2_OUTPUT_SHIFT 24 |
| # define RADEON_TCL_TEX_3_OUTPUT_SHIFT 28 |
| #define RADEON_SE_TCL_PER_LIGHT_CTL_0 0x2270 |
| # define RADEON_LIGHT_0_ENABLE (1 << 0) |
| # define RADEON_LIGHT_0_ENABLE_AMBIENT (1 << 1) |
| # define RADEON_LIGHT_0_ENABLE_SPECULAR (1 << 2) |
| # define RADEON_LIGHT_0_IS_LOCAL (1 << 3) |
| # define RADEON_LIGHT_0_IS_SPOT (1 << 4) |
| # define RADEON_LIGHT_0_DUAL_CONE (1 << 5) |
| # define RADEON_LIGHT_0_ENABLE_RANGE_ATTEN (1 << 6) |
| # define RADEON_LIGHT_0_CONSTANT_RANGE_ATTEN (1 << 7) |
| # define RADEON_LIGHT_0_SHIFT 0 |
| # define RADEON_LIGHT_1_ENABLE (1 << 16) |
| # define RADEON_LIGHT_1_ENABLE_AMBIENT (1 << 17) |
| # define RADEON_LIGHT_1_ENABLE_SPECULAR (1 << 18) |
| # define RADEON_LIGHT_1_IS_LOCAL (1 << 19) |
| # define RADEON_LIGHT_1_IS_SPOT (1 << 20) |
| # define RADEON_LIGHT_1_DUAL_CONE (1 << 21) |
| # define RADEON_LIGHT_1_ENABLE_RANGE_ATTEN (1 << 22) |
| # define RADEON_LIGHT_1_CONSTANT_RANGE_ATTEN (1 << 23) |
| # define RADEON_LIGHT_1_SHIFT 16 |
| #define RADEON_SE_TCL_PER_LIGHT_CTL_1 0x2274 |
| # define RADEON_LIGHT_2_SHIFT 0 |
| # define RADEON_LIGHT_3_SHIFT 16 |
| #define RADEON_SE_TCL_PER_LIGHT_CTL_2 0x2278 |
| # define RADEON_LIGHT_4_SHIFT 0 |
| # define RADEON_LIGHT_5_SHIFT 16 |
| #define RADEON_SE_TCL_PER_LIGHT_CTL_3 0x227c |
| # define RADEON_LIGHT_6_SHIFT 0 |
| # define RADEON_LIGHT_7_SHIFT 16 |
| #define RADEON_SE_TCL_SHININESS 0x2250 |
| #define RADEON_SE_TCL_TEXTURE_PROC_CTL 0x2268 |
| # define RADEON_TEXGEN_TEXMAT_0_ENABLE (1 << 0) |
| # define RADEON_TEXGEN_TEXMAT_1_ENABLE (1 << 1) |
| # define RADEON_TEXGEN_TEXMAT_2_ENABLE (1 << 2) |
| # define RADEON_TEXGEN_TEXMAT_3_ENABLE (1 << 3) |
| # define RADEON_TEXMAT_0_ENABLE (1 << 4) |
| # define RADEON_TEXMAT_1_ENABLE (1 << 5) |
| # define RADEON_TEXMAT_2_ENABLE (1 << 6) |
| # define RADEON_TEXMAT_3_ENABLE (1 << 7) |
| # define RADEON_TEXGEN_INPUT_MASK 0xf |
| # define RADEON_TEXGEN_INPUT_TEXCOORD_0 0 |
| # define RADEON_TEXGEN_INPUT_TEXCOORD_1 1 |
| # define RADEON_TEXGEN_INPUT_TEXCOORD_2 2 |
| # define RADEON_TEXGEN_INPUT_TEXCOORD_3 3 |
| # define RADEON_TEXGEN_INPUT_OBJ 4 |
| # define RADEON_TEXGEN_INPUT_EYE 5 |
| # define RADEON_TEXGEN_INPUT_EYE_NORMAL 6 |
| # define RADEON_TEXGEN_INPUT_EYE_REFLECT 7 |
| # define RADEON_TEXGEN_INPUT_EYE_NORMALIZED 8 |
| # define RADEON_TEXGEN_0_INPUT_SHIFT 16 |
| # define RADEON_TEXGEN_1_INPUT_SHIFT 20 |
| # define RADEON_TEXGEN_2_INPUT_SHIFT 24 |
| # define RADEON_TEXGEN_3_INPUT_SHIFT 28 |
| #define RADEON_SE_TCL_UCP_VERT_BLEND_CTL 0x2264 |
| # define RADEON_UCP_IN_CLIP_SPACE (1 << 0) |
| # define RADEON_UCP_IN_MODEL_SPACE (1 << 1) |
| # define RADEON_UCP_ENABLE_0 (1 << 2) |
| # define RADEON_UCP_ENABLE_1 (1 << 3) |
| # define RADEON_UCP_ENABLE_2 (1 << 4) |
| # define RADEON_UCP_ENABLE_3 (1 << 5) |
| # define RADEON_UCP_ENABLE_4 (1 << 6) |
| # define RADEON_UCP_ENABLE_5 (1 << 7) |
| # define RADEON_TCL_FOG_MASK (3 << 8) |
| # define RADEON_TCL_FOG_DISABLE (0 << 8) |
| # define RADEON_TCL_FOG_EXP (1 << 8) |
| # define RADEON_TCL_FOG_EXP2 (2 << 8) |
| # define RADEON_TCL_FOG_LINEAR (3 << 8) |
| # define RADEON_RNG_BASED_FOG (1 << 10) |
| # define RADEON_LIGHT_TWOSIDE (1 << 11) |
| # define RADEON_BLEND_OP_COUNT_MASK (7 << 12) |
| # define RADEON_BLEND_OP_COUNT_SHIFT 12 |
| # define RADEON_POSITION_BLEND_OP_ENABLE (1 << 16) |
| # define RADEON_NORMAL_BLEND_OP_ENABLE (1 << 17) |
| # define RADEON_VERTEX_BLEND_SRC_0_PRIMARY (1 << 18) |
| # define RADEON_VERTEX_BLEND_SRC_0_SECONDARY (1 << 18) |
| # define RADEON_VERTEX_BLEND_SRC_1_PRIMARY (1 << 19) |
| # define RADEON_VERTEX_BLEND_SRC_1_SECONDARY (1 << 19) |
| # define RADEON_VERTEX_BLEND_SRC_2_PRIMARY (1 << 20) |
| # define RADEON_VERTEX_BLEND_SRC_2_SECONDARY (1 << 20) |
| # define RADEON_VERTEX_BLEND_SRC_3_PRIMARY (1 << 21) |
| # define RADEON_VERTEX_BLEND_SRC_3_SECONDARY (1 << 21) |
| # define RADEON_VERTEX_BLEND_WGT_MINUS_ONE (1 << 22) |
| # define RADEON_CULL_FRONT_IS_CW (0 << 28) |
| # define RADEON_CULL_FRONT_IS_CCW (1 << 28) |
| # define RADEON_CULL_FRONT (1 << 29) |
| # define RADEON_CULL_BACK (1 << 30) |
| # define RADEON_FORCE_W_TO_ONE (1 << 31) |
| #define RADEON_SE_VPORT_XSCALE 0x1d98 |
| #define RADEON_SE_VPORT_XOFFSET 0x1d9c |
| #define RADEON_SE_VPORT_YSCALE 0x1da0 |
| #define RADEON_SE_VPORT_YOFFSET 0x1da4 |
| #define RADEON_SE_VPORT_ZSCALE 0x1da8 |
| #define RADEON_SE_VPORT_ZOFFSET 0x1dac |
| #define RADEON_SE_ZBIAS_FACTOR 0x1db0 |
| #define RADEON_SE_ZBIAS_CONSTANT 0x1db4 |
| #define RADEON_SE_VTX_FMT 0x2080 |
| # define RADEON_SE_VTX_FMT_XY 0x00000000 |
| # define RADEON_SE_VTX_FMT_W0 0x00000001 |
| # define RADEON_SE_VTX_FMT_FPCOLOR 0x00000002 |
| # define RADEON_SE_VTX_FMT_FPALPHA 0x00000004 |
| # define RADEON_SE_VTX_FMT_PKCOLOR 0x00000008 |
| # define RADEON_SE_VTX_FMT_FPSPEC 0x00000010 |
| # define RADEON_SE_VTX_FMT_FPFOG 0x00000020 |
| # define RADEON_SE_VTX_FMT_PKSPEC 0x00000040 |
| # define RADEON_SE_VTX_FMT_ST0 0x00000080 |
| # define RADEON_SE_VTX_FMT_ST1 0x00000100 |
| # define RADEON_SE_VTX_FMT_Q1 0x00000200 |
| # define RADEON_SE_VTX_FMT_ST2 0x00000400 |
| # define RADEON_SE_VTX_FMT_Q2 0x00000800 |
| # define RADEON_SE_VTX_FMT_ST3 0x00001000 |
| # define RADEON_SE_VTX_FMT_Q3 0x00002000 |
| # define RADEON_SE_VTX_FMT_Q0 0x00004000 |
| # define RADEON_SE_VTX_FMT_BLND_WEIGHT_CNT_MASK 0x00038000 |
| # define RADEON_SE_VTX_FMT_N0 0x00040000 |
| # define RADEON_SE_VTX_FMT_XY1 0x08000000 |
| # define RADEON_SE_VTX_FMT_Z1 0x10000000 |
| # define RADEON_SE_VTX_FMT_W1 0x20000000 |
| # define RADEON_SE_VTX_FMT_N1 0x40000000 |
| # define RADEON_SE_VTX_FMT_Z 0x80000000 |
| #define RADEON_SE_VF_CNTL 0x2084 |
| # define RADEON_VF_PRIM_TYPE_POINT_LIST 1 |
| # define RADEON_VF_PRIM_TYPE_LINE_LIST 2 |
| # define RADEON_VF_PRIM_TYPE_LINE_STRIP 3 |
| # define RADEON_VF_PRIM_TYPE_TRIANGLE_LIST 4 |
| # define RADEON_VF_PRIM_TYPE_TRIANGLE_FAN 5 |
| # define RADEON_VF_PRIM_TYPE_TRIANGLE_STRIP 6 |
| # define RADEON_VF_PRIM_TYPE_TRIANGLE_FLAG 7 |
| # define RADEON_VF_PRIM_TYPE_RECTANGLE_LIST 8 |
| # define RADEON_VF_PRIM_TYPE_POINT_LIST_3 9 |
| # define RADEON_VF_PRIM_TYPE_LINE_LIST_3 10 |
| # define RADEON_VF_PRIM_TYPE_SPIRIT_LIST 11 |
| # define RADEON_VF_PRIM_TYPE_LINE_LOOP 12 |
| # define RADEON_VF_PRIM_TYPE_QUAD_LIST 13 |
| # define RADEON_VF_PRIM_TYPE_QUAD_STRIP 14 |
| # define RADEON_VF_PRIM_TYPE_POLYGON 15 |
| # define RADEON_VF_PRIM_WALK_STATE (0<<4) |
| # define RADEON_VF_PRIM_WALK_INDEX (1<<4) |
| # define RADEON_VF_PRIM_WALK_LIST (2<<4) |
| # define RADEON_VF_PRIM_WALK_DATA (3<<4) |
| # define RADEON_VF_COLOR_ORDER_RGBA (1<<6) |
| # define RADEON_VF_RADEON_MODE (1<<8) |
| # define RADEON_VF_TCL_OUTPUT_CTL_ENA (1<<9) |
| # define RADEON_VF_PROG_STREAM_ENA (1<<10) |
| # define RADEON_VF_INDEX_SIZE_SHIFT 11 |
| # define RADEON_VF_NUM_VERTICES_SHIFT 16 |
| #define RADEON_SE_PORT_DATA0 0x2000 |
| #define R200_SE_VAP_CNTL 0x2080 |
| # define R200_VAP_TCL_ENABLE 0x00000001 |
| # define R200_VAP_SINGLE_BUF_STATE_ENABLE 0x00000010 |
| # define R200_VAP_FORCE_W_TO_ONE 0x00010000 |
| # define R200_VAP_D3D_TEX_DEFAULT 0x00020000 |
| # define R200_VAP_VF_MAX_VTX_NUM__SHIFT 18 |
| # define R200_VAP_VF_MAX_VTX_NUM (9 << 18) |
| # define R200_VAP_DX_CLIP_SPACE_DEF 0x00400000 |
| #define R200_VF_MAX_VTX_INDX 0x210c |
| #define R200_VF_MIN_VTX_INDX 0x2110 |
| #define R200_SE_VTE_CNTL 0x20b0 |
| # define R200_VPORT_X_SCALE_ENA 0x00000001 |
| # define R200_VPORT_X_OFFSET_ENA 0x00000002 |
| # define R200_VPORT_Y_SCALE_ENA 0x00000004 |
| # define R200_VPORT_Y_OFFSET_ENA 0x00000008 |
| # define R200_VPORT_Z_SCALE_ENA 0x00000010 |
| # define R200_VPORT_Z_OFFSET_ENA 0x00000020 |
| # define R200_VTX_XY_FMT 0x00000100 |
| # define R200_VTX_Z_FMT 0x00000200 |
| # define R200_VTX_W0_FMT 0x00000400 |
| # define R200_VTX_W0_NORMALIZE 0x00000800 |
| # define R200_VTX_ST_DENORMALIZED 0x00001000 |
| #define R200_SE_VAP_CNTL_STATUS 0x2140 |
| # define R200_VC_NO_SWAP (0 << 0) |
| # define R200_VC_16BIT_SWAP (1 << 0) |
| # define R200_VC_32BIT_SWAP (2 << 0) |
| #define R200_PP_TXFILTER_0 0x2c00 |
| #define R200_PP_TXFILTER_1 0x2c20 |
| #define R200_PP_TXFILTER_2 0x2c40 |
| #define R200_PP_TXFILTER_3 0x2c60 |
| #define R200_PP_TXFILTER_4 0x2c80 |
| #define R200_PP_TXFILTER_5 0x2ca0 |
| # define R200_MAG_FILTER_NEAREST (0 << 0) |
| # define R200_MAG_FILTER_LINEAR (1 << 0) |
| # define R200_MAG_FILTER_MASK (1 << 0) |
| # define R200_MIN_FILTER_NEAREST (0 << 1) |
| # define R200_MIN_FILTER_LINEAR (1 << 1) |
| # define R200_MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1) |
| # define R200_MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1) |
| # define R200_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1) |
| # define R200_MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1) |
| # define R200_MIN_FILTER_ANISO_NEAREST (8 << 1) |
| # define R200_MIN_FILTER_ANISO_LINEAR (9 << 1) |
| # define R200_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1) |
| # define R200_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1) |
| # define R200_MIN_FILTER_MASK (15 << 1) |
| # define R200_MAX_ANISO_1_TO_1 (0 << 5) |
| # define R200_MAX_ANISO_2_TO_1 (1 << 5) |
| # define R200_MAX_ANISO_4_TO_1 (2 << 5) |
| # define R200_MAX_ANISO_8_TO_1 (3 << 5) |
| # define R200_MAX_ANISO_16_TO_1 (4 << 5) |
| # define R200_MAX_ANISO_MASK (7 << 5) |
| # define R200_MAX_MIP_LEVEL_MASK (0x0f << 16) |
| # define R200_MAX_MIP_LEVEL_SHIFT 16 |
| # define R200_YUV_TO_RGB (1 << 20) |
| # define R200_YUV_TEMPERATURE_COOL (0 << 21) |
| # define R200_YUV_TEMPERATURE_HOT (1 << 21) |
| # define R200_YUV_TEMPERATURE_MASK (1 << 21) |
| # define R200_WRAPEN_S (1 << 22) |
| # define R200_CLAMP_S_WRAP (0 << 23) |
| # define R200_CLAMP_S_MIRROR (1 << 23) |
| # define R200_CLAMP_S_CLAMP_LAST (2 << 23) |
| # define R200_CLAMP_S_MIRROR_CLAMP_LAST (3 << 23) |
| # define R200_CLAMP_S_CLAMP_BORDER (4 << 23) |
| # define R200_CLAMP_S_MIRROR_CLAMP_BORDER (5 << 23) |
| # define R200_CLAMP_S_CLAMP_GL (6 << 23) |
| # define R200_CLAMP_S_MIRROR_CLAMP_GL (7 << 23) |
| # define R200_CLAMP_S_MASK (7 << 23) |
| # define R200_WRAPEN_T (1 << 26) |
| # define R200_CLAMP_T_WRAP (0 << 27) |
| # define R200_CLAMP_T_MIRROR (1 << 27) |
| # define R200_CLAMP_T_CLAMP_LAST (2 << 27) |
| # define R200_CLAMP_T_MIRROR_CLAMP_LAST (3 << 27) |
| # define R200_CLAMP_T_CLAMP_BORDER (4 << 27) |
| # define R200_CLAMP_T_MIRROR_CLAMP_BORDER (5 << 27) |
| # define R200_CLAMP_T_CLAMP_GL (6 << 27) |
| # define R200_CLAMP_T_MIRROR_CLAMP_GL (7 << 27) |
| # define R200_CLAMP_T_MASK (7 << 27) |
| # define R200_KILL_LT_ZERO (1 << 30) |
| # define R200_BORDER_MODE_OGL (0 << 31) |
| # define R200_BORDER_MODE_D3D (1 << 31) |
| #define R200_PP_TXFORMAT_0 0x2c04 |
| #define R200_PP_TXFORMAT_1 0x2c24 |
| #define R200_PP_TXFORMAT_2 0x2c44 |
| #define R200_PP_TXFORMAT_3 0x2c64 |
| #define R200_PP_TXFORMAT_4 0x2c84 |
| #define R200_PP_TXFORMAT_5 0x2ca4 |
| # define R200_TXFORMAT_I8 (0 << 0) |
| # define R200_TXFORMAT_AI88 (1 << 0) |
| # define R200_TXFORMAT_RGB332 (2 << 0) |
| # define R200_TXFORMAT_ARGB1555 (3 << 0) |
| # define R200_TXFORMAT_RGB565 (4 << 0) |
| # define R200_TXFORMAT_ARGB4444 (5 << 0) |
| # define R200_TXFORMAT_ARGB8888 (6 << 0) |
| # define R200_TXFORMAT_RGBA8888 (7 << 0) |
| # define R200_TXFORMAT_Y8 (8 << 0) |
| # define R200_TXFORMAT_AVYU4444 (9 << 0) |
| # define R200_TXFORMAT_VYUY422 (10 << 0) |
| # define R200_TXFORMAT_YVYU422 (11 << 0) |
| # define R200_TXFORMAT_DXT1 (12 << 0) |
| # define R200_TXFORMAT_DXT23 (14 << 0) |
| # define R200_TXFORMAT_DXT45 (15 << 0) |
| # define R200_TXFORMAT_ABGR8888 (22 << 0) |
| # define R200_TXFORMAT_FORMAT_MASK (31 << 0) |
| # define R200_TXFORMAT_FORMAT_SHIFT 0 |
| # define R200_TXFORMAT_ALPHA_IN_MAP (1 << 6) |
| # define R200_TXFORMAT_NON_POWER2 (1 << 7) |
| # define R200_TXFORMAT_WIDTH_MASK (15 << 8) |
| # define R200_TXFORMAT_WIDTH_SHIFT 8 |
| # define R200_TXFORMAT_HEIGHT_MASK (15 << 12) |
| # define R200_TXFORMAT_HEIGHT_SHIFT 12 |
| # define R200_TXFORMAT_F5_WIDTH_MASK (15 << 16) /* cube face 5 */ |
| # define R200_TXFORMAT_F5_WIDTH_SHIFT 16 |
| # define R200_TXFORMAT_F5_HEIGHT_MASK (15 << 20) |
| # define R200_TXFORMAT_F5_HEIGHT_SHIFT 20 |
| # define R200_TXFORMAT_ST_ROUTE_STQ0 (0 << 24) |
| # define R200_TXFORMAT_ST_ROUTE_STQ1 (1 << 24) |
| # define R200_TXFORMAT_ST_ROUTE_STQ2 (2 << 24) |
| # define R200_TXFORMAT_ST_ROUTE_STQ3 (3 << 24) |
| # define R200_TXFORMAT_ST_ROUTE_STQ4 (4 << 24) |
| # define R200_TXFORMAT_ST_ROUTE_STQ5 (5 << 24) |
| # define R200_TXFORMAT_ST_ROUTE_MASK (7 << 24) |
| # define R200_TXFORMAT_ST_ROUTE_SHIFT 24 |
| # define R200_TXFORMAT_ALPHA_MASK_ENABLE (1 << 28) |
| # define R200_TXFORMAT_CHROMA_KEY_ENABLE (1 << 29) |
| # define R200_TXFORMAT_CUBIC_MAP_ENABLE (1 << 30) |
| #define R200_PP_TXFORMAT_X_0 0x2c08 |
| #define R200_PP_TXFORMAT_X_1 0x2c28 |
| #define R200_PP_TXFORMAT_X_2 0x2c48 |
| #define R200_PP_TXFORMAT_X_3 0x2c68 |
| #define R200_PP_TXFORMAT_X_4 0x2c88 |
| #define R200_PP_TXFORMAT_X_5 0x2ca8 |
| #define R200_PP_TXSIZE_0 0x2c0c /* NPOT only */ |
| #define R200_PP_TXSIZE_1 0x2c2c /* NPOT only */ |
| #define R200_PP_TXSIZE_2 0x2c4c /* NPOT only */ |
| #define R200_PP_TXSIZE_3 0x2c6c /* NPOT only */ |
| #define R200_PP_TXSIZE_4 0x2c8c /* NPOT only */ |
| #define R200_PP_TXSIZE_5 0x2cac /* NPOT only */ |
| #define R200_PP_TXPITCH_0 0x2c10 /* NPOT only */ |
| #define R200_PP_TXPITCH_1 0x2c30 /* NPOT only */ |
| #define R200_PP_TXPITCH_2 0x2c50 /* NPOT only */ |
| #define R200_PP_TXPITCH_3 0x2c70 /* NPOT only */ |
| #define R200_PP_TXPITCH_4 0x2c90 /* NPOT only */ |
| #define R200_PP_TXPITCH_5 0x2cb0 /* NPOT only */ |
| #define R200_PP_TXOFFSET_0 0x2d00 |
| # define R200_TXO_ENDIAN_NO_SWAP (0 << 0) |
| # define R200_TXO_ENDIAN_BYTE_SWAP (1 << 0) |
| # define R200_TXO_ENDIAN_WORD_SWAP (2 << 0) |
| # define R200_TXO_ENDIAN_HALFDW_SWAP (3 << 0) |
| # define R200_TXO_MACRO_LINEAR (0 << 2) |
| # define R200_TXO_MACRO_TILE (1 << 2) |
| # define R200_TXO_MICRO_LINEAR (0 << 3) |
| # define R200_TXO_MICRO_TILE (1 << 3) |
| # define R200_TXO_OFFSET_MASK 0xffffffe0 |
| # define R200_TXO_OFFSET_SHIFT 5 |
| #define R200_PP_TXOFFSET_1 0x2d18 |
| #define R200_PP_TXOFFSET_2 0x2d30 |
| #define R200_PP_TXOFFSET_3 0x2d48 |
| #define R200_PP_TXOFFSET_4 0x2d60 |
| #define R200_PP_TXOFFSET_5 0x2d78 |
| #define R200_PP_TFACTOR_0 0x2ee0 |
| #define R200_PP_TFACTOR_1 0x2ee4 |
| #define R200_PP_TFACTOR_2 0x2ee8 |
| #define R200_PP_TFACTOR_3 0x2eec |
| #define R200_PP_TFACTOR_4 0x2ef0 |
| #define R200_PP_TFACTOR_5 0x2ef4 |
| #define R200_PP_TXCBLEND_0 0x2f00 |
| # define R200_TXC_ARG_A_ZERO (0) |
| # define R200_TXC_ARG_A_CURRENT_COLOR (2) |
| # define R200_TXC_ARG_A_CURRENT_ALPHA (3) |
| # define R200_TXC_ARG_A_DIFFUSE_COLOR (4) |
| # define R200_TXC_ARG_A_DIFFUSE_ALPHA (5) |
| # define R200_TXC_ARG_A_SPECULAR_COLOR (6) |
| # define R200_TXC_ARG_A_SPECULAR_ALPHA (7) |
| # define R200_TXC_ARG_A_TFACTOR_COLOR (8) |
| # define R200_TXC_ARG_A_TFACTOR_ALPHA (9) |
| # define R200_TXC_ARG_A_R0_COLOR (10) |
| # define R200_TXC_ARG_A_R0_ALPHA (11) |
| # define R200_TXC_ARG_A_R1_COLOR (12) |
| # define R200_TXC_ARG_A_R1_ALPHA (13) |
| # define R200_TXC_ARG_A_R2_COLOR (14) |
| # define R200_TXC_ARG_A_R2_ALPHA (15) |
| # define R200_TXC_ARG_A_R3_COLOR (16) |
| # define R200_TXC_ARG_A_R3_ALPHA (17) |
| # define R200_TXC_ARG_A_R4_COLOR (18) |
| # define R200_TXC_ARG_A_R4_ALPHA (19) |
| # define R200_TXC_ARG_A_R5_COLOR (20) |
| # define R200_TXC_ARG_A_R5_ALPHA (21) |
| # define R200_TXC_ARG_A_TFACTOR1_COLOR (26) |
| # define R200_TXC_ARG_A_TFACTOR1_ALPHA (27) |
| # define R200_TXC_ARG_A_MASK (31 << 0) |
| # define R200_TXC_ARG_A_SHIFT 0 |
| # define R200_TXC_ARG_B_ZERO (0 << 5) |
| # define R200_TXC_ARG_B_CURRENT_COLOR (2 << 5) |
| # define R200_TXC_ARG_B_CURRENT_ALPHA (3 << 5) |
| # define R200_TXC_ARG_B_DIFFUSE_COLOR (4 << 5) |
| # define R200_TXC_ARG_B_DIFFUSE_ALPHA (5 << 5) |
| # define R200_TXC_ARG_B_SPECULAR_COLOR (6 << 5) |
| # define R200_TXC_ARG_B_SPECULAR_ALPHA (7 << 5) |
| # define R200_TXC_ARG_B_TFACTOR_COLOR (8 << 5) |
| # define R200_TXC_ARG_B_TFACTOR_ALPHA (9 << 5) |
| # define R200_TXC_ARG_B_R0_COLOR (10 << 5) |
| # define R200_TXC_ARG_B_R0_ALPHA (11 << 5) |
| # define R200_TXC_ARG_B_R1_COLOR (12 << 5) |
| # define R200_TXC_ARG_B_R1_ALPHA (13 << 5) |
| # define R200_TXC_ARG_B_R2_COLOR (14 << 5) |
| # define R200_TXC_ARG_B_R2_ALPHA (15 << 5) |
| # define R200_TXC_ARG_B_R3_COLOR (16 << 5) |
| # define R200_TXC_ARG_B_R3_ALPHA (17 << 5) |
| # define R200_TXC_ARG_B_R4_COLOR (18 << 5) |
| # define R200_TXC_ARG_B_R4_ALPHA (19 << 5) |
| # define R200_TXC_ARG_B_R5_COLOR (20 << 5) |
| # define R200_TXC_ARG_B_R5_ALPHA (21 << 5) |
| # define R200_TXC_ARG_B_TFACTOR1_COLOR (26 << 5) |
| # define R200_TXC_ARG_B_TFACTOR1_ALPHA (27 << 5) |
| # define R200_TXC_ARG_B_MASK (31 << 5) |
| # define R200_TXC_ARG_B_SHIFT 5 |
| # define R200_TXC_ARG_C_ZERO (0 << 10) |
| # define R200_TXC_ARG_C_CURRENT_COLOR (2 << 10) |
| # define R200_TXC_ARG_C_CURRENT_ALPHA (3 << 10) |
| # define R200_TXC_ARG_C_DIFFUSE_COLOR (4 << 10) |
| # define R200_TXC_ARG_C_DIFFUSE_ALPHA (5 << 10) |
| # define R200_TXC_ARG_C_SPECULAR_COLOR (6 << 10) |
| # define R200_TXC_ARG_C_SPECULAR_ALPHA (7 << 10) |
| # define R200_TXC_ARG_C_TFACTOR_COLOR (8 << 10) |
| # define R200_TXC_ARG_C_TFACTOR_ALPHA (9 << 10) |
| # define R200_TXC_ARG_C_R0_COLOR (10 << 10) |
| # define R200_TXC_ARG_C_R0_ALPHA (11 << 10) |
| # define R200_TXC_ARG_C_R1_COLOR (12 << 10) |
| # define R200_TXC_ARG_C_R1_ALPHA (13 << 10) |
| # define R200_TXC_ARG_C_R2_COLOR (14 << 10) |
| # define R200_TXC_ARG_C_R2_ALPHA (15 << 10) |
| # define R200_TXC_ARG_C_R3_COLOR (16 << 10) |
| # define R200_TXC_ARG_C_R3_ALPHA (17 << 10) |
| # define R200_TXC_ARG_C_R4_COLOR (18 << 10) |
| # define R200_TXC_ARG_C_R4_ALPHA (19 << 10) |
| # define R200_TXC_ARG_C_R5_COLOR (20 << 10) |
| # define R200_TXC_ARG_C_R5_ALPHA (21 << 10) |
| # define R200_TXC_ARG_C_TFACTOR1_COLOR (26 << 10) |
| # define R200_TXC_ARG_C_TFACTOR1_ALPHA (27 << 10) |
| # define R200_TXC_ARG_C_MASK (31 << 10) |
| # define R200_TXC_ARG_C_SHIFT 10 |
| # define R200_TXC_COMP_ARG_A (1 << 16) |
| # define R200_TXC_COMP_ARG_A_SHIFT (16) |
| # define R200_TXC_BIAS_ARG_A (1 << 17) |
| # define R200_TXC_SCALE_ARG_A (1 << 18) |
| # define R200_TXC_NEG_ARG_A (1 << 19) |
| # define R200_TXC_COMP_ARG_B (1 << 20) |
| # define R200_TXC_COMP_ARG_B_SHIFT (20) |
| # define R200_TXC_BIAS_ARG_B (1 << 21) |
| # define R200_TXC_SCALE_ARG_B (1 << 22) |
| # define R200_TXC_NEG_ARG_B (1 << 23) |
| # define R200_TXC_COMP_ARG_C (1 << 24) |
| # define R200_TXC_COMP_ARG_C_SHIFT (24) |
| # define R200_TXC_BIAS_ARG_C (1 << 25) |
| # define R200_TXC_SCALE_ARG_C (1 << 26) |
| # define R200_TXC_NEG_ARG_C (1 << 27) |
| # define R200_TXC_OP_MADD (0 << 28) |
| # define R200_TXC_OP_CND0 (2 << 28) |
| # define R200_TXC_OP_LERP (3 << 28) |
| # define R200_TXC_OP_DOT3 (4 << 28) |
| # define R200_TXC_OP_DOT4 (5 << 28) |
| # define R200_TXC_OP_CONDITIONAL (6 << 28) |
| # define R200_TXC_OP_DOT2_ADD (7 << 28) |
| # define R200_TXC_OP_MASK (7 << 28) |
| #define R200_PP_TXCBLEND2_0 0x2f04 |
| # define R200_TXC_TFACTOR_SEL_SHIFT 0 |
| # define R200_TXC_TFACTOR_SEL_MASK 0x7 |
| # define R200_TXC_TFACTOR1_SEL_SHIFT 4 |
| # define R200_TXC_TFACTOR1_SEL_MASK (0x7 << 4) |
| # define R200_TXC_SCALE_SHIFT 8 |
| # define R200_TXC_SCALE_MASK (7 << 8) |
| # define R200_TXC_SCALE_1X (0 << 8) |
| # define R200_TXC_SCALE_2X (1 << 8) |
| # define R200_TXC_SCALE_4X (2 << 8) |
| # define R200_TXC_SCALE_8X (3 << 8) |
| # define R200_TXC_SCALE_INV2 (5 << 8) |
| # define R200_TXC_SCALE_INV4 (6 << 8) |
| # define R200_TXC_SCALE_INV8 (7 << 8) |
| # define R200_TXC_CLAMP_SHIFT 12 |
| # define R200_TXC_CLAMP_MASK (3 << 12) |
| # define R200_TXC_CLAMP_WRAP (0 << 12) |
| # define R200_TXC_CLAMP_0_1 (1 << 12) |
| # define R200_TXC_CLAMP_8_8 (2 << 12) |
| # define R200_TXC_OUTPUT_REG_MASK (7 << 16) |
| # define R200_TXC_OUTPUT_REG_NONE (0 << 16) |
| # define R200_TXC_OUTPUT_REG_R0 (1 << 16) |
| # define R200_TXC_OUTPUT_REG_R1 (2 << 16) |
| # define R200_TXC_OUTPUT_REG_R2 (3 << 16) |
| # define R200_TXC_OUTPUT_REG_R3 (4 << 16) |
| # define R200_TXC_OUTPUT_REG_R4 (5 << 16) |
| # define R200_TXC_OUTPUT_REG_R5 (6 << 16) |
| # define R200_TXC_OUTPUT_MASK_MASK (7 << 20) |
| # define R200_TXC_OUTPUT_MASK_RGB (0 << 20) |
| # define R200_TXC_OUTPUT_MASK_RG (1 << 20) |
| # define R200_TXC_OUTPUT_MASK_RB (2 << 20) |
| # define R200_TXC_OUTPUT_MASK_R (3 << 20) |
| # define R200_TXC_OUTPUT_MASK_GB (4 << 20) |
| # define R200_TXC_OUTPUT_MASK_G (5 << 20) |
| # define R200_TXC_OUTPUT_MASK_B (6 << 20) |
| # define R200_TXC_OUTPUT_MASK_NONE (7 << 20) |
| # define R200_TXC_REPL_NORMAL 0 |
| # define R200_TXC_REPL_RED 1 |
| # define R200_TXC_REPL_GREEN 2 |
| # define R200_TXC_REPL_BLUE 3 |
| # define R200_TXC_REPL_ARG_A_SHIFT 26 |
| # define R200_TXC_REPL_ARG_A_MASK (3 << 26) |
| # define R200_TXC_REPL_ARG_B_SHIFT 28 |
| # define R200_TXC_REPL_ARG_B_MASK (3 << 28) |
| # define R200_TXC_REPL_ARG_C_SHIFT 30 |
| # define R200_TXC_REPL_ARG_C_MASK (3 << 30) |
| #define R200_PP_TXABLEND_0 0x2f08 |
| # define R200_TXA_ARG_A_ZERO (0) |
| # define R200_TXA_ARG_A_CURRENT_ALPHA (2) /* guess */ |
| # define R200_TXA_ARG_A_CURRENT_BLUE (3) /* guess */ |
| # define R200_TXA_ARG_A_DIFFUSE_ALPHA (4) |
| # define R200_TXA_ARG_A_DIFFUSE_BLUE (5) |
| # define R200_TXA_ARG_A_SPECULAR_ALPHA (6) |
| # define R200_TXA_ARG_A_SPECULAR_BLUE (7) |
| # define R200_TXA_ARG_A_TFACTOR_ALPHA (8) |
| # define R200_TXA_ARG_A_TFACTOR_BLUE (9) |
| # define R200_TXA_ARG_A_R0_ALPHA (10) |
| # define R200_TXA_ARG_A_R0_BLUE (11) |
| # define R200_TXA_ARG_A_R1_ALPHA (12) |
| # define R200_TXA_ARG_A_R1_BLUE (13) |
| # define R200_TXA_ARG_A_R2_ALPHA (14) |
| # define R200_TXA_ARG_A_R2_BLUE (15) |
| # define R200_TXA_ARG_A_R3_ALPHA (16) |
| # define R200_TXA_ARG_A_R3_BLUE (17) |
| # define R200_TXA_ARG_A_R4_ALPHA (18) |
| # define R200_TXA_ARG_A_R4_BLUE (19) |
| # define R200_TXA_ARG_A_R5_ALPHA (20) |
| # define R200_TXA_ARG_A_R5_BLUE (21) |
| # define R200_TXA_ARG_A_TFACTOR1_ALPHA (26) |
| # define R200_TXA_ARG_A_TFACTOR1_BLUE (27) |
| # define R200_TXA_ARG_A_MASK (31 << 0) |
| # define R200_TXA_ARG_A_SHIFT 0 |
| # define R200_TXA_ARG_B_ZERO (0 << 5) |
| # define R200_TXA_ARG_B_CURRENT_ALPHA (2 << 5) /* guess */ |
| # define R200_TXA_ARG_B_CURRENT_BLUE (3 << 5) /* guess */ |
| # define R200_TXA_ARG_B_DIFFUSE_ALPHA (4 << 5) |
| # define R200_TXA_ARG_B_DIFFUSE_BLUE (5 << 5) |
| # define R200_TXA_ARG_B_SPECULAR_ALPHA (6 << 5) |
| # define R200_TXA_ARG_B_SPECULAR_BLUE (7 << 5) |
| # define R200_TXA_ARG_B_TFACTOR_ALPHA (8 << 5) |
| # define R200_TXA_ARG_B_TFACTOR_BLUE (9 << 5) |
| # define R200_TXA_ARG_B_R0_ALPHA (10 << 5) |
| # define R200_TXA_ARG_B_R0_BLUE (11 << 5) |
| # define R200_TXA_ARG_B_R1_ALPHA (12 << 5) |
| # define R200_TXA_ARG_B_R1_BLUE (13 << 5) |
| # define R200_TXA_ARG_B_R2_ALPHA (14 << 5) |
| # define R200_TXA_ARG_B_R2_BLUE (15 << 5) |
| # define R200_TXA_ARG_B_R3_ALPHA (16 << 5) |
| # define R200_TXA_ARG_B_R3_BLUE (17 << 5) |
| # define R200_TXA_ARG_B_R4_ALPHA (18 << 5) |
| # define R200_TXA_ARG_B_R4_BLUE (19 << 5) |
| # define R200_TXA_ARG_B_R5_ALPHA (20 << 5) |
| # define R200_TXA_ARG_B_R5_BLUE (21 << 5) |
| # define R200_TXA_ARG_B_TFACTOR1_ALPHA (26 << 5) |
| # define R200_TXA_ARG_B_TFACTOR1_BLUE (27 << 5) |
| # define R200_TXA_ARG_B_MASK (31 << 5) |
| # define R200_TXA_ARG_B_SHIFT 5 |
| # define R200_TXA_ARG_C_ZERO (0 << 10) |
| # define R200_TXA_ARG_C_CURRENT_ALPHA (2 << 10) /* guess */ |
| # define R200_TXA_ARG_C_CURRENT_BLUE (3 << 10) /* guess */ |
| # define R200_TXA_ARG_C_DIFFUSE_ALPHA (4 << 10) |
| # define R200_TXA_ARG_C_DIFFUSE_BLUE (5 << 10) |
| # define R200_TXA_ARG_C_SPECULAR_ALPHA (6 << 10) |
| # define R200_TXA_ARG_C_SPECULAR_BLUE (7 << 10) |
| # define R200_TXA_ARG_C_TFACTOR_ALPHA (8 << 10) |
| # define R200_TXA_ARG_C_TFACTOR_BLUE (9 << 10) |
| # define R200_TXA_ARG_C_R0_ALPHA (10 << 10) |
| # define R200_TXA_ARG_C_R0_BLUE (11 << 10) |
| # define R200_TXA_ARG_C_R1_ALPHA (12 << 10) |
| # define R200_TXA_ARG_C_R1_BLUE (13 << 10) |
| # define R200_TXA_ARG_C_R2_ALPHA (14 << 10) |
| # define R200_TXA_ARG_C_R2_BLUE (15 << 10) |
| # define R200_TXA_ARG_C_R3_ALPHA (16 << 10) |
| # define R200_TXA_ARG_C_R3_BLUE (17 << 10) |
| # define R200_TXA_ARG_C_R4_ALPHA (18 << 10) |
| # define R200_TXA_ARG_C_R4_BLUE (19 << 10) |
| # define R200_TXA_ARG_C_R5_ALPHA (20 << 10) |
| # define R200_TXA_ARG_C_R5_BLUE (21 << 10) |
| # define R200_TXA_ARG_C_TFACTOR1_ALPHA (26 << 10) |
| # define R200_TXA_ARG_C_TFACTOR1_BLUE (27 << 10) |
| # define R200_TXA_ARG_C_MASK (31 << 10) |
| # define R200_TXA_ARG_C_SHIFT 10 |
| # define R200_TXA_COMP_ARG_A (1 << 16) |
| # define R200_TXA_COMP_ARG_A_SHIFT (16) |
| # define R200_TXA_BIAS_ARG_A (1 << 17) |
| # define R200_TXA_SCALE_ARG_A (1 << 18) |
| # define R200_TXA_NEG_ARG_A (1 << 19) |
| # define R200_TXA_COMP_ARG_B (1 << 20) |
| # define R200_TXA_COMP_ARG_B_SHIFT (20) |
| # define R200_TXA_BIAS_ARG_B (1 << 21) |
| # define R200_TXA_SCALE_ARG_B (1 << 22) |
| # define R200_TXA_NEG_ARG_B (1 << 23) |
| # define R200_TXA_COMP_ARG_C (1 << 24) |
| # define R200_TXA_COMP_ARG_C_SHIFT (24) |
| # define R200_TXA_BIAS_ARG_C (1 << 25) |
| # define R200_TXA_SCALE_ARG_C (1 << 26) |
| # define R200_TXA_NEG_ARG_C (1 << 27) |
| # define R200_TXA_OP_MADD (0 << 28) |
| # define R200_TXA_OP_CND0 (2 << 28) |
| # define R200_TXA_OP_LERP (3 << 28) |
| # define R200_TXA_OP_CONDITIONAL (6 << 28) |
| # define R200_TXA_OP_MASK (7 << 28) |
| #define R200_PP_TXABLEND2_0 0x2f0c |
| # define R200_TXA_TFACTOR_SEL_SHIFT 0 |
| # define R200_TXA_TFACTOR_SEL_MASK 0x7 |
| # define R200_TXA_TFACTOR1_SEL_SHIFT 4 |
| # define R200_TXA_TFACTOR1_SEL_MASK (0x7 << 4) |
| # define R200_TXA_SCALE_SHIFT 8 |
| # define R200_TXA_SCALE_MASK (7 << 8) |
| # define R200_TXA_SCALE_1X (0 << 8) |
| # define R200_TXA_SCALE_2X (1 << 8) |
| # define R200_TXA_SCALE_4X (2 << 8) |
| # define R200_TXA_SCALE_8X (3 << 8) |
| # define R200_TXA_SCALE_INV2 (5 << 8) |
| # define R200_TXA_SCALE_INV4 (6 << 8) |
| # define R200_TXA_SCALE_INV8 (7 << 8) |
| # define R200_TXA_CLAMP_SHIFT 12 |
| # define R200_TXA_CLAMP_MASK (3 << 12) |
| # define R200_TXA_CLAMP_WRAP (0 << 12) |
| # define R200_TXA_CLAMP_0_1 (1 << 12) |
| # define R200_TXA_CLAMP_8_8 (2 << 12) |
| # define R200_TXA_OUTPUT_REG_MASK (7 << 16) |
| # define R200_TXA_OUTPUT_REG_NONE (0 << 16) |
| # define R200_TXA_OUTPUT_REG_R0 (1 << 16) |
| # define R200_TXA_OUTPUT_REG_R1 (2 << 16) |
| # define R200_TXA_OUTPUT_REG_R2 (3 << 16) |
| # define R200_TXA_OUTPUT_REG_R3 (4 << 16) |
| # define R200_TXA_OUTPUT_REG_R4 (5 << 16) |
| # define R200_TXA_OUTPUT_REG_R5 (6 << 16) |
| # define R200_TXA_DOT_ALPHA (1 << 20) |
| # define R200_TXA_REPL_NORMAL 0 |
| # define R200_TXA_REPL_RED 1 |
| # define R200_TXA_REPL_GREEN 2 |
| # define R200_TXA_REPL_ARG_A_SHIFT 26 |
| # define R200_TXA_REPL_ARG_A_MASK (3 << 26) |
| # define R200_TXA_REPL_ARG_B_SHIFT 28 |
| # define R200_TXA_REPL_ARG_B_MASK (3 << 28) |
| # define R200_TXA_REPL_ARG_C_SHIFT 30 |
| # define R200_TXA_REPL_ARG_C_MASK (3 << 30) |
| #define R200_SE_VTX_FMT_0 0x2088 |
| # define R200_VTX_XY 0 /* always have xy */ |
| # define R200_VTX_Z0 (1<<0) |
| # define R200_VTX_W0 (1<<1) |
| # define R200_VTX_WEIGHT_COUNT_SHIFT (2) |
| # define R200_VTX_PV_MATRIX_SEL (1<<5) |
| # define R200_VTX_N0 (1<<6) |
| # define R200_VTX_POINT_SIZE (1<<7) |
| # define R200_VTX_DISCRETE_FOG (1<<8) |
| # define R200_VTX_SHININESS_0 (1<<9) |
| # define R200_VTX_SHININESS_1 (1<<10) |
| # define R200_VTX_COLOR_NOT_PRESENT 0 |
| # define R200_VTX_PK_RGBA 1 |
| # define R200_VTX_FP_RGB 2 |
| # define R200_VTX_FP_RGBA 3 |
| # define R200_VTX_COLOR_MASK 3 |
| # define R200_VTX_COLOR_0_SHIFT 11 |
| # define R200_VTX_COLOR_1_SHIFT 13 |
| # define R200_VTX_COLOR_2_SHIFT 15 |
| # define R200_VTX_COLOR_3_SHIFT 17 |
| # define R200_VTX_COLOR_4_SHIFT 19 |
| # define R200_VTX_COLOR_5_SHIFT 21 |
| # define R200_VTX_COLOR_6_SHIFT 23 |
| # define R200_VTX_COLOR_7_SHIFT 25 |
| # define R200_VTX_XY1 (1<<28) |
| # define R200_VTX_Z1 (1<<29) |
| # define R200_VTX_W1 (1<<30) |
| # define R200_VTX_N1 (1<<31) |
| #define R200_SE_VTX_FMT_1 0x208c |
| # define R200_VTX_TEX0_COMP_CNT_SHIFT 0 |
| # define R200_VTX_TEX1_COMP_CNT_SHIFT 3 |
| # define R200_VTX_TEX2_COMP_CNT_SHIFT 6 |
| # define R200_VTX_TEX3_COMP_CNT_SHIFT 9 |
| # define R200_VTX_TEX4_COMP_CNT_SHIFT 12 |
| # define R200_VTX_TEX5_COMP_CNT_SHIFT 15 |
| #define R200_SE_TCL_OUTPUT_VTX_FMT_0 0x2090 |
| #define R200_SE_TCL_OUTPUT_VTX_FMT_1 0x2094 |
| #define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250 |
| # define R200_OUTPUT_XYZW (1<<0) |
| # define R200_OUTPUT_COLOR_0 (1<<8) |
| # define R200_OUTPUT_COLOR_1 (1<<9) |
| # define R200_OUTPUT_TEX_0 (1<<16) |
| # define R200_OUTPUT_TEX_1 (1<<17) |
| # define R200_OUTPUT_TEX_2 (1<<18) |
| # define R200_OUTPUT_TEX_3 (1<<19) |
| # define R200_OUTPUT_TEX_4 (1<<20) |
| # define R200_OUTPUT_TEX_5 (1<<21) |
| # define R200_OUTPUT_TEX_MASK (0x3f<<16) |
| # define R200_OUTPUT_DISCRETE_FOG (1<<24) |
| # define R200_OUTPUT_PT_SIZE (1<<25) |
| # define R200_FORCE_INORDER_PROC (1<<31) |
| #define R200_PP_CNTL_X 0x2cc4 |
| #define R200_PP_TXMULTI_CTL_0 0x2c1c |
| #define R200_SE_VTX_STATE_CNTL 0x2180 |
| # define R200_UPDATE_USER_COLOR_0_ENA_MASK (1<<16) |
| /* Registers for CP and Microcode Engine */ |
| #define RADEON_CP_ME_RAM_ADDR 0x07d4 |
| #define RADEON_CP_ME_RAM_RADDR 0x07d8 |
| #define RADEON_CP_ME_RAM_DATAH 0x07dc |
| #define RADEON_CP_ME_RAM_DATAL 0x07e0 |
| #define RADEON_CP_RB_BASE 0x0700 |
| #define RADEON_CP_RB_CNTL 0x0704 |
| # define RADEON_RB_BUFSZ_SHIFT 0 |
| # define RADEON_RB_BUFSZ_MASK (0x3f << 0) |
| # define RADEON_RB_BLKSZ_SHIFT 8 |
| # define RADEON_RB_BLKSZ_MASK (0x3f << 8) |
| # define RADEON_BUF_SWAP_32BIT (1 << 17) |
| # define RADEON_MAX_FETCH_SHIFT 18 |
| # define RADEON_MAX_FETCH_MASK (0x3 << 18) |
| # define RADEON_RB_NO_UPDATE (1 << 27) |
| # define RADEON_RB_RPTR_WR_ENA (1 << 31) |
| #define RADEON_CP_RB_RPTR_ADDR 0x070c |
| #define RADEON_CP_RB_RPTR 0x0710 |
| #define RADEON_CP_RB_WPTR 0x0714 |
| #define RADEON_CP_RB_RPTR_WR 0x071c |
| #define RADEON_CP_IB_BASE 0x0738 |
| #define RADEON_CP_IB_BUFSZ 0x073c |
| #define RADEON_CP_CSQ_CNTL 0x0740 |
| # define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0) |
| # define RADEON_CSQ_PRIDIS_INDDIS (0 << 28) |
| # define RADEON_CSQ_PRIPIO_INDDIS (1 << 28) |
| # define RADEON_CSQ_PRIBM_INDDIS (2 << 28) |
| # define RADEON_CSQ_PRIPIO_INDBM (3 << 28) |
| # define RADEON_CSQ_PRIBM_INDBM (4 << 28) |
| # define RADEON_CSQ_PRIPIO_INDPIO (15 << 28) |
| #define R300_CP_RESYNC_ADDR 0x778 |
| #define R300_CP_RESYNC_DATA 0x77c |
| #define RADEON_CP_CSQ_STAT 0x07f8 |
| # define RADEON_CSQ_RPTR_PRIMARY_MASK (0xff << 0) |
| # define RADEON_CSQ_WPTR_PRIMARY_MASK (0xff << 8) |
| # define RADEON_CSQ_RPTR_INDIRECT_MASK (0xff << 16) |
| # define RADEON_CSQ_WPTR_INDIRECT_MASK (0xff << 24) |
| #define RADEON_CP_CSQ2_STAT 0x07fc |
| #define RADEON_CP_CSQ_ADDR 0x07f0 |
| #define RADEON_CP_CSQ_DATA 0x07f4 |
| #define RADEON_CP_CSQ_APER_PRIMARY 0x1000 |
| #define RADEON_CP_CSQ_APER_INDIRECT 0x1300 |
| #define RADEON_CP_RB_WPTR_DELAY 0x0718 |
| # define RADEON_PRE_WRITE_TIMER_SHIFT 0 |
| # define RADEON_PRE_WRITE_LIMIT_SHIFT 23 |
| #define RADEON_CP_CSQ_MODE 0x0744 |
| # define RADEON_INDIRECT2_START_SHIFT 0 |
| # define RADEON_INDIRECT2_START_MASK (0x7f << 0) |
| # define RADEON_INDIRECT1_START_SHIFT 8 |
| # define RADEON_INDIRECT1_START_MASK (0x7f << 8) |
| #define RADEON_AIC_CNTL 0x01d0 |
| # define RADEON_PCIGART_TRANSLATE_EN (1 << 0) |
| # define RADEON_DIS_OUT_OF_PCI_GART_ACCESS (1 << 1) |
| #define RADEON_AIC_LO_ADDR 0x01dc |
| #define RADEON_AIC_PT_BASE 0x01d8 |
| #define RADEON_AIC_HI_ADDR 0x01e0 |
| /* Constants */ |
| /* #define RADEON_LAST_FRAME_REG RADEON_GUI_SCRATCH_REG0 */ |
| /* efine RADEON_LAST_CLEAR_REG RADEON_GUI_SCRATCH_REG2 */ |
| /* CP packet types */ |
| #define RADEON_CP_PACKET0 0x00000000 |
| #define RADEON_CP_PACKET1 0x40000000 |
| #define RADEON_CP_PACKET2 0x80000000 |
| #define RADEON_CP_PACKET3 0xC0000000 |
| # define RADEON_CP_PACKET_MASK 0xC0000000 |
| # define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000 |
| # define RADEON_CP_PACKET_MAX_DWORDS (1 << 12) |
| # define RADEON_CP_PACKET0_REG_MASK 0x000007ff |
| # define R300_CP_PACKET0_REG_MASK 0x00001fff |
| # define RADEON_CP_PACKET1_REG0_MASK 0x000007ff |
| # define RADEON_CP_PACKET1_REG1_MASK 0x003ff800 |
| #define RADEON_CP_PACKET0_ONE_REG_WR 0x00008000 |
| #define RADEON_CP_PACKET3_NOP 0xC0001000 |
| #define RADEON_CP_PACKET3_NEXT_CHAR 0xC0001900 |
| #define RADEON_CP_PACKET3_PLY_NEXTSCAN 0xC0001D00 |
| #define RADEON_CP_PACKET3_SET_SCISSORS 0xC0001E00 |
| #define RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM 0xC0002300 |
| #define RADEON_CP_PACKET3_LOAD_MICROCODE 0xC0002400 |
| #define RADEON_CP_PACKET3_WAIT_FOR_IDLE 0xC0002600 |
| #define RADEON_CP_PACKET3_3D_DRAW_VBUF 0xC0002800 |
| #define RADEON_CP_PACKET3_3D_DRAW_IMMD 0xC0002900 |
| #define RADEON_CP_PACKET3_3D_DRAW_INDX 0xC0002A00 |
| #define RADEON_CP_PACKET3_LOAD_PALETTE 0xC0002C00 |
| #define R200_CP_PACKET3_3D_DRAW_IMMD_2 0xc0003500 |
| #define RADEON_CP_PACKET3_3D_LOAD_VBPNTR 0xC0002F00 |
| #define RADEON_CP_PACKET3_CNTL_PAINT 0xC0009100 |
| #define RADEON_CP_PACKET3_CNTL_BITBLT 0xC0009200 |
| #define RADEON_CP_PACKET3_CNTL_SMALLTEXT 0xC0009300 |
| #define RADEON_CP_PACKET3_CNTL_HOSTDATA_BLT 0xC0009400 |
| #define RADEON_CP_PACKET3_CNTL_POLYLINE 0xC0009500 |
| #define RADEON_CP_PACKET3_CNTL_POLYSCANLINES 0xC0009800 |
| #define RADEON_CP_PACKET3_CNTL_PAINT_MULTI 0xC0009A00 |
| #define RADEON_CP_PACKET3_CNTL_BITBLT_MULTI 0xC0009B00 |
| #define RADEON_CP_PACKET3_CNTL_TRANS_BITBLT 0xC0009C00 |
| #define RADEON_CP_VC_FRMT_XY 0x00000000 |
| #define RADEON_CP_VC_FRMT_W0 0x00000001 |
| #define RADEON_CP_VC_FRMT_FPCOLOR 0x00000002 |
| #define RADEON_CP_VC_FRMT_FPALPHA 0x00000004 |
| #define RADEON_CP_VC_FRMT_PKCOLOR 0x00000008 |
| #define RADEON_CP_VC_FRMT_FPSPEC 0x00000010 |
| #define RADEON_CP_VC_FRMT_FPFOG 0x00000020 |
| #define RADEON_CP_VC_FRMT_PKSPEC 0x00000040 |
| #define RADEON_CP_VC_FRMT_ST0 0x00000080 |
| #define RADEON_CP_VC_FRMT_ST1 0x00000100 |
| #define RADEON_CP_VC_FRMT_Q1 0x00000200 |
| #define RADEON_CP_VC_FRMT_ST2 0x00000400 |
| #define RADEON_CP_VC_FRMT_Q2 0x00000800 |
| #define RADEON_CP_VC_FRMT_ST3 0x00001000 |
| #define RADEON_CP_VC_FRMT_Q3 0x00002000 |
| #define RADEON_CP_VC_FRMT_Q0 0x00004000 |
| #define RADEON_CP_VC_FRMT_BLND_WEIGHT_CNT_MASK 0x00038000 |
| #define RADEON_CP_VC_FRMT_N0 0x00040000 |
| #define RADEON_CP_VC_FRMT_XY1 0x08000000 |
| #define RADEON_CP_VC_FRMT_Z1 0x10000000 |
| #define RADEON_CP_VC_FRMT_W1 0x20000000 |
| #define RADEON_CP_VC_FRMT_N1 0x40000000 |
| #define RADEON_CP_VC_FRMT_Z 0x80000000 |
| #define RADEON_CP_VC_CNTL_PRIM_TYPE_NONE 0x00000000 |
| #define RADEON_CP_VC_CNTL_PRIM_TYPE_POINT 0x00000001 |
| #define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE 0x00000002 |
| #define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP 0x00000003 |
| #define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004 |
| #define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005 |
| #define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006 |
| #define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_TYPE_2 0x00000007 |
| #define RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST 0x00000008 |
| #define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_POINT_LIST 0x00000009 |
| #define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_LINE_LIST 0x0000000a |
| #define RADEON_CP_VC_CNTL_PRIM_WALK_IND 0x00000010 |
| #define RADEON_CP_VC_CNTL_PRIM_WALK_LIST 0x00000020 |
| #define RADEON_CP_VC_CNTL_PRIM_WALK_RING 0x00000030 |
| #define RADEON_CP_VC_CNTL_COLOR_ORDER_BGRA 0x00000000 |
| #define RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA 0x00000040 |
| #define RADEON_CP_VC_CNTL_MAOS_ENABLE 0x00000080 |
| #define RADEON_CP_VC_CNTL_VTX_FMT_NON_RADEON_MODE 0x00000000 |
| #define RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE 0x00000100 |
| #define RADEON_CP_VC_CNTL_TCL_DISABLE 0x00000000 |
| #define RADEON_CP_VC_CNTL_TCL_ENABLE 0x00000200 |
| #define RADEON_CP_VC_CNTL_NUM_SHIFT 16 |
| #define RADEON_VS_MATRIX_0_ADDR 0 |
| #define RADEON_VS_MATRIX_1_ADDR 4 |
| #define RADEON_VS_MATRIX_2_ADDR 8 |
| #define RADEON_VS_MATRIX_3_ADDR 12 |
| #define RADEON_VS_MATRIX_4_ADDR 16 |
| #define RADEON_VS_MATRIX_5_ADDR 20 |
| #define RADEON_VS_MATRIX_6_ADDR 24 |
| #define RADEON_VS_MATRIX_7_ADDR 28 |
| #define RADEON_VS_MATRIX_8_ADDR 32 |
| #define RADEON_VS_MATRIX_9_ADDR 36 |
| #define RADEON_VS_MATRIX_10_ADDR 40 |
| #define RADEON_VS_MATRIX_11_ADDR 44 |
| #define RADEON_VS_MATRIX_12_ADDR 48 |
| #define RADEON_VS_MATRIX_13_ADDR 52 |
| #define RADEON_VS_MATRIX_14_ADDR 56 |
| #define RADEON_VS_MATRIX_15_ADDR 60 |
| #define RADEON_VS_LIGHT_AMBIENT_ADDR 64 |
| #define RADEON_VS_LIGHT_DIFFUSE_ADDR 72 |
| #define RADEON_VS_LIGHT_SPECULAR_ADDR 80 |
| #define RADEON_VS_LIGHT_DIRPOS_ADDR 88 |
| #define RADEON_VS_LIGHT_HWVSPOT_ADDR 96 |
| #define RADEON_VS_LIGHT_ATTENUATION_ADDR 104 |
| #define RADEON_VS_MATRIX_EYE2CLIP_ADDR 112 |
| #define RADEON_VS_UCP_ADDR 116 |
| #define RADEON_VS_GLOBAL_AMBIENT_ADDR 122 |
| #define RADEON_VS_FOG_PARAM_ADDR 123 |
| #define RADEON_VS_EYE_VECTOR_ADDR 124 |
| #define RADEON_SS_LIGHT_DCD_ADDR 0 |
| #define RADEON_SS_LIGHT_SPOT_EXPONENT_ADDR 8 |
| #define RADEON_SS_LIGHT_SPOT_CUTOFF_ADDR 16 |
| #define RADEON_SS_LIGHT_SPECULAR_THRESH_ADDR 24 |
| #define RADEON_SS_LIGHT_RANGE_CUTOFF_ADDR 32 |
| #define RADEON_SS_VERT_GUARD_CLIP_ADJ_ADDR 48 |
| #define RADEON_SS_VERT_GUARD_DISCARD_ADJ_ADDR 49 |
| #define RADEON_SS_HORZ_GUARD_CLIP_ADJ_ADDR 50 |
| #define RADEON_SS_HORZ_GUARD_DISCARD_ADJ_ADDR 51 |
| #define RADEON_SS_SHININESS 60 |
| #define RADEON_TV_MASTER_CNTL 0x0800 |
| # define RADEON_TV_ASYNC_RST (1 << 0) |
| # define RADEON_CRT_ASYNC_RST (1 << 1) |
| # define RADEON_RESTART_PHASE_FIX (1 << 3) |
| # define RADEON_TV_FIFO_ASYNC_RST (1 << 4) |
| # define RADEON_VIN_ASYNC_RST (1 << 5) |
| # define RADEON_AUD_ASYNC_RST (1 << 6) |
| # define RADEON_DVS_ASYNC_RST (1 << 7) |
| # define RADEON_CRT_FIFO_CE_EN (1 << 9) |
| # define RADEON_TV_FIFO_CE_EN (1 << 10) |
| # define RADEON_RE_SYNC_NOW_SEL_MASK (3 << 14) |
| # define RADEON_TVCLK_ALWAYS_ONb (1 << 30) |
| # define RADEON_TV_ON (1 << 31) |
| #define RADEON_TV_PRE_DAC_MUX_CNTL 0x0888 |
| # define RADEON_Y_RED_EN (1 << 0) |
| # define RADEON_C_GRN_EN (1 << 1) |
| # define RADEON_CMP_BLU_EN (1 << 2) |
| # define RADEON_DAC_DITHER_EN (1 << 3) |
| # define RADEON_RED_MX_FORCE_DAC_DATA (6 << 4) |
| # define RADEON_GRN_MX_FORCE_DAC_DATA (6 << 8) |
| # define RADEON_BLU_MX_FORCE_DAC_DATA (6 << 12) |
| # define RADEON_TV_FORCE_DAC_DATA_SHIFT 16 |
| #define RADEON_TV_RGB_CNTL 0x0804 |
| # define RADEON_SWITCH_TO_BLUE (1 << 4) |
| # define RADEON_RGB_DITHER_EN (1 << 5) |
| # define RADEON_RGB_SRC_SEL_MASK (3 << 8) |
| # define RADEON_RGB_SRC_SEL_CRTC1 (0 << 8) |
| # define RADEON_RGB_SRC_SEL_RMX (1 << 8) |
| # define RADEON_RGB_SRC_SEL_CRTC2 (2 << 8) |
| # define RADEON_RGB_CONVERT_BY_PASS (1 << 10) |
| # define RADEON_UVRAM_READ_MARGIN_SHIFT 16 |
| # define RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT 20 |
| # define RADEON_TVOUT_SCALE_EN (1 << 26) |
| #define RADEON_TV_SYNC_CNTL 0x0808 |
| # define RADEON_SYNC_OE (1 << 0) |
| # define RADEON_SYNC_OUT (1 << 1) |
| # define RADEON_SYNC_IN (1 << 2) |
| # define RADEON_SYNC_PUB (1 << 3) |
| # define RADEON_SYNC_PD (1 << 4) |
| # define RADEON_TV_SYNC_IO_DRIVE (1 << 5) |
| #define RADEON_TV_HTOTAL 0x080c |
| #define RADEON_TV_HDISP 0x0810 |
| #define RADEON_TV_HSTART 0x0818 |
| #define RADEON_TV_HCOUNT 0x081C |
| #define RADEON_TV_VTOTAL 0x0820 |
| #define RADEON_TV_VDISP 0x0824 |
| #define RADEON_TV_VCOUNT 0x0828 |
| #define RADEON_TV_FTOTAL 0x082c |
| #define RADEON_TV_FCOUNT 0x0830 |
| #define RADEON_TV_FRESTART 0x0834 |
| #define RADEON_TV_HRESTART 0x0838 |
| #define RADEON_TV_VRESTART 0x083c |
| #define RADEON_TV_HOST_READ_DATA 0x0840 |
| #define RADEON_TV_HOST_WRITE_DATA 0x0844 |
| #define RADEON_TV_HOST_RD_WT_CNTL 0x0848 |
| # define RADEON_HOST_FIFO_RD (1 << 12) |
| # define RADEON_HOST_FIFO_RD_ACK (1 << 13) |
| # define RADEON_HOST_FIFO_WT (1 << 14) |
| # define RADEON_HOST_FIFO_WT_ACK (1 << 15) |
| #define RADEON_TV_VSCALER_CNTL1 0x084c |
| # define RADEON_UV_INC_MASK 0xffff |
| # define RADEON_UV_INC_SHIFT 0 |
| # define RADEON_Y_W_EN (1 << 24) |
| # define RADEON_RESTART_FIELD (1 << 29) /* restart on field 0 */ |
| # define RADEON_Y_DEL_W_SIG_SHIFT 26 |
| #define RADEON_TV_TIMING_CNTL 0x0850 |
| # define RADEON_H_INC_MASK 0xfff |
| # define RADEON_H_INC_SHIFT 0 |
| # define RADEON_REQ_Y_FIRST (1 << 19) |
| # define RADEON_FORCE_BURST_ALWAYS (1 << 21) |
| # define RADEON_UV_POST_SCALE_BYPASS (1 << 23) |
| # define RADEON_UV_OUTPUT_POST_SCALE_SHIFT 24 |
| #define RADEON_TV_VSCALER_CNTL2 0x0854 |
| # define RADEON_DITHER_MODE (1 << 0) |
| # define RADEON_Y_OUTPUT_DITHER_EN (1 << 1) |
| # define RADEON_UV_OUTPUT_DITHER_EN (1 << 2) |
| # define RADEON_UV_TO_BUF_DITHER_EN (1 << 3) |
| #define RADEON_TV_Y_FALL_CNTL 0x0858 |
| # define RADEON_Y_FALL_PING_PONG (1 << 16) |
| # define RADEON_Y_COEF_EN (1 << 17) |
| #define RADEON_TV_Y_RISE_CNTL 0x085c |
| # define RADEON_Y_RISE_PING_PONG (1 << 16) |
| #define RADEON_TV_Y_SAW_TOOTH_CNTL 0x0860 |
| #define RADEON_TV_UPSAMP_AND_GAIN_CNTL 0x0864 |
| # define RADEON_YUPSAMP_EN (1 << 0) |
| # define RADEON_UVUPSAMP_EN (1 << 2) |
| #define RADEON_TV_GAIN_LIMIT_SETTINGS 0x0868 |
| # define RADEON_Y_GAIN_LIMIT_SHIFT 0 |
| # define RADEON_UV_GAIN_LIMIT_SHIFT 16 |
| #define RADEON_TV_LINEAR_GAIN_SETTINGS 0x086c |
| # define RADEON_Y_GAIN_SHIFT 0 |
| # define RADEON_UV_GAIN_SHIFT 16 |
| #define RADEON_TV_MODULATOR_CNTL1 0x0870 |
| # define RADEON_YFLT_EN (1 << 2) |
| # define RADEON_UVFLT_EN (1 << 3) |
| # define RADEON_ALT_PHASE_EN (1 << 6) |
| # define RADEON_SYNC_TIP_LEVEL (1 << 7) |
| # define RADEON_BLANK_LEVEL_SHIFT 8 |
| # define RADEON_SET_UP_LEVEL_SHIFT 16 |
| # define RADEON_SLEW_RATE_LIMIT (1 << 23) |
| # define RADEON_CY_FILT_BLEND_SHIFT 28 |
| #define RADEON_TV_MODULATOR_CNTL2 0x0874 |
| # define RADEON_TV_U_BURST_LEVEL_MASK 0x1ff |
| # define RADEON_TV_V_BURST_LEVEL_MASK 0x1ff |
| # define RADEON_TV_V_BURST_LEVEL_SHIFT 16 |
| #define RADEON_TV_CRC_CNTL 0x0890 |
| #define RADEON_TV_UV_ADR 0x08ac |
| # define RADEON_MAX_UV_ADR_MASK 0x000000ff |
| # define RADEON_MAX_UV_ADR_SHIFT 0 |
| # define RADEON_TABLE1_BOT_ADR_MASK 0x0000ff00 |
| # define RADEON_TABLE1_BOT_ADR_SHIFT 8 |
| # define RADEON_TABLE3_TOP_ADR_MASK 0x00ff0000 |
| # define RADEON_TABLE3_TOP_ADR_SHIFT 16 |
| # define RADEON_HCODE_TABLE_SEL_MASK 0x06000000 |
| # define RADEON_HCODE_TABLE_SEL_SHIFT 25 |
| # define RADEON_VCODE_TABLE_SEL_MASK 0x18000000 |
| # define RADEON_VCODE_TABLE_SEL_SHIFT 27 |
| # define RADEON_TV_MAX_FIFO_ADDR 0x1a7 |
| # define RADEON_TV_MAX_FIFO_ADDR_INTERNAL 0x1ff |
| #define RADEON_TV_PLL_FINE_CNTL 0x0020 /* PLL */ |
| #define RADEON_TV_PLL_CNTL 0x0021 /* PLL */ |
| # define RADEON_TV_M0LO_MASK 0xff |
| # define RADEON_TV_M0HI_MASK 0x7 |
| # define RADEON_TV_M0HI_SHIFT 18 |
| # define RADEON_TV_N0LO_MASK 0x1ff |
| # define RADEON_TV_N0LO_SHIFT 8 |
| # define RADEON_TV_N0HI_MASK 0x3 |
| # define RADEON_TV_N0HI_SHIFT 21 |
| # define RADEON_TV_P_MASK 0xf |
| # define RADEON_TV_P_SHIFT 24 |
| # define RADEON_TV_SLIP_EN (1 << 23) |
| # define RADEON_TV_DTO_EN (1 << 28) |
| #define RADEON_TV_PLL_CNTL1 0x0022 /* PLL */ |
| # define RADEON_TVPLL_RESET (1 << 1) |
| # define RADEON_TVPLL_SLEEP (1 << 3) |
| # define RADEON_TVPLL_REFCLK_SEL (1 << 4) |
| # define RADEON_TVPCP_SHIFT 8 |
| # define RADEON_TVPCP_MASK (7 << 8) |
| # define RADEON_TVPVG_SHIFT 11 |
| # define RADEON_TVPVG_MASK (7 << 11) |
| # define RADEON_TVPDC_SHIFT 14 |
| # define RADEON_TVPDC_MASK (3 << 14) |
| # define RADEON_TVPLL_TEST_DIS (1 << 31) |
| # define RADEON_TVCLK_SRC_SEL_TVPLL (1 << 30) |
| #define RS400_DISP2_REQ_CNTL1 0xe30 |
| # define RS400_DISP2_START_REQ_LEVEL_SHIFT 0 |
| # define RS400_DISP2_START_REQ_LEVEL_MASK 0x3ff |
| # define RS400_DISP2_STOP_REQ_LEVEL_SHIFT 12 |
| # define RS400_DISP2_STOP_REQ_LEVEL_MASK 0x3ff |
| # define RS400_DISP2_ALLOW_FID_LEVEL_SHIFT 22 |
| # define RS400_DISP2_ALLOW_FID_LEVEL_MASK 0x3ff |
| #define RS400_DISP2_REQ_CNTL2 0xe34 |
| # define RS400_DISP2_CRITICAL_POINT_START_SHIFT 12 |
| # define RS400_DISP2_CRITICAL_POINT_START_MASK 0x3ff |
| # define RS400_DISP2_CRITICAL_POINT_STOP_SHIFT 22 |
| # define RS400_DISP2_CRITICAL_POINT_STOP_MASK 0x3ff |
| #define RS400_DMIF_MEM_CNTL1 0xe38 |
| # define RS400_DISP2_START_ADR_SHIFT 0 |
| # define RS400_DISP2_START_ADR_MASK 0x3ff |
| # define RS400_DISP1_CRITICAL_POINT_START_SHIFT 12 |
| # define RS400_DISP1_CRITICAL_POINT_START_MASK 0x3ff |
| # define RS400_DISP1_CRITICAL_POINT_STOP_SHIFT 22 |
| # define RS400_DISP1_CRITICAL_POINT_STOP_MASK 0x3ff |
| #define RS400_DISP1_REQ_CNTL1 0xe3c |
| # define RS400_DISP1_START_REQ_LEVEL_SHIFT 0 |
| # define RS400_DISP1_START_REQ_LEVEL_MASK 0x3ff |
| # define RS400_DISP1_STOP_REQ_LEVEL_SHIFT 12 |
| # define RS400_DISP1_STOP_REQ_LEVEL_MASK 0x3ff |
| # define RS400_DISP1_ALLOW_FID_LEVEL_SHIFT 22 |
| # define RS400_DISP1_ALLOW_FID_LEVEL_MASK 0x3ff |
| #define RADEON_PCIE_INDEX 0x0030 |
| #define RADEON_PCIE_DATA 0x0034 |
| #define RADEON_PCIE_TX_GART_CNTL 0x10 |
| # define RADEON_PCIE_TX_GART_EN (1 << 0) |
| # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1) |
| # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1 << 1) |
| # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3 << 1) |
| # define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0 << 3) |
| # define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1 << 3) |
| # define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1 << 5) |
| # define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1 << 8) |
| #define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11 |
| #define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12 |
| #define RADEON_PCIE_TX_GART_BASE 0x13 |
| #define RADEON_PCIE_TX_GART_START_LO 0x14 |
| #define RADEON_PCIE_TX_GART_START_HI 0x15 |
| #define RADEON_PCIE_TX_GART_END_LO 0x16 |
| #define RADEON_PCIE_TX_GART_END_HI 0x17 |
| #define RADEON_PCIE_TX_GART_ERROR 0x18 |
| #define RADEON_SCRATCH_REG0 0x15e0 |
| #define RADEON_SCRATCH_REG1 0x15e4 |
| #define RADEON_SCRATCH_REG2 0x15e8 |
| #define RADEON_SCRATCH_REG3 0x15ec |
| #define RADEON_SCRATCH_REG4 0x15f0 |
| #define RADEON_SCRATCH_REG5 0x15f4 |
| #endif |
| /drivers/video/drm/radeon/radeon_ring.c |
|---|
| 0,0 → 1,517 |
| /* |
| * Copyright 2008 Advanced Micro Devices, Inc. |
| * Copyright 2008 Red Hat Inc. |
| * Copyright 2009 Jerome Glisse. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice shall be included in |
| * all copies or substantial portions of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| * OTHER DEALINGS IN THE SOFTWARE. |
| * |
| * Authors: Dave Airlie |
| * Alex Deucher |
| * Jerome Glisse |
| */ |
| //#include <linux/seq_file.h> |
| //#include "drmP.h" |
| #include "radeon_drm.h" |
| #include "radeon_reg.h" |
| #include "radeon.h" |
| #include "atom.h" |
| #if 0 |
| int radeon_debugfs_ib_init(struct radeon_device *rdev); |
| /* |
| * IB. |
| */ |
| int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib) |
| { |
| struct radeon_fence *fence; |
| struct radeon_ib *nib; |
| unsigned long i; |
| int r = 0; |
| *ib = NULL; |
| r = radeon_fence_create(rdev, &fence); |
| if (r) { |
| DRM_ERROR("failed to create fence for new IB\n"); |
| return r; |
| } |
| mutex_lock(&rdev->ib_pool.mutex); |
| i = find_first_zero_bit(rdev->ib_pool.alloc_bm, RADEON_IB_POOL_SIZE); |
| if (i < RADEON_IB_POOL_SIZE) { |
| set_bit(i, rdev->ib_pool.alloc_bm); |
| rdev->ib_pool.ibs[i].length_dw = 0; |
| *ib = &rdev->ib_pool.ibs[i]; |
| goto out; |
| } |
| if (list_empty(&rdev->ib_pool.scheduled_ibs)) { |
| /* we go do nothings here */ |
| DRM_ERROR("all IB allocated none scheduled.\n"); |
| r = -EINVAL; |
| goto out; |
| } |
| /* get the first ib on the scheduled list */ |
| nib = list_entry(rdev->ib_pool.scheduled_ibs.next, |
| struct radeon_ib, list); |
| if (nib->fence == NULL) { |
| /* we go do nothings here */ |
| DRM_ERROR("IB %lu scheduled without a fence.\n", nib->idx); |
| r = -EINVAL; |
| goto out; |
| } |
| r = radeon_fence_wait(nib->fence, false); |
| if (r) { |
| DRM_ERROR("radeon: IB(%lu:0x%016lX:%u)\n", nib->idx, |
| (unsigned long)nib->gpu_addr, nib->length_dw); |
| DRM_ERROR("radeon: GPU lockup detected, fail to get a IB\n"); |
| goto out; |
| } |
| radeon_fence_unref(&nib->fence); |
| nib->length_dw = 0; |
| list_del(&nib->list); |
| INIT_LIST_HEAD(&nib->list); |
| *ib = nib; |
| out: |
| mutex_unlock(&rdev->ib_pool.mutex); |
| if (r) { |
| radeon_fence_unref(&fence); |
| } else { |
| (*ib)->fence = fence; |
| } |
| return r; |
| } |
| void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib) |
| { |
| struct radeon_ib *tmp = *ib; |
| *ib = NULL; |
| if (tmp == NULL) { |
| return; |
| } |
| mutex_lock(&rdev->ib_pool.mutex); |
| if (!list_empty(&tmp->list) && !radeon_fence_signaled(tmp->fence)) { |
| /* IB is scheduled & not signaled don't do anythings */ |
| mutex_unlock(&rdev->ib_pool.mutex); |
| return; |
| } |
| list_del(&tmp->list); |
| INIT_LIST_HEAD(&tmp->list); |
| if (tmp->fence) { |
| radeon_fence_unref(&tmp->fence); |
| } |
| tmp->length_dw = 0; |
| clear_bit(tmp->idx, rdev->ib_pool.alloc_bm); |
| mutex_unlock(&rdev->ib_pool.mutex); |
| } |
| static void radeon_ib_align(struct radeon_device *rdev, struct radeon_ib *ib) |
| { |
| while ((ib->length_dw & rdev->cp.align_mask)) { |
| ib->ptr[ib->length_dw++] = PACKET2(0); |
| } |
| } |
| static void radeon_ib_cpu_flush(struct radeon_device *rdev, |
| struct radeon_ib *ib) |
| { |
| unsigned long tmp; |
| unsigned i; |
| /* To force CPU cache flush ugly but seems reliable */ |
| for (i = 0; i < ib->length_dw; i += (rdev->cp.align_mask + 1)) { |
| tmp = readl(&ib->ptr[i]); |
| } |
| } |
| int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib) |
| { |
| int r = 0; |
| mutex_lock(&rdev->ib_pool.mutex); |
| radeon_ib_align(rdev, ib); |
| radeon_ib_cpu_flush(rdev, ib); |
| if (!ib->length_dw || !rdev->cp.ready) { |
| /* TODO: Nothings in the ib we should report. */ |
| mutex_unlock(&rdev->ib_pool.mutex); |
| DRM_ERROR("radeon: couldn't schedule IB(%lu).\n", ib->idx); |
| return -EINVAL; |
| } |
| /* 64 dwords should be enought for fence too */ |
| r = radeon_ring_lock(rdev, 64); |
| if (r) { |
| DRM_ERROR("radeon: scheduling IB failled (%d).\n", r); |
| mutex_unlock(&rdev->ib_pool.mutex); |
| return r; |
| } |
| radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1)); |
| radeon_ring_write(rdev, ib->gpu_addr); |
| radeon_ring_write(rdev, ib->length_dw); |
| radeon_fence_emit(rdev, ib->fence); |
| radeon_ring_unlock_commit(rdev); |
| list_add_tail(&ib->list, &rdev->ib_pool.scheduled_ibs); |
| mutex_unlock(&rdev->ib_pool.mutex); |
| return 0; |
| } |
| int radeon_ib_pool_init(struct radeon_device *rdev) |
| { |
| void *ptr; |
| uint64_t gpu_addr; |
| int i; |
| int r = 0; |
| /* Allocate 1M object buffer */ |
| INIT_LIST_HEAD(&rdev->ib_pool.scheduled_ibs); |
| r = radeon_object_create(rdev, NULL, RADEON_IB_POOL_SIZE*64*1024, |
| true, RADEON_GEM_DOMAIN_GTT, |
| false, &rdev->ib_pool.robj); |
| if (r) { |
| DRM_ERROR("radeon: failed to ib pool (%d).\n", r); |
| return r; |
| } |
| r = radeon_object_pin(rdev->ib_pool.robj, RADEON_GEM_DOMAIN_GTT, &gpu_addr); |
| if (r) { |
| DRM_ERROR("radeon: failed to pin ib pool (%d).\n", r); |
| return r; |
| } |
| r = radeon_object_kmap(rdev->ib_pool.robj, &ptr); |
| if (r) { |
| DRM_ERROR("radeon: failed to map ib poll (%d).\n", r); |
| return r; |
| } |
| for (i = 0; i < RADEON_IB_POOL_SIZE; i++) { |
| unsigned offset; |
| offset = i * 64 * 1024; |
| rdev->ib_pool.ibs[i].gpu_addr = gpu_addr + offset; |
| rdev->ib_pool.ibs[i].ptr = ptr + offset; |
| rdev->ib_pool.ibs[i].idx = i; |
| rdev->ib_pool.ibs[i].length_dw = 0; |
| INIT_LIST_HEAD(&rdev->ib_pool.ibs[i].list); |
| } |
| bitmap_zero(rdev->ib_pool.alloc_bm, RADEON_IB_POOL_SIZE); |
| rdev->ib_pool.ready = true; |
| DRM_INFO("radeon: ib pool ready.\n"); |
| if (radeon_debugfs_ib_init(rdev)) { |
| DRM_ERROR("Failed to register debugfs file for IB !\n"); |
| } |
| return r; |
| } |
| void radeon_ib_pool_fini(struct radeon_device *rdev) |
| { |
| if (!rdev->ib_pool.ready) { |
| return; |
| } |
| mutex_lock(&rdev->ib_pool.mutex); |
| bitmap_zero(rdev->ib_pool.alloc_bm, RADEON_IB_POOL_SIZE); |
| if (rdev->ib_pool.robj) { |
| radeon_object_kunmap(rdev->ib_pool.robj); |
| radeon_object_unref(&rdev->ib_pool.robj); |
| rdev->ib_pool.robj = NULL; |
| } |
| mutex_unlock(&rdev->ib_pool.mutex); |
| } |
| int radeon_ib_test(struct radeon_device *rdev) |
| { |
| struct radeon_ib *ib; |
| uint32_t scratch; |
| uint32_t tmp = 0; |
| unsigned i; |
| int r; |
| r = radeon_scratch_get(rdev, &scratch); |
| if (r) { |
| DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r); |
| return r; |
| } |
| WREG32(scratch, 0xCAFEDEAD); |
| r = radeon_ib_get(rdev, &ib); |
| if (r) { |
| return r; |
| } |
| ib->ptr[0] = PACKET0(scratch, 0); |
| ib->ptr[1] = 0xDEADBEEF; |
| ib->ptr[2] = PACKET2(0); |
| ib->ptr[3] = PACKET2(0); |
| ib->ptr[4] = PACKET2(0); |
| ib->ptr[5] = PACKET2(0); |
| ib->ptr[6] = PACKET2(0); |
| ib->ptr[7] = PACKET2(0); |
| ib->length_dw = 8; |
| r = radeon_ib_schedule(rdev, ib); |
| if (r) { |
| radeon_scratch_free(rdev, scratch); |
| radeon_ib_free(rdev, &ib); |
| return r; |
| } |
| r = radeon_fence_wait(ib->fence, false); |
| if (r) { |
| return r; |
| } |
| for (i = 0; i < rdev->usec_timeout; i++) { |
| tmp = RREG32(scratch); |
| if (tmp == 0xDEADBEEF) { |
| break; |
| } |
| DRM_UDELAY(1); |
| } |
| if (i < rdev->usec_timeout) { |
| DRM_INFO("ib test succeeded in %u usecs\n", i); |
| } else { |
| DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n", |
| scratch, tmp); |
| r = -EINVAL; |
| } |
| radeon_scratch_free(rdev, scratch); |
| radeon_ib_free(rdev, &ib); |
| return r; |
| } |
| #endif |
| /* |
| * Ring. |
| */ |
| void radeon_ring_free_size(struct radeon_device *rdev) |
| { |
| rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR); |
| /* This works because ring_size is a power of 2 */ |
| rdev->cp.ring_free_dw = (rdev->cp.rptr + (rdev->cp.ring_size / 4)); |
| rdev->cp.ring_free_dw -= rdev->cp.wptr; |
| rdev->cp.ring_free_dw &= rdev->cp.ptr_mask; |
| if (!rdev->cp.ring_free_dw) { |
| rdev->cp.ring_free_dw = rdev->cp.ring_size / 4; |
| } |
| } |
| int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw) |
| { |
| int r; |
| /* Align requested size with padding so unlock_commit can |
| * pad safely */ |
| ndw = (ndw + rdev->cp.align_mask) & ~rdev->cp.align_mask; |
| // mutex_lock(&rdev->cp.mutex); |
| while (ndw > (rdev->cp.ring_free_dw - 1)) { |
| radeon_ring_free_size(rdev); |
| if (ndw < rdev->cp.ring_free_dw) { |
| break; |
| } |
| delay(1); |
| // r = radeon_fence_wait_next(rdev); |
| // if (r) { |
| // mutex_unlock(&rdev->cp.mutex); |
| // return r; |
| // } |
| } |
| rdev->cp.count_dw = ndw; |
| rdev->cp.wptr_old = rdev->cp.wptr; |
| return 0; |
| } |
| void radeon_ring_unlock_commit(struct radeon_device *rdev) |
| { |
| unsigned count_dw_pad; |
| unsigned i; |
| /* We pad to match fetch size */ |
| count_dw_pad = (rdev->cp.align_mask + 1) - |
| (rdev->cp.wptr & rdev->cp.align_mask); |
| for (i = 0; i < count_dw_pad; i++) { |
| radeon_ring_write(rdev, PACKET2(0)); |
| } |
| DRM_MEMORYBARRIER(); |
| WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr); |
| (void)RREG32(RADEON_CP_RB_WPTR); |
| // mutex_unlock(&rdev->cp.mutex); |
| } |
| void radeon_ring_unlock_undo(struct radeon_device *rdev) |
| { |
| rdev->cp.wptr = rdev->cp.wptr_old; |
| // mutex_unlock(&rdev->cp.mutex); |
| } |
| int radeon_ring_test(struct radeon_device *rdev) |
| { |
| uint32_t scratch; |
| uint32_t tmp = 0; |
| unsigned i; |
| int r; |
| dbgprintf("%s\n\r",__FUNCTION__); |
| r = radeon_scratch_get(rdev, &scratch); |
| if (r) { |
| DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r); |
| return r; |
| } |
| WREG32(scratch, 0xCAFEDEAD); |
| r = radeon_ring_lock(rdev, 2); |
| if (r) { |
| DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); |
| radeon_scratch_free(rdev, scratch); |
| return r; |
| } |
| radeon_ring_write(rdev, PACKET0(scratch, 0)); |
| radeon_ring_write(rdev, 0xDEADBEEF); |
| radeon_ring_unlock_commit(rdev); |
| for (i = 0; i < rdev->usec_timeout; i++) { |
| tmp = RREG32(scratch); |
| if (tmp == 0xDEADBEEF) { |
| break; |
| } |
| DRM_UDELAY(1); |
| } |
| if (i < rdev->usec_timeout) { |
| DRM_INFO("ring test succeeded in %d usecs\n", i); |
| } else { |
| DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n", |
| scratch, tmp); |
| r = -EINVAL; |
| } |
| radeon_scratch_free(rdev, scratch); |
| return r; |
| } |
| int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size) |
| { |
| int r; |
| dbgprintf("%s\n\r",__FUNCTION__); |
| rdev->cp.ring_size = ring_size; |
| #if 0 |
| /* Allocate ring buffer */ |
| if (rdev->cp.ring_obj == NULL) { |
| r = radeon_object_create(rdev, NULL, rdev->cp.ring_size, |
| true, |
| RADEON_GEM_DOMAIN_GTT, |
| false, |
| &rdev->cp.ring_obj); |
| if (r) { |
| DRM_ERROR("radeon: failed to create ring buffer (%d).\n", r); |
| // mutex_unlock(&rdev->cp.mutex); |
| return r; |
| } |
| r = radeon_object_pin(rdev->cp.ring_obj, |
| RADEON_GEM_DOMAIN_GTT, |
| &rdev->cp.gpu_addr); |
| if (r) { |
| DRM_ERROR("radeon: failed to pin ring buffer (%d).\n", r); |
| // mutex_unlock(&rdev->cp.mutex); |
| return r; |
| } |
| r = radeon_object_kmap(rdev->cp.ring_obj, |
| (void **)&rdev->cp.ring); |
| if (r) { |
| DRM_ERROR("radeon: failed to map ring buffer (%d).\n", r); |
| // mutex_unlock(&rdev->cp.mutex); |
| return r; |
| } |
| } |
| #endif |
| rdev->cp.ring = CreateRingBuffer( ring_size, PG_SW); |
| rdev->cp.gpu_addr = GetPgAddr(rdev->cp.ring); |
| rdev->cp.ptr_mask = (rdev->cp.ring_size / 4) - 1; |
| rdev->cp.ring_free_dw = rdev->cp.ring_size / 4; |
| return 0; |
| } |
| void radeon_ring_fini(struct radeon_device *rdev) |
| { |
| // mutex_lock(&rdev->cp.mutex); |
| if (rdev->cp.ring_obj) { |
| // radeon_object_kunmap(rdev->cp.ring_obj); |
| // radeon_object_unpin(rdev->cp.ring_obj); |
| // radeon_object_unref(&rdev->cp.ring_obj); |
| rdev->cp.ring = NULL; |
| rdev->cp.ring_obj = NULL; |
| } |
| // mutex_unlock(&rdev->cp.mutex); |
| } |
| /* |
| * Debugfs info |
| */ |
| #if defined(CONFIG_DEBUG_FS) |
| static int radeon_debugfs_ib_info(struct seq_file *m, void *data) |
| { |
| struct drm_info_node *node = (struct drm_info_node *) m->private; |
| struct radeon_ib *ib = node->info_ent->data; |
| unsigned i; |
| if (ib == NULL) { |
| return 0; |
| } |
| seq_printf(m, "IB %04lu\n", ib->idx); |
| seq_printf(m, "IB fence %p\n", ib->fence); |
| seq_printf(m, "IB size %05u dwords\n", ib->length_dw); |
| for (i = 0; i < ib->length_dw; i++) { |
| seq_printf(m, "[%05u]=0x%08X\n", i, ib->ptr[i]); |
| } |
| return 0; |
| } |
| static struct drm_info_list radeon_debugfs_ib_list[RADEON_IB_POOL_SIZE]; |
| static char radeon_debugfs_ib_names[RADEON_IB_POOL_SIZE][32]; |
| #endif |
| int radeon_debugfs_ib_init(struct radeon_device *rdev) |
| { |
| #if defined(CONFIG_DEBUG_FS) |
| unsigned i; |
| for (i = 0; i < RADEON_IB_POOL_SIZE; i++) { |
| sprintf(radeon_debugfs_ib_names[i], "radeon_ib_%04u", i); |
| radeon_debugfs_ib_list[i].name = radeon_debugfs_ib_names[i]; |
| radeon_debugfs_ib_list[i].show = &radeon_debugfs_ib_info; |
| radeon_debugfs_ib_list[i].driver_features = 0; |
| radeon_debugfs_ib_list[i].data = &rdev->ib_pool.ibs[i]; |
| } |
| return radeon_debugfs_add_files(rdev, radeon_debugfs_ib_list, |
| RADEON_IB_POOL_SIZE); |
| #else |
| return 0; |
| #endif |
| } |
| int drm_order(unsigned long size) |
| { |
| int order; |
| unsigned long tmp; |
| for (order = 0, tmp = size >> 1; tmp; tmp >>= 1, order++) ; |
| if (size & (size - 1)) |
| ++order; |
| return order; |
| } |
| /drivers/video/drm/radeon/rv515.c |
|---|
| 0,0 → 1,574 |
| /* |
| * Copyright 2008 Advanced Micro Devices, Inc. |
| * Copyright 2008 Red Hat Inc. |
| * Copyright 2009 Jerome Glisse. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice shall be included in |
| * all copies or substantial portions of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| * OTHER DEALINGS IN THE SOFTWARE. |
| * |
| * Authors: Dave Airlie |
| * Alex Deucher |
| * Jerome Glisse |
| */ |
| //#include <linux/seq_file.h> |
| //#include "drmP.h" |
| #include "radeon_reg.h" |
| #include "radeon.h" |
| /* rv515 depends on : */ |
| void r100_hdp_reset(struct radeon_device *rdev); |
| int r100_cp_reset(struct radeon_device *rdev); |
| int r100_rb2d_reset(struct radeon_device *rdev); |
| int r100_gui_wait_for_idle(struct radeon_device *rdev); |
| int r100_cp_init(struct radeon_device *rdev, unsigned ring_size); |
| int rv370_pcie_gart_enable(struct radeon_device *rdev); |
| void rv370_pcie_gart_disable(struct radeon_device *rdev); |
| void r420_pipes_init(struct radeon_device *rdev); |
| void rs600_mc_disable_clients(struct radeon_device *rdev); |
| void rs600_disable_vga(struct radeon_device *rdev); |
| /* This files gather functions specifics to: |
| * rv515 |
| * |
| * Some of these functions might be used by newer ASICs. |
| */ |
| int rv515_debugfs_pipes_info_init(struct radeon_device *rdev); |
| int rv515_debugfs_ga_info_init(struct radeon_device *rdev); |
| void rv515_gpu_init(struct radeon_device *rdev); |
| int rv515_mc_wait_for_idle(struct radeon_device *rdev); |
| #if 0 |
| /* |
| * MC |
| */ |
| int rv515_mc_init(struct radeon_device *rdev) |
| { |
| uint32_t tmp; |
| int r; |
| if (r100_debugfs_rbbm_init(rdev)) { |
| DRM_ERROR("Failed to register debugfs file for RBBM !\n"); |
| } |
| if (rv515_debugfs_pipes_info_init(rdev)) { |
| DRM_ERROR("Failed to register debugfs file for pipes !\n"); |
| } |
| if (rv515_debugfs_ga_info_init(rdev)) { |
| DRM_ERROR("Failed to register debugfs file for pipes !\n"); |
| } |
| rv515_gpu_init(rdev); |
| rv370_pcie_gart_disable(rdev); |
| /* Setup GPU memory space */ |
| rdev->mc.vram_location = 0xFFFFFFFFUL; |
| rdev->mc.gtt_location = 0xFFFFFFFFUL; |
| if (rdev->flags & RADEON_IS_AGP) { |
| r = radeon_agp_init(rdev); |
| if (r) { |
| printk(KERN_WARNING "[drm] Disabling AGP\n"); |
| rdev->flags &= ~RADEON_IS_AGP; |
| rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; |
| } else { |
| rdev->mc.gtt_location = rdev->mc.agp_base; |
| } |
| } |
| r = radeon_mc_setup(rdev); |
| if (r) { |
| return r; |
| } |
| /* Program GPU memory space */ |
| rs600_mc_disable_clients(rdev); |
| if (rv515_mc_wait_for_idle(rdev)) { |
| printk(KERN_WARNING "Failed to wait MC idle while " |
| "programming pipes. Bad things might happen.\n"); |
| } |
| /* Write VRAM size in case we are limiting it */ |
| WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size); |
| tmp = REG_SET(RV515_MC_FB_START, rdev->mc.vram_location >> 16); |
| WREG32(0x134, tmp); |
| tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1; |
| tmp = REG_SET(RV515_MC_FB_TOP, tmp >> 16); |
| tmp |= REG_SET(RV515_MC_FB_START, rdev->mc.vram_location >> 16); |
| WREG32_MC(RV515_MC_FB_LOCATION, tmp); |
| WREG32(RS690_HDP_FB_LOCATION, rdev->mc.vram_location >> 16); |
| WREG32(0x310, rdev->mc.vram_location); |
| if (rdev->flags & RADEON_IS_AGP) { |
| tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; |
| tmp = REG_SET(RV515_MC_AGP_TOP, tmp >> 16); |
| tmp |= REG_SET(RV515_MC_AGP_START, rdev->mc.gtt_location >> 16); |
| WREG32_MC(RV515_MC_AGP_LOCATION, tmp); |
| WREG32_MC(RV515_MC_AGP_BASE, rdev->mc.agp_base); |
| WREG32_MC(RV515_MC_AGP_BASE_2, 0); |
| } else { |
| WREG32_MC(RV515_MC_AGP_LOCATION, 0x0FFFFFFF); |
| WREG32_MC(RV515_MC_AGP_BASE, 0); |
| WREG32_MC(RV515_MC_AGP_BASE_2, 0); |
| } |
| return 0; |
| } |
| void rv515_mc_fini(struct radeon_device *rdev) |
| { |
| rv370_pcie_gart_disable(rdev); |
| radeon_gart_table_vram_free(rdev); |
| radeon_gart_fini(rdev); |
| } |
| /* |
| * Global GPU functions |
| */ |
| void rv515_ring_start(struct radeon_device *rdev) |
| { |
| unsigned gb_tile_config; |
| int r; |
| /* Sub pixel 1/12 so we can have 4K rendering according to doc */ |
| gb_tile_config = R300_ENABLE_TILING | R300_TILE_SIZE_16; |
| switch (rdev->num_gb_pipes) { |
| case 2: |
| gb_tile_config |= R300_PIPE_COUNT_R300; |
| break; |
| case 3: |
| gb_tile_config |= R300_PIPE_COUNT_R420_3P; |
| break; |
| case 4: |
| gb_tile_config |= R300_PIPE_COUNT_R420; |
| break; |
| case 1: |
| default: |
| gb_tile_config |= R300_PIPE_COUNT_RV350; |
| break; |
| } |
| r = radeon_ring_lock(rdev, 64); |
| if (r) { |
| return; |
| } |
| radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0)); |
| radeon_ring_write(rdev, |
| RADEON_ISYNC_ANY2D_IDLE3D | |
| RADEON_ISYNC_ANY3D_IDLE2D | |
| RADEON_ISYNC_WAIT_IDLEGUI | |
| RADEON_ISYNC_CPSCRATCH_IDLEGUI); |
| radeon_ring_write(rdev, PACKET0(R300_GB_TILE_CONFIG, 0)); |
| radeon_ring_write(rdev, gb_tile_config); |
| radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); |
| radeon_ring_write(rdev, |
| RADEON_WAIT_2D_IDLECLEAN | |
| RADEON_WAIT_3D_IDLECLEAN); |
| radeon_ring_write(rdev, PACKET0(0x170C, 0)); |
| radeon_ring_write(rdev, 1 << 31); |
| radeon_ring_write(rdev, PACKET0(R300_GB_SELECT, 0)); |
| radeon_ring_write(rdev, 0); |
| radeon_ring_write(rdev, PACKET0(R300_GB_ENABLE, 0)); |
| radeon_ring_write(rdev, 0); |
| radeon_ring_write(rdev, PACKET0(0x42C8, 0)); |
| radeon_ring_write(rdev, (1 << rdev->num_gb_pipes) - 1); |
| radeon_ring_write(rdev, PACKET0(R500_VAP_INDEX_OFFSET, 0)); |
| radeon_ring_write(rdev, 0); |
| radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); |
| radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); |
| radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); |
| radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE); |
| radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); |
| radeon_ring_write(rdev, |
| RADEON_WAIT_2D_IDLECLEAN | |
| RADEON_WAIT_3D_IDLECLEAN); |
| radeon_ring_write(rdev, PACKET0(R300_GB_AA_CONFIG, 0)); |
| radeon_ring_write(rdev, 0); |
| radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); |
| radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); |
| radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); |
| radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE); |
| radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS0, 0)); |
| radeon_ring_write(rdev, |
| ((6 << R300_MS_X0_SHIFT) | |
| (6 << R300_MS_Y0_SHIFT) | |
| (6 << R300_MS_X1_SHIFT) | |
| (6 << R300_MS_Y1_SHIFT) | |
| (6 << R300_MS_X2_SHIFT) | |
| (6 << R300_MS_Y2_SHIFT) | |
| (6 << R300_MSBD0_Y_SHIFT) | |
| (6 << R300_MSBD0_X_SHIFT))); |
| radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS1, 0)); |
| radeon_ring_write(rdev, |
| ((6 << R300_MS_X3_SHIFT) | |
| (6 << R300_MS_Y3_SHIFT) | |
| (6 << R300_MS_X4_SHIFT) | |
| (6 << R300_MS_Y4_SHIFT) | |
| (6 << R300_MS_X5_SHIFT) | |
| (6 << R300_MS_Y5_SHIFT) | |
| (6 << R300_MSBD1_SHIFT))); |
| radeon_ring_write(rdev, PACKET0(R300_GA_ENHANCE, 0)); |
| radeon_ring_write(rdev, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL); |
| radeon_ring_write(rdev, PACKET0(R300_GA_POLY_MODE, 0)); |
| radeon_ring_write(rdev, |
| R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE); |
| radeon_ring_write(rdev, PACKET0(R300_GA_ROUND_MODE, 0)); |
| radeon_ring_write(rdev, |
| R300_GEOMETRY_ROUND_NEAREST | |
| R300_COLOR_ROUND_NEAREST); |
| radeon_ring_write(rdev, PACKET0(0x20C8, 0)); |
| radeon_ring_write(rdev, 0); |
| radeon_ring_unlock_commit(rdev); |
| } |
| void rv515_errata(struct radeon_device *rdev) |
| { |
| rdev->pll_errata = 0; |
| } |
| int rv515_mc_wait_for_idle(struct radeon_device *rdev) |
| { |
| unsigned i; |
| uint32_t tmp; |
| for (i = 0; i < rdev->usec_timeout; i++) { |
| /* read MC_STATUS */ |
| tmp = RREG32_MC(RV515_MC_STATUS); |
| if (tmp & RV515_MC_STATUS_IDLE) { |
| return 0; |
| } |
| DRM_UDELAY(1); |
| } |
| return -1; |
| } |
| void rv515_gpu_init(struct radeon_device *rdev) |
| { |
| unsigned pipe_select_current, gb_pipe_select, tmp; |
| r100_hdp_reset(rdev); |
| r100_rb2d_reset(rdev); |
| if (r100_gui_wait_for_idle(rdev)) { |
| printk(KERN_WARNING "Failed to wait GUI idle while " |
| "reseting GPU. Bad things might happen.\n"); |
| } |
| rs600_disable_vga(rdev); |
| r420_pipes_init(rdev); |
| gb_pipe_select = RREG32(0x402C); |
| tmp = RREG32(0x170C); |
| pipe_select_current = (tmp >> 2) & 3; |
| tmp = (1 << pipe_select_current) | |
| (((gb_pipe_select >> 8) & 0xF) << 4); |
| WREG32_PLL(0x000D, tmp); |
| if (r100_gui_wait_for_idle(rdev)) { |
| printk(KERN_WARNING "Failed to wait GUI idle while " |
| "reseting GPU. Bad things might happen.\n"); |
| } |
| if (rv515_mc_wait_for_idle(rdev)) { |
| printk(KERN_WARNING "Failed to wait MC idle while " |
| "programming pipes. Bad things might happen.\n"); |
| } |
| } |
| #endif |
| int rv515_ga_reset(struct radeon_device *rdev) |
| { |
| uint32_t tmp; |
| bool reinit_cp; |
| int i; |
| dbgprintf("%s\n\r",__FUNCTION__); |
| reinit_cp = rdev->cp.ready; |
| rdev->cp.ready = false; |
| for (i = 0; i < rdev->usec_timeout; i++) { |
| WREG32(RADEON_CP_CSQ_MODE, 0); |
| WREG32(RADEON_CP_CSQ_CNTL, 0); |
| WREG32(RADEON_RBBM_SOFT_RESET, 0x32005); |
| (void)RREG32(RADEON_RBBM_SOFT_RESET); |
| udelay(200); |
| WREG32(RADEON_RBBM_SOFT_RESET, 0); |
| /* Wait to prevent race in RBBM_STATUS */ |
| mdelay(1); |
| tmp = RREG32(RADEON_RBBM_STATUS); |
| if (tmp & ((1 << 20) | (1 << 26))) { |
| DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)\n", tmp); |
| /* GA still busy soft reset it */ |
| WREG32(0x429C, 0x200); |
| WREG32(R300_VAP_PVS_STATE_FLUSH_REG, 0); |
| WREG32(0x43E0, 0); |
| WREG32(0x43E4, 0); |
| WREG32(0x24AC, 0); |
| } |
| /* Wait to prevent race in RBBM_STATUS */ |
| mdelay(1); |
| tmp = RREG32(RADEON_RBBM_STATUS); |
| if (!(tmp & ((1 << 20) | (1 << 26)))) { |
| break; |
| } |
| } |
| for (i = 0; i < rdev->usec_timeout; i++) { |
| tmp = RREG32(RADEON_RBBM_STATUS); |
| if (!(tmp & ((1 << 20) | (1 << 26)))) { |
| DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n", |
| tmp); |
| DRM_INFO("GA_IDLE=0x%08X\n", RREG32(0x425C)); |
| DRM_INFO("RB3D_RESET_STATUS=0x%08X\n", RREG32(0x46f0)); |
| DRM_INFO("ISYNC_CNTL=0x%08X\n", RREG32(0x1724)); |
| if (reinit_cp) { |
| return r100_cp_init(rdev, rdev->cp.ring_size); |
| } |
| return 0; |
| } |
| DRM_UDELAY(1); |
| } |
| tmp = RREG32(RADEON_RBBM_STATUS); |
| DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp); |
| return -1; |
| } |
| int rv515_gpu_reset(struct radeon_device *rdev) |
| { |
| uint32_t status; |
| dbgprintf("%s\n\r",__FUNCTION__); |
| /* reset order likely matter */ |
| status = RREG32(RADEON_RBBM_STATUS); |
| /* reset HDP */ |
| r100_hdp_reset(rdev); |
| /* reset rb2d */ |
| if (status & ((1 << 17) | (1 << 18) | (1 << 27))) { |
| r100_rb2d_reset(rdev); |
| } |
| /* reset GA */ |
| if (status & ((1 << 20) | (1 << 26))) { |
| rv515_ga_reset(rdev); |
| } |
| /* reset CP */ |
| status = RREG32(RADEON_RBBM_STATUS); |
| if (status & (1 << 16)) { |
| r100_cp_reset(rdev); |
| } |
| /* Check if GPU is idle */ |
| status = RREG32(RADEON_RBBM_STATUS); |
| if (status & (1 << 31)) { |
| DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status); |
| return -1; |
| } |
| DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status); |
| return 0; |
| } |
| #if 0 |
| /* |
| * VRAM info |
| */ |
| static void rv515_vram_get_type(struct radeon_device *rdev) |
| { |
| uint32_t tmp; |
| rdev->mc.vram_width = 128; |
| rdev->mc.vram_is_ddr = true; |
| tmp = RREG32_MC(RV515_MC_CNTL); |
| tmp &= RV515_MEM_NUM_CHANNELS_MASK; |
| switch (tmp) { |
| case 0: |
| rdev->mc.vram_width = 64; |
| break; |
| case 1: |
| rdev->mc.vram_width = 128; |
| break; |
| default: |
| rdev->mc.vram_width = 128; |
| break; |
| } |
| } |
| void rv515_vram_info(struct radeon_device *rdev) |
| { |
| rv515_vram_get_type(rdev); |
| rdev->mc.vram_size = RREG32(RADEON_CONFIG_MEMSIZE); |
| rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); |
| rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); |
| } |
| #endif |
| /* |
| * Indirect registers accessor |
| */ |
| uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
| { |
| uint32_t r; |
| WREG32(R520_MC_IND_INDEX, 0x7f0000 | (reg & 0xffff)); |
| r = RREG32(R520_MC_IND_DATA); |
| WREG32(R520_MC_IND_INDEX, 0); |
| return r; |
| } |
| void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
| { |
| WREG32(R520_MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff)); |
| WREG32(R520_MC_IND_DATA, (v)); |
| WREG32(R520_MC_IND_INDEX, 0); |
| } |
| uint32_t rv515_pcie_rreg(struct radeon_device *rdev, uint32_t reg) |
| { |
| uint32_t r; |
| WREG32(RADEON_PCIE_INDEX, ((reg) & 0x7ff)); |
| (void)RREG32(RADEON_PCIE_INDEX); |
| r = RREG32(RADEON_PCIE_DATA); |
| return r; |
| } |
| void rv515_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
| { |
| WREG32(RADEON_PCIE_INDEX, ((reg) & 0x7ff)); |
| (void)RREG32(RADEON_PCIE_INDEX); |
| WREG32(RADEON_PCIE_DATA, (v)); |
| (void)RREG32(RADEON_PCIE_DATA); |
| } |
| #if 0 |
| /* |
| * Debugfs info |
| */ |
| #if defined(CONFIG_DEBUG_FS) |
| static int rv515_debugfs_pipes_info(struct seq_file *m, void *data) |
| { |
| struct drm_info_node *node = (struct drm_info_node *) m->private; |
| struct drm_device *dev = node->minor->dev; |
| struct radeon_device *rdev = dev->dev_private; |
| uint32_t tmp; |
| tmp = RREG32(R400_GB_PIPE_SELECT); |
| seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp); |
| tmp = RREG32(R500_SU_REG_DEST); |
| seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp); |
| tmp = RREG32(R300_GB_TILE_CONFIG); |
| seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp); |
| tmp = RREG32(R300_DST_PIPE_CONFIG); |
| seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp); |
| return 0; |
| } |
| static int rv515_debugfs_ga_info(struct seq_file *m, void *data) |
| { |
| struct drm_info_node *node = (struct drm_info_node *) m->private; |
| struct drm_device *dev = node->minor->dev; |
| struct radeon_device *rdev = dev->dev_private; |
| uint32_t tmp; |
| tmp = RREG32(0x2140); |
| seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp); |
| radeon_gpu_reset(rdev); |
| tmp = RREG32(0x425C); |
| seq_printf(m, "GA_IDLE 0x%08x\n", tmp); |
| return 0; |
| } |
| static struct drm_info_list rv515_pipes_info_list[] = { |
| {"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL}, |
| }; |
| static struct drm_info_list rv515_ga_info_list[] = { |
| {"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL}, |
| }; |
| #endif |
| int rv515_debugfs_pipes_info_init(struct radeon_device *rdev) |
| { |
| #if defined(CONFIG_DEBUG_FS) |
| return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1); |
| #else |
| return 0; |
| #endif |
| } |
| int rv515_debugfs_ga_info_init(struct radeon_device *rdev) |
| { |
| #if defined(CONFIG_DEBUG_FS) |
| return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1); |
| #else |
| return 0; |
| #endif |
| } |
| #endif |
| /* |
| * Asic initialization |
| */ |
| static const unsigned r500_reg_safe_bm[159] = { |
| 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
| 0xFFFFFFBF, 0xFFFFFFFF, 0xFFFFFFBF, 0xFFFFFFFF, |
| 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
| 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
| 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
| 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
| 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
| 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
| 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
| 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
| 0x17FF1FFF, 0xFFFFFFFC, 0xFFFFFFFF, 0xFF30FFBF, |
| 0xFFFFFFF8, 0xC3E6FFFF, 0xFFFFF6DF, 0xFFFFFFFF, |
| 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
| 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
| 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFF03F, |
| 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
| 0xFFFFFFFF, 0xFFFFEFCE, 0xF00EBFFF, 0x007C0000, |
| 0xF0000038, 0xFF000009, 0xFFFFFFFF, 0xFFFFFFFF, |
| 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, |
| 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
| 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
| 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
| 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
| 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
| 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
| 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
| 0xFFFFF7FF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
| 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
| 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
| 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
| 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
| 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
| 0x1FFFFC78, 0xFFFFE000, 0xFFFFFFFE, 0xFFFFFFFF, |
| 0x38CF8F50, 0xFFF88082, 0xFF0000FC, 0xFAE009FF, |
| 0x0000FFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, |
| 0xFFFF8CFC, 0xFFFFC1FF, 0xFFFFFFFF, 0xFFFFFFFF, |
| 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, |
| 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFF80FFFF, |
| 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 0x0003FC01, 0x3FFFFCF8, 0xFE800B19, |
| }; |
| int rv515_init(struct radeon_device *rdev) |
| { |
| dbgprintf("%s\n\r",__FUNCTION__); |
| rdev->config.r300.reg_safe_bm = r500_reg_safe_bm; |
| rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r500_reg_safe_bm); |
| return 0; |
| } |