/contrib/toolchain/avra/.gitignore |
---|
0,0 → 1,5 |
archives |
releases |
patches |
*.o |
*.exe |
/contrib/toolchain/avra/doc/ChangeLog.html |
---|
0,0 → 1,763 |
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" |
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<title>AVRA ChangeLog</title> |
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<div id="layout-banner"> |
<div id="layout-title">AVRA</div> |
<div id="layout-description">Assember for the Atmel AVR microcontroller family</div> |
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<tr valign="top"> |
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<div>»<a href="index.html">Home</a></div> |
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<div id="page-source">»<a href="ChangeLog.txt">Page Source</a></div> |
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<td> |
<div id="layout-content"> |
<div id="header"> |
<h1>AVRA ChangeLog</h1> |
</div> |
<div id="content"> |
<h2 id="_version_1_3_0_20100628">Version 1.3.0 (20100628)</h2> |
<div class="sectionbody"> |
<div class="paragraph"><p>by Jerry Jacobs</p></div> |
<div class="ulist"><div class="title">Additions and changes</div><ul> |
<li> |
<p> |
Added new targets, ATtiny13A, ATtiny24/A, ATtiny44/A, ATtiny84, ATtiny2313A, |
ATtiny4313, ATmega328P |
</p> |
</li> |
<li> |
<p> |
Added mingw32 support for building windows binairies from linux host |
</p> |
</li> |
<li> |
<p> |
Removed obsolete Dev-C++ for windows building |
</p> |
</li> |
<li> |
<p> |
Updated documentation and rewritten in asciidoc markup language |
</p> |
</li> |
</ul></div> |
<div class="ulist"><div class="title">Bug fixes</div><ul> |
<li> |
<p> |
<strong>FIXED</strong>: 1934647: Handle also <em>#</em> directives because include files don’t use <em>.</em> directives. |
</p> |
</li> |
<li> |
<p> |
<strong>FIXED</strong>: 1970530: Make whitespace character possible between function name and open bracket. |
</p> |
</li> |
<li> |
<p> |
<strong>FIXED</strong>: 1970630: Make line continuation possible with backslash as the last character of a line. |
</p> |
</li> |
<li> |
<p> |
<strong>FIXED</strong>: 2929406: Change incorrect argument --includedir to includepath. |
</p> |
</li> |
</ul></div> |
</div> |
<h2 id="_version_1_2_3_20071115">Version 1.2.3 (20071115)</h2> |
<div class="sectionbody"> |
<div class="paragraph"><p>by Burkhard Arenfeld</p></div> |
<div class="ulist"><ul> |
<li> |
<p> |
Fix bug 1697037 (Error with single character <em>;</em>) |
</p> |
</li> |
<li> |
<p> |
Better check for line termination. Now a single CR or a FF generates an warning message. Code with bad CR |
termination could appear, if you edit CR-LF terminated files (WIN/DOS) with linux (LF only) editors. |
</p> |
</li> |
<li> |
<p> |
Add patch 1604128 from Jim Galbraith (New devices ATtiny25/45/85, small fix for ATmega8 (no jmp, call instruction)) |
</p> |
</li> |
<li> |
<p> |
Fix bug in handling of special tags (%HOUR% …). A % without a special tag was replaced by previous tag value. |
</p> |
</li> |
<li> |
<p> |
Use a global timestamp for all functions which needs a time (pi→time). |
</p> |
</li> |
<li> |
<p> |
Fix bug in handling of unknown args (E.g.: avra --abc → Segfault). |
</p> |
</li> |
<li> |
<p> |
Fix segfault if .error directive without parameter is used. |
</p> |
</li> |
<li> |
<p> |
Add a warning, if characters with code > 127 are used in .db strings and fix listing output. |
</p> |
</li> |
<li> |
<p> |
Take a look at Testcode_avra-1_2_3.asm, which demonstrate some differences between 1.2.3 and previous releases |
</p> |
</li> |
<li> |
<p> |
AVR000.zip contains some header files for different devices. |
</p> |
</li> |
<li> |
<p> |
Included avra binary was created with ubuntu 7.10 linux |
</p> |
</li> |
</ul></div> |
<div class="ulist"><div class="title">Bug fixes</div><ul> |
<li> |
<p> |
<strong>FIXED</strong>: 1462900: Segfault, if error in -D parameter. |
</p> |
</li> |
<li> |
<p> |
<strong>FIXED</strong>: 1742436: Error in .dseg size check. |
</p> |
</li> |
<li> |
<p> |
<strong>FIXED</strong>: 1742437: Error in EEPROM presence check |
</p> |
</li> |
</ul></div> |
</div> |
<h2 id="_version_1_2_2_20070511">Version 1.2.2 (20070511)</h2> |
<div class="sectionbody"> |
<div class="paragraph"><p>by Burkhard Arenfeld</p></div> |
<div class="ulist"><ul> |
<li> |
<p> |
Check in print_msg() if filename is NULL. Avoid printing a NULL-Pointer. |
</p> |
</li> |
<li> |
<p> |
Warning, if no .DEVICE was found, because address range check doesn’t work without it |
</p> |
</li> |
<li> |
<p> |
Error, if more than one .DEVICE was found. |
</p> |
</li> |
<li> |
<p> |
Error, if .DEVICE is after any assembled code or .ORG directive, because .DEVICE resets the address |
counters and the assembler builds wrong code. |
</p> |
</li> |
<li> |
<p> |
Create a list of program segments (see orglist). Every .ORG, .DEVICE, .?SEG is stored, so the |
assembler now can check for overlapping segments. Now overlapped segments in Flash, Data or EEPROM memory |
are detected. Very usefull, if .ORG is used to build tables or bootloader code at specific addresses. |
</p> |
</li> |
<li> |
<p> |
Better check for exceeding device space in RAM, Flash or EEPROM memory. Now not the total count of |
assembled memory is used, instead every assembled address range is checked. |
</p> |
</li> |
<li> |
<p> |
.DSEG and .ESEG now generates an error, if device has no RAM / EEPROM. |
</p> |
</li> |
<li> |
<p> |
Now a warning appears, if a .DEF name is already used as constant or label. Atmel assembler generates this |
warning, too. |
</p> |
</li> |
<li> |
<p> |
Fix a small bug in the example program. |
</p> |
</li> |
</ul></div> |
</div> |
<h2 id="_version_1_2_1_20061117">Version 1.2.1 (20061117)</h2> |
<div class="sectionbody"> |
<div class="paragraph"><p>by Roland Riegel</p></div> |
<div class="ulist"><ul> |
<li> |
<p> |
Some of the high end AVRs use the SRAM adress range from 0x60 to 0x100 for IO extension. |
Avra so far used to start with SRAM Usage at 0x60. This is now set from case by case. |
</p> |
</li> |
</ul></div> |
</div> |
<h2 id="_version_1_2_0_20061015">Version 1.2.0 (20061015)</h2> |
<div class="sectionbody"> |
<div class="paragraph"><p>by Burkhard Arenfeld</p></div> |
<div class="ulist"><ul> |
<li> |
<p> |
Patch segfault, if .error is given without parameter |
</p> |
</li> |
<li> |
<p> |
Patch segfault, if .device is given with an invalid parameter |
</p> |
</li> |
<li> |
<p> |
Check in predef_dev() if symbol is already defined. Can happens, if someone |
tries to define the symbol with the -D parameter. E.g.: <em>avra -D <em>ATMEGA8</em> Test.asm</em> |
now generate error message, because <em>ATMEGA8</em> is reserved |
</p> |
</li> |
<li> |
<p> |
Add .elseif directive. It’s the same like .elif. (Original Atmel assembler use .elseif |
and not .elif) |
</p> |
</li> |
<li> |
<p> |
In .db lines strings can now contain <em>,</em> and <em>;</em> characters. |
</p> |
</li> |
<li> |
<p> |
Allow forward declaration of constants (.equ) except for .ifdef and .ifndef. |
Invalid forward declarations are checked now. (In the first pass undefined Symbols in |
.ifdef and .ifndef parameters are stored in a <em>blacklist</em> and checked in the second pass) |
</p> |
</li> |
<li> |
<p> |
Extend the .message directive for better debugging. Now it accept not only a String. |
You can use a list of expressions like in a .db directive as parameter. |
</p> |
</li> |
<li> |
<p> |
The assembler <em>pass</em> variable moved into the pi struct. I deleted the pass variable from |
a lot of functions. |
</p> |
</li> |
<li> |
<p> |
New functions in avra.c. It was easier for me, to understand the code without the |
for(label = first; …)-loops. Replaced a lot of for(label = …) -loops by one of this |
functions. |
</p> |
</li> |
</ul></div> |
</div> |
<h2 id="_version_1_1_1_20060906">Version 1.1.1 (20060906)</h2> |
<div class="sectionbody"> |
<div class="ulist"><ul> |
<li> |
<p> |
right shift operator bug |
</p> |
</li> |
<li> |
<p> |
LPM is supported on ATtiny26 but avra say it isn’t |
</p> |
</li> |
<li> |
<p> |
bugfix for jmp/call opcode |
</p> |
</li> |
<li> |
<p> |
crash due to a strcmp with null pointer when parsing the cmd line args |
</p> |
</li> |
</ul></div> |
</div> |
<h2 id="_version_1_1_0_20051227">Version 1.1.0 (20051227)</h2> |
<div class="sectionbody"> |
<div class="paragraph"><p>by Tobias Weber</p></div> |
<div class="ulist"><ul> |
<li> |
<p> |
.DW defines were missing in the listfile. |
</p> |
</li> |
<li> |
<p> |
Support for mega8515. |
</p> |
</li> |
<li> |
<p> |
Fix for generic register names and extended macro syntax. |
</p> |
</li> |
<li> |
<p> |
Makefile for lcc-win32 Compiler. |
</p> |
</li> |
<li> |
<p> |
Changed "global" keyword to ".global". |
</p> |
</li> |
<li> |
<p> |
Added .includepath directive that allows setting include path. |
</p> |
</li> |
<li> |
<p> |
segfault when not passing any sourcefiles. |
</p> |
</li> |
<li> |
<p> |
--define FOO=2 does not work as claimed by the documentation. |
</p> |
</li> |
<li> |
<p> |
Added return value, indicating whether avra failed or succeded. |
</p> |
</li> |
<li> |
<p> |
Added support for automake utilities. See manual for more info. |
</p> |
</li> |
<li> |
<p> |
if no code is present, eeprom hex file will be written anyway. |
</p> |
</li> |
<li> |
<p> |
added -W NoRegDef for suppressing Register assignment warnings. |
</p> |
</li> |
<li> |
<p> |
.db values were sometimes wrong printed in lst file with 6 leading F. |
</p> |
</li> |
<li> |
<p> |
Added BYTE1() function equivalent to LOW(). |
</p> |
</li> |
<li> |
<p> |
The character " (pharentesis) could not be use as single character like <em>"</em> |
</p> |
</li> |
</ul></div> |
</div> |
<h2 id="_version_1_0_1_20040610">Version 1.0.1 (20040610)</h2> |
<div class="sectionbody"> |
<div class="paragraph"><p>by Tobias Weber</p></div> |
<div class="ulist"><ul> |
<li> |
<p> |
Added meta tags for time and date. |
</p> |
</li> |
<li> |
<p> |
Expression of .elif was cutted off in list file - fixed. |
</p> |
</li> |
<li> |
<p> |
.equ, .org, .defines added to list file output. |
</p> |
</li> |
<li> |
<p> |
Values and expressions of .db assignemts are now listed in listfile. |
</p> |
</li> |
<li> |
<p> |
Added Support for ATmega48, ATmega88 and ATmega168. |
</p> |
</li> |
<li> |
<p> |
Added .include error file name print out. |
</p> |
</li> |
<li> |
<p> |
Fixed seg fault that could happen while using .LIST directive with no |
listfile switched on. |
</p> |
</li> |
<li> |
<p> |
Error when using comments within macros that made use of sign @ fixed. |
</p> |
</li> |
<li> |
<p> |
Listfile lines are now prefixed with the current segment C,D,E for |
code, data and eeprom. |
</p> |
</li> |
</ul></div> |
</div> |
<h2 id="_version_1_0_0_20040214">Version 1.0.0 (20040214)</h2> |
<div class="sectionbody"> |
<div class="paragraph"><p>by Tobias Weber</p></div> |
<div class="ulist"><ul> |
<li> |
<p> |
Added support for ATtiny13 and ATtiny2313 |
</p> |
</li> |
<li> |
<p> |
List file command line syntax now AVRASM compatible |
</p> |
</li> |
<li> |
<p> |
Map file command line syntax now AVRASM compatible |
</p> |
</li> |
<li> |
<p> |
Fixed problem with limited macro label running numbers |
</p> |
</li> |
<li> |
<p> |
Now multiple labels can be used within macros |
</p> |
</li> |
<li> |
<p> |
Fixed error output line number for included files |
</p> |
</li> |
<li> |
<p> |
code cleaned up |
</p> |
</li> |
</ul></div> |
</div> |
<h2 id="_version_0_9_1_20030602">Version 0.9.1 (20030602)</h2> |
<div class="sectionbody"> |
<div class="paragraph"><p>by Tobias Weber</p></div> |
<div class="ulist"><ul> |
<li> |
<p> |
fixed code for Linux compiler |
</p> |
</li> |
<li> |
<p> |
fixed nested macro labels |
</p> |
</li> |
<li> |
<p> |
code cleaned up |
</p> |
</li> |
</ul></div> |
</div> |
<h2 id="_version_0_9_20030523">Version 0.9 (20030523)</h2> |
<div class="sectionbody"> |
<div class="paragraph"><p>by Tobias Weber</p></div> |
<div class="ulist"><ul> |
<li> |
<p> |
Added labels to macros |
</p> |
</li> |
<li> |
<p> |
Added special codes <em>dst</em> and <em>src</em> |
</p> |
</li> |
<li> |
<p> |
Added directive .endmacro, only .endm was allowed so far |
</p> |
</li> |
<li> |
<p> |
Added a return(0); at the end of main() to quiet the Borland C++ 5.5 |
compiler (Jim Galbraith) |
</p> |
</li> |
<li> |
<p> |
Fixed wrong flash size calculation (Jim Galbraith) |
</p> |
</li> |
<li> |
<p> |
In device.c, added ATtiny26 to struct device device_list[] (Jim Galbraith) |
</p> |
</li> |
</ul></div> |
</div> |
<h2 id="_version_0_8_20030307">Version 0.8 (20030307)</h2> |
<div class="sectionbody"> |
<div class="paragraph"><p>by Tobias Weber</p></div> |
<div class="ulist"><ul> |
<li> |
<p> |
Added new macro assembler coding facilities |
</p> |
</li> |
<li> |
<p> |
Added error description for .include directives |
</p> |
</li> |
</ul></div> |
</div> |
<h2 id="_version_0_7_20000217">Version 0.7 (20000217)</h2> |
<div class="sectionbody"> |
<div class="ulist"><ul> |
<li> |
<p> |
Added supported() function to check in a .if if a instruction is |
supported (From Lesha Bogdanow <<a href="mailto:boga@inbox.ru">boga@inbox.ru</a>>). |
</p> |
</li> |
<li> |
<p> |
Added checking of which mnemonic that work on the different AVRs |
(From Lesha Bogdanow <<a href="mailto:boga@inbox.ru">boga@inbox.ru</a>>). |
</p> |
</li> |
<li> |
<p> |
Added constants <em>DEVICE</em>, <em>FLASH_SIZE</em>, <em>RAM_SIZE</em> and |
<em>EEPROM_SIZE</em> (From Lesha Bogdanow <<a href="mailto:boga@inbox.ru">boga@inbox.ru</a>>). |
</p> |
</li> |
<li> |
<p> |
Added tiny devices (From Lesha Bogdanow <<a href="mailto:boga@inbox.ru">boga@inbox.ru</a>>). |
</p> |
</li> |
<li> |
<p> |
Changed error on constant out of range into a warning. |
</p> |
</li> |
<li> |
<p> |
Added support for instructions: (E)LPM Rd,Z(+), SPM, ESPM, BREAK, |
MOVW, MULS, MULSU, FMUL, FMULS, FMULSU |
</p> |
</li> |
<li> |
<p> |
Added support for new devices: ATmega8, ATmega16, ATmega32, |
ATmega128, ATmega162, ATmega163, ATmega323, AT94K |
</p> |
</li> |
<li> |
<p> |
Added --devices switch to list all supported devices. |
</p> |
</li> |
<li> |
<p> |
Fixed bug in map file name when the name had more than one . (dot) |
</p> |
</li> |
<li> |
<p> |
Added option --includedirs to add additional include dirs in |
search path. |
</p> |
</li> |
<li> |
<p> |
Added support for creation of intel hex 32 files to be able to |
address memory above 64KB. Uses 02 records for addresses up to 1MB |
and 04 record for addresses above 1MB. |
</p> |
</li> |
</ul></div> |
</div> |
<h2 id="_version_0_6_20000124">Version 0.6 (20000124)</h2> |
<div class="sectionbody"> |
<div class="ulist"><ul> |
<li> |
<p> |
Added COFF support from Bob Harris <<a href="mailto:rth@McLean.Sparta.Com">rth@McLean.Sparta.Com</a>> |
</p> |
</li> |
</ul></div> |
</div> |
<h2 id="_version_0_5_19990331">Version 0.5 (19990331)</h2> |
<div class="sectionbody"> |
<div class="ulist"><ul> |
<li> |
<p> |
Bugfix: a inline string copy did not terminate string. |
</p> |
</li> |
<li> |
<p> |
Fixed bug causing --define symbol=value not to work. |
</p> |
</li> |
<li> |
<p> |
Added output of memory usage. |
</p> |
</li> |
<li> |
<p> |
Fixed bug when there was a { in a comment. |
</p> |
</li> |
<li> |
<p> |
Fixed count for data segment. |
</p> |
</li> |
<li> |
<p> |
Fix to make a forward referenced label in .db/.dw work. |
</p> |
</li> |
<li> |
<p> |
Added ATmega161 and ATtiny15 in list. |
</p> |
</li> |
<li> |
<p> |
rjmp and rcall now wraps around with 4k word devices. |
</p> |
</li> |
<li> |
<p> |
Fixed bug when branching backwards with BRBS or BRBC |
</p> |
</li> |
</ul></div> |
</div> |
<h2 id="_version_0_4_19990202">Version 0.4 (19990202)</h2> |
<div class="sectionbody"> |
<div class="ulist"><ul> |
<li> |
<p> |
Added support for global keyword to use on labels in macros. |
</p> |
</li> |
<li> |
<p> |
Fixed get_next_token to handle commas inside ' ' |
</p> |
</li> |
<li> |
<p> |
Fixed bug when searching for correct macro_call, so recursive |
and nested macros will work. |
</p> |
</li> |
<li> |
<p> |
Now handles commas in strings. |
</p> |
</li> |
<li> |
<p> |
Added fix to handle semi colon in a string. |
</p> |
</li> |
<li> |
<p> |
Improved mnemonic parsing for ld and st |
</p> |
</li> |
</ul></div> |
</div> |
</div> |
<div id="footnotes"><hr /></div> |
<div id="footer"> |
<div id="footer-text"> |
Version 1.3.0<br /> |
Last updated 2010-06-28 16:04:24 CEST |
</div> |
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/contrib/toolchain/avra/doc/Makefile |
---|
0,0 → 1,55 |
### |
# Sourceforge helper Makefile |
### |
USER=jerryjacobs |
HOSTNAME=shell.sourceforge.net |
PROJECT=avra |
HTDOCS=/home/groups/a/av/avra/htdocs |
all: help |
upload: htdocs_scp htdocs_chmod |
### |
# Help message |
### |
help: |
@echo "No command specified! Available commands:" |
@echo |
@echo "Current settings" |
@echo "----------------" |
@echo " User: ${USER}" |
@echo " Hostname: ${HOSTNAME}" |
@echo " Project: ${PROJECT}" |
@echo " Remote htdoc: ${HTDOCS}" |
@echo |
@echo "Shell commands" |
@echo "--------------" |
@echo " * shell, open a shell" |
@echo " * shell_create, create a shell" |
@echo |
@echo "htdocs commands" |
@echo "---------------" |
@echo " * htdocs_scp, copy all files from current dir to remote htdocs" |
@echo " * htdocs_rm, remove all files from remote htdocs" |
### |
# Shell |
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shell: |
ssh ${USER},${PROJECT}@${HOSTNAME} |
shell_create: |
ssh ${USER},${PROJECT}@${HOSTNAME} create |
### |
# htdocs |
### |
htdocs_scp: |
scp -r * ${USER}@${HOSTNAME}:${HTDOCS} |
htdocs_chmod: |
ssh ${USER}@${HOSTNAME} chmod -Rv ug+rw ${HTDOCS}/* |
htdocs_rm: |
ssh ${USER}@${HOSTNAME} rm -Rv ${HTDOCS}/* |
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<div id="header"> |
<h1>README</h1> |
</div> |
<div id="content"> |
<h2 id="_general_and_licensing_information">General and licensing information</h2> |
<div class="sectionbody"> |
<div class="paragraph"><p>AVRA v1.3.0 - Assember for the Atmel AVR microcontroller family</p></div> |
<h3 id="_licensing_information">Licensing information</h3><div style="clear:left"></div> |
<div class="paragraph"><p>This program is free software; you can redistribute it and/or modify |
it under the terms of the GNU General Public License as published by |
the Free Software Foundation; either version 2 of the License, or |
(at your option) any later version. Please read below for for information.</p></div> |
<h3 id="_disclaimer">Disclaimer</h3><div style="clear:left"></div> |
<div class="paragraph"><p>This program is distributed in the hope that it will be useful, but |
WITHOUT ANY WARRANTY; without even the implied warranty of |
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
GNU General Public License for more details.</p></div> |
<h3 id="_gnu_general_public_license">GNU General Public License</h3><div style="clear:left"></div> |
<div class="paragraph"><p>You should have received a copy of the GNU General Public License |
along with this program; see the file "COPYING". If not, visit |
<a href="http://www.gnu.org">http://www.gnu.org</a> or write to the Free Software Foundation, Inc., |
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. You can |
also contact the authors of AVRA to receive a copy of the COPYING file.</p></div> |
<h3 id="_trademarks_and_copyright">Trademarks and copyright</h3><div style="clear:left"></div> |
<div class="paragraph"><p>Atmel, AVR, AVR Studio, Intel, Windows are registered enterprises, brands |
and registered trademarks. The mentioned companies have no relation to |
AVRA and are therefore not responslible for any problems that occur when |
using AVRA. Many thanks for your products, support and efforts.</p></div> |
</div> |
<h2 id="_introducion">Introducion</h2> |
<div class="sectionbody"> |
<div class="paragraph"><p>AVRA is an assembler for Atmel AVR microcontrollers, and it is almost |
compatible with Atmel’s own assembler AVRASM32. The programming |
principles and conceptions are based on the ANSI programming language "C".</p></div> |
<div class="paragraph"><p>The initial version of AVRA was written by John Anders Haugum. He released |
all versions until v0.7. All later versions were released by Tobias Weber.</p></div> |
<h3 id="_differences_between_avra_and_avrasm32">Differences between AVRA and AVRASM32</h3><div style="clear:left"></div> |
<div class="paragraph"><p>There are some differences between the original Atmel assembler AVRASM32 and AVRA. Basically AVRA is designed to replace AVRASM32 without special changes in your current Atmel AVR Studio enviroment. |
Command line options have been adapted as far as it was possible until now. Jumping to fault containing line directly by double-clicking on the error message in the output window does work as with AVRASM32.</p></div> |
<h3 id="_the_differences_in_detail">The differences in detail</h3><div style="clear:left"></div> |
<div class="ulist"><ul> |
<li> |
<p> |
Support for some extra preprocessor directives. |
</p> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>.define, .undef, .ifdef, .ifndef, .if, .else, .endif, .elif, .elseif, .warning</tt></pre> |
</div></div> |
</li> |
<li> |
<p> |
Not all command line options are supported. |
Specifying an eeprom file (-e) is not supported. All eeprom data is |
put out into a file called program.eep.hex and always Intel hex |
format. Other hex file formats than Intel are currently not supported. |
</p> |
</li> |
<li> |
<p> |
Forward references not supported for .ifdef and .ifndef directives. |
This makes sure, that directives like .ifdef and .undef are working |
properly. If you are familiar with the C programming language, you |
should get easily into AVRA. See chapter "Programming techniques" for |
more information about how to write proper code. |
</p> |
</li> |
<li> |
<p> |
Enhanced macro support |
AVRA has some new features for writing flexible macros. This should |
increase the ability to reuse code e.g. build your own library. |
</p> |
</li> |
<li> |
<p> |
Debugging support |
AVRA creates a coff file everytime the assembly was sucessful. This |
file allows AVR Studio or any coff compatible debugger to simulate |
or emulate the program. |
</p> |
</li> |
<li> |
<p> |
Meta tags for assembly time |
This helps you tracking versions of your software and can also be |
used to generate customer specific serial numbers. |
</p> |
</li> |
</ul></div> |
<h3 id="_compatibility">Compatibility</h3><div style="clear:left"></div> |
<div class="paragraph"><p>Since AVRA is written in ANSI C, it should be possible to compile it on |
most system platforms. If you have problems compiling AVRA, please leave |
a message on the sourceforge message board or send a mail to the |
authors of AVRA.</p></div> |
</div> |
<h2 id="_installation">Installation</h2> |
<div class="sectionbody"> |
<div class="paragraph"><p>To install avra you should copy the avra-executable to an apropriate |
location. To compile you should rename the appropriate makefile, and |
perform a make (use smake for Amiga SAS/C, and nmake for Mickeysoft |
visual c++).</p></div> |
<h3 id="_linux">Linux</h3><div style="clear:left"></div> |
<div class="paragraph"><p>To compile avra you need gcc and the automake utilities. These will create |
a ./configure script that evaluates your system enviroment. To get the |
AVRA executable, you have to issue the following commands:</p></div> |
<div class="paragraph"><p>aclocal |
autoconf |
automake -a |
./configure |
make && make install</p></div> |
<h3 id="_amigaos">AmigaOS</h3><div style="clear:left"></div> |
<div class="paragraph"><p>avra can be copied any apropriate directory. If you are using the source |
distribution a <em>make install</em> will do the same.</p></div> |
<h3 id="_microsoft_windows">Microsoft Windows</h3><div style="clear:left"></div> |
<div class="paragraph"><p>If you received the Windows binary package, look into the \bin |
directory where you can find avra.exe. This should be copied to any |
apropriate location. You can also overwrite AVRASM32.EXE in your |
Atmel AVR Studio. If you want to compile it yourself you could download then |
OpenWatcom C/C++ Toolchain for windows and create a new project and add the C |
and H files to it and compile.</p></div> |
<h3 id="_apple_os_x">Apple OS X</h3><div style="clear:left"></div> |
<div class="paragraph"><p>If you recieved the Apple OS X binary package, look into the bin directory this |
file is compiled universal and should run on intel 32 and 64 bit and powerpc. If |
you want to compile it yourself go to the src directory and invoke <tt>make -f |
makefiles/Makefiles.osx</tt> and then the executable should be created.</p></div> |
</div> |
<h2 id="_synopsis">Synopsis</h2> |
<div class="sectionbody"> |
<h3 id="_command_line_usage">Command line usage</h3><div style="clear:left"></div> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>usage: AVRA [-f][O|M|I|G] output file type |
[-o <filename>] output file name |
[-l <filename>] generate list file |
[-m <mapfile>] generate map file |
[--define <symbol>[=<value>]] [--includedir <dir>] [--listmac] |
[--max_errors <number>] [--devices] [--version] |
[-h] [--help] general help |
[-W NoRegDef] supress register redefinition warnings |
<file to assemble></tt></pre> |
</div></div> |
<h3 id="_parameter_list">Parameter list</h3><div style="clear:left"></div> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>--listfile -l : Create list file |
--mapfile -m : Create map file |
--define -D : Define symbol. |
--includedir -I : Additional include dirs. |
--listmac : List macro expansion in listfile. |
--max_errors : Maximum number of errors before exit |
(default: 10) |
--devices : List out supported devices. |
--version : Version information. |
--help, -h : This help text.</tt></pre> |
</div></div> |
<h3 id="_warning_supression">Warning supression</h3><div style="clear:left"></div> |
<div class="paragraph"><p>Since avra 1.1 there is a possibility to supress certain warnings. |
Currently only register reassignment warnings can be supressed.</p></div> |
<div class="paragraph"><p>Example: avra -W NoRegDef</p></div> |
</div> |
<h2 id="_programming_techniques">Programming techniques</h2> |
<div class="sectionbody"> |
<h3 id="_using_directives">Using directives</h3><div style="clear:left"></div> |
<div class="paragraph"><p>AVRA offers a number of directives that are not part of Atmel’s |
assembler. These directives should help you creating versatile code that |
can be designed more modular.</p></div> |
<h4 id="_directive_define">Directive .define</h4> |
<div class="paragraph"><p>To define a constant, use ".define". This does the same thing as ".equ", |
it is just a little more C style. Keep in mind that AVRA is not case |
sensitive. Do not mix ".def" and ".define", because ".def" is used to |
assign registers only. This is due to backward compatibility to Atmel’s |
AVRASM32. Here is an example on how .define can be used.</p></div> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>.define network 1</tt></pre> |
</div></div> |
<div class="paragraph"><p>Now "network" is set to the value 1. You may want to assemble a specific |
part of your code depeding on a define or switch setting. You can test |
your defined word on existence (.ifdef and .ifndef) as well as on the |
value it represents. The following code shows a way to prevent error |
messages due to testing undefined constants. Conditional directives must |
always end with an .endif directive.</p></div> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>.ifndef network |
.define network 0 |
.endif</tt></pre> |
</div></div> |
<h4 id="_directive_if_and_else">Directive .if and .else</h4> |
<div class="paragraph"><p>The three lines in the last example set the default value of "network". |
In the next example, you see how we can use default values. If a constant |
has not defined previously, it is set to zero. Now you can test wether |
e.g. network support is included into the assemby process.</p></div> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>.if network = 1 |
.include "include\tcpip.asm" |
.else |
.include "include\dummynet.asm" |
.endif</tt></pre> |
</div></div> |
<div class="paragraph"><p>In the second part of the above listing you see the use of .else, which |
defines the part of the condition that is being executed if the equation |
of the preceding .if statement is not equal. You can also use the else |
statement to test another equasion. For that purpose use .elif, which |
means "else if". Always close this conditional part with ".endif"</p></div> |
<h4 id="_directive_error">Directive .error</h4> |
<div class="paragraph"><p>This directive can be used to throw errors if a part in the code has reached |
that should not be reached. The following example shows how we can stop |
the assembly process if a particular value has not been previously set.</p></div> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>.ifndef network |
.error "network is not configured!" ;the assembler stops here</tt></pre> |
</div></div> |
<h4 id="_directive_nolist_and_list">Directive .nolist and .list</h4> |
<div class="paragraph"><p>The ouput to the list file can be paused by this two directives. After |
avra discovers a .nolist while assembling, it stops output to the list file. |
After a .list directive is detected, it continues the normal list file output.</p></div> |
<h4 id="_directive_includepath">Directive .includepath</h4> |
<div class="paragraph"><p>By default, any file that is included from within the source file must |
either be a single filename or a complete absolute path. With the directive |
.includepath you can set an additional include path . Furthermore you can |
set as many include paths as you want. Be sure not no use same filename |
in separate includes, because then it is no longer clear which one avra |
should take.</p></div> |
</div> |
<h2 id="_using_include_files">Using include files</h2> |
<div class="sectionbody"> |
<div class="paragraph"><p>To avoid multiple inclusions of include files, you may use some pre- |
processor directives. See example file stack.asm that is being included |
into the main programm file as well as in other include files.</p></div> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>.ifndef _STACK_ASM_ |
.define _STACK_ASM_</tt></pre> |
</div></div> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>.include "include/config.inc"</tt></pre> |
</div></div> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>; *** stack macro ***</tt></pre> |
</div></div> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>.dseg |
m_stack: .byte __stack_size__ |
.cseg</tt></pre> |
</div></div> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>.macro stack_setup |
load [v:w,m_stack + __stack_size__] |
outp [SPREG,v:w] |
.endm</tt></pre> |
</div></div> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>.endif ; avoid multiple inclusion of stack.asm</tt></pre> |
</div></div> |
<h3 id="_using_build_date_meta_tags">Using build date meta tags</h3><div style="clear:left"></div> |
<div class="paragraph"><p>If you like to implement compiler build time and date into your |
program, you can make use of some sepcial tags that avra supports.</p></div> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>%MINUTE% is being replaced by the current minute (00-59) |
%HOUR% is being replaced by the current hour (00-23) |
%DAY% is being replaced by the current day of month (01-31) |
%MONTH% is being replaced by the current month (01-12) |
%YEAR% is being replaced by the current year (2004-9999)</tt></pre> |
</div></div> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>buildtime: .db "Release date %DAY%.%MONTH%.%YEAR% %HOUR%:%MINUTE%"</tt></pre> |
</div></div> |
<div class="paragraph"><p>This line will then assembled by avra into:</p></div> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>buildtime: .db "Release date 10.05.2004 19:54"</tt></pre> |
</div></div> |
<div class="paragraph"><p>You may also create a self defined serial number with meta tags:</p></div> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>.define serialnumber %DAY% + %MONTH%*31 + (%YEAR% - 2000) *31*12</tt></pre> |
</div></div> |
<div class="paragraph"><p>The %TAG% is translated before any other parsing happens. The real |
output can be found in the list file.</p></div> |
</div> |
<h2 id="_macro_features">Macro features</h2> |
<div class="sectionbody"> |
<div class="paragraph"><p>Sometimes you have to work with 16 bit or greater variables stored |
in 8 bit registers. The enhanced macro support allows you to write short |
and flexible macros that simplify access to big variables. The extended |
mode is active, as soon as you use parenthesis like this "[ ]" to wrap |
macro parameters.</p></div> |
<h3 id="_auto_type_conversion_for_macros">Auto type conversion for macros</h3><div style="clear:left"></div> |
<div class="paragraph"><p>Values representing more than 8 Bits are usualy kept in a set of byte |
wide registers. To simplify 16 Bit or greater operations, I added a new |
language definitions. Words can be written as r16:r17, whereas register |
r16 contains the higher part and register r17 the lower part of this |
16 Bit value.</p></div> |
<h4 id="_macro_data_types">Macro data types</h4> |
<div class="paragraph"><p>There are 3 data types that can be used. They will be added as character |
separated by one underline character.</p></div> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>immediate values _i |
registers _8,_16,_24,_32,_40,_48,_56,_64 |
void parameter _v</tt></pre> |
</div></div> |
<div class="paragraph"><p>16 Bit Source and Destionation registers <em>dst</em> and <em>src</em></p></div> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>src = YH:YL |
dst = ZH:ZL</tt></pre> |
</div></div> |
<div class="paragraph"><p>Within the parenthesis, the two words src and dst are interpreted as YH:YL |
and ZH:ZL. Normal code outside of the macro parameter parenthesis can |
still make use of these special key words "src" and "dst".</p></div> |
<h4 id="_examples_for_automatic_type_conversion">Examples for automatic type conversion</h4> |
<div class="paragraph"><p>To simplify the parameters in the demonstration below, we need to |
redefine some registers.</p></div> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>.def a = r16 ; general purpose registers |
.def b = r17 |
.def c = r18 |
.def d = r19</tt></pre> |
</div></div> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>.def w = r20 ; working register |
.def v = r21 ; working register</tt></pre> |
</div></div> |
<div class="paragraph"><p>If we substract 16 Bit values stored in a, higher byte and b, lower byte |
with that in c:d, we usually have to use the following command sequence:</p></div> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>sub b,d |
sbc a,c</tt></pre> |
</div></div> |
<div class="paragraph"><p>Now we can do the following steps to simplify 16 or more Bit manipulations</p></div> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>.macro subs |
.message "no parameters specified" |
.endm</tt></pre> |
</div></div> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>.macro subs_16_16 |
sub @1,@3 |
sbc @0,@2 |
.endm</tt></pre> |
</div></div> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>.macro subs_16_8 |
sub @1,@2 |
sbci @0,0 |
.endm</tt></pre> |
</div></div> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>;now we can write a 16 Bit subraction as:</tt></pre> |
</div></div> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>subs [a:b,c:d]</tt></pre> |
</div></div> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>;or for calculating 16 minus 8 Bit</tt></pre> |
</div></div> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>subs [a:b,c]</tt></pre> |
</div></div> |
<h3 id="_overloading_macros">Overloading macros</h3><div style="clear:left"></div> |
<div class="paragraph"><p>Like in you are used to C functions, you can write macros for different |
parameter lists. If you would like to have a versatile macro, you can |
specify a unique macro for each parameter situation. See the next sample.</p></div> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>.macro load</tt></pre> |
</div></div> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>; this message is shown if you use the macro within your code |
; specifying no parameters. If your macro allows the case where |
; no parameters are given, exchange .message with your code.</tt></pre> |
</div></div> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>.message "no parameters specified" |
.endm</tt></pre> |
</div></div> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>; Here we define the macro "load" for the case it is being used |
; with two registers as first parameter and a immediate (constant) |
; value as second parameter.</tt></pre> |
</div></div> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>.macro load_16_i |
ldi @0,high(@2) |
ldi @1,low(@2) |
.endm</tt></pre> |
</div></div> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>; the same case, but now with a 32 bit register value as first |
; parameter</tt></pre> |
</div></div> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>.macro load_32_i |
ldi @0,BYTE4(@4) |
ldi @1,BYTE3(@4) |
ldi @2,high(@4) |
ldi @3,low(@4) |
.endm</tt></pre> |
</div></div> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>; Now let's see how these macros are being used in the code</tt></pre> |
</div></div> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>load [a:b,15] ;uses macro load_16_i to load immediate</tt></pre> |
</div></div> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>load [a:b:c:d,15] ;uses macro load_32_i to load immediate</tt></pre> |
</div></div> |
<h3 id="_more_examples">More examples</h3><div style="clear:left"></div> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>.dseg |
counter .byte 2 |
.cseg</tt></pre> |
</div></div> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>.macro poke |
.message "no parameters" |
.endm</tt></pre> |
</div></div> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>.macro poke_i_16_i |
ldi @1,high(@3) |
sts @0+0,@1 |
ldi @2,low(@3) |
sts @0+1,@2 |
.endm</tt></pre> |
</div></div> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>.macro poke_i_i |
ldi w,@1 |
sts @0+0,w |
.endm</tt></pre> |
</div></div> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>.macro poke_i_v_i |
ldi w,high(@3) |
sts @0+0,w |
ldi w,low(@3) |
sts @0+1,w |
.endm</tt></pre> |
</div></div> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>.macro poke_i_v_v_v_i |
ldi w,high(@3) |
sts @0+0,w |
ldi w,low(@3) |
sts @0+1,w |
ldi w,BYTE3(@3) |
sts @0+2,w |
ldi w,BYTE4(@3) |
sts @0+3,w |
.endm</tt></pre> |
</div></div> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>; this writes '9999' into the memory at 'counter' |
; uses only the working register for transfering the values.</tt></pre> |
</div></div> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>poke [counter,w:w,9999]</tt></pre> |
</div></div> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>; works same as above, but the transferred value '9999' is also |
; kept in the pair of register a:b</tt></pre> |
</div></div> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>poke [counter,a:b,9999]</tt></pre> |
</div></div> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>; in my design 'w' is always working reg. which implies that |
; it cannot be used for normal variables. The following example |
; uses poke_i_i because the parameter contains two immediate values.</tt></pre> |
</div></div> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>poke [counter,9999] ;uses poke_i_i</tt></pre> |
</div></div> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>; to be able to choose between a 8,16 or 32 Bit operation, you just |
; add a void parameter.</tt></pre> |
</div></div> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>poke [counter,,9999] ;uses poke_i_v_i</tt></pre> |
</div></div> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>; and the same for 32 Bit pokes</tt></pre> |
</div></div> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>poke [counter,,,,9999] ;uses poke_i_v_v_v_i</tt></pre> |
</div></div> |
<h3 id="_loops_within_macros">Loops within macros</h3><div style="clear:left"></div> |
<div class="paragraph"><p>One problem you may have experienced, is that labels defined within macros |
are defined twice if you call the macro for example two times. Now you can |
use labels for macro loops. Loops within macros must end with <em>_%</em>. the |
"%" symbol is replaced by a running number.</p></div> |
<h4 id="_loop_example">Loop example</h4> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>; Definition of the macro</tt></pre> |
</div></div> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>.macro write_8_8 |
write_%: |
st Z+,@0 |
dec @1 |
brne write_% |
.endm</tt></pre> |
</div></div> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>; Use in user code</tt></pre> |
</div></div> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>write [a,b] |
write [c,d]</tt></pre> |
</div></div> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>; After assembling this code, the result looks like this</tt></pre> |
</div></div> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>write_1: |
st Z+,a |
dec b |
brne write_1 |
write_2: |
st Z+,c |
dec d |
brne write_2</tt></pre> |
</div></div> |
</div> |
<h2 id="_warnings_and_errors">Warnings and Errors</h2> |
<div class="sectionbody"> |
<div class="paragraph"><p>Some errors and warnings may confuse you a little bit so we will try to |
clear some frequently asked questions about such cases.</p></div> |
<h3 id="_constant_out_of_range">Constant out of range</h3><div style="clear:left"></div> |
<div class="paragraph"><p>This warning occurs if a value exceeds the byte or word value of a assignment. |
Read the comment posted by Jim Galbraith:</p></div> |
<div class="paragraph"><p>The expression (~0x80) is a Bitwise Not operation. This |
operator returns the input expression with all its bits |
inverted. If 0x80 represents -128, then 0x7f, or +127 |
should be ok. If this is considered as a 32-bit expression |
(AVRA internal representation), then it appears to be more |
like oxffffffff-0x80 or 0xffffffff<sup>0x80. The result would then |
be 0xffffff7f. The assembler would then have to be told or it |
would have to decide, based on context, how much |
significance to assign to the higher bits. I have also |
encountered such conditions with various assemblers, |
including AVRA. To make sure the assembler does what I |
really want, I use a construct like 0xff-0x80 or 0xff</sup>0x80. |
This way the bit significance cannot extend beyond bit-7 and |
there cannot be any misunderstanding.</p></div> |
<h3 id="_can_8217_t_use_db_directive_in_data_segment">Can’t use .DB directive in data segment</h3><div style="clear:left"></div> |
<div class="paragraph"><div class="title">DB and .DW is only used to assign constant data in eeprom or code space.</div><p>The reason why using it within data segment is forbidden is, that you |
cannot set ram content at assembly time. The values must be programmed into |
ROM area and at boot read from ROM into RAM. This is up to the user code. |
You can only allocate memory for your variables using labels and the .byte |
directive.</p></div> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>.dseg |
my_string: .byte 15</tt></pre> |
</div></div> |
<h3 id="_byte_directive">BYTE directive</h3><div style="clear:left"></div> |
<div class="paragraph"><div class="title">BYTE directive can only be used in data segment (.DSEG)</div><p>This directive cannot be used in code or eeprom region because this only |
allocates memory without assgning distinct values to it. Please use .db |
or .dw instead.</p></div> |
<h3 id="_internal_assembler_error">Internal assembler error</h3><div style="clear:left"></div> |
<div class="paragraph"><p>If you get an "Internal assembler error" please contact the project maintainer |
by sending him a code example and a description of your working enviroment.</p></div> |
</div> |
<h2 id="_avra_internals">AVRA internals</h2> |
<div class="sectionbody"> |
<div class="paragraph"><p>This section provides thoughts of the avra internal design. I have to admit |
that the code of avra is anything else than clean and optimized. To increase |
the code readability I will try to give you some standards that should improve |
quality. The following standards are similar to what GNU proposes.</p></div> |
<h3 id="_coding_standards">Coding standards</h3><div style="clear:left"></div> |
<div class="paragraph"><p>Tab space is always 2 spaces. The Tab character (ascii 9) is not used. |
if,while,for are always opened on the same line but closed on the next line. |
The closing bracket is in the same column as the first letter of the loop |
directive.</p></div> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>Example:</tt></pre> |
</div></div> |
<div class="listingblock"> |
<div class="content"> |
<pre><tt> while(i > 0) { |
do_something(); |
}</tt></pre> |
</div></div> |
</div> |
<h2 id="_credits">Credits</h2> |
<div class="sectionbody"> |
<div class="paragraph"><p>We would like to thank the following people for giving contributions, |
patches and bug reports, as well as suggestions and new ideas.</p></div> |
<div class="listingblock"> |
<div class="content"> |
<pre><tt> Jon Anders Haugum (project founder) |
Burkhard Arenfeld (release 1.2.0) |
Tobias Weber (old maintainer) |
Jerry Jacobs (release 1.3.0) |
Bernt Hembre |
Nils Strøm |
Roberto Biancardi |
Qwerty Jones |
Ben Hitchcock (Maker of the mac port) |
Daniel Drotos |
Laurence Boyd II |
Varuzhan Danielyan |
Laurence Turner |
Eugene R. O'Bryan |
Dmitry Dicky |
Bob Harris (Maker of coff support) |
Tobias Weber (enhanced macro support) |
Lesha Bogdanow |
Jim Galbraith |
Mark Brinicombe |
Igor Nikolayenko |
Peter Hettkamp |
Herb Poppe |
David Burke |
Alexey Pavluchenko |
Alan Probandt |
Mariusz Matuszek |
Arne Rossius |
Marti Tichacek |
Patrick Parity |
Johannes Overmann |
Roland Riegel |
Peter Katzmann |
Donald D. Davis</tt></pre> |
</div></div> |
<div class="paragraph"><p>And all the anonymous people who submitted patches!</p></div> |
<div class="paragraph"><p>Thank you for your work and support.</p></div> |
</div> |
<h2 id="_references">References</h2> |
<div class="sectionbody"> |
<div class="literalblock"> |
<div class="content"> |
<pre><tt>http://www.suprafluid.com/avra |
http://www.avrfreaks.de |
http://www.atmel.com</tt></pre> |
</div></div> |
</div> |
</div> |
<div id="footnotes"><hr /></div> |
<div id="footer"> |
<div id="footer-text"> |
Version 1.3.0<br /> |
Last updated 2010-06-28 16:04:26 CEST |
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/contrib/toolchain/avra/doc/README.txt |
---|
0,0 → 1,679 |
README |
====== |
General and licensing information |
--------------------------------- |
AVRA v1.3.0 - Assember for the Atmel AVR microcontroller family |
Licensing information |
~~~~~~~~~~~~~~~~~~~~~ |
This program is free software; you can redistribute it and/or modify |
it under the terms of the GNU General Public License as published by |
the Free Software Foundation; either version 2 of the License, or |
(at your option) any later version. Please read below for for information. |
Disclaimer |
~~~~~~~~~~ |
This program is distributed in the hope that it will be useful, but |
WITHOUT ANY WARRANTY; without even the implied warranty of |
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
GNU General Public License for more details. |
GNU General Public License |
~~~~~~~~~~~~~~~~~~~~~~~~~~ |
You should have received a copy of the GNU General Public License |
along with this program; see the file "COPYING". If not, visit |
http://www.gnu.org or write to the Free Software Foundation, Inc., |
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. You can |
also contact the authors of AVRA to receive a copy of the COPYING file. |
Trademarks and copyright |
~~~~~~~~~~~~~~~~~~~~~~~~ |
Atmel, AVR, AVR Studio, Intel, Windows are registered enterprises, brands |
and registered trademarks. The mentioned companies have no relation to |
AVRA and are therefore not responslible for any problems that occur when |
using AVRA. Many thanks for your products, support and efforts. |
Introducion |
----------- |
AVRA is an assembler for Atmel AVR microcontrollers, and it is almost |
compatible with Atmel's own assembler AVRASM32. The programming |
principles and conceptions are based on the ANSI programming language "C". |
The initial version of AVRA was written by John Anders Haugum. He released |
all versions until v0.7. All later versions were released by Tobias Weber. |
Differences between AVRA and AVRASM32 |
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
There are some differences between the original Atmel assembler AVRASM32 and AVRA. Basically AVRA is designed to replace AVRASM32 without special changes in your current Atmel AVR Studio enviroment. |
Command line options have been adapted as far as it was possible until now. Jumping to fault containing line directly by double-clicking on the error message in the output window does work as with AVRASM32. |
The differences in detail |
~~~~~~~~~~~~~~~~~~~~~~~~~ |
- Support for some extra preprocessor directives. |
.define, .undef, .ifdef, .ifndef, .if, .else, .endif, .elif, .elseif, .warning |
- Not all command line options are supported. |
Specifying an eeprom file (-e) is not supported. All eeprom data is |
put out into a file called program.eep.hex and always Intel hex |
format. Other hex file formats than Intel are currently not supported. |
- Forward references not supported for .ifdef and .ifndef directives. |
This makes sure, that directives like .ifdef and .undef are working |
properly. If you are familiar with the C programming language, you |
should get easily into AVRA. See chapter "Programming techniques" for |
more information about how to write proper code. |
- Enhanced macro support |
AVRA has some new features for writing flexible macros. This should |
increase the ability to reuse code e.g. build your own library. |
- Debugging support |
AVRA creates a coff file everytime the assembly was sucessful. This |
file allows AVR Studio or any coff compatible debugger to simulate |
or emulate the program. |
- Meta tags for assembly time |
This helps you tracking versions of your software and can also be |
used to generate customer specific serial numbers. |
Compatibility |
~~~~~~~~~~~~~ |
Since AVRA is written in ANSI C, it should be possible to compile it on |
most system platforms. If you have problems compiling AVRA, please leave |
a message on the sourceforge message board or send a mail to the |
authors of AVRA. |
Installation |
------------ |
To install avra you should copy the avra-executable to an apropriate |
location. To compile you should rename the appropriate makefile, and |
perform a make (use smake for Amiga SAS/C, and nmake for Mickeysoft |
visual c++). |
Linux |
~~~~~ |
To compile avra you need gcc and the automake utilities. These will create |
a ./configure script that evaluates your system enviroment. To get the |
AVRA executable, you have to issue the following commands: |
aclocal |
autoconf |
automake -a |
./configure |
make && make install |
AmigaOS |
~~~~~~~ |
avra can be copied any apropriate directory. If you are using the source |
distribution a 'make install' will do the same. |
Microsoft Windows |
~~~~~~~~~~~~~~~~~ |
If you received the Windows binary package, look into the \bin |
directory where you can find avra.exe. This should be copied to any |
apropriate location. You can also overwrite AVRASM32.EXE in your |
Atmel AVR Studio. If you want to compile it yourself you could download then |
OpenWatcom C/C++ Toolchain for windows and create a new project and add the C |
and H files to it and compile. |
Apple OS X |
~~~~~~~~~~ |
If you recieved the Apple OS X binary package, look into the bin directory this |
file is compiled universal and should run on intel 32 and 64 bit and powerpc. If |
you want to compile it yourself go to the src directory and invoke `make -f |
makefiles/Makefiles.osx` and then the executable should be created. |
Synopsis |
-------- |
Command line usage |
~~~~~~~~~~~~~~~~~~ |
usage: AVRA [-f][O|M|I|G] output file type |
[-o <filename>] output file name |
[-l <filename>] generate list file |
[-m <mapfile>] generate map file |
[--define <symbol>[=<value>]] [--includedir <dir>] [--listmac] |
[--max_errors <number>] [--devices] [--version] |
[-h] [--help] general help |
[-W NoRegDef] supress register redefinition warnings |
<file to assemble> |
Parameter list |
~~~~~~~~~~~~~~ |
--listfile -l : Create list file |
--mapfile -m : Create map file |
--define -D : Define symbol. |
--includedir -I : Additional include dirs. |
--listmac : List macro expansion in listfile. |
--max_errors : Maximum number of errors before exit |
(default: 10) |
--devices : List out supported devices. |
--version : Version information. |
--help, -h : This help text. |
Warning supression |
~~~~~~~~~~~~~~~~~~ |
Since avra 1.1 there is a possibility to supress certain warnings. |
Currently only register reassignment warnings can be supressed. |
Example: avra -W NoRegDef |
Programming techniques |
---------------------- |
Using directives |
~~~~~~~~~~~~~~~~ |
AVRA offers a number of directives that are not part of Atmel's |
assembler. These directives should help you creating versatile code that |
can be designed more modular. |
Directive .define |
^^^^^^^^^^^^^^^^^ |
To define a constant, use ".define". This does the same thing as ".equ", |
it is just a little more C style. Keep in mind that AVRA is not case |
sensitive. Do not mix ".def" and ".define", because ".def" is used to |
assign registers only. This is due to backward compatibility to Atmel's |
AVRASM32. Here is an example on how .define can be used. |
.define network 1 |
Now "network" is set to the value 1. You may want to assemble a specific |
part of your code depeding on a define or switch setting. You can test |
your defined word on existence (.ifdef and .ifndef) as well as on the |
value it represents. The following code shows a way to prevent error |
messages due to testing undefined constants. Conditional directives must |
always end with an .endif directive. |
.ifndef network |
.define network 0 |
.endif |
Directive .if and .else |
^^^^^^^^^^^^^^^^^^^^^^^ |
The three lines in the last example set the default value of "network". |
In the next example, you see how we can use default values. If a constant |
has not defined previously, it is set to zero. Now you can test wether |
e.g. network support is included into the assemby process. |
.if network = 1 |
.include "include\tcpip.asm" |
.else |
.include "include\dummynet.asm" |
.endif |
In the second part of the above listing you see the use of .else, which |
defines the part of the condition that is being executed if the equation |
of the preceding .if statement is not equal. You can also use the else |
statement to test another equasion. For that purpose use .elif, which |
means "else if". Always close this conditional part with ".endif" |
Directive .error |
^^^^^^^^^^^^^^^^ |
This directive can be used to throw errors if a part in the code has reached |
that should not be reached. The following example shows how we can stop |
the assembly process if a particular value has not been previously set. |
.ifndef network |
.error "network is not configured!" ;the assembler stops here |
Directive .nolist and .list |
^^^^^^^^^^^^^^^^^^^^^^^^^^^ |
The ouput to the list file can be paused by this two directives. After |
avra discovers a .nolist while assembling, it stops output to the list file. |
After a .list directive is detected, it continues the normal list file output. |
Directive .includepath |
^^^^^^^^^^^^^^^^^^^^^^ |
By default, any file that is included from within the source file must |
either be a single filename or a complete absolute path. With the directive |
.includepath you can set an additional include path . Furthermore you can |
set as many include paths as you want. Be sure not no use same filename |
in separate includes, because then it is no longer clear which one avra |
should take. |
Using include files |
------------------- |
To avoid multiple inclusions of include files, you may use some pre- |
processor directives. See example file stack.asm that is being included |
into the main programm file as well as in other include files. |
.ifndef _STACK_ASM_ |
.define _STACK_ASM_ |
.include "include/config.inc" |
; *** stack macro *** |
.dseg |
m_stack: .byte __stack_size__ |
.cseg |
.macro stack_setup |
load [v:w,m_stack + __stack_size__] |
outp [SPREG,v:w] |
.endm |
.endif ; avoid multiple inclusion of stack.asm |
Using build date meta tags |
~~~~~~~~~~~~~~~~~~~~~~~~~~ |
If you like to implement compiler build time and date into your |
program, you can make use of some sepcial tags that avra supports. |
%MINUTE% is being replaced by the current minute (00-59) |
%HOUR% is being replaced by the current hour (00-23) |
%DAY% is being replaced by the current day of month (01-31) |
%MONTH% is being replaced by the current month (01-12) |
%YEAR% is being replaced by the current year (2004-9999) |
buildtime: .db "Release date %DAY%.%MONTH%.%YEAR% %HOUR%:%MINUTE%" |
This line will then assembled by avra into: |
buildtime: .db "Release date 10.05.2004 19:54" |
You may also create a self defined serial number with meta tags: |
.define serialnumber %DAY% + %MONTH%*31 + (%YEAR% - 2000) *31*12 |
The %TAG% is translated before any other parsing happens. The real |
output can be found in the list file. |
Macro features |
-------------- |
Sometimes you have to work with 16 bit or greater variables stored |
in 8 bit registers. The enhanced macro support allows you to write short |
and flexible macros that simplify access to big variables. The extended |
mode is active, as soon as you use parenthesis like this "[ ]" to wrap |
macro parameters. |
Auto type conversion for macros |
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
Values representing more than 8 Bits are usualy kept in a set of byte |
wide registers. To simplify 16 Bit or greater operations, I added a new |
language definitions. Words can be written as r16:r17, whereas register |
r16 contains the higher part and register r17 the lower part of this |
16 Bit value. |
Macro data types |
^^^^^^^^^^^^^^^^ |
There are 3 data types that can be used. They will be added as character |
separated by one underline character. |
immediate values _i |
registers _8,_16,_24,_32,_40,_48,_56,_64 |
void parameter _v |
16 Bit Source and Destionation registers 'dst' and 'src' |
src = YH:YL |
dst = ZH:ZL |
Within the parenthesis, the two words src and dst are interpreted as YH:YL |
and ZH:ZL. Normal code outside of the macro parameter parenthesis can |
still make use of these special key words "src" and "dst". |
Examples for automatic type conversion |
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ |
To simplify the parameters in the demonstration below, we need to |
redefine some registers. |
.def a = r16 ; general purpose registers |
.def b = r17 |
.def c = r18 |
.def d = r19 |
.def w = r20 ; working register |
.def v = r21 ; working register |
If we substract 16 Bit values stored in a, higher byte and b, lower byte |
with that in c:d, we usually have to use the following command sequence: |
sub b,d |
sbc a,c |
Now we can do the following steps to simplify 16 or more Bit manipulations |
.macro subs |
.message "no parameters specified" |
.endm |
.macro subs_16_16 |
sub @1,@3 |
sbc @0,@2 |
.endm |
.macro subs_16_8 |
sub @1,@2 |
sbci @0,0 |
.endm |
;now we can write a 16 Bit subraction as: |
subs [a:b,c:d] |
;or for calculating 16 minus 8 Bit |
subs [a:b,c] |
Overloading macros |
~~~~~~~~~~~~~~~~~~ |
Like in you are used to C functions, you can write macros for different |
parameter lists. If you would like to have a versatile macro, you can |
specify a unique macro for each parameter situation. See the next sample. |
.macro load |
; this message is shown if you use the macro within your code |
; specifying no parameters. If your macro allows the case where |
; no parameters are given, exchange .message with your code. |
.message "no parameters specified" |
.endm |
; Here we define the macro "load" for the case it is being used |
; with two registers as first parameter and a immediate (constant) |
; value as second parameter. |
.macro load_16_i |
ldi @0,high(@2) |
ldi @1,low(@2) |
.endm |
; the same case, but now with a 32 bit register value as first |
; parameter |
.macro load_32_i |
ldi @0,BYTE4(@4) |
ldi @1,BYTE3(@4) |
ldi @2,high(@4) |
ldi @3,low(@4) |
.endm |
; Now let's see how these macros are being used in the code |
load [a:b,15] ;uses macro load_16_i to load immediate |
load [a:b:c:d,15] ;uses macro load_32_i to load immediate |
More examples |
~~~~~~~~~~~~~ |
.dseg |
counter .byte 2 |
.cseg |
.macro poke |
.message "no parameters" |
.endm |
.macro poke_i_16_i |
ldi @1,high(@3) |
sts @0+0,@1 |
ldi @2,low(@3) |
sts @0+1,@2 |
.endm |
.macro poke_i_i |
ldi w,@1 |
sts @0+0,w |
.endm |
.macro poke_i_v_i |
ldi w,high(@3) |
sts @0+0,w |
ldi w,low(@3) |
sts @0+1,w |
.endm |
.macro poke_i_v_v_v_i |
ldi w,high(@3) |
sts @0+0,w |
ldi w,low(@3) |
sts @0+1,w |
ldi w,BYTE3(@3) |
sts @0+2,w |
ldi w,BYTE4(@3) |
sts @0+3,w |
.endm |
; this writes '9999' into the memory at 'counter' |
; uses only the working register for transfering the values. |
poke [counter,w:w,9999] |
; works same as above, but the transferred value '9999' is also |
; kept in the pair of register a:b |
poke [counter,a:b,9999] |
; in my design 'w' is always working reg. which implies that |
; it cannot be used for normal variables. The following example |
; uses poke_i_i because the parameter contains two immediate values. |
poke [counter,9999] ;uses poke_i_i |
; to be able to choose between a 8,16 or 32 Bit operation, you just |
; add a void parameter. |
poke [counter,,9999] ;uses poke_i_v_i |
; and the same for 32 Bit pokes |
poke [counter,,,,9999] ;uses poke_i_v_v_v_i |
Loops within macros |
~~~~~~~~~~~~~~~~~~~ |
One problem you may have experienced, is that labels defined within macros |
are defined twice if you call the macro for example two times. Now you can |
use labels for macro loops. Loops within macros must end with '_%'. the |
"%" symbol is replaced by a running number. |
Loop example |
^^^^^^^^^^^^ |
; Definition of the macro |
.macro write_8_8 |
write_%: |
st Z+,@0 |
dec @1 |
brne write_% |
.endm |
; Use in user code |
write [a,b] |
write [c,d] |
; After assembling this code, the result looks like this |
write_1: |
st Z+,a |
dec b |
brne write_1 |
write_2: |
st Z+,c |
dec d |
brne write_2 |
Warnings and Errors |
------------------- |
Some errors and warnings may confuse you a little bit so we will try to |
clear some frequently asked questions about such cases. |
Constant out of range |
~~~~~~~~~~~~~~~~~~~~~ |
This warning occurs if a value exceeds the byte or word value of a assignment. |
Read the comment posted by Jim Galbraith: |
The expression (~0x80) is a Bitwise Not operation. This |
operator returns the input expression with all its bits |
inverted. If 0x80 represents -128, then 0x7f, or +127 |
should be ok. If this is considered as a 32-bit expression |
(AVRA internal representation), then it appears to be more |
like oxffffffff-0x80 or 0xffffffff^0x80. The result would then |
be 0xffffff7f. The assembler would then have to be told or it |
would have to decide, based on context, how much |
significance to assign to the higher bits. I have also |
encountered such conditions with various assemblers, |
including AVRA. To make sure the assembler does what I |
really want, I use a construct like 0xff-0x80 or 0xff^0x80. |
This way the bit significance cannot extend beyond bit-7 and |
there cannot be any misunderstanding. |
Can't use .DB directive in data segment |
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
.DB and .DW is only used to assign constant data in eeprom or code space. |
The reason why using it within data segment is forbidden is, that you |
cannot set ram content at assembly time. The values must be programmed into |
ROM area and at boot read from ROM into RAM. This is up to the user code. |
You can only allocate memory for your variables using labels and the .byte |
directive. |
.dseg |
my_string: .byte 15 |
BYTE directive |
~~~~~~~~~~~~~~ |
.BYTE directive can only be used in data segment (.DSEG) |
This directive cannot be used in code or eeprom region because this only |
allocates memory without assgning distinct values to it. Please use .db |
or .dw instead. |
Internal assembler error |
~~~~~~~~~~~~~~~~~~~~~~~~ |
If you get an "Internal assembler error" please contact the project maintainer |
by sending him a code example and a description of your working enviroment. |
AVRA internals |
-------------- |
This section provides thoughts of the avra internal design. I have to admit |
that the code of avra is anything else than clean and optimized. To increase |
the code readability I will try to give you some standards that should improve |
quality. The following standards are similar to what GNU proposes. |
Coding standards |
~~~~~~~~~~~~~~~~ |
Tab space is always 2 spaces. The Tab character (ascii 9) is not used. |
if,while,for are always opened on the same line but closed on the next line. |
The closing bracket is in the same column as the first letter of the loop |
directive. |
Example: |
---- |
while(i > 0) { |
do_something(); |
} |
---- |
Credits |
------- |
We would like to thank the following people for giving contributions, |
patches and bug reports, as well as suggestions and new ideas. |
---- |
Jon Anders Haugum (project founder) |
Burkhard Arenfeld (release 1.2.0) |
Tobias Weber (old maintainer) |
Jerry Jacobs (release 1.3.0) |
Bernt Hembre |
Nils Strøm |
Roberto Biancardi |
Qwerty Jones |
Ben Hitchcock (Maker of the mac port) |
Daniel Drotos |
Laurence Boyd II |
Varuzhan Danielyan |
Laurence Turner |
Eugene R. O'Bryan |
Dmitry Dicky |
Bob Harris (Maker of coff support) |
Tobias Weber (enhanced macro support) |
Lesha Bogdanow |
Jim Galbraith |
Mark Brinicombe |
Igor Nikolayenko |
Peter Hettkamp |
Herb Poppe |
David Burke |
Alexey Pavluchenko |
Alan Probandt |
Mariusz Matuszek |
Arne Rossius |
Marti Tichacek |
Patrick Parity |
Johannes Overmann |
Roland Riegel |
Peter Katzmann |
Donald D. Davis |
---- |
And all the anonymous people who submitted patches! |
Thank you for your work and support. |
References |
---------- |
http://www.suprafluid.com/avra |
http://www.avrfreaks.de |
http://www.atmel.com |
/contrib/toolchain/avra/doc/asciidoc-xhtml11.js |
---|
0,0 → 1,128 |
var asciidoc = { // Namespace. |
///////////////////////////////////////////////////////////////////// |
// Table Of Contents generator |
///////////////////////////////////////////////////////////////////// |
/* Author: Mihai Bazon, September 2002 |
* http://students.infoiasi.ro/~mishoo |
* |
* Table Of Content generator |
* Version: 0.4 |
* |
* Feel free to use this script under the terms of the GNU General Public |
* License, as long as you do not remove or alter this notice. |
*/ |
/* modified by Troy D. Hanson, September 2006. License: GPL */ |
/* modified by Stuart Rackham, 2006, 2009. License: GPL */ |
// toclevels = 1..4. |
toc: function (toclevels) { |
function getText(el) { |
var text = ""; |
for (var i = el.firstChild; i != null; i = i.nextSibling) { |
if (i.nodeType == 3 /* Node.TEXT_NODE */) // IE doesn't speak constants. |
text += i.data; |
else if (i.firstChild != null) |
text += getText(i); |
} |
return text; |
} |
function TocEntry(el, text, toclevel) { |
this.element = el; |
this.text = text; |
this.toclevel = toclevel; |
} |
function tocEntries(el, toclevels) { |
var result = new Array; |
var re = new RegExp('[hH]([2-'+(toclevels+1)+'])'); |
// Function that scans the DOM tree for header elements (the DOM2 |
// nodeIterator API would be a better technique but not supported by all |
// browsers). |
var iterate = function (el) { |
for (var i = el.firstChild; i != null; i = i.nextSibling) { |
if (i.nodeType == 1 /* Node.ELEMENT_NODE */) { |
var mo = re.exec(i.tagName); |
if (mo && (i.getAttribute("class") || i.getAttribute("className")) != "float") { |
result[result.length] = new TocEntry(i, getText(i), mo[1]-1); |
} |
iterate(i); |
} |
} |
} |
iterate(el); |
return result; |
} |
var toc = document.getElementById("toc"); |
var entries = tocEntries(document.getElementById("content"), toclevels); |
for (var i = 0; i < entries.length; ++i) { |
var entry = entries[i]; |
if (entry.element.id == "") |
entry.element.id = "_toc_" + i; |
var a = document.createElement("a"); |
a.href = "#" + entry.element.id; |
a.appendChild(document.createTextNode(entry.text)); |
var div = document.createElement("div"); |
div.appendChild(a); |
div.className = "toclevel" + entry.toclevel; |
toc.appendChild(div); |
} |
if (entries.length == 0) |
toc.parentNode.removeChild(toc); |
}, |
///////////////////////////////////////////////////////////////////// |
// Footnotes generator |
///////////////////////////////////////////////////////////////////// |
/* Based on footnote generation code from: |
* http://www.brandspankingnew.net/archive/2005/07/format_footnote.html |
*/ |
footnotes: function () { |
var cont = document.getElementById("content"); |
var noteholder = document.getElementById("footnotes"); |
var spans = cont.getElementsByTagName("span"); |
var refs = {}; |
var n = 0; |
for (i=0; i<spans.length; i++) { |
if (spans[i].className == "footnote") { |
n++; |
// Use [\s\S] in place of . so multi-line matches work. |
// Because JavaScript has no s (dotall) regex flag. |
note = spans[i].innerHTML.match(/\s*\[([\s\S]*)]\s*/)[1]; |
noteholder.innerHTML += |
"<div class='footnote' id='_footnote_" + n + "'>" + |
"<a href='#_footnoteref_" + n + "' title='Return to text'>" + |
n + "</a>. " + note + "</div>"; |
spans[i].innerHTML = |
"[<a id='_footnoteref_" + n + "' href='#_footnote_" + n + |
"' title='View footnote' class='footnote'>" + n + "</a>]"; |
var id =spans[i].getAttribute("id"); |
if (id != null) refs["#"+id] = n; |
} |
} |
if (n == 0) |
noteholder.parentNode.removeChild(noteholder); |
else { |
// Process footnoterefs. |
for (i=0; i<spans.length; i++) { |
if (spans[i].className == "footnoteref") { |
var href = spans[i].getElementsByTagName("a")[0].getAttribute("href"); |
href = href.match(/#.*/)[0]; // Because IE return full URL. |
n = refs[href]; |
spans[i].innerHTML = |
"[<a href='#_footnote_" + n + |
"' title='View footnote' class='footnote'>" + n + "</a>]"; |
} |
} |
} |
} |
} |
/contrib/toolchain/avra/doc/build-website.sh |
---|
0,0 → 1,11 |
#!/bin/sh |
VERS="1.3.0" |
DATE="2010-06-28" |
ASCIIDOC_HTML="asciidoc --unsafe --backend=xhtml11 --conf-file=layout1.conf --attribute icons --attribute iconsdir=./images/icons --attribute=badges --attribute=revision=$VERS --attribute=date=$DATE" |
$ASCIIDOC_HTML -a index-only index.txt |
$ASCIIDOC_HTML ChangeLog.txt |
$ASCIIDOC_HTML downloads.txt |
$ASCIIDOC_HTML README.txt |
Property changes: |
Added: svn:executable |
+* |
\ No newline at end of property |
/contrib/toolchain/avra/doc/downloads.html |
---|
0,0 → 1,75 |
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" |
"http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd"> |
<html xmlns="http://www.w3.org/1999/xhtml" xml:lang="en"> |
<head> |
<meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /> |
<meta name="generator" content="AsciiDoc 8.5.3" /> |
<link rel="stylesheet" href="./xhtml11.css" type="text/css" /> |
<link rel="stylesheet" href="./xhtml11-quirks.css" type="text/css" /> |
<link rel="stylesheet" href="./layout1.css" type="text/css" /> |
<script type="text/javascript"> |
/*<![CDATA[*/ |
window.onload = function(){asciidoc.footnotes();} |
/*]]>*/ |
</script> |
<script type="text/javascript" src="./asciidoc-xhtml11.js"></script> |
<title>Downloads</title> |
</head> |
<body> |
<div id="layout-banner"> |
<div id="layout-title">AVRA</div> |
<div id="layout-description">Assember for the Atmel AVR microcontroller family</div> |
</div> |
<table> |
<tr valign="top"> |
<td id="layout-menu"> |
<div>»<a href="index.html">Home</a></div> |
<div>»<a href="README.html">Readme</a></div> |
<div>»<a href="downloads.html">Downloads</a></div> |
<div>»<a href="ChangeLog.html">ChangeLog</a></div> |
<div>»<a href="http://sourceforge.net/projects/avra">Sourceforge</a></div> |
<div id="page-source">»<a href="downloads.txt">Page Source</a></div> |
</td> |
<td> |
<div id="layout-content"> |
<div id="header"> |
<h1>Downloads</h1> |
</div> |
<div id="content"> |
<div id="preamble"> |
<div class="sectionbody"> |
<div class="paragraph"><p>The latest release can always be downloaded from sourceforge.</p></div> |
<div class="paragraph"><p><a href="http://sourceforge.net/projects/avra/files">http://sourceforge.net/projects/avra/files</a></p></div> |
</div> |
</div> |
</div> |
<div id="footnotes"><hr /></div> |
<div id="footer"> |
<div id="footer-text"> |
Version 1.3.0<br /> |
Last updated 2010-06-28 16:04:25 CEST |
</div> |
<div id="footer-badges"> |
<a href="http://validator.w3.org/check?uri=referer"> |
<img style="border:0;width:88px;height:31px" |
src="http://www.w3.org/Icons/valid-xhtml11-blue" |
alt="Valid XHTML 1.1" height="31" width="88" /> |
</a> |
<a href="http://jigsaw.w3.org/css-validator/"> |
<img style="border:0;width:88px;height:31px" |
src="http://jigsaw.w3.org/css-validator/images/vcss-blue" |
alt="Valid CSS!" /> |
</a> |
<a href="http://www.mozilla.org/products/firefox/"> |
<img style="border:none; width:110px; height:32px;" |
src="http://www.spreadfirefox.com/community/images/affiliates/Buttons/110x32/safer.gif" |
alt="Get Firefox!" /> |
</a> |
</div> |
</div> |
</div> |
</td> |
</tr> |
</table> |
</body> |
</html> |
/contrib/toolchain/avra/doc/downloads.txt |
---|
0,0 → 1,6 |
Downloads |
========= |
The latest release can always be downloaded from sourceforge. |
http://sourceforge.net/projects/avra/files |
/contrib/toolchain/avra/doc/images/highlighter.png |
---|
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svn:mime-type = application/octet-stream |
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+application/octet-stream |
\ No newline at end of property |
/contrib/toolchain/avra/doc/images/icons/README |
---|
0,0 → 1,5 |
Replaced the plain DocBook XSL admonition icons with Jimmac's DocBook |
icons (http://jimmac.musichall.cz/ikony.php3). I dropped transparency |
from the Jimmac icons to get round MS IE and FOP PNG incompatibilies. |
Stuart Rackham |
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---|
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---|
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---|
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---|
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---|
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---|
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---|
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---|
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---|
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---|
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/contrib/toolchain/avra/doc/index.html |
---|
0,0 → 1,94 |
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" |
"http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd"> |
<html xmlns="http://www.w3.org/1999/xhtml" xml:lang="en"> |
<head> |
<meta http-equiv="Content-Type" content="text/html; charset=UTF-8" /> |
<meta name="generator" content="AsciiDoc 8.5.3" /> |
<meta name="description" content="Text based document generation" /> |
<meta name="keywords" content="text to HTML, text to DocBook, text to XML, AsciiDoc" /> |
<link rel="stylesheet" href="./xhtml11.css" type="text/css" /> |
<link rel="stylesheet" href="./xhtml11-quirks.css" type="text/css" /> |
<link rel="stylesheet" href="./layout1.css" type="text/css" /> |
<script type="text/javascript"> |
/*<![CDATA[*/ |
window.onload = function(){asciidoc.footnotes();} |
/*]]>*/ |
</script> |
<script type="text/javascript" src="./asciidoc-xhtml11.js"></script> |
<title>AVRA Home Page</title> |
</head> |
<body> |
<div id="layout-banner"> |
<div id="layout-title">AVRA</div> |
<div id="layout-description">Assember for the Atmel AVR microcontroller family</div> |
</div> |
<table> |
<tr valign="top"> |
<td id="layout-menu"> |
<div>»<a href="index.html">Home</a></div> |
<div>»<a href="README.html">Readme</a></div> |
<div>»<a href="downloads.html">Downloads</a></div> |
<div>»<a href="ChangeLog.html">ChangeLog</a></div> |
<div>»<a href="http://sourceforge.net/projects/avra">Sourceforge</a></div> |
<div id="page-source">»<a href="index.txt">Page Source</a></div> |
</td> |
<td> |
<div id="layout-content"> |
<div id="header"> |
<h1>AVRA Home Page</h1> |
</div> |
<div id="content"> |
<div id="preamble"> |
<div class="sectionbody"> |
<div class="sidebarblock"> |
<div class="sidebar-content"> |
<div class="sidebar-title">2010-06-28: AVRA 1.3.0 Released</div> |
<div class="paragraph"><p>This release contains a few improvements, a couple of bug fixes and |
documentation updates.</p></div> |
<div class="paragraph"><p>Read the <a href="ChangeLog.html">ChangeLog</a> for a full list of all |
additions, changes and bug fixes. Changes are documented in the |
updated <a href="README.html">Readme</a>. See the |
<a href="downloads.html">Downloads</a> page for sourcecode and binary releases.</p></div> |
</div></div> |
</div> |
</div> |
<h2 id="_introduction">Introduction</h2> |
<div class="sectionbody"> |
<div class="paragraph"><p>AVRA is an assembler for Atmel AVR microcontrollers, and it is almost |
compatible with Atmel’s own assembler AVRASM32. The programming |
principles and conceptions are based on the ANSI programming language "C".</p></div> |
<div class="paragraph"><p>The initial version of AVRA was written by John Anders Haugum in 1999. He |
released all versions until v0.7. All later versions were released by Tobias |
Weber. And version 1.3.0 is released by Jerry Jacobs.</p></div> |
</div> |
</div> |
<div id="footnotes"><hr /></div> |
<div id="footer"> |
<div id="footer-text"> |
Version 1.3.0<br /> |
Last updated 2010-06-28 16:04:24 CEST |
</div> |
<div id="footer-badges"> |
<a href="http://validator.w3.org/check?uri=referer"> |
<img style="border:0;width:88px;height:31px" |
src="http://www.w3.org/Icons/valid-xhtml11-blue" |
alt="Valid XHTML 1.1" height="31" width="88" /> |
</a> |
<a href="http://jigsaw.w3.org/css-validator/"> |
<img style="border:0;width:88px;height:31px" |
src="http://jigsaw.w3.org/css-validator/images/vcss-blue" |
alt="Valid CSS!" /> |
</a> |
<a href="http://www.mozilla.org/products/firefox/"> |
<img style="border:none; width:110px; height:32px;" |
src="http://www.spreadfirefox.com/community/images/affiliates/Buttons/110x32/safer.gif" |
alt="Get Firefox!" /> |
</a> |
</div> |
</div> |
</div> |
</td> |
</tr> |
</table> |
</body> |
</html> |
/contrib/toolchain/avra/doc/index.txt |
---|
0,0 → 1,23 |
AVRA Home Page |
============== |
.{revdate}: AVRA {revnumber} Released |
************************************************************************ |
This release contains a few improvements, a couple of bug fixes and |
documentation updates. |
Read the link:ChangeLog.html[ChangeLog] for a full list of all |
additions, changes and bug fixes. Changes are documented in the |
updated link:README.html[Readme]. See the |
link:downloads.html[Downloads] page for sourcecode and binary releases. |
************************************************************************ |
Introduction |
------------ |
AVRA is an assembler for Atmel AVR microcontrollers, and it is almost |
compatible with Atmel's own assembler AVRASM32. The programming |
principles and conceptions are based on the ANSI programming language "C". |
The initial version of AVRA was written by John Anders Haugum in 1999. He |
released all versions until v0.7. All later versions were released by Tobias |
Weber. And version 1.3.0 is released by Jerry Jacobs. |
/contrib/toolchain/avra/doc/layout1.conf |
---|
0,0 → 1,155 |
# |
# AsciiDoc website. |
# Three division table based layout (layout1). |
# |
# +-----------------------------------------------------+ |
# | #layout-banner | |
# +--------------+--------------------------------------+ |
# | | | |
# | | | |
# | #layout-menu | #layout-content | |
# | | | |
# | | | |
# | | | |
# +--------------+--------------------------------------+ |
# |
# - The #layout-menu and #layout-content divisions are contained in a |
# two cell table. |
# I would be nice to use pure CSS for the layout but the table is better for |
# this layout because: |
# |
# * The column widths automatically size to fit column width (specifically |
# the #layout-menu) |
# * The column heights automatically size to the tallest. |
# |
# - The #layout-content division is a container for AsciiDoc page documents. |
# - Documents rendered in the #layout-content use the standard AsciiDoc |
# xhtml11 backend stylesheets. |
[specialwords] |
monospacedwords=(?u)\\?\basciidoc\(1\) (?u)\\?\ba2x\(1\) |
[header] |
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" |
"http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd"> |
<html xmlns="http://www.w3.org/1999/xhtml" xml:lang="en"> |
<head> |
<meta http-equiv="Content-Type" content="text/html; charset={encoding}" /> |
<meta name="generator" content="AsciiDoc {asciidoc-version}" /> |
ifdef::index-only[] |
<meta name="description" content="Text based document generation" /> |
<meta name="keywords" content="text to HTML, text to DocBook, text to XML, AsciiDoc" /> |
endif::index-only[] |
<link rel="stylesheet" href="{stylesdir=.}/{theme={backend}}.css" type="text/css" /> |
{doctype-manpage}<link rel="stylesheet" href="{stylesdir=.}/{theme={backend}}-manpage.css" type="text/css" /> |
<link rel="stylesheet" href="{stylesdir=.}/{theme={backend}}-quirks.css" type="text/css" /> |
<link rel="stylesheet" href="{stylesdir=.}/layout1.css" type="text/css" /> |
<script type="text/javascript"> |
/*<![CDATA[*/ |
window.onload = function()\{asciidoc.footnotes();{toc? asciidoc.toc({toclevels});}\} |
/*]]>*/ |
</script> |
<script type="text/javascript" src="{scriptsdir=.}/asciidoc-xhtml11.js"></script> |
ifdef::asciimath[] |
<script type="text/javascript" src="{scriptsdir=.}/ASCIIMathML.js"></script> |
endif::asciimath[] |
ifdef::latexmath[] |
<script type="text/javascript" src="{scriptsdir=.}/LaTeXMathML.js"></script> |
endif::latexmath[] |
<title>{doctitle}</title> |
</head> |
<body{max-width? style="max-width:{max-width}"}> |
<div id="layout-banner"> |
<div id="layout-title">AVRA</div> |
<div id="layout-description">Assember for the Atmel AVR microcontroller family</div> |
</div> |
<table> |
<tr valign="top"> |
<td id="layout-menu"> |
<div>»<a href="index.html">Home</a></div> |
<div>»<a href="README.html">Readme</a></div> |
<div>»<a href="downloads.html">Downloads</a></div> |
<div>»<a href="ChangeLog.html">ChangeLog</a></div> |
<div>»<a href="http://sourceforge.net/projects/avra">Sourceforge</a></div> |
<div id="page-source">»<a href="{eval:os.path.basename('{infile}')}">Page Source</a></div> |
</td> |
<td> |
<div id="layout-content"> |
# Article, book header. |
ifndef::doctype-manpage[] |
<div id="header"> |
<h1>{doctitle}</h1> |
<span id="author">{author}</span><br /> |
<span id="email"><tt><<a href="mailto:{email}">{email}</a>></tt></span><br /> |
{authored}<span id="revision">version {revnumber}{revdate?,}</span> |
{authored}{revdate} |
ifdef::toc[] |
<div id="toc"> |
<div id="toctitle">Table of Contents</div> |
<noscript><p><b>JavaScript must be enabled in your browser to display the table of contents.</b></p></noscript> |
</div> |
endif::toc[] |
</div> |
endif::doctype-manpage[] |
# Man page header. |
ifdef::doctype-manpage[] |
<div id="header"> |
<h1> |
{doctitle} Manual Page |
</h1> |
ifdef::toc[] |
<div id="toc"> |
<div id="toctitle">Table of Contents</div> |
<noscript><p><b>JavaScript must be enabled in your browser to display the table of contents.</b></p></noscript> |
</div> |
endif::toc[] |
<h2>NAME</h2> |
<div class="sectionbody"> |
<p>{manname} - |
{manpurpose} |
</p> |
</div> |
</div> |
endif::doctype-manpage[] |
<div id="content"> |
[footer] |
</div> |
{disable-javascript%<div id="footnotes"><hr /></div>} |
<div id="footer"> |
<div id="footer-text"> |
Version {revnumber}<br /> |
Last updated {localdate} {localtime} |
</div> |
ifdef::badges[] |
<div id="footer-badges"> |
ifdef::textonly[] |
Valid <a href="http://validator.w3.org/check?uri=referer">XHTML</a> |
and <a href="http://jigsaw.w3.org/css-validator/check/referer">CSS</a>. |
endif::textonly[] |
ifndef::textonly[] |
<a href="http://validator.w3.org/check?uri=referer"> |
<img style="border:0;width:88px;height:31px" |
src="http://www.w3.org/Icons/valid-xhtml11-blue" |
alt="Valid XHTML 1.1" height="31" width="88" /> |
</a> |
<a href="http://jigsaw.w3.org/css-validator/"> |
<img style="border:0;width:88px;height:31px" |
src="http://jigsaw.w3.org/css-validator/images/vcss-blue" |
alt="Valid CSS!" /> |
</a> |
<a href="http://www.mozilla.org/products/firefox/"> |
<img style="border:none; width:110px; height:32px;" |
src="http://www.spreadfirefox.com/community/images/affiliates/Buttons/110x32/safer.gif" |
alt="Get Firefox!" /> |
</a> |
endif::textonly[] |
</div> |
endif::badges[] |
</div> |
</div> |
</td> |
</tr> |
</table> |
</body> |
</html> |
/contrib/toolchain/avra/doc/layout1.css |
---|
0,0 → 1,65 |
body { |
background-color: white; |
margin: 1%; |
} |
h1 { |
margin-top: 0.5em; |
} |
#layout-banner { |
background-color: #73a0c5; |
color: white; |
font-family: sans-serif; |
text-align: left; |
padding: 0.8em 20px; |
} |
#layout-title { |
font-family: monospace; |
font-size: 3.5em; |
font-weight: bold; |
letter-spacing: 0.2em; |
margin: 0; |
} |
#layout-description { |
font-size: 1.2em; |
letter-spacing: 0.1em; |
} |
#layout-menu { |
background-color: #f4f4f4; |
border-right: 3px solid #eeeeee; |
padding-top: 0.8em; |
padding-left: 20px; |
padding-right: 0.8em; |
font-size: 1.1em; |
font-family: sans-serif; |
font-weight: bold; |
} |
#layout-menu a { |
line-height: 2em; |
margin-left: 0.5em; |
} |
#layout-menu a:link, #layout-menu a:visited, #layout-menu a:hover { |
color: #527bbd; |
text-decoration: none; |
} |
#layout-menu a:hover { |
color: navy; |
text-decoration: none; |
} |
#layout-menu #page-source { |
border-top: 2px solid silver; |
margin-top: 0.2em; |
} |
#layout-content { |
margin-left: 1.0em; |
} |
@media print { |
#layout-banner { display: none; } |
#layout-menu { display: none; } |
} |
/contrib/toolchain/avra/doc/xhtml11-manpage.css |
---|
0,0 → 1,18 |
/* Overrides for manpage documents */ |
h1 { |
padding-top: 0.5em; |
padding-bottom: 0.5em; |
border-top: 2px solid silver; |
border-bottom: 2px solid silver; |
} |
h2 { |
border-style: none; |
} |
div.sectionbody { |
margin-left: 5%; |
} |
@media print { |
div#toc { display: none; } |
} |
/contrib/toolchain/avra/doc/xhtml11-quirks.css |
---|
0,0 → 1,41 |
/* Workarounds for IE6's broken and incomplete CSS2. */ |
div.sidebar-content { |
background: #ffffee; |
border: 1px solid silver; |
padding: 0.5em; |
} |
div.sidebar-title, div.image-title { |
color: #527bbd; |
font-family: sans-serif; |
font-weight: bold; |
margin-top: 0.0em; |
margin-bottom: 0.5em; |
} |
div.listingblock div.content { |
border: 1px solid silver; |
background: #f4f4f4; |
padding: 0.5em; |
} |
div.quoteblock-attribution { |
padding-top: 0.5em; |
text-align: right; |
} |
pre.verseblock-content { |
font-family: inherit; |
} |
div.verseblock-attribution { |
padding-top: 0.75em; |
text-align: left; |
} |
div.exampleblock-content { |
border-left: 3px solid #dddddd; |
padding-left: 0.5em; |
} |
/* IE6 sets dynamically generated links as visited. */ |
div#toc a:visited { color: blue; } |
/contrib/toolchain/avra/doc/xhtml11.css |
---|
0,0 → 1,367 |
/* Debug borders */ |
p, li, dt, dd, div, pre, h1, h2, h3, h4, h5, h6 { |
/* |
border: 1px solid red; |
*/ |
} |
body { |
margin: 1em 5% 1em 5%; |
} |
a { |
color: blue; |
text-decoration: underline; |
} |
a:visited { |
color: fuchsia; |
} |
em { |
font-style: italic; |
color: navy; |
} |
strong { |
font-weight: bold; |
color: #083194; |
} |
tt { |
color: navy; |
} |
h1, h2, h3, h4, h5, h6 { |
color: #527bbd; |
font-family: sans-serif; |
margin-top: 1.2em; |
margin-bottom: 0.5em; |
line-height: 1.3; |
} |
h1, h2, h3 { |
border-bottom: 2px solid silver; |
} |
h2 { |
padding-top: 0.5em; |
} |
h3 { |
float: left; |
} |
h3 + * { |
clear: left; |
} |
div.sectionbody { |
font-family: serif; |
margin-left: 0; |
} |
hr { |
border: 1px solid silver; |
} |
p { |
margin-top: 0.5em; |
margin-bottom: 0.5em; |
} |
ul, ol, li > p { |
margin-top: 0; |
} |
pre { |
padding: 0; |
margin: 0; |
} |
span#author { |
color: #527bbd; |
font-family: sans-serif; |
font-weight: bold; |
font-size: 1.1em; |
} |
span#email { |
} |
span#revnumber, span#revdate, span#revremark { |
font-family: sans-serif; |
} |
div#footer { |
font-family: sans-serif; |
font-size: small; |
border-top: 2px solid silver; |
padding-top: 0.5em; |
margin-top: 4.0em; |
} |
div#footer-text { |
float: left; |
padding-bottom: 0.5em; |
} |
div#footer-badges { |
float: right; |
padding-bottom: 0.5em; |
} |
div#preamble { |
margin-top: 1.5em; |
margin-bottom: 1.5em; |
} |
div.tableblock, div.imageblock, div.exampleblock, div.verseblock, |
div.quoteblock, div.literalblock, div.listingblock, div.sidebarblock, |
div.admonitionblock { |
margin-top: 1.0em; |
margin-bottom: 1.5em; |
} |
div.admonitionblock { |
margin-top: 2.0em; |
margin-bottom: 2.0em; |
margin-right: 10%; |
color: #606060; |
} |
div.content { /* Block element content. */ |
padding: 0; |
} |
/* Block element titles. */ |
div.title, caption.title { |
color: #527bbd; |
font-family: sans-serif; |
font-weight: bold; |
text-align: left; |
margin-top: 1.0em; |
margin-bottom: 0.5em; |
} |
div.title + * { |
margin-top: 0; |
} |
td div.title:first-child { |
margin-top: 0.0em; |
} |
div.content div.title:first-child { |
margin-top: 0.0em; |
} |
div.content + div.title { |
margin-top: 0.0em; |
} |
div.sidebarblock > div.content { |
background: #ffffee; |
border: 1px solid silver; |
padding: 0.5em; |
} |
div.listingblock > div.content { |
border: 1px solid silver; |
background: #f4f4f4; |
padding: 0.5em; |
} |
div.quoteblock, div.verseblock { |
padding-left: 1.0em; |
margin-left: 1.0em; |
margin-right: 10%; |
border-left: 5px solid #dddddd; |
color: #777777; |
} |
div.quoteblock > div.attribution { |
padding-top: 0.5em; |
text-align: right; |
} |
div.verseblock > pre.content { |
font-family: inherit; |
} |
div.verseblock > div.attribution { |
padding-top: 0.75em; |
text-align: left; |
} |
/* DEPRECATED: Pre version 8.2.7 verse style literal block. */ |
div.verseblock + div.attribution { |
text-align: left; |
} |
div.admonitionblock .icon { |
vertical-align: top; |
font-size: 1.1em; |
font-weight: bold; |
text-decoration: underline; |
color: #527bbd; |
padding-right: 0.5em; |
} |
div.admonitionblock td.content { |
padding-left: 0.5em; |
border-left: 3px solid #dddddd; |
} |
div.exampleblock > div.content { |
border-left: 3px solid #dddddd; |
padding-left: 0.5em; |
} |
div.imageblock div.content { padding-left: 0; } |
span.image img { border-style: none; } |
a.image:visited { color: white; } |
dl { |
margin-top: 0.8em; |
margin-bottom: 0.8em; |
} |
dt { |
margin-top: 0.5em; |
margin-bottom: 0; |
font-style: normal; |
color: navy; |
} |
dd > *:first-child { |
margin-top: 0.1em; |
} |
ul, ol { |
list-style-position: outside; |
} |
ol.arabic { |
list-style-type: decimal; |
} |
ol.loweralpha { |
list-style-type: lower-alpha; |
} |
ol.upperalpha { |
list-style-type: upper-alpha; |
} |
ol.lowerroman { |
list-style-type: lower-roman; |
} |
ol.upperroman { |
list-style-type: upper-roman; |
} |
div.compact ul, div.compact ol, |
div.compact p, div.compact p, |
div.compact div, div.compact div { |
margin-top: 0.1em; |
margin-bottom: 0.1em; |
} |
div.tableblock > table { |
border: 3px solid #527bbd; |
} |
thead, p.table.header { |
font-family: sans-serif; |
font-weight: bold; |
} |
tfoot { |
font-weight: bold; |
} |
td > div.verse { |
white-space: pre; |
} |
p.table { |
margin-top: 0; |
} |
/* Because the table frame attribute is overriden by CSS in most browsers. */ |
div.tableblock > table[frame="void"] { |
border-style: none; |
} |
div.tableblock > table[frame="hsides"] { |
border-left-style: none; |
border-right-style: none; |
} |
div.tableblock > table[frame="vsides"] { |
border-top-style: none; |
border-bottom-style: none; |
} |
div.hdlist { |
margin-top: 0.8em; |
margin-bottom: 0.8em; |
} |
div.hdlist tr { |
padding-bottom: 15px; |
} |
dt.hdlist1.strong, td.hdlist1.strong { |
font-weight: bold; |
} |
td.hdlist1 { |
vertical-align: top; |
font-style: normal; |
padding-right: 0.8em; |
color: navy; |
} |
td.hdlist2 { |
vertical-align: top; |
} |
div.hdlist.compact tr { |
margin: 0; |
padding-bottom: 0; |
} |
.comment { |
background: yellow; |
} |
.footnote, .footnoteref { |
font-size: 0.8em; |
} |
span.footnote, span.footnoteref { |
vertical-align: super; |
} |
#footnotes { |
margin: 20px 0 20px 0; |
padding: 7px 0 0 0; |
} |
#footnotes div.footnote { |
margin: 0 0 5px 0; |
} |
#footnotes hr { |
border: none; |
border-top: 1px solid silver; |
height: 1px; |
text-align: left; |
margin-left: 0; |
width: 20%; |
min-width: 100px; |
} |
@media print { |
div#footer-badges { display: none; } |
} |
div#toc { |
margin-bottom: 2.5em; |
} |
div#toctitle { |
color: #527bbd; |
font-family: sans-serif; |
font-size: 1.1em; |
font-weight: bold; |
margin-top: 1.0em; |
margin-bottom: 0.1em; |
} |
div.toclevel1, div.toclevel2, div.toclevel3, div.toclevel4 { |
margin-top: 0; |
margin-bottom: 0; |
} |
div.toclevel2 { |
margin-left: 2em; |
font-size: 0.9em; |
} |
div.toclevel3 { |
margin-left: 4em; |
font-size: 0.9em; |
} |
div.toclevel4 { |
margin-left: 6em; |
font-size: 0.9em; |
} |
/contrib/toolchain/avra/examples/testcode_avra-1_2_3.asm |
---|
0,0 → 1,19 |
.device ATmega8 |
+ .db 1,2 |
+ .message "The previous line is ignored with avra-1.2.2 because .org 0 is terminated with CR only. " |
+ .message "This is line 5 but avra-1.2.2 shows line 4" |
+ .db "X%MINUTE%YEAR%" ; Take a look at this percent chars too : % % % % |
+ .db "%YEAR%HELLO%" ; Strange replacement, if one percent char is missing |
+ .db "%HOUR%:%MINUTE%%" |
+ .db "øC" ; Look at the special char. (Error in listing only. HEX-file was ok) |
+ ; Additional warning : Don't use linux editors with UTF charset ! A single special char |
+ ; (Code > 127 in codepage 850 e.g. german umlauts) could be an unvisible TWO bytes sequence |
+ ; in UTF coding. To be on the save side never use chars with code > 127. |
+ ; It's better to replace them by the code e.g. .db "M",129,"nchen" (german town 'Munich') |
+ ldi R16, ';' ; This is wrong with avra-1.2.2. |
+ ldi R16, 0x3b ; Should generate same code like above |
+ |
+; TODO : |
+; ldi R16,high (11111) ; "high(" is OK, "high (" isn't. Same with other functions... |
+ |
/contrib/toolchain/avra/examples/testcode_avra-1_3_0.asm |
---|
0,0 → 1,27 |
; Test new device |
.device ATmega328P |
; Test number sign labels |
#define TEST |
.define DOTTEST |
; Test whitespace between function name and value |
ldi r16, high(0) |
ldi r17, high (0) |
;--- |
; Test data segment start with a number sign instead of a dot |
;--- |
#DSEG |
Buffer: .BYTE 8 ; Reserve 64 bits |
;--- |
; EEPROM segment |
;--- |
.ESEG |
; Test line continuation |
AVERAGE: .db 0xF0, 0xFF, \ |
0x55, 0xFF, \ |
0x55, 0x0F |
/contrib/toolchain/avra/examples/throttle.asm |
---|
0,0 → 1,916 |
; *************************************************************************************** |
; * PWM MODEL RAILROAD THROTTLE * |
; * * |
; * "throttle.asm" * |
; * * |
; * WRITTEN BY: PHILIP DEVRIES * |
; * * |
; * Copyright (C) 2003 Philip DeVries * |
; * * |
; * This program is free software; you can redistribute it and/or modify * |
; * it under the terms of the GNU General Public License as published by * |
; * the Free Software Foundation; either version 2 of the License, or * |
; * (at your option) any later version. * |
; * * |
; * This program is distributed in the hope that it will be useful, * |
; * but WITHOUT ANY WARRANTY; without even the implied warranty of * |
; * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * |
; * GNU General Public License for more details. * |
; * * |
; * You should have received a copy of the GNU General Public License * |
; * along with this program; if not, write to the Free Software * |
; * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA * |
; * * |
; *************************************************************************************** |
; *************************************************************************************** |
; * Fixed Version for avra >= 1.2.2 because .DSEG cannot be used, if device has no SRAM * |
; * B.Arenfeld, 10.05.2007 * |
; *************************************************************************************** |
; *************************************************************************************** |
; *For Attiny 15 * |
; * * |
; *For compilation with: Avra 0.70 or later * |
; * * |
; * Atmel avrasm32.exe will not work becaue of the * |
; * use of preprocessor directives #ifdef, #ifndef * |
; * , and #endif, which Atmel doesn't support! * |
; * * |
; *Compiling requires the following files: * |
; * "tn15def.inc" Labels and identifiers for tiny15 * |
; * "throttle_dev_set.inc" Tiny 15 device settings * |
; * "throttle_op_set.inc" Operation settings (THIS IS THE ONE TO EDIT THE * |
; * COMPLIE-TIME OPTIONS ON THE WAY THE THROTTLE * |
; * PERFORMS * |
; * * |
; *Depending on the compile time options, the following files are also required: * |
; * "throttle_divide.asm" Two division routines. (one from atmel) * |
; * "throttle_set_lowpass.asm" Lowpass filter on throttle handle * |
; * "throttle_momentum.asm" Compute speed according to momentum * |
; * "throttle_momentum_lowpass.asm" Lowpass filter on momentum handle * |
; * "throttle_backemf.asm" Adjust pwm based on motor speed * |
; * "throttle_pulse.asm" Provide pulse assist at low motor speeds * |
; * "throttle_multiply.asm" atmel multiplication routine * |
; * * |
; *Subroutine Categories and Stack * |
; * * |
; * The Tiny 15 has a three level stack which handles return addresses for * |
; * subroutine calls and for interrupt service routines. The categories below * |
; * ensure that the stack does not overflow. The four (4) categories are: * |
; * * |
; * -- Top Level Routines: These routines are never called, and never * |
; * return ("ret") and so the stack is, "empty" * |
; * These routines may call any subroutine. * |
; * Register Variables: Temp, Temp1, ... * |
; * * |
; * -- First Level Subroutines: Stack has 1 entry. These routines may call * |
; * Second Level Subroutines only. * |
; * Register Variables: A_Temp, A_Temp1, ... * |
; * * |
; * -- Second Level Subroutines: Stack has 2 entries. These routines may NOT * |
; * call any subroutines. * |
; * Register Variables: B_Temp, B_Temp1, ... * |
; * * |
; * -- Interrupt Service These occur assynchronously, and therefor may * |
; * occur during Second Level Subroutines. If so, * |
; * the stack has 3 entries and IS FULL. These routines * |
; * may NOT call any subroutines. * |
; * Register Variables: I_Temp, I_Temp1, ... * |
; * * |
; * Register variables are reserved for each level of routine. Each level may freely * |
; * use the register variables for it's own level. Some sharing of variables may * |
; * occur subject to these guidelines: * |
; * -- No category execpt Interrupt Service may use Interrupt Service variables. This * |
; * is because ISRs occur asynchronously. * |
; * -- A category may NOT use variables reserved for higher level categories. * |
; * -- A category may use lower level routine variables as long as their use does not * |
; * span any subroutine calls. * |
; * * |
; *Other settings * |
; * There is no way to put these settings into this file, but these must also be * |
; * done: * |
; * * |
; * BODLEVEL: 0 4.0V * |
; * BOODEN: 0 ENABLED (brown out detection) * |
; * SPIEN: 0 ENABLED (in circuit programming) * |
; * RSTDISBL 0 DISABLED (reset on PB5) * |
; * CKSEL 11 (very quickly rising power) * |
; * LB1 1 (LB1 & LB2: No lock) * |
; * LB2 1 * |
; * * |
; * Calibration byte into flash byte address as specified in * |
; * osccal_location. * |
; * * |
; * Notes regarding these settings: * |
; * --Brown out detection. The datasheet warns against using the EEPROM without * |
; * brownout detection because of the possibility of errant execution at very low * |
; * voltage levels. * |
; * * |
; ************************************************************************************** |
;***************************************************************************************** |
;***************************************************************************************** |
;* Included files * |
;***************************************************************************************** |
;***************************************************************************************** |
.INCLUDE "tn15def.inc" ; Labels and identifiers for tiny15 |
.INCLUDE "throttle_op_set.inc" ; Operation settings |
.INCLUDE "throttle_dev_set.inc" ; Tiny 15 device settings |
;***************************************************************************************** |
;***************************************************************************************** |
;* DATA TABLE * |
;***************************************************************************************** |
;***************************************************************************************** |
;.CSEG |
;.ORG 0x01E0 ; Program .ORG 0x01E0 actually means byte |
; location 0x03C0. |
;***************************************************************************************** |
;***************************************************************************************** |
;* Data: reserved for OSCCAL byte * |
;***************************************************************************************** |
;***************************************************************************************** |
; Fix : The Tiny15 has NO SRAM. Use of .DSEG is invalid ! |
;.DSEG |
; |
;.SET osccal_location = 0x3FF ;Place in the last byte of program memory. |
; ;High byte of program memory 1FF |
; |
;.ORG osccal_location ;reserve this byte for oscillator |
;.BYTE 1 ;calibration value |
; Fixed Version for avra >= 1.2.2 |
.CSEG |
.EQU osccal_location = 0x3FF ; The last flash byte is used for the calibration |
; value and is replaced by the programmer |
; Now reserve the last word in flash memory. If you are sure, that the program doesn't use |
; the last flash word, you can disable the following lines. If not, it's better to enable |
; them to check for overlapping code segments. |
.ORG 0x01FF ; Last word in flash memory |
.DB 0xff,0xff ; Fill with dummy values. Only last byte is used |
; but flash is organized in words. |
; 0xff is the value of unprogrammed flash |
;***************************************************************************************** |
;***************************************************************************************** |
;* Reset and Interrupt Vectors * |
;***************************************************************************************** |
;***************************************************************************************** |
.CSEG |
.ORG 0x000 |
rjmp ST_RESET |
.ifdef OVERLOAD_ENABLED |
rjmp ST_PWM_LEVEL_OFF ; INT0 interrupt handler |
.else |
reti ; Not used. |
.endif ;OVERLOAD_ENABLED |
reti ; Not used. rjmp PIN_CHANGE |
reti ; Not used. rjmp TIM1_CMP |
reti ; Not used. rjmp TIM1_OVF |
reti ; Not used. rjmp TIM0_OVF |
reti ; Not used. rjmp EE_RDY |
reti ; Not used. rjmp ANA_COMP |
reti ; Not used. rjmp ADC |
;***************************************************************************************** |
;***************************************************************************************** |
;* Top level routines. The basic program is a state machine, with states all being * |
;* top level routines. These routines are never used as subroutines * |
;* and therefore can call any subroutine. * |
;***************************************************************************************** |
;***************************************************************************************** |
;******************************************************************************** |
;* ST_RESET * |
;* This is power on reset. The reset vector points here. * |
;* * |
;* Inputs: none * |
;* Returns: none * |
;* Changed: B_Temp * |
;* Calls: * |
;* Goto: ST_MOTOR_OFF * |
;******************************************************************************** |
ST_RESET: |
cli ; Disable interrupts |
ldi B_Temp,(dir_out_port_bit | pwm_port_bit | dir_in_port_bit | momentum_port_bit) |
out DDRB,B_Temp ; Assign output port directions. |
; Inclusion in the above list makes the |
; port an output port |
ldi B_Temp,0x00 ; A "1" makes output logic level high |
out PORTB,B_Temp ; A "1" assigns pullups on inputs |
; Therefore all outputs are at logic low, and |
; all inputs do not have a pullup assigned |
ldi B_Temp,acsr_val ; Disable comparator and interrupt |
out ACSR,B_Temp ; Using port for PWM |
; (comparator defaults to powered up) |
ldi B_Temp,0b01000010 ; Disable pullups. |
out MCUCR,B_Temp ; Set sleep mode (moot) |
; INT0 interrupt on falling edge |
ldi ZL,low(osccal_location) ; r30 |
ldi ZH,high(osccal_location) ; r31 |
lpm |
out OSCCAL,Implicit ; Place calibration byte |
ldi B_Temp,0b00001010 ; Enable watchdog |
out WDTCR,B_Temp ; timout 64mS (nom) |
ldi B_Temp1,pwm_period ; Set pwm oscillator period |
out OCR1B,B_Temp1 |
ldi B_Temp1,tccr1_enable_t1 ; Turn on the PWM oscillator |
out TCCR1,B_Temp1 |
ldi Flags_1,(0b00000000 | F_stop) ; Set emergency stop flag so that |
; throttle doesn't start on powerup |
.ifdef TRADITIONAL_ENABLED |
.ifdef MOMENTUM_LOWPASS_ENABLED |
clr momentum_lo_prev ; MOMENTUM LOWPASS |
clr momentum_hi_prev ; Clear the history |
.endif ;MOMENTUM_LOWPASS_ENABLED |
.endif ;TRADITIONAL_ENABLED |
; rjmp ST_EMERGENCY_STOP ; ***EXIT STATE*** |
;******************************************************************************** |
;* ST_EMERGENCY_STOP * |
;* * |
;* Reset to "off" state. * |
;* Clear global variables associated with momentum and lowpass filters. * |
;* * |
;* Inputs: none * |
;* Returns: none * |
;* Changed: Global variables cleared * |
;* Calls: None * |
;* Goto: ST_PWM_LEVEL_OFF If throttle is zero * |
;******************************************************************************** |
ST_EMERGENCY_STOP: |
.ifdef BACKEMF_ENABLED |
.ifdef LOWPASS_ENABLED ; BACKEMF LOWPASS |
clr error_hi_prev ; Clear the history |
clr error_lo_prev |
.endif ;LOWPASS_ENABLED |
.endif ;BACKEMF_ENABLED |
.ifdef MOMENTUM_ENABLED ; MOMENTUM |
clr speed_lo_prev ; Clear the history |
clr speed_hi_prev |
.endif ;MOMENTUM_ENABLED |
.ifdef TRADITIONAL_ENABLED |
.ifdef WALKAROUND_ENABLED |
clr throttle_hold ; Clear the history |
.endif ;WALKAROUND_ENABLED |
.ifdef THROTTLE_LOWPASS_ENABLED |
clr throttle_lo_prev ; THROTTLE LOWPASS |
clr throttle_hi_prev ; Clear the history |
.endif ;THROTTLE_LOWPASS_ENABLED |
.endif ;TRADITIONAL_ENABLED |
; rjmp ST_PWM_LEVEL_OFF ; ***EXIT STATE*** |
;******************************************************************************** |
;* ST_PWM_LEVEL_OFF * |
;* ST_MEASUREMENT_SETTLE * |
;* 1. If entered at ST_PWM_LEVEL_OFF turn pwm off * |
;* 2. Set the ADC ports to input * |
;* 3. Pause to let ADC inputs (including back-emf) settle. * |
;* 4. Read the throttle controller. * |
;* 5. Set LED ports and overload ports (also ADC inputs) to output * |
;* 6. If throttle_set is not zero, or if motor is still running by momentum * |
;* continue running motor (jump to ST_SET_NEW_PWM) * |
;* 7. If throttle set is zero and motor is not running, then set the direction * |
;* relay and test backemf input to determine backemf mode. * |
;* 8. Turn of motor (jump to ST_PWM_LEVEL_OFF) * |
;* * |
;* Inputs: none * |
;* Returns: none * |
;* Changed: B_Temp, B_Temp1 * |
;* Calls: READ_THROTTLE * |
;* Goto: ST_PWM_LEVEL_OFF If throttle is zero * |
;* ST_SET_NEW_PWM After delay * |
;******************************************************************************** |
ST_PWM_LEVEL_OFF: |
clr B_Temp ; Set PWM duty = 0. |
rcall SET_PWM_DUTY ; i.e. turn off the power |
ST_MEASUREMENT_SETTLE: |
;******************************************** |
;* Set all measurement ports for input and pause. |
;* During the pause: |
;* 1. inductive current in the locomotive falls to zero, and |
;* the backemf voltage appears on the backemf port |
;* 2. the momentum, direction, and throttle voltages stabilize |
;******************************************** |
.ifdef TRADITIONAL_ENABLED |
.ifdef LEDS_ENABLED |
cbi DDRB,momentum_port ; Make input port (pullup must be disabled) |
cbi DDRB,dir_in_port ; Make input port (pullup must be disabled) |
.endif ;LEDS_ENABLED |
.ifdef OVERLOAD_ENABLED |
in B_Temp,GIMSK ; disable INT0 interrupt |
andi B_Temp,0b10111111 |
out GIMSK,B_Temp |
cbi DDRB,throttle_port ; Make input port (pullup must be disabled) |
.endif ;OVERLOAD_ENABLED |
.endif ;TRADITIONAL_ENABLED |
sei ; Enable interrupts |
wdr ; Reset watchdog timer |
ldi B_Temp1,pwm_full_count ; Pause for inputs to settle |
rcall COUNT_PWM_CYCLES |
clr Cycle_count |
;******************************************** |
;* Read the input ports and make some |
;* mode decisions based on those inputs. |
;******************************************** |
rcall READ_THROTTLE ; Find throttle handle position in throttle_set |
.ifdef TRADITIONAL_ENABLED |
.ifdef MOMENTUM_ENABLED |
.ifdef MOMENTUM_LOWPASS_ENABLED |
.include "throttle_momentum_lowpass.asm" |
.endif;MOMENTUM_LOWPASS_ENABLED |
.endif; MOMENTUM_ENABLED |
.endif ;TRADITIONAL_ENABLED |
.ifdef DIRECTION_ENABLED ; Check Stop, and Adjust Direction |
CHECKING_STOP: |
sbrs Flags_1,BF_stop ; Check stop flag is set |
rjmp DONE_CHECKING_STOP |
cpi throttle_set,0x00 ; If throttle handle is at zero |
brne ST_EMERGENCY_STOP ; reset the emergency stop flag |
cbr Flags_1,F_stop ; reset emergency stop flag. |
rjmp ST_EMERGENCY_STOP ; ALWAYS STOP |
DONE_CHECKING_STOP: |
CHECKING_DIRECTION: |
.ifdef MOMENTUM_ENABLED |
mov B_Temp,speed_hi_prev ; Don't set direction unless the actual |
cpi B_Temp,direction_threshold ; speed is less than direction_threshold |
brsh DONE_CHECKING_DIRECTION |
.else |
cpi throttle_set,0x00 ; Don't set direction unless the throttle |
brne DONE_CHECKING_DIRECTION ; handle is at zero |
.endif ;MOMENTUM_ENABLED |
sbic PORTB,dir_out_port ; Find port direction |
rjmp PORT_REVERSE |
;rjmp PORT_FORWARD |
PORT_FORWARD: |
sbrs Flags_1,BF_reverse ; If port says forward |
rjmp DONE_CHECKING_DIRECTION |
sbi PORTB,dir_out_port ; But flag says reverse, then reverse |
rjmp ST_EMERGENCY_STOP |
PORT_REVERSE: |
sbrc Flags_1,BF_reverse ; If port says reverse |
rjmp DONE_CHECKING_DIRECTION |
cbi PORTB,dir_out_port ; But flag says foreward, then forward |
rjmp ST_EMERGENCY_STOP |
DONE_CHECKING_DIRECTION: |
.endif ;DIRECTION_ENABLED |
.ifdef TRADITIONAL_ENABLED |
.ifdef THROTTLE_LOWPASS_ENABLED |
.include "throttle_set_lowpass.asm" |
.endif ;THROTTLE_LOWPASS_ENABLED |
.endif ;TRADITIONAL_ENABLED |
cpi throttle_set,0x00 ; Run the pwm unless the throttle |
brne ST_SET_NEW_PWM ; is zero |
.ifdef MOMENTUM_ENABLED |
mov B_Temp,speed_hi_prev ; In momentum mode, run the pwm unless |
cpi B_Temp,0x00 ; the actual throttle setting reaches zero |
brne ST_SET_NEW_PWM |
.endif ;MOMENTUM_ENABLED |
;******************************************** |
;* Only arrive here if the throttle is set for 0 speed |
;* and the locomotive is actually stopped (momentum) |
;******************************************** |
.ifdef BACKEMF_ENABLED |
;******************************************** |
;* The backemf measurement should be at or near zero, |
;* since the locomotive is stopped. If it isn't, |
;* do not use backemf speed control. |
;******************************************** |
sbr Flags_1,F_use_backemf ; Default to use backemf |
rcall ADC_SETUP_EMF ; 4 lines read the backemf |
WAIT_FOR_VALID: |
sbis ADCSR,ADIF |
rjmp WAIT_FOR_VALID |
in B_Temp,ADCH ; Read the measurement |
cpi B_Temp,0x40 ; Test measurement |
brlo END_CHECK_BACKEMF_MODE ; If small, use backemf adjustment. |
cbr Flags_1,F_use_backemf ; Otherwise, don't use backemf |
END_CHECK_BACKEMF_MODE: |
.endif ;BACKEMF_ENABLED |
.ifdef TRADITIONAL_ENABLED |
.ifdef LOCO_LIGHT_ENABLED |
ldi throttle_set,light_pwm |
rjmp STABLE_PWM_SET |
.else |
rjmp ST_PWM_LEVEL_OFF |
.endif ;LOCO_LIGHT_ON |
.else |
rjmp ST_PWM_LEVEL_OFF |
.endif ;TRADITIONAL_ENABLED |
;******************************************************************************** |
;* ST_SET_NEW_PWM * |
;* Compute the pwm setting based upon momentum, backemf, and throttle setting * |
;* Inputs: throttle_set * |
;* Returns: none * |
;* Changed: throttle_set, other variables in included files * |
;* Calls: various in included files * |
;* Goto: ST_PWM_LEVEL_ON * |
;******************************************************************************** |
ST_SET_NEW_PWM: |
.ifdef TRADITIONAL_ENABLED |
.ifdef LEDS_ENABLED |
cbi PORTB,dir_in_port ; logic low out (turn off LED) |
sbi DDRB,dir_in_port ; Assign output to drive led (output is low) |
cbi PORTB,momentum_port ; logic low out (turn off LED) |
sbi DDRB,momentum_port ; Assign output to drive led (output is low) |
.endif ;LEDS_ENABLED |
.ifdef OVERLOAD_ENABLED |
;******************************************** |
;* The thottle port is driven to logic high. If this port gets pulled |
;* low (overload), this triggers the INT0 interrupt, which will shut off |
;* the pwm. |
;******************************************** |
sbi PORTB,throttle_port ; Logic hi out. |
sbi DDRB,throttle_port ; Make output port. |
.endif ;OVERLOAD_ENABLED |
.endif ;TRADITIONAL_ENABLED |
.ifdef MOMENTUM_ENABLED |
.include "throttle_momentum.asm" ; momentum adjustment |
.endif ;MOMENTUM_ENABLED |
.ifdef TRADITIONAL_ENABLED |
.ifdef WALKAROUND_ENABLED |
mov throttle_hold,throttle_set |
.endif ;WALKAROUND_ENABLED |
.endif ;TRADITIONAL_ENABLED |
.ifdef BACKEMF_ENABLED ;******************************************** |
; Adjust throttle_set according to |
; measured backemf. |
;******************************************** |
sbrs Flags_1,BF_use_backemf ; If the flag is set, use backemf |
rjmp DONT_BACKEMF ; Otherwise, don't |
.include "throttle_backemf.asm" |
; If using backemf, don't use throttle_scale |
rjmp ST_PWM_LEVEL_ON ; ***EXIT STATE*** |
DONT_BACKEMF: |
.endif ;BACKEMF |
;***************************************************************** |
;* Scale the throttle_set between 0 and pwm_period * |
;* multiply pwm_period and throttle_set and divide by 256 * |
;* read answer from hi byte of return. * |
;***************************************************************** |
HILOCAL1 _main_scale_multiplicand |
B_TEMPLOCAL _main_scale_multiplier |
B_TEMPLOCAL1 _main_scale_result_hi |
ldi _main_scale_multiplicand,pwm_period - pwm_min |
mov _main_scale_multiplier,throttle_set |
rcall mpy8u ; multiply |
mov throttle_set,_main_scale_result_hi ; read result |
; rjmp ST_PWM_LEVEL_ON ; ***EXIT STATE*** |
;******************************************************************************** |
;* ST_PWM_LEVEL_ON * |
;* 1. Enable overload testing * |
;* 2. Produce pulse if required * |
;* 3. Run pwm at throttle_set * |
;* 4. Wait for a while * |
;* * |
;* Inputs: throttle_set * |
;* Returns: none * |
;* Changed: B_Temp, B_Temp1, various * |
;* Calls: SET_PWM_DUTY * |
;* COUNT_PWM_CYCLES * |
;* Goto: ST_PWM_LEVEL_OFF After PWM goes to off state * |
;******************************************************************************** |
ST_PWM_LEVEL_ON: |
.ifdef TRADITIONAL_ENABLED |
.ifdef OVERLOAD_ENABLED |
ldi B_Temp,0b01000000 ; clear INT0 interrupt |
out GIFR,B_Temp |
in B_Temp,GIMSK ; enable INT0 interrupt |
ori B_Temp,0b01000000 |
out GIMSK,B_Temp |
.endif ;OVERLOAD_ENABLED |
.endif ;TRADITIONAL_ENABLED |
cpi throttle_set,light_pwm ; never run pwm lower than light_pwm level |
brsh DONE_CHECKING_MINIMUM |
ldi throttle_set,light_pwm |
rjmp STABLE_PWM_SET |
DONE_CHECKING_MINIMUM: |
.ifdef PULSE_ENABLED ; Produce pulses during output |
.ifdef BACKEMF_ENABLED |
sbrc Flags_1,BF_use_backemf ; If the flag is set to use backemf |
rjmp STABLE_PWM_SET ; don't pulse |
.endif ;BACKEMF_ENABLED |
; Pass in: throttle_set |
.include "throttle_pulse.asm" |
.endif ;PULSE_ENABLED |
STABLE_PWM_SET: |
mov B_Temp,throttle_set ; Stabilize at throttle_set |
rcall SET_PWM_DUTY |
ldi B_Temp1,pwm_full_count-pwm_settle_count |
rcall COUNT_PWM_CYCLES ; Wait for end of interval |
.ifdef BACKEMF_ENABLED |
sbrc Flags_1,BF_use_backemf ; If the flag is set to use backemf |
rjmp ST_PWM_LEVEL_OFF ; ***EXIT STATE*** |
.endif ;BACKEMF_ENABLED |
rjmp ST_MEASUREMENT_SETTLE ; ***EXIT STATE*** |
;***************************************************************************************** |
;***************************************************************************************** |
;* First Level Subroutines. * |
;* These routines include the routines which are called by other code and also call * |
;* Second Level Subroutines. * |
;***************************************************************************************** |
;***************************************************************************************** |
;******************************************************************************** |
;* READ_THROTTLE * |
;* First Level Subroutine * |
;* * |
;* Read the throttle controls, which are: * |
;* Momentum level (analog): Returned in "momentum_set" * |
;* Returns and 8 bit number, with '0' meaning minimum momentum. * |
;* * |
;* Direction, brake, and stop switch. * |
;* Returns value in flags: F_brake, F_reverse, and F_stop * |
;* * |
;* Throttle setting (analog: Returned in "throttle_set" * |
;* Returns an 8 bit number (0x00 to 0xFF; 0 to 255), * |
;* where '0' means "motor off" and 0xFF (255) means full speed. * |
;* * |
;* If a speed table is implemented, it will be in this routine * |
;* * |
;* Just now, this value comes from the analog input and is converted by the * |
;* ADC. The raw 8 bit number is returned. * |
;* * |
;* Inputs: None * |
;* Returns: Momentum setting in "momentum_set" * |
;* Switch positions in F_brake, F_reverse, and F_stop * |
;* Throttle setting in "throttle_set" * |
;* Changed: Cycle_count incremented by up to 5 * |
;* Calls: ADC_SETUP_MOMENTUM * |
;* ADC_SETUP_DIRECTION * |
;* ADC_SETUP_THROTTLE * |
;******************************************************************************** |
READ_THROTTLE: |
.ifdef TRADITIONAL_ENABLED |
.ifdef DIRECTION_ENABLED |
;******************************************** |
;* Measure the direction, brake, and stop switches and |
;* set the flags appropriately |
;******************************************** |
rcall ADC_SETUP_DIRECTION ; Setup to read |
WAIT_FOR_VALID_DIRECTION: |
sbis ADCSR,ADIF ; Check for ADC completion |
rjmp WAIT_FOR_VALID_DIRECTION |
in B_Temp,ADCH ; Read value |
.ifdef WALKAROUND_ENABLED |
cpi B_Temp,0x90 ; Above this threshold |
; deactivates handheld controller |
; brsh HOLD_THROTTLE |
brlo HOLD_THROTTLE_NOT |
rjmp HOLD_THROTTLE |
HOLD_THROTTLE_NOT: |
.endif ;WALKAROUND_ENABLED |
cpi B_Temp,0x1B ; Below this threshold (0.53V) sets 'stop' flag |
brsh TEST_BRAKE_LEVEL ; Typical stop voltage is 0.30V |
.ifdef SWITCH_LOWPASS_ENABLED |
sbrs Flags_2,BF_stop_count ; If the stop count flag is not set, then |
clr Flags_2 ; set the counter to zero |
cbr Flags_2,F_stop_count ; clear the stop count flag |
inc Flags_2 ; increment the counter |
cpi Flags_2,stop_count_max ; compare the count to the maximum |
sbr Flags_2,F_stop_count ; set the stop count flag |
brlo END_READ_DIRECTION ; if the count is lower, don't change status flag |
dec Flags_2,F_stop_count ; decrement stop count flag |
.endif;SWITCH_LOWPASS_ENABLED |
sbr Flags_1,F_stop |
rjmp END_READ_DIRECTION |
TEST_BRAKE_LEVEL: |
cpi B_Temp,0x37 ; Below this threshold (1.07V) sets 'brake' flag |
brsh TEST_REVERSE_LEVEL ; Typical brake voltage 0.87V |
.ifdef SWITCH_LOWPASS_ENABLED |
sbrs Flags_2,BF_brake_count ; If the brake count flag is not set, then |
clr Flags_2 ; set the counter to zero |
cbr Flags_2,F_brake_count ; clear the break count flag |
inc Flags_2 ; increment the counter |
cpi Flags_2,brake_count_max ; compare the count to the maximum |
sbr Flags_2,F_brake_count ; set the break count flag |
brlo END_READ_DIRECTION ; if the count is lower, don't change status flag |
dec Flags_2,F_brake_count ; decrement break count flag |
.endif;SWITCH_LOWPASS_ENABLED |
sbr Flags_1,F_brake |
rjmp END_READ_DIRECTION |
TEST_REVERSE_LEVEL: |
cpi B_Temp,0x53 ; Below this threshold (1.62V) sets 'reverse' flag |
brsh TEST_FOREWARD_LEVEL ; Typical reverse level 1.40V |
.ifdef SWITCH_LOWPASS_ENABLED |
sbrs Flags_2,BF_reverse_count ; If the reverse count flag is not set, then |
clr Flags_2 ; set the counter to zero |
cbr Flags_2,F_reverse_count ; clear the reverse count flag |
inc Flags_2 ; increment the counter |
cpi Flags_2,reverse_count_max ; compare the count to the maximum |
sbr Flags_2,F_reverse_count ; set the reverse count flag |
brlo END_READ_DIRECTION ; if the count is lower, don't change status flag |
dec Flags_2,F_reverse_count ; decrement reverse count flag |
.endif;SWITCH_LOWPASS_ENABLED |
cbr Flags_1,F_brake ; Clear brake flag |
sbr Flags_1,F_reverse ; Set brake flag |
rjmp END_READ_DIRECTION |
TEST_FOREWARD_LEVEL: ; Typical "nothing" 1.95V |
;no test required |
.ifdef SWITCH_LOWPASS_ENABLED |
sbrs Flags_2,BF_foreward_count ; If the foreward count flag is not set, then |
clr Flags_2 ; set the counter to zero |
cbr Flags_2,F_foreward_count ; clear the foreward count flag |
inc Flags_2 ; increment the counter |
cpi Flags_2,foreward_count_max ; compare the count to the maximum |
sbr Flags_2,F_foreward_count ; set the foreward count flag |
brlo END_READ_DIRECTION ; if the count is lower, don't change status flag |
dec Flags_2,F_foreward_count ; decrement forward count flag |
.endif;SWITCH_LOWPASS_ENABLED |
cbr Flags_1,F_brake ; Clear brake flag |
cbr Flags_1,F_reverse ; Clear reverse flag (i.e., foreward) |
END_READ_DIRECTION: |
.endif ;DIRECTION_ENABLED |
.ifdef MOMENTUM_ENABLED |
;******************************************** |
;* Measure and adjust the momentum input |
;******************************************** |
rcall ADC_SETUP_MOMENTUM ; Setup to read |
WAIT_FOR_VALID_MOMENTUM: |
sbis ADCSR,ADIF ; Wait for ADC completion |
rjmp WAIT_FOR_VALID_MOMENTUM |
in momentum_set,ADCH ; Read value |
.ifdef WALKAROUND_ENABLED |
ldi B_Temp,0x90 |
cp momentum_set,B_Temp ; Above this threshold |
; deactivates handheld controller |
brsh HOLD_THROTTLE |
.endif ;WALKAROUND_ENABLED |
ldi B_Temp,0x40 |
sub momentum_set,B_Temp ; Subtract offset (1/4 of 0xFF) |
brsh END_READ_MOMENTUM |
sub momentum_set,momentum_set ; If smaller than offset, make zero |
END_READ_MOMENTUM: |
.endif ;MOMENTUM_ENABLED |
;******************************************** |
;* Read the throttle level |
;******************************************** |
rcall ADC_SETUP_THROTTLE |
WAIT_FOR_VALID_THROTTLE: |
sbis ADCSR,ADIF ; Check for ADC completion |
rjmp WAIT_FOR_VALID_THROTTLE |
in throttle_set,ADCH ; Read throttle value |
subi throttle_set,0x08 ; Subtract offset (force zero) |
brcc DONE_READ_THROTTLE ; If new throttle is negative, |
clr throttle_set ; make throttle zero. |
DONE_READ_THROTTLE: |
subi Cycle_count,256-3 ; Normal arrival here occurs after 3 adc |
ret ; conversions, which take 195uS, or 4.875 |
; pwm cycles |
.ifdef WALKAROUND_ENABLED |
HOLD_THROTTLE: ; Normal arrival here occurs after 1 adc |
; conversion, which takes 65uS, or 1.625 |
; pwm cycles |
cbr Flags_1,F_brake ; Clear brake flag |
mov throttle_set,throttle_hold ; Use previous value. |
.ifdef SWITCH_LOWPASS_ENABLED |
clr Flags_2 |
.endif;SWITCH_LOWPASS_ENABLED |
.ifdef MOMENTUM_ENABLED |
ldi B_Temp,0x40 |
mov momentum_set,B_Temp ; 'long' momentum |
.endif ;MOMENTUM_ENABLED |
ret |
.endif ;WALKAROUND_ENABLED |
.else ;NOT TRADITIONAL_THROTTLE |
sbr Flags_1,F_stop |
ret |
.endif ;TRADITIONAL_THROTTLE |
;******************************************************************************** |
;* COUNT_PWM_CYCLES * |
;* First evel Subroutine * |
;* * |
;* Increment Cycle_count timer each PWM cycle. * |
;* Return when Cycle_count = B_Temp1 * |
;* * |
;* Inputs: B_Temp1 Exit when count reaches this number * |
;* Returns: None * |
;* Changed: B_Temp,Cycle_count * |
;* Calls: None * |
;******************************************************************************** |
COUNT_PWM_CYCLES: |
in B_Temp,TIFR ; Wait for pwm timer to reset |
sbrs B_Temp,OCF1A |
rjmp COUNT_PWM_CYCLES |
ldi B_Temp,0b01000000 ; reset interrupt flag |
out TIFR,B_Temp |
inc Cycle_count ; increment counter and repeat |
cp Cycle_count,B_Temp1 |
brne COUNT_PWM_CYCLES |
ret |
;***************************************************************************************** |
;***************************************************************************************** |
;* Second Level Subroutines. * |
;* These routines make no further subroutine calls. * |
;***************************************************************************************** |
;***************************************************************************************** |
.include "throttle_divide.asm" |
.include "throttle_multiply.asm" |
;******************************************************************************** |
;* SET_PWM_DUTY * |
;* Second Level Subroutine * |
;* * |
;* Inputs: B_Temp PWM on count * |
;* Returns: None * |
;* Changed: None * |
;* Calls: Not allowed * |
;******************************************************************************** |
SET_PWM_DUTY: |
out OCR1A,B_Temp ; Set the PWM equal to the input B_Temp |
ret |
;******************************************************************************** |
;* ADC_SETUP_DIRECTION * |
;* ADC_SETUP_MOMENTUM * |
;* ADC_SETUP_THROTTLE * |
;* ADC_SETUP_BACK_EMF * |
;* Second Level Subroutine * |
;* * |
;* The ADC is switched off, and restarted on the selected port. * |
;* * |
;* Inputs: None * |
;* Returns: None * |
;* Changed: Various B_Temp variables * |
;* Calls: Not allowed * |
;******************************************************************************** |
.ifdef DIRECTION_ENABLED |
ADC_SETUP_DIRECTION: |
ldi B_Temp,admux_direction ; Setup MUX for direction/brake measurement |
rjmp ADC_SETUP |
.endif ;DIRECTION_ENABLED |
.ifdef MOMENTUM_ENABLED |
ADC_SETUP_MOMENTUM: |
ldi B_Temp,admux_momentum ; Setup MUX for momentum set measurement |
rjmp ADC_SETUP |
.endif ;MOMENUTM_ENABLED |
.ifdef BACKEMF_ENABLED |
ADC_SETUP_EMF: |
ldi B_Temp,admux_emf ; Setup MUX for back_emf measurement |
rjmp ADC_SETUP |
.endif ;BACKEMF_ENABLED |
.ifdef TRADITIONAL_ENABLED |
ADC_SETUP_THROTTLE: |
ldi B_Temp,admux_throttle ; Setup MUX for analog measure |
; rjmp ADC_SETUP ; of throttle. |
.endif ;TRADITIONAL_ENABLED |
ADC_SETUP: |
ldi B_Temp1,adcsr_off ; Turn off the ADC |
out ADCSR,B_Temp1 ; |
out ADMUX,B_Temp ; Setup MUX as per entry point |
ldi B_Temp,adcsr_enable ; enable ADC, disable interrupt, clear |
out ADCSR,B_Temp ; interrupt flag, free-running. |
ret |
;***************************************************************************************** |
;***************************************************************************************** |
;* Interrupt Service routines. * |
;* These routines can occur assynchronously. Therfore, they might occur during a second * |
;* level routine. Therefore THEY MAY NOT CALL ANY SUBROUTINES. * |
;***************************************************************************************** |
;***************************************************************************************** |
/contrib/toolchain/avra/examples/throttle_backemf.asm |
---|
0,0 → 1,328 |
;throttle_backemf.asm |
.NOLIST |
; *************************************************************************************** |
; * PWM MODEL RAILROAD THROTTLE * |
; * * |
; * WRITTEN BY: PHILIP DEVRIES * |
; * * |
; * Copyright (C) 2003 Philip DeVries * |
; * * |
; * This program is free software; you can redistribute it and/or modify * |
; * it under the terms of the GNU General Public License as published by * |
; * the Free Software Foundation; either version 2 of the License, or * |
; * (at your option) any later version. * |
; * * |
; * This program is distributed in the hope that it will be useful, * |
; * but WITHOUT ANY WARRANTY; without even the implied warranty of * |
; * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * |
; * GNU General Public License for more details. * |
; * * |
; * You should have received a copy of the GNU General Public License * |
; * along with this program; if not, write to the Free Software * |
; * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA * |
; * * |
; *************************************************************************************** |
.LIST |
.ifdef BACKEMF_ENABLED |
;******************************************************************************** |
;* BACKEMF_ADJUST * |
;* Top level routine * |
;* * |
;* The throttle_set is compared against the back emf generated by the motor * |
;* and adjusted to reduce the error * |
;* * |
;* Inputs: throttle_set Target speed * |
;* Returns: throttle_set Adjusted target speed * |
;* Changed: error_hi Adjusted throttle, upper 8 bits (local) * |
;* error_lo Adjusted throttle, lower 8 bits (local) * |
;* error_hi_prev Previous throttle, for filter (global) * |
;* error_lo_prev Previous throttle, for filter (global) * |
;* emf_hi Measured emf, upper 8 bits (local) * |
;* emf_lo Measured emf, lower 8 bits (local) * |
;* B_Temp,B_Temp1 * |
;* Calls: ADC_SETUP_EMF * |
;* div16u * |
;* DIVIDE_16_SIMPLE * |
;* Goto: none * |
;******************************************************************************** |
HILOCAL1 error_lo ; assign local variables |
HILOCAL2 error_hi |
;***************************************************************** |
;*Convert throttle setting into 2 byte 2's compl. * |
;* * |
;* This is a 7 bit number plus 1 more bits after the radix * |
;* It is in (error_hi) -radix- (error_lo) * |
;***************************************************************** |
mov error_hi,throttle_set ; Put throttle into 16 bit form |
clr error_lo |
lsr error_hi ; Convert to 2's compliment |
ror error_lo |
;******************************************************************************** |
;* READ_BACKEMF * |
;* Returns a 2 byte 2's compliment measurement of the motor backemf. * |
;* * |
;* 1. Add together 8 samples of the (8 bit) pwm value in the two byte * |
;* emf_hi--emf_lo register. * |
;* 2. Multiply by 16. * |
;* 3. Result: Minimum value = 0x000 (decimal 0) * |
;* Maximum value = 0x7F8 (decimal 2040) * |
;* * |
;* Time required: * |
;* 1. 1st Sample: 125uS * |
;* 2. next 7 Samples: 455uS * |
;* 3. balance of Subroutine: 10's of uS * |
;* TOTAL 580uS min * |
;* * |
;* Each cycle of the 25kHz PWM takes 40uS, therefore, this routine takes * |
;* at least 14.5 cycles of the 25kHz pwm. * |
;* * |
;* Inputs: None * |
;* Returns: emf_hi--emf_lo: 2 Byte 2's compl (but always positive) * |
;* measure of motor backemf. * |
;* Changed: B_Temp,B_Temp1 * |
;* Calls: ADC_SETUP_EMF * |
;******************************************************************************** |
LOWLOCAL1 emf_hi ; Names of local registers |
LOWLOCAL2 emf_lo |
;READ_BACKEMF: |
rcall ADC_SETUP_EMF ; Setup ADC to measure back_emf. |
clr emf_lo ; Clear the value of emf. |
clr emf_hi |
ldi B_Temp,8 ; Add 8 samples |
WAIT_FOR_EMF_MEASURE: ; Wait for a measurement of the EMF |
sbis ADCSR,ADIF |
rjmp WAIT_FOR_EMF_MEASURE |
in B_Temp1,ADCH ; Read the measurement |
sbi ADCSR,4 ; Clear the interrupt |
add emf_lo,B_Temp1 ; Add to low byte (no carry) |
clr B_Temp1 |
adc emf_hi,B_Temp1 ; Add carry to high byte. |
dec B_Temp |
brne WAIT_FOR_EMF_MEASURE ; Measure for complete set |
; Sum of 8 samples. |
ldi B_Temp,4 ; Convert 11 bit number into a 15 bit |
COMPUTE_EMF_AVERAGE: ; number (only 11 significant figures |
lsl emf_lo ; though) |
rol emf_hi |
dec B_Temp |
brne COMPUTE_EMF_AVERAGE |
;***************************************************************** |
;* Compute the error. That is, throttle = throttle - emf * |
;* * |
;* The result is a two byte number (signed two's compl) in * |
;* error_hi -radix- error_lo * |
;***************************************************************** |
sub error_lo,emf_lo ; subtract low bytes (after radix) |
sbc error_hi,emf_hi ; subtract high bytes (before radix) |
.ifdef BACKEMF_SCALE_ENABLED |
;***************************************************************** |
;* Error multiplier (complex) * |
;* * |
;* Error gain is equal to: * |
;* * |
;* Error err_scale err_mult * |
;* ------------------------ * 2 * 2 * |
;* err_scale * |
;* 2 + throttle_set * |
;* * |
;* The maximum gain when throttle_set = 0 is 2^err_mult * |
;* is cut in half when throttle_set = 2^err_scale * |
;* * |
;* Result is signed two's compliment in * |
;* error_hi--error_lo -radix- * |
;***************************************************************** |
cbr Flags_1,F_negative_err ; Assume error is positive |
sbrs error_hi,7 ; Test algebraic sign |
rjmp POSITIVE_ERR |
sbr Flags_1,F_negative_err ; If error is negative, set flag. |
com error_lo ; Convert to positive |
com error_hi |
subi error_lo,0xFF |
sbci error_hi,0xFF |
POSITIVE_ERR: |
B_TEMPLOCAL _bemf_lo_byte |
B_TEMPLOCAL1 _bemf_hi_byte |
mov _bemf_lo_byte,throttle_set ; Divisor = throttle_set+2^err_scale |
clr _bemf_hi_byte |
ldi B_Temp2,EXP2(err_scale) |
add _bemf_lo_byte,B_Temp2 |
adc _bemf_hi_byte,_bemf_hi_byte |
; mov dd16uL,error_lo ; Dividend = error (same register) |
; mov dd16uH,error_hi |
rcall div16u ; Divide error by (throttle+offset) |
; (almost 4 pwm cycles) |
; adds 3 to Cycle_count |
; mov error_lo,dres16uL ; Same register |
; mov error_hi,dres16uH |
sbrs Flags_1,BF_negative_err ; Check sign flag |
rjmp POSITIVE_ERR_1 |
com error_lo ; Convert back to negative |
com error_hi ; if necessary |
subi error_lo,0xFF |
sbci error_hi,0xFF |
POSITIVE_ERR_1: ; Scale for maximum |
ldi _bemf_lo_byte, 7 - error_mult - err_scale |
rcall DIVIDE_16_SIMPLE |
.else ;case BACKEMF_SCALE_ENABLED is NOT enabled |
;***************************************************************** |
;* Error multiplier (simple) * |
;* * |
;* The error multiplier setting (error_mult) can range * |
;* from -8 to +7, and the actual error multiplier is * |
;* 2^(error_mult), which therefore ranges from 1/256 to 128. * |
;* * |
;* Step 1. Multiply by 2^8. * |
;* Equivalent to moving the radix point to after * |
;* error_lo. THIS STEP REQUIRES NO CODE * |
;* * |
;* Step 2. Divide by 2^(error_mult - 8) * |
;* * |
;* Result is signed two's compliment in * |
;* error_hi--error_lo -radix- * |
;***************************************************************** |
ldi _bemf_lo_byte, 7 - error_mult |
rcall DIVIDE_16_SIMPLE |
.endif ;BACKEMF_SCALE_ENABLED |
COMPUTE_NEW_PWM: |
;***************************************************************** |
;* Add in the original throttle * |
;***************************************************************** |
add error_lo,throttle_set |
clr B_Temp |
adc error_hi,B_Temp |
;***************************************************************** |
;* Clamp to between 0 and +255 * |
;***************************************************************** |
brmi SET_ZERO_PWM ; If result is NEGATIVE, set to zero. |
cpi error_hi,0x00 ; If hi byte is zero, result is ok. |
breq LOWPASS |
ldi error_lo,0xFF ; otherwise, clamp |
rjmp LOWPASS |
SET_ZERO_PWM: |
clr error_lo |
LOWPASS: |
.ifdef LOWPASS_ENABLED |
;***************************************************************** |
;* A transversal low pass filter * |
;* Lowpass on the emf-adjusted pwm * |
;* * |
;* gain input "emf_lowpass_gain", range = 0 to 8 * |
;* * |
;* The actual filter time constant "tau" is equal to * |
;* tau = 2^emf_lowpass_gain * sample_interval * |
;* * |
;* The sample interval is nominally 10mS, so the time * |
;* constant values are: * |
;* 0 1 2 3 4 5 6 7 8 * |
;* 10mS,20mS,40mS,80mS,160mS,320mS,640mS,1.28S,2.56S * |
;* * |
;* The current sample is added to an attenuated sum of previous * |
;* samples as follows: * |
;* * |
;* Adjusted Value = 1/(2^gain) x * |
;* ( 1x sample number (i) * |
;* + gain x sample number (i-1) * |
;* + gain^2 x sample number (i-2) * |
;* + gain^3 x sample number (i-3) * |
;* + .... * |
;* ) * |
;* Where: * |
;* Gain values: gain = (2^emf_lowpass_gain - 1) / 2^n * |
;* 0,1/2,3/4,7/8,15/16 ... 255/256 * |
;* * |
;* Algorithm: * |
;* * |
;* -Input (current sample) in error_lo (error_hi=0) * |
;* 0x00FF max * |
;* * |
;* -Input (scaled sum of previous samples) in * |
;* error_hi_prev--error_lo_prev. * |
;* 0x00FF * (2^emf_lowpass_gain - 1 ) max * |
;* * |
;* 1. The error_hi_prev--error_lo_prev is added to * |
;* error_hi--error_lo * |
;* 0x00FF * (2^emf_lowpass_gain) max * |
;* * |
;* 2. This value is also stored in * |
;* error_hi_prev--error_lo_prev * |
;* * |
;* 3. The value (error_hi--error_lo) is divided by * |
;* 2^emf_lowpass_gain (resulting in lowpass value, * |
;* max 0x00FF) * |
;* * |
;* 4. The value (error_hi--error_lo) is subtracted from * |
;* error_hi_prev--error_lo_prev. This is the new * |
;* stored value. * |
;***************************************************************** |
clr error_hi |
;**** |
;* 1. Add in cumulative previous error |
;**** |
add error_lo,error_lo_prev ; Add in scaled previous samples |
adc error_hi,error_hi_prev ; |
;**** |
;* 2. Store |
;**** |
mov error_lo_prev,error_lo ; Store new value |
mov error_hi_prev,error_hi ; Store new value |
;**** |
;* 3. Divide new value |
;**** |
ldi _bemf_lo_byte,emf_lowpass_gain |
rcall DIVIDE_16_SIMPLE |
;**** |
;* 4. New value in error_prev |
;**** |
ADJUST_STORED: |
sub error_lo_prev,error_lo |
sbc error_hi_prev,error_hi |
.endif ;LOWPASS_FILTER |
mov throttle_set,error_lo |
subi Cycle_count,256-15 ; Normal arrival here occurs after 3.5 + 14.5 + |
; pwm cycles. Add 15 counts here, also 3 added in |
; div16u |
.endif BACKEMF_ENABLED |
/contrib/toolchain/avra/examples/throttle_dev_set.inc |
---|
0,0 → 1,348 |
;throttle_dev_set.inc |
.NOLIST |
; *************************************************************************************** |
; * PWM MODEL RAILROAD THROTTLE * |
; * * |
; * WRITTEN BY: PHILIP DEVRIES * |
; * * |
; * Copyright (C) 2003 Philip DeVries * |
; * * |
; * This program is free software; you can redistribute it and/or modify * |
; * it under the terms of the GNU General Public License as published by * |
; * the Free Software Foundation; either version 2 of the License, or * |
; * (at your option) any later version. * |
; * * |
; * This program is distributed in the hope that it will be useful, * |
; * but WITHOUT ANY WARRANTY; without even the implied warranty of * |
; * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * |
; * GNU General Public License for more details. * |
; * * |
; * You should have received a copy of the GNU General Public License * |
; * along with this program; if not, write to the Free Software * |
; * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA * |
; * * |
; *************************************************************************************** |
;********************************************************* |
;* Hardware Settings * |
;********************************************************* |
; |
; REGISTER ASSGINMENTS |
; Note that registes 16 - 31 are acessed by a larger instruction |
; set than registers 0 - 15. |
; |
;********************************************************* |
; REGISTER ASSIGNMENTS |
; GLOBAL VISIBILITY ;all functions have access to this NAME of the register |
; GLOBAL DURATION ;the register always MEANS the same thing. |
;********************************************************* |
.DEF Flags_1= r16 ; Global. Status flags |
.DEF Cycle_count= r17 ; Global. Count PWM cycles |
.DEF throttle_set= r18 ; Global. Current Throttle Setting |
.ifdef SWITCH_LOWPASS ENABLED |
.DEF Flags_2= r19 ; Global. Switch "status" flags |
.endif SWITCH_LOWPASS_ENABLED |
.ifdef MOMENTUM_ENABLED |
.DEF momentum_set= r4 ; Global. Input control |
.endif ;MOMENTUM_ENABLED |
.ifdef TRADITIONAL_ENABLED |
.ifdef WALKAROUND_ENABLED |
.DEF throttle_hold= r14 ; Global. Previous throttle setting |
.DEF Flags_2= r19 ; Global. Switch "status" flags |
.endif ;WALKAROUND_ENABLED |
.endif ;TRADITIONAL_ENABLED |
;********************************************************* |
; REGISTER ASSIGNMENTS |
; LOCAL VISIBILITY ;only the translation unit has (should have) |
; access to any NAME of the register |
; GLOBAL DURATION ;the register always MEANS the same thing. |
;********************************************************* |
.ifdef MOMENTUM_ENABLED |
.ifdef LOWPASS_ENABLED |
.DEF error_hi_prev= r2 ; Global. History of error |
.DEF error_lo_prev= r3 ; Global. History of error |
.endif ;LOWPASS_ENABLED |
.endif ;MOMENTUM_ENABLED |
.ifdef TRADITIONAL_ENABLED |
.ifdef THROTTLE_LOWPASS_ENABLED |
.DEF throttle_hi_prev= r9 ; Global. History of throttle handle |
.DEF throttle_lo_prev= r10 ; Global. History of throttle handle |
.endif ;THROTTLE_LOWPASS_ENABLED |
.ifdef MOMENTUM_LOWPASS_ENABLED |
.DEF momentum_hi_prev= r11 ; Global. History of momentum handle |
.DEF momentum_lo_prev= r12 ; Global. History of momentum handle |
.endif ;THROTTLE_LOWPASS_ENABLED |
.endif ;TRADITIONAL_ENABLED |
.ifdef MOMENTUM_ENABLED |
.DEF speed_hi_prev= r5 ; Global. Speed at last sample time |
.DEF speed_lo_prev= r6 ; Global. Speed at last sample time |
.endif ;MOMENTUM_ENABLED |
;********************************************************* |
; REGISTER ASSIGNMENTS |
; LOCAL VISIBILITY ;only the translation unit has (should have) |
; access to any NAME of the register |
; LOCAL DURATION ;the register has different meanings in different contexts |
;********************************************************* |
.DEF Implicit= r0 ; Local. Used for implicit lpm |
.DEF Sreg_stack= r1 ; Local. "stack" for SREG during interrupts |
; .DEF ZL= r30 ; Local. Used for Z pointer (low byte) |
; .DEF ZH= r31 ; Local. Used for Z pointer (high byte) |
.MACRO LOWLOCAL1 |
.DEF @0 = r7 ; Local. General Use |
.ENDMACRO |
.MACRO LOWLOCAL2 |
.DEF @0 = r8 ; Local. General Use |
.ENDMACRO |
.MACRO HILOCAL1 |
.DEF @0 = r26 ; Local. General Use |
.ENDMACRO |
.MACRO HILOCAL2 |
.DEF @0 = r27 ; Local. General Use |
.ENDMACRO |
;********************************************************* |
; REGISTER ASSIGNMENTS |
; GLOBAL VISIBILITY ;all functions have access to this NAME of the register |
; LOCAL DURATION ;the register has different meanings in different contexts |
;********************************************************* |
.MACRO B_TEMPLOCAL |
.DEF @0 = r23 ; Local. Second Level Routine Safe |
.ENDMACRO |
.MACRO B_TEMPLOCAL1 |
.DEF @0 = r24 ; Local. Second Level Routine Safe |
.ENDMACRO |
.MACRO B_TEMPLOCAL2 |
.DEF @0 = r25 ; Local. Second Level Routine Safe |
.ENDMACRO |
B_TEMPLOCAL B_Temp ; General use names |
B_TEMPLOCAL1 B_Temp1 |
B_TEMPLOCAL2 b_Temp2 |
;ISR LOCALS |
; UNUSED |
;.DEF Not_used= r29 |
; GLOBALS |
;FLAGS_1 flag data |
;.SET F_Flags_1= 0b11111111 ; All flags |
.SET F_accel= 0b00000001 ; Accelerating if 1, decel if 0 |
.SET BF_accel= 0x00 ; Flag bit location |
.SET F_brake= 0b00000010 ; Brake set if 1 |
.SET BF_brake= 0x01 ; |
.SET F_stop= 0b00000100 |
.SET BF_stop= 0x02 |
.SET F_reverse= 0b00001000 |
.SET BF_reverse= 0x03 |
.SET F_negative_err= 0b00010000 |
.SET BF_negative_err= 0x04 |
.SET F_use_backemf= 0b00100000 |
.SET BF_use_backemf= 0x05 |
;.SET F_= 0b01000000 |
;.SET BF_= 0x06 |
;.SET F_= 0b10000000 |
;.SET BF_= 0x07 |
.ifdef SWITCH_LOWPASS_ENABLED |
;FLAGS_2 flag data - count and status for forward/reverse/brake/stop |
.SET F_Flags_2= 0b00001111 ; All flags |
.SET F_stop_count= 0b00010000 |
.SET BF_stop_count= 0x04 |
.SET F_brake_count= 0b00100000 |
.SET BF_brake_count= 0x05 |
.SET F_reverse_count= 0b01000000 |
.SET BF_reverse_count= 0x06 |
.SET F_foreward_count= 0b10000000 |
.SET BF_foreward_count= 0x07 |
;bits 0-3 the count- from 0-16 |
.endif SWITCH_LOWPASS_ENABLED |
;PORT SETUP STUFF |
.SET emf_port= 0x05 ;PB5 - INPUT -- Back EMF input |
.SET emf_port_bit= 0b00100000 ;PIN1 ADC0 |
.SET momentum_port= 0x04 ;PB4 - INPUT -- Momentum Level input |
.SET momentum_port_bit= 0b00010000 ;PIN2 ADC3 Acceleration-indicator output |
.SET dir_in_port= 0x03 ;PB3 - INPUT -- Direction/Brake |
.SET dir_in_port_bit= 0b00001000 ;PIN3 ADC2 Deceleration-indicator output |
.SET throttle_port= 0x02 ;PB2 - INPUT -- Throttle Handle MAY USE INT0 |
.SET throttle_port_bit= 0b00000100 ;PIN7 ADC1 (Could also use INTO |
; INT0 as DCC input.) |
.SET pwm_port= 0x01 ;PB1 - OUTPUT -- PWM (off L) |
.SET pwm_port_bit= 0b00000010 ;PIN6 NO ADC |
; ONLY PWM PIN. |
.SET dir_out_port= 0x00 ;PB0 - OUTPUT -- '1' = forward |
.SET dir_out_port_bit= 0b00000001 ;PIN5 NO ADC '0' = reverse |
.SET acsr_val= 0b10000000 ; bit 7 --AC0 1 --comparator disabled |
.SET eecr_read_enable= 0b00000001 ; bit 4,5,6,7 --unused |
; bit 3 --EERIE 0 --interrupt disabled |
; bit 2 --EEMWE 0 --master write disabled |
; bit 1 --EEWE 0 --write disabled |
; bit 0 --EERE 1 --read ENABLED |
.SET eecr_mwrite_enable= 0b00000100 ; bit 4,5,6,7 --unused |
; bit 3 --EERIE 0 --interrupt disabled |
; bit 2 --EEMWE 1 --master write ENABLED |
; bit 1 --EEWE 0 --write disabled |
; bit 0 --EERE 0 --read disabled |
.SET eecr_write_enable= 0b00000110 ; bit 4,5,6,7 --unused |
; bit 3 --EERIE 0 --interrupt disabled |
; bit 2 --EEMWE 1 --master write ENABLED |
; bit 1 --EEWE 1 --write ENABLED |
; bit 0 --EERE 0 --read disabled |
.SET admux_emf= 0b00100000 ; bit 4,3 --unused |
; bit 7 --REFS1 0 Two bits: |
; bit 6 --REFS0 0 Select VCC volt reference |
; bit 5 --ADLAR 1 left adjust, 8 bit data in ADCH |
; bit 2 --MUX2 0 Three bits: |
; bit 1 --MUX1 0 |
; bit 0 --MUX0 0 Select ADC0 from PB5 |
.SET admux_throttle= 0b00100001 ; bit 4,3 --unused |
; bit 7 --REFS1 0 Two bits: |
; bit 6 --REFS0 0 Select VCC volt reference |
; bit 5 --ADLAR 1 left adjust, 8 bit data in ADCH |
; bit 2 --MUX2 0 Three bits: |
; bit 1 --MUX1 0 |
; bit 0 --MUX0 1 Select ADC1 from PB2 |
.SET admux_direction= 0b00100010 ; bit 4,3 --unused |
; bit 7 --REFS1 0 Two bits: |
; bit 6 --REFS0 0 Select VCC volt reference |
; bit 5 --ADLAR 1 left adjust, 8 bit data in ADCH |
; bit 2 --MUX2 0 Three bits: |
; bit 1 --MUX1 1 |
; bit 0 --MUX0 0 Select ADC2 from PB3 |
.SET admux_momentum= 0b00100011 ; bit 4,3 --unused |
; bit 7 --REFS1 0 Two bits: |
; bit 6 --REFS0 0 Select VCC volt reference |
; bit 5 --ADLAR 1 left adjust, 8 bit data in ADCH |
; bit 2 --MUX2 0 Three bits: |
; bit 1 --MUX1 1 |
; bit 0 --MUX0 1 Select ADC3 from PB4 |
.SET admux_off= 0b00000000 ; bit 4,3 --unused |
; bit 7 --REFS1 0 Two bits: |
; bit 6 --REFS0 0 Select VCC volt reference |
; bit 5 --ADLAR 0 right adjust |
; bit 2 --MUX2 0 Three bits: |
; bit 1 --MUX1 0 |
; bit 0 --MUX0 0 Select ADC0 from PB5 |
.SET adcsr_off= 0b00010011 ; bit 7 --ADCEN 0 ADC enable disable |
; bit 6 --ADSC 0 Start conversion no |
; bit 5 --ADFR 0 Free running mode disable |
; bit 4 --ADIF 1 Interrupt flag clear |
; bit 3 --ADIE 0 Interrupt enable disabled |
; bit 2 --ADPS2 0 Three bits: |
; bit 1 --ADPS1 1 |
; bit 0 --ADPS0 1 Prescaler div 8 (200kHz) |
.SET adcsr_enable= 0b11110011 ; bit 7 --ADCEN 1 ADC enable ENABLED |
; bit 6 --ADSC 1 Start conversion yes |
; bit 5 --ADFR 1 Free running mode ENABLED |
; bit 4 --ADIF 1 Interrupt flag clear |
; bit 3 --ADIE 0 Interrupt enable disabled |
; bit 2 --ADPS2 0 Three bits: |
; bit 1 --ADPS1 1 |
; bit 0 --ADPS0 1 Prescaler div 8 (200kHz) |
.SET mcucr_power_down_mode= 0b00110000 |
; bit 7 --unused |
; bit 6 --PUD 0 pullups ENABLED |
; bit 5 --SE 1 sleep ENABLED |
; bit 4 --SM1 1 Two bits: |
; bit 3 --SM0 0 Sleep in power down mode |
; bit 2 --unused |
; bit 1 --ISC01 0 Two bits: |
; bit 0 --ISC00 0 INTO interrupt on logic |
; low input |
.SET wdtcr_off_enable= 0b00011000 ; enable watchdog turn off |
.SET wdtcr_off= 0b00010000 ; watchdog turn off |
.SET gimsk_val_off= 0b00000000 ; bit 7,4,3,2,1,0 --unused |
; bit 6 --INTO 0 INTO interrupt disabled |
; bit 5 --PCIE 0 pin change interrupt disabled |
.SET gimsk_val_pcie= 0b00100000 ; bit 7,4,3,2,1,0 --unused |
; bit 6 --INTO 0 INTO interrupt disabled |
; bit 5 --PCIE 1 pin change interrupt ENABLED |
.SET gifr_clear= 0b01100000 ; bit 7,4,3,2,1,0 --unused |
; bit 6 --INTF0 1 INTO interrupt flag cleared |
; bit 5 --PCIF 1 pin ch. interrupt flag cleared |
.SET timsk_val_off= 0b00000000 ; bit 7,5,4,3,0 --unused |
; bit 6 --OCIE1A 0 TC1 compare interrupt disabled |
; bit 2 --TOIE1 0 TC1 overflow interrupt disabled |
; bit 1 --TOIE0 0 TC0 overflow interrupt disabled |
.SET timsk_enable_t1= 0b01000000 ; bit 7,5,4,3,0 --unused |
; bit 6 --OCIE1A 0 TC1 compare interrupt disabled |
; bit 2 --TOIE1 0 TC1 overflow interrupt disabled |
; bit 1 --TOIE0 0 TC0 overflow interrupt disabled |
.SET tifr_clear_tov0= 0b00000010 ; bit 7,5,4,3,0 --unused |
; bit 6 --OCF1A 0 OCF1A flag not cleared |
; bit 2 --TOV1 0 TOV1 flag not cleared |
; bit 1 --TOV0 1 TOV0 flag CLEARED |
.SET tccr1_enable_t1= 0b01100011 |
; bit 7 --CTC1 0 Clear on compare match no |
; bit 6 --PWM1 1 PWM mode ENABLED |
; bit 5 --COM1A1 1 Two bits: |
; bit 4 --COM1A0 0 Clear output on OCR1A match |
; Set output when TCNT1 = 0 |
; bit 3 --CS13 0 Four bits: |
; bit 2 --CS12 0 |
; bit 3 --CS11 1 |
; bit 4 --CS10 1 CK*4: 156.25nS |
; 256cnt = 25kHz |
.LIST |
/contrib/toolchain/avra/examples/throttle_divide.asm |
---|
0,0 → 1,135 |
;throttle_divide.asm |
; |
;******************************************************************************** |
;* div16u * |
;* Second Level Subroutine * |
;* * |
;* Program from Atmel file avr200.asm * |
;* * |
;* Since the 25kHz pwm cycle is 64 clock cycles long, this subroutine * |
;* requires 3.67 to 3.92 25kHz clock cycles. * |
;* * |
;* A single line was added which adds 3 to Cycle_count * |
;* * |
;* Inputs: HILOCAL2:HILOCAL1 and B_TEMPLOCAL1:B_TEMPLOCAL * |
;* Returns: HILOCAL2:HILOCAL1 = HILOCAL2:HILOCAL1 / B_TEMPLOCAL1:B_TEMPLOCAL * |
;* LOLOCAL2:LOLOCAL1 = remainder * |
;* Changed: B_TEMPLOCAL2 * |
;* * |
;* Calls: Not allowed * |
;******************************************************************************** |
B_TEMPLOCAL2 dcnt16u ; Local counter |
HILOCAL1 dd16uL ; 16 bit Innput |
HILOCAL2 dd16uH |
B_TEMPLOCAL dv16uL ; 16 bit Input |
B_TEMPLOCAL1 dv16uH |
HILOCAL1 dres16uL ; 16 bit Output |
HILOCAL2 dres16uH |
LOWLOCAL1 drem16uL ; 16 bit Remainder |
LOWLOCAL2 drem16uH ; |
;<ATMEL ROUTINE> |
;*************************************************************************** |
;* |
;* "div16u" - 16/16 Bit Unsigned Division |
;* |
;* This subroutine divides the two 16-bit numbers |
;* "dd16uH:dd16uL" (dividend) and "dv16uH:dv16uL" (divisor). |
;* The result is placed in "dres16uH:dres16uL" and the remainder in |
;* "drem16uH:drem16uL". |
;* |
;* Number of words :19 |
;* Number of cycles :235/251 (Min/Max) |
;* Low registers used :2 (drem16uL,drem16uH) |
;* High registers used :5 (dres16uL/dd16uL,dres16uH/dd16uH,dv16uL,dv16uH, |
;* dcnt16u) |
;* |
;*************************************************************************** |
;***** Subroutine Register Variables |
;.def drem16uL= r14 ; Reassigned |
;.def drem16uH= r15 |
;.def dres16uL= r16 |
;.def dres16uH= r17 |
;.def dd16uL= r16 |
;.def dd16uH= r17 |
;.def dv16uL= r18 |
;.def dv16uH= r19 |
;.def dcnt16u= r20 |
;***** Code |
div16u: |
clr drem16uL ; clear remainder Low byte |
sub drem16uH,drem16uH ; clear remainder High byte and carry |
ldi dcnt16u,17 ; init loop counter |
d16u_1: |
rol dd16uL ; shift left dividend |
rol dd16uH |
dec dcnt16u ; decrement counter |
brne d16u_2 ; if done |
subi Cycle_count,256-3 ; Add 3 to Cycle_count |
ret ; return |
d16u_2: |
rol drem16uL ; shift dividend into remainder |
rol drem16uH |
sub drem16uL,dv16uL ; remainder = remainder - divisor |
sbc drem16uH,dv16uH ; |
brcc d16u_3 ; |
add drem16uL,dv16uL ; if result negative |
adc drem16uH,dv16uH ; restore remainder |
clc ; clear carry to be shifted into result |
rjmp d16u_1 ; |
d16u_3: ; if result NOT negative |
sec ; set carry to be shifted into result |
rjmp d16u_1 |
;<END ATMEL ROUTINE> |
;******************************************************************************** |
;* DIVIDE_16_SIMPLE * |
;* Second Level Subroutine * |
;* * |
;* Inputs: dd16uH:dd16ul and dv16uL * |
;* Returns: dres16uH:dres16uL = dd8uH:dd8uL / 2^dv16uL * |
;* * |
;* Changed: nothing else * |
;* N.B that dd16uH, dd16uL, dv16uH and dv16uL are aliases for: * |
;* dd16uH=error_hi * |
;* dd16uL=error_lo * |
;* dv16uH=B_TempX * |
;* dv16uL=B_TempX * |
;* dcnt16u=B_TempX * |
;* Calls: Not allowed * |
;******************************************************************************** |
DIVIDE_16_SIMPLE: |
inc dv16uL |
DIVIDE_16_SIMPLE_LOOP: |
dec dv16uL ; decrement counter |
brne DIVIDE_BY_2 |
ret |
DIVIDE_BY_2: |
asr dd16uH ; divide by two |
ror dd16uL |
rjmp DIVIDE_16_SIMPLE_LOOP |
/contrib/toolchain/avra/examples/throttle_momentum.asm |
---|
0,0 → 1,314 |
;throttle_momentum.asm |
.NOLIST |
; *************************************************************************************** |
; * PWM MODEL RAILROAD THROTTLE * |
; * * |
; * WRITTEN BY: PHILIP DEVRIES * |
; * * |
; * Copyright (C) 2003 Philip DeVries * |
; * * |
; * This program is free software; you can redistribute it and/or modify * |
; * it under the terms of the GNU General Public License as published by * |
; * the Free Software Foundation; either version 2 of the License, or * |
; * (at your option) any later version. * |
; * * |
; * This program is distributed in the hope that it will be useful, * |
; * but WITHOUT ANY WARRANTY; without even the implied warranty of * |
; * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * |
; * GNU General Public License for more details. * |
; * * |
; * You should have received a copy of the GNU General Public License * |
; * along with this program; if not, write to the Free Software * |
; * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA * |
; * * |
; ***************************************************************************************: |
.LIST |
.ifdef MOMENTUM_ENABLED |
;******************************************************************************** |
;* MOMENTUM_ADJUST * |
;* Top level routine * |
;* * |
;* Momentum simulates the mass of the train. Since model trains have little * |
;* mass, the locomotive speed can directly follow the throttle setting; in * |
;* other words, a model train can accelerate and decelerate instantly. * |
;* Real trains are very massive, and therefore they do not accelerate or * |
;* decelerate quickly. * |
;* * |
;* According to Newtons law, the acceleration is proportional to the force, * |
;* and inversely proportional to the mass. Therefore, the more massive the * |
;* train, the more slowly the train will accelerate or decelerate. Also, the * |
;* more force the locomotive can provide, the faster the train will accelerate. * |
;* Deceler depends on the braking capability of the overall train. * |
;* * |
;* If force were constant, Newtons law states that acceleration would be * |
;* constant too. This subroutine assumes that somewhat more force is * |
;* available at low speeds than at high speeds, so that acceleration will be * |
;* greater at low speeds. The subroutine also assumes that opposing forces * |
;* (friction, wind resistance, etc) are stronger at higher speeds. This * |
;* assumption also means that acceleration will be greater at low speeds. * |
;* * |
;* This subroutine calculates acceleration/deceleration by this simple * |
;* Method: * |
;* * |
;* The rate of speed change (accleration and deceleration) depends on the * |
;* current speed as * |
;* {Speed_Max (0xFF) - Current_Speed} / {Tau*Rate} * |
;* * |
;* Where T = index of sample time * |
;* t = real time * |
;* Tau = time constant * |
;* Rate = Update rate (nominally 100Hz) * |
;* * |
;* That is, the acceleration/deceleration is maximum at zero speed, and * |
;* approaches zero at maximum speed. * |
;* * |
;* When accelerating, the speed at the next sample period is * |
;* Speed(T) = Speed(T-1) + {0xFF - Speed(T-1)} / {Tau*Rate} * |
;* * |
;* Giving an acceleration curve that looks like a normal exponential. * |
;* Speed(t) = 0xFF { 1 - exp( - t / Tau) } * |
;* * |
;* * * * |
;* * * |
;* * * |
;* * * |
;* * * |
;* * * |
;* * * |
;* * * |
;* * |
;* * |
;* When decelerating, the change rate equation is the same, but the change * |
;* is subtracted, as * |
;* Speed(T) = Speed(T) - {0xFF - Speed(T-1)} / {Tau*Rate} * |
;* * |
;* Giving a deceleration curve that looks like * |
;* Speed(t) = 0xFF { 1 - exp( -(T1 - t) / Tau) } * |
;* which is a mirror image of the acceleration, NOT a normal exponential. * |
;* * |
;* * * * |
;* * * |
;* * * |
;* * * |
;* * * |
;* * * |
;* * * |
;* * |
;* * |
;* In each case, the acceleration or deceleration is "clipped" at the current * |
;* throttle setting so that the speed doesn't overshoot or undershoot. * |
;* * |
;* Three different values of Tau are used, that is * |
;* Tau_accel Corresponding to acceleration under power * |
;* Tau_coast Corresponding to deceleration when coasting * |
;* Tau_brake Corresponding to deceleration when braking * |
;* * |
;* To permit finer control of momentum, the throttle setting is converted to a * |
;* 16 bit number, where the 8 msb's correspond to the throttle setting from * |
;* the throttle handle and sent forward. * |
;* * |
;* Inputs: throttle_set Throttle handle position ( 0x00 to 0xFF ) * |
;* speed_hi_prev Hi byte of (T-1) throttle setting (stored) * |
;* speed_lo_prev Lo byte of (T-1) throttle setting (stored) * |
;* Returns: throttle_set Adjusted throttle setting (T) * |
;* speed_hi_prev Hi byte of (T) throttle setting (stored) * |
;* speed_lo_prev Lo byte of (T) throttle setting (stored) * |
;* Changed: B_Temp * |
;* B_Temp1 * |
;* B_Temp2 * |
;* B_Temp3 * |
;* Calls: NONE * |
;* Goto: MOMENTUM_ADJUST_RETURN * |
;******************************************************************************** |
B_TEMPLOCAL2 _time_constant_adj |
.ifdef TRADITIONAL_ENABLED |
.ifdef LEDS_ENABLED |
sbrc Flags_1,BF_brake ; If the brake flag is set, |
sbi PORTB,dir_in_port ; Port Output: Indicate deceleration |
.endif ;LEDS_ENABLED |
.endif ;TRADITIONAL_ENABLED |
;******************************************************************* |
;* Adjust the value of "momentum_set". |
;* This adjustment makes it easier to fine adjust low momentum settings |
;* while still permitting large momentum settings. |
;* |
;* The ammount of momentum to apply comes in in "momentum_set" |
;* which is read in READ_THROTTLE. The nominal range is |
;* 0x00 to 0x40. This value is multiplied by two and squared, |
;* giving a new range from 0x00 to 0x4000. The update rate is 100Hz, |
;* and so the new range corresponds to a time constant from |
;* 0(decimal) to 164(decimal) seconds. Since the adjustment was |
;* done by performing a square, the adjusted value is non-linear |
;* with the input value. |
;******************************************************************* |
lsl momentum_set ; multiply by two |
HILOCAL1 _mset_multiplier ; supply to mpy8u |
B_TEMPLOCAL _mset_multiplicand ; supply to mpy8u |
mov _mset_multiplier,momentum_set ; |
mov _mset_multiplicand,momentum_set ; |
rcall mpy8u ; square |
B_TEMPLOCAL1 _mset_hi_byte ; return from mpy8u |
B_TEMPLOCAL _mset_lo_byte ; return from mpy8u |
;******************************************************************* |
;* Compute the difference between the maximum throttle and |
;* the current throttle |
;******************************************************************* |
HILOCAL2 _mset_diff_hi_byte |
HILOCAL1 _mset_diff_lo_byte |
ldi _mset_diff_hi_byte,0xFF ; Maximum possible speed |
ldi _mset_diff_lo_byte,0xFF ; |
sub _mset_diff_lo_byte,speed_lo_prev ; Difference between max speed |
sbc _mset_diff_hi_byte,speed_hi_prev ; and current speed |
;******************************************************************* |
;* Determine whether to accelerate, decelerate, or remain unchanged. |
;* Compare the throttle handle setting with the actual speed |
;******************************************************************* |
cp throttle_set,speed_hi_prev ; Test if throttle position is larger |
; or smaller than the speed. |
breq EVEN_SPEED ; If the throttle position is the same |
; as the speed. |
brlo SETUP_DECELERATE ; If the throttle position is smaller |
; than the speed, then need to decelerate. |
; brsh SETUP_ACCELERATE ; If the throttle position is larger |
; than the speed, then need to accelerate. |
SETUP_ACCELERATE: |
.ifdef TRADITIONAL_ENABLED |
.ifdef LEDS_ENABLED |
cpi throttle_set,accel_led_threshold ; If the throttle is less than minimum |
brlo END_SET_ACCEL_LED ; don't light led |
mov B_Temp2,throttle_set ; If the throttle is closer than led_threshold |
subi B_Temp2,accel_led_threshold ; don't light led |
cp B_Temp2,speed_hi_prev |
brlo END_SET_ACCEL_LED |
sbi PORTB,momentum_port ; Port Output: Indicate acceleration |
END_SET_ACCEL_LED: |
.endif LEDS_ENABLED |
.endif TRADITIONAL_ENABLED |
sbr Flags_1,F_accel ; Set accelerating flag |
; Indicate acceleration |
ldi _time_constant_adj,accel_offset+1 ; Acceleration time constant adjust |
rjmp CHECK_BRAKE |
EVEN_SPEED: ; Arrive here if throttle_set=current speed |
sbrc Flags_1,BF_brake ; If the brake flag is set, decelerate |
rjmp CHECK_BRAKE ; |
rjmp DONE_WITH_MOMENTUM ; Otherwise adjustment is necessary |
SETUP_DECELERATE: |
cbr Flags_1,F_accel ; Clear accelerating flag |
.ifdef TRADITIONAL_ENABLED |
.ifdef LEDS_ENABLED |
cpi throttle_set,0xff-decel_led_threshold ; If the throttle is more than maximum |
brsh END_SET_DECEL_LED ; don't light led |
mov B_Temp2,throttle_set |
subi B_Temp2,0x00-decel_led_threshold ; If the throttle is closer than the led |
cp B_Temp2,speed_hi_prev ; threshold, don't light the led |
brsh END_SET_DECEL_LED |
sbi PORTB,dir_in_port ; Port Output: Indicate deceleration |
END_SET_DECEL_LED: |
.endif LEDS_ENABLED |
.endif TRADITIONAL_ENABLED |
ldi _time_constant_adj,0+1 ; Coasting deceleration time const. adjust. |
; rjmp CHECK_BRAKE |
CHECK_BRAKE: ; Always check for the brake. |
sbrs Flags_1,BF_brake ; If brake flag is not set, |
rjmp ADJUST_TAU ; proceed. |
; Brake overrides acceleration |
; or coasting. |
cbr Flags_1,F_accel ; clear accelerating flag |
; Indicate deceleration |
ldi _time_constant_adj,brake_offset+1 ; Braking deceleration time const. adjust. |
; rjmp ADJUST_TAU |
ADJUST_TAU: |
;B_TEMP2=B_TEMPLOCAL2 |
dec _time_constant_adj ; Divide tau_base by 2^_time_constant_adj |
breq DIVIDE_TAU ; to produce adjusted tau. |
lsr _mset_hi_byte |
ror _mset_lo_byte |
rjmp ADJUST_TAU |
DIVIDE_TAU: |
sbr _mset_lo_byte,0b00000001 ; Force last bit 1. Prevent divide by zero. |
rcall div16u ; Divide _mset_diff_hi_byte:_mset_diff_lo_byte |
; (difference) |
; by _mset_hi_byte:_mset_lo_byte (dividor) |
sbrs Flags_1,BF_accel ; add or subtract change depending |
rjmp SUBTRACT_CHANGE ; on F_accel flag |
;rjmp ADD_CHANGE |
ADD_CHANGE: ; Case accelerating |
; HILOCAL2 _mset_diff_hi_byte |
; HILOCAL1 _mset_diff_lo_byte |
add speed_lo_prev,_mset_diff_lo_byte ; Add in the change |
adc speed_hi_prev,_mset_diff_hi_byte |
cp throttle_set,speed_hi_prev ; If larger than the throttle_set value |
brlo USE_SET_SPEED ; clamp at throttle_set value |
rjmp DONE_WITH_MOMENTUM |
SUBTRACT_CHANGE: ; Case decelerating |
sbrc Flags_1,BF_brake ; If the brake flag is set, |
clr throttle_set ; decelerate all the way to zero |
sub speed_lo_prev,_mset_diff_lo_byte ; Subtract the change |
sbc speed_hi_prev,_mset_diff_hi_byte ; |
brlo USE_SET_SPEED ; If less than zero |
; clamp at throttle_set value |
cp speed_hi_prev,throttle_set ; If less than the throttle_set value |
brlo USE_SET_SPEED ; clamp at throttle_set value |
rjmp DONE_WITH_MOMENTUM |
USE_SET_SPEED: ; Use the throttle_set value directly |
mov speed_hi_prev,throttle_set |
clr speed_lo_prev |
DONE_WITH_MOMENTUM: |
mov throttle_set,speed_hi_prev ; Put the new value into throttle_set. |
.endif ;MOMENTUM_ENABLED |
/contrib/toolchain/avra/examples/throttle_momentum_lowpass.asm |
---|
0,0 → 1,69 |
;throttle_momentum_lowpass.asm |
.NOLIST |
; *************************************************************************************** |
; * PWM MODEL RAILROAD THROTTLE * |
; * * |
; * WRITTEN BY: PHILIP DEVRIES * |
; * * |
; * Copyright (C) 2003 Philip DeVries * |
; * * |
; * This program is free software; you can redistribute it and/or modify * |
; * it under the terms of the GNU General Public License as published by * |
; * the Free Software Foundation; either version 2 of the License, or * |
; * (at your option) any later version. * |
; * * |
; * This program is distributed in the hope that it will be useful, * |
; * but WITHOUT ANY WARRANTY; without even the implied warranty of * |
; * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * |
; * GNU General Public License for more details. * |
; * * |
; * You should have received a copy of the GNU General Public License * |
; * along with this program; if not, write to the Free Software * |
; * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA * |
; * * |
; *************************************************************************************** |
.LIST |
.ifdef MOMENTUM_LOWPASS_ENABLED |
;***************************************************************** |
;* A transversal low pass filter * |
;* * |
;* This is copied from throttle_backemf.asm. * |
;* See the documentation there. * |
;***************************************************************** |
HILOCAL1 _momentum_lo ; assign local variables |
HILOCAL2 _momentum_hi |
mov _momentum_lo,momentum_set |
clr _momentum_hi |
;**** |
;* 1. Add in cumulative previous throttle |
;**** |
add _momentum_lo,momentum_lo_prev ; Add in scaled previous samples |
adc _momentum_hi,momentum_hi_prev ; |
;**** |
;* 2. |
;**** |
mov momentum_lo_prev,_momentum_lo ; Store new value |
mov momentum_hi_prev,_momentum_hi ; Store new value |
;**** |
;* 3. |
;**** |
B_TEMPLOCAL _lowpass_lo_byte |
ldi _lowpass_lo_byte, momentum_lowpass_gain |
rcall DIVIDE_16_SIMPLE |
;**** |
;* 4. |
;**** |
sub momentum_lo_prev,_momentum_lo |
sbc momentum_hi_prev,_momentum_hi |
mov momentum_set,_momentum_lo |
.endif ;MOMENTUM_LOWPASS_ENABLED |
/contrib/toolchain/avra/examples/throttle_multiply.asm |
---|
0,0 → 1,74 |
;throttle_multiply.asm |
; |
;******************************************************************************** |
;* mpy8u * |
;* Second Level Subroutine * |
;* * |
;* Program from Atmel file avr200.asm * |
;* * |
;* Since the 25kHz pwm cycle is 64 clock cycles long, this subroutine * |
;* requires just under 1 25kHz clock cycles. * |
;* * |
;* A single line was added which adds 3 to Cycle_count * |
;* * |
;* Inputs: HILOCAL1 and B_TEMPLOCAL * |
;* * |
;* Returns: HILOCAL1 x B_TEMPLOCAL = B_TEMPLOCAL1:B_TEMPLOCAL * |
;* * |
;* Changed: B_TEMPLOCAL2 * |
;* * |
;* Calls: Not allowed * |
;******************************************************************************** |
HILOCAL1 mc8u ; multiplicand |
B_TEMPLOCAL mp8u ; multiplier |
B_TEMPLOCAL m8uL ; result Low byte |
B_TEMPLOCAL1 m8uH ; result High byte |
B_TEMPLOCAL2 mcnt8u ; loop counter |
;<ATMEL ROUTINE> |
;*************************************************************************** |
;* |
;* "mpy8u" - 8x8 Bit Unsigned Multiplication |
;* |
;* This subroutine multiplies the two register variables mp8u and mc8u. |
;* The result is placed in registers m8uH, m8uL |
;* |
;* Number of words :9 + return |
;* Number of cycles :58 + return |
;* Low registers used :None |
;* High registers used :4 (mp8u,mc8u/m8uL,m8uH,mcnt8u) |
;* |
;* Note: Result Low byte and the multiplier share the same register. |
;* This causes the multiplier to be overwritten by the result. |
;* |
;*************************************************************************** |
;***** Subroutine Register Variables |
;.def mc8u =r16 ;multiplicand |
;.def mp8u =r17 ;multiplier |
;.def m8uL =r17 ;result Low byte |
;.def m8uH =r18 ;result High byte |
;.def mcnt8u =r19 ;loop counter |
;***** Code |
mpy8u: |
clr m8uH ;clear result High byte |
ldi mcnt8u,8 ;init loop counter |
lsr mp8u ;rotate multiplier |
m8u_1: |
brcc m8u_2 ;carry set |
add m8uH,mc8u ;add multiplicand to result High byte |
m8u_2: |
ror m8uH ;rotate right result High byte |
ror m8uL ;rotate right result L byte and multiplier |
dec mcnt8u ;decrement loop counter |
brne m8u_1 ;if not done, loop more |
ret |
;<END ATMEL ROUTINE> |
/contrib/toolchain/avra/examples/throttle_op_set.inc |
---|
0,0 → 1,227 |
;throttle_op_set.inc |
.NOLIST |
; *************************************************************************************** |
; * PWM MODEL RAILROAD THROTTLE * |
; * * |
; * WRITTEN BY: PHILIP DEVRIES * |
; * * |
; * Copyright (C) 2003 Philip DeVries * |
; * * |
; * This program is free software; you can redistribute it and/or modify * |
; * it under the terms of the GNU General Public License as published by * |
; * the Free Software Foundation; either version 2 of the License, or * |
; * (at your option) any later version. * |
; * * |
; * This program is distributed in the hope that it will be useful, * |
; * but WITHOUT ANY WARRANTY; without even the implied warranty of * |
; * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * |
; * GNU General Public License for more details. * |
; * * |
; * You should have received a copy of the GNU General Public License * |
; * along with this program; if not, write to the Free Software * |
; * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA * |
; * * |
; *************************************************************************************** |
;********************************************************* |
;* Operation Settings * |
;********************************************************* |
;********************************************************* |
;* Compile time options |
;********************************************************* |
.define TRADITIONAL_ENABLED ; A traditional throttle. NOT |
; a dcc decoder |
.define WALKAROUND_ENABLED ; Removable, walkaround throttle |
; (Does nothing unless the |
; TRADITIONAL_ENABLED is also defined) |
.define THROTTLE_LOWPASS_ENABLED ; Lowpass filter on throttle handle |
; (Does nothing unless the |
; TRADITIONAL_ENABLED is also defined) |
.define MOMENTUM_LOWPASS_ENABLED ; Lowpass filter on momentum handle |
; (Does nothing unless the |
; TRADITIONAL_ENABLED and |
; MOMENTUM_ENABLED are defined) |
.define SWITCH_LOWPASS_ENABLED ; Lowpass filter on direction switches |
.define LEDS_ENABLED ; Acceleration/Deceleration indicators |
; (Does nothing unless the |
; TRADITIONAL_ENABLED is also defined) |
.define LOCO_LIGHT_ENABLED ; Keep pwm on at low level so light |
; remains on. |
; (Does nothing unless the |
; TRADITIONAL_ENABLED is also defined) |
.define BACKEMF_ENABLED ; If enabled, speed is compensated |
; according to motor back emf |
.define BACKEMF_SCALE_ENABLED ; If enabled, the speed compensation |
; is reduced as the throttle setting |
; is increased. |
; (Does nothing unless the |
; BACKEMF_ENABLED is also defined) |
.define LOWPASS_ENABLED ; Provide a lowpass filter on the |
; the back-emf error amplifier |
; (Does nothing unless the |
; BACKEMF_ENABLED is also defined) |
.define OVERLOAD_ENABLED ; Enable overload protection |
.define PULSE_ENABLED ; Pulse power at low throttle |
;.define PULSE_AMPLITUDE_SCALE ; Increase pulse size at lowest throttle |
; (Does nothing unless the |
; PULSE_ENABLED is also defined) |
.define PULSE_WIDTH_SCALE ; Increase pulse width at higher throttle |
; (Does nothing unless the |
; PULSE_ENABLED is also defined) |
.define MOMENTUM_ENABLED ; Simulate momentum |
.define DIRECTION_ENABLED ; Direction/brake/STOP input |
;********************************************************* |
;********************************************************* |
;* Variables for all compilations |
;********************************************************* |
;******************* |
;* High frequency pwm settings |
;******************* |
.SET pwm_period= 0xFF ; The pwm clock ticks at 156.25nS per tick |
; The pwm runs at pwm_period * 156.25nS |
; The pwm frequency is 1/ (156.25nS * pwm_period) |
; Maximum is 255 (0xFF) |
.SET pwm_max= 0xFF ; Maximum pwm "duty cycle" is equal to |
; pwm_max / pwm_period |
.SET pwm_min= 0x08 ; Minimum PWM "duty cycle" is equal to |
; pwm_min / pwm_period |
;******************* |
;* Sample rate for throttle/ backemf/ pulses, etc |
;******************* |
.SET pwm_settle_count= 16 ; settling time for analog measurements |
; (x 40uS) |
.SET pwm_full_count= 250 ; time (x 40uS) between recalculations |
; (255 max) |
;********************************************************* |
;* Variables associated with backemf speed control |
;********************************************************* |
.ifdef BACKEMF_ENABLED |
;******************* |
;* General settings |
;******************* |
.SET error_mult= 2 ; Error Multiplier. The error between |
; the throttle_set and back_emf is |
; multiplied by 2^error_mult |
; limit -8 < n < 7 |
; 1/256 to 128 |
.ifdef BACKEMF_SCALE_ENABLED |
.SET err_scale= 5 ; Maximum error gain is as set by error_mult. |
; Error gain decreases exponentially toward |
; zero. When the throttle is set at 2^err_scale |
; the error be reduced by 2 |
; Err scale must not be less than 0. |
; The sum of err_scale and err_mult MUST NOT |
; exceed 7. |
.endif ;BACKEMF_SCALE_ENABLED |
.ifdef LOWPASS_ENABLED |
.SET emf_lowpass_gain= 2 ; tau is about 2^emf_lowpass_gain / 100 |
; emf_lowpass_gain 0 to 8 (7?) |
.endif ;LOWPASS_ENABLED |
.endif ;BACKEMF_ENABLED |
;********************************************************* |
;* Variables associated with lowspeed pulses |
;********************************************************* |
.ifdef PULSE_ENABLED |
.SET pwm_min= 0x00 ; override previous setting |
.SET pulse_slope_up= 0x0C |
.SET pulse_slope_down= 0x08 |
.SET pulse_width_min= 0x08 ; minimum 0x01 |
.endif ; PULSE_ENABLED |
;********************************************************* |
;* Variables associated with momentum |
;********************************************************* |
.ifdef MOMENTUM_ENABLED |
; MAY NOT BE MORE THAN 7 |
.SET accel_offset=1 ; divide tau_base by 2^accel_offset to give |
; acceleration time constant |
.SET brake_offset=2 ; divide tau_base by 2^brake_offset to give |
; brake time constant |
.endif MOMENTUM_ENABLED |
;********************************************************* |
;* Variables associated with direction |
;********************************************************* |
.ifdef DIRECTION_ENABLED |
.SET direction_threshold= 16 ; direction relay will switch as long as |
; the throttle (handle and momentum) are |
; less than this value |
.endif ;DIRECTION_ENABLED |
;********************************************************* |
;* Variables associated with traditional throttle |
;********************************************************* |
.ifdef TRADITIONAL_ENABLED |
.ifdef SWITCH_LOWPASS_ENABLED |
.SET stop_count_max= 10 ; number of identical samples to indicate |
.SET brake_count_max= 10 ; number of identical samples to indicate |
.SET reverse_count_max= 10 ; number of identical samples to indicate |
.SET foreward_count_max= 10 ; number of identical samples to indicate |
.endif ;SWITCH_LOWPASS_ENABLED |
.ifdef THROTTLE_LOWPASS_ENABLED |
.SET throttle_lowpass_gain= 5 ; tau is about 2^throttle_lowpass_gain / 100 |
; throttle_lowpass_gain range 0 to 8 (7?) |
.endif ;THROTTLE_LOWPASS_ENABLED |
.ifdef MOMENTUM_LOWPASS_ENABLED |
.SET momentum_lowpass_gain= 7 ; tau is about 2^momentum_lowpass_gain / 100 |
; momentum_lowpass_gain range 0 to 8 (7?) |
.endif ;MOMENTUM_LOWPASS_ENABLED |
.ifdef LEDS_ENABLED |
.SET accel_led_threshold=2 ; dont light led when acceleration/deceleration |
; is closer than this to the actual speed |
.SET decel_led_threshold=2 ; dont light led when acceleration/deceleration |
; is closer than this to the actual speed |
.endif;LEDS_ENABLED |
.ifdef LOCO_LIGHT_ENABLED |
.SET light_pwm= 6 ; run this pwm "duty cycle when throttle is off |
.endif ;LOCO_LIGHT_ENABLED ; to keep loco light on |
.endif ;TRADITIONAL_ENABLED |
.LIST |
/contrib/toolchain/avra/examples/throttle_pulse.asm |
---|
0,0 → 1,140 |
;throttle_pulse.asm |
.NOLIST |
; *************************************************************************************** |
; * PWM MODEL RAILROAD THROTTLE * |
; * * |
; * WRITTEN BY: PHILIP DEVRIES * |
; * * |
; * Copyright (C) 2003 Philip DeVries * |
; * * |
; * This program is free software; you can redistribute it and/or modify * |
; * it under the terms of the GNU General Public License as published by * |
; * the Free Software Foundation; either version 2 of the License, or * |
; * (at your option) any later version. * |
; * * |
; * This program is distributed in the hope that it will be useful, * |
; * but WITHOUT ANY WARRANTY; without even the implied warranty of * |
; * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * |
; * GNU General Public License for more details. * |
; * * |
; * You should have received a copy of the GNU General Public License * |
; * along with this program; if not, write to the Free Software * |
; * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA * |
; * * |
; *************************************************************************************** |
.LIST |
.ifdef PULSE_ENABLED |
;******************************************************************************** |
;* PULSE_GENERATE * |
;* Top level routine * |
;* * |
;* Inputs: throttle_set * |
;* Returns: none * |
;* Changed: B_Temp,ramp_target,ramp_target1 * |
;* Calls: SET_PWM_DUTY * |
;* COUNT_PWM_CYCLES * |
;* Goto: none * |
;******************************************************************************** |
HILOCAL1 ramp_target |
HILOCAL2 ramp_target1 |
;***************************************************************** |
;* If throttle_set is less than 128 (0x80) |
;* Ramp up from wherever the pwm is up to (255 - throttle) |
;* If throttle_set is greater than 127 0x7F) |
;* Ramp up to throttle_set |
;***************************************************************** |
mov ramp_target1,throttle_set |
sbrs ramp_target1,7 |
.ifdef PULSE_AMPLITUDE_SCALE |
com ramp_target1 ; Ramp up to this value |
.else |
ldi ramp_target1,0x80 |
.endif |
mov ramp_target,ramp_target1 |
subi ramp_target,pulse_slope_up ; Ramp up value - pulse_slope |
WAIT_FOR_PWM_1: ; Wait for PWM to reset to 0 |
in B_Temp,TIFR |
sbrs B_Temp,OCF1A |
rjmp WAIT_FOR_PWM_1 |
ldi B_Temp,0b01000000 |
out TIFR,B_Temp |
inc Cycle_count |
in B_Temp,OCR1A ; Find PWM value |
cp B_Temp,ramp_target ; Make sure won't go past max. |
brsh DONE_SLOPING_UP |
subi B_Temp, 0x100-pulse_slope_up ; OCR1A + pulse_slope_up |
rcall SET_PWM_DUTY |
rjmp WAIT_FOR_PWM_1 |
DONE_SLOPING_UP: |
mov B_Temp,ramp_target1 |
rcall SET_PWM_DUTY |
;***************************************************************** |
;* See if we need to slope down to the throttle setting |
;***************************************************************** |
in B_Temp,OCR1A ; Find PWM value |
cp B_Temp,throttle_set |
breq PULSE_GENERATE_RETURN ; Do nothing if already at final voltage |
;***************************************************************** |
;* Hang about at the top of the pulse for a while... |
;***************************************************************** |
.ifdef PULSE_WIDTH_SCALE |
mov ramp_target1,throttle_set |
.else |
clr ramp_target1 |
.endif |
add ramp_target1,Cycle_count |
subi ramp_target1,0x100-pulse_width_min ; ramp_target1 + pulse_width_min |
mov B_Temp1,ramp_target1 |
rcall COUNT_PWM_CYCLES |
;***************************************************************** |
;* Slope down |
;***************************************************************** |
mov ramp_target,throttle_set ; Ramp DOWN to this value |
subi ramp_target,0x100-pulse_slope_down ;ramp_target + pulse_slope_down |
WAIT_FOR_PWM_2: ; Wait for PWM to reset to 0 |
in B_Temp,TIFR |
sbrs B_Temp,OCF1A |
rjmp WAIT_FOR_PWM_2 |
ldi B_Temp,0b01000000 |
out TIFR,B_Temp |
inc Cycle_count |
in B_Temp,OCR1A ; Find PWM value |
cp ramp_target,B_Temp ; Make sure won't go past min |
brsh PULSE_GENERATE_RETURN |
subi B_Temp,pulse_slope_down |
rcall SET_PWM_DUTY |
rjmp WAIT_FOR_PWM_2 |
PULSE_GENERATE_RETURN: |
.endif ;PULSE_ENABLED |
/contrib/toolchain/avra/examples/throttle_set_lowpass.asm |
---|
0,0 → 1,69 |
;throttle_set_lowpass.asm |
.NOLIST |
; *************************************************************************************** |
; * PWM MODEL RAILROAD THROTTLE * |
; * * |
; * WRITTEN BY: PHILIP DEVRIES * |
; * * |
; * Copyright (C) 2003 Philip DeVries * |
; * * |
; * This program is free software; you can redistribute it and/or modify * |
; * it under the terms of the GNU General Public License as published by * |
; * the Free Software Foundation; either version 2 of the License, or * |
; * (at your option) any later version. * |
; * * |
; * This program is distributed in the hope that it will be useful, * |
; * but WITHOUT ANY WARRANTY; without even the implied warranty of * |
; * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * |
; * GNU General Public License for more details. * |
; * * |
; * You should have received a copy of the GNU General Public License * |
; * along with this program; if not, write to the Free Software * |
; * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA * |
; * * |
; *************************************************************************************** |
.LIST |
.ifdef THROTTLE_LOWPASS_ENABLED |
;***************************************************************** |
;* A transversal low pass filter * |
;* * |
;* This is copied from throttle_backemf.asm. * |
;* See the documentation there. * |
;***************************************************************** |
HILOCAL1 throttle_lo ; assign local variables |
HILOCAL2 throttle_hi |
mov throttle_lo,throttle_set |
clr throttle_hi |
;**** |
;* 1. Add in cumulative previous throttle |
;**** |
add throttle_lo,throttle_lo_prev ; Add in scaled previous samples |
adc throttle_hi,throttle_hi_prev ; |
;**** |
;* 2. |
;**** |
mov throttle_lo_prev,throttle_lo ; Store new value |
mov throttle_hi_prev,throttle_hi ; Store new value |
;**** |
;* 3. |
;**** |
B_TEMPLOCAL _lowpass_lo_byte |
ldi _lowpass_lo_byte, throttle_lowpass_gain |
rcall DIVIDE_16_SIMPLE |
;**** |
;* 4. |
;**** |
sub throttle_lo_prev,throttle_lo |
sbc throttle_hi_prev,throttle_hi |
mov throttle_set,throttle_lo |
.endif ;THROTTLE_LOWPASS_FILTER |
/contrib/toolchain/avra/examples/tn15def.inc |
---|
0,0 → 1,195 |
.NOLIST |
;*************************************************************************** |
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y |
;* |
;* Number :AVR000 |
;* File Name :"tn15def.inc" |
;* Title :Register/Bit Definitions for the ATtiny15 |
;* Date :99.07.05 |
;* Version :1.00 |
;* Support telephone :+47 72 88 87 20 (ATMEL Norway) |
;* Support fax :+47 72 88 87 18 (ATMEL Norway) |
;* Support E-mail :avr@atmel.com |
;* Target MCU :ATtiny15 |
;* |
;* DESCRIPTION |
;* When including this file in the assembly program file, all I/O register |
;* names and I/O register bit names appearing in the data book can be used. |
;* In addition, the six registers forming the three data pointers X, Y and |
;* Z have been assigned names XL - ZH. Highest RAM address for Internal |
;* SRAM is also defined |
;* |
;* The Register names are represented by their hexadecimal address. |
;* |
;* The Register Bit names are represented by their bit number (0-7). |
;* |
;* Please observe the difference in using the bit names with instructions |
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" |
;* (skip if bit in register set/cleared). The following example illustrates |
;* this: |
;* |
;* in r16,PORTB ;read PORTB latch |
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) |
;* out PORTB,r16 ;output to PORTB |
;* |
;* in r16,TIFR ;read the Timer Interrupt Flag Register |
;* sbrc r16,TOV0 ;test the overflow flag (use bit#) |
;* rjmp TOV0_is_set ;jump if set |
;* ... ;otherwise do something else |
;*************************************************************************** |
;***** Specify Device |
.device ATtiny15 |
;***** I/O Register Definitions |
.equ SREG =$3f |
.equ GIMSK =$3b |
.equ GIFR =$3a |
.equ TIMSK =$39 |
.equ TIFR =$38 |
.equ MCUCR =$35 |
.equ MCUSR =$34 |
.equ TCCR0 =$33 |
.equ TCNT0 =$32 |
.equ OSCCAL =$31 |
.equ TCCR1 =$30 |
.equ TCNT1 =$2f |
.equ OCR1A =$2e |
.equ OCR1B =$2d |
.equ SFIOR =$2c |
.equ WDTCR =$21 |
.equ EEAR =$1e |
.equ EEDR =$1d |
.equ EECR =$1c |
.equ PORTB =$18 |
.equ DDRB =$17 |
.equ PINB =$16 |
.equ ACSR =$08 |
.equ ADMUX =$07 |
.equ ADCSR =$06 |
.equ ADCH =$05 |
.equ ADCL =$04 |
;***** Bit Definitions |
.equ INT0 =6 |
.equ PCIE =5 |
.equ INTF0 =6 |
.equ PCIF =5 |
.equ OCIE1 =6 |
.equ TOIE1 =2 |
.equ TOIE0 =1 |
.equ OCF1A =6 |
.equ TOV1 =2 |
.equ TOV0 =1 |
.equ PUD =6 |
.equ SE =5 |
.equ SM =4 |
.equ SM1 =4 |
.equ SM0 =3 |
.equ ISC01 =1 |
.equ ISC00 =0 |
.equ WDRF =3 |
.equ BORF =2 |
.equ EXTRF =1 |
.equ PORF =0 |
.equ CS02 =2 |
.equ CS01 =1 |
.equ CS00 =0 |
.equ CAL7 =7 |
.equ CAL6 =6 |
.equ CAL5 =5 |
.equ CAL4 =4 |
.equ CAL3 =3 |
.equ CAL2 =2 |
.equ CAL1 =1 |
.equ CAL0 =0 |
.equ CTC1 =7 |
.equ PWM1 =6 |
.equ COM11 =5 |
.equ COM10 =4 |
.equ CS13 =3 |
.equ CS12 =2 |
.equ CS11 =1 |
.equ CS10 =0 |
.equ FOCM =2 |
.equ PSR1 =1 |
.equ PSR0 =0 |
.equ WDTOE =4 |
.equ WDE =3 |
.equ WDP2 =2 |
.equ WDP1 =1 |
.equ WDP0 =0 |
.equ EERIE =3 |
.equ EEMWE =2 |
.equ EEWE =1 |
.equ EERE =0 |
.equ PB4 =4 |
.equ PB3 =3 |
.equ PB2 =2 |
.equ PB1 =1 |
.equ PB0 =0 |
.equ DDB5 =5 |
.equ DDB4 =4 |
.equ DDB3 =3 |
.equ DDB2 =2 |
.equ DDB1 =1 |
.equ DDB0 =0 |
.equ PINB5 =5 |
.equ PINB4 =4 |
.equ PINB3 =3 |
.equ PINB2 =2 |
.equ PINB1 =1 |
.equ PINB0 =0 |
.equ ACD =7 |
.equ ACO =5 |
.equ ACI =4 |
.equ ACIE =3 |
.equ ACIS1 =1 |
.equ ACIS0 =0 |
.equ REFS1 =7 |
.equ REFS0 =6 |
.equ ADLAR =5 |
.equ MUX2 =2 |
.equ MUX1 =1 |
.equ MUX0 =0 |
.equ ADEN =7 |
.equ ADSC =6 |
.equ ADFR =5 |
.equ ADIF =4 |
.equ ADIE =3 |
.equ ADPS2 =2 |
.equ ADPS1 =1 |
.equ ADPS0 =0 |
.def ZL =r30 |
.def ZH =r31 |
.equ INT0addr=$001 ;External Interrupt0 Vector Address |
.equ PCINTaddr=$002 ;Pin change Interrupt Vector Address |
.equ T1COMPaddr=$003 ;Timer1 Compare match interrupt vector address |
.equ OVF1addr=$004 ;Overflow 1 Interrupt Vector Address |
.equ OVF0addr=$005 ;Overflow 1 Interrupt Vector Address |
.equ EERDYaddr =$006 ;EEPROM Interrupt Vector Address |
.equ ACIaddr =$007 ;Analog Comparator Interrupt Vector Address |
.equ ADCCaddr =$008 ;ADC Interrupt Vector Address |
.LIST |
/contrib/toolchain/avra/includes/1200def.inc |
---|
0,0 → 1,297 |
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** |
;***** Created: 2005-01-11 10:30 ******* Source: AT90S1200.xml *********** |
;************************************************************************* |
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y |
;* |
;* Number : AVR000 |
;* File Name : "1200def.inc" |
;* Title : Register/Bit Definitions for the AT90S1200 |
;* Date : 2005-01-11 |
;* Version : 2.14 |
;* Support E-mail : avr@atmel.com |
;* Target MCU : AT90S1200 |
;* |
;* DESCRIPTION |
;* When including this file in the assembly program file, all I/O register |
;* names and I/O register bit names appearing in the data book can be used. |
;* In addition, the six registers forming the three data pointers X, Y and |
;* Z have been assigned names XL - ZH. Highest RAM address for Internal |
;* SRAM is also defined |
;* |
;* The Register names are represented by their hexadecimal address. |
;* |
;* The Register Bit names are represented by their bit number (0-7). |
;* |
;* Please observe the difference in using the bit names with instructions |
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" |
;* (skip if bit in register set/cleared). The following example illustrates |
;* this: |
;* |
;* in r16,PORTB ;read PORTB latch |
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) |
;* out PORTB,r16 ;output to PORTB |
;* |
;* in r16,TIFR ;read the Timer Interrupt Flag Register |
;* sbrc r16,TOV0 ;test the overflow flag (use bit#) |
;* rjmp TOV0_is_set ;jump if set |
;* ... ;otherwise do something else |
;************************************************************************* |
#ifndef _1200DEF_INC_ |
#define _1200DEF_INC_ |
#pragma partinc 0 |
; ***** SPECIFY DEVICE *************************************************** |
.device AT90S1200 |
#pragma AVRPART ADMIN PART_NAME AT90S1200 |
.equ SIGNATURE_000 = 0x1e |
.equ SIGNATURE_001 = 0x90 |
.equ SIGNATURE_002 = 0x01 |
#pragma AVRPART CORE CORE_VERSION V0 |
; ***** I/O REGISTER DEFINITIONS ***************************************** |
; NOTE: |
; Definitions marked "MEMORY MAPPED"are extended I/O ports |
; and cannot be used with IN/OUT instructions |
.equ SREG = 0x3f |
.equ GIMSK = 0x3b |
.equ TIMSK = 0x39 |
.equ TIFR = 0x38 |
.equ MCUCR = 0x35 |
.equ TCCR0 = 0x33 |
.equ TCNT0 = 0x32 |
.equ WDTCR = 0x21 |
.equ EEAR = 0x1e |
.equ EEDR = 0x1d |
.equ EECR = 0x1c |
.equ PORTB = 0x18 |
.equ DDRB = 0x17 |
.equ PINB = 0x16 |
.equ PORTD = 0x12 |
.equ DDRD = 0x11 |
.equ PIND = 0x10 |
.equ ACSR = 0x08 |
; ***** BIT DEFINITIONS ************************************************** |
; ***** TIMER_COUNTER_0 ************** |
; TIMSK - Timer/Counter Interrupt Mask Register |
.equ TOIE0 = 1 ; Timer/Counter0 Overflow Interrupt Enable |
; TIFR - Timer/Counter Interrupt Flag register |
.equ TOV0 = 1 ; Timer/Counter0 Overflow Flag |
; TCCR0 - Timer/Counter0 Control Register |
.equ CS00 = 0 ; Clock Select0 bit 0 |
.equ CS01 = 1 ; Clock Select0 bit 1 |
.equ CS02 = 2 ; Clock Select0 bit 2 |
; TCNT0 - Timer Counter 0 |
.equ TCNT00 = 0 ; Timer Counter 0 bit 0 |
.equ TCNT01 = 1 ; Timer Counter 0 bit 1 |
.equ TCNT02 = 2 ; Timer Counter 0 bit 2 |
.equ TCNT03 = 3 ; Timer Counter 0 bit 3 |
.equ TCNT04 = 4 ; Timer Counter 0 bit 4 |
.equ TCNT05 = 5 ; Timer Counter 0 bit 5 |
.equ TCNT06 = 6 ; Timer Counter 0 bit 6 |
.equ TCNT07 = 7 ; Timer Counter 0 bit 7 |
; ***** WATCHDOG ********************* |
; WDTCR - Watchdog Timer Control Register |
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 |
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 |
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 |
.equ WDE = 3 ; Watch Dog Enable |
; ***** PORTB ************************ |
; PORTB - Port B Data Register |
.equ PORTB0 = 0 ; Port B Data Register bit 0 |
.equ PB0 = 0 ; For compatibility |
.equ PORTB1 = 1 ; Port B Data Register bit 1 |
.equ PB1 = 1 ; For compatibility |
.equ PORTB2 = 2 ; Port B Data Register bit 2 |
.equ PB2 = 2 ; For compatibility |
.equ PORTB3 = 3 ; Port B Data Register bit 3 |
.equ PB3 = 3 ; For compatibility |
.equ PORTB4 = 4 ; Port B Data Register bit 4 |
.equ PB4 = 4 ; For compatibility |
.equ PORTB5 = 5 ; Port B Data Register bit 5 |
.equ PB5 = 5 ; For compatibility |
.equ PORTB6 = 6 ; Port B Data Register bit 6 |
.equ PB6 = 6 ; For compatibility |
.equ PORTB7 = 7 ; Port B Data Register bit 7 |
.equ PB7 = 7 ; For compatibility |
; DDRB - Port B Data Direction Register |
.equ DDB0 = 0 ; Port B Data Direction Register bit 0 |
.equ DDB1 = 1 ; Port B Data Direction Register bit 1 |
.equ DDB2 = 2 ; Port B Data Direction Register bit 2 |
.equ DDB3 = 3 ; Port B Data Direction Register bit 3 |
.equ DDB4 = 4 ; Port B Data Direction Register bit 4 |
.equ DDB5 = 5 ; Port B Data Direction Register bit 5 |
.equ DDB6 = 6 ; Port B Data Direction Register bit 6 |
.equ DDB7 = 7 ; Port B Data Direction Register bit 7 |
; PINB - Port B Input Pins |
.equ PINB0 = 0 ; Port B Input Pins bit 0 |
.equ PINB1 = 1 ; Port B Input Pins bit 1 |
.equ PINB2 = 2 ; Port B Input Pins bit 2 |
.equ PINB3 = 3 ; Port B Input Pins bit 3 |
.equ PINB4 = 4 ; Port B Input Pins bit 4 |
.equ PINB5 = 5 ; Port B Input Pins bit 5 |
.equ PINB6 = 6 ; Port B Input Pins bit 6 |
.equ PINB7 = 7 ; Port B Input Pins bit 7 |
; ***** PORTD ************************ |
; PORTD - Data Register, Port D |
.equ PORTD0 = 0 ; |
.equ PD0 = 0 ; For compatibility |
.equ PORTD1 = 1 ; |
.equ PD1 = 1 ; For compatibility |
.equ PORTD2 = 2 ; |
.equ PD2 = 2 ; For compatibility |
.equ PORTD3 = 3 ; |
.equ PD3 = 3 ; For compatibility |
.equ PORTD4 = 4 ; |
.equ PD4 = 4 ; For compatibility |
.equ PORTD5 = 5 ; |
.equ PD5 = 5 ; For compatibility |
.equ PORTD6 = 6 ; |
.equ PD6 = 6 ; For compatibility |
; DDRD |
.equ DDD0 = 0 ; |
.equ DDD1 = 1 ; |
.equ DDD2 = 2 ; |
.equ DDD3 = 3 ; |
.equ DDD4 = 4 ; |
.equ DDD5 = 5 ; |
.equ DDD6 = 6 ; |
; PIND - Input Pins, Port D |
.equ PIND0 = 0 ; |
.equ PIND1 = 1 ; |
.equ PIND2 = 2 ; |
.equ PIND3 = 3 ; |
.equ PIND4 = 4 ; |
.equ PIND5 = 5 ; |
.equ PIND6 = 6 ; |
; ***** ANALOG_COMPARATOR ************ |
; ACSR - Analog Comparator Control And Status Register |
.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 |
.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 |
.equ ACIE = 3 ; Analog Comparator Interrupt Enable |
.equ ACI = 4 ; Analog Comparator Interrupt Flag |
.equ ACO = 5 ; Analog Comparator Output |
.equ ACD = 7 ; Analog Comparator Disable |
; ***** CPU ************************** |
; SREG - Status Register |
.equ SREG_C = 0 ; Carry Flag |
.equ SREG_Z = 1 ; Zero Flag |
.equ SREG_N = 2 ; Negative Flag |
.equ SREG_V = 3 ; Two's Complement Overflow Flag |
.equ SREG_S = 4 ; Sign Bit |
.equ SREG_H = 5 ; Half Carry Flag |
.equ SREG_T = 6 ; Bit Copy Storage |
.equ SREG_I = 7 ; Global Interrupt Enable |
; MCUCR - MCU Control Register |
.equ ISC00 = 0 ; Interrupt Sense Control 0 bit 0 |
.equ ISC01 = 1 ; Interrupt Sense Control 0 bit 1 |
.equ SM = 4 ; Sleep Mode |
.equ SE = 5 ; Sleep Enable |
; ***** EXTERNAL_INTERRUPT *********** |
; GIMSK - General Interrupt Mask Register |
.equ INT0 = 6 ; External Interrupt Request 0 Enable |
; ***** EEPROM *********************** |
; EEAR - EEPROM Read/Write Access |
.equ EEAR0 = 0 ; EEPROM Read/Write Access bit 0 |
.equ EEAR1 = 1 ; EEPROM Read/Write Access bit 1 |
.equ EEAR2 = 2 ; EEPROM Read/Write Access bit 2 |
.equ EEAR3 = 3 ; EEPROM Read/Write Access bit 3 |
.equ EEAR4 = 4 ; EEPROM Read/Write Access bit 4 |
.equ EEAR5 = 5 ; EEPROM Read/Write Access bit 5 |
.equ EEAR6 = 6 ; EEPROM Read/Write Access bit 6 |
; EEDR - EEPROM Data Register |
.equ EEDR0 = 0 ; EEPROM Data Register bit 0 |
.equ EEDR1 = 1 ; EEPROM Data Register bit 1 |
.equ EEDR2 = 2 ; EEPROM Data Register bit 2 |
.equ EEDR3 = 3 ; EEPROM Data Register bit 3 |
.equ EEDR4 = 4 ; EEPROM Data Register bit 4 |
.equ EEDR5 = 5 ; EEPROM Data Register bit 5 |
.equ EEDR6 = 6 ; EEPROM Data Register bit 6 |
.equ EEDR7 = 7 ; EEPROM Data Register bit 7 |
; EECR - EEPROM Control Register |
.equ EERE = 0 ; EEPROM Read Enable |
.equ EEWE = 1 ; EEPROM Write Enable |
; ***** LOCKSBITS ******************************************************** |
.equ LB1 = 0 ; Lockbit |
.equ LB2 = 1 ; Lockbit |
; ***** FUSES ************************************************************ |
; LOW fuse bits |
; ***** CPU REGISTER DEFINITIONS ***************************************** |
.def XH = r27 |
.def XL = r26 |
.def YH = r29 |
.def YL = r28 |
.def ZH = r31 |
.def ZL = r30 |
; ***** DATA MEMORY DECLARATIONS ***************************************** |
.equ FLASHEND = 0x01ff ; Note: Word address |
.equ IOEND = 0x003f |
.equ SRAM_SIZE = 0 |
.equ RAMEND = 0x0000 |
.equ XRAMEND = 0x0000 |
.equ E2END = 0x003f |
.equ EEPROMEND = 0x003f |
.equ EEADRBITS = 6 |
#pragma AVRPART MEMORY PROG_FLASH 1024 |
#pragma AVRPART MEMORY EEPROM 64 |
#pragma AVRPART MEMORY INT_SRAM SIZE 0 |
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x0 |
; ***** INTERRUPT VECTORS ************************************************ |
.equ INT0addr = 0x0001 ; External Interrupt 0 |
.equ OVF0addr = 0x0002 ; Timer/Counter0 Overflow |
.equ ACIaddr = 0x0003 ; Analog Comparator |
.equ INT_VECTORS_SIZE = 4 ; size in words |
#pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED break |
#endif /* _1200DEF_INC_ */ |
; ***** END OF FILE ****************************************************** |
/contrib/toolchain/avra/includes/2313def.inc |
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0,0 → 1,406 |
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** |
;***** Created: 2005-01-11 10:30 ******* Source: AT90S2313.xml *********** |
;************************************************************************* |
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y |
;* |
;* Number : AVR000 |
;* File Name : "2313def.inc" |
;* Title : Register/Bit Definitions for the AT90S2313 |
;* Date : 2005-01-11 |
;* Version : 2.14 |
;* Support E-mail : avr@atmel.com |
;* Target MCU : AT90S2313 |
;* |
;* DESCRIPTION |
;* When including this file in the assembly program file, all I/O register |
;* names and I/O register bit names appearing in the data book can be used. |
;* In addition, the six registers forming the three data pointers X, Y and |
;* Z have been assigned names XL - ZH. Highest RAM address for Internal |
;* SRAM is also defined |
;* |
;* The Register names are represented by their hexadecimal address. |
;* |
;* The Register Bit names are represented by their bit number (0-7). |
;* |
;* Please observe the difference in using the bit names with instructions |
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" |
;* (skip if bit in register set/cleared). The following example illustrates |
;* this: |
;* |
;* in r16,PORTB ;read PORTB latch |
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) |
;* out PORTB,r16 ;output to PORTB |
;* |
;* in r16,TIFR ;read the Timer Interrupt Flag Register |
;* sbrc r16,TOV0 ;test the overflow flag (use bit#) |
;* rjmp TOV0_is_set ;jump if set |
;* ... ;otherwise do something else |
;************************************************************************* |
#ifndef _2313DEF_INC_ |
#define _2313DEF_INC_ |
#pragma partinc 0 |
; ***** SPECIFY DEVICE *************************************************** |
.device AT90S2313 |
#pragma AVRPART ADMIN PART_NAME AT90S2313 |
.equ SIGNATURE_000 = 0x1e |
.equ SIGNATURE_001 = 0x91 |
.equ SIGNATURE_002 = 0x01 |
#pragma AVRPART CORE CORE_VERSION V1 |
; ***** I/O REGISTER DEFINITIONS ***************************************** |
; NOTE: |
; Definitions marked "MEMORY MAPPED"are extended I/O ports |
; and cannot be used with IN/OUT instructions |
.equ SREG = 0x3f |
.equ SPL = 0x3d |
.equ GIMSK = 0x3b |
.equ GIFR = 0x3a |
.equ TIMSK = 0x39 |
.equ TIFR = 0x38 |
.equ MCUCR = 0x35 |
.equ TCCR0 = 0x33 |
.equ TCNT0 = 0x32 |
.equ TCCR1A = 0x2f |
.equ TCCR1B = 0x2e |
.equ TCNT1H = 0x2d |
.equ TCNT1L = 0x2c |
.equ OCR1AH = 0x2b |
.equ OCR1AL = 0x2a |
.equ ICR1H = 0x25 |
.equ ICR1L = 0x24 |
.equ WDTCR = 0x21 |
.equ EEAR = 0x1e |
.equ EEDR = 0x1d |
.equ EECR = 0x1c |
.equ PORTB = 0x18 |
.equ DDRB = 0x17 |
.equ PINB = 0x16 |
.equ PORTD = 0x12 |
.equ DDRD = 0x11 |
.equ PIND = 0x10 |
.equ UDR = 0x0c |
.equ USR = 0x0b |
.equ UCR = 0x0a |
.equ UBRR = 0x09 |
.equ ACSR = 0x08 |
; ***** BIT DEFINITIONS ************************************************** |
; ***** PORTB ************************ |
; PORTB - Port B Data Register |
.equ PORTB0 = 0 ; Port B Data Register bit 0 |
.equ PB0 = 0 ; For compatibility |
.equ PORTB1 = 1 ; Port B Data Register bit 1 |
.equ PB1 = 1 ; For compatibility |
.equ PORTB2 = 2 ; Port B Data Register bit 2 |
.equ PB2 = 2 ; For compatibility |
.equ PORTB3 = 3 ; Port B Data Register bit 3 |
.equ PB3 = 3 ; For compatibility |
.equ PORTB4 = 4 ; Port B Data Register bit 4 |
.equ PB4 = 4 ; For compatibility |
.equ PORTB5 = 5 ; Port B Data Register bit 5 |
.equ PB5 = 5 ; For compatibility |
.equ PORTB6 = 6 ; Port B Data Register bit 6 |
.equ PB6 = 6 ; For compatibility |
.equ PORTB7 = 7 ; Port B Data Register bit 7 |
.equ PB7 = 7 ; For compatibility |
; DDRB - Port B Data Direction Register |
.equ DDB0 = 0 ; Port B Data Direction Register bit 0 |
.equ DDB1 = 1 ; Port B Data Direction Register bit 1 |
.equ DDB2 = 2 ; Port B Data Direction Register bit 2 |
.equ DDB3 = 3 ; Port B Data Direction Register bit 3 |
.equ DDB4 = 4 ; Port B Data Direction Register bit 4 |
.equ DDB5 = 5 ; Port B Data Direction Register bit 5 |
.equ DDB6 = 6 ; Port B Data Direction Register bit 6 |
.equ DDB7 = 7 ; Port B Data Direction Register bit 7 |
; PINB - Port B Input Pins |
.equ PINB0 = 0 ; Port B Input Pins bit 0 |
.equ PINB1 = 1 ; Port B Input Pins bit 1 |
.equ PINB2 = 2 ; Port B Input Pins bit 2 |
.equ PINB3 = 3 ; Port B Input Pins bit 3 |
.equ PINB4 = 4 ; Port B Input Pins bit 4 |
.equ PINB5 = 5 ; Port B Input Pins bit 5 |
.equ PINB6 = 6 ; Port B Input Pins bit 6 |
.equ PINB7 = 7 ; Port B Input Pins bit 7 |
; ***** TIMER_COUNTER_0 ************** |
; TIMSK - Timer/Counter Interrupt Mask Register |
.equ TOIE0 = 1 ; Timer/Counter0 Overflow Interrupt Enable |
; TIFR - Timer/Counter Interrupt Flag register |
.equ TOV0 = 1 ; Timer/Counter0 Overflow Flag |
; TCCR0 - Timer/Counter0 Control Register |
.equ CS00 = 0 ; Clock Select0 bit 0 |
.equ CS01 = 1 ; Clock Select0 bit 1 |
.equ CS02 = 2 ; Clock Select0 bit 2 |
; TCNT0 - Timer Counter 0 |
.equ TCNT00 = 0 ; Timer Counter 0 bit 0 |
.equ TCNT01 = 1 ; Timer Counter 0 bit 1 |
.equ TCNT02 = 2 ; Timer Counter 0 bit 2 |
.equ TCNT03 = 3 ; Timer Counter 0 bit 3 |
.equ TCNT04 = 4 ; Timer Counter 0 bit 4 |
.equ TCNT05 = 5 ; Timer Counter 0 bit 5 |
.equ TCNT06 = 6 ; Timer Counter 0 bit 6 |
.equ TCNT07 = 7 ; Timer Counter 0 bit 7 |
; ***** TIMER_COUNTER_1 ************** |
; TIMSK - Timer/Counter Interrupt Mask Register |
.equ TICIE1 = 3 ; Timer/Counter1 Input Capture Interrupt Enable |
.equ OCIE1A = 6 ; Timer/Counter1 Output CompareA Match Interrupt Enable |
.equ TOIE1 = 7 ; Timer/Counter1 Overflow Interrupt Enable |
; TIFR - Timer/Counter Interrupt Flag register |
.equ ICF1 = 3 ; Input Capture Flag 1 |
.equ OCF1A = 6 ; Output Compare Flag 1A |
.equ TOV1 = 7 ; Timer/Counter1 Overflow Flag |
; TCCR1A - Timer/Counter1 Control Register A |
.equ PWM10 = 0 ; Pulse Width Modulator Select Bit 0 |
.equ PWM11 = 1 ; Pulse Width Modulator Select Bit 1 |
.equ COM1A0 = 6 ; Comparet Ouput Mode 1A, bit 0 |
.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1 |
; TCCR1B - Timer/Counter1 Control Register B |
.equ CS10 = 0 ; Clock Select bit 0 |
.equ CS11 = 1 ; Clock Select 1 bit 1 |
.equ CS12 = 2 ; Clock Select1 bit 2 |
.equ CTC1 = 3 ; Clear Timer/Counter1 on Compare Match |
.equ ICES1 = 6 ; Input Capture 1 Edge Select |
.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler |
; ***** WATCHDOG ********************* |
; WDTCR - Watchdog Timer Control Register |
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 |
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 |
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 |
.equ WDE = 3 ; Watch Dog Enable |
.equ WDTOE = 4 ; RW |
.equ WDDE = WDTOE ; For compatibility |
; ***** EXTERNAL_INTERRUPT *********** |
; GIMSK - General Interrupt Mask Register |
.equ INT0 = 6 ; External Interrupt Request 0 Enable |
.equ INT1 = 7 ; External Interrupt Request 1 Enable |
; GIFR - General Interrupt Flag register |
.equ INTF0 = 6 ; External Interrupt Flag 0 |
.equ INTF1 = 7 ; External Interrupt Flag 1 |
; ***** UART ************************* |
; UDR - UART I/O Data Register |
.equ UDR0 = 0 ; UART I/O Data Register bit 0 |
.equ UDR1 = 1 ; UART I/O Data Register bit 1 |
.equ UDR2 = 2 ; UART I/O Data Register bit 2 |
.equ UDR3 = 3 ; UART I/O Data Register bit 3 |
.equ UDR4 = 4 ; UART I/O Data Register bit 4 |
.equ UDR5 = 5 ; UART I/O Data Register bit 5 |
.equ UDR6 = 6 ; UART I/O Data Register bit 6 |
.equ UDR7 = 7 ; UART I/O Data Register bit 7 |
; USR - UART Status Register |
.equ DOR = 3 ; Data overRun |
.equ FE = 4 ; Framing Error |
.equ UDRE = 5 ; UART Data Register Empty |
.equ TXC = 6 ; UART Transmit Complete |
.equ RXC = 7 ; UART Receive Complete |
; UCR - UART Control Register |
.equ TXB8 = 0 ; Transmit Data Bit 8 |
.equ RXB8 = 1 ; Receive Data Bit 8 |
.equ CHR9 = 2 ; 9-bit Characters |
.equ TXEN = 3 ; Transmitter Enable |
.equ RXEN = 4 ; Receiver Enable |
.equ UDRIE = 5 ; UART Data Register Empty Interrupt Enable |
.equ TXCIE = 6 ; TX Complete Interrupt Enable |
.equ RXCIE = 7 ; RX Complete Interrupt Enable |
; UBRR - UART BAUD Rate Register |
.equ UBRR0 = 0 ; UART Baud Rate Register bit 0 |
.equ UBRR1 = 1 ; UART Baud Rate Register bit 1 |
.equ UBRR2 = 2 ; UART Baud Rate Register bit 2 |
.equ UBRR3 = 3 ; UART Baud Rate Register bit 3 |
.equ UBRR4 = 4 ; UART Baud Rate Register bit 4 |
.equ UBRR5 = 5 ; UART Baud Rate Register bit 5 |
.equ UBRR6 = 6 ; UART Baud Rate Register bit 6 |
.equ UBRR7 = 7 ; UART Baud Rate Register bit 7 |
; ***** ANALOG_COMPARATOR ************ |
; ACSR - Analog Comparator Control And Status Register |
.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 |
.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 |
.equ ACIC = 2 ; Analog Comparator Input Capture Enable |
.equ ACIE = 3 ; Analog Comparator Interrupt Enable |
.equ ACI = 4 ; Analog Comparator Interrupt Flag |
.equ ACO = 5 ; Analog Comparator Output |
.equ ACD = 7 ; Analog Comparator Disable |
; ***** CPU ************************** |
; SREG - Status Register |
.equ SREG_C = 0 ; Carry Flag |
.equ SREG_Z = 1 ; Zero Flag |
.equ SREG_N = 2 ; Negative Flag |
.equ SREG_V = 3 ; Two's Complement Overflow Flag |
.equ SREG_S = 4 ; Sign Bit |
.equ SREG_H = 5 ; Half Carry Flag |
.equ SREG_T = 6 ; Bit Copy Storage |
.equ SREG_I = 7 ; Global Interrupt Enable |
; SPL - Stack Pointer Low |
.equ SP0 = 0 ; Stack pointer bit 0 |
.equ SP1 = 1 ; Stack pointer bit 1 |
.equ SP2 = 2 ; Stack pointer bit 2 |
.equ SP3 = 3 ; Stack pointer bit 3 |
.equ SP4 = 4 |
.equ SP5 = 5 ; Stack pointer bit 5 |
.equ SP6 = 6 ; Stack pointer bit 6 |
.equ SP7 = 7 ; Stack pointer bit 7 |
; MCUCR - MCU Control Register |
.equ ISC00 = 0 ; Interrupt Sense Control 0 bit 0 |
.equ ISC01 = 1 ; Interrupt Sense Control 0 bit 1 |
.equ ISC10 = 2 ; Interrupt Sense Control 1 bit 0 |
.equ ISC11 = 3 ; Interrupt Sense Control 1 bit 1 |
.equ SM = 4 ; Sleep Mode |
.equ SE = 5 ; Sleep Enable |
; ***** PORTD ************************ |
; PORTD - Data Register, Port D |
.equ PORTD0 = 0 ; |
.equ PD0 = 0 ; For compatibility |
.equ PORTD1 = 1 ; |
.equ PD1 = 1 ; For compatibility |
.equ PORTD2 = 2 ; |
.equ PD2 = 2 ; For compatibility |
.equ PORTD3 = 3 ; |
.equ PD3 = 3 ; For compatibility |
.equ PORTD4 = 4 ; |
.equ PD4 = 4 ; For compatibility |
.equ PORTD5 = 5 ; |
.equ PD5 = 5 ; For compatibility |
.equ PORTD6 = 6 ; |
.equ PD6 = 6 ; For compatibility |
; DDRD |
.equ DDD0 = 0 ; |
.equ DDD1 = 1 ; |
.equ DDD2 = 2 ; |
.equ DDD3 = 3 ; |
.equ DDD4 = 4 ; |
.equ DDD5 = 5 ; |
.equ DDD6 = 6 ; |
; PIND - Input Pins, Port D |
.equ PIND0 = 0 ; |
.equ PIND1 = 1 ; |
.equ PIND2 = 2 ; |
.equ PIND3 = 3 ; |
.equ PIND4 = 4 ; |
.equ PIND5 = 5 ; |
.equ PIND6 = 6 ; |
; ***** EEPROM *********************** |
; EEAR - EEPROM Read/Write Access |
.equ EEARL = EEAR ; For compatibility |
.equ EEAR0 = 0 ; EEPROM Read/Write Access bit 0 |
.equ EEAR1 = 1 ; EEPROM Read/Write Access bit 1 |
.equ EEAR2 = 2 ; EEPROM Read/Write Access bit 2 |
.equ EEAR3 = 3 ; EEPROM Read/Write Access bit 3 |
.equ EEAR4 = 4 ; EEPROM Read/Write Access bit 4 |
.equ EEAR5 = 5 ; EEPROM Read/Write Access bit 5 |
.equ EEAR6 = 6 ; EEPROM Read/Write Access bit 6 |
; EEDR - EEPROM Data Register |
.equ EEDR0 = 0 ; EEPROM Data Register bit 0 |
.equ EEDR1 = 1 ; EEPROM Data Register bit 1 |
.equ EEDR2 = 2 ; EEPROM Data Register bit 2 |
.equ EEDR3 = 3 ; EEPROM Data Register bit 3 |
.equ EEDR4 = 4 ; EEPROM Data Register bit 4 |
.equ EEDR5 = 5 ; EEPROM Data Register bit 5 |
.equ EEDR6 = 6 ; EEPROM Data Register bit 6 |
.equ EEDR7 = 7 ; EEPROM Data Register bit 7 |
; EECR - EEPROM Control Register |
.equ EERE = 0 ; EEPROM Read Enable |
.equ EEWE = 1 ; EEPROM Write Enable |
.equ EEMWE = 2 ; EEPROM Master Write Enable |
; ***** LOCKSBITS ******************************************************** |
.equ LB1 = 0 ; Lockbit |
.equ LB2 = 1 ; Lockbit |
; ***** FUSES ************************************************************ |
; LOW fuse bits |
; ***** CPU REGISTER DEFINITIONS ***************************************** |
.def XH = r27 |
.def XL = r26 |
.def YH = r29 |
.def YL = r28 |
.def ZH = r31 |
.def ZL = r30 |
; ***** DATA MEMORY DECLARATIONS ***************************************** |
.equ FLASHEND = 0x03ff ; Note: Word address |
.equ IOEND = 0x003f |
.equ SRAM_START = 0x0060 |
.equ SRAM_SIZE = 128 |
.equ RAMEND = 0x00df |
.equ XRAMEND = 0x0000 |
.equ E2END = 0x007f |
.equ EEPROMEND = 0x007f |
.equ EEADRBITS = 7 |
#pragma AVRPART MEMORY PROG_FLASH 2048 |
#pragma AVRPART MEMORY EEPROM 128 |
#pragma AVRPART MEMORY INT_SRAM SIZE 128 |
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60 |
; ***** INTERRUPT VECTORS ************************************************ |
.equ INT0addr = 0x0001 ; External Interrupt Request 0 |
.equ INT1addr = 0x0002 ; External Interrupt Request 1 |
.equ ICP1addr = 0x0003 ; Timer/Counter1 Capture Event |
.equ OC1addr = 0x0004 ; Timer/Counter1 Compare Match |
.equ OVF1addr = 0x0005 ; Timer/Counter1 Overflow |
.equ OVF0addr = 0x0006 ; Timer/Counter0 Overflow |
.equ URXCaddr = 0x0007 ; UART, Rx Complete |
.equ UDREaddr = 0x0008 ; UART Data Register Empty |
.equ UTXCaddr = 0x0009 ; UART, Tx Complete |
.equ ACIaddr = 0x000a ; Analog Comparator |
.equ INT_VECTORS_SIZE = 11 ; size in words |
#pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED break |
#endif /* _2313DEF_INC_ */ |
; ***** END OF FILE ****************************************************** |
/contrib/toolchain/avra/includes/2323def.inc |
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0,0 → 1,248 |
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** |
;***** Created: 2005-01-11 10:30 ******* Source: AT90S2323.xml *********** |
;************************************************************************* |
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y |
;* |
;* Number : AVR000 |
;* File Name : "2323def.inc" |
;* Title : Register/Bit Definitions for the AT90S2323 |
;* Date : 2005-01-11 |
;* Version : 2.14 |
;* Support E-mail : avr@atmel.com |
;* Target MCU : AT90S2323 |
;* |
;* DESCRIPTION |
;* When including this file in the assembly program file, all I/O register |
;* names and I/O register bit names appearing in the data book can be used. |
;* In addition, the six registers forming the three data pointers X, Y and |
;* Z have been assigned names XL - ZH. Highest RAM address for Internal |
;* SRAM is also defined |
;* |
;* The Register names are represented by their hexadecimal address. |
;* |
;* The Register Bit names are represented by their bit number (0-7). |
;* |
;* Please observe the difference in using the bit names with instructions |
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" |
;* (skip if bit in register set/cleared). The following example illustrates |
;* this: |
;* |
;* in r16,PORTB ;read PORTB latch |
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) |
;* out PORTB,r16 ;output to PORTB |
;* |
;* in r16,TIFR ;read the Timer Interrupt Flag Register |
;* sbrc r16,TOV0 ;test the overflow flag (use bit#) |
;* rjmp TOV0_is_set ;jump if set |
;* ... ;otherwise do something else |
;************************************************************************* |
#ifndef _2323DEF_INC_ |
#define _2323DEF_INC_ |
#pragma partinc 0 |
; ***** SPECIFY DEVICE *************************************************** |
.device AT90S2323 |
#pragma AVRPART ADMIN PART_NAME AT90S2323 |
.equ SIGNATURE_000 = 0x1e |
.equ SIGNATURE_001 = 0x91 |
.equ SIGNATURE_002 = 0x02 |
#pragma AVRPART CORE CORE_VERSION V1 |
; ***** I/O REGISTER DEFINITIONS ***************************************** |
; NOTE: |
; Definitions marked "MEMORY MAPPED"are extended I/O ports |
; and cannot be used with IN/OUT instructions |
.equ SREG = 0x3f |
.equ SPL = 0x3d |
.equ GIMSK = 0x3b |
.equ GIFR = 0x3a |
.equ TIMSK = 0x39 |
.equ TIFR = 0x38 |
.equ MCUCR = 0x35 |
.equ MCUSR = 0x34 |
.equ TCCR0 = 0x33 |
.equ TCNT0 = 0x32 |
.equ WDTCR = 0x21 |
.equ EEAR = 0x1e |
.equ EEDR = 0x1d |
.equ EECR = 0x1c |
.equ PORTB = 0x18 |
.equ DDRB = 0x17 |
.equ PINB = 0x16 |
; ***** BIT DEFINITIONS ************************************************** |
; ***** CPU ************************** |
; SREG - Status Register |
.equ SREG_C = 0 ; Carry Flag |
.equ SREG_Z = 1 ; Zero Flag |
.equ SREG_N = 2 ; Negative Flag |
.equ SREG_V = 3 ; Two's Complement Overflow Flag |
.equ SREG_S = 4 ; Sign Bit |
.equ SREG_H = 5 ; Half Carry Flag |
.equ SREG_T = 6 ; Bit Copy Storage |
.equ SREG_I = 7 ; Global Interrupt Enable |
; SPL - Stack Pointer Low |
.equ SP0 = 0 ; Stack pointer bit 0 |
.equ SP1 = 1 ; Stack pointer bit 1 |
.equ SP2 = 2 ; Stack pointer bit 2 |
.equ SP3 = 3 ; Stack pointer bit 3 |
.equ SP4 = 4 |
.equ SP5 = 5 ; Stack pointer bit 5 |
.equ SP6 = 6 ; Stack pointer bit 6 |
.equ SP7 = 7 ; Stack pointer bit 7 |
; MCUCR - MCU Control Register |
.equ ISC00 = 0 ; Interrupt Sense Control 0 bit 0 |
.equ ISC01 = 1 ; Interrupt Sense Control 0 bit 1 |
.equ SM = 4 ; Sleep Mode |
.equ SE = 5 ; Sleep Enable |
; MCUSR - |
.equ PORF = 0 ; Power On Reset Flag |
.equ EXTRF = 1 ; Externl Reset Flag |
; GIMSK - General Interrupt Mask Register |
.equ INT0 = 6 ; External Interrupt Request 0 Enable |
; GIFR - General Interrupt Flag Register |
.equ INTF0 = 6 ; External Interrupt Flag 0 |
; ***** EEPROM *********************** |
; EEAR - EEPROM Read/Write Access |
.equ EEAR0 = 0 ; EEPROM Read/Write Access bit 0 |
.equ EEAR1 = 1 ; EEPROM Read/Write Access bit 1 |
.equ EEAR2 = 2 ; EEPROM Read/Write Access bit 2 |
.equ EEAR3 = 3 ; EEPROM Read/Write Access bit 3 |
.equ EEAR4 = 4 ; EEPROM Read/Write Access bit 4 |
.equ EEAR5 = 5 ; EEPROM Read/Write Access bit 5 |
.equ EEAR6 = 6 ; EEPROM Read/Write Access bit 6 |
; EEDR - EEPROM Data Register |
.equ EEDR0 = 0 ; EEPROM Data Register bit 0 |
.equ EEDR1 = 1 ; EEPROM Data Register bit 1 |
.equ EEDR2 = 2 ; EEPROM Data Register bit 2 |
.equ EEDR3 = 3 ; EEPROM Data Register bit 3 |
.equ EEDR4 = 4 ; EEPROM Data Register bit 4 |
.equ EEDR5 = 5 ; EEPROM Data Register bit 5 |
.equ EEDR6 = 6 ; EEPROM Data Register bit 6 |
.equ EEDR7 = 7 ; EEPROM Data Register bit 7 |
; EECR - EEPROM Control Register |
.equ EERE = 0 ; EEPROM Read Enable |
.equ EEWE = 1 ; EEPROM Write Enable |
.equ EEMWE = 2 ; EEPROM Master Write Enable |
; ***** WATCHDOG ********************* |
; WDTCR - Watchdog Timer Control Register |
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 |
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 |
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 |
.equ WDE = 3 ; Watch Dog Enable |
.equ WDTOE = 4 ; RW |
.equ WDDE = WDTOE ; For compatibility |
; ***** TIMER_COUNTER_0 ************** |
; TIMSK - Timer/Counter Interrupt Mask Register |
.equ TOIE0 = 1 ; Timer/Counter0 Overflow Interrupt Enable |
; TIFR - Timer/Counter Interrupt Flag register |
.equ TOV0 = 1 ; Timer/Counter0 Overflow Flag |
; TCCR0 - Timer/Counter0 Control Register |
.equ CS00 = 0 ; Clock Select0 bit 0 |
.equ CS01 = 1 ; Clock Select0 bit 1 |
.equ CS02 = 2 ; Clock Select0 bit 2 |
; TCNT0 - Timer Counter 0 |
.equ TCNT00 = 0 ; Timer Counter 0 bit 0 |
.equ TCNT01 = 1 ; Timer Counter 0 bit 1 |
.equ TCNT02 = 2 ; Timer Counter 0 bit 2 |
.equ TCNT03 = 3 ; Timer Counter 0 bit 3 |
.equ TCNT04 = 4 ; Timer Counter 0 bit 4 |
.equ TCNT05 = 5 ; Timer Counter 0 bit 5 |
.equ TCNT06 = 6 ; Timer Counter 0 bit 6 |
.equ TCNT07 = 7 ; Timer Counter 0 bit 7 |
; ***** PORTB ************************ |
; PORTB - Data Register, Port B |
.equ PORTB0 = 0 ; |
.equ PB0 = 0 ; For compatibility |
.equ PORTB1 = 1 ; |
.equ PB1 = 1 ; For compatibility |
.equ PORTB2 = 2 ; |
.equ PB2 = 2 ; For compatibility |
; DDRB - Data Direction Register, Port B |
.equ DDB0 = 0 ; |
.equ DDB1 = 1 ; |
.equ DDB2 = 2 ; |
; PINB - Input Pins, Port B |
.equ PINB0 = 0 ; |
.equ PINB1 = 1 ; |
.equ PINB2 = 2 ; |
; ***** LOCKSBITS ******************************************************** |
.equ LB1 = 0 ; Lockbit |
.equ LB2 = 1 ; Lockbit |
; ***** FUSES ************************************************************ |
; LOW fuse bits |
; ***** CPU REGISTER DEFINITIONS ***************************************** |
.def XH = r27 |
.def XL = r26 |
.def YH = r29 |
.def YL = r28 |
.def ZH = r31 |
.def ZL = r30 |
; ***** DATA MEMORY DECLARATIONS ***************************************** |
.equ FLASHEND = 0x03ff ; Note: Word address |
.equ IOEND = 0x003f |
.equ SRAM_START = 0x0060 |
.equ SRAM_SIZE = 128 |
.equ RAMEND = 0x00df |
.equ XRAMEND = 0x0000 |
.equ E2END = 0x007f |
.equ EEPROMEND = 0x007f |
.equ EEADRBITS = 7 |
#pragma AVRPART MEMORY PROG_FLASH 2048 |
#pragma AVRPART MEMORY EEPROM 128 |
#pragma AVRPART MEMORY INT_SRAM SIZE 128 |
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60 |
; ***** INTERRUPT VECTORS ************************************************ |
.equ INT0addr = 0x0001 ; External Interrupt 0 |
.equ OVF0addr = 0x0002 ; Timer/Counter0 Overflow |
.equ INT_VECTORS_SIZE = 3 ; size in words |
#pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED break |
#endif /* _2323DEF_INC_ */ |
; ***** END OF FILE ****************************************************** |
/contrib/toolchain/avra/includes/2343def.inc |
---|
0,0 → 1,256 |
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** |
;***** Created: 2005-01-11 10:30 ******* Source: AT90S2343.xml *********** |
;************************************************************************* |
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y |
;* |
;* Number : AVR000 |
;* File Name : "2343def.inc" |
;* Title : Register/Bit Definitions for the AT90S2343 |
;* Date : 2005-01-11 |
;* Version : 2.14 |
;* Support E-mail : avr@atmel.com |
;* Target MCU : AT90S2343 |
;* |
;* DESCRIPTION |
;* When including this file in the assembly program file, all I/O register |
;* names and I/O register bit names appearing in the data book can be used. |
;* In addition, the six registers forming the three data pointers X, Y and |
;* Z have been assigned names XL - ZH. Highest RAM address for Internal |
;* SRAM is also defined |
;* |
;* The Register names are represented by their hexadecimal address. |
;* |
;* The Register Bit names are represented by their bit number (0-7). |
;* |
;* Please observe the difference in using the bit names with instructions |
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" |
;* (skip if bit in register set/cleared). The following example illustrates |
;* this: |
;* |
;* in r16,PORTB ;read PORTB latch |
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) |
;* out PORTB,r16 ;output to PORTB |
;* |
;* in r16,TIFR ;read the Timer Interrupt Flag Register |
;* sbrc r16,TOV0 ;test the overflow flag (use bit#) |
;* rjmp TOV0_is_set ;jump if set |
;* ... ;otherwise do something else |
;************************************************************************* |
#ifndef _2343DEF_INC_ |
#define _2343DEF_INC_ |
#pragma partinc 0 |
; ***** SPECIFY DEVICE *************************************************** |
.device AT90S2343 |
#pragma AVRPART ADMIN PART_NAME AT90S2343 |
.equ SIGNATURE_000 = 0x1e |
.equ SIGNATURE_001 = 0x91 |
.equ SIGNATURE_002 = 0x03 |
#pragma AVRPART CORE CORE_VERSION V1 |
; ***** I/O REGISTER DEFINITIONS ***************************************** |
; NOTE: |
; Definitions marked "MEMORY MAPPED"are extended I/O ports |
; and cannot be used with IN/OUT instructions |
.equ SREG = 0x3f |
.equ SPL = 0x3d |
.equ GIMSK = 0x3b |
.equ GIFR = 0x3a |
.equ TIMSK = 0x39 |
.equ TIFR = 0x38 |
.equ MCUCR = 0x35 |
.equ MCUSR = 0x34 |
.equ TCCR0 = 0x33 |
.equ TCNT0 = 0x32 |
.equ WDTCR = 0x21 |
.equ EEAR = 0x1e |
.equ EEDR = 0x1d |
.equ EECR = 0x1c |
.equ PORTB = 0x18 |
.equ DDRB = 0x17 |
.equ PINB = 0x16 |
; ***** BIT DEFINITIONS ************************************************** |
; ***** CPU ************************** |
; SREG - Status Register |
.equ SREG_C = 0 ; Carry Flag |
.equ SREG_Z = 1 ; Zero Flag |
.equ SREG_N = 2 ; Negative Flag |
.equ SREG_V = 3 ; Two's Complement Overflow Flag |
.equ SREG_S = 4 ; Sign Bit |
.equ SREG_H = 5 ; Half Carry Flag |
.equ SREG_T = 6 ; Bit Copy Storage |
.equ SREG_I = 7 ; Global Interrupt Enable |
; SPL - Stack Pointer Low |
.equ SP0 = 0 ; Stack pointer bit 0 |
.equ SP1 = 1 ; Stack pointer bit 1 |
.equ SP2 = 2 ; Stack pointer bit 2 |
.equ SP3 = 3 ; Stack pointer bit 3 |
.equ SP4 = 4 |
.equ SP5 = 5 ; Stack pointer bit 5 |
.equ SP6 = 6 ; Stack pointer bit 6 |
.equ SP7 = 7 ; Stack pointer bit 7 |
; MCUCR - MCU Control Register |
.equ ISC00 = 0 ; Interrupt Sense Control 0 bit 0 |
.equ ISC01 = 1 ; Interrupt Sense Control 0 bit 1 |
.equ SM = 4 ; Sleep Mode |
.equ SE = 5 ; Sleep Enable |
; MCUSR - |
.equ PORF = 0 ; Power On Reset Flag |
.equ EXTRF = 1 ; Externl Reset Flag |
; GIMSK - General Interrupt Mask Register |
.equ INT0 = 6 ; External Interrupt Request 0 Enable |
; GIFR - General Interrupt Flag Register |
.equ INTF0 = 6 ; External Interrupt Flag 0 |
; ***** EEPROM *********************** |
; EEAR - EEPROM Read/Write Access |
.equ EEAR0 = 0 ; EEPROM Read/Write Access bit 0 |
.equ EEAR1 = 1 ; EEPROM Read/Write Access bit 1 |
.equ EEAR2 = 2 ; EEPROM Read/Write Access bit 2 |
.equ EEAR3 = 3 ; EEPROM Read/Write Access bit 3 |
.equ EEAR4 = 4 ; EEPROM Read/Write Access bit 4 |
.equ EEAR5 = 5 ; EEPROM Read/Write Access bit 5 |
.equ EEAR6 = 6 ; EEPROM Read/Write Access bit 6 |
; EEDR - EEPROM Data Register |
.equ EEDR0 = 0 ; EEPROM Data Register bit 0 |
.equ EEDR1 = 1 ; EEPROM Data Register bit 1 |
.equ EEDR2 = 2 ; EEPROM Data Register bit 2 |
.equ EEDR3 = 3 ; EEPROM Data Register bit 3 |
.equ EEDR4 = 4 ; EEPROM Data Register bit 4 |
.equ EEDR5 = 5 ; EEPROM Data Register bit 5 |
.equ EEDR6 = 6 ; EEPROM Data Register bit 6 |
.equ EEDR7 = 7 ; EEPROM Data Register bit 7 |
; EECR - EEPROM Control Register |
.equ EERE = 0 ; EEPROM Read Enable |
.equ EEWE = 1 ; EEPROM Write Enable |
.equ EEMWE = 2 ; EEPROM Master Write Enable |
; ***** WATCHDOG ********************* |
; WDTCR - Watchdog Timer Control Register |
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 |
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 |
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 |
.equ WDE = 3 ; Watch Dog Enable |
.equ WDTOE = 4 ; RW |
.equ WDDE = WDTOE ; For compatibility |
; ***** PORTB ************************ |
; PORTB - Data Register, Port B |
.equ PORTB0 = 0 ; |
.equ PB0 = 0 ; For compatibility |
.equ PORTB1 = 1 ; |
.equ PB1 = 1 ; For compatibility |
.equ PORTB2 = 2 ; |
.equ PB2 = 2 ; For compatibility |
.equ PORTB3 = 3 ; |
.equ PB3 = 3 ; For compatibility |
.equ PORTB4 = 4 ; |
.equ PB4 = 4 ; For compatibility |
; DDRB - Data Direction Register, Port B |
.equ DDB0 = 0 ; |
.equ DDB1 = 1 ; |
.equ DDB2 = 2 ; |
.equ DDB3 = 3 ; |
.equ DDB4 = 4 ; |
; PINB - Input Pins, Port B |
.equ PINB0 = 0 ; |
.equ PINB1 = 1 ; |
.equ PINB2 = 2 ; |
.equ PINB3 = 3 ; |
.equ PINB4 = 4 ; |
; ***** TIMER_COUNTER_0 ************** |
; TIMSK - Timer/Counter Interrupt Mask Register |
.equ TOIE0 = 1 ; Timer/Counter0 Overflow Interrupt Enable |
; TIFR - Timer/Counter Interrupt Flag register |
.equ TOV0 = 1 ; Timer/Counter0 Overflow Flag |
; TCCR0 - Timer/Counter0 Control Register |
.equ CS00 = 0 ; Clock Select0 bit 0 |
.equ CS01 = 1 ; Clock Select0 bit 1 |
.equ CS02 = 2 ; Clock Select0 bit 2 |
; TCNT0 - Timer Counter 0 |
.equ TCNT00 = 0 ; Timer Counter 0 bit 0 |
.equ TCNT01 = 1 ; Timer Counter 0 bit 1 |
.equ TCNT02 = 2 ; Timer Counter 0 bit 2 |
.equ TCNT03 = 3 ; Timer Counter 0 bit 3 |
.equ TCNT04 = 4 ; Timer Counter 0 bit 4 |
.equ TCNT05 = 5 ; Timer Counter 0 bit 5 |
.equ TCNT06 = 6 ; Timer Counter 0 bit 6 |
.equ TCNT07 = 7 ; Timer Counter 0 bit 7 |
; ***** LOCKSBITS ******************************************************** |
.equ LB1 = 0 ; Lockbit |
.equ LB2 = 1 ; Lockbit |
; ***** FUSES ************************************************************ |
; LOW fuse bits |
; ***** CPU REGISTER DEFINITIONS ***************************************** |
.def XH = r27 |
.def XL = r26 |
.def YH = r29 |
.def YL = r28 |
.def ZH = r31 |
.def ZL = r30 |
; ***** DATA MEMORY DECLARATIONS ***************************************** |
.equ FLASHEND = 0x03ff ; Note: Word address |
.equ IOEND = 0x003f |
.equ SRAM_START = 0x0060 |
.equ SRAM_SIZE = 128 |
.equ RAMEND = 0x00df |
.equ XRAMEND = 0x0000 |
.equ E2END = 0x007f |
.equ EEPROMEND = 0x007f |
.equ EEADRBITS = 7 |
#pragma AVRPART MEMORY PROG_FLASH 2048 |
#pragma AVRPART MEMORY EEPROM 128 |
#pragma AVRPART MEMORY INT_SRAM SIZE 128 |
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60 |
; ***** INTERRUPT VECTORS ************************************************ |
.equ INT0addr = 0x0001 ; External Interrupt 0 |
.equ OVF0addr = 0x0002 ; Timer/Counter0 Overflow |
.equ INT_VECTORS_SIZE = 3 ; size in words |
#pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED break |
#endif /* _2343DEF_INC_ */ |
; ***** END OF FILE ****************************************************** |
/contrib/toolchain/avra/includes/4414def.inc |
---|
0,0 → 1,528 |
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** |
;***** Created: 2005-01-11 10:30 ******* Source: AT90S4414.xml *********** |
;************************************************************************* |
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y |
;* |
;* Number : AVR000 |
;* File Name : "4414def.inc" |
;* Title : Register/Bit Definitions for the AT90S4414 |
;* Date : 2005-01-11 |
;* Version : 2.14 |
;* Support E-mail : avr@atmel.com |
;* Target MCU : AT90S4414 |
;* |
;* DESCRIPTION |
;* When including this file in the assembly program file, all I/O register |
;* names and I/O register bit names appearing in the data book can be used. |
;* In addition, the six registers forming the three data pointers X, Y and |
;* Z have been assigned names XL - ZH. Highest RAM address for Internal |
;* SRAM is also defined |
;* |
;* The Register names are represented by their hexadecimal address. |
;* |
;* The Register Bit names are represented by their bit number (0-7). |
;* |
;* Please observe the difference in using the bit names with instructions |
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" |
;* (skip if bit in register set/cleared). The following example illustrates |
;* this: |
;* |
;* in r16,PORTB ;read PORTB latch |
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) |
;* out PORTB,r16 ;output to PORTB |
;* |
;* in r16,TIFR ;read the Timer Interrupt Flag Register |
;* sbrc r16,TOV0 ;test the overflow flag (use bit#) |
;* rjmp TOV0_is_set ;jump if set |
;* ... ;otherwise do something else |
;************************************************************************* |
#ifndef _4414DEF_INC_ |
#define _4414DEF_INC_ |
#pragma partinc 0 |
; ***** SPECIFY DEVICE *************************************************** |
.device AT90S4414 |
#pragma AVRPART ADMIN PART_NAME AT90S4414 |
.equ SIGNATURE_000 = 0x1e |
.equ SIGNATURE_001 = 0x92 |
.equ SIGNATURE_002 = 0x01 |
#pragma AVRPART CORE CORE_VERSION V1 |
; ***** I/O REGISTER DEFINITIONS ***************************************** |
; NOTE: |
; Definitions marked "MEMORY MAPPED"are extended I/O ports |
; and cannot be used with IN/OUT instructions |
.equ SREG = 0x3f |
.equ SPH = 0x3e |
.equ SPL = 0x3d |
.equ GIMSK = 0x3b |
.equ GIFR = 0x3a |
.equ TIMSK = 0x39 |
.equ TIFR = 0x38 |
.equ MCUCR = 0x35 |
.equ TCCR0 = 0x33 |
.equ TCNT0 = 0x32 |
.equ TCCR1A = 0x2f |
.equ TCCR1B = 0x2e |
.equ TCNT1H = 0x2d |
.equ TCNT1L = 0x2c |
.equ OCR1AH = 0x2b |
.equ OCR1AL = 0x2a |
.equ OCR1BH = 0x29 |
.equ OCR1BL = 0x28 |
.equ ICR1H = 0x25 |
.equ ICR1L = 0x24 |
.equ WDTCR = 0x21 |
.equ EEAR = 0x1e |
.equ EEDR = 0x1d |
.equ EECR = 0x1c |
.equ PORTA = 0x1b |
.equ DDRA = 0x1a |
.equ PINA = 0x19 |
.equ PORTB = 0x18 |
.equ DDRB = 0x17 |
.equ PINB = 0x16 |
.equ PORTC = 0x15 |
.equ DDRC = 0x14 |
.equ PINC = 0x13 |
.equ PORTD = 0x12 |
.equ DDRD = 0x11 |
.equ PIND = 0x10 |
.equ SPDR = 0x0f |
.equ SPSR = 0x0e |
.equ SPCR = 0x0d |
.equ UDR = 0x0c |
.equ USR = 0x0b |
.equ UCR = 0x0a |
.equ UBRR = 0x09 |
.equ ACSR = 0x08 |
; ***** BIT DEFINITIONS ************************************************** |
; ***** ANALOG_COMPARATOR ************ |
; ACSR - Analog Comparator Control And Status Register |
.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 |
.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 |
.equ ACIC = 2 ; Analog Comparator Input Capture Enable |
.equ ACIE = 3 ; Analog Comparator Interrupt Enable |
.equ ACI = 4 ; Analog Comparator Interrupt Flag |
.equ ACO = 5 ; Analog Comparator Output |
.equ ACD = 7 ; Analog Comparator Disable |
; ***** SPI ************************** |
; SPDR - SPI Data Register |
.equ SPDR0 = 0 ; SPI Data Register bit 0 |
.equ SPDR1 = 1 ; SPI Data Register bit 1 |
.equ SPDR2 = 2 ; SPI Data Register bit 2 |
.equ SPDR3 = 3 ; SPI Data Register bit 3 |
.equ SPDR4 = 4 ; SPI Data Register bit 4 |
.equ SPDR5 = 5 ; SPI Data Register bit 5 |
.equ SPDR6 = 6 ; SPI Data Register bit 6 |
.equ SPDR7 = 7 ; SPI Data Register bit 7 |
; SPSR - SPI Status Register |
.equ WCOL = 6 ; Write Collision Flag |
.equ SPIF = 7 ; SPI Interrupt Flag |
; SPCR - SPI Control Register |
.equ SPR0 = 0 ; SPI Clock Rate Select 0 |
.equ SPR1 = 1 ; SPI Clock Rate Select 1 |
.equ CPHA = 2 ; Clock Phase |
.equ CPOL = 3 ; Clock polarity |
.equ MSTR = 4 ; Master/Slave Select |
.equ DORD = 5 ; Data Order |
.equ SPE = 6 ; SPI Enable |
.equ SPIE = 7 ; SPI Interrupt Enable |
; ***** UART ************************* |
; UDR - UART I/O Data Register |
.equ UDR0 = 0 ; UART I/O Data Register bit 0 |
.equ UDR1 = 1 ; UART I/O Data Register bit 1 |
.equ UDR2 = 2 ; UART I/O Data Register bit 2 |
.equ UDR3 = 3 ; UART I/O Data Register bit 3 |
.equ UDR4 = 4 ; UART I/O Data Register bit 4 |
.equ UDR5 = 5 ; UART I/O Data Register bit 5 |
.equ UDR6 = 6 ; UART I/O Data Register bit 6 |
.equ UDR7 = 7 ; UART I/O Data Register bit 7 |
; USR - UART Status Register |
.equ DOR = 3 ; Data overRun |
.equ FE = 4 ; Framing Error |
.equ UDRE = 5 ; UART Data Register Empty |
.equ TXC = 6 ; UART Transmit Complete |
.equ RXC = 7 ; UART Receive Complete |
; UCR - UART Control Register |
.equ TXB8 = 0 ; Transmit Data Bit 8 |
.equ RXB8 = 1 ; Receive Data Bit 8 |
.equ CHR9 = 2 ; 9-bit Characters |
.equ TXEN = 3 ; Transmitter Enable |
.equ RXEN = 4 ; Receiver Enable |
.equ UDRIE = 5 ; UART Data Register Empty Interrupt Enable |
.equ TXCIE = 6 ; TX Complete Interrupt Enable |
.equ RXCIE = 7 ; RX Complete Interrupt Enable |
; UBRR - UART BAUD Rate Register |
.equ UBRR0 = 0 ; UART Baud Rate Register bit 0 |
.equ UBRR1 = 1 ; UART Baud Rate Register bit 1 |
.equ UBRR2 = 2 ; UART Baud Rate Register bit 2 |
.equ UBRR3 = 3 ; UART Baud Rate Register bit 3 |
.equ UBRR4 = 4 ; UART Baud Rate Register bit 4 |
.equ UBRR5 = 5 ; UART Baud Rate Register bit 5 |
.equ UBRR6 = 6 ; UART Baud Rate Register bit 6 |
.equ UBRR7 = 7 ; UART Baud Rate Register bit 7 |
; ***** EXTERNAL_INTERRUPT *********** |
; GIMSK - General Interrupt Mask Register |
.equ INT0 = 6 ; External Interrupt Request 0 Enable |
.equ INT1 = 7 ; External Interrupt Request 1 Enable |
; GIFR - General Interrupt Flag register |
.equ INTF0 = 6 ; External Interrupt Flag 0 |
.equ INTF1 = 7 ; External Interrupt Flag 1 |
; ***** PORTA ************************ |
; PORTA - Port A Data Register |
.equ PORTA0 = 0 ; Port A Data Register bit 0 |
.equ PA0 = 0 ; For compatibility |
.equ PORTA1 = 1 ; Port A Data Register bit 1 |
.equ PA1 = 1 ; For compatibility |
.equ PORTA2 = 2 ; Port A Data Register bit 2 |
.equ PA2 = 2 ; For compatibility |
.equ PORTA3 = 3 ; Port A Data Register bit 3 |
.equ PA3 = 3 ; For compatibility |
.equ PORTA4 = 4 ; Port A Data Register bit 4 |
.equ PA4 = 4 ; For compatibility |
.equ PORTA5 = 5 ; Port A Data Register bit 5 |
.equ PA5 = 5 ; For compatibility |
.equ PORTA6 = 6 ; Port A Data Register bit 6 |
.equ PA6 = 6 ; For compatibility |
.equ PORTA7 = 7 ; Port A Data Register bit 7 |
.equ PA7 = 7 ; For compatibility |
; DDRA - Port A Data Direction Register |
.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0 |
.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1 |
.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2 |
.equ DDA3 = 3 ; Data Direction Register, Port A, bit 3 |
.equ DDA4 = 4 ; Data Direction Register, Port A, bit 4 |
.equ DDA5 = 5 ; Data Direction Register, Port A, bit 5 |
.equ DDA6 = 6 ; Data Direction Register, Port A, bit 6 |
.equ DDA7 = 7 ; Data Direction Register, Port A, bit 7 |
; PINA - Port A Input Pins |
.equ PINA0 = 0 ; Input Pins, Port A bit 0 |
.equ PINA1 = 1 ; Input Pins, Port A bit 1 |
.equ PINA2 = 2 ; Input Pins, Port A bit 2 |
.equ PINA3 = 3 ; Input Pins, Port A bit 3 |
.equ PINA4 = 4 ; Input Pins, Port A bit 4 |
.equ PINA5 = 5 ; Input Pins, Port A bit 5 |
.equ PINA6 = 6 ; Input Pins, Port A bit 6 |
.equ PINA7 = 7 ; Input Pins, Port A bit 7 |
; ***** PORTB ************************ |
; PORTB - Port B Data Register |
.equ PORTB0 = 0 ; Port B Data Register bit 0 |
.equ PB0 = 0 ; For compatibility |
.equ PORTB1 = 1 ; Port B Data Register bit 1 |
.equ PB1 = 1 ; For compatibility |
.equ PORTB2 = 2 ; Port B Data Register bit 2 |
.equ PB2 = 2 ; For compatibility |
.equ PORTB3 = 3 ; Port B Data Register bit 3 |
.equ PB3 = 3 ; For compatibility |
.equ PORTB4 = 4 ; Port B Data Register bit 4 |
.equ PB4 = 4 ; For compatibility |
.equ PORTB5 = 5 ; Port B Data Register bit 5 |
.equ PB5 = 5 ; For compatibility |
.equ PORTB6 = 6 ; Port B Data Register bit 6 |
.equ PB6 = 6 ; For compatibility |
.equ PORTB7 = 7 ; Port B Data Register bit 7 |
.equ PB7 = 7 ; For compatibility |
; DDRB - Port B Data Direction Register |
.equ DDB0 = 0 ; Port B Data Direction Register bit 0 |
.equ DDB1 = 1 ; Port B Data Direction Register bit 1 |
.equ DDB2 = 2 ; Port B Data Direction Register bit 2 |
.equ DDB3 = 3 ; Port B Data Direction Register bit 3 |
.equ DDB4 = 4 ; Port B Data Direction Register bit 4 |
.equ DDB5 = 5 ; Port B Data Direction Register bit 5 |
.equ DDB6 = 6 ; Port B Data Direction Register bit 6 |
.equ DDB7 = 7 ; Port B Data Direction Register bit 7 |
; PINB - Port B Input Pins |
.equ PINB0 = 0 ; Port B Input Pins bit 0 |
.equ PINB1 = 1 ; Port B Input Pins bit 1 |
.equ PINB2 = 2 ; Port B Input Pins bit 2 |
.equ PINB3 = 3 ; Port B Input Pins bit 3 |
.equ PINB4 = 4 ; Port B Input Pins bit 4 |
.equ PINB5 = 5 ; Port B Input Pins bit 5 |
.equ PINB6 = 6 ; Port B Input Pins bit 6 |
.equ PINB7 = 7 ; Port B Input Pins bit 7 |
; ***** PORTC ************************ |
; PORTC - Port C Data Register |
.equ PORTC0 = 0 ; Port C Data Register bit 0 |
.equ PC0 = 0 ; For compatibility |
.equ PORTC1 = 1 ; Port C Data Register bit 1 |
.equ PC1 = 1 ; For compatibility |
.equ PORTC2 = 2 ; Port C Data Register bit 2 |
.equ PC2 = 2 ; For compatibility |
.equ PORTC3 = 3 ; Port C Data Register bit 3 |
.equ PC3 = 3 ; For compatibility |
.equ PORTC4 = 4 ; Port C Data Register bit 4 |
.equ PC4 = 4 ; For compatibility |
.equ PORTC5 = 5 ; Port C Data Register bit 5 |
.equ PC5 = 5 ; For compatibility |
.equ PORTC6 = 6 ; Port C Data Register bit 6 |
.equ PC6 = 6 ; For compatibility |
.equ PORTC7 = 7 ; Port C Data Register bit 7 |
.equ PC7 = 7 ; For compatibility |
; DDRC - Port C Data Direction Register |
.equ DDC0 = 0 ; Port C Data Direction Register bit 0 |
.equ DDC1 = 1 ; Port C Data Direction Register bit 1 |
.equ DDC2 = 2 ; Port C Data Direction Register bit 2 |
.equ DDC3 = 3 ; Port C Data Direction Register bit 3 |
.equ DDC4 = 4 ; Port C Data Direction Register bit 4 |
.equ DDC5 = 5 ; Port C Data Direction Register bit 5 |
.equ DDC6 = 6 ; Port C Data Direction Register bit 6 |
.equ DDC7 = 7 ; Port C Data Direction Register bit 7 |
; PINC - Port C Input Pins |
.equ PINC0 = 0 ; Port C Input Pins bit 0 |
.equ PINC1 = 1 ; Port C Input Pins bit 1 |
.equ PINC2 = 2 ; Port C Input Pins bit 2 |
.equ PINC3 = 3 ; Port C Input Pins bit 3 |
.equ PINC4 = 4 ; Port C Input Pins bit 4 |
.equ PINC5 = 5 ; Port C Input Pins bit 5 |
.equ PINC6 = 6 ; Port C Input Pins bit 6 |
.equ PINC7 = 7 ; Port C Input Pins bit 7 |
; ***** PORTD ************************ |
; PORTD - Port D Data Register |
.equ PORTD0 = 0 ; Port D Data Register bit 0 |
.equ PD0 = 0 ; For compatibility |
.equ PORTD1 = 1 ; Port D Data Register bit 1 |
.equ PD1 = 1 ; For compatibility |
.equ PORTD2 = 2 ; Port D Data Register bit 2 |
.equ PD2 = 2 ; For compatibility |
.equ PORTD3 = 3 ; Port D Data Register bit 3 |
.equ PD3 = 3 ; For compatibility |
.equ PORTD4 = 4 ; Port D Data Register bit 4 |
.equ PD4 = 4 ; For compatibility |
.equ PORTD5 = 5 ; Port D Data Register bit 5 |
.equ PD5 = 5 ; For compatibility |
.equ PORTD6 = 6 ; Port D Data Register bit 6 |
.equ PD6 = 6 ; For compatibility |
.equ PORTD7 = 7 ; Port D Data Register bit 7 |
.equ PD7 = 7 ; For compatibility |
; DDRD - Port D Data Direction Register |
.equ DDD0 = 0 ; Port D Data Direction Register bit 0 |
.equ DDD1 = 1 ; Port D Data Direction Register bit 1 |
.equ DDD2 = 2 ; Port D Data Direction Register bit 2 |
.equ DDD3 = 3 ; Port D Data Direction Register bit 3 |
.equ DDD4 = 4 ; Port D Data Direction Register bit 4 |
.equ DDD5 = 5 ; Port D Data Direction Register bit 5 |
.equ DDD6 = 6 ; Port D Data Direction Register bit 6 |
.equ DDD7 = 7 ; Port D Data Direction Register bit 7 |
; PIND - Port D Input Pins |
.equ PIND0 = 0 ; Port D Input Pins bit 0 |
.equ PIND1 = 1 ; Port D Input Pins bit 1 |
.equ PIND2 = 2 ; Port D Input Pins bit 2 |
.equ PIND3 = 3 ; Port D Input Pins bit 3 |
.equ PIND4 = 4 ; Port D Input Pins bit 4 |
.equ PIND5 = 5 ; Port D Input Pins bit 5 |
.equ PIND6 = 6 ; Port D Input Pins bit 6 |
.equ PIND7 = 7 ; Port D Input Pins bit 7 |
; ***** TIMER_COUNTER_1 ************** |
; TIMSK - Timer/Counter Interrupt Mask Register |
.equ TICIE1 = 3 ; Timer/Counter1 Input Capture Interrupt Enable |
.equ OCIE1B = 5 ; Timer/Counter1 Output CompareB Match Interrupt Enable |
.equ OCIE1A = 6 ; Timer/Counter1 Output CompareA Match Interrupt Enable |
.equ TOIE1 = 7 ; Timer/Counter1 Overflow Interrupt Enable |
; TIFR - Timer/Counter Interrupt Flag register |
.equ ICF1 = 3 ; Input Capture Flag 1 |
.equ OCF1B = 5 ; Output Compare Flag 1B |
.equ OCF1A = 6 ; Output Compare Flag 1A |
.equ TOV1 = 7 ; Timer/Counter1 Overflow Flag |
; TCCR1A - Timer/Counter1 Control Register A |
.equ PWM10 = 0 ; Pulse Width Modulator Select Bit 0 |
.equ PWM11 = 1 ; Pulse Width Modulator Select Bit 1 |
.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0 |
.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1 |
.equ COM1A0 = 6 ; Compare Ouput Mode 1A, bit 0 |
.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1 |
; TCCR1B - Timer/Counter1 Control Register B |
.equ CS10 = 0 ; Clock Select1 bit 0 |
.equ CS11 = 1 ; Clock Select1 bit 1 |
.equ CS12 = 2 ; Clock Select1 bit 2 |
.equ CTC1 = 3 ; Clear Timer/Counter1 on Compare Match |
.equ ICES1 = 6 ; Input Capture 1 Edge Select |
.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler |
; ***** TIMER_COUNTER_0 ************** |
; TIMSK - Timer/Counter Interrupt Mask Register |
.equ TOIE0 = 1 ; Timer/Counter0 Overflow Interrupt Enable |
; TIFR - Timer/Counter Interrupt Flag register |
.equ TOV0 = 1 ; Timer/Counter0 Overflow Flag |
; TCCR0 - Timer/Counter0 Control Register |
.equ CS00 = 0 ; Clock Select0 bit 0 |
.equ CS01 = 1 ; Clock Select0 bit 1 |
.equ CS02 = 2 ; Clock Select0 bit 2 |
; TCNT0 - Timer Counter 0 |
.equ TCNT00 = 0 ; Timer Counter 0 bit 0 |
.equ TCNT01 = 1 ; Timer Counter 0 bit 1 |
.equ TCNT02 = 2 ; Timer Counter 0 bit 2 |
.equ TCNT03 = 3 ; Timer Counter 0 bit 3 |
.equ TCNT04 = 4 ; Timer Counter 0 bit 4 |
.equ TCNT05 = 5 ; Timer Counter 0 bit 5 |
.equ TCNT06 = 6 ; Timer Counter 0 bit 6 |
.equ TCNT07 = 7 ; Timer Counter 0 bit 7 |
; ***** WATCHDOG ********************* |
; WDTCR - Watchdog Timer Control Register |
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 |
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 |
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 |
.equ WDE = 3 ; Watch Dog Enable |
.equ WDTOE = 4 ; RW |
.equ WDDE = WDTOE ; For compatibility |
; ***** CPU ************************** |
; SREG - Status Register |
.equ SREG_C = 0 ; Carry Flag |
.equ SREG_Z = 1 ; Zero Flag |
.equ SREG_N = 2 ; Negative Flag |
.equ SREG_V = 3 ; Two's Complement Overflow Flag |
.equ SREG_S = 4 ; Sign Bit |
.equ SREG_H = 5 ; Half Carry Flag |
.equ SREG_T = 6 ; Bit Copy Storage |
.equ SREG_I = 7 ; Global Interrupt Enable |
; MCUCR - MCU Control Register |
.equ ISC00 = 0 ; Interrupt Sense Control 0 bit 0 |
.equ ISC01 = 1 ; Interrupt Sense Control 0 bit 1 |
.equ ISC10 = 2 ; Interrupt Sense Control 1 bit 0 |
.equ ISC11 = 3 ; Interrupt Sense Control 1 bit 1 |
.equ SM = 4 ; Sleep Mode |
.equ SE = 5 ; Sleep Enable |
.equ SRW = 6 ; External SRAM Wait State |
.equ SRE = 7 ; External SRAM Enable |
; ***** EEPROM *********************** |
; EEAR - EEPROM Read/Write Access |
.equ EEAR0 = 0 ; EEPROM Read/Write Access bit 0 |
.equ EEAR1 = 1 ; EEPROM Read/Write Access bit 1 |
.equ EEAR2 = 2 ; EEPROM Read/Write Access bit 2 |
.equ EEAR3 = 3 ; EEPROM Read/Write Access bit 3 |
.equ EEAR4 = 4 ; EEPROM Read/Write Access bit 4 |
.equ EEAR5 = 5 ; EEPROM Read/Write Access bit 5 |
.equ EEAR6 = 6 ; EEPROM Read/Write Access bit 6 |
.equ EEAR7 = 7 ; EEPROM Read/Write Access bit 7 |
; EEDR - EEPROM Data Register |
.equ EEDR0 = 0 ; EEPROM Data Register bit 0 |
.equ EEDR1 = 1 ; EEPROM Data Register bit 1 |
.equ EEDR2 = 2 ; EEPROM Data Register bit 2 |
.equ EEDR3 = 3 ; EEPROM Data Register bit 3 |
.equ EEDR4 = 4 ; EEPROM Data Register bit 4 |
.equ EEDR5 = 5 ; EEPROM Data Register bit 5 |
.equ EEDR6 = 6 ; EEPROM Data Register bit 6 |
.equ EEDR7 = 7 ; EEPROM Data Register bit 7 |
; EECR - EEPROM Control Register |
.equ EERE = 0 ; EEPROM Read Enable |
.equ EEWE = 1 ; EEPROM Write Enable |
.equ EEMWE = 2 ; EEPROM Master Write Enable |
; ***** LOCKSBITS ******************************************************** |
.equ LB1 = 0 ; Lockbit |
.equ LB2 = 1 ; Lockbit |
; ***** FUSES ************************************************************ |
; LOW fuse bits |
.equ SPIEN = 1 ; Serial Program Downloading Enabled |
.equ FSTRT = 2 ; Short Start-up time selected |
; ***** CPU REGISTER DEFINITIONS ***************************************** |
.def XH = r27 |
.def XL = r26 |
.def YH = r29 |
.def YL = r28 |
.def ZH = r31 |
.def ZL = r30 |
; ***** DATA MEMORY DECLARATIONS ***************************************** |
.equ FLASHEND = 0x07ff ; Note: Word address |
.equ IOEND = 0x003f |
.equ SRAM_START = 0x0060 |
.equ SRAM_SIZE = 256 |
.equ RAMEND = 0x015f |
.equ XRAMEND = 0xffff |
.equ E2END = 0x00ff |
.equ EEPROMEND = 0x00ff |
.equ EEADRBITS = 8 |
#pragma AVRPART MEMORY PROG_FLASH 4096 |
#pragma AVRPART MEMORY EEPROM 256 |
#pragma AVRPART MEMORY INT_SRAM SIZE 256 |
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60 |
; ***** INTERRUPT VECTORS ************************************************ |
.equ INT0addr = 0x0001 ; External Interrupt Request 0 |
.equ INT1addr = 0x0002 ; External Interrupt Request 1 |
.equ ICP1addr = 0x0003 ; Timer/Counter Capture Event |
.equ OC1Aaddr = 0x0004 ; Timer/Counter1 Compare Match A |
.equ OC1Baddr = 0x0005 ; Timer/Counter1 Compare MatchB |
.equ OVF1addr = 0x0006 ; Timer/Counter1 Overflow |
.equ OVF0addr = 0x0007 ; Timer/Counter0 Overflow |
.equ SPIaddr = 0x0008 ; Serial Transfer Complete |
.equ URXCaddr = 0x0009 ; UART, Rx Complete |
.equ UDREaddr = 0x000a ; UART Data Register Empty |
.equ UTXCaddr = 0x000b ; UART, Tx Complete |
.equ ACIaddr = 0x000c ; Analog Comparator |
.equ INT_VECTORS_SIZE = 13 ; size in words |
#pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED break |
#endif /* _4414DEF_INC_ */ |
; ***** END OF FILE ****************************************************** |
/contrib/toolchain/avra/includes/4433def.inc |
---|
0,0 → 1,522 |
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** |
;***** Created: 2005-01-11 10:30 ******* Source: AT90S4433.xml *********** |
;************************************************************************* |
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y |
;* |
;* Number : AVR000 |
;* File Name : "4433def.inc" |
;* Title : Register/Bit Definitions for the AT90S4433 |
;* Date : 2005-01-11 |
;* Version : 2.14 |
;* Support E-mail : avr@atmel.com |
;* Target MCU : AT90S4433 |
;* |
;* DESCRIPTION |
;* When including this file in the assembly program file, all I/O register |
;* names and I/O register bit names appearing in the data book can be used. |
;* In addition, the six registers forming the three data pointers X, Y and |
;* Z have been assigned names XL - ZH. Highest RAM address for Internal |
;* SRAM is also defined |
;* |
;* The Register names are represented by their hexadecimal address. |
;* |
;* The Register Bit names are represented by their bit number (0-7). |
;* |
;* Please observe the difference in using the bit names with instructions |
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" |
;* (skip if bit in register set/cleared). The following example illustrates |
;* this: |
;* |
;* in r16,PORTB ;read PORTB latch |
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) |
;* out PORTB,r16 ;output to PORTB |
;* |
;* in r16,TIFR ;read the Timer Interrupt Flag Register |
;* sbrc r16,TOV0 ;test the overflow flag (use bit#) |
;* rjmp TOV0_is_set ;jump if set |
;* ... ;otherwise do something else |
;************************************************************************* |
#ifndef _4433DEF_INC_ |
#define _4433DEF_INC_ |
#pragma partinc 0 |
; ***** SPECIFY DEVICE *************************************************** |
.device AT90S4433 |
#pragma AVRPART ADMIN PART_NAME AT90S4433 |
.equ SIGNATURE_000 = 0x1e |
.equ SIGNATURE_001 = 0x92 |
.equ SIGNATURE_002 = 0x03 |
#pragma AVRPART CORE CORE_VERSION V1 |
; ***** I/O REGISTER DEFINITIONS ***************************************** |
; NOTE: |
; Definitions marked "MEMORY MAPPED"are extended I/O ports |
; and cannot be used with IN/OUT instructions |
.equ SREG = 0x3f |
.equ SP = 0x3d |
.equ GIMSK = 0x3b |
.equ GIFR = 0x3a |
.equ TIMSK = 0x39 |
.equ TIFR = 0x38 |
.equ MCUCR = 0x35 |
.equ MCUSR = 0x34 |
.equ TCCR0 = 0x33 |
.equ TCNT0 = 0x32 |
.equ TCCR1A = 0x2f |
.equ TCCR1B = 0x2e |
.equ TCNT1H = 0x2d |
.equ TCNT1L = 0x2c |
.equ OCR1H = 0x2b |
.equ OCR1L = 0x2a |
.equ ICR1H = 0x27 |
.equ ICR1L = 0x26 |
.equ WDTCR = 0x21 |
.equ EEAR = 0x1e |
.equ EEDR = 0x1d |
.equ EECR = 0x1c |
.equ PORTB = 0x18 |
.equ DDRB = 0x17 |
.equ PINB = 0x16 |
.equ PORTC = 0x15 |
.equ DDRC = 0x14 |
.equ PINC = 0x13 |
.equ PORTD = 0x12 |
.equ DDRD = 0x11 |
.equ PIND = 0x10 |
.equ SPDR = 0x0f |
.equ SPSR = 0x0e |
.equ SPCR = 0x0d |
.equ UDR = 0x0c |
.equ UCSRA = 0x0b |
.equ UCSRB = 0x0a |
.equ UBRR = 0x09 |
.equ ACSR = 0x08 |
.equ ADMUX = 0x07 |
.equ ADCSR = 0x06 |
.equ ADCH = 0x05 |
.equ ADCL = 0x04 |
.equ UBRRHI = 0x03 |
; ***** BIT DEFINITIONS ************************************************** |
; ***** ANALOG_COMPARATOR ************ |
; ACSR - Analog Comparator Control And Status Register |
.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 |
.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 |
.equ ACIC = 2 ; Analog Comparator Input Capture Enable |
.equ ACIE = 3 ; Analog Comparator Interrupt Enable |
.equ ACI = 4 ; Analog Comparator Interrupt Flag |
.equ ACO = 5 ; Analog Compare Output |
.equ AINBG = 6 ; Analog Comparator Bandgap Select |
.equ ACD = 7 ; Analog Comparator Disable |
; ***** AD_CONVERTER ***************** |
; ADMUX - The ADC multiplexer Selection Register |
.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits |
.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits |
.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits |
.equ ADCBG = 6 ; ADC Bandgap Select |
; ADCSR - The ADC Control and Status register |
.equ ADPS0 = 0 ; ADC Prescaler Select Bits |
.equ ADPS1 = 1 ; ADC Prescaler Select Bits |
.equ ADPS2 = 2 ; ADC Prescaler Select Bits |
.equ ADIE = 3 ; ADC Interrupt Enable |
.equ ADIF = 4 ; ADC Interrupt Flag |
.equ ADFR = 5 ; ADC Free Running Select |
.equ ADSC = 6 ; ADC Start Conversion |
.equ ADEN = 7 ; ADC Enable |
; ADCH - ADC Data Register High Byte |
.equ ADC8 = 0 ; ADC Data Register High Byte Bit 0 |
.equ ADC9 = 1 ; ADC Data Register High Byte Bit 1 |
; ADCL - ADC Data Register Low Byte |
.equ ADC0 = 0 ; ADC Data Register Low Byte Bit 0 |
.equ ADC1 = 1 ; ADC Data Register Low Byte Bit 1 |
.equ ADC2 = 2 ; ADC Data Register Low Byte Bit 2 |
.equ ADC3 = 3 ; ADC Data Register Low Byte Bit 3 |
.equ ADC4 = 4 ; ADC Data Register Low Byte Bit 4 |
.equ ADC5 = 5 ; ADC Data Register Low Byte Bit 5 |
.equ ADC6 = 6 ; ADC Data Register Low Byte Bit 6 |
.equ ADC7 = 7 ; ADC Data Register Low Byte Bit 7 |
; ***** UART ************************* |
; UDR - UART I/O Data Register |
.equ UDR0 = 0 ; UART I/O Data Register bit 0 |
.equ UDR1 = 1 ; UART I/O Data Register bit 1 |
.equ UDR2 = 2 ; UART I/O Data Register bit 2 |
.equ UDR3 = 3 ; UART I/O Data Register bit 3 |
.equ UDR4 = 4 ; UART I/O Data Register bit 4 |
.equ UDR5 = 5 ; UART I/O Data Register bit 5 |
.equ UDR6 = 6 ; UART I/O Data Register bit 6 |
.equ UDR7 = 7 ; UART I/O Data Register bit 7 |
; UCSRA - UART Control and Status register A |
.equ MPCM = 0 ; Mulit-processor Communication Mode |
.equ DOR = 3 ; Data overRun |
.equ FE = 4 ; Framing Error |
.equ UDRE = 5 ; UART Data Register Empty |
.equ TXC = 6 ; UART Transmitt Complete |
.equ RXC = 7 ; UART Receive Complete |
; UCSRB - UART Control an Status register B |
.equ TXB8 = 0 ; Transmit Data Bit 8 |
.equ RXB8 = 1 ; Receive Data Bit 8 |
.equ CHR9 = 2 ; 9-bit Characters |
.equ TXEN = 3 ; Transmitter Enable |
.equ RXEN = 4 ; Receiver Enable |
.equ UDRIE = 5 ; UART Data Register Empty Interrupt Enable |
.equ TXCIE = 6 ; TX Complete Interrupt Enable |
.equ RXCIE = 7 ; RX Complete Interrupt Enable |
; UBRRHI - UART Baud Rate Register High Byte |
.equ UBRRHI0 = 0 ; UART Baud Rate Register High Byte bit 0 |
.equ UBRRHI1 = 1 ; UART Baud Rate Register High Byte bit 1 |
.equ UBRRHI2 = 2 ; UART Baud Rate Register High Byte bit 2 |
.equ UBRRHI3 = 3 ; UART Baud Rate Register High Byte bit 3 |
; UBRR - UART Baud Rate Register |
.equ UBRR0 = 0 ; UART Baud Rate Register bit 0 |
.equ UBRR1 = 1 ; UART Baud Rate Register bit 1 |
.equ UBRR2 = 2 ; UART Baud Rate Register bit 2 |
.equ UBRR3 = 3 ; UART Baud Rate Register bit 3 |
.equ UBRR4 = 4 ; UART Baud Rate Register bit 4 |
.equ UBRR5 = 5 ; UART Baud Rate Register bit 5 |
.equ UBRR6 = 6 ; UART Baud Rate Register bit 6 |
.equ UBRR7 = 7 ; UART Baud Rate Register bit 7 |
; ***** SPI ************************** |
; SPDR - SPI Data Register |
.equ SPDR0 = 0 ; SPI Data Register bit 0 |
.equ SPDR1 = 1 ; SPI Data Register bit 1 |
.equ SPDR2 = 2 ; SPI Data Register bit 2 |
.equ SPDR3 = 3 ; SPI Data Register bit 3 |
.equ SPDR4 = 4 ; SPI Data Register bit 4 |
.equ SPDR5 = 5 ; SPI Data Register bit 5 |
.equ SPDR6 = 6 ; SPI Data Register bit 6 |
.equ SPDR7 = 7 ; SPI Data Register bit 7 |
; SPSR - SPI Status Register |
.equ WCOL = 6 ; Write Collision Flag |
.equ SPIF = 7 ; SPI Interrupt Flag |
; SPCR - SPI Control Register |
.equ SPR0 = 0 ; SPI Clock Rate Select 0 |
.equ SPR1 = 1 ; SPI Clock Rate Select 1 |
.equ CPHA = 2 ; Clock Phase |
.equ CPOL = 3 ; Clock polarity |
.equ MSTR = 4 ; Master/Slave Select |
.equ DORD = 5 ; Data Order |
.equ SPE = 6 ; SPI Enable |
.equ SPIE = 7 ; SPI Interrupt Enable |
; ***** CPU ************************** |
; SREG - Status Register |
.equ SREG_C = 0 ; Carry Flag |
.equ SREG_Z = 1 ; Zero Flag |
.equ SREG_N = 2 ; Negative Flag |
.equ SREG_V = 3 ; Two's Complement Overflow Flag |
.equ SREG_S = 4 ; Sign Bit |
.equ SREG_H = 5 ; Half Carry Flag |
.equ SREG_T = 6 ; Bit Copy Storage |
.equ SREG_I = 7 ; Global Interrupt Enable |
; SP - Stack Pointer |
.equ SP0 = 0 ; Stack pointer bit 0 |
.equ SP1 = 1 ; Stack pointer bit 1 |
.equ SP2 = 2 ; Stack pointer bit 2 |
.equ SP3 = 3 ; Stack pointer bit 3 |
.equ SP4 = 4 ; Stack pointer bit 4 |
.equ SP5 = 5 ; Stack pointer bit 5 |
.equ SP6 = 6 ; Stack pointer bit 6 |
.equ SP7 = 7 ; Stack pointer bit 7 |
; MCUCR - MCU Control Register |
.equ ISC00 = 0 ; Interrupt Sense Control 0 bit 0 |
.equ ISC01 = 1 ; Interrupt Sense Control 0 bit 1 |
.equ ISC10 = 2 ; Interrupt Sense Control 1 bit 0 |
.equ ISC11 = 3 ; Interrupt Sense Control 1 bit 1 |
.equ SM = 4 ; Sleep Mode Select |
.equ SE = 5 ; Sleep Enable |
; MCUSR - |
.equ PORF = 0 ; Power-on Reset Flag |
.equ EXTRF = 1 ; External Reset Flag |
.equ BORF = 2 ; Brown-Out Reset Flag |
.equ WDRF = 3 ; Watchdog Reset Flag |
; ***** EXTERNAL_INTERRUPT *********** |
; GIMSK - General Interrupt Mask Register |
.equ INT0 = 6 ; External Interrupt Request 0 Enable |
.equ INT1 = 7 ; External Interrupt Request 1 Enable |
; GIFR - General Interrupt Flag register |
.equ INTF0 = 6 ; External Interrupt Flag 0 |
.equ INTF1 = 7 ; External Interrupt Flag 1 |
; ***** EEPROM *********************** |
; EEAR - EEPROM Read/Write Access |
.equ EEAR0 = 0 ; EEPROM Read/Write Access bit 0 |
.equ EEAR1 = 1 ; EEPROM Read/Write Access bit 1 |
.equ EEAR2 = 2 ; EEPROM Read/Write Access bit 2 |
.equ EEAR3 = 3 ; EEPROM Read/Write Access bit 3 |
.equ EEAR4 = 4 ; EEPROM Read/Write Access bit 4 |
.equ EEAR5 = 5 ; EEPROM Read/Write Access bit 5 |
.equ EEAR6 = 6 ; EEPROM Read/Write Access bit 6 |
.equ EEAR7 = 7 ; EEPROM Read/Write Access bit 7 |
; EEDR - EEPROM Data Register |
.equ EEDR0 = 0 ; EEPROM Data Register bit 0 |
.equ EEDR1 = 1 ; EEPROM Data Register bit 1 |
.equ EEDR2 = 2 ; EEPROM Data Register bit 2 |
.equ EEDR3 = 3 ; EEPROM Data Register bit 3 |
.equ EEDR4 = 4 ; EEPROM Data Register bit 4 |
.equ EEDR5 = 5 ; EEPROM Data Register bit 5 |
.equ EEDR6 = 6 ; EEPROM Data Register bit 6 |
.equ EEDR7 = 7 ; EEPROM Data Register bit 7 |
; EECR - EEPROM Control Register |
.equ EERE = 0 ; EEPROM Read Enable |
.equ EEWE = 1 ; EEPROM Write Enable |
.equ EEMWE = 2 ; EEPROM Master Write Enable |
.equ EERIE = 3 ; EEProm Ready Interrupt Enable |
; ***** PORTB ************************ |
; PORTB - Data Register, Port B |
.equ PORTB0 = 0 ; |
.equ PB0 = 0 ; For compatibility |
.equ PORTB1 = 1 ; |
.equ PB1 = 1 ; For compatibility |
.equ PORTB2 = 2 ; |
.equ PB2 = 2 ; For compatibility |
.equ PORTB3 = 3 ; |
.equ PB3 = 3 ; For compatibility |
.equ PORTB4 = 4 ; |
.equ PB4 = 4 ; For compatibility |
.equ PORTB5 = 5 ; |
.equ PB5 = 5 ; For compatibility |
; DDRB - Data Direction Register, Port B |
.equ DDB0 = 0 ; |
.equ DDB1 = 1 ; |
.equ DDB2 = 2 ; |
.equ DDB3 = 3 ; |
.equ DDB4 = 4 ; |
.equ DDB5 = 5 ; |
; PINB - Input Pins, Port B |
.equ PINB0 = 0 ; |
.equ PINB1 = 1 ; |
.equ PINB2 = 2 ; |
.equ PINB3 = 3 ; |
.equ PINB4 = 4 ; |
.equ PINB5 = 5 ; |
; ***** PORTC ************************ |
; PORTC - Port C Data Register |
.equ PORTC0 = 0 ; Port C Data Register bit 0 |
.equ PC0 = 0 ; For compatibility |
.equ PORTC1 = 1 ; Port C Data Register bit 1 |
.equ PC1 = 1 ; For compatibility |
.equ PORTC2 = 2 ; Port C Data Register bit 2 |
.equ PC2 = 2 ; For compatibility |
.equ PORTC3 = 3 ; Port C Data Register bit 3 |
.equ PC3 = 3 ; For compatibility |
.equ PORTC4 = 4 ; Port C Data Register bit 4 |
.equ PC4 = 4 ; For compatibility |
.equ PORTC5 = 5 ; Port C Data Register bit 5 |
.equ PC5 = 5 ; For compatibility |
; DDRC - Port C Data Direction Register |
.equ DDC0 = 0 ; Port C Data Direction Register bit 0 |
.equ DDC1 = 1 ; Port C Data Direction Register bit 1 |
.equ DDC2 = 2 ; Port C Data Direction Register bit 2 |
.equ DDC3 = 3 ; Port C Data Direction Register bit 3 |
.equ DDC4 = 4 ; Port C Data Direction Register bit 4 |
.equ DDC5 = 5 ; Port C Data Direction Register bit 5 |
; PINC - Port C Input Pins |
.equ PINC0 = 0 ; Port C Input Pins bit 0 |
.equ PINC1 = 1 ; Port C Input Pins bit 1 |
.equ PINC2 = 2 ; Port C Input Pins bit 2 |
.equ PINC3 = 3 ; Port C Input Pins bit 3 |
.equ PINC4 = 4 ; Port C Input Pins bit 4 |
.equ PINC5 = 5 ; Port C Input Pins bit 5 |
; ***** PORTD ************************ |
; PORTD - Port D Data Register |
.equ PORTD0 = 0 ; Port D Data Register bit 0 |
.equ PD0 = 0 ; For compatibility |
.equ PORTD1 = 1 ; Port D Data Register bit 1 |
.equ PD1 = 1 ; For compatibility |
.equ PORTD2 = 2 ; Port D Data Register bit 2 |
.equ PD2 = 2 ; For compatibility |
.equ PORTD3 = 3 ; Port D Data Register bit 3 |
.equ PD3 = 3 ; For compatibility |
.equ PORTD4 = 4 ; Port D Data Register bit 4 |
.equ PD4 = 4 ; For compatibility |
.equ PORTD5 = 5 ; Port D Data Register bit 5 |
.equ PD5 = 5 ; For compatibility |
.equ PORTD6 = 6 ; Port D Data Register bit 6 |
.equ PD6 = 6 ; For compatibility |
.equ PORTD7 = 7 ; Port D Data Register bit 7 |
.equ PD7 = 7 ; For compatibility |
; DDRD - Port D Data Direction Register |
.equ DDD0 = 0 ; Port D Data Direction Register bit 0 |
.equ DDD1 = 1 ; Port D Data Direction Register bit 1 |
.equ DDD2 = 2 ; Port D Data Direction Register bit 2 |
.equ DDD3 = 3 ; Port D Data Direction Register bit 3 |
.equ DDD4 = 4 ; Port D Data Direction Register bit 4 |
.equ DDD5 = 5 ; Port D Data Direction Register bit 5 |
.equ DDD6 = 6 ; Port D Data Direction Register bit 6 |
.equ DDD7 = 7 ; Port D Data Direction Register bit 7 |
; PIND - Port D Input Pins |
.equ PIND0 = 0 ; Port D Input Pins bit 0 |
.equ PIND1 = 1 ; Port D Input Pins bit 1 |
.equ PIND2 = 2 ; Port D Input Pins bit 2 |
.equ PIND3 = 3 ; Port D Input Pins bit 3 |
.equ PIND4 = 4 ; Port D Input Pins bit 4 |
.equ PIND5 = 5 ; Port D Input Pins bit 5 |
.equ PIND6 = 6 ; Port D Input Pins bit 6 |
.equ PIND7 = 7 ; Port D Input Pins bit 7 |
; ***** TIMER_COUNTER_0 ************** |
; TIMSK - Timer/Counter Interrupt Mask Register |
.equ TOIE0 = 1 ; Timer/Counter0 Overflow Interrupt Enable |
; TIFR - Timer/Counter Interrupt Flag register |
.equ TOV0 = 1 ; Timer/Counter0 Overflow Flag |
; TCCR0 - Timer/Counter0 Control Register |
.equ CS00 = 0 ; Clock Select0 bit 0 |
.equ CS01 = 1 ; Clock Select0 bit 1 |
.equ CS02 = 2 ; Clock Select0 bit 2 |
; TCNT0 - Timer Counter 0 |
.equ TCNT00 = 0 ; Timer Counter 0 bit 0 |
.equ TCNT01 = 1 ; Timer Counter 0 bit 1 |
.equ TCNT02 = 2 ; Timer Counter 0 bit 2 |
.equ TCNT03 = 3 ; Timer Counter 0 bit 3 |
.equ TCNT04 = 4 ; Timer Counter 0 bit 4 |
.equ TCNT05 = 5 ; Timer Counter 0 bit 5 |
.equ TCNT06 = 6 ; Timer Counter 0 bit 6 |
.equ TCNT07 = 7 ; Timer Counter 0 bit 7 |
; ***** TIMER_COUNTER_1 ************** |
; TIMSK - Timer/Counter Interrupt Mask Register |
.equ TICIE1 = 3 ; Timer/Counter1 Input Capture Interrupt Enable |
.equ OCIE1 = 6 ; Timer/Counter1 Output Compare Match Interrupt Enable |
.equ TOIE1 = 7 ; Timer/Counter1 Overflow Interrupt Enable |
; TIFR - Timer/Counter Interrupt Flag register |
.equ ICF1 = 3 ; Input Capture Flag 1 |
.equ OCF1 = 6 ; Output Compare Flag 1 |
.equ TOV1 = 7 ; Timer/Counter1 Overflow Flag |
; TCCR1A - Timer/Counter1 Control Register A |
.equ PWM10 = 0 ; Pulse Width Modulator Select Bit 0 |
.equ PWM11 = 1 ; Pulse Width Modulator Select Bit 1 |
.equ COM10 = 6 ; Compare Ouput Mode 1, bit 0 |
.equ COM11 = 7 ; Compare Output Mode 1, bit 1 |
; TCCR1B - Timer/Counter1 Control Register B |
.equ CS10 = 0 ; Clock Select1 bit 0 |
.equ CS11 = 1 ; Clock Select1 bit 1 |
.equ CS12 = 2 ; Clock Select1 bit 2 |
.equ CTC1 = 3 ; Clear Timer/Counter1 on Compare Match |
.equ ICES1 = 6 ; Input Capture 1 Edge Select |
.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler |
; ***** WATCHDOG ********************* |
; WDTCR - Watchdog Timer Control Register |
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 |
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 |
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 |
.equ WDE = 3 ; Watch Dog Enable |
.equ WDTOE = 4 ; RW |
.equ WDDE = WDTOE ; For compatibility |
; ***** LOCKSBITS ******************************************************** |
.equ LB1 = 0 ; Lockbit |
.equ LB2 = 1 ; Lockbit |
; ***** FUSES ************************************************************ |
; LOW fuse bits |
; ***** CPU REGISTER DEFINITIONS ***************************************** |
.def XH = r27 |
.def XL = r26 |
.def YH = r29 |
.def YL = r28 |
.def ZH = r31 |
.def ZL = r30 |
; ***** DATA MEMORY DECLARATIONS ***************************************** |
.equ FLASHEND = 0x07ff ; Note: Word address |
.equ IOEND = 0x003f |
.equ SRAM_START = 0x0060 |
.equ SRAM_SIZE = 128 |
.equ RAMEND = 0x00df |
.equ XRAMEND = 0x0000 |
.equ E2END = 0x00ff |
.equ EEPROMEND = 0x00ff |
.equ EEADRBITS = 8 |
#pragma AVRPART MEMORY PROG_FLASH 4096 |
#pragma AVRPART MEMORY EEPROM 256 |
#pragma AVRPART MEMORY INT_SRAM SIZE 128 |
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60 |
; ***** INTERRUPT VECTORS ************************************************ |
.equ INT0addr = 0x0001 ; External Interrupt 0 |
.equ INT1addr = 0x0002 ; External Interrupt 1 |
.equ ICP1addr = 0x0003 ; Timer/Counter Capture Event |
.equ OC1addr = 0x0004 ; Timer/Counter1 Compare Match |
.equ OVF1addr = 0x0005 ; Timer/Counter1 Overflow |
.equ OVF0addr = 0x0006 ; Timer/Counter0 Overflow |
.equ SPIaddr = 0x0007 ; Serial Transfer Complete |
.equ URXCaddr = 0x0008 ; UART, Rx Complete |
.equ UDREaddr = 0x0009 ; UART Data Register Empty |
.equ UTXCaddr = 0x000a ; UART, Tx Complete |
.equ ADCCaddr = 0x000b ; ADC Conversion Complete |
.equ ERDYaddr = 0x000c ; EEPROM Ready |
.equ ACIaddr = 0x000d ; Analog Comparator |
.equ INT_VECTORS_SIZE = 14 ; size in words |
#pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED break |
#endif /* _4433DEF_INC_ */ |
; ***** END OF FILE ****************************************************** |
/contrib/toolchain/avra/includes/4434def.inc |
---|
0,0 → 1,613 |
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** |
;***** Created: 2005-01-11 10:30 ******* Source: AT90S4434.xml *********** |
;************************************************************************* |
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y |
;* |
;* Number : AVR000 |
;* File Name : "4434def.inc" |
;* Title : Register/Bit Definitions for the AT90S4434 |
;* Date : 2005-01-11 |
;* Version : 2.14 |
;* Support E-mail : avr@atmel.com |
;* Target MCU : AT90S4434 |
;* |
;* DESCRIPTION |
;* When including this file in the assembly program file, all I/O register |
;* names and I/O register bit names appearing in the data book can be used. |
;* In addition, the six registers forming the three data pointers X, Y and |
;* Z have been assigned names XL - ZH. Highest RAM address for Internal |
;* SRAM is also defined |
;* |
;* The Register names are represented by their hexadecimal address. |
;* |
;* The Register Bit names are represented by their bit number (0-7). |
;* |
;* Please observe the difference in using the bit names with instructions |
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" |
;* (skip if bit in register set/cleared). The following example illustrates |
;* this: |
;* |
;* in r16,PORTB ;read PORTB latch |
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) |
;* out PORTB,r16 ;output to PORTB |
;* |
;* in r16,TIFR ;read the Timer Interrupt Flag Register |
;* sbrc r16,TOV0 ;test the overflow flag (use bit#) |
;* rjmp TOV0_is_set ;jump if set |
;* ... ;otherwise do something else |
;************************************************************************* |
#ifndef _4434DEF_INC_ |
#define _4434DEF_INC_ |
#pragma partinc 0 |
; ***** SPECIFY DEVICE *************************************************** |
.device AT90S4434 |
#pragma AVRPART ADMIN PART_NAME AT90S4434 |
.equ SIGNATURE_000 = 0x1e |
.equ SIGNATURE_001 = 0x93 |
.equ SIGNATURE_002 = 0x03 |
#pragma AVRPART CORE CORE_VERSION V1 |
; ***** I/O REGISTER DEFINITIONS ***************************************** |
; NOTE: |
; Definitions marked "MEMORY MAPPED"are extended I/O ports |
; and cannot be used with IN/OUT instructions |
.equ SREG = 0x3f |
.equ SPH = 0x3e |
.equ SPL = 0x3d |
.equ GIMSK = 0x3b |
.equ GIFR = 0x3a |
.equ TIMSK = 0x39 |
.equ TIFR = 0x38 |
.equ MCUCR = 0x35 |
.equ MCUSR = 0x34 |
.equ TCCR0 = 0x33 |
.equ TCNT0 = 0x32 |
.equ TCCR1A = 0x2f |
.equ TCCR1B = 0x2e |
.equ TCNT1H = 0x2d |
.equ TCNT1L = 0x2c |
.equ OCR1AH = 0x2b |
.equ OCR1AL = 0x2a |
.equ OCR1BH = 0x29 |
.equ OCR1BL = 0x28 |
.equ ICR1H = 0x27 |
.equ ICR1L = 0x26 |
.equ TCCR2 = 0x25 |
.equ TCNT2 = 0x24 |
.equ OCR2 = 0x23 |
.equ ASSR = 0x22 |
.equ WDTCR = 0x21 |
.equ EEARH = 0x1f |
.equ EEARL = 0x1e |
.equ EEDR = 0x1d |
.equ EECR = 0x1c |
.equ PORTA = 0x1b |
.equ DDRA = 0x1a |
.equ PINA = 0x19 |
.equ PORTB = 0x18 |
.equ DDRB = 0x17 |
.equ PINB = 0x16 |
.equ PORTC = 0x15 |
.equ DDRC = 0x14 |
.equ PINC = 0x13 |
.equ PORTD = 0x12 |
.equ DDRD = 0x11 |
.equ PIND = 0x10 |
.equ SPDR = 0x0f |
.equ SPSR = 0x0e |
.equ SPCR = 0x0d |
.equ UDR = 0x0c |
.equ USR = 0x0b |
.equ UCR = 0x0a |
.equ UBRR = 0x09 |
.equ ACSR = 0x08 |
.equ ADMUX = 0x07 |
.equ ADCSR = 0x06 |
.equ ADCH = 0x05 |
.equ ADCL = 0x04 |
; ***** BIT DEFINITIONS ************************************************** |
; ***** TIMER_COUNTER_0 ************** |
; TIMSK - Timer/Counter Interrupt Mask Register |
.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable |
; TIFR - Timer/Counter Interrupt Flag register |
.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag |
; TCCR0 - Timer/Counter0 Control Register |
.equ CS00 = 0 ; Clock Select0 bit 0 |
.equ CS01 = 1 ; Clock Select0 bit 1 |
.equ CS02 = 2 ; Clock Select0 bit 2 |
; TCNT0 - Timer Counter 0 |
.equ TCNT00 = 0 ; Timer Counter 0 bit 0 |
.equ TCNT01 = 1 ; Timer Counter 0 bit 1 |
.equ TCNT02 = 2 ; Timer Counter 0 bit 2 |
.equ TCNT03 = 3 ; Timer Counter 0 bit 3 |
.equ TCNT04 = 4 ; Timer Counter 0 bit 4 |
.equ TCNT05 = 5 ; Timer Counter 0 bit 5 |
.equ TCNT06 = 6 ; Timer Counter 0 bit 6 |
.equ TCNT07 = 7 ; Timer Counter 0 bit 7 |
; ***** TIMER_COUNTER_1 ************** |
; TIMSK - Timer/Counter Interrupt Mask Register |
.equ TOIE1 = 2 ; Timer/Counter1 Overflow Interrupt Enable |
.equ OCIE1B = 3 ; Timer/Counter1 Output CompareB Match Interrupt Enable |
.equ OCIE1A = 4 ; Timer/Counter1 Output CompareA Match Interrupt Enable |
.equ TICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable |
; TIFR - Timer/Counter Interrupt Flag register |
.equ TOV1 = 2 ; Timer/Counter1 Overflow Flag |
.equ OCF1B = 3 ; Output Compare Flag 1B |
.equ OCF1A = 4 ; Output Compare Flag 1A |
.equ ICF1 = 5 ; Input Capture Flag 1 |
; TCCR1A - Timer/Counter1 Control Register A |
.equ PWM10 = 0 ; Pulse Width Modulator Select Bit 0 |
.equ PWM11 = 1 ; Pulse Width Modulator Select Bit 1 |
.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0 |
.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1 |
.equ COM1A0 = 6 ; Compare Ouput Mode 1A, bit 0 |
.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1 |
; TCCR1B - Timer/Counter1 Control Register B |
.equ CS10 = 0 ; Clock Select1 bit 0 |
.equ CS11 = 1 ; Clock Select1 bit 1 |
.equ CS12 = 2 ; Clock Select1 bit 2 |
.equ CTC1 = 3 ; Clear Timer/Counter1 on Compare Match |
.equ ICES1 = 6 ; Input Capture 1 Edge Select |
.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler |
; ***** TIMER_COUNTER_2 ************** |
; TCCR2 - Timer/Counter Control Register |
.equ CS20 = 0 ; Clock Select |
.equ CS21 = 1 ; Clock Select |
.equ CS22 = 2 ; Clock Select |
.equ CTC2 = 3 ; Clear Timer/Counter Compare Match |
.equ COM20 = 4 ; Compare Match Output Mode |
.equ COM21 = 5 ; Compare Match Output Mode |
.equ PWM2 = 6 ; Pulse Width Modulator Enable |
; TCNT2 - Timer/Counter Register |
.equ TCNT2_0 = 0 ; Timer/Counter Register Bit 0 |
.equ TCNT2_1 = 1 ; Timer/Counter Register Bit 1 |
.equ TCNT2_2 = 2 ; Timer/Counter Register Bit 2 |
.equ TCNT2_3 = 3 ; Timer/Counter Register Bit 3 |
.equ TCNT2_4 = 4 ; Timer/Counter Register Bit 4 |
.equ TCNT2_5 = 5 ; Timer/Counter Register Bit 5 |
.equ TCNT2_6 = 6 ; Timer/Counter Register Bit 6 |
.equ TCNT2_7 = 7 ; Timer/Counter Register Bit 7 |
; OCR2 - Output Compare Register |
.equ OCR2_0 = 0 ; Output Compare Register Bit 0 |
.equ OCR2_1 = 1 ; Output Compare Register Bit 1 |
.equ OCR2_2 = 2 ; Output Compare Register Bit 2 |
.equ OCR2_3 = 3 ; Output Compare Register Bit 3 |
.equ OCR2_4 = 4 ; Output Compare Register Bit 4 |
.equ OCR2_5 = 5 ; Output Compare Register Bit 5 |
.equ OCR2_6 = 6 ; Output Compare Register Bit 6 |
.equ OCR2_7 = 7 ; Output Compare Register Bit 7 |
; ASSR - Asynchronous Status Register |
.equ TCR2UB = 0 ; Timer/Counter Control Register2 Update Busy |
.equ OCR2UB = 1 ; Output Compare Register2 Update Busy |
.equ TCN2UB = 2 ; Timer/Counter2 Update Busy |
.equ AS2 = 3 ; Asynchronous Timer 2 |
; TIMSK - Timer/Counter Interrupt Mask Register |
.equ TOIE2 = 6 ; Timer/Counter2 Overflow Interrupt Enable |
.equ OCIE2 = 7 ; Timer/Counter2 Output Compare Match Interrupt Enable |
; TIFR - Timer/Counter Interrupt Flag Register |
.equ TOV2 = 6 ; Timer/Counter2 Overflow Flag |
.equ OCF2 = 7 ; Output Compare Flag 2 |
; ***** UART ************************* |
; UDR - UART I/O Data Register |
.equ UDR0 = 0 ; UART I/O Data Register bit 0 |
.equ UDR1 = 1 ; UART I/O Data Register bit 1 |
.equ UDR2 = 2 ; UART I/O Data Register bit 2 |
.equ UDR3 = 3 ; UART I/O Data Register bit 3 |
.equ UDR4 = 4 ; UART I/O Data Register bit 4 |
.equ UDR5 = 5 ; UART I/O Data Register bit 5 |
.equ UDR6 = 6 ; UART I/O Data Register bit 6 |
.equ UDR7 = 7 ; UART I/O Data Register bit 7 |
; USR - UART Status Register |
.equ DOR = 3 ; Data overRun |
.equ FE = 4 ; Framing Error |
.equ UDRE = 5 ; UART Data Register Empty |
.equ TXC = 6 ; UART Transmit Complete |
.equ RXC = 7 ; UART Receive Complete |
; UCR - UART Control Register |
.equ TXB8 = 0 ; Transmit Data Bit 8 |
.equ RXB8 = 1 ; Receive Data Bit 8 |
.equ CHR9 = 2 ; 9-bit Characters |
.equ TXEN = 3 ; Transmitter Enable |
.equ RXEN = 4 ; Receiver Enable |
.equ UDRIE = 5 ; UART Data Register Empty Interrupt Enable |
.equ TXCIE = 6 ; TX Complete Interrupt Enable |
.equ RXCIE = 7 ; RX Complete Interrupt Enable |
; UBRR - UART BAUD Rate Register |
.equ UBRR0 = 0 ; UART Baud Rate Register bit 0 |
.equ UBRR1 = 1 ; UART Baud Rate Register bit 1 |
.equ UBRR2 = 2 ; UART Baud Rate Register bit 2 |
.equ UBRR3 = 3 ; UART Baud Rate Register bit 3 |
.equ UBRR4 = 4 ; UART Baud Rate Register bit 4 |
.equ UBRR5 = 5 ; UART Baud Rate Register bit 5 |
.equ UBRR6 = 6 ; UART Baud Rate Register bit 6 |
.equ UBRR7 = 7 ; UART Baud Rate Register bit 7 |
; ***** SPI ************************** |
; SPDR - SPI Data Register |
.equ SPDR0 = 0 ; SPI Data Register bit 0 |
.equ SPDR1 = 1 ; SPI Data Register bit 1 |
.equ SPDR2 = 2 ; SPI Data Register bit 2 |
.equ SPDR3 = 3 ; SPI Data Register bit 3 |
.equ SPDR4 = 4 ; SPI Data Register bit 4 |
.equ SPDR5 = 5 ; SPI Data Register bit 5 |
.equ SPDR6 = 6 ; SPI Data Register bit 6 |
.equ SPDR7 = 7 ; SPI Data Register bit 7 |
; SPSR - SPI Status Register |
.equ WCOL = 6 ; Write Collision Flag |
.equ SPIF = 7 ; SPI Interrupt Flag |
; SPCR - SPI Control Register |
.equ SPR0 = 0 ; SPI Clock Rate Select 0 |
.equ SPR1 = 1 ; SPI Clock Rate Select 1 |
.equ CPHA = 2 ; Clock Phase |
.equ CPOL = 3 ; Clock polarity |
.equ MSTR = 4 ; Master/Slave Select |
.equ DORD = 5 ; Data Order |
.equ SPE = 6 ; SPI Enable |
.equ SPIE = 7 ; SPI Interrupt Enable |
; ***** PORTA ************************ |
; PORTA - Port A Data Register |
.equ PORTA0 = 0 ; Port A Data Register bit 0 |
.equ PA0 = 0 ; For compatibility |
.equ PORTA1 = 1 ; Port A Data Register bit 1 |
.equ PA1 = 1 ; For compatibility |
.equ PORTA2 = 2 ; Port A Data Register bit 2 |
.equ PA2 = 2 ; For compatibility |
.equ PORTA3 = 3 ; Port A Data Register bit 3 |
.equ PA3 = 3 ; For compatibility |
.equ PORTA4 = 4 ; Port A Data Register bit 4 |
.equ PA4 = 4 ; For compatibility |
.equ PORTA5 = 5 ; Port A Data Register bit 5 |
.equ PA5 = 5 ; For compatibility |
.equ PORTA6 = 6 ; Port A Data Register bit 6 |
.equ PA6 = 6 ; For compatibility |
.equ PORTA7 = 7 ; Port A Data Register bit 7 |
.equ PA7 = 7 ; For compatibility |
; DDRA - Port A Data Direction Register |
.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0 |
.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1 |
.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2 |
.equ DDA3 = 3 ; Data Direction Register, Port A, bit 3 |
.equ DDA4 = 4 ; Data Direction Register, Port A, bit 4 |
.equ DDA5 = 5 ; Data Direction Register, Port A, bit 5 |
.equ DDA6 = 6 ; Data Direction Register, Port A, bit 6 |
.equ DDA7 = 7 ; Data Direction Register, Port A, bit 7 |
; PINA - Port A Input Pins |
.equ PINA0 = 0 ; Input Pins, Port A bit 0 |
.equ PINA1 = 1 ; Input Pins, Port A bit 1 |
.equ PINA2 = 2 ; Input Pins, Port A bit 2 |
.equ PINA3 = 3 ; Input Pins, Port A bit 3 |
.equ PINA4 = 4 ; Input Pins, Port A bit 4 |
.equ PINA5 = 5 ; Input Pins, Port A bit 5 |
.equ PINA6 = 6 ; Input Pins, Port A bit 6 |
.equ PINA7 = 7 ; Input Pins, Port A bit 7 |
; ***** PORTB ************************ |
; PORTB - Port B Data Register |
.equ PORTB0 = 0 ; Port B Data Register bit 0 |
.equ PB0 = 0 ; For compatibility |
.equ PORTB1 = 1 ; Port B Data Register bit 1 |
.equ PB1 = 1 ; For compatibility |
.equ PORTB2 = 2 ; Port B Data Register bit 2 |
.equ PB2 = 2 ; For compatibility |
.equ PORTB3 = 3 ; Port B Data Register bit 3 |
.equ PB3 = 3 ; For compatibility |
.equ PORTB4 = 4 ; Port B Data Register bit 4 |
.equ PB4 = 4 ; For compatibility |
.equ PORTB5 = 5 ; Port B Data Register bit 5 |
.equ PB5 = 5 ; For compatibility |
.equ PORTB6 = 6 ; Port B Data Register bit 6 |
.equ PB6 = 6 ; For compatibility |
.equ PORTB7 = 7 ; Port B Data Register bit 7 |
.equ PB7 = 7 ; For compatibility |
; DDRB - Port B Data Direction Register |
.equ DDB0 = 0 ; Port B Data Direction Register bit 0 |
.equ DDB1 = 1 ; Port B Data Direction Register bit 1 |
.equ DDB2 = 2 ; Port B Data Direction Register bit 2 |
.equ DDB3 = 3 ; Port B Data Direction Register bit 3 |
.equ DDB4 = 4 ; Port B Data Direction Register bit 4 |
.equ DDB5 = 5 ; Port B Data Direction Register bit 5 |
.equ DDB6 = 6 ; Port B Data Direction Register bit 6 |
.equ DDB7 = 7 ; Port B Data Direction Register bit 7 |
; PINB - Port B Input Pins |
.equ PINB0 = 0 ; Port B Input Pins bit 0 |
.equ PINB1 = 1 ; Port B Input Pins bit 1 |
.equ PINB2 = 2 ; Port B Input Pins bit 2 |
.equ PINB3 = 3 ; Port B Input Pins bit 3 |
.equ PINB4 = 4 ; Port B Input Pins bit 4 |
.equ PINB5 = 5 ; Port B Input Pins bit 5 |
.equ PINB6 = 6 ; Port B Input Pins bit 6 |
.equ PINB7 = 7 ; Port B Input Pins bit 7 |
; ***** PORTC ************************ |
; PORTC - Port C Data Register |
.equ PORTC0 = 0 ; Port C Data Register bit 0 |
.equ PC0 = 0 ; For compatibility |
.equ PORTC1 = 1 ; Port C Data Register bit 1 |
.equ PC1 = 1 ; For compatibility |
.equ PORTC2 = 2 ; Port C Data Register bit 2 |
.equ PC2 = 2 ; For compatibility |
.equ PORTC3 = 3 ; Port C Data Register bit 3 |
.equ PC3 = 3 ; For compatibility |
.equ PORTC4 = 4 ; Port C Data Register bit 4 |
.equ PC4 = 4 ; For compatibility |
.equ PORTC5 = 5 ; Port C Data Register bit 5 |
.equ PC5 = 5 ; For compatibility |
.equ PORTC6 = 6 ; Port C Data Register bit 6 |
.equ PC6 = 6 ; For compatibility |
.equ PORTC7 = 7 ; Port C Data Register bit 7 |
.equ PC7 = 7 ; For compatibility |
; DDRC - Port C Data Direction Register |
.equ DDC0 = 0 ; Port C Data Direction Register bit 0 |
.equ DDC1 = 1 ; Port C Data Direction Register bit 1 |
.equ DDC2 = 2 ; Port C Data Direction Register bit 2 |
.equ DDC3 = 3 ; Port C Data Direction Register bit 3 |
.equ DDC4 = 4 ; Port C Data Direction Register bit 4 |
.equ DDC5 = 5 ; Port C Data Direction Register bit 5 |
.equ DDC6 = 6 ; Port C Data Direction Register bit 6 |
.equ DDC7 = 7 ; Port C Data Direction Register bit 7 |
; PINC - Port C Input Pins |
.equ PINC0 = 0 ; Port C Input Pins bit 0 |
.equ PINC1 = 1 ; Port C Input Pins bit 1 |
.equ PINC2 = 2 ; Port C Input Pins bit 2 |
.equ PINC3 = 3 ; Port C Input Pins bit 3 |
.equ PINC4 = 4 ; Port C Input Pins bit 4 |
.equ PINC5 = 5 ; Port C Input Pins bit 5 |
.equ PINC6 = 6 ; Port C Input Pins bit 6 |
.equ PINC7 = 7 ; Port C Input Pins bit 7 |
; ***** PORTD ************************ |
; PORTD - Port D Data Register |
.equ PORTD0 = 0 ; Port D Data Register bit 0 |
.equ PD0 = 0 ; For compatibility |
.equ PORTD1 = 1 ; Port D Data Register bit 1 |
.equ PD1 = 1 ; For compatibility |
.equ PORTD2 = 2 ; Port D Data Register bit 2 |
.equ PD2 = 2 ; For compatibility |
.equ PORTD3 = 3 ; Port D Data Register bit 3 |
.equ PD3 = 3 ; For compatibility |
.equ PORTD4 = 4 ; Port D Data Register bit 4 |
.equ PD4 = 4 ; For compatibility |
.equ PORTD5 = 5 ; Port D Data Register bit 5 |
.equ PD5 = 5 ; For compatibility |
.equ PORTD6 = 6 ; Port D Data Register bit 6 |
.equ PD6 = 6 ; For compatibility |
.equ PORTD7 = 7 ; Port D Data Register bit 7 |
.equ PD7 = 7 ; For compatibility |
; DDRD - Port D Data Direction Register |
.equ DDD0 = 0 ; Port D Data Direction Register bit 0 |
.equ DDD1 = 1 ; Port D Data Direction Register bit 1 |
.equ DDD2 = 2 ; Port D Data Direction Register bit 2 |
.equ DDD3 = 3 ; Port D Data Direction Register bit 3 |
.equ DDD4 = 4 ; Port D Data Direction Register bit 4 |
.equ DDD5 = 5 ; Port D Data Direction Register bit 5 |
.equ DDD6 = 6 ; Port D Data Direction Register bit 6 |
.equ DDD7 = 7 ; Port D Data Direction Register bit 7 |
; PIND - Port D Input Pins |
.equ PIND0 = 0 ; Port D Input Pins bit 0 |
.equ PIND1 = 1 ; Port D Input Pins bit 1 |
.equ PIND2 = 2 ; Port D Input Pins bit 2 |
.equ PIND3 = 3 ; Port D Input Pins bit 3 |
.equ PIND4 = 4 ; Port D Input Pins bit 4 |
.equ PIND5 = 5 ; Port D Input Pins bit 5 |
.equ PIND6 = 6 ; Port D Input Pins bit 6 |
.equ PIND7 = 7 ; Port D Input Pins bit 7 |
; ***** ANALOG_COMPARATOR ************ |
; ACSR - Analog Comparator Control And Status Register |
.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 |
.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 |
.equ ACIC = 2 ; Analog Comparator Input Capture Enable |
.equ ACIE = 3 ; Analog Comparator Interrupt Enable |
.equ ACI = 4 ; Analog Comparator Interrupt Flag |
.equ ACO = 5 ; Analog Comparator Output |
.equ ACD = 7 ; Analog Comparator Disable |
; ***** AD_CONVERTER ***************** |
; ADMUX - The ADC multiplexer Selection Register |
.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits |
.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits |
.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits |
; ADCSR - The ADC Control and Status register |
.equ ADPS0 = 0 ; ADC Prescaler Select Bits |
.equ ADPS1 = 1 ; ADC Prescaler Select Bits |
.equ ADPS2 = 2 ; ADC Prescaler Select Bits |
.equ ADIE = 3 ; ADC Interrupt Enable |
.equ ADIF = 4 ; ADC Interrupt Flag |
.equ ADFR = 5 ; ADC Free Running Select |
.equ ADSC = 6 ; ADC Start Conversion |
.equ ADEN = 7 ; ADC Enable |
; ADCH - ADC Data Register High Byte |
.equ ADC8 = 0 ; ADC Data Register High Byte Bit 0 |
.equ ADC9 = 1 ; ADC Data Register High Byte Bit 1 |
; ADCL - ADC Data Register Low Byte |
.equ ADC0 = 0 ; ADC Data Register Low Byte Bit 0 |
.equ ADC1 = 1 ; ADC Data Register Low Byte Bit 1 |
.equ ADC2 = 2 ; ADC Data Register Low Byte Bit 2 |
.equ ADC3 = 3 ; ADC Data Register Low Byte Bit 3 |
.equ ADC4 = 4 ; ADC Data Register Low Byte Bit 4 |
.equ ADC5 = 5 ; ADC Data Register Low Byte Bit 5 |
.equ ADC6 = 6 ; ADC Data Register Low Byte Bit 6 |
.equ ADC7 = 7 ; ADC Data Register Low Byte Bit 7 |
; ***** WATCHDOG ********************* |
; WDTCR - Watchdog Timer Control Register |
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 |
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 |
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 |
.equ WDE = 3 ; Watch Dog Enable |
.equ WDTOE = 4 ; RW |
.equ WDDE = WDTOE ; For compatibility |
; ***** EEPROM *********************** |
; EEDR - EEPROM Data Register |
.equ EEDR0 = 0 ; EEPROM Data Register bit 0 |
.equ EEDR1 = 1 ; EEPROM Data Register bit 1 |
.equ EEDR2 = 2 ; EEPROM Data Register bit 2 |
.equ EEDR3 = 3 ; EEPROM Data Register bit 3 |
.equ EEDR4 = 4 ; EEPROM Data Register bit 4 |
.equ EEDR5 = 5 ; EEPROM Data Register bit 5 |
.equ EEDR6 = 6 ; EEPROM Data Register bit 6 |
.equ EEDR7 = 7 ; EEPROM Data Register bit 7 |
; EECR - EEPROM Control Register |
.equ EERE = 0 ; EEPROM Read Enable |
.equ EEWE = 1 ; EEPROM Write Enable |
.equ EEMWE = 2 ; EEPROM Master Write Enable |
.equ EEWEE = EEMWE ; For compatibility |
.equ EERIE = 3 ; EEPROM Ready Interrupt Enable |
; ***** CPU ************************** |
; SREG - Status Register |
.equ SREG_C = 0 ; Carry Flag |
.equ SREG_Z = 1 ; Zero Flag |
.equ SREG_N = 2 ; Negative Flag |
.equ SREG_V = 3 ; Two's Complement Overflow Flag |
.equ SREG_S = 4 ; Sign Bit |
.equ SREG_H = 5 ; Half Carry Flag |
.equ SREG_T = 6 ; Bit Copy Storage |
.equ SREG_I = 7 ; Global Interrupt Enable |
; MCUCR - MCU Control Register |
.equ ISC00 = 0 ; Interrupt Sense Control 0 bit 0 |
.equ ISC01 = 1 ; Interrupt Sense Control 0 bit 1 |
.equ ISC10 = 2 ; Interrupt Sense Control 1 bit 0 |
.equ ISC11 = 3 ; Interrupt Sense Control 1 bit 1 |
.equ SM0 = 4 ; Sleep Mode Select 0 |
.equ SM1 = 5 ; Sleep Mode Select 1 |
.equ SE = 6 ; Sleep Enable |
; MCUSR - |
.equ PORF = 0 ; Power-on Reset Flag |
.equ EXTRF = 1 ; External Reset Flag |
; ***** EXTERNAL_INTERRUPT *********** |
; GIMSK - General Interrupt Mask Register |
.equ INT0 = 6 ; External Interrupt Request 0 Enable |
.equ INT1 = 7 ; External Interrupt Request 1 Enable |
; GIFR - General Interrupt Flag register |
.equ INTF0 = 6 ; External Interrupt Flag 0 |
.equ INTF1 = 7 ; External Interrupt Flag 1 |
; ***** LOCKSBITS ******************************************************** |
.equ LB1 = 0 ; Lockbit |
.equ LB2 = 1 ; Lockbit |
; ***** FUSES ************************************************************ |
; LOW fuse bits |
.equ SPIEN = 1 ; Serial Program Downloading Enabled |
.equ FSTRT = 2 ; Short Start-up time selected |
; ***** CPU REGISTER DEFINITIONS ***************************************** |
.def XH = r27 |
.def XL = r26 |
.def YH = r29 |
.def YL = r28 |
.def ZH = r31 |
.def ZL = r30 |
; ***** DATA MEMORY DECLARATIONS ***************************************** |
.equ FLASHEND = 0x07ff ; Note: Word address |
.equ IOEND = 0x003f |
.equ SRAM_START = 0x0060 |
.equ SRAM_SIZE = 256 |
.equ RAMEND = 0x015f |
.equ XRAMEND = 0x0000 |
.equ E2END = 0x00ff |
.equ EEPROMEND = 0x00ff |
.equ EEADRBITS = 8 |
#pragma AVRPART MEMORY PROG_FLASH 4096 |
#pragma AVRPART MEMORY EEPROM 256 |
#pragma AVRPART MEMORY INT_SRAM SIZE 256 |
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60 |
; ***** INTERRUPT VECTORS ************************************************ |
.equ INT0addr = 0x0001 ; External Interrupt 0 |
.equ INT1addr = 0x0002 ; External Interrupt 1 |
.equ OC2addr = 0x0003 ; Timer/Counter2 Compare Match |
.equ OVF2addr = 0x0004 ; Timer/Counter2 Overflow |
.equ ICP1addr = 0x0005 ; Timer/Counter1 Capture Event |
.equ OC1Aaddr = 0x0006 ; Timer/Counter1 Compare Match A |
.equ OC1Baddr = 0x0007 ; Timer/Counter1 Compare Match B |
.equ OVF1addr = 0x0008 ; Timer/Counter1 Overflow |
.equ OVF0addr = 0x0009 ; Timer/Counter0 Overflow |
.equ SPIaddr = 0x000a ; SPI Serial Transfer Complete |
.equ URXCaddr = 0x000b ; UART, RX Complete |
.equ UDREaddr = 0x000c ; UART Data Register Empty |
.equ UTXCaddr = 0x000d ; UART, TX Complete |
.equ ADCCaddr = 0x000e ; ADC Conversion Complete |
.equ ERDYaddr = 0x000f ; EEPROM Ready |
.equ ACIaddr = 0x0010 ; Analog Comparator |
.equ INT_VECTORS_SIZE = 17 ; size in words |
#pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED break |
#endif /* _4434DEF_INC_ */ |
; ***** END OF FILE ****************************************************** |
/contrib/toolchain/avra/includes/8515def.inc |
---|
0,0 → 1,519 |
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** |
;***** Created: 2005-01-11 10:30 ******* Source: AT90S8515.xml *********** |
;************************************************************************* |
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y |
;* |
;* Number : AVR000 |
;* File Name : "8515def.inc" |
;* Title : Register/Bit Definitions for the AT90S8515 |
;* Date : 2005-01-11 |
;* Version : 2.14 |
;* Support E-mail : avr@atmel.com |
;* Target MCU : AT90S8515 |
;* |
;* DESCRIPTION |
;* When including this file in the assembly program file, all I/O register |
;* names and I/O register bit names appearing in the data book can be used. |
;* In addition, the six registers forming the three data pointers X, Y and |
;* Z have been assigned names XL - ZH. Highest RAM address for Internal |
;* SRAM is also defined |
;* |
;* The Register names are represented by their hexadecimal address. |
;* |
;* The Register Bit names are represented by their bit number (0-7). |
;* |
;* Please observe the difference in using the bit names with instructions |
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" |
;* (skip if bit in register set/cleared). The following example illustrates |
;* this: |
;* |
;* in r16,PORTB ;read PORTB latch |
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) |
;* out PORTB,r16 ;output to PORTB |
;* |
;* in r16,TIFR ;read the Timer Interrupt Flag Register |
;* sbrc r16,TOV0 ;test the overflow flag (use bit#) |
;* rjmp TOV0_is_set ;jump if set |
;* ... ;otherwise do something else |
;************************************************************************* |
#ifndef _8515DEF_INC_ |
#define _8515DEF_INC_ |
#pragma partinc 0 |
; ***** SPECIFY DEVICE *************************************************** |
.device AT90S8515 |
#pragma AVRPART ADMIN PART_NAME AT90S8515 |
.equ SIGNATURE_000 = 0x1e |
.equ SIGNATURE_001 = 0x93 |
.equ SIGNATURE_002 = 0x01 |
#pragma AVRPART CORE CORE_VERSION V1 |
; ***** I/O REGISTER DEFINITIONS ***************************************** |
; NOTE: |
; Definitions marked "MEMORY MAPPED"are extended I/O ports |
; and cannot be used with IN/OUT instructions |
.equ SREG = 0x3f |
.equ SPH = 0x3e |
.equ SPL = 0x3d |
.equ GIMSK = 0x3b |
.equ GIFR = 0x3a |
.equ TIMSK = 0x39 |
.equ TIFR = 0x38 |
.equ MCUCR = 0x35 |
.equ TCCR0 = 0x33 |
.equ TCNT0 = 0x32 |
.equ TCCR1A = 0x2f |
.equ TCCR1B = 0x2e |
.equ TCNT1H = 0x2d |
.equ TCNT1L = 0x2c |
.equ OCR1AH = 0x2b |
.equ OCR1AL = 0x2a |
.equ OCR1BH = 0x29 |
.equ OCR1BL = 0x28 |
.equ ICR1H = 0x25 |
.equ ICR1L = 0x24 |
.equ WDTCR = 0x21 |
.equ EEARH = 0x1f |
.equ EEARL = 0x1e |
.equ EEDR = 0x1d |
.equ EECR = 0x1c |
.equ PORTA = 0x1b |
.equ DDRA = 0x1a |
.equ PINA = 0x19 |
.equ PORTB = 0x18 |
.equ DDRB = 0x17 |
.equ PINB = 0x16 |
.equ PORTC = 0x15 |
.equ DDRC = 0x14 |
.equ PINC = 0x13 |
.equ PORTD = 0x12 |
.equ DDRD = 0x11 |
.equ PIND = 0x10 |
.equ SPDR = 0x0f |
.equ SPSR = 0x0e |
.equ SPCR = 0x0d |
.equ UDR = 0x0c |
.equ USR = 0x0b |
.equ UCR = 0x0a |
.equ UBRR = 0x09 |
.equ ACSR = 0x08 |
; ***** BIT DEFINITIONS ************************************************** |
; ***** ANALOG_COMPARATOR ************ |
; ACSR - Analog Comparator Control And Status Register |
.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 |
.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 |
.equ ACIC = 2 ; Analog Comparator Input Capture Enable |
.equ ACIE = 3 ; Analog Comparator Interrupt Enable |
.equ ACI = 4 ; Analog Comparator Interrupt Flag |
.equ ACO = 5 ; Analog Comparator Output |
.equ ACD = 7 ; Analog Comparator Disable |
; ***** SPI ************************** |
; SPDR - SPI Data Register |
.equ SPDR0 = 0 ; SPI Data Register bit 0 |
.equ SPDR1 = 1 ; SPI Data Register bit 1 |
.equ SPDR2 = 2 ; SPI Data Register bit 2 |
.equ SPDR3 = 3 ; SPI Data Register bit 3 |
.equ SPDR4 = 4 ; SPI Data Register bit 4 |
.equ SPDR5 = 5 ; SPI Data Register bit 5 |
.equ SPDR6 = 6 ; SPI Data Register bit 6 |
.equ SPDR7 = 7 ; SPI Data Register bit 7 |
; SPSR - SPI Status Register |
.equ WCOL = 6 ; Write Collision Flag |
.equ SPIF = 7 ; SPI Interrupt Flag |
; SPCR - SPI Control Register |
.equ SPR0 = 0 ; SPI Clock Rate Select 0 |
.equ SPR1 = 1 ; SPI Clock Rate Select 1 |
.equ CPHA = 2 ; Clock Phase |
.equ CPOL = 3 ; Clock polarity |
.equ MSTR = 4 ; Master/Slave Select |
.equ DORD = 5 ; Data Order |
.equ SPE = 6 ; SPI Enable |
.equ SPIE = 7 ; SPI Interrupt Enable |
; ***** UART ************************* |
; UDR - UART I/O Data Register |
.equ UDR0 = 0 ; UART I/O Data Register bit 0 |
.equ UDR1 = 1 ; UART I/O Data Register bit 1 |
.equ UDR2 = 2 ; UART I/O Data Register bit 2 |
.equ UDR3 = 3 ; UART I/O Data Register bit 3 |
.equ UDR4 = 4 ; UART I/O Data Register bit 4 |
.equ UDR5 = 5 ; UART I/O Data Register bit 5 |
.equ UDR6 = 6 ; UART I/O Data Register bit 6 |
.equ UDR7 = 7 ; UART I/O Data Register bit 7 |
; USR - UART Status Register |
.equ DOR = 3 ; Data overRun |
.equ FE = 4 ; Framing Error |
.equ UDRE = 5 ; UART Data Register Empty |
.equ TXC = 6 ; UART Transmit Complete |
.equ RXC = 7 ; UART Receive Complete |
; UCR - UART Control Register |
.equ TXB8 = 0 ; Transmit Data Bit 8 |
.equ RXB8 = 1 ; Receive Data Bit 8 |
.equ CHR9 = 2 ; 9-bit Characters |
.equ TXEN = 3 ; Transmitter Enable |
.equ RXEN = 4 ; Receiver Enable |
.equ UDRIE = 5 ; UART Data Register Empty Interrupt Enable |
.equ TXCIE = 6 ; TX Complete Interrupt Enable |
.equ RXCIE = 7 ; RX Complete Interrupt Enable |
; UBRR - UART BAUD Rate Register |
.equ UBRR0 = 0 ; UART Baud Rate Register bit 0 |
.equ UBRR1 = 1 ; UART Baud Rate Register bit 1 |
.equ UBRR2 = 2 ; UART Baud Rate Register bit 2 |
.equ UBRR3 = 3 ; UART Baud Rate Register bit 3 |
.equ UBRR4 = 4 ; UART Baud Rate Register bit 4 |
.equ UBRR5 = 5 ; UART Baud Rate Register bit 5 |
.equ UBRR6 = 6 ; UART Baud Rate Register bit 6 |
.equ UBRR7 = 7 ; UART Baud Rate Register bit 7 |
; ***** EXTERNAL_INTERRUPT *********** |
; GIMSK - General Interrupt Mask Register |
.equ INT0 = 6 ; External Interrupt Request 0 Enable |
.equ INT1 = 7 ; External Interrupt Request 1 Enable |
; GIFR - General Interrupt Flag register |
.equ INTF0 = 6 ; External Interrupt Flag 0 |
.equ INTF1 = 7 ; External Interrupt Flag 1 |
; ***** PORTA ************************ |
; PORTA - Port A Data Register |
.equ PORTA0 = 0 ; Port A Data Register bit 0 |
.equ PA0 = 0 ; For compatibility |
.equ PORTA1 = 1 ; Port A Data Register bit 1 |
.equ PA1 = 1 ; For compatibility |
.equ PORTA2 = 2 ; Port A Data Register bit 2 |
.equ PA2 = 2 ; For compatibility |
.equ PORTA3 = 3 ; Port A Data Register bit 3 |
.equ PA3 = 3 ; For compatibility |
.equ PORTA4 = 4 ; Port A Data Register bit 4 |
.equ PA4 = 4 ; For compatibility |
.equ PORTA5 = 5 ; Port A Data Register bit 5 |
.equ PA5 = 5 ; For compatibility |
.equ PORTA6 = 6 ; Port A Data Register bit 6 |
.equ PA6 = 6 ; For compatibility |
.equ PORTA7 = 7 ; Port A Data Register bit 7 |
.equ PA7 = 7 ; For compatibility |
; DDRA - Port A Data Direction Register |
.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0 |
.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1 |
.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2 |
.equ DDA3 = 3 ; Data Direction Register, Port A, bit 3 |
.equ DDA4 = 4 ; Data Direction Register, Port A, bit 4 |
.equ DDA5 = 5 ; Data Direction Register, Port A, bit 5 |
.equ DDA6 = 6 ; Data Direction Register, Port A, bit 6 |
.equ DDA7 = 7 ; Data Direction Register, Port A, bit 7 |
; PINA - Port A Input Pins |
.equ PINA0 = 0 ; Input Pins, Port A bit 0 |
.equ PINA1 = 1 ; Input Pins, Port A bit 1 |
.equ PINA2 = 2 ; Input Pins, Port A bit 2 |
.equ PINA3 = 3 ; Input Pins, Port A bit 3 |
.equ PINA4 = 4 ; Input Pins, Port A bit 4 |
.equ PINA5 = 5 ; Input Pins, Port A bit 5 |
.equ PINA6 = 6 ; Input Pins, Port A bit 6 |
.equ PINA7 = 7 ; Input Pins, Port A bit 7 |
; ***** PORTB ************************ |
; PORTB - Port B Data Register |
.equ PORTB0 = 0 ; Port B Data Register bit 0 |
.equ PB0 = 0 ; For compatibility |
.equ PORTB1 = 1 ; Port B Data Register bit 1 |
.equ PB1 = 1 ; For compatibility |
.equ PORTB2 = 2 ; Port B Data Register bit 2 |
.equ PB2 = 2 ; For compatibility |
.equ PORTB3 = 3 ; Port B Data Register bit 3 |
.equ PB3 = 3 ; For compatibility |
.equ PORTB4 = 4 ; Port B Data Register bit 4 |
.equ PB4 = 4 ; For compatibility |
.equ PORTB5 = 5 ; Port B Data Register bit 5 |
.equ PB5 = 5 ; For compatibility |
.equ PORTB6 = 6 ; Port B Data Register bit 6 |
.equ PB6 = 6 ; For compatibility |
.equ PORTB7 = 7 ; Port B Data Register bit 7 |
.equ PB7 = 7 ; For compatibility |
; DDRB - Port B Data Direction Register |
.equ DDB0 = 0 ; Port B Data Direction Register bit 0 |
.equ DDB1 = 1 ; Port B Data Direction Register bit 1 |
.equ DDB2 = 2 ; Port B Data Direction Register bit 2 |
.equ DDB3 = 3 ; Port B Data Direction Register bit 3 |
.equ DDB4 = 4 ; Port B Data Direction Register bit 4 |
.equ DDB5 = 5 ; Port B Data Direction Register bit 5 |
.equ DDB6 = 6 ; Port B Data Direction Register bit 6 |
.equ DDB7 = 7 ; Port B Data Direction Register bit 7 |
; PINB - Port B Input Pins |
.equ PINB0 = 0 ; Port B Input Pins bit 0 |
.equ PINB1 = 1 ; Port B Input Pins bit 1 |
.equ PINB2 = 2 ; Port B Input Pins bit 2 |
.equ PINB3 = 3 ; Port B Input Pins bit 3 |
.equ PINB4 = 4 ; Port B Input Pins bit 4 |
.equ PINB5 = 5 ; Port B Input Pins bit 5 |
.equ PINB6 = 6 ; Port B Input Pins bit 6 |
.equ PINB7 = 7 ; Port B Input Pins bit 7 |
; ***** PORTC ************************ |
; PORTC - Port C Data Register |
.equ PORTC0 = 0 ; Port C Data Register bit 0 |
.equ PC0 = 0 ; For compatibility |
.equ PORTC1 = 1 ; Port C Data Register bit 1 |
.equ PC1 = 1 ; For compatibility |
.equ PORTC2 = 2 ; Port C Data Register bit 2 |
.equ PC2 = 2 ; For compatibility |
.equ PORTC3 = 3 ; Port C Data Register bit 3 |
.equ PC3 = 3 ; For compatibility |
.equ PORTC4 = 4 ; Port C Data Register bit 4 |
.equ PC4 = 4 ; For compatibility |
.equ PORTC5 = 5 ; Port C Data Register bit 5 |
.equ PC5 = 5 ; For compatibility |
.equ PORTC6 = 6 ; Port C Data Register bit 6 |
.equ PC6 = 6 ; For compatibility |
.equ PORTC7 = 7 ; Port C Data Register bit 7 |
.equ PC7 = 7 ; For compatibility |
; DDRC - Port C Data Direction Register |
.equ DDC0 = 0 ; Port C Data Direction Register bit 0 |
.equ DDC1 = 1 ; Port C Data Direction Register bit 1 |
.equ DDC2 = 2 ; Port C Data Direction Register bit 2 |
.equ DDC3 = 3 ; Port C Data Direction Register bit 3 |
.equ DDC4 = 4 ; Port C Data Direction Register bit 4 |
.equ DDC5 = 5 ; Port C Data Direction Register bit 5 |
.equ DDC6 = 6 ; Port C Data Direction Register bit 6 |
.equ DDC7 = 7 ; Port C Data Direction Register bit 7 |
; PINC - Port C Input Pins |
.equ PINC0 = 0 ; Port C Input Pins bit 0 |
.equ PINC1 = 1 ; Port C Input Pins bit 1 |
.equ PINC2 = 2 ; Port C Input Pins bit 2 |
.equ PINC3 = 3 ; Port C Input Pins bit 3 |
.equ PINC4 = 4 ; Port C Input Pins bit 4 |
.equ PINC5 = 5 ; Port C Input Pins bit 5 |
.equ PINC6 = 6 ; Port C Input Pins bit 6 |
.equ PINC7 = 7 ; Port C Input Pins bit 7 |
; ***** PORTD ************************ |
; PORTD - Port D Data Register |
.equ PORTD0 = 0 ; Port D Data Register bit 0 |
.equ PD0 = 0 ; For compatibility |
.equ PORTD1 = 1 ; Port D Data Register bit 1 |
.equ PD1 = 1 ; For compatibility |
.equ PORTD2 = 2 ; Port D Data Register bit 2 |
.equ PD2 = 2 ; For compatibility |
.equ PORTD3 = 3 ; Port D Data Register bit 3 |
.equ PD3 = 3 ; For compatibility |
.equ PORTD4 = 4 ; Port D Data Register bit 4 |
.equ PD4 = 4 ; For compatibility |
.equ PORTD5 = 5 ; Port D Data Register bit 5 |
.equ PD5 = 5 ; For compatibility |
.equ PORTD6 = 6 ; Port D Data Register bit 6 |
.equ PD6 = 6 ; For compatibility |
.equ PORTD7 = 7 ; Port D Data Register bit 7 |
.equ PD7 = 7 ; For compatibility |
; DDRD - Port D Data Direction Register |
.equ DDD0 = 0 ; Port D Data Direction Register bit 0 |
.equ DDD1 = 1 ; Port D Data Direction Register bit 1 |
.equ DDD2 = 2 ; Port D Data Direction Register bit 2 |
.equ DDD3 = 3 ; Port D Data Direction Register bit 3 |
.equ DDD4 = 4 ; Port D Data Direction Register bit 4 |
.equ DDD5 = 5 ; Port D Data Direction Register bit 5 |
.equ DDD6 = 6 ; Port D Data Direction Register bit 6 |
.equ DDD7 = 7 ; Port D Data Direction Register bit 7 |
; PIND - Port D Input Pins |
.equ PIND0 = 0 ; Port D Input Pins bit 0 |
.equ PIND1 = 1 ; Port D Input Pins bit 1 |
.equ PIND2 = 2 ; Port D Input Pins bit 2 |
.equ PIND3 = 3 ; Port D Input Pins bit 3 |
.equ PIND4 = 4 ; Port D Input Pins bit 4 |
.equ PIND5 = 5 ; Port D Input Pins bit 5 |
.equ PIND6 = 6 ; Port D Input Pins bit 6 |
.equ PIND7 = 7 ; Port D Input Pins bit 7 |
; ***** TIMER_COUNTER_1 ************** |
; TIMSK - Timer/Counter Interrupt Mask Register |
.equ TICIE1 = 3 ; Timer/Counter1 Input Capture Interrupt Enable |
.equ OCIE1B = 5 ; Timer/Counter1 Output CompareB Match Interrupt Enable |
.equ OCIE1A = 6 ; Timer/Counter1 Output CompareA Match Interrupt Enable |
.equ TOIE1 = 7 ; Timer/Counter1 Overflow Interrupt Enable |
; TIFR - Timer/Counter Interrupt Flag register |
.equ ICF1 = 3 ; Input Capture Flag 1 |
.equ OCF1B = 5 ; Output Compare Flag 1B |
.equ OCF1A = 6 ; Output Compare Flag 1A |
.equ TOV1 = 7 ; Timer/Counter1 Overflow Flag |
; TCCR1A - Timer/Counter1 Control Register A |
.equ PWM10 = 0 ; Pulse Width Modulator Select Bit 0 |
.equ PWM11 = 1 ; Pulse Width Modulator Select Bit 1 |
.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0 |
.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1 |
.equ COM1A0 = 6 ; Compare Ouput Mode 1A, bit 0 |
.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1 |
; TCCR1B - Timer/Counter1 Control Register B |
.equ CS10 = 0 ; Clock Select1 bit 0 |
.equ CS11 = 1 ; Clock Select1 bit 1 |
.equ CS12 = 2 ; Clock Select1 bit 2 |
.equ CTC1 = 3 ; Clear Timer/Counter1 on Compare Match |
.equ ICES1 = 6 ; Input Capture 1 Edge Select |
.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler |
; ***** TIMER_COUNTER_0 ************** |
; TIMSK - Timer/Counter Interrupt Mask Register |
.equ TOIE0 = 1 ; Timer/Counter0 Overflow Interrupt Enable |
; TIFR - Timer/Counter Interrupt Flag register |
.equ TOV0 = 1 ; Timer/Counter0 Overflow Flag |
; TCCR0 - Timer/Counter0 Control Register |
.equ CS00 = 0 ; Clock Select0 bit 0 |
.equ CS01 = 1 ; Clock Select0 bit 1 |
.equ CS02 = 2 ; Clock Select0 bit 2 |
; TCNT0 - Timer Counter 0 |
.equ TCNT00 = 0 ; Timer Counter 0 bit 0 |
.equ TCNT01 = 1 ; Timer Counter 0 bit 1 |
.equ TCNT02 = 2 ; Timer Counter 0 bit 2 |
.equ TCNT03 = 3 ; Timer Counter 0 bit 3 |
.equ TCNT04 = 4 ; Timer Counter 0 bit 4 |
.equ TCNT05 = 5 ; Timer Counter 0 bit 5 |
.equ TCNT06 = 6 ; Timer Counter 0 bit 6 |
.equ TCNT07 = 7 ; Timer Counter 0 bit 7 |
; ***** WATCHDOG ********************* |
; WDTCR - Watchdog Timer Control Register |
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 |
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 |
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 |
.equ WDE = 3 ; Watch Dog Enable |
.equ WDTOE = 4 ; RW |
.equ WDDE = WDTOE ; For compatibility |
; ***** CPU ************************** |
; SREG - Status Register |
.equ SREG_C = 0 ; Carry Flag |
.equ SREG_Z = 1 ; Zero Flag |
.equ SREG_N = 2 ; Negative Flag |
.equ SREG_V = 3 ; Two's Complement Overflow Flag |
.equ SREG_S = 4 ; Sign Bit |
.equ SREG_H = 5 ; Half Carry Flag |
.equ SREG_T = 6 ; Bit Copy Storage |
.equ SREG_I = 7 ; Global Interrupt Enable |
; MCUCR - MCU Control Register |
.equ ISC00 = 0 ; Interrupt Sense Control 0 bit 0 |
.equ ISC01 = 1 ; Interrupt Sense Control 0 bit 1 |
.equ ISC10 = 2 ; Interrupt Sense Control 1 bit 0 |
.equ ISC11 = 3 ; Interrupt Sense Control 1 bit 1 |
.equ SM = 4 ; Sleep Mode |
.equ SE = 5 ; Sleep Enable |
.equ SRW = 6 ; External SRAM Wait State |
.equ SRE = 7 ; External SRAM Enable |
; ***** EEPROM *********************** |
; EEDR - EEPROM Data Register |
.equ EEDR0 = 0 ; EEPROM Data Register bit 0 |
.equ EEDR1 = 1 ; EEPROM Data Register bit 1 |
.equ EEDR2 = 2 ; EEPROM Data Register bit 2 |
.equ EEDR3 = 3 ; EEPROM Data Register bit 3 |
.equ EEDR4 = 4 ; EEPROM Data Register bit 4 |
.equ EEDR5 = 5 ; EEPROM Data Register bit 5 |
.equ EEDR6 = 6 ; EEPROM Data Register bit 6 |
.equ EEDR7 = 7 ; EEPROM Data Register bit 7 |
; EECR - EEPROM Control Register |
.equ EERE = 0 ; EEPROM Read Enable |
.equ EEWE = 1 ; EEPROM Write Enable |
.equ EEMWE = 2 ; EEPROM Master Write Enable |
; ***** LOCKSBITS ******************************************************** |
.equ LB1 = 0 ; Lockbit |
.equ LB2 = 1 ; Lockbit |
; ***** FUSES ************************************************************ |
; LOW fuse bits |
.equ SPIEN = 1 ; Serial Program Downloading Enabled |
.equ FSTRT = 2 ; Short Start-up time selected |
; ***** CPU REGISTER DEFINITIONS ***************************************** |
.def XH = r27 |
.def XL = r26 |
.def YH = r29 |
.def YL = r28 |
.def ZH = r31 |
.def ZL = r30 |
; ***** DATA MEMORY DECLARATIONS ***************************************** |
.equ FLASHEND = 0x0fff ; Note: Word address |
.equ IOEND = 0x003f |
.equ SRAM_START = 0x0060 |
.equ SRAM_SIZE = 512 |
.equ RAMEND = 0x025f |
.equ XRAMEND = 0xffff |
.equ E2END = 0x01ff |
.equ EEPROMEND = 0x01ff |
.equ EEADRBITS = 9 |
#pragma AVRPART MEMORY PROG_FLASH 8192 |
#pragma AVRPART MEMORY EEPROM 512 |
#pragma AVRPART MEMORY INT_SRAM SIZE 512 |
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60 |
; ***** INTERRUPT VECTORS ************************************************ |
.equ INT0addr = 0x0001 ; External Interrupt Request 0 |
.equ INT1addr = 0x0002 ; External Interrupt Request 1 |
.equ ICP1addr = 0x0003 ; Timer/Counter Capture Event |
.equ OC1Aaddr = 0x0004 ; Timer/Counter1 Compare Match A |
.equ OC1Baddr = 0x0005 ; Timer/Counter1 Compare MatchB |
.equ OVF1addr = 0x0006 ; Timer/Counter1 Overflow |
.equ OVF0addr = 0x0007 ; Timer/Counter0 Overflow |
.equ SPIaddr = 0x0008 ; Serial Transfer Complete |
.equ URXCaddr = 0x0009 ; UART, Rx Complete |
.equ UDREaddr = 0x000a ; UART Data Register Empty |
.equ UTXCaddr = 0x000b ; UART, Tx Complete |
.equ ACIaddr = 0x000c ; Analog Comparator |
.equ INT_VECTORS_SIZE = 13 ; size in words |
#pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED break |
#endif /* _8515DEF_INC_ */ |
; ***** END OF FILE ****************************************************** |
/contrib/toolchain/avra/includes/8535def.inc |
---|
0,0 → 1,613 |
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** |
;***** Created: 2005-01-11 10:30 ******* Source: AT90S8535.xml *********** |
;************************************************************************* |
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y |
;* |
;* Number : AVR000 |
;* File Name : "8535def.inc" |
;* Title : Register/Bit Definitions for the AT90S8535 |
;* Date : 2005-01-11 |
;* Version : 2.14 |
;* Support E-mail : avr@atmel.com |
;* Target MCU : AT90S8535 |
;* |
;* DESCRIPTION |
;* When including this file in the assembly program file, all I/O register |
;* names and I/O register bit names appearing in the data book can be used. |
;* In addition, the six registers forming the three data pointers X, Y and |
;* Z have been assigned names XL - ZH. Highest RAM address for Internal |
;* SRAM is also defined |
;* |
;* The Register names are represented by their hexadecimal address. |
;* |
;* The Register Bit names are represented by their bit number (0-7). |
;* |
;* Please observe the difference in using the bit names with instructions |
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" |
;* (skip if bit in register set/cleared). The following example illustrates |
;* this: |
;* |
;* in r16,PORTB ;read PORTB latch |
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) |
;* out PORTB,r16 ;output to PORTB |
;* |
;* in r16,TIFR ;read the Timer Interrupt Flag Register |
;* sbrc r16,TOV0 ;test the overflow flag (use bit#) |
;* rjmp TOV0_is_set ;jump if set |
;* ... ;otherwise do something else |
;************************************************************************* |
#ifndef _8535DEF_INC_ |
#define _8535DEF_INC_ |
#pragma partinc 0 |
; ***** SPECIFY DEVICE *************************************************** |
.device AT90S8535 |
#pragma AVRPART ADMIN PART_NAME AT90S8535 |
.equ SIGNATURE_000 = 0x1e |
.equ SIGNATURE_001 = 0x93 |
.equ SIGNATURE_002 = 0x03 |
#pragma AVRPART CORE CORE_VERSION V1 |
; ***** I/O REGISTER DEFINITIONS ***************************************** |
; NOTE: |
; Definitions marked "MEMORY MAPPED"are extended I/O ports |
; and cannot be used with IN/OUT instructions |
.equ SREG = 0x3f |
.equ SPH = 0x3e |
.equ SPL = 0x3d |
.equ GIMSK = 0x3b |
.equ GIFR = 0x3a |
.equ TIMSK = 0x39 |
.equ TIFR = 0x38 |
.equ MCUCR = 0x35 |
.equ MCUSR = 0x34 |
.equ TCCR0 = 0x33 |
.equ TCNT0 = 0x32 |
.equ TCCR1A = 0x2f |
.equ TCCR1B = 0x2e |
.equ TCNT1H = 0x2d |
.equ TCNT1L = 0x2c |
.equ OCR1AH = 0x2b |
.equ OCR1AL = 0x2a |
.equ OCR1BH = 0x29 |
.equ OCR1BL = 0x28 |
.equ ICR1H = 0x27 |
.equ ICR1L = 0x26 |
.equ TCCR2 = 0x25 |
.equ TCNT2 = 0x24 |
.equ OCR2 = 0x23 |
.equ ASSR = 0x22 |
.equ WDTCR = 0x21 |
.equ EEARH = 0x1f |
.equ EEARL = 0x1e |
.equ EEDR = 0x1d |
.equ EECR = 0x1c |
.equ PORTA = 0x1b |
.equ DDRA = 0x1a |
.equ PINA = 0x19 |
.equ PORTB = 0x18 |
.equ DDRB = 0x17 |
.equ PINB = 0x16 |
.equ PORTC = 0x15 |
.equ DDRC = 0x14 |
.equ PINC = 0x13 |
.equ PORTD = 0x12 |
.equ DDRD = 0x11 |
.equ PIND = 0x10 |
.equ SPDR = 0x0f |
.equ SPSR = 0x0e |
.equ SPCR = 0x0d |
.equ UDR = 0x0c |
.equ USR = 0x0b |
.equ UCR = 0x0a |
.equ UBRR = 0x09 |
.equ ACSR = 0x08 |
.equ ADMUX = 0x07 |
.equ ADCSR = 0x06 |
.equ ADCH = 0x05 |
.equ ADCL = 0x04 |
; ***** BIT DEFINITIONS ************************************************** |
; ***** TIMER_COUNTER_0 ************** |
; TIMSK - Timer/Counter Interrupt Mask Register |
.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable |
; TIFR - Timer/Counter Interrupt Flag register |
.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag |
; TCCR0 - Timer/Counter0 Control Register |
.equ CS00 = 0 ; Clock Select0 bit 0 |
.equ CS01 = 1 ; Clock Select0 bit 1 |
.equ CS02 = 2 ; Clock Select0 bit 2 |
; TCNT0 - Timer Counter 0 |
.equ TCNT00 = 0 ; Timer Counter 0 bit 0 |
.equ TCNT01 = 1 ; Timer Counter 0 bit 1 |
.equ TCNT02 = 2 ; Timer Counter 0 bit 2 |
.equ TCNT03 = 3 ; Timer Counter 0 bit 3 |
.equ TCNT04 = 4 ; Timer Counter 0 bit 4 |
.equ TCNT05 = 5 ; Timer Counter 0 bit 5 |
.equ TCNT06 = 6 ; Timer Counter 0 bit 6 |
.equ TCNT07 = 7 ; Timer Counter 0 bit 7 |
; ***** TIMER_COUNTER_1 ************** |
; TIMSK - Timer/Counter Interrupt Mask Register |
.equ TOIE1 = 2 ; Timer/Counter1 Overflow Interrupt Enable |
.equ OCIE1B = 3 ; Timer/Counter1 Output CompareB Match Interrupt Enable |
.equ OCIE1A = 4 ; Timer/Counter1 Output CompareA Match Interrupt Enable |
.equ TICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable |
; TIFR - Timer/Counter Interrupt Flag register |
.equ TOV1 = 2 ; Timer/Counter1 Overflow Flag |
.equ OCF1B = 3 ; Output Compare Flag 1B |
.equ OCF1A = 4 ; Output Compare Flag 1A |
.equ ICF1 = 5 ; Input Capture Flag 1 |
; TCCR1A - Timer/Counter1 Control Register A |
.equ PWM10 = 0 ; Pulse Width Modulator Select Bit 0 |
.equ PWM11 = 1 ; Pulse Width Modulator Select Bit 1 |
.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0 |
.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1 |
.equ COM1A0 = 6 ; Compare Ouput Mode 1A, bit 0 |
.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1 |
; TCCR1B - Timer/Counter1 Control Register B |
.equ CS10 = 0 ; Clock Select1 bit 0 |
.equ CS11 = 1 ; Clock Select1 bit 1 |
.equ CS12 = 2 ; Clock Select1 bit 2 |
.equ CTC1 = 3 ; Clear Timer/Counter1 on Compare Match |
.equ ICES1 = 6 ; Input Capture 1 Edge Select |
.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler |
; ***** TIMER_COUNTER_2 ************** |
; TCCR2 - Timer/Counter Control Register |
.equ CS20 = 0 ; Clock Select |
.equ CS21 = 1 ; Clock Select |
.equ CS22 = 2 ; Clock Select |
.equ CTC2 = 3 ; Clear Timer/Counter Compare Match |
.equ COM20 = 4 ; Compare Match Output Mode |
.equ COM21 = 5 ; Compare Match Output Mode |
.equ PWM2 = 6 ; Pulse Width Modulator Enable |
; TCNT2 - Timer/Counter Register |
.equ TCNT2_0 = 0 ; Timer/Counter Register Bit 0 |
.equ TCNT2_1 = 1 ; Timer/Counter Register Bit 1 |
.equ TCNT2_2 = 2 ; Timer/Counter Register Bit 2 |
.equ TCNT2_3 = 3 ; Timer/Counter Register Bit 3 |
.equ TCNT2_4 = 4 ; Timer/Counter Register Bit 4 |
.equ TCNT2_5 = 5 ; Timer/Counter Register Bit 5 |
.equ TCNT2_6 = 6 ; Timer/Counter Register Bit 6 |
.equ TCNT2_7 = 7 ; Timer/Counter Register Bit 7 |
; OCR2 - Output Compare Register |
.equ OCR2_0 = 0 ; Output Compare Register Bit 0 |
.equ OCR2_1 = 1 ; Output Compare Register Bit 1 |
.equ OCR2_2 = 2 ; Output Compare Register Bit 2 |
.equ OCR2_3 = 3 ; Output Compare Register Bit 3 |
.equ OCR2_4 = 4 ; Output Compare Register Bit 4 |
.equ OCR2_5 = 5 ; Output Compare Register Bit 5 |
.equ OCR2_6 = 6 ; Output Compare Register Bit 6 |
.equ OCR2_7 = 7 ; Output Compare Register Bit 7 |
; ASSR - Asynchronous Status Register |
.equ TCR2UB = 0 ; Timer/Counter Control Register2 Update Busy |
.equ OCR2UB = 1 ; Output Compare Register2 Update Busy |
.equ TCN2UB = 2 ; Timer/Counter2 Update Busy |
.equ AS2 = 3 ; Asynchronous Timer 2 |
; TIMSK - Timer/Counter Interrupt Mask Register |
.equ TOIE2 = 6 ; Timer/Counter2 Overflow Interrupt Enable |
.equ OCIE2 = 7 ; Timer/Counter2 Output Compare Match Interrupt Enable |
; TIFR - Timer/Counter Interrupt Flag Register |
.equ TOV2 = 6 ; Timer/Counter2 Overflow Flag |
.equ OCF2 = 7 ; Output Compare Flag 2 |
; ***** UART ************************* |
; UDR - UART I/O Data Register |
.equ UDR0 = 0 ; UART I/O Data Register bit 0 |
.equ UDR1 = 1 ; UART I/O Data Register bit 1 |
.equ UDR2 = 2 ; UART I/O Data Register bit 2 |
.equ UDR3 = 3 ; UART I/O Data Register bit 3 |
.equ UDR4 = 4 ; UART I/O Data Register bit 4 |
.equ UDR5 = 5 ; UART I/O Data Register bit 5 |
.equ UDR6 = 6 ; UART I/O Data Register bit 6 |
.equ UDR7 = 7 ; UART I/O Data Register bit 7 |
; USR - UART Status Register |
.equ DOR = 3 ; Data overRun |
.equ FE = 4 ; Framing Error |
.equ UDRE = 5 ; UART Data Register Empty |
.equ TXC = 6 ; UART Transmit Complete |
.equ RXC = 7 ; UART Receive Complete |
; UCR - UART Control Register |
.equ TXB8 = 0 ; Transmit Data Bit 8 |
.equ RXB8 = 1 ; Receive Data Bit 8 |
.equ CHR9 = 2 ; 9-bit Characters |
.equ TXEN = 3 ; Transmitter Enable |
.equ RXEN = 4 ; Receiver Enable |
.equ UDRIE = 5 ; UART Data Register Empty Interrupt Enable |
.equ TXCIE = 6 ; TX Complete Interrupt Enable |
.equ RXCIE = 7 ; RX Complete Interrupt Enable |
; UBRR - UART BAUD Rate Register |
.equ UBRR0 = 0 ; UART Baud Rate Register bit 0 |
.equ UBRR1 = 1 ; UART Baud Rate Register bit 1 |
.equ UBRR2 = 2 ; UART Baud Rate Register bit 2 |
.equ UBRR3 = 3 ; UART Baud Rate Register bit 3 |
.equ UBRR4 = 4 ; UART Baud Rate Register bit 4 |
.equ UBRR5 = 5 ; UART Baud Rate Register bit 5 |
.equ UBRR6 = 6 ; UART Baud Rate Register bit 6 |
.equ UBRR7 = 7 ; UART Baud Rate Register bit 7 |
; ***** SPI ************************** |
; SPDR - SPI Data Register |
.equ SPDR0 = 0 ; SPI Data Register bit 0 |
.equ SPDR1 = 1 ; SPI Data Register bit 1 |
.equ SPDR2 = 2 ; SPI Data Register bit 2 |
.equ SPDR3 = 3 ; SPI Data Register bit 3 |
.equ SPDR4 = 4 ; SPI Data Register bit 4 |
.equ SPDR5 = 5 ; SPI Data Register bit 5 |
.equ SPDR6 = 6 ; SPI Data Register bit 6 |
.equ SPDR7 = 7 ; SPI Data Register bit 7 |
; SPSR - SPI Status Register |
.equ WCOL = 6 ; Write Collision Flag |
.equ SPIF = 7 ; SPI Interrupt Flag |
; SPCR - SPI Control Register |
.equ SPR0 = 0 ; SPI Clock Rate Select 0 |
.equ SPR1 = 1 ; SPI Clock Rate Select 1 |
.equ CPHA = 2 ; Clock Phase |
.equ CPOL = 3 ; Clock polarity |
.equ MSTR = 4 ; Master/Slave Select |
.equ DORD = 5 ; Data Order |
.equ SPE = 6 ; SPI Enable |
.equ SPIE = 7 ; SPI Interrupt Enable |
; ***** PORTA ************************ |
; PORTA - Port A Data Register |
.equ PORTA0 = 0 ; Port A Data Register bit 0 |
.equ PA0 = 0 ; For compatibility |
.equ PORTA1 = 1 ; Port A Data Register bit 1 |
.equ PA1 = 1 ; For compatibility |
.equ PORTA2 = 2 ; Port A Data Register bit 2 |
.equ PA2 = 2 ; For compatibility |
.equ PORTA3 = 3 ; Port A Data Register bit 3 |
.equ PA3 = 3 ; For compatibility |
.equ PORTA4 = 4 ; Port A Data Register bit 4 |
.equ PA4 = 4 ; For compatibility |
.equ PORTA5 = 5 ; Port A Data Register bit 5 |
.equ PA5 = 5 ; For compatibility |
.equ PORTA6 = 6 ; Port A Data Register bit 6 |
.equ PA6 = 6 ; For compatibility |
.equ PORTA7 = 7 ; Port A Data Register bit 7 |
.equ PA7 = 7 ; For compatibility |
; DDRA - Port A Data Direction Register |
.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0 |
.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1 |
.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2 |
.equ DDA3 = 3 ; Data Direction Register, Port A, bit 3 |
.equ DDA4 = 4 ; Data Direction Register, Port A, bit 4 |
.equ DDA5 = 5 ; Data Direction Register, Port A, bit 5 |
.equ DDA6 = 6 ; Data Direction Register, Port A, bit 6 |
.equ DDA7 = 7 ; Data Direction Register, Port A, bit 7 |
; PINA - Port A Input Pins |
.equ PINA0 = 0 ; Input Pins, Port A bit 0 |
.equ PINA1 = 1 ; Input Pins, Port A bit 1 |
.equ PINA2 = 2 ; Input Pins, Port A bit 2 |
.equ PINA3 = 3 ; Input Pins, Port A bit 3 |
.equ PINA4 = 4 ; Input Pins, Port A bit 4 |
.equ PINA5 = 5 ; Input Pins, Port A bit 5 |
.equ PINA6 = 6 ; Input Pins, Port A bit 6 |
.equ PINA7 = 7 ; Input Pins, Port A bit 7 |
; ***** PORTB ************************ |
; PORTB - Port B Data Register |
.equ PORTB0 = 0 ; Port B Data Register bit 0 |
.equ PB0 = 0 ; For compatibility |
.equ PORTB1 = 1 ; Port B Data Register bit 1 |
.equ PB1 = 1 ; For compatibility |
.equ PORTB2 = 2 ; Port B Data Register bit 2 |
.equ PB2 = 2 ; For compatibility |
.equ PORTB3 = 3 ; Port B Data Register bit 3 |
.equ PB3 = 3 ; For compatibility |
.equ PORTB4 = 4 ; Port B Data Register bit 4 |
.equ PB4 = 4 ; For compatibility |
.equ PORTB5 = 5 ; Port B Data Register bit 5 |
.equ PB5 = 5 ; For compatibility |
.equ PORTB6 = 6 ; Port B Data Register bit 6 |
.equ PB6 = 6 ; For compatibility |
.equ PORTB7 = 7 ; Port B Data Register bit 7 |
.equ PB7 = 7 ; For compatibility |
; DDRB - Port B Data Direction Register |
.equ DDB0 = 0 ; Port B Data Direction Register bit 0 |
.equ DDB1 = 1 ; Port B Data Direction Register bit 1 |
.equ DDB2 = 2 ; Port B Data Direction Register bit 2 |
.equ DDB3 = 3 ; Port B Data Direction Register bit 3 |
.equ DDB4 = 4 ; Port B Data Direction Register bit 4 |
.equ DDB5 = 5 ; Port B Data Direction Register bit 5 |
.equ DDB6 = 6 ; Port B Data Direction Register bit 6 |
.equ DDB7 = 7 ; Port B Data Direction Register bit 7 |
; PINB - Port B Input Pins |
.equ PINB0 = 0 ; Port B Input Pins bit 0 |
.equ PINB1 = 1 ; Port B Input Pins bit 1 |
.equ PINB2 = 2 ; Port B Input Pins bit 2 |
.equ PINB3 = 3 ; Port B Input Pins bit 3 |
.equ PINB4 = 4 ; Port B Input Pins bit 4 |
.equ PINB5 = 5 ; Port B Input Pins bit 5 |
.equ PINB6 = 6 ; Port B Input Pins bit 6 |
.equ PINB7 = 7 ; Port B Input Pins bit 7 |
; ***** PORTC ************************ |
; PORTC - Port C Data Register |
.equ PORTC0 = 0 ; Port C Data Register bit 0 |
.equ PC0 = 0 ; For compatibility |
.equ PORTC1 = 1 ; Port C Data Register bit 1 |
.equ PC1 = 1 ; For compatibility |
.equ PORTC2 = 2 ; Port C Data Register bit 2 |
.equ PC2 = 2 ; For compatibility |
.equ PORTC3 = 3 ; Port C Data Register bit 3 |
.equ PC3 = 3 ; For compatibility |
.equ PORTC4 = 4 ; Port C Data Register bit 4 |
.equ PC4 = 4 ; For compatibility |
.equ PORTC5 = 5 ; Port C Data Register bit 5 |
.equ PC5 = 5 ; For compatibility |
.equ PORTC6 = 6 ; Port C Data Register bit 6 |
.equ PC6 = 6 ; For compatibility |
.equ PORTC7 = 7 ; Port C Data Register bit 7 |
.equ PC7 = 7 ; For compatibility |
; DDRC - Port C Data Direction Register |
.equ DDC0 = 0 ; Port C Data Direction Register bit 0 |
.equ DDC1 = 1 ; Port C Data Direction Register bit 1 |
.equ DDC2 = 2 ; Port C Data Direction Register bit 2 |
.equ DDC3 = 3 ; Port C Data Direction Register bit 3 |
.equ DDC4 = 4 ; Port C Data Direction Register bit 4 |
.equ DDC5 = 5 ; Port C Data Direction Register bit 5 |
.equ DDC6 = 6 ; Port C Data Direction Register bit 6 |
.equ DDC7 = 7 ; Port C Data Direction Register bit 7 |
; PINC - Port C Input Pins |
.equ PINC0 = 0 ; Port C Input Pins bit 0 |
.equ PINC1 = 1 ; Port C Input Pins bit 1 |
.equ PINC2 = 2 ; Port C Input Pins bit 2 |
.equ PINC3 = 3 ; Port C Input Pins bit 3 |
.equ PINC4 = 4 ; Port C Input Pins bit 4 |
.equ PINC5 = 5 ; Port C Input Pins bit 5 |
.equ PINC6 = 6 ; Port C Input Pins bit 6 |
.equ PINC7 = 7 ; Port C Input Pins bit 7 |
; ***** PORTD ************************ |
; PORTD - Port D Data Register |
.equ PORTD0 = 0 ; Port D Data Register bit 0 |
.equ PD0 = 0 ; For compatibility |
.equ PORTD1 = 1 ; Port D Data Register bit 1 |
.equ PD1 = 1 ; For compatibility |
.equ PORTD2 = 2 ; Port D Data Register bit 2 |
.equ PD2 = 2 ; For compatibility |
.equ PORTD3 = 3 ; Port D Data Register bit 3 |
.equ PD3 = 3 ; For compatibility |
.equ PORTD4 = 4 ; Port D Data Register bit 4 |
.equ PD4 = 4 ; For compatibility |
.equ PORTD5 = 5 ; Port D Data Register bit 5 |
.equ PD5 = 5 ; For compatibility |
.equ PORTD6 = 6 ; Port D Data Register bit 6 |
.equ PD6 = 6 ; For compatibility |
.equ PORTD7 = 7 ; Port D Data Register bit 7 |
.equ PD7 = 7 ; For compatibility |
; DDRD - Port D Data Direction Register |
.equ DDD0 = 0 ; Port D Data Direction Register bit 0 |
.equ DDD1 = 1 ; Port D Data Direction Register bit 1 |
.equ DDD2 = 2 ; Port D Data Direction Register bit 2 |
.equ DDD3 = 3 ; Port D Data Direction Register bit 3 |
.equ DDD4 = 4 ; Port D Data Direction Register bit 4 |
.equ DDD5 = 5 ; Port D Data Direction Register bit 5 |
.equ DDD6 = 6 ; Port D Data Direction Register bit 6 |
.equ DDD7 = 7 ; Port D Data Direction Register bit 7 |
; PIND - Port D Input Pins |
.equ PIND0 = 0 ; Port D Input Pins bit 0 |
.equ PIND1 = 1 ; Port D Input Pins bit 1 |
.equ PIND2 = 2 ; Port D Input Pins bit 2 |
.equ PIND3 = 3 ; Port D Input Pins bit 3 |
.equ PIND4 = 4 ; Port D Input Pins bit 4 |
.equ PIND5 = 5 ; Port D Input Pins bit 5 |
.equ PIND6 = 6 ; Port D Input Pins bit 6 |
.equ PIND7 = 7 ; Port D Input Pins bit 7 |
; ***** ANALOG_COMPARATOR ************ |
; ACSR - Analog Comparator Control And Status Register |
.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 |
.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 |
.equ ACIC = 2 ; Analog Comparator Input Capture Enable |
.equ ACIE = 3 ; Analog Comparator Interrupt Enable |
.equ ACI = 4 ; Analog Comparator Interrupt Flag |
.equ ACO = 5 ; Analog Comparator Output |
.equ ACD = 7 ; Analog Comparator Disable |
; ***** AD_CONVERTER ***************** |
; ADMUX - The ADC multiplexer Selection Register |
.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits |
.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits |
.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits |
; ADCSR - The ADC Control and Status register |
.equ ADPS0 = 0 ; ADC Prescaler Select Bits |
.equ ADPS1 = 1 ; ADC Prescaler Select Bits |
.equ ADPS2 = 2 ; ADC Prescaler Select Bits |
.equ ADIE = 3 ; ADC Interrupt Enable |
.equ ADIF = 4 ; ADC Interrupt Flag |
.equ ADFR = 5 ; ADC Free Running Select |
.equ ADSC = 6 ; ADC Start Conversion |
.equ ADEN = 7 ; ADC Enable |
; ADCH - ADC Data Register High Byte |
.equ ADC8 = 0 ; ADC Data Register High Byte Bit 0 |
.equ ADC9 = 1 ; ADC Data Register High Byte Bit 1 |
; ADCL - ADC Data Register Low Byte |
.equ ADC0 = 0 ; ADC Data Register Low Byte Bit 0 |
.equ ADC1 = 1 ; ADC Data Register Low Byte Bit 1 |
.equ ADC2 = 2 ; ADC Data Register Low Byte Bit 2 |
.equ ADC3 = 3 ; ADC Data Register Low Byte Bit 3 |
.equ ADC4 = 4 ; ADC Data Register Low Byte Bit 4 |
.equ ADC5 = 5 ; ADC Data Register Low Byte Bit 5 |
.equ ADC6 = 6 ; ADC Data Register Low Byte Bit 6 |
.equ ADC7 = 7 ; ADC Data Register Low Byte Bit 7 |
; ***** WATCHDOG ********************* |
; WDTCR - Watchdog Timer Control Register |
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 |
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 |
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 |
.equ WDE = 3 ; Watch Dog Enable |
.equ WDTOE = 4 ; RW |
.equ WDDE = WDTOE ; For compatibility |
; ***** EEPROM *********************** |
; EEDR - EEPROM Data Register |
.equ EEDR0 = 0 ; EEPROM Data Register bit 0 |
.equ EEDR1 = 1 ; EEPROM Data Register bit 1 |
.equ EEDR2 = 2 ; EEPROM Data Register bit 2 |
.equ EEDR3 = 3 ; EEPROM Data Register bit 3 |
.equ EEDR4 = 4 ; EEPROM Data Register bit 4 |
.equ EEDR5 = 5 ; EEPROM Data Register bit 5 |
.equ EEDR6 = 6 ; EEPROM Data Register bit 6 |
.equ EEDR7 = 7 ; EEPROM Data Register bit 7 |
; EECR - EEPROM Control Register |
.equ EERE = 0 ; EEPROM Read Enable |
.equ EEWE = 1 ; EEPROM Write Enable |
.equ EEMWE = 2 ; EEPROM Master Write Enable |
.equ EEWEE = EEMWE ; For compatibility |
.equ EERIE = 3 ; EEPROM Ready Interrupt Enable |
; ***** CPU ************************** |
; SREG - Status Register |
.equ SREG_C = 0 ; Carry Flag |
.equ SREG_Z = 1 ; Zero Flag |
.equ SREG_N = 2 ; Negative Flag |
.equ SREG_V = 3 ; Two's Complement Overflow Flag |
.equ SREG_S = 4 ; Sign Bit |
.equ SREG_H = 5 ; Half Carry Flag |
.equ SREG_T = 6 ; Bit Copy Storage |
.equ SREG_I = 7 ; Global Interrupt Enable |
; MCUCR - MCU Control Register |
.equ ISC00 = 0 ; Interrupt Sense Control 0 bit 0 |
.equ ISC01 = 1 ; Interrupt Sense Control 0 bit 1 |
.equ ISC10 = 2 ; Interrupt Sense Control 1 bit 0 |
.equ ISC11 = 3 ; Interrupt Sense Control 1 bit 1 |
.equ SM0 = 4 ; Sleep Mode Select 0 |
.equ SM1 = 5 ; Sleep Mode Select 1 |
.equ SE = 6 ; Sleep Enable |
; MCUSR - |
.equ PORF = 0 ; Power-on Reset Flag |
.equ EXTRF = 1 ; External Reset Flag |
; ***** EXTERNAL_INTERRUPT *********** |
; GIMSK - General Interrupt Mask Register |
.equ INT0 = 6 ; External Interrupt Request 0 Enable |
.equ INT1 = 7 ; External Interrupt Request 1 Enable |
; GIFR - General Interrupt Flag register |
.equ INTF0 = 6 ; External Interrupt Flag 0 |
.equ INTF1 = 7 ; External Interrupt Flag 1 |
; ***** LOCKSBITS ******************************************************** |
.equ LB1 = 0 ; Lockbit |
.equ LB2 = 1 ; Lockbit |
; ***** FUSES ************************************************************ |
; LOW fuse bits |
.equ SPIEN = 1 ; Serial Program Downloading Enabled |
.equ FSTRT = 2 ; Short Start-up time selected |
; ***** CPU REGISTER DEFINITIONS ***************************************** |
.def XH = r27 |
.def XL = r26 |
.def YH = r29 |
.def YL = r28 |
.def ZH = r31 |
.def ZL = r30 |
; ***** DATA MEMORY DECLARATIONS ***************************************** |
.equ FLASHEND = 0x0fff ; Note: Word address |
.equ IOEND = 0x003f |
.equ SRAM_START = 0x0060 |
.equ SRAM_SIZE = 512 |
.equ RAMEND = 0x025f |
.equ XRAMEND = 0x0000 |
.equ E2END = 0x01ff |
.equ EEPROMEND = 0x01ff |
.equ EEADRBITS = 9 |
#pragma AVRPART MEMORY PROG_FLASH 8192 |
#pragma AVRPART MEMORY EEPROM 512 |
#pragma AVRPART MEMORY INT_SRAM SIZE 512 |
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60 |
; ***** INTERRUPT VECTORS ************************************************ |
.equ INT0addr = 0x0001 ; External Interrupt 0 |
.equ INT1addr = 0x0002 ; External Interrupt 1 |
.equ OC2addr = 0x0003 ; Timer/Counter2 Compare Match |
.equ OVF2addr = 0x0004 ; Timer/Counter2 Overflow |
.equ ICP1addr = 0x0005 ; Timer/Counter1 Capture Event |
.equ OC1Aaddr = 0x0006 ; Timer/Counter1 Compare Match A |
.equ OC1Baddr = 0x0007 ; Timer/Counter1 Compare Match B |
.equ OVF1addr = 0x0008 ; Timer/Counter1 Overflow |
.equ OVF0addr = 0x0009 ; Timer/Counter0 Overflow |
.equ SPIaddr = 0x000a ; SPI Serial Transfer Complete |
.equ URXCaddr = 0x000b ; UART, RX Complete |
.equ UDREaddr = 0x000c ; UART Data Register Empty |
.equ UTXCaddr = 0x000d ; UART, TX Complete |
.equ ADCCaddr = 0x000e ; ADC Conversion Complete |
.equ ERDYaddr = 0x000f ; EEPROM Ready |
.equ ACIaddr = 0x0010 ; Analog Comparator |
.equ INT_VECTORS_SIZE = 17 ; size in words |
#pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED break |
#endif /* _8535DEF_INC_ */ |
; ***** END OF FILE ****************************************************** |
/contrib/toolchain/avra/includes/m103def.inc |
---|
0,0 → 1,713 |
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** |
;***** Created: 2005-01-11 10:30 ******* Source: ATmega103.xml *********** |
;************************************************************************* |
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y |
;* |
;* Number : AVR000 |
;* File Name : "m103def.inc" |
;* Title : Register/Bit Definitions for the ATmega103 |
;* Date : 2005-01-11 |
;* Version : 2.14 |
;* Support E-mail : avr@atmel.com |
;* Target MCU : ATmega103 |
;* |
;* DESCRIPTION |
;* When including this file in the assembly program file, all I/O register |
;* names and I/O register bit names appearing in the data book can be used. |
;* In addition, the six registers forming the three data pointers X, Y and |
;* Z have been assigned names XL - ZH. Highest RAM address for Internal |
;* SRAM is also defined |
;* |
;* The Register names are represented by their hexadecimal address. |
;* |
;* The Register Bit names are represented by their bit number (0-7). |
;* |
;* Please observe the difference in using the bit names with instructions |
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" |
;* (skip if bit in register set/cleared). The following example illustrates |
;* this: |
;* |
;* in r16,PORTB ;read PORTB latch |
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) |
;* out PORTB,r16 ;output to PORTB |
;* |
;* in r16,TIFR ;read the Timer Interrupt Flag Register |
;* sbrc r16,TOV0 ;test the overflow flag (use bit#) |
;* rjmp TOV0_is_set ;jump if set |
;* ... ;otherwise do something else |
;************************************************************************* |
#ifndef _M103DEF_INC_ |
#define _M103DEF_INC_ |
#pragma partinc 0 |
; ***** SPECIFY DEVICE *************************************************** |
.device ATmega103 |
#pragma AVRPART ADMIN PART_NAME ATmega103 |
.equ SIGNATURE_000 = 0x1e |
.equ SIGNATURE_001 = 0x97 |
.equ SIGNATURE_002 = 0x01 |
#pragma AVRPART CORE CORE_VERSION V2 |
#pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED movw:break:lpm rd,z:spm |
; ***** I/O REGISTER DEFINITIONS ***************************************** |
; NOTE: |
; Definitions marked "MEMORY MAPPED"are extended I/O ports |
; and cannot be used with IN/OUT instructions |
.equ SREG = 0x3f |
.equ SPH = 0x3e |
.equ SPL = 0x3d |
.equ XDIV = 0x3c |
.equ RAMPZ = 0x3b |
.equ EICR = 0x3a |
.equ EIMSK = 0x39 |
.equ EIFR = 0x38 |
.equ TIMSK = 0x37 |
.equ TIFR = 0x36 |
.equ MCUCR = 0x35 |
.equ MCUSR = 0x34 |
.equ TCCR0 = 0x33 |
.equ TCNT0 = 0x32 |
.equ OCR0 = 0x31 |
.equ ASSR = 0x30 |
.equ TCCR1A = 0x2f |
.equ TCCR1B = 0x2e |
.equ TCNT1H = 0x2d |
.equ TCNT1L = 0x2c |
.equ OCR1AH = 0x2b |
.equ OCR1AL = 0x2a |
.equ OCR1BH = 0x29 |
.equ OCR1BL = 0x28 |
.equ ICR1H = 0x27 |
.equ ICR1L = 0x26 |
.equ TCCR2 = 0x25 |
.equ TCNT2 = 0x24 |
.equ OCR2 = 0x23 |
.equ WDTCR = 0x21 |
.equ EEARH = 0x1f |
.equ EEARL = 0x1e |
.equ EEDR = 0x1d |
.equ EECR = 0x1c |
.equ PORTA = 0x1b |
.equ DDRA = 0x1a |
.equ PINA = 0x19 |
.equ PORTB = 0x18 |
.equ DDRB = 0x17 |
.equ PINB = 0x16 |
.equ PORTC = 0x15 |
.equ PORTD = 0x12 |
.equ DDRD = 0x11 |
.equ PIND = 0x10 |
.equ SPDR = 0x0f |
.equ SPSR = 0x0e |
.equ SPCR = 0x0d |
.equ UDR = 0x0c |
.equ USR = 0x0b |
.equ UCR = 0x0a |
.equ UBRR = 0x09 |
.equ ACSR = 0x08 |
.equ ADMUX = 0x07 |
.equ ADCSR = 0x06 |
.equ ADCH = 0x05 |
.equ ADCL = 0x04 |
.equ PORTE = 0x03 |
.equ DDRE = 0x02 |
.equ PINE = 0x01 |
.equ PINF = 0x00 |
; ***** BIT DEFINITIONS ************************************************** |
; ***** AD_CONVERTER ***************** |
; ADMUX - The ADC multiplexer Selection Register |
.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits |
.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits |
.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits |
; ADCSR - The ADC Control and Status register |
.equ ADPS0 = 0 ; ADC Prescaler Select Bits |
.equ ADPS1 = 1 ; ADC Prescaler Select Bits |
.equ ADPS2 = 2 ; ADC Prescaler Select Bits |
.equ ADIE = 3 ; ADC Interrupt Enable |
.equ ADIF = 4 ; ADC Interrupt Flag |
.equ ADSC = 6 ; ADC Start Conversion |
.equ ADEN = 7 ; ADC Enable |
; ADCH - ADC Data Register High Byte |
.equ ADC8 = 0 ; ADC Data Register High Byte Bit 0 |
.equ ADC9 = 1 ; ADC Data Register High Byte Bit 1 |
; ADCL - ADC Data Register Low Byte |
.equ ADC0 = 0 ; ADC Data Register Low Byte Bit 0 |
.equ ADC1 = 1 ; ADC Data Register Low Byte Bit 1 |
.equ ADC2 = 2 ; ADC Data Register Low Byte Bit 2 |
.equ ADC3 = 3 ; ADC Data Register Low Byte Bit 3 |
.equ ADC4 = 4 ; ADC Data Register Low Byte Bit 4 |
.equ ADC5 = 5 ; ADC Data Register Low Byte Bit 5 |
.equ ADC6 = 6 ; ADC Data Register Low Byte Bit 6 |
.equ ADC7 = 7 ; ADC Data Register Low Byte Bit 7 |
; ***** ANALOG_COMPARATOR ************ |
; ACSR - Analog Comparator Control And Status Register |
.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 |
.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 |
.equ ACIC = 2 ; Analog Comparator Input Capture Enable |
.equ ACIE = 3 ; Analog Comparator Interrupt Enable |
.equ ACI = 4 ; Analog Comparator Interrupt Flag |
.equ ACO = 5 ; Analog Comparator Output |
.equ ACD = 7 ; Analog Comparator Disable |
; ***** SPI ************************** |
; SPDR - SPI Data Register |
.equ SPDR0 = 0 ; SPI Data Register bit 0 |
.equ SPDR1 = 1 ; SPI Data Register bit 1 |
.equ SPDR2 = 2 ; SPI Data Register bit 2 |
.equ SPDR3 = 3 ; SPI Data Register bit 3 |
.equ SPDR4 = 4 ; SPI Data Register bit 4 |
.equ SPDR5 = 5 ; SPI Data Register bit 5 |
.equ SPDR6 = 6 ; SPI Data Register bit 6 |
.equ SPDR7 = 7 ; SPI Data Register bit 7 |
; SPSR - SPI Status Register |
.equ WCOL = 6 ; Write Collision Flag |
.equ SPIF = 7 ; SPI Interrupt Flag |
; SPCR - SPI Control Register |
.equ SPR0 = 0 ; SPI Clock Rate Select 0 |
.equ SPR1 = 1 ; SPI Clock Rate Select 1 |
.equ CPHA = 2 ; Clock Phase |
.equ CPOL = 3 ; Clock polarity |
.equ MSTR = 4 ; Master/Slave Select |
.equ DORD = 5 ; Data Order |
.equ SPE = 6 ; SPI Enable |
.equ SPIE = 7 ; SPI Interrupt Enable |
; ***** UART ************************* |
; UDR - UART I/O Data Register |
.equ UDR0 = 0 ; UART I/O Data Register bit 0 |
.equ UDR1 = 1 ; UART I/O Data Register bit 1 |
.equ UDR2 = 2 ; UART I/O Data Register bit 2 |
.equ UDR3 = 3 ; UART I/O Data Register bit 3 |
.equ UDR4 = 4 ; UART I/O Data Register bit 4 |
.equ UDR5 = 5 ; UART I/O Data Register bit 5 |
.equ UDR6 = 6 ; UART I/O Data Register bit 6 |
.equ UDR7 = 7 ; UART I/O Data Register bit 7 |
; USR - UART Status Register |
.equ DOR = 3 ; Data overRun |
.equ FE = 4 ; Framing Error |
.equ UDRE = 5 ; UART Data Register Empty |
.equ TXC = 6 ; UART Transmit Complete |
.equ RXC = 7 ; UART Receive Complete |
; UCR - UART Control Register |
.equ TXB8 = 0 ; Transmit Data Bit 8 |
.equ RXB8 = 1 ; Receive Data Bit 8 |
.equ CHR9 = 2 ; 9-bit Characters |
.equ TXEN = 3 ; Transmitter Enable |
.equ RXEN = 4 ; Receiver Enable |
.equ UDRIE = 5 ; UART Data Register Empty Interrupt Enable |
.equ TXCIE = 6 ; TX Complete Interrupt Enable |
.equ RXCIE = 7 ; RX Complete Interrupt Enable |
; UBRR - UART BAUD Rate Register |
.equ UBRR0 = 0 ; UART Baud Rate Register bit 0 |
.equ UBRR1 = 1 ; UART Baud Rate Register bit 1 |
.equ UBRR2 = 2 ; UART Baud Rate Register bit 2 |
.equ UBRR3 = 3 ; UART Baud Rate Register bit 3 |
.equ UBRR4 = 4 ; UART Baud Rate Register bit 4 |
.equ UBRR5 = 5 ; UART Baud Rate Register bit 5 |
.equ UBRR6 = 6 ; UART Baud Rate Register bit 6 |
.equ UBRR7 = 7 ; UART Baud Rate Register bit 7 |
; ***** CPU ************************** |
; SREG - Status Register |
.equ SREG_C = 0 ; Carry Flag |
.equ SREG_Z = 1 ; Zero Flag |
.equ SREG_N = 2 ; Negative Flag |
.equ SREG_V = 3 ; Two's Complement Overflow Flag |
.equ SREG_S = 4 ; Sign Bit |
.equ SREG_H = 5 ; Half Carry Flag |
.equ SREG_T = 6 ; Bit Copy Storage |
.equ SREG_I = 7 ; Global Interrupt Enable |
; MCUCR - MCU Control Register |
.equ SM0 = 3 ; Sleep Mode Select |
.equ SM1 = 4 ; Sleep Mode Select |
.equ SE = 5 ; Sleep Enable |
.equ SRW = 6 ; External SRAM Wait State Select |
.equ SRE = 7 ; External SRAM Enable |
; MCUSR - MCU Status Register |
.equ PORF = 0 ; Power-on reset flag |
.equ EXTRF = 1 ; External Reset Flag |
.equ EXTREF = EXTRF ; For compatibility |
; XDIV - XTAL Divide Control Register |
.equ XDIV0 = 0 ; XTAl Divide Select Bit 0 |
.equ XDIV1 = 1 ; XTAl Divide Select Bit 1 |
.equ XDIV2 = 2 ; XTAl Divide Select Bit 2 |
.equ XDIV3 = 3 ; XTAl Divide Select Bit 3 |
.equ XDIV4 = 4 ; XTAl Divide Select Bit 4 |
.equ XDIV5 = 5 ; XTAl Divide Select Bit 5 |
.equ XDIV6 = 6 ; XTAl Divide Select Bit 6 |
.equ XDIVEN = 7 ; XTAL Divide Enable |
; RAMPZ - RAM Page Z Select Register |
.equ RAMPZ0 = 0 ; RAMPZ0 = 0: Program memory address $0000 - $7FFF. RAMPZ0 = 1, program memory address $8000 - $FFFF. |
; ***** EXTERNAL_INTERRUPT *********** |
; EICR - External Interrupt Control Register B |
.equ ISC40 = 0 ; External Interrupt 7-4 Sense Control Bit |
.equ ISC41 = 1 ; External Interrupt 7-4 Sense Control Bit |
.equ ISC50 = 2 ; External Interrupt 7-4 Sense Control Bit |
.equ ISC51 = 3 ; External Interrupt 7-4 Sense Control Bit |
.equ ISC60 = 4 ; External Interrupt 7-4 Sense Control Bit |
.equ ISC61 = 5 ; External Interrupt 7-4 Sense Control Bit |
.equ ISC70 = 6 ; External Interrupt 7-4 Sense Control Bit |
.equ ISC71 = 7 ; External Interrupt 7-4 Sense Control Bit |
; EIMSK - External Interrupt Mask Register |
.equ INT0 = 0 ; External Interrupt Request 0 Enable |
.equ INT1 = 1 ; External Interrupt Request 1 Enable |
.equ INT2 = 2 ; External Interrupt Request 2 Enable |
.equ INT3 = 3 ; External Interrupt Request 3 Enable |
.equ INT4 = 4 ; External Interrupt Request 4 Enable |
.equ INT5 = 5 ; External Interrupt Request 5 Enable |
.equ INT6 = 6 ; External Interrupt Request 6 Enable |
.equ INT7 = 7 ; External Interrupt Request 7 Enable |
; EIFR - External Interrupt Flag Register |
.equ INTF4 = 4 ; External Interrupt Flag 4 |
.equ INTF5 = 5 ; External Interrupt Flag 5 |
.equ INTF6 = 6 ; External Interrupt Flag 6 |
.equ INTF7 = 7 ; External Interrupt Flag 7 |
; ***** EEPROM *********************** |
; EEDR - EEPROM Data Register |
.equ EEDR0 = 0 ; EEPROM Data Register bit 0 |
.equ EEDR1 = 1 ; EEPROM Data Register bit 1 |
.equ EEDR2 = 2 ; EEPROM Data Register bit 2 |
.equ EEDR3 = 3 ; EEPROM Data Register bit 3 |
.equ EEDR4 = 4 ; EEPROM Data Register bit 4 |
.equ EEDR5 = 5 ; EEPROM Data Register bit 5 |
.equ EEDR6 = 6 ; EEPROM Data Register bit 6 |
.equ EEDR7 = 7 ; EEPROM Data Register bit 7 |
; EECR - EEPROM Control Register |
.equ EERE = 0 ; EEPROM Read Enable |
.equ EEWE = 1 ; EEPROM Write Enable |
.equ EEMWE = 2 ; EEPROM Master Write Enable |
.equ EERIE = 3 ; EEPROM Ready Interrupt Enable |
; ***** PORTA ************************ |
; PORTA - Port A Data Register |
.equ PORTA0 = 0 ; Port A Data Register bit 0 |
.equ PA0 = 0 ; For compatibility |
.equ PORTA1 = 1 ; Port A Data Register bit 1 |
.equ PA1 = 1 ; For compatibility |
.equ PORTA2 = 2 ; Port A Data Register bit 2 |
.equ PA2 = 2 ; For compatibility |
.equ PORTA3 = 3 ; Port A Data Register bit 3 |
.equ PA3 = 3 ; For compatibility |
.equ PORTA4 = 4 ; Port A Data Register bit 4 |
.equ PA4 = 4 ; For compatibility |
.equ PORTA5 = 5 ; Port A Data Register bit 5 |
.equ PA5 = 5 ; For compatibility |
.equ PORTA6 = 6 ; Port A Data Register bit 6 |
.equ PA6 = 6 ; For compatibility |
.equ PORTA7 = 7 ; Port A Data Register bit 7 |
.equ PA7 = 7 ; For compatibility |
; DDRA - Port A Data Direction Register |
.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0 |
.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1 |
.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2 |
.equ DDA3 = 3 ; Data Direction Register, Port A, bit 3 |
.equ DDA4 = 4 ; Data Direction Register, Port A, bit 4 |
.equ DDA5 = 5 ; Data Direction Register, Port A, bit 5 |
.equ DDA6 = 6 ; Data Direction Register, Port A, bit 6 |
.equ DDA7 = 7 ; Data Direction Register, Port A, bit 7 |
; PINA - Port A Input Pins |
.equ PINA0 = 0 ; Input Pins, Port A bit 0 |
.equ PINA1 = 1 ; Input Pins, Port A bit 1 |
.equ PINA2 = 2 ; Input Pins, Port A bit 2 |
.equ PINA3 = 3 ; Input Pins, Port A bit 3 |
.equ PINA4 = 4 ; Input Pins, Port A bit 4 |
.equ PINA5 = 5 ; Input Pins, Port A bit 5 |
.equ PINA6 = 6 ; Input Pins, Port A bit 6 |
.equ PINA7 = 7 ; Input Pins, Port A bit 7 |
; ***** PORTB ************************ |
; PORTB - Port B Data Register |
.equ PORTB0 = 0 ; Port B Data Register bit 0 |
.equ PB0 = 0 ; For compatibility |
.equ PORTB1 = 1 ; Port B Data Register bit 1 |
.equ PB1 = 1 ; For compatibility |
.equ PORTB2 = 2 ; Port B Data Register bit 2 |
.equ PB2 = 2 ; For compatibility |
.equ PORTB3 = 3 ; Port B Data Register bit 3 |
.equ PB3 = 3 ; For compatibility |
.equ PORTB4 = 4 ; Port B Data Register bit 4 |
.equ PB4 = 4 ; For compatibility |
.equ PORTB5 = 5 ; Port B Data Register bit 5 |
.equ PB5 = 5 ; For compatibility |
.equ PORTB6 = 6 ; Port B Data Register bit 6 |
.equ PB6 = 6 ; For compatibility |
.equ PORTB7 = 7 ; Port B Data Register bit 7 |
.equ PB7 = 7 ; For compatibility |
; DDRB - Port B Data Direction Register |
.equ DDB0 = 0 ; Port B Data Direction Register bit 0 |
.equ DDB1 = 1 ; Port B Data Direction Register bit 1 |
.equ DDB2 = 2 ; Port B Data Direction Register bit 2 |
.equ DDB3 = 3 ; Port B Data Direction Register bit 3 |
.equ DDB4 = 4 ; Port B Data Direction Register bit 4 |
.equ DDB5 = 5 ; Port B Data Direction Register bit 5 |
.equ DDB6 = 6 ; Port B Data Direction Register bit 6 |
.equ DDB7 = 7 ; Port B Data Direction Register bit 7 |
; PINB - Port B Input Pins |
.equ PINB0 = 0 ; Port B Input Pins bit 0 |
.equ PINB1 = 1 ; Port B Input Pins bit 1 |
.equ PINB2 = 2 ; Port B Input Pins bit 2 |
.equ PINB3 = 3 ; Port B Input Pins bit 3 |
.equ PINB4 = 4 ; Port B Input Pins bit 4 |
.equ PINB5 = 5 ; Port B Input Pins bit 5 |
.equ PINB6 = 6 ; Port B Input Pins bit 6 |
.equ PINB7 = 7 ; Port B Input Pins bit 7 |
; ***** PORTD ************************ |
; PORTD - Port D Data Register |
.equ PORTD0 = 0 ; Port D Data Register bit 0 |
.equ PD0 = 0 ; For compatibility |
.equ PORTD1 = 1 ; Port D Data Register bit 1 |
.equ PD1 = 1 ; For compatibility |
.equ PORTD2 = 2 ; Port D Data Register bit 2 |
.equ PD2 = 2 ; For compatibility |
.equ PORTD3 = 3 ; Port D Data Register bit 3 |
.equ PD3 = 3 ; For compatibility |
.equ PORTD4 = 4 ; Port D Data Register bit 4 |
.equ PD4 = 4 ; For compatibility |
.equ PORTD5 = 5 ; Port D Data Register bit 5 |
.equ PD5 = 5 ; For compatibility |
.equ PORTD6 = 6 ; Port D Data Register bit 6 |
.equ PD6 = 6 ; For compatibility |
.equ PORTD7 = 7 ; Port D Data Register bit 7 |
.equ PD7 = 7 ; For compatibility |
; DDRD - Port D Data Direction Register |
.equ DDD0 = 0 ; Port D Data Direction Register bit 0 |
.equ DDD1 = 1 ; Port D Data Direction Register bit 1 |
.equ DDD2 = 2 ; Port D Data Direction Register bit 2 |
.equ DDD3 = 3 ; Port D Data Direction Register bit 3 |
.equ DDD4 = 4 ; Port D Data Direction Register bit 4 |
.equ DDD5 = 5 ; Port D Data Direction Register bit 5 |
.equ DDD6 = 6 ; Port D Data Direction Register bit 6 |
.equ DDD7 = 7 ; Port D Data Direction Register bit 7 |
; PIND - Port D Input Pins |
.equ PIND0 = 0 ; Port D Input Pins bit 0 |
.equ PIND1 = 1 ; Port D Input Pins bit 1 |
.equ PIND2 = 2 ; Port D Input Pins bit 2 |
.equ PIND3 = 3 ; Port D Input Pins bit 3 |
.equ PIND4 = 4 ; Port D Input Pins bit 4 |
.equ PIND5 = 5 ; Port D Input Pins bit 5 |
.equ PIND6 = 6 ; Port D Input Pins bit 6 |
.equ PIND7 = 7 ; Port D Input Pins bit 7 |
; ***** PORTC ************************ |
; PORTC - Port C Data Register |
.equ PORTC0 = 0 ; Port C Data Register bit 0 |
.equ PC0 = 0 ; For compatibility |
.equ PORTC1 = 1 ; Port C Data Register bit 1 |
.equ PC1 = 1 ; For compatibility |
.equ PORTC2 = 2 ; Port C Data Register bit 2 |
.equ PC2 = 2 ; For compatibility |
.equ PORTC3 = 3 ; Port C Data Register bit 3 |
.equ PC3 = 3 ; For compatibility |
.equ PORTC4 = 4 ; Port C Data Register bit 4 |
.equ PC4 = 4 ; For compatibility |
.equ PORTC5 = 5 ; Port C Data Register bit 5 |
.equ PC5 = 5 ; For compatibility |
.equ PORTC6 = 6 ; Port C Data Register bit 6 |
.equ PC6 = 6 ; For compatibility |
.equ PORTC7 = 7 ; Port C Data Register bit 7 |
.equ PC7 = 7 ; For compatibility |
; ***** PORTE ************************ |
; PORTE - Data Register, Port E |
.equ PORTE0 = 0 ; |
.equ PE0 = 0 ; For compatibility |
.equ PORTE1 = 1 ; |
.equ PE1 = 1 ; For compatibility |
.equ PORTE2 = 2 ; |
.equ PE2 = 2 ; For compatibility |
.equ PORTE3 = 3 ; |
.equ PE3 = 3 ; For compatibility |
.equ PORTE4 = 4 ; |
.equ PE4 = 4 ; For compatibility |
.equ PORTE5 = 5 ; |
.equ PE5 = 5 ; For compatibility |
.equ PORTE6 = 6 ; |
.equ PE6 = 6 ; For compatibility |
.equ PORTE7 = 7 ; |
.equ PE7 = 7 ; For compatibility |
; DDRE - Data Direction Register, Port E |
.equ DDE0 = 0 ; |
.equ DDE1 = 1 ; |
.equ DDE2 = 2 ; |
.equ DDE3 = 3 ; |
.equ DDE4 = 4 ; |
.equ DDE5 = 5 ; |
.equ DDE6 = 6 ; |
.equ DDE7 = 7 ; |
; PINE - Input Pins, Port E |
.equ PINE0 = 0 ; |
.equ PINE1 = 1 ; |
.equ PINE2 = 2 ; |
.equ PINE3 = 3 ; |
.equ PINE4 = 4 ; |
.equ PINE5 = 5 ; |
.equ PINE6 = 6 ; |
.equ PINE7 = 7 ; |
; ***** PORTF ************************ |
; PINF - Input Pins, Port F |
.equ PINF0 = 0 ; |
.equ PINF1 = 1 ; |
.equ PINF2 = 2 ; |
.equ PINF3 = 3 ; |
.equ PINF4 = 4 ; |
.equ PINF5 = 5 ; |
.equ PINF6 = 6 ; |
.equ PINF7 = 7 ; |
; ***** TIMER_COUNTER_2 ************** |
; TIMSK - Timer/Counter Interrupt Mask register |
.equ TOIE2 = 6 ; Timer/Counter2 Overflow Interrupt Enable |
.equ OCIE2 = 7 ; Timer/Counter2 Output Compare Match Interrupt Enable |
; TIFR - Timer/Counter Interrupt Flag Register |
.equ TOV2 = 6 ; Timer/Counter2 Overflow Flag |
.equ OCF2 = 7 ; Output Compare Flag 2 |
; TCCR2 - Timer/Counter2 Control Register |
.equ CS20 = 0 ; Clock Select bit 0 |
.equ CS21 = 1 ; Clock Select bit 1 |
.equ CS22 = 2 ; Clock Select bit 2 |
.equ CTC2 = 3 ; Clear Timer/Counter2 on Compare Match |
.equ COM20 = 4 ; Compare Output Mode bit 0 |
.equ COM21 = 5 ; Compare Output Mode bit 1 |
.equ PWM2 = 6 ; Pulse Width Modulator Enable |
; TCNT2 - Timer/Counter2 |
.equ TCNT2_0 = 0 ; Timer/Counter 2 bit 0 |
.equ TCNT2_1 = 1 ; Timer/Counter 2 bit 1 |
.equ TCNT2_2 = 2 ; Timer/Counter 2 bit 2 |
.equ TCNT2_3 = 3 ; Timer/Counter 2 bit 3 |
.equ TCNT2_4 = 4 ; Timer/Counter 2 bit 4 |
.equ TCNT2_5 = 5 ; Timer/Counter 2 bit 5 |
.equ TCNT2_6 = 6 ; Timer/Counter 2 bit 6 |
.equ TCNT2_7 = 7 ; Timer/Counter 2 bit 7 |
; OCR2 - Timer/Counter2 Output Compare Register |
.equ OCR2_0 = 0 ; Timer/Counter2 Output Compare Register Bit 0 |
.equ OCR2_1 = 1 ; Timer/Counter2 Output Compare Register Bit 1 |
.equ OCR2_2 = 2 ; Timer/Counter2 Output Compare Register Bit 2 |
.equ OCR2_3 = 3 ; Timer/Counter2 Output Compare Register Bit 3 |
.equ OCR2_4 = 4 ; Timer/Counter2 Output Compare Register Bit 4 |
.equ OCR2_5 = 5 ; Timer/Counter2 Output Compare Register Bit 5 |
.equ OCR2_6 = 6 ; Timer/Counter2 Output Compare Register Bit 6 |
.equ OCR2_7 = 7 ; Timer/Counter2 Output Compare Register Bit 7 |
; ***** TIMER_COUNTER_0 ************** |
; TCCR0 - Timer/Counter Control Register |
.equ CS00 = 0 ; Clock Select 1 |
.equ CS01 = 1 ; Clock Select 1 |
.equ CS02 = 2 ; Clock Select 2 |
.equ CTC0 = 3 ; CLear Timer/Counter on Compare Match |
.equ COM00 = 4 ; Compare match Output Mode 0 |
.equ COM01 = 5 ; Compare Match Output Mode 1 |
.equ PWM0 = 6 ; Pulse Width Modulator Enable |
; TCNT0 - Timer/Counter Register |
.equ TCNT0_0 = 0 ; |
.equ TCNT0_1 = 1 ; |
.equ TCNT0_2 = 2 ; |
.equ TCNT0_3 = 3 ; |
.equ TCNT0_4 = 4 ; |
.equ TCNT0_5 = 5 ; |
.equ TCNT0_6 = 6 ; |
.equ TCNT0_7 = 7 ; |
; OCR0 - Output Compare Register |
.equ OCR0_0 = 0 ; |
.equ OCR0_1 = 1 ; |
.equ OCR0_2 = 2 ; |
.equ OCR0_3 = 3 ; |
.equ OCR0_4 = 4 ; |
.equ OCR0_5 = 5 ; |
.equ OCR0_6 = 6 ; |
.equ OCR0_7 = 7 ; |
; ASSR - Asynchronus Status Register |
.equ TCR0UB = 0 ; Timer/Counter Control Register 0 Update Busy |
.equ OCR0UB = 1 ; Output Compare register 0 Busy |
.equ TCN0UB = 2 ; Timer/Couner0 Update Busy |
.equ AS0 = 3 ; Asynchronus Timer/Counter 0 |
; TIMSK - Timer/Counter Interrupt Mask Register |
.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable |
.equ OCIE0 = 1 ; Timer/Counter0 Output Compare Match Interrupt register |
; TIFR - Timer/Counter Interrupt Flag register |
.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag |
.equ OCF0 = 1 ; Output Compare Flag 0 |
; ***** TIMER_COUNTER_1 ************** |
; TIMSK - Timer/Counter Interrupt Mask Register |
.equ TOIE1 = 2 ; Timer/Counter1 Overflow Interrupt Enable |
.equ OCIE1B = 3 ; Timer/Counter1 Output CompareB Match Interrupt Enable |
.equ OCIE1A = 4 ; Timer/Counter1 Output CompareA Match Interrupt Enable |
.equ TICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable |
; TIFR - Timer/Counter Interrupt Flag register |
.equ TOV1 = 2 ; Timer/Counter1 Overflow Flag |
.equ OCF1B = 3 ; Output Compare Flag 1B |
.equ OCF1A = 4 ; Output Compare Flag 1A |
.equ ICF1 = 5 ; Input Capture Flag 1 |
; TCCR1A - Timer/Counter1 Control Register A |
.equ PWM10 = 0 ; Pulse Width Modulator Select Bit 0 |
.equ PWM11 = 1 ; Pulse Width Modulator Select Bit 1 |
.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0 |
.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1 |
.equ COM1A0 = 6 ; Compare Ouput Mode 1A, bit 0 |
.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1 |
; TCCR1B - Timer/Counter1 Control Register B |
.equ CS10 = 0 ; Clock Select1 bit 0 |
.equ CS11 = 1 ; Clock Select1 bit 1 |
.equ CS12 = 2 ; Clock Select1 bit 2 |
.equ CTC1 = 3 ; Clear Timer/Counter1 on Compare Match |
.equ ICES1 = 6 ; Input Capture 1 Edge Select |
.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler |
; ***** WATCHDOG ********************* |
; WDTCR - Watchdog Timer Control Register |
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 |
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 |
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 |
.equ WDE = 3 ; Watch Dog Enable |
.equ WDTOE = 4 ; RW |
.equ WDDE = WDTOE ; For compatibility |
; ***** LOCKSBITS ******************************************************** |
.equ LB1 = 0 ; Lockbit |
.equ LB2 = 1 ; Lockbit |
; ***** FUSES ************************************************************ |
; LOW fuse bits |
.equ CKSEL0 = 0 ; Select Clock Source |
.equ CKSEL1 = 1 ; Select Clock Source |
.equ CKSEL2 = 2 ; Select Clock Source |
.equ CKSEL3 = 3 ; Select Clock Source |
.equ SUT0 = 4 ; Select start-up time |
.equ SUT1 = 5 ; Select start-up time |
.equ BODEN = 6 ; Brown out detector enable |
.equ BODLEVEL = 7 ; Brown out detector trigger level |
; HIGH fuse bits |
; EXTENDED fuse bits |
; ***** CPU REGISTER DEFINITIONS ***************************************** |
.def XH = r27 |
.def XL = r26 |
.def YH = r29 |
.def YL = r28 |
.def ZH = r31 |
.def ZL = r30 |
; ***** DATA MEMORY DECLARATIONS ***************************************** |
.equ FLASHEND = 0xffff ; Note: Word address |
.equ IOEND = 0x003f |
.equ SRAM_START = 0x0060 |
.equ SRAM_SIZE = 4000 |
.equ RAMEND = 0x0fff |
.equ XRAMEND = 0xffff |
.equ E2END = 0x0fff |
.equ EEPROMEND = 0x0fff |
.equ EEADRBITS = 12 |
#pragma AVRPART MEMORY PROG_FLASH 131072 |
#pragma AVRPART MEMORY EEPROM 4096 |
#pragma AVRPART MEMORY INT_SRAM SIZE 4000 |
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60 |
; ***** INTERRUPT VECTORS ************************************************ |
.equ INT0addr = 0x0002 ; External Interrupt 0 |
.equ INT1addr = 0x0004 ; External Interrupt 1 |
.equ INT2addr = 0x0006 ; External Interrupt 2 |
.equ INT3addr = 0x0008 ; External Interrupt 3 |
.equ INT4addr = 0x000a ; External Interrupt 4 |
.equ INT5addr = 0x000c ; External Interrupt 5 |
.equ INT6addr = 0x000e ; External Interrupt 6 |
.equ INT7addr = 0x0010 ; External Interrupt 7 |
.equ OC2addr = 0x0012 ; Timer/Counter2 Compare Match |
.equ OVF2addr = 0x0014 ; Timer/Counter2 Overflow |
.equ ICP1addr = 0x0016 ; Timer/Counter1 Capture Event |
.equ OC1Aaddr = 0x0018 ; Timer/Counter1 Compare Match A |
.equ OC1Baddr = 0x001a ; Timer/Counter1 Compare Match B |
.equ OVF1addr = 0x001c ; Timer/Counter1 Overflow |
.equ OC0addr = 0x001e ; Timer/Counter0 Compare Match |
.equ OVF0addr = 0x0020 ; Timer/Counter0 Overflow |
.equ SPIaddr = 0x0022 ; SPI Serial Transfer Complete |
.equ URXCaddr = 0x0024 ; UART, Rx Complete |
.equ UDREaddr = 0x0026 ; UART Data Register Empty |
.equ UTXCaddr = 0x0028 ; UART, Tx Complete |
.equ ADCCaddr = 0x002a ; ADC Conversion Complete |
.equ ERDYaddr = 0x002c ; EEPROM Ready |
.equ ACIaddr = 0x002e ; Analog Comparator |
.equ INT_VECTORS_SIZE = 48 ; size in words |
#pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED break |
#endif /* _M103DEF_INC_ */ |
; ***** END OF FILE ****************************************************** |
/contrib/toolchain/avra/includes/m128def.inc |
---|
0,0 → 1,1175 |
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** |
;***** Created: 2005-01-11 10:30 ******* Source: ATmega128.xml *********** |
;************************************************************************* |
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y |
;* |
;* Number : AVR000 |
;* File Name : "m128def.inc" |
;* Title : Register/Bit Definitions for the ATmega128 |
;* Date : 2005-01-11 |
;* Version : 2.14 |
;* Support E-mail : avr@atmel.com |
;* Target MCU : ATmega128 |
;* |
;* DESCRIPTION |
;* When including this file in the assembly program file, all I/O register |
;* names and I/O register bit names appearing in the data book can be used. |
;* In addition, the six registers forming the three data pointers X, Y and |
;* Z have been assigned names XL - ZH. Highest RAM address for Internal |
;* SRAM is also defined |
;* |
;* The Register names are represented by their hexadecimal address. |
;* |
;* The Register Bit names are represented by their bit number (0-7). |
;* |
;* Please observe the difference in using the bit names with instructions |
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" |
;* (skip if bit in register set/cleared). The following example illustrates |
;* this: |
;* |
;* in r16,PORTB ;read PORTB latch |
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) |
;* out PORTB,r16 ;output to PORTB |
;* |
;* in r16,TIFR ;read the Timer Interrupt Flag Register |
;* sbrc r16,TOV0 ;test the overflow flag (use bit#) |
;* rjmp TOV0_is_set ;jump if set |
;* ... ;otherwise do something else |
;************************************************************************* |
#ifndef _M128DEF_INC_ |
#define _M128DEF_INC_ |
#pragma partinc 0 |
; ***** SPECIFY DEVICE *************************************************** |
.device ATmega128 |
#pragma AVRPART ADMIN PART_NAME ATmega128 |
.equ SIGNATURE_000 = 0x1e |
.equ SIGNATURE_001 = 0x97 |
.equ SIGNATURE_002 = 0x02 |
#pragma AVRPART CORE CORE_VERSION V2E |
; ***** I/O REGISTER DEFINITIONS ***************************************** |
; NOTE: |
; Definitions marked "MEMORY MAPPED"are extended I/O ports |
; and cannot be used with IN/OUT instructions |
.equ UCSR1C = 0x9d ; MEMORY MAPPED |
.equ UDR1 = 0x9c ; MEMORY MAPPED |
.equ UCSR1A = 0x9b ; MEMORY MAPPED |
.equ UCSR1B = 0x9a ; MEMORY MAPPED |
.equ UBRR1L = 0x99 ; MEMORY MAPPED |
.equ UBRR1H = 0x98 ; MEMORY MAPPED |
.equ UCSR0C = 0x95 ; MEMORY MAPPED |
.equ UBRR0H = 0x90 ; MEMORY MAPPED |
.equ TCCR3C = 0x8c ; MEMORY MAPPED |
.equ TCCR3A = 0x8b ; MEMORY MAPPED |
.equ TCCR3B = 0x8a ; MEMORY MAPPED |
.equ TCNT3H = 0x89 ; MEMORY MAPPED |
.equ TCNT3L = 0x88 ; MEMORY MAPPED |
.equ OCR3AH = 0x87 ; MEMORY MAPPED |
.equ OCR3AL = 0x86 ; MEMORY MAPPED |
.equ OCR3BH = 0x85 ; MEMORY MAPPED |
.equ OCR3BL = 0x84 ; MEMORY MAPPED |
.equ OCR3CH = 0x83 ; MEMORY MAPPED |
.equ OCR3CL = 0x82 ; MEMORY MAPPED |
.equ ICR3H = 0x81 ; MEMORY MAPPED |
.equ ICR3L = 0x80 ; MEMORY MAPPED |
.equ ETIMSK = 0x7d ; MEMORY MAPPED |
.equ ETIFR = 0x7c ; MEMORY MAPPED |
.equ TCCR1C = 0x7a ; MEMORY MAPPED |
.equ OCR1CH = 0x79 ; MEMORY MAPPED |
.equ OCR1CL = 0x78 ; MEMORY MAPPED |
.equ TWCR = 0x74 ; MEMORY MAPPED |
.equ TWDR = 0x73 ; MEMORY MAPPED |
.equ TWAR = 0x72 ; MEMORY MAPPED |
.equ TWSR = 0x71 ; MEMORY MAPPED |
.equ TWBR = 0x70 ; MEMORY MAPPED |
.equ OSCCAL = 0x6f ; MEMORY MAPPED |
.equ XMCRA = 0x6d ; MEMORY MAPPED |
.equ XMCRB = 0x6c ; MEMORY MAPPED |
.equ EICRA = 0x6a ; MEMORY MAPPED |
.equ SPMCSR = 0x68 ; MEMORY MAPPED |
.equ PORTG = 0x65 ; MEMORY MAPPED |
.equ DDRG = 0x64 ; MEMORY MAPPED |
.equ PING = 0x63 ; MEMORY MAPPED |
.equ PORTF = 0x62 ; MEMORY MAPPED |
.equ DDRF = 0x61 ; MEMORY MAPPED |
.equ SREG = 0x3f |
.equ SPH = 0x3e |
.equ SPL = 0x3d |
.equ XDIV = 0x3c |
.equ RAMPZ = 0x3b |
.equ EICRB = 0x3a |
.equ EIMSK = 0x39 |
.equ EIFR = 0x38 |
.equ TIMSK = 0x37 |
.equ TIFR = 0x36 |
.equ MCUCR = 0x35 |
.equ MCUCSR = 0x34 |
.equ TCCR0 = 0x33 |
.equ TCNT0 = 0x32 |
.equ OCR0 = 0x31 |
.equ ASSR = 0x30 |
.equ TCCR1A = 0x2f |
.equ TCCR1B = 0x2e |
.equ TCNT1H = 0x2d |
.equ TCNT1L = 0x2c |
.equ OCR1AH = 0x2b |
.equ OCR1AL = 0x2a |
.equ OCR1BH = 0x29 |
.equ OCR1BL = 0x28 |
.equ ICR1H = 0x27 |
.equ ICR1L = 0x26 |
.equ TCCR2 = 0x25 |
.equ TCNT2 = 0x24 |
.equ OCR2 = 0x23 |
.equ OCDR = 0x22 |
.equ WDTCR = 0x21 |
.equ SFIOR = 0x20 |
.equ EEARH = 0x1f |
.equ EEARL = 0x1e |
.equ EEDR = 0x1d |
.equ EECR = 0x1c |
.equ PORTA = 0x1b |
.equ DDRA = 0x1a |
.equ PINA = 0x19 |
.equ PORTB = 0x18 |
.equ DDRB = 0x17 |
.equ PINB = 0x16 |
.equ PORTC = 0x15 |
.equ DDRC = 0x14 |
.equ PINC = 0x13 |
.equ PORTD = 0x12 |
.equ DDRD = 0x11 |
.equ PIND = 0x10 |
.equ SPDR = 0x0f |
.equ SPSR = 0x0e |
.equ SPCR = 0x0d |
.equ UDR0 = 0x0c |
.equ UCSR0A = 0x0b |
.equ UCSR0B = 0x0a |
.equ UBRR0L = 0x09 |
.equ ACSR = 0x08 |
.equ ADMUX = 0x07 |
.equ ADCSRA = 0x06 |
.equ ADCH = 0x05 |
.equ ADCL = 0x04 |
.equ PORTE = 0x03 |
.equ DDRE = 0x02 |
.equ PINE = 0x01 |
.equ PINF = 0x00 |
; ***** BIT DEFINITIONS ************************************************** |
; ***** ANALOG_COMPARATOR ************ |
; SFIOR - Special Function IO Register |
.equ ACME = 3 ; Analog Comparator Multiplexer Enable |
; ACSR - Analog Comparator Control And Status Register |
.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 |
.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 |
.equ ACIC = 2 ; Analog Comparator Input Capture Enable |
.equ ACIE = 3 ; Analog Comparator Interrupt Enable |
.equ ACI = 4 ; Analog Comparator Interrupt Flag |
.equ ACO = 5 ; Analog Compare Output |
.equ ACBG = 6 ; Analog Comparator Bandgap Select |
.equ ACD = 7 ; Analog Comparator Disable |
; ***** AD_CONVERTER ***************** |
; ADMUX - The ADC multiplexer Selection Register |
.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits |
.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits |
.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits |
.equ MUX3 = 3 ; Analog Channel and Gain Selection Bits |
.equ MUX4 = 4 ; Analog Channel and Gain Selection Bits |
.equ ADLAR = 5 ; Left Adjust Result |
.equ REFS0 = 6 ; Reference Selection Bit 0 |
.equ REFS1 = 7 ; Reference Selection Bit 1 |
; ADCSRA - The ADC Control and Status register |
.equ ADCSR = ADCSRA ; For compatibility |
.equ ADPS0 = 0 ; ADC Prescaler Select Bits |
.equ ADPS1 = 1 ; ADC Prescaler Select Bits |
.equ ADPS2 = 2 ; ADC Prescaler Select Bits |
.equ ADIE = 3 ; ADC Interrupt Enable |
.equ ADIF = 4 ; ADC Interrupt Flag |
.equ ADFR = 5 ; ADC Free Running Select |
.equ ADSC = 6 ; ADC Start Conversion |
.equ ADEN = 7 ; ADC Enable |
; ADCH - ADC Data Register High Byte |
.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0 |
.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1 |
.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2 |
.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3 |
.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4 |
.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5 |
.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6 |
.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7 |
; ADCL - ADC Data Register Low Byte |
.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0 |
.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1 |
.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2 |
.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3 |
.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4 |
.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5 |
.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6 |
.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7 |
; ***** SPI ************************** |
; SPDR - SPI Data Register |
.equ SPDR0 = 0 ; SPI Data Register bit 0 |
.equ SPDR1 = 1 ; SPI Data Register bit 1 |
.equ SPDR2 = 2 ; SPI Data Register bit 2 |
.equ SPDR3 = 3 ; SPI Data Register bit 3 |
.equ SPDR4 = 4 ; SPI Data Register bit 4 |
.equ SPDR5 = 5 ; SPI Data Register bit 5 |
.equ SPDR6 = 6 ; SPI Data Register bit 6 |
.equ SPDR7 = 7 ; SPI Data Register bit 7 |
; SPSR - SPI Status Register |
.equ SPI2X = 0 ; Double SPI Speed Bit |
.equ WCOL = 6 ; Write Collision Flag |
.equ SPIF = 7 ; SPI Interrupt Flag |
; SPCR - SPI Control Register |
.equ SPR0 = 0 ; SPI Clock Rate Select 0 |
.equ SPR1 = 1 ; SPI Clock Rate Select 1 |
.equ CPHA = 2 ; Clock Phase |
.equ CPOL = 3 ; Clock polarity |
.equ MSTR = 4 ; Master/Slave Select |
.equ DORD = 5 ; Data Order |
.equ SPE = 6 ; SPI Enable |
.equ SPIE = 7 ; SPI Interrupt Enable |
; ***** TWI ************************** |
; TWBR - TWI Bit Rate register |
.equ I2BR = TWBR ; For compatibility |
.equ TWBR0 = 0 ; |
.equ TWBR1 = 1 ; |
.equ TWBR2 = 2 ; |
.equ TWBR3 = 3 ; |
.equ TWBR4 = 4 ; |
.equ TWBR5 = 5 ; |
.equ TWBR6 = 6 ; |
.equ TWBR7 = 7 ; |
; TWCR - TWI Control Register |
.equ I2CR = TWCR ; For compatibility |
.equ TWIE = 0 ; TWI Interrupt Enable |
.equ I2IE = TWIE ; For compatibility |
.equ TWEN = 2 ; TWI Enable Bit |
.equ I2EN = TWEN ; For compatibility |
.equ ENI2C = TWEN ; For compatibility |
.equ TWWC = 3 ; TWI Write Collition Flag |
.equ I2WC = TWWC ; For compatibility |
.equ TWSTO = 4 ; TWI Stop Condition Bit |
.equ I2STO = TWSTO ; For compatibility |
.equ TWSTA = 5 ; TWI Start Condition Bit |
.equ I2STA = TWSTA ; For compatibility |
.equ TWEA = 6 ; TWI Enable Acknowledge Bit |
.equ I2EA = TWEA ; For compatibility |
.equ TWINT = 7 ; TWI Interrupt Flag |
.equ I2INT = TWINT ; For compatibility |
; TWSR - TWI Status Register |
.equ I2SR = TWSR ; For compatibility |
.equ TWPS0 = 0 ; TWI Prescaler |
.equ TWS0 = TWPS0 ; For compatibility |
.equ I2GCE = TWPS0 ; For compatibility |
.equ TWPS1 = 1 ; TWI Prescaler |
.equ TWS1 = TWPS1 ; For compatibility |
.equ TWS3 = 3 ; TWI Status |
.equ I2S3 = TWS3 ; For compatibility |
.equ TWS4 = 4 ; TWI Status |
.equ I2S4 = TWS4 ; For compatibility |
.equ TWS5 = 5 ; TWI Status |
.equ I2S5 = TWS5 ; For compatibility |
.equ TWS6 = 6 ; TWI Status |
.equ I2S6 = TWS6 ; For compatibility |
.equ TWS7 = 7 ; TWI Status |
.equ I2S7 = TWS7 ; For compatibility |
; TWDR - TWI Data register |
.equ I2DR = TWDR ; For compatibility |
.equ TWD0 = 0 ; TWI Data Register Bit 0 |
.equ TWD1 = 1 ; TWI Data Register Bit 1 |
.equ TWD2 = 2 ; TWI Data Register Bit 2 |
.equ TWD3 = 3 ; TWI Data Register Bit 3 |
.equ TWD4 = 4 ; TWI Data Register Bit 4 |
.equ TWD5 = 5 ; TWI Data Register Bit 5 |
.equ TWD6 = 6 ; TWI Data Register Bit 6 |
.equ TWD7 = 7 ; TWI Data Register Bit 7 |
; TWAR - TWI (Slave) Address register |
.equ I2AR = TWAR ; For compatibility |
.equ TWGCE = 0 ; TWI General Call Recognition Enable Bit |
.equ TWA0 = 1 ; TWI (Slave) Address register Bit 0 |
.equ TWA1 = 2 ; TWI (Slave) Address register Bit 1 |
.equ TWA2 = 3 ; TWI (Slave) Address register Bit 2 |
.equ TWA3 = 4 ; TWI (Slave) Address register Bit 3 |
.equ TWA4 = 5 ; TWI (Slave) Address register Bit 4 |
.equ TWA5 = 6 ; TWI (Slave) Address register Bit 5 |
.equ TWA6 = 7 ; TWI (Slave) Address register Bit 6 |
; ***** USART0 *********************** |
; UDR0 - USART I/O Data Register |
.equ UDR00 = 0 ; USART I/O Data Register bit 0 |
.equ UDR01 = 1 ; USART I/O Data Register bit 1 |
.equ UDR02 = 2 ; USART I/O Data Register bit 2 |
.equ UDR03 = 3 ; USART I/O Data Register bit 3 |
.equ UDR04 = 4 ; USART I/O Data Register bit 4 |
.equ UDR05 = 5 ; USART I/O Data Register bit 5 |
.equ UDR06 = 6 ; USART I/O Data Register bit 6 |
.equ UDR07 = 7 ; USART I/O Data Register bit 7 |
; UCSR0A - USART Control and Status Register A |
.equ MPCM0 = 0 ; Multi-processor Communication Mode |
.equ U2X0 = 1 ; Double the USART transmission speed |
.equ UPE0 = 2 ; Parity Error |
.equ DOR0 = 3 ; Data overRun |
.equ FE0 = 4 ; Framing Error |
.equ UDRE0 = 5 ; USART Data Register Empty |
.equ TXC0 = 6 ; USART Transmitt Complete |
.equ RXC0 = 7 ; USART Receive Complete |
; UCSR0B - USART Control and Status Register B |
.equ TXB80 = 0 ; Transmit Data Bit 8 |
.equ RXB80 = 1 ; Receive Data Bit 8 |
.equ UCSZ02 = 2 ; Character Size |
.equ UCSZ2 = UCSZ02 ; For compatibility |
.equ TXEN0 = 3 ; Transmitter Enable |
.equ RXEN0 = 4 ; Receiver Enable |
.equ UDRIE0 = 5 ; USART Data register Empty Interrupt Enable |
.equ TXCIE0 = 6 ; TX Complete Interrupt Enable |
.equ RXCIE0 = 7 ; RX Complete Interrupt Enable |
; UCSR0C - USART Control and Status Register C |
.equ UCPOL0 = 0 ; Clock Polarity |
.equ UCSZ00 = 1 ; Character Size |
.equ UCSZ01 = 2 ; Character Size |
.equ USBS0 = 3 ; Stop Bit Select |
.equ UPM00 = 4 ; Parity Mode Bit 0 |
.equ UPM01 = 5 ; Parity Mode Bit 1 |
.equ UMSEL0 = 6 ; USART Mode Select |
; ***** USART1 *********************** |
; UDR1 - USART I/O Data Register |
.equ UDR10 = 0 ; USART I/O Data Register bit 0 |
.equ UDR11 = 1 ; USART I/O Data Register bit 1 |
.equ UDR12 = 2 ; USART I/O Data Register bit 2 |
.equ UDR13 = 3 ; USART I/O Data Register bit 3 |
.equ UDR14 = 4 ; USART I/O Data Register bit 4 |
.equ UDR15 = 5 ; USART I/O Data Register bit 5 |
.equ UDR16 = 6 ; USART I/O Data Register bit 6 |
.equ UDR17 = 7 ; USART I/O Data Register bit 7 |
; UCSR1A - USART Control and Status Register A |
.equ MPCM1 = 0 ; Multi-processor Communication Mode |
.equ U2X1 = 1 ; Double the USART transmission speed |
.equ UPE1 = 2 ; Parity Error |
.equ DOR1 = 3 ; Data overRun |
.equ FE1 = 4 ; Framing Error |
.equ UDRE1 = 5 ; USART Data Register Empty |
.equ TXC1 = 6 ; USART Transmitt Complete |
.equ RXC1 = 7 ; USART Receive Complete |
; UCSR1B - USART Control and Status Register B |
.equ TXB81 = 0 ; Transmit Data Bit 8 |
.equ RXB81 = 1 ; Receive Data Bit 8 |
.equ UCSZ12 = 2 ; Character Size |
.equ TXEN1 = 3 ; Transmitter Enable |
.equ RXEN1 = 4 ; Receiver Enable |
.equ UDRIE1 = 5 ; USART Data register Empty Interrupt Enable |
.equ TXCIE1 = 6 ; TX Complete Interrupt Enable |
.equ RXCIE1 = 7 ; RX Complete Interrupt Enable |
; UCSR1C - USART Control and Status Register C |
.equ UCPOL1 = 0 ; Clock Polarity |
.equ UCSZ10 = 1 ; Character Size |
.equ UCSZ11 = 2 ; Character Size |
.equ USBS1 = 3 ; Stop Bit Select |
.equ UPM10 = 4 ; Parity Mode Bit 0 |
.equ UPM11 = 5 ; Parity Mode Bit 1 |
.equ UMSEL1 = 6 ; USART Mode Select |
; ***** CPU ************************** |
; SREG - Status Register |
.equ SREG_C = 0 ; Carry Flag |
.equ SREG_Z = 1 ; Zero Flag |
.equ SREG_N = 2 ; Negative Flag |
.equ SREG_V = 3 ; Two's Complement Overflow Flag |
.equ SREG_S = 4 ; Sign Bit |
.equ SREG_H = 5 ; Half Carry Flag |
.equ SREG_T = 6 ; Bit Copy Storage |
.equ SREG_I = 7 ; Global Interrupt Enable |
; MCUCR - MCU Control Register |
.equ IVCE = 0 ; Interrupt Vector Change Enable |
.equ IVSEL = 1 ; Interrupt Vector Select |
.equ SM2 = 2 ; Sleep Mode Select |
.equ SM0 = 3 ; Sleep Mode Select |
.equ SM1 = 4 ; Sleep Mode Select |
.equ SE = 5 ; Sleep Enable |
.equ SRW10 = 6 ; External SRAM Wait State Select |
.equ SRE = 7 ; External SRAM Enable |
; XMCRA - External Memory Control Register A |
.equ SRW11 = 1 ; Wait state select bit upper page |
.equ SRW00 = 2 ; Wait state select bit lower page |
.equ SRW01 = 3 ; Wait state select bit lower page |
.equ SRL0 = 4 ; Wait state page limit |
.equ SRL1 = 5 ; Wait state page limit |
.equ SRL2 = 6 ; Wait state page limit |
; XMCRB - External Memory Control Register B |
.equ XMM0 = 0 ; External Memory High Mask |
.equ XMM1 = 1 ; External Memory High Mask |
.equ XMM2 = 2 ; External Memory High Mask |
.equ XMBK = 7 ; External Memory Bus Keeper Enable |
; OSCCAL - Oscillator Calibration Value |
.equ CAL0 = 0 ; Oscillator Calibration Value |
.equ CAL1 = 1 ; Oscillator Calibration Value |
.equ CAL2 = 2 ; Oscillator Calibration Value |
.equ CAL3 = 3 ; Oscillator Calibration Value |
.equ CAL4 = 4 ; Oscillator Calibration Value |
.equ CAL5 = 5 ; Oscillator Calibration Value |
.equ CAL6 = 6 ; Oscillator Calibration Value |
.equ CAL7 = 7 ; Oscillator Calibration Value |
; XDIV - XTAL Divide Control Register |
.equ XDIV0 = 0 ; XTAl Divide Select Bit 0 |
.equ XDIV1 = 1 ; XTAl Divide Select Bit 1 |
.equ XDIV2 = 2 ; XTAl Divide Select Bit 2 |
.equ XDIV3 = 3 ; XTAl Divide Select Bit 3 |
.equ XDIV4 = 4 ; XTAl Divide Select Bit 4 |
.equ XDIV5 = 5 ; XTAl Divide Select Bit 5 |
.equ XDIV6 = 6 ; XTAl Divide Select Bit 6 |
.equ XDIVEN = 7 ; XTAL Divide Enable |
; MCUCSR - MCU Control And Status Register |
.equ PORF = 0 ; Power-on reset flag |
.equ EXTRF = 1 ; External Reset Flag |
.equ BORF = 2 ; Brown-out Reset Flag |
.equ WDRF = 3 ; Watchdog Reset Flag |
.equ JTRF = 4 ; JTAG Reset Flag |
.equ JTD = 7 ; JTAG Interface Disable |
; RAMPZ - RAM Page Z Select Register |
.equ RAMPZ0 = 0 ; RAM Page Z Select Register Bit 0 |
; ***** BOOT_LOAD ******************** |
; SPMCSR - Store Program Memory Control Register |
.equ SPMCR = SPMCSR ; For compatibility |
.equ SPMEN = 0 ; Store Program Memory Enable |
.equ PGERS = 1 ; Page Erase |
.equ PGWRT = 2 ; Page Write |
.equ BLBSET = 3 ; Boot Lock Bit Set |
.equ RWWSRE = 4 ; Read While Write section read enable |
.equ ASRE = RWWSRE ; For compatibility |
.equ RWWSB = 6 ; Read While Write Section Busy |
.equ ASB = RWWSB ; For compatibility |
.equ SPMIE = 7 ; SPM Interrupt Enable |
; ***** JTAG ************************* |
; OCDR - On-Chip Debug Related Register in I/O Memory |
.equ OCDR0 = 0 ; On-Chip Debug Register Bit 0 |
.equ OCDR1 = 1 ; On-Chip Debug Register Bit 1 |
.equ OCDR2 = 2 ; On-Chip Debug Register Bit 2 |
.equ OCDR3 = 3 ; On-Chip Debug Register Bit 3 |
.equ OCDR4 = 4 ; On-Chip Debug Register Bit 4 |
.equ OCDR5 = 5 ; On-Chip Debug Register Bit 5 |
.equ OCDR6 = 6 ; On-Chip Debug Register Bit 6 |
.equ OCDR7 = 7 ; On-Chip Debug Register Bit 7 |
.equ IDRD = OCDR7 ; For compatibility |
; MCUCSR - MCU Control And Status Register |
;.equ JTRF = 4 ; JTAG Reset Flag |
;.equ JTD = 7 ; JTAG Interface Disable |
; ***** MISC ************************* |
; SFIOR - Special Function IO Register |
.equ PSR321 = 0 ; Prescaler Reset Timer/Counter3, Timer/Counter2, and Timer/Counter1 |
.equ PSR1 = PSR321 ; For compatibility |
.equ PSR2 = PSR321 ; For compatibility |
.equ PSR3 = PSR321 ; For compatibility |
.equ PSR0 = 1 ; Prescaler Reset Timer/Counter0 |
.equ PUD = 2 ; Pull Up Disable |
;.equ ACME = 3 ; Analog Comparator Multiplexer Enable |
.equ TSM = 7 ; Timer/Counter Synchronization Mode |
; ***** EXTERNAL_INTERRUPT *********** |
; EICRA - External Interrupt Control Register A |
.equ ISC00 = 0 ; External Interrupt Sense Control Bit |
.equ ISC01 = 1 ; External Interrupt Sense Control Bit |
.equ ISC10 = 2 ; External Interrupt Sense Control Bit |
.equ ISC11 = 3 ; External Interrupt Sense Control Bit |
.equ ISC20 = 4 ; External Interrupt Sense Control Bit |
.equ ISC21 = 5 ; External Interrupt Sense Control Bit |
.equ ISC30 = 6 ; External Interrupt Sense Control Bit |
.equ ISC31 = 7 ; External Interrupt Sense Control Bit |
; EICRB - External Interrupt Control Register B |
.equ ISC40 = 0 ; External Interrupt 7-4 Sense Control Bit |
.equ ISC41 = 1 ; External Interrupt 7-4 Sense Control Bit |
.equ ISC50 = 2 ; External Interrupt 7-4 Sense Control Bit |
.equ ISC51 = 3 ; External Interrupt 7-4 Sense Control Bit |
.equ ISC60 = 4 ; External Interrupt 7-4 Sense Control Bit |
.equ ISC61 = 5 ; External Interrupt 7-4 Sense Control Bit |
.equ ISC70 = 6 ; External Interrupt 7-4 Sense Control Bit |
.equ ISC71 = 7 ; External Interrupt 7-4 Sense Control Bit |
; EIMSK - External Interrupt Mask Register |
.equ GICR = EIMSK ; For compatibility |
.equ GIMSK = EIMSK ; For compatibility |
.equ INT0 = 0 ; External Interrupt Request 0 Enable |
.equ INT1 = 1 ; External Interrupt Request 1 Enable |
.equ INT2 = 2 ; External Interrupt Request 2 Enable |
.equ INT3 = 3 ; External Interrupt Request 3 Enable |
.equ INT4 = 4 ; External Interrupt Request 4 Enable |
.equ INT5 = 5 ; External Interrupt Request 5 Enable |
.equ INT6 = 6 ; External Interrupt Request 6 Enable |
.equ INT7 = 7 ; External Interrupt Request 7 Enable |
; EIFR - External Interrupt Flag Register |
.equ GIFR = EIFR ; For compatibility |
.equ INTF0 = 0 ; External Interrupt Flag 0 |
.equ INTF1 = 1 ; External Interrupt Flag 1 |
.equ INTF2 = 2 ; External Interrupt Flag 2 |
.equ INTF3 = 3 ; External Interrupt Flag 3 |
.equ INTF4 = 4 ; External Interrupt Flag 4 |
.equ INTF5 = 5 ; External Interrupt Flag 5 |
.equ INTF6 = 6 ; External Interrupt Flag 6 |
.equ INTF7 = 7 ; External Interrupt Flag 7 |
; ***** EEPROM *********************** |
; EEDR - EEPROM Data Register |
.equ EEDR0 = 0 ; EEPROM Data Register bit 0 |
.equ EEDR1 = 1 ; EEPROM Data Register bit 1 |
.equ EEDR2 = 2 ; EEPROM Data Register bit 2 |
.equ EEDR3 = 3 ; EEPROM Data Register bit 3 |
.equ EEDR4 = 4 ; EEPROM Data Register bit 4 |
.equ EEDR5 = 5 ; EEPROM Data Register bit 5 |
.equ EEDR6 = 6 ; EEPROM Data Register bit 6 |
.equ EEDR7 = 7 ; EEPROM Data Register bit 7 |
; EECR - EEPROM Control Register |
.equ EERE = 0 ; EEPROM Read Enable |
.equ EEWE = 1 ; EEPROM Write Enable |
.equ EEMWE = 2 ; EEPROM Master Write Enable |
.equ EERIE = 3 ; EEPROM Ready Interrupt Enable |
; ***** PORTA ************************ |
; PORTA - Port A Data Register |
.equ PORTA0 = 0 ; Port A Data Register bit 0 |
.equ PA0 = 0 ; For compatibility |
.equ PORTA1 = 1 ; Port A Data Register bit 1 |
.equ PA1 = 1 ; For compatibility |
.equ PORTA2 = 2 ; Port A Data Register bit 2 |
.equ PA2 = 2 ; For compatibility |
.equ PORTA3 = 3 ; Port A Data Register bit 3 |
.equ PA3 = 3 ; For compatibility |
.equ PORTA4 = 4 ; Port A Data Register bit 4 |
.equ PA4 = 4 ; For compatibility |
.equ PORTA5 = 5 ; Port A Data Register bit 5 |
.equ PA5 = 5 ; For compatibility |
.equ PORTA6 = 6 ; Port A Data Register bit 6 |
.equ PA6 = 6 ; For compatibility |
.equ PORTA7 = 7 ; Port A Data Register bit 7 |
.equ PA7 = 7 ; For compatibility |
; DDRA - Port A Data Direction Register |
.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0 |
.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1 |
.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2 |
.equ DDA3 = 3 ; Data Direction Register, Port A, bit 3 |
.equ DDA4 = 4 ; Data Direction Register, Port A, bit 4 |
.equ DDA5 = 5 ; Data Direction Register, Port A, bit 5 |
.equ DDA6 = 6 ; Data Direction Register, Port A, bit 6 |
.equ DDA7 = 7 ; Data Direction Register, Port A, bit 7 |
; PINA - Port A Input Pins |
.equ PINA0 = 0 ; Input Pins, Port A bit 0 |
.equ PINA1 = 1 ; Input Pins, Port A bit 1 |
.equ PINA2 = 2 ; Input Pins, Port A bit 2 |
.equ PINA3 = 3 ; Input Pins, Port A bit 3 |
.equ PINA4 = 4 ; Input Pins, Port A bit 4 |
.equ PINA5 = 5 ; Input Pins, Port A bit 5 |
.equ PINA6 = 6 ; Input Pins, Port A bit 6 |
.equ PINA7 = 7 ; Input Pins, Port A bit 7 |
; ***** PORTB ************************ |
; PORTB - Port B Data Register |
.equ PORTB0 = 0 ; Port B Data Register bit 0 |
.equ PB0 = 0 ; For compatibility |
.equ PORTB1 = 1 ; Port B Data Register bit 1 |
.equ PB1 = 1 ; For compatibility |
.equ PORTB2 = 2 ; Port B Data Register bit 2 |
.equ PB2 = 2 ; For compatibility |
.equ PORTB3 = 3 ; Port B Data Register bit 3 |
.equ PB3 = 3 ; For compatibility |
.equ PORTB4 = 4 ; Port B Data Register bit 4 |
.equ PB4 = 4 ; For compatibility |
.equ PORTB5 = 5 ; Port B Data Register bit 5 |
.equ PB5 = 5 ; For compatibility |
.equ PORTB6 = 6 ; Port B Data Register bit 6 |
.equ PB6 = 6 ; For compatibility |
.equ PORTB7 = 7 ; Port B Data Register bit 7 |
.equ PB7 = 7 ; For compatibility |
; DDRB - Port B Data Direction Register |
.equ DDB0 = 0 ; Port B Data Direction Register bit 0 |
.equ DDB1 = 1 ; Port B Data Direction Register bit 1 |
.equ DDB2 = 2 ; Port B Data Direction Register bit 2 |
.equ DDB3 = 3 ; Port B Data Direction Register bit 3 |
.equ DDB4 = 4 ; Port B Data Direction Register bit 4 |
.equ DDB5 = 5 ; Port B Data Direction Register bit 5 |
.equ DDB6 = 6 ; Port B Data Direction Register bit 6 |
.equ DDB7 = 7 ; Port B Data Direction Register bit 7 |
; PINB - Port B Input Pins |
.equ PINB0 = 0 ; Port B Input Pins bit 0 |
.equ PINB1 = 1 ; Port B Input Pins bit 1 |
.equ PINB2 = 2 ; Port B Input Pins bit 2 |
.equ PINB3 = 3 ; Port B Input Pins bit 3 |
.equ PINB4 = 4 ; Port B Input Pins bit 4 |
.equ PINB5 = 5 ; Port B Input Pins bit 5 |
.equ PINB6 = 6 ; Port B Input Pins bit 6 |
.equ PINB7 = 7 ; Port B Input Pins bit 7 |
; ***** PORTC ************************ |
; PORTC - Port C Data Register |
.equ PORTC0 = 0 ; Port C Data Register bit 0 |
.equ PC0 = 0 ; For compatibility |
.equ PORTC1 = 1 ; Port C Data Register bit 1 |
.equ PC1 = 1 ; For compatibility |
.equ PORTC2 = 2 ; Port C Data Register bit 2 |
.equ PC2 = 2 ; For compatibility |
.equ PORTC3 = 3 ; Port C Data Register bit 3 |
.equ PC3 = 3 ; For compatibility |
.equ PORTC4 = 4 ; Port C Data Register bit 4 |
.equ PC4 = 4 ; For compatibility |
.equ PORTC5 = 5 ; Port C Data Register bit 5 |
.equ PC5 = 5 ; For compatibility |
.equ PORTC6 = 6 ; Port C Data Register bit 6 |
.equ PC6 = 6 ; For compatibility |
.equ PORTC7 = 7 ; Port C Data Register bit 7 |
.equ PC7 = 7 ; For compatibility |
; DDRC - Port C Data Direction Register |
.equ DDC0 = 0 ; Port C Data Direction Register bit 0 |
.equ DDC1 = 1 ; Port C Data Direction Register bit 1 |
.equ DDC2 = 2 ; Port C Data Direction Register bit 2 |
.equ DDC3 = 3 ; Port C Data Direction Register bit 3 |
.equ DDC4 = 4 ; Port C Data Direction Register bit 4 |
.equ DDC5 = 5 ; Port C Data Direction Register bit 5 |
.equ DDC6 = 6 ; Port C Data Direction Register bit 6 |
.equ DDC7 = 7 ; Port C Data Direction Register bit 7 |
; PINC - Port C Input Pins |
.equ PINC0 = 0 ; Port C Input Pins bit 0 |
.equ PINC1 = 1 ; Port C Input Pins bit 1 |
.equ PINC2 = 2 ; Port C Input Pins bit 2 |
.equ PINC3 = 3 ; Port C Input Pins bit 3 |
.equ PINC4 = 4 ; Port C Input Pins bit 4 |
.equ PINC5 = 5 ; Port C Input Pins bit 5 |
.equ PINC6 = 6 ; Port C Input Pins bit 6 |
.equ PINC7 = 7 ; Port C Input Pins bit 7 |
; ***** PORTD ************************ |
; PORTD - Port D Data Register |
.equ PORTD0 = 0 ; Port D Data Register bit 0 |
.equ PD0 = 0 ; For compatibility |
.equ PORTD1 = 1 ; Port D Data Register bit 1 |
.equ PD1 = 1 ; For compatibility |
.equ PORTD2 = 2 ; Port D Data Register bit 2 |
.equ PD2 = 2 ; For compatibility |
.equ PORTD3 = 3 ; Port D Data Register bit 3 |
.equ PD3 = 3 ; For compatibility |
.equ PORTD4 = 4 ; Port D Data Register bit 4 |
.equ PD4 = 4 ; For compatibility |
.equ PORTD5 = 5 ; Port D Data Register bit 5 |
.equ PD5 = 5 ; For compatibility |
.equ PORTD6 = 6 ; Port D Data Register bit 6 |
.equ PD6 = 6 ; For compatibility |
.equ PORTD7 = 7 ; Port D Data Register bit 7 |
.equ PD7 = 7 ; For compatibility |
; DDRD - Port D Data Direction Register |
.equ DDD0 = 0 ; Port D Data Direction Register bit 0 |
.equ DDD1 = 1 ; Port D Data Direction Register bit 1 |
.equ DDD2 = 2 ; Port D Data Direction Register bit 2 |
.equ DDD3 = 3 ; Port D Data Direction Register bit 3 |
.equ DDD4 = 4 ; Port D Data Direction Register bit 4 |
.equ DDD5 = 5 ; Port D Data Direction Register bit 5 |
.equ DDD6 = 6 ; Port D Data Direction Register bit 6 |
.equ DDD7 = 7 ; Port D Data Direction Register bit 7 |
; PIND - Port D Input Pins |
.equ PIND0 = 0 ; Port D Input Pins bit 0 |
.equ PIND1 = 1 ; Port D Input Pins bit 1 |
.equ PIND2 = 2 ; Port D Input Pins bit 2 |
.equ PIND3 = 3 ; Port D Input Pins bit 3 |
.equ PIND4 = 4 ; Port D Input Pins bit 4 |
.equ PIND5 = 5 ; Port D Input Pins bit 5 |
.equ PIND6 = 6 ; Port D Input Pins bit 6 |
.equ PIND7 = 7 ; Port D Input Pins bit 7 |
; ***** PORTE ************************ |
; PORTE - Data Register, Port E |
.equ PORTE0 = 0 ; |
.equ PE0 = 0 ; For compatibility |
.equ PORTE1 = 1 ; |
.equ PE1 = 1 ; For compatibility |
.equ PORTE2 = 2 ; |
.equ PE2 = 2 ; For compatibility |
.equ PORTE3 = 3 ; |
.equ PE3 = 3 ; For compatibility |
.equ PORTE4 = 4 ; |
.equ PE4 = 4 ; For compatibility |
.equ PORTE5 = 5 ; |
.equ PE5 = 5 ; For compatibility |
.equ PORTE6 = 6 ; |
.equ PE6 = 6 ; For compatibility |
.equ PORTE7 = 7 ; |
.equ PE7 = 7 ; For compatibility |
; DDRE - Data Direction Register, Port E |
.equ DDE0 = 0 ; |
.equ DDE1 = 1 ; |
.equ DDE2 = 2 ; |
.equ DDE3 = 3 ; |
.equ DDE4 = 4 ; |
.equ DDE5 = 5 ; |
.equ DDE6 = 6 ; |
.equ DDE7 = 7 ; |
; PINE - Input Pins, Port E |
.equ PINE0 = 0 ; |
.equ PINE1 = 1 ; |
.equ PINE2 = 2 ; |
.equ PINE3 = 3 ; |
.equ PINE4 = 4 ; |
.equ PINE5 = 5 ; |
.equ PINE6 = 6 ; |
.equ PINE7 = 7 ; |
; ***** PORTF ************************ |
; PORTF - Data Register, Port F |
.equ PORTF0 = 0 ; |
.equ PF0 = 0 ; For compatibility |
.equ PORTF1 = 1 ; |
.equ PF1 = 1 ; For compatibility |
.equ PORTF2 = 2 ; |
.equ PF2 = 2 ; For compatibility |
.equ PORTF3 = 3 ; |
.equ PF3 = 3 ; For compatibility |
.equ PORTF4 = 4 ; |
.equ PF4 = 4 ; For compatibility |
.equ PORTF5 = 5 ; |
.equ PF5 = 5 ; For compatibility |
.equ PORTF6 = 6 ; |
.equ PF6 = 6 ; For compatibility |
.equ PORTF7 = 7 ; |
.equ PF7 = 7 ; For compatibility |
; DDRF - Data Direction Register, Port F |
.equ DDF0 = 0 ; |
.equ DDF1 = 1 ; |
.equ DDF2 = 2 ; |
.equ DDF3 = 3 ; |
.equ DDF4 = 4 ; |
.equ DDF5 = 5 ; |
.equ DDF6 = 6 ; |
.equ DDF7 = 7 ; |
; PINF - Input Pins, Port F |
.equ PINF0 = 0 ; |
.equ PINF1 = 1 ; |
.equ PINF2 = 2 ; |
.equ PINF3 = 3 ; |
.equ PINF4 = 4 ; |
.equ PINF5 = 5 ; |
.equ PINF6 = 6 ; |
.equ PINF7 = 7 ; |
; ***** PORTG ************************ |
; PORTG - Data Register, Port G |
.equ PORTG0 = 0 ; |
.equ PG0 = 0 ; For compatibility |
.equ PORTG1 = 1 ; |
.equ PG1 = 1 ; For compatibility |
.equ PORTG2 = 2 ; |
.equ PG2 = 2 ; For compatibility |
.equ PORTG3 = 3 ; |
.equ PG3 = 3 ; For compatibility |
.equ PORTG4 = 4 ; |
.equ PG4 = 4 ; For compatibility |
; DDRG - Data Direction Register, Port G |
.equ DDG0 = 0 ; |
.equ DDG1 = 1 ; |
.equ DDG2 = 2 ; |
.equ DDG3 = 3 ; |
.equ DDG4 = 4 ; |
; PING - Input Pins, Port G |
.equ PING0 = 0 ; |
.equ PING1 = 1 ; |
.equ PING2 = 2 ; |
.equ PING3 = 3 ; |
.equ PING4 = 4 ; |
; ***** TIMER_COUNTER_0 ************** |
; TCCR0 - Timer/Counter Control Register |
.equ CS00 = 0 ; Clock Select 0 |
.equ CS01 = 1 ; Clock Select 1 |
.equ CS02 = 2 ; Clock Select 2 |
.equ WGM01 = 3 ; Waveform Generation Mode 1 |
.equ CTC0 = WGM01 ; For compatibility |
.equ COM00 = 4 ; Compare match Output Mode 0 |
.equ COM01 = 5 ; Compare Match Output Mode 1 |
.equ WGM00 = 6 ; Waveform Generation Mode 0 |
.equ PWM0 = WGM00 ; For compatibility |
.equ FOC0 = 7 ; Force Output Compare |
; TCNT0 - Timer/Counter Register |
.equ TCNT0_0 = 0 ; |
.equ TCNT0_1 = 1 ; |
.equ TCNT0_2 = 2 ; |
.equ TCNT0_3 = 3 ; |
.equ TCNT0_4 = 4 ; |
.equ TCNT0_5 = 5 ; |
.equ TCNT0_6 = 6 ; |
.equ TCNT0_7 = 7 ; |
; OCR0 - Output Compare Register |
.equ OCR0_0 = 0 ; |
.equ OCR0_1 = 1 ; |
.equ OCR0_2 = 2 ; |
.equ OCR0_3 = 3 ; |
.equ OCR0_4 = 4 ; |
.equ OCR0_5 = 5 ; |
.equ OCR0_6 = 6 ; |
.equ OCR0_7 = 7 ; |
; ASSR - Asynchronus Status Register |
.equ TCR0UB = 0 ; Timer/Counter Control Register 0 Update Busy |
.equ OCR0UB = 1 ; Output Compare register 0 Busy |
.equ TCN0UB = 2 ; Timer/Counter0 Update Busy |
.equ AS0 = 3 ; Asynchronus Timer/Counter 0 |
; TIMSK - Timer/Counter Interrupt Mask Register |
.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable |
.equ OCIE0 = 1 ; Timer/Counter0 Output Compare Match Interrupt register |
; TIFR - Timer/Counter Interrupt Flag register |
.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag |
.equ OCF0 = 1 ; Output Compare Flag 0 |
; SFIOR - Special Function IO Register |
;.equ PSR0 = 1 ; Prescaler Reset Timer/Counter0 |
;.equ TSM = 7 ; Timer/Counter Synchronization Mode |
; ***** TIMER_COUNTER_1 ************** |
; TIMSK - Timer/Counter Interrupt Mask Register |
.equ TOIE1 = 2 ; Timer/Counter1 Overflow Interrupt Enable |
.equ OCIE1B = 3 ; Timer/Counter1 Output CompareB Match Interrupt Enable |
.equ OCIE1A = 4 ; Timer/Counter1 Output CompareA Match Interrupt Enable |
.equ TICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable |
; ETIMSK - Extended Timer/Counter Interrupt Mask Register |
.equ OCIE1C = 0 ; Timer/Counter 1, Output Compare Match C Interrupt Enable |
; TIFR - Timer/Counter Interrupt Flag register |
.equ TOV1 = 2 ; Timer/Counter1 Overflow Flag |
.equ OCF1B = 3 ; Output Compare Flag 1B |
.equ OCF1A = 4 ; Output Compare Flag 1A |
.equ ICF1 = 5 ; Input Capture Flag 1 |
; ETIFR - Extended Timer/Counter Interrupt Flag register |
.equ OCF1C = 0 ; Timer/Counter 1, Output Compare C Match Flag |
; SFIOR - Special Function IO Register |
;.equ PSR321 = 0 ; Prescaler Reset, T/C3, T/C2, T/C1 |
;.equ TSM = 7 ; Timer/Counter Synchronization Mode |
; TCCR1A - Timer/Counter1 Control Register A |
.equ WGM10 = 0 ; Waveform Generation Mode Bit 0 |
.equ PWM10 = WGM10 ; For compatibility |
.equ WGM11 = 1 ; Waveform Generation Mode Bit 1 |
.equ PWM11 = WGM11 ; For compatibility |
.equ COM1C0 = 2 ; Compare Output Mode 1C, bit 0 |
.equ COM1C1 = 3 ; Compare Output Mode 1C, bit 1 |
.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0 |
.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1 |
.equ COM1A0 = 6 ; Compare Ouput Mode 1A, bit 0 |
.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1 |
; TCCR1B - Timer/Counter1 Control Register B |
.equ CS10 = 0 ; Clock Select bit 0 |
.equ CS11 = 1 ; Clock Select 1 bit 1 |
.equ CS12 = 2 ; Clock Select1 bit 2 |
.equ WGM12 = 3 ; Waveform Generation Mode |
.equ CTC10 = WGM12 ; For compatibility |
.equ WGM13 = 4 ; Waveform Generation Mode |
.equ CTC11 = WGM13 ; For compatibility |
.equ ICES1 = 6 ; Input Capture 1 Edge Select |
.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler |
; TCCR1C - Timer/Counter1 Control Register C |
.equ FOC1C = 5 ; Force Output Compare for channel C |
.equ FOC1B = 6 ; Force Output Compare for channel B |
.equ FOC1A = 7 ; Force Output Compare for channel A |
; ***** TIMER_COUNTER_2 ************** |
; TCCR2 - Timer/Counter Control Register |
.equ CS20 = 0 ; Clock Select |
.equ CS21 = 1 ; Clock Select |
.equ CS22 = 2 ; Clock Select |
.equ WGM21 = 3 ; Waveform Generation Mode |
.equ CTC2 = WGM21 ; For compatibility |
.equ COM20 = 4 ; Compare Match Output Mode |
.equ COM21 = 5 ; Compare Match Output Mode |
.equ WGM20 = 6 ; Wafeform Generation Mode |
.equ PWM2 = WGM20 ; For compatibility |
.equ FOC2 = 7 ; Force Output Compare |
; TCNT2 - Timer/Counter Register |
.equ TCNT2_0 = 0 ; Timer/Counter Register Bit 0 |
.equ TCNT2_1 = 1 ; Timer/Counter Register Bit 1 |
.equ TCNT2_2 = 2 ; Timer/Counter Register Bit 2 |
.equ TCNT2_3 = 3 ; Timer/Counter Register Bit 3 |
.equ TCNT2_4 = 4 ; Timer/Counter Register Bit 4 |
.equ TCNT2_5 = 5 ; Timer/Counter Register Bit 5 |
.equ TCNT2_6 = 6 ; Timer/Counter Register Bit 6 |
.equ TCNT2_7 = 7 ; Timer/Counter Register Bit 7 |
; OCR2 - Output Compare Register |
.equ OCR2_0 = 0 ; Output Compare Register Bit 0 |
.equ OCR2_1 = 1 ; Output Compare Register Bit 1 |
.equ OCR2_2 = 2 ; Output Compare Register Bit 2 |
.equ OCR2_3 = 3 ; Output Compare Register Bit 3 |
.equ OCR2_4 = 4 ; Output Compare Register Bit 4 |
.equ OCR2_5 = 5 ; Output Compare Register Bit 5 |
.equ OCR2_6 = 6 ; Output Compare Register Bit 6 |
.equ OCR2_7 = 7 ; Output Compare Register Bit 7 |
; TIMSK - |
.equ TOIE2 = 6 ; |
.equ OCIE2 = 7 ; |
; TIFR - Timer/Counter Interrupt Flag Register |
.equ TOV2 = 6 ; Timer/Counter2 Overflow Flag |
.equ OCF2 = 7 ; Output Compare Flag 2 |
; ***** TIMER_COUNTER_3 ************** |
; ETIMSK - Extended Timer/Counter Interrupt Mask Register |
.equ OCIE3C = 1 ; Timer/Counter3, Output Compare Match Interrupt Enable |
.equ TOIE3 = 2 ; Timer/Counter3 Overflow Interrupt Enable |
.equ OCIE3B = 3 ; Timer/Counter3 Output CompareB Match Interrupt Enable |
.equ OCIE3A = 4 ; Timer/Counter3 Output CompareA Match Interrupt Enable |
.equ TICIE3 = 5 ; Timer/Counter3 Input Capture Interrupt Enable |
; ETIFR - Extended Timer/Counter Interrupt Flag register |
.equ OCF3C = 1 ; Timer/Counter3 Output Compare C Match Flag |
.equ TOV3 = 2 ; Timer/Counter3 Overflow Flag |
.equ OCF3B = 3 ; Output Compare Flag 1B |
.equ OCF3A = 4 ; Output Compare Flag 1A |
.equ ICF3 = 5 ; Input Capture Flag 1 |
; SFIOR - Special Function IO Register |
;.equ PSR321 = 0 ; Prescaler Reset, T/C3, T/C2, T/C1 |
;.equ PSR1 = PSR321 ; For compatibility |
;.equ PSR2 = PSR321 ; For compatibility |
;.equ TSM = 7 ; Timer/Counter Synchronization Mode |
; TCCR3A - Timer/Counter3 Control Register A |
.equ WGM30 = 0 ; Waveform Generation Mode Bit 0 |
.equ PWM30 = WGM30 ; For compatibility |
.equ WGM31 = 1 ; Waveform Generation Mode Bit 1 |
.equ PWM31 = WGM31 ; For compatibility |
.equ COM3C0 = 2 ; Compare Output Mode 3C, bit 0 |
.equ COM3C1 = 3 ; Compare Output Mode 3C, bit 1 |
.equ COM3B0 = 4 ; Compare Output Mode 3B, bit 0 |
.equ COM3B1 = 5 ; Compare Output Mode 3B, bit 1 |
.equ COM3A0 = 6 ; Comparet Ouput Mode 3A, bit 0 |
.equ COM3A1 = 7 ; Compare Output Mode 3A, bit 1 |
; TCCR3B - Timer/Counter3 Control Register B |
.equ CS30 = 0 ; Clock Select 3 bit 0 |
.equ CS31 = 1 ; Clock Select 3 bit 1 |
.equ CS32 = 2 ; Clock Select3 bit 2 |
.equ WGM32 = 3 ; Waveform Generation Mode |
.equ CTC30 = WGM32 ; For compatibility |
.equ WGM33 = 4 ; Waveform Generation Mode |
.equ CTC31 = WGM33 ; For compatibility |
.equ ICES3 = 6 ; Input Capture 3 Edge Select |
.equ ICNC3 = 7 ; Input Capture 3 Noise Canceler |
; TCCR3C - Timer/Counter3 Control Register C |
.equ FOC3C = 5 ; Force Output Compare for channel C |
.equ FOC3B = 6 ; Force Output Compare for channel B |
.equ FOC3A = 7 ; Force Output Compare for channel A |
; ***** WATCHDOG ********************* |
; WDTCR - Watchdog Timer Control Register |
.equ WDTCSR = WDTCR ; For compatibility |
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 |
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 |
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 |
.equ WDE = 3 ; Watch Dog Enable |
.equ WDCE = 4 ; Watchdog Change Enable |
.equ WDTOE = WDCE ; For compatibility |
; ***** LOCKSBITS ******************************************************** |
.equ LB1 = 0 ; Lock bit |
.equ LB2 = 1 ; Lock bit |
.equ BLB01 = 2 ; Boot Lock bit |
.equ BLB02 = 3 ; Boot Lock bit |
.equ BLB11 = 4 ; Boot lock bit |
.equ BLB12 = 5 ; Boot lock bit |
; ***** FUSES ************************************************************ |
; LOW fuse bits |
.equ CKSEL0 = 0 ; Select Clock Source |
.equ CKSEL1 = 1 ; Select Clock Source |
.equ CKSEL2 = 2 ; Select Clock Source |
.equ CKSEL3 = 3 ; Select Clock Source |
.equ SUT0 = 4 ; Select start-up time |
.equ SUT1 = 5 ; Select start-up time |
.equ BODEN = 6 ; Brown out detector enable |
.equ BODLEVEL = 7 ; Brown out detector trigger level |
; HIGH fuse bits |
.equ BOOTRST = 0 ; Select Reset Vector |
.equ BOOTSZ0 = 1 ; Select Boot Size |
.equ BOOTSZ1 = 2 ; Select Boot Size |
.equ EESAVE = 3 ; EEPROM memory is preserved through chip erase |
.equ CKOPT = 4 ; Oscillator Options |
.equ SPIEN = 5 ; Enable Serial programming and Data Downloading |
.equ JTAGEN = 6 ; Enable JTAG |
.equ OCDEN = 7 ; Enable OCD |
; EXTENDED fuse bits |
.equ WDTON = 0 ; Watchdog timer always on |
.equ M103C = 1 ; ATmega103 compatibility mode |
; ***** CPU REGISTER DEFINITIONS ***************************************** |
.def XH = r27 |
.def XL = r26 |
.def YH = r29 |
.def YL = r28 |
.def ZH = r31 |
.def ZL = r30 |
; ***** DATA MEMORY DECLARATIONS ***************************************** |
.equ FLASHEND = 0xffff ; Note: Word address |
.equ IOEND = 0x00ff |
.equ SRAM_START = 0x0100 |
.equ SRAM_SIZE = 4096 |
.equ RAMEND = 0x10ff |
.equ XRAMEND = 0xffff |
.equ E2END = 0x0fff |
.equ EEPROMEND = 0x0fff |
.equ EEADRBITS = 12 |
#pragma AVRPART MEMORY PROG_FLASH 131072 |
#pragma AVRPART MEMORY EEPROM 4096 |
#pragma AVRPART MEMORY INT_SRAM SIZE 4096 |
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x100 |
; ***** BOOTLOADER DECLARATIONS ****************************************** |
.equ NRWW_START_ADDR = 0xf000 |
.equ NRWW_STOP_ADDR = 0xffff |
.equ RWW_START_ADDR = 0x0 |
.equ RWW_STOP_ADDR = 0xefff |
.equ PAGESIZE = 128 |
.equ FIRSTBOOTSTART = 0xfe00 |
.equ SECONDBOOTSTART = 0xfc00 |
.equ THIRDBOOTSTART = 0xf800 |
.equ FOURTHBOOTSTART = 0xf000 |
.equ SMALLBOOTSTART = FIRSTBOOTSTART |
.equ LARGEBOOTSTART = FOURTHBOOTSTART |
; ***** INTERRUPT VECTORS ************************************************ |
.equ INT0addr = 0x0002 ; External Interrupt Request 0 |
.equ INT1addr = 0x0004 ; External Interrupt Request 1 |
.equ INT2addr = 0x0006 ; External Interrupt Request 2 |
.equ INT3addr = 0x0008 ; External Interrupt Request 3 |
.equ INT4addr = 0x000a ; External Interrupt Request 4 |
.equ INT5addr = 0x000c ; External Interrupt Request 5 |
.equ INT6addr = 0x000e ; External Interrupt Request 6 |
.equ INT7addr = 0x0010 ; External Interrupt Request 7 |
.equ OC2addr = 0x0012 ; Timer/Counter2 Compare Match |
.equ OVF2addr = 0x0014 ; Timer/Counter2 Overflow |
.equ ICP1addr = 0x0016 ; Timer/Counter1 Capture Event |
.equ OC1Aaddr = 0x0018 ; Timer/Counter1 Compare Match A |
.equ OC1Baddr = 0x001a ; Timer/Counter Compare Match B |
.equ OVF1addr = 0x001c ; Timer/Counter1 Overflow |
.equ OC0addr = 0x001e ; Timer/Counter0 Compare Match |
.equ OVF0addr = 0x0020 ; Timer/Counter0 Overflow |
.equ SPIaddr = 0x0022 ; SPI Serial Transfer Complete |
.equ URXC0addr = 0x0024 ; USART0, Rx Complete |
.equ UDRE0addr = 0x0026 ; USART0 Data Register Empty |
.equ UTXC0addr = 0x0028 ; USART0, Tx Complete |
.equ ADCCaddr = 0x002a ; ADC Conversion Complete |
.equ ERDYaddr = 0x002c ; EEPROM Ready |
.equ ACIaddr = 0x002e ; Analog Comparator |
.equ OC1Caddr = 0x0030 ; Timer/Counter1 Compare Match C |
.equ ICP3addr = 0x0032 ; Timer/Counter3 Capture Event |
.equ OC3Aaddr = 0x0034 ; Timer/Counter3 Compare Match A |
.equ OC3Baddr = 0x0036 ; Timer/Counter3 Compare Match B |
.equ OC3Caddr = 0x0038 ; Timer/Counter3 Compare Match C |
.equ OVF3addr = 0x003a ; Timer/Counter3 Overflow |
.equ URXC1addr = 0x003c ; USART1, Rx Complete |
.equ UDRE1addr = 0x003e ; USART1, Data Register Empty |
.equ UTXC1addr = 0x0040 ; USART1, Tx Complete |
.equ TWIaddr = 0x0042 ; 2-wire Serial Interface |
.equ SPMRaddr = 0x0044 ; Store Program Memory Read |
.equ INT_VECTORS_SIZE = 70 ; size in words |
#endif /* _M128DEF_INC_ */ |
; ***** END OF FILE ****************************************************** |
/contrib/toolchain/avra/includes/m161def.inc |
---|
0,0 → 1,736 |
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** |
;***** Created: 2005-01-11 10:30 ******* Source: ATmega161.xml *********** |
;************************************************************************* |
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y |
;* |
;* Number : AVR000 |
;* File Name : "m161def.inc" |
;* Title : Register/Bit Definitions for the ATmega161 |
;* Date : 2005-01-11 |
;* Version : 2.14 |
;* Support E-mail : avr@atmel.com |
;* Target MCU : ATmega161 |
;* |
;* DESCRIPTION |
;* When including this file in the assembly program file, all I/O register |
;* names and I/O register bit names appearing in the data book can be used. |
;* In addition, the six registers forming the three data pointers X, Y and |
;* Z have been assigned names XL - ZH. Highest RAM address for Internal |
;* SRAM is also defined |
;* |
;* The Register names are represented by their hexadecimal address. |
;* |
;* The Register Bit names are represented by their bit number (0-7). |
;* |
;* Please observe the difference in using the bit names with instructions |
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" |
;* (skip if bit in register set/cleared). The following example illustrates |
;* this: |
;* |
;* in r16,PORTB ;read PORTB latch |
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) |
;* out PORTB,r16 ;output to PORTB |
;* |
;* in r16,TIFR ;read the Timer Interrupt Flag Register |
;* sbrc r16,TOV0 ;test the overflow flag (use bit#) |
;* rjmp TOV0_is_set ;jump if set |
;* ... ;otherwise do something else |
;************************************************************************* |
#ifndef _M161DEF_INC_ |
#define _M161DEF_INC_ |
#pragma partinc 0 |
; ***** SPECIFY DEVICE *************************************************** |
.device ATmega161 |
#pragma AVRPART ADMIN PART_NAME ATmega161 |
.equ SIGNATURE_000 = 0x1e |
.equ SIGNATURE_001 = 0x94 |
.equ SIGNATURE_002 = 0x01 |
#pragma AVRPART CORE CORE_VERSION V2E |
; ***** I/O REGISTER DEFINITIONS ***************************************** |
; NOTE: |
; Definitions marked "MEMORY MAPPED"are extended I/O ports |
; and cannot be used with IN/OUT instructions |
.equ SREG = 0x3f |
.equ SPH = 0x3e |
.equ SPL = 0x3d |
.equ GIMSK = 0x3b |
.equ GIFR = 0x3a |
.equ TIMSK = 0x39 |
.equ TIFR = 0x38 |
.equ SPMCR = 0x37 |
.equ EMCUCR = 0x36 |
.equ MCUCR = 0x35 |
.equ MCUSR = 0x34 |
.equ TCCR0 = 0x33 |
.equ TCNT0 = 0x32 |
.equ OCR0 = 0x31 |
.equ SFIOR = 0x30 |
.equ TCCR1A = 0x2f |
.equ TCCR1B = 0x2e |
.equ TCNT1H = 0x2d |
.equ TCNT1L = 0x2c |
.equ OCR1AH = 0x2b |
.equ OCR1AL = 0x2a |
.equ OCR1BH = 0x29 |
.equ OCR1BL = 0x28 |
.equ TCCR2 = 0x27 |
.equ ASSR = 0x26 |
.equ ICR1H = 0x25 |
.equ ICR1L = 0x24 |
.equ TCNT2 = 0x23 |
.equ OCR2 = 0x22 |
.equ WDTCR = 0x21 |
.equ UBRRHI = 0x20 |
.equ EEARH = 0x1f |
.equ EEARL = 0x1e |
.equ EEDR = 0x1d |
.equ EECR = 0x1c |
.equ PORTA = 0x1b |
.equ DDRA = 0x1a |
.equ PINA = 0x19 |
.equ PORTB = 0x18 |
.equ DDRB = 0x17 |
.equ PINB = 0x16 |
.equ PORTC = 0x15 |
.equ DDRC = 0x14 |
.equ PINC = 0x13 |
.equ PORTD = 0x12 |
.equ DDRD = 0x11 |
.equ PIND = 0x10 |
.equ SPDR = 0x0f |
.equ SPSR = 0x0e |
.equ SPCR = 0x0d |
.equ UDR0 = 0x0c |
.equ UCSR0A = 0x0b |
.equ UCSR0B = 0x0a |
.equ UBRR0 = 0x09 |
.equ ACSR = 0x08 |
.equ PORTE = 0x07 |
.equ DDRE = 0x06 |
.equ PINE = 0x05 |
.equ UDR1 = 0x03 |
.equ UCSR1A = 0x02 |
.equ UCSR1B = 0x01 |
.equ UBRR1 = 0x00 |
; ***** BIT DEFINITIONS ************************************************** |
; ***** ANALOG_COMPARATOR ************ |
; ACSR - Analog Comparator Control And Status Register |
.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 |
.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 |
.equ ACIC = 2 ; Analog Comparator Input Capture Enable |
.equ ACIE = 3 ; Analog Comparator Interrupt Enable |
.equ ACI = 4 ; Analog Comparator Interrupt Flag |
.equ ACO = 5 ; Analog Compare Output |
.equ AINBG = 6 ; Analog Comparator Bandgap Select |
.equ ACD = 7 ; Analog Comparator Disable |
; ***** SPI ************************** |
; SPDR - SPI Data Register |
.equ SPDR0 = 0 ; SPI Data Register bit 0 |
.equ SPDR1 = 1 ; SPI Data Register bit 1 |
.equ SPDR2 = 2 ; SPI Data Register bit 2 |
.equ SPDR3 = 3 ; SPI Data Register bit 3 |
.equ SPDR4 = 4 ; SPI Data Register bit 4 |
.equ SPDR5 = 5 ; SPI Data Register bit 5 |
.equ SPDR6 = 6 ; SPI Data Register bit 6 |
.equ SPDR7 = 7 ; SPI Data Register bit 7 |
; SPSR - SPI Status Register |
.equ SPI2X = 0 ; Double SPI Speed Bit |
.equ WCOL = 6 ; Write Collision Flag |
.equ SPIF = 7 ; SPI Interrupt Flag |
; SPCR - SPI Control Register |
.equ SPR0 = 0 ; SPI Clock Rate Select 0 |
.equ SPR1 = 1 ; SPI Clock Rate Select 1 |
.equ CPHA = 2 ; Clock Phase |
.equ CPOL = 3 ; Clock polarity |
.equ MSTR = 4 ; Master/Slave Select |
.equ DORD = 5 ; Data Order |
.equ SPE = 6 ; SPI Enable |
.equ SPIE = 7 ; SPI Interrupt Enable |
; ***** USART0 *********************** |
; UDR0 - USART I/O Data Register |
.equ UDR00 = 0 ; USART I/O Data Register bit 0 |
.equ UDR01 = 1 ; USART I/O Data Register bit 1 |
.equ UDR02 = 2 ; USART I/O Data Register bit 2 |
.equ UDR03 = 3 ; USART I/O Data Register bit 3 |
.equ UDR04 = 4 ; USART I/O Data Register bit 4 |
.equ UDR05 = 5 ; USART I/O Data Register bit 5 |
.equ UDR06 = 6 ; USART I/O Data Register bit 6 |
.equ UDR07 = 7 ; USART I/O Data Register bit 7 |
; UCSR0A - USART Control and Status Register A |
.equ MPCM0 = 0 ; Multi-processor Communication Mode |
.equ U2X0 = 1 ; Double the USART transmission speed |
.equ OR0 = 3 ; Data overRun |
.equ FE0 = 4 ; Framing Error |
.equ UDRE0 = 5 ; USART Data Register Empty |
.equ TXC0 = 6 ; USART Transmitt Complete |
.equ RXC0 = 7 ; USART Receive Complete |
; UCSR0B - USART Control and Status Register B |
.equ TXB80 = 0 ; Transmit Data Bit 8 |
.equ RXB80 = 1 ; Receive Data Bit 8 |
.equ CHR90 = 2 ; 9-Bit Character |
.equ TXEN0 = 3 ; Transmitter Enable |
.equ RXEN0 = 4 ; Receiver Enable |
.equ UDR0IE0 = 5 ; USART Data register Empty Interrupt Enable |
.equ TXCIE0 = 6 ; TX Complete Interrupt Enable |
.equ RXCIE0 = 7 ; RX Complete Interrupt Enable |
; UBRR0 - USART Baud Rate Register Byte |
.equ UBRR00 = 0 ; USART Baud Rate Register bit 0 |
.equ UBRR01 = 1 ; USART Baud Rate Register bit 1 |
.equ UBRR02 = 2 ; USART Baud Rate Register bit 2 |
.equ UBRR03 = 3 ; USART Baud Rate Register bit 3 |
.equ UBRR04 = 4 ; USART Baud Rate Register bit 4 |
.equ UBRR05 = 5 ; USART Baud Rate Register bit 5 |
.equ UBRR06 = 6 ; USART Baud Rate Register bit 6 |
.equ UBRR07 = 7 ; USART Baud Rate Register bit 7 |
; UBRRHI - High Byte Baud Rate Register |
.equ UBRRHI00 = 0 ; High Byte Baud Rate Register Port 0 Bit 0 |
.equ UBRRHI01 = 1 ; High Byte Baud Rate Register Port 0 Bit 1 |
.equ UBRRHI02 = 2 ; High Byte Baud Rate Register Port 0 Bit 2 |
.equ UBRRHI03 = 3 ; High Byte Baud Rate Register Port 0 Bit 3 |
; ***** USART1 *********************** |
; UDR1 - USART I/O Data Register |
.equ UDR10 = 0 ; USART I/O Data Register bit 0 |
.equ UDR11 = 1 ; USART I/O Data Register bit 1 |
.equ UDR12 = 2 ; USART I/O Data Register bit 2 |
.equ UDR13 = 3 ; USART I/O Data Register bit 3 |
.equ UDR14 = 4 ; USART I/O Data Register bit 4 |
.equ UDR15 = 5 ; USART I/O Data Register bit 5 |
.equ UDR16 = 6 ; USART I/O Data Register bit 6 |
.equ UDR17 = 7 ; USART I/O Data Register bit 7 |
; UCSR1A - USART Control and Status Register A |
.equ MPCM1 = 0 ; Multi-processor Communication Mode |
.equ U2X1 = 1 ; Double the USART transmission speed |
.equ OR1 = 3 ; Data overRun |
.equ FE1 = 4 ; Framing Error |
.equ UDRE1 = 5 ; USART Data Register Empty |
.equ TXC1 = 6 ; USART Transmitt Complete |
.equ RXC1 = 7 ; USART Receive Complete |
; UCSR1B - USART Control and Status Register B |
.equ TXB81 = 0 ; Transmit Data Bit 8 |
.equ RXB81 = 1 ; Receive Data Bit 8 |
.equ CHR91 = 2 ; 9-Bit Character |
.equ TXEN1 = 3 ; Transmitter Enable |
.equ RXEN1 = 4 ; Receiver Enable |
.equ UDR1IE1 = 5 ; USART Data register Empty Interrupt Enable |
.equ TXCIE1 = 6 ; TX Complete Interrupt Enable |
.equ RXCIE1 = 7 ; RX Complete Interrupt Enable |
; UBRR1 - USART Baud Rate Register Byte |
.equ UBRR10 = 0 ; USART Baud Rate Register bit 0 |
.equ UBRR11 = 1 ; USART Baud Rate Register bit 1 |
.equ UBRR12 = 2 ; USART Baud Rate Register bit 2 |
.equ UBRR13 = 3 ; USART Baud Rate Register bit 3 |
.equ UBRR14 = 4 ; USART Baud Rate Register bit 4 |
.equ UBRR15 = 5 ; USART Baud Rate Register bit 5 |
.equ UBRR16 = 6 ; USART Baud Rate Register bit 6 |
.equ UBRR17 = 7 ; USART Baud Rate Register bit 7 |
; UBRRHI - high Byte Baud Rate Register |
.equ UBRRHI10 = 4 ; High Byte Baud Rate Register Port 0 Bit 0 |
.equ UBRRHI11 = 5 ; High Byte Baud Rate Register Port 0 Bit 1 |
.equ UBRRHI12 = 6 ; High Byte Baud Rate Register Port 0 Bit 2 |
.equ UBRRHI13 = 7 ; High Byte Baud Rate Register Port 0 Bit 3 |
; ***** PORTA ************************ |
; PORTA - Port A Data Register |
.equ PORTA0 = 0 ; Port A Data Register bit 0 |
.equ PA0 = 0 ; For compatibility |
.equ PORTA1 = 1 ; Port A Data Register bit 1 |
.equ PA1 = 1 ; For compatibility |
.equ PORTA2 = 2 ; Port A Data Register bit 2 |
.equ PA2 = 2 ; For compatibility |
.equ PORTA3 = 3 ; Port A Data Register bit 3 |
.equ PA3 = 3 ; For compatibility |
.equ PORTA4 = 4 ; Port A Data Register bit 4 |
.equ PA4 = 4 ; For compatibility |
.equ PORTA5 = 5 ; Port A Data Register bit 5 |
.equ PA5 = 5 ; For compatibility |
.equ PORTA6 = 6 ; Port A Data Register bit 6 |
.equ PA6 = 6 ; For compatibility |
.equ PORTA7 = 7 ; Port A Data Register bit 7 |
.equ PA7 = 7 ; For compatibility |
; DDRA - Port A Data Direction Register |
.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0 |
.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1 |
.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2 |
.equ DDA3 = 3 ; Data Direction Register, Port A, bit 3 |
.equ DDA4 = 4 ; Data Direction Register, Port A, bit 4 |
.equ DDA5 = 5 ; Data Direction Register, Port A, bit 5 |
.equ DDA6 = 6 ; Data Direction Register, Port A, bit 6 |
.equ DDA7 = 7 ; Data Direction Register, Port A, bit 7 |
; PINA - Port A Input Pins |
.equ PINA0 = 0 ; Input Pins, Port A bit 0 |
.equ PINA1 = 1 ; Input Pins, Port A bit 1 |
.equ PINA2 = 2 ; Input Pins, Port A bit 2 |
.equ PINA3 = 3 ; Input Pins, Port A bit 3 |
.equ PINA4 = 4 ; Input Pins, Port A bit 4 |
.equ PINA5 = 5 ; Input Pins, Port A bit 5 |
.equ PINA6 = 6 ; Input Pins, Port A bit 6 |
.equ PINA7 = 7 ; Input Pins, Port A bit 7 |
; ***** PORTB ************************ |
; PORTB - Port B Data Register |
.equ PORTB0 = 0 ; Port B Data Register bit 0 |
.equ PB0 = 0 ; For compatibility |
.equ PORTB1 = 1 ; Port B Data Register bit 1 |
.equ PB1 = 1 ; For compatibility |
.equ PORTB2 = 2 ; Port B Data Register bit 2 |
.equ PB2 = 2 ; For compatibility |
.equ PORTB3 = 3 ; Port B Data Register bit 3 |
.equ PB3 = 3 ; For compatibility |
.equ PORTB4 = 4 ; Port B Data Register bit 4 |
.equ PB4 = 4 ; For compatibility |
.equ PORTB5 = 5 ; Port B Data Register bit 5 |
.equ PB5 = 5 ; For compatibility |
.equ PORTB6 = 6 ; Port B Data Register bit 6 |
.equ PB6 = 6 ; For compatibility |
.equ PORTB7 = 7 ; Port B Data Register bit 7 |
.equ PB7 = 7 ; For compatibility |
; DDRB - Port B Data Direction Register |
.equ DDB0 = 0 ; Port B Data Direction Register bit 0 |
.equ DDB1 = 1 ; Port B Data Direction Register bit 1 |
.equ DDB2 = 2 ; Port B Data Direction Register bit 2 |
.equ DDB3 = 3 ; Port B Data Direction Register bit 3 |
.equ DDB4 = 4 ; Port B Data Direction Register bit 4 |
.equ DDB5 = 5 ; Port B Data Direction Register bit 5 |
.equ DDB6 = 6 ; Port B Data Direction Register bit 6 |
.equ DDB7 = 7 ; Port B Data Direction Register bit 7 |
; PINB - Port B Input Pins |
.equ PINB0 = 0 ; Port B Input Pins bit 0 |
.equ PINB1 = 1 ; Port B Input Pins bit 1 |
.equ PINB2 = 2 ; Port B Input Pins bit 2 |
.equ PINB3 = 3 ; Port B Input Pins bit 3 |
.equ PINB4 = 4 ; Port B Input Pins bit 4 |
.equ PINB5 = 5 ; Port B Input Pins bit 5 |
.equ PINB6 = 6 ; Port B Input Pins bit 6 |
.equ PINB7 = 7 ; Port B Input Pins bit 7 |
; ***** PORTC ************************ |
; PORTC - Port C Data Register |
.equ PORTC0 = 0 ; Port C Data Register bit 0 |
.equ PC0 = 0 ; For compatibility |
.equ PORTC1 = 1 ; Port C Data Register bit 1 |
.equ PC1 = 1 ; For compatibility |
.equ PORTC2 = 2 ; Port C Data Register bit 2 |
.equ PC2 = 2 ; For compatibility |
.equ PORTC3 = 3 ; Port C Data Register bit 3 |
.equ PC3 = 3 ; For compatibility |
.equ PORTC4 = 4 ; Port C Data Register bit 4 |
.equ PC4 = 4 ; For compatibility |
.equ PORTC5 = 5 ; Port C Data Register bit 5 |
.equ PC5 = 5 ; For compatibility |
.equ PORTC6 = 6 ; Port C Data Register bit 6 |
.equ PC6 = 6 ; For compatibility |
.equ PORTC7 = 7 ; Port C Data Register bit 7 |
.equ PC7 = 7 ; For compatibility |
; DDRC - Port C Data Direction Register |
.equ DDC0 = 0 ; Port C Data Direction Register bit 0 |
.equ DDC1 = 1 ; Port C Data Direction Register bit 1 |
.equ DDC2 = 2 ; Port C Data Direction Register bit 2 |
.equ DDC3 = 3 ; Port C Data Direction Register bit 3 |
.equ DDC4 = 4 ; Port C Data Direction Register bit 4 |
.equ DDC5 = 5 ; Port C Data Direction Register bit 5 |
.equ DDC6 = 6 ; Port C Data Direction Register bit 6 |
.equ DDC7 = 7 ; Port C Data Direction Register bit 7 |
; PINC - Port C Input Pins |
.equ PINC0 = 0 ; Port C Input Pins bit 0 |
.equ PINC1 = 1 ; Port C Input Pins bit 1 |
.equ PINC2 = 2 ; Port C Input Pins bit 2 |
.equ PINC3 = 3 ; Port C Input Pins bit 3 |
.equ PINC4 = 4 ; Port C Input Pins bit 4 |
.equ PINC5 = 5 ; Port C Input Pins bit 5 |
.equ PINC6 = 6 ; Port C Input Pins bit 6 |
.equ PINC7 = 7 ; Port C Input Pins bit 7 |
; ***** PORTD ************************ |
; PORTD - Port D Data Register |
.equ PORTD0 = 0 ; Port D Data Register bit 0 |
.equ PD0 = 0 ; For compatibility |
.equ PORTD1 = 1 ; Port D Data Register bit 1 |
.equ PD1 = 1 ; For compatibility |
.equ PORTD2 = 2 ; Port D Data Register bit 2 |
.equ PD2 = 2 ; For compatibility |
.equ PORTD3 = 3 ; Port D Data Register bit 3 |
.equ PD3 = 3 ; For compatibility |
.equ PORTD4 = 4 ; Port D Data Register bit 4 |
.equ PD4 = 4 ; For compatibility |
.equ PORTD5 = 5 ; Port D Data Register bit 5 |
.equ PD5 = 5 ; For compatibility |
.equ PORTD6 = 6 ; Port D Data Register bit 6 |
.equ PD6 = 6 ; For compatibility |
.equ PORTD7 = 7 ; Port D Data Register bit 7 |
.equ PD7 = 7 ; For compatibility |
; DDRD - Port D Data Direction Register |
.equ DDD0 = 0 ; Port D Data Direction Register bit 0 |
.equ DDD1 = 1 ; Port D Data Direction Register bit 1 |
.equ DDD2 = 2 ; Port D Data Direction Register bit 2 |
.equ DDD3 = 3 ; Port D Data Direction Register bit 3 |
.equ DDD4 = 4 ; Port D Data Direction Register bit 4 |
.equ DDD5 = 5 ; Port D Data Direction Register bit 5 |
.equ DDD6 = 6 ; Port D Data Direction Register bit 6 |
.equ DDD7 = 7 ; Port D Data Direction Register bit 7 |
; PIND - Port D Input Pins |
.equ PIND0 = 0 ; Port D Input Pins bit 0 |
.equ PIND1 = 1 ; Port D Input Pins bit 1 |
.equ PIND2 = 2 ; Port D Input Pins bit 2 |
.equ PIND3 = 3 ; Port D Input Pins bit 3 |
.equ PIND4 = 4 ; Port D Input Pins bit 4 |
.equ PIND5 = 5 ; Port D Input Pins bit 5 |
.equ PIND6 = 6 ; Port D Input Pins bit 6 |
.equ PIND7 = 7 ; Port D Input Pins bit 7 |
; ***** PORTE ************************ |
; PORTE - Port E Data Register |
.equ PORTE0 = 0 ; |
.equ PE0 = 0 ; For compatibility |
.equ PORTE1 = 1 ; |
.equ PE1 = 1 ; For compatibility |
.equ PORTE2 = 2 ; |
.equ PE2 = 2 ; For compatibility |
; DDRE - Port E Data Direction Register |
.equ DDE0 = 0 ; |
.equ DDE1 = 1 ; |
.equ DDE2 = 2 ; |
; PINE - Port E Input Pins |
.equ PINE0 = 0 ; |
.equ PINE1 = 1 ; |
.equ PINE2 = 2 ; |
; ***** EEPROM *********************** |
; EEDR - EEPROM Data Register |
.equ EEDR0 = 0 ; EEPROM Data Register bit 0 |
.equ EEDR1 = 1 ; EEPROM Data Register bit 1 |
.equ EEDR2 = 2 ; EEPROM Data Register bit 2 |
.equ EEDR3 = 3 ; EEPROM Data Register bit 3 |
.equ EEDR4 = 4 ; EEPROM Data Register bit 4 |
.equ EEDR5 = 5 ; EEPROM Data Register bit 5 |
.equ EEDR6 = 6 ; EEPROM Data Register bit 6 |
.equ EEDR7 = 7 ; EEPROM Data Register bit 7 |
; EECR - EEPROM Control Register |
.equ EERE = 0 ; EEPROM Read Enable |
.equ EEWE = 1 ; EEPROM Write Enable |
.equ EEMWE = 2 ; EEPROM Master Write Enable |
.equ EEWEE = EEMWE ; For compatibility |
.equ EERIE = 3 ; EEPROM Ready Interrupt Enable |
; ***** EXTERNAL_INTERRUPT *********** |
; GIMSK - General Interrupt Mask Register |
.equ INT2 = 5 ; External Interrupt Request 2 Enable |
.equ INT0 = 6 ; External Interrupt Request 0 Enable |
.equ INT1 = 7 ; External Interrupt Request 1 Enable |
; GIFR - General Interrupt Flag Register |
.equ INTF2 = 5 ; External Interrupt Flag 2 |
.equ INTF0 = 6 ; External Interrupt Flag 0 |
.equ INTF1 = 7 ; External Interrupt Flag 1 |
; ***** CPU ************************** |
; SREG - Status Register |
.equ SREG_C = 0 ; Carry Flag |
.equ SREG_Z = 1 ; Zero Flag |
.equ SREG_N = 2 ; Negative Flag |
.equ SREG_V = 3 ; Two's Complement Overflow Flag |
.equ SREG_S = 4 ; Sign Bit |
.equ SREG_H = 5 ; Half Carry Flag |
.equ SREG_T = 6 ; Bit Copy Storage |
.equ SREG_I = 7 ; Global Interrupt Enable |
; MCUCR - MCU Control Register |
.equ ISC00 = 0 ; Interrupt Sense Control 0 bit 0 |
.equ ISC01 = 1 ; Interrupt Sense Control 0 bit 1 |
.equ ISC10 = 2 ; Interrupt Sense Control 1 bit 1 |
.equ ISC11 = 3 ; Interrupt Sense Control 1 bit 1 |
.equ SM1 = 4 ; Sleep Mode Select |
.equ SE = 5 ; Sleep Enable |
.equ SRW10 = 6 ; External SRAM Wait State Select |
.equ SRE = 7 ; External SRAM Enable |
; MCUSR - MCU Status Register |
.equ PORF = 0 ; Power-on reset flag |
.equ EXTRF = 1 ; External Reset Flag |
.equ BORF = 2 ; Brown-out Reset Flag |
.equ WDRF = 3 ; Watchdog Reset Flag |
; EMCUCR - Extended MCU Control Register |
.equ ISC2 = 0 ; Interrupt Sense Control 2 |
.equ SRW11 = 1 ; Wait State Select Bit 1 for Upper Sector |
.equ SRW00 = 2 ; Wait State Select Bit 0 for Lower Sector |
.equ SRW01 = 3 ; Wait State Select Bit 1 for Lower Sector |
.equ SRL0 = 4 ; Wait State Sector Limit Bit 0 |
.equ SRL1 = 5 ; Wait State Sector Limit Bit 1 |
.equ SRL2 = 6 ; Wait State Sector Limit Bit 2 |
.equ SM0 = 7 ; Sleep mode Select Bit 0 |
; SPMCR - Store Program Memory Control Register |
.equ SPMEN = 0 ; Store Program Memory Enable |
.equ PGERS = 1 ; Page Erase |
.equ PGWRT = 2 ; Page Write |
.equ BLBSET = 3 ; Boot Lock Bit Set |
; ***** TIMER_COUNTER_0 ************** |
; TCCR0 - Timer/Counter Control Register |
.equ CS00 = 0 ; Clock Select 1 |
.equ CS01 = 1 ; Clock Select 1 |
.equ CS02 = 2 ; Clock Select 2 |
.equ WGM01 = 3 ; Waveform Generation Mode 1 |
.equ COM00 = 4 ; Compare match Output Mode 0 |
.equ COM01 = 5 ; Compare Match Output Mode 1 |
.equ WGM00 = 6 ; Waveform Generation Mode 0 |
.equ FOC0 = 7 ; Force Output Compare |
; TCNT0 - Timer/Counter Register |
.equ TCNT0_0 = 0 ; |
.equ TCNT0_1 = 1 ; |
.equ TCNT0_2 = 2 ; |
.equ TCNT0_3 = 3 ; |
.equ TCNT0_4 = 4 ; |
.equ TCNT0_5 = 5 ; |
.equ TCNT0_6 = 6 ; |
.equ TCNT0_7 = 7 ; |
; OCR0 - Output Compare Register |
.equ OCR0_0 = 0 ; |
.equ OCR0_1 = 1 ; |
.equ OCR0_2 = 2 ; |
.equ OCR0_3 = 3 ; |
.equ OCR0_4 = 4 ; |
.equ OCR0_5 = 5 ; |
.equ OCR0_6 = 6 ; |
.equ OCR0_7 = 7 ; |
; TIMSK - Timer/Counter Interrupt Mask Register |
.equ OCIE0 = 0 ; Timer/Counter0 Output Compare Match Interrupt register |
.equ TOIE0 = 1 ; Timer/Counter0 Overflow Interrupt Enable |
; TIFR - Timer/Counter Interrupt Flag register |
.equ OCF0 = 0 ; Output Compare Flag 0 |
.equ TOV0 = 1 ; Timer/Counter0 Overflow Flag |
; SFIOR - Special Function IO Register |
.equ PSR10 = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0 |
; ***** TIMER_COUNTER_2 ************** |
; TIMSK - Timer/Counter Interrupt Mask register |
.equ OCIE2 = 2 ; Timer/Counter2 Output Compare Match Interrupt Enable |
.equ TOIE2 = 4 ; Timer/Counter2 Overflow Interrupt Enable |
; TIFR - Timer/Counter Interrupt Flag Register |
.equ OCF2 = 2 ; Output Compare Flag 2 |
.equ TOV2 = 4 ; Timer/Counter2 Overflow Flag |
; TCCR2 - Timer/Counter2 Control Register |
.equ CS20 = 0 ; Clock Select bit 0 |
.equ CS21 = 1 ; Clock Select bit 1 |
.equ CS22 = 2 ; Clock Select bit 2 |
.equ CTC2 = 3 ; Clear Timer/Counter2 on Compare Match |
.equ COM20 = 4 ; Compare Output Mode bit 0 |
.equ COM21 = 5 ; Compare Output Mode bit 1 |
.equ PWM2 = 6 ; Pulse Width Modulator Enable |
.equ FOC2 = 7 ; Force Output Compare |
; TCNT2 - Timer/Counter2 |
.equ TCNT2_0 = 0 ; Timer/Counter 2 bit 0 |
.equ TCNT2_1 = 1 ; Timer/Counter 2 bit 1 |
.equ TCNT2_2 = 2 ; Timer/Counter 2 bit 2 |
.equ TCNT2_3 = 3 ; Timer/Counter 2 bit 3 |
.equ TCNT2_4 = 4 ; Timer/Counter 2 bit 4 |
.equ TCNT2_5 = 5 ; Timer/Counter 2 bit 5 |
.equ TCNT2_6 = 6 ; Timer/Counter 2 bit 6 |
.equ TCNT2_7 = 7 ; Timer/Counter 2 bit 7 |
; OCR2 - Timer/Counter2 Output Compare Register |
.equ OCR2_0 = 0 ; Timer/Counter2 Output Compare Register Bit 0 |
.equ OCR2_1 = 1 ; Timer/Counter2 Output Compare Register Bit 1 |
.equ OCR2_2 = 2 ; Timer/Counter2 Output Compare Register Bit 2 |
.equ OCR2_3 = 3 ; Timer/Counter2 Output Compare Register Bit 3 |
.equ OCR2_4 = 4 ; Timer/Counter2 Output Compare Register Bit 4 |
.equ OCR2_5 = 5 ; Timer/Counter2 Output Compare Register Bit 5 |
.equ OCR2_6 = 6 ; Timer/Counter2 Output Compare Register Bit 6 |
.equ OCR2_7 = 7 ; Timer/Counter2 Output Compare Register Bit 7 |
; ASSR - Asynchronous Status Register |
.equ TCR2UB = 0 ; Timer/counter Control Register2 Update Busy |
.equ OCR2UB = 1 ; Output Compare Register2 Update Busy |
.equ TCN2UB = 2 ; Timer/Counter2 Update Busy |
.equ AS2 = 3 ; Asynchronous Timer/counter2 |
; SFIOR - Specil Function IO Register |
.equ PSR2 = 1 ; Prescaler Reset Timer/Counter2 |
; ***** TIMER_COUNTER_1 ************** |
; TIMSK - Timer/Counter Interrupt Mask Register |
.equ TICIE1 = 3 ; Timer/Counter1 Input Capture Interrupt Enable |
.equ OCIE1B = 5 ; Timer/Counter1 Output CompareB Match Interrupt Enable |
.equ OCIE1A = 6 ; Timer/Counter1 Output CompareA Match Interrupt Enable |
.equ TOIE1 = 7 ; Timer/Counter1 Overflow Interrupt Enable |
; TIFR - Timer/Counter Interrupt Flag register |
.equ ICF1 = 3 ; Input Capture Flag 1 |
.equ OCF1B = 5 ; Output Compare Flag 1B |
.equ OCF1A = 6 ; Output Compare Flag 1A |
.equ TOV1 = 7 ; Timer/Counter1 Overflow Flag |
; TCCR1A - Timer/Counter1 Control Register A |
.equ WGM10 = 0 ; Waveform Generation Mode |
.equ WGM11 = 1 ; Waveform Generation Mode |
.equ FOC1B = 2 ; Force Output Compare 1B |
.equ FOC1A = 3 ; Force Output Compare 1A |
.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0 |
.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1 |
.equ COM1A0 = 6 ; Comparet Ouput Mode 1A, bit 0 |
.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1 |
; TCCR1B - Timer/Counter1 Control Register B |
.equ CS10 = 0 ; Prescaler source of Timer/Counter 1 |
.equ CS11 = 1 ; Prescaler source of Timer/Counter 1 |
.equ CS12 = 2 ; Prescaler source of Timer/Counter 1 |
.equ CTC1 = 3 ; Clear Timer/Counter1 on Compare Match |
.equ ICES1 = 6 ; Input Capture 1 Edge Select |
.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler |
; ***** WATCHDOG ********************* |
; WDTCR - Watchdog Timer Control Register |
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 |
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 |
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 |
.equ WDE = 3 ; Watch Dog Enable |
.equ WDTOE = 4 ; RW |
.equ WDDE = WDTOE ; For compatibility |
; ***** LOCKSBITS ******************************************************** |
.equ LB1 = 0 ; Lock bit |
.equ LB2 = 1 ; Lock bit |
.equ BLB01 = 2 ; Boot Lock bit |
.equ BLB02 = 3 ; Boot Lock bit |
.equ BLB11 = 4 ; Boot lock bit |
.equ BLB12 = 5 ; Boot lock bit |
; ***** FUSES ************************************************************ |
; LOW fuse bits |
.equ CKSEL0 = 0 ; Select Clock Source |
.equ CKSEL1 = 1 ; Select Clock Source |
.equ CKSEL2 = 2 ; Select Clock Source |
.equ SUT = 3 ; Start-up time |
.equ SPIEN = 4 ; Serial program downloading (SPI) enabled |
.equ BOOTRST = 5 ; Boot Reset Vector Enabled |
; HIGH fuse bits |
; EXTENDED fuse bits |
; ***** CPU REGISTER DEFINITIONS ***************************************** |
.def XH = r27 |
.def XL = r26 |
.def YH = r29 |
.def YL = r28 |
.def ZH = r31 |
.def ZL = r30 |
; ***** DATA MEMORY DECLARATIONS ***************************************** |
.equ FLASHEND = 0x1fff ; Note: Word address |
.equ IOEND = 0x003f |
.equ SRAM_START = 0x0060 |
.equ SRAM_SIZE = 1024 |
.equ RAMEND = 0x045f |
.equ XRAMEND = 0xfbff |
.equ E2END = 0x01ff |
.equ EEPROMEND = 0x01ff |
.equ EEADRBITS = 9 |
#pragma AVRPART MEMORY PROG_FLASH 16384 |
#pragma AVRPART MEMORY EEPROM 512 |
#pragma AVRPART MEMORY INT_SRAM SIZE 1024 |
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60 |
; ***** BOOTLOADER DECLARATIONS ****************************************** |
.equ NRWW_START_ADDR = 0x0 |
.equ NRWW_STOP_ADDR = 0x1fff |
.equ PAGESIZE = 64 |
.equ FIRSTBOOTSTART = 0x1e00 |
; ***** INTERRUPT VECTORS ************************************************ |
.equ INT0addr = 0x0002 ; External Interrupt 0 |
.equ INT1addr = 0x0004 ; External Interrupt 1 |
.equ INT2addr = 0x0006 ; External Interrupt 2 |
.equ OC2addr = 0x0008 ; Timer/Counter2 Compare Match |
.equ OVF2addr = 0x000a ; Timer/Counter2 Overflow |
.equ ICP1addr = 0x000c ; Timer/Counter1 Capture Event |
.equ OC1Aaddr = 0x000e ; Timer/Counter1 Compare Match A |
.equ OC1Baddr = 0x0010 ; Timer/Counter1 Compare Match B |
.equ OVF1addr = 0x0012 ; Timer/Counter1 Overflow |
.equ OC0addr = 0x0014 ; Timer/Counter0 Compare Match |
.equ OVF0addr = 0x0016 ; Timer/Counter0 Overflow |
.equ SPIaddr = 0x0018 ; Serial Transfer Complete |
.equ URXC0addr = 0x001a ; UART0, Rx Complete |
.equ URXC1addr = 0x001c ; UART1, Rx Complete |
.equ UDRE0addr = 0x001e ; UART0 Data Register Empty |
.equ UDRE1addr = 0x0020 ; UART1 Data Register Empty |
.equ UTXC0addr = 0x0022 ; UART0, Tx Complete |
.equ UTXC1addr = 0x0024 ; UART1, Tx Complete |
.equ ERDYaddr = 0x0026 ; EEPROM Ready |
.equ ACIaddr = 0x0028 ; Analog Comparator |
.equ INT_VECTORS_SIZE = 42 ; size in words |
#pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED break |
#endif /* _M161DEF_INC_ */ |
; ***** END OF FILE ****************************************************** |
/contrib/toolchain/avra/includes/m162def.inc |
---|
0,0 → 1,929 |
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** |
;***** Created: 2005-01-11 10:30 ******* Source: ATmega162.xml *********** |
;************************************************************************* |
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y |
;* |
;* Number : AVR000 |
;* File Name : "m162def.inc" |
;* Title : Register/Bit Definitions for the ATmega162 |
;* Date : 2005-01-11 |
;* Version : 2.14 |
;* Support E-mail : avr@atmel.com |
;* Target MCU : ATmega162 |
;* |
;* DESCRIPTION |
;* When including this file in the assembly program file, all I/O register |
;* names and I/O register bit names appearing in the data book can be used. |
;* In addition, the six registers forming the three data pointers X, Y and |
;* Z have been assigned names XL - ZH. Highest RAM address for Internal |
;* SRAM is also defined |
;* |
;* The Register names are represented by their hexadecimal address. |
;* |
;* The Register Bit names are represented by their bit number (0-7). |
;* |
;* Please observe the difference in using the bit names with instructions |
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" |
;* (skip if bit in register set/cleared). The following example illustrates |
;* this: |
;* |
;* in r16,PORTB ;read PORTB latch |
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) |
;* out PORTB,r16 ;output to PORTB |
;* |
;* in r16,TIFR ;read the Timer Interrupt Flag Register |
;* sbrc r16,TOV0 ;test the overflow flag (use bit#) |
;* rjmp TOV0_is_set ;jump if set |
;* ... ;otherwise do something else |
;************************************************************************* |
#ifndef _M162DEF_INC_ |
#define _M162DEF_INC_ |
#pragma partinc 0 |
; ***** SPECIFY DEVICE *************************************************** |
.device ATmega162 |
#pragma AVRPART ADMIN PART_NAME ATmega162 |
.equ SIGNATURE_000 = 0x1e |
.equ SIGNATURE_001 = 0x94 |
.equ SIGNATURE_002 = 0x04 |
#pragma AVRPART CORE CORE_VERSION V2E |
; ***** I/O REGISTER DEFINITIONS ***************************************** |
; NOTE: |
; Definitions marked "MEMORY MAPPED"are extended I/O ports |
; and cannot be used with IN/OUT instructions |
.equ TCCR3A = 0x8b ; MEMORY MAPPED |
.equ TCCR3B = 0x8a ; MEMORY MAPPED |
.equ TCNT3H = 0x89 ; MEMORY MAPPED |
.equ TCNT3L = 0x88 ; MEMORY MAPPED |
.equ OCR3AH = 0x87 ; MEMORY MAPPED |
.equ OCR3AL = 0x86 ; MEMORY MAPPED |
.equ OCR3BH = 0x85 ; MEMORY MAPPED |
.equ OCR3BL = 0x84 ; MEMORY MAPPED |
.equ ICR3H = 0x81 ; MEMORY MAPPED |
.equ ICR3L = 0x80 ; MEMORY MAPPED |
.equ ETIMSK = 0x7d ; MEMORY MAPPED |
.equ ETIFR = 0x7c ; MEMORY MAPPED |
.equ PCMSK1 = 0x6c ; MEMORY MAPPED |
.equ PCMSK0 = 0x6b ; MEMORY MAPPED |
.equ CLKPR = 0x61 ; MEMORY MAPPED |
.equ SREG = 0x3f |
.equ SPH = 0x3e |
.equ SPL = 0x3d |
.equ UBRR1H = 0x3c |
.equ UCSR1C = 0x3c |
.equ GICR = 0x3b |
.equ GIFR = 0x3a |
.equ TIMSK = 0x39 |
.equ TIFR = 0x38 |
.equ SPMCR = 0x37 |
.equ EMCUCR = 0x36 |
.equ MCUCR = 0x35 |
.equ MCUCSR = 0x34 |
.equ TCCR0 = 0x33 |
.equ TCNT0 = 0x32 |
.equ OCR0 = 0x31 |
.equ SFIOR = 0x30 |
.equ TCCR1A = 0x2f |
.equ TCCR1B = 0x2e |
.equ TCNT1H = 0x2d |
.equ TCNT1L = 0x2c |
.equ OCR1AH = 0x2b |
.equ OCR1AL = 0x2a |
.equ OCR1BH = 0x29 |
.equ OCR1BL = 0x28 |
.equ TCCR2 = 0x27 |
.equ ASSR = 0x26 |
.equ ICR1H = 0x25 |
.equ ICR1L = 0x24 |
.equ TCNT2 = 0x23 |
.equ OCR2 = 0x22 |
.equ WDTCR = 0x21 |
.equ UBRR0H = 0x20 |
.equ UCSR0C = 0x20 |
.equ EEARH = 0x1f |
.equ EEARL = 0x1e |
.equ EEDR = 0x1d |
.equ EECR = 0x1c |
.equ PORTA = 0x1b |
.equ DDRA = 0x1a |
.equ PINA = 0x19 |
.equ PORTB = 0x18 |
.equ DDRB = 0x17 |
.equ PINB = 0x16 |
.equ PORTC = 0x15 |
.equ DDRC = 0x14 |
.equ PINC = 0x13 |
.equ PORTD = 0x12 |
.equ DDRD = 0x11 |
.equ PIND = 0x10 |
.equ SPDR = 0x0f |
.equ SPSR = 0x0e |
.equ SPCR = 0x0d |
.equ UDR0 = 0x0c |
.equ UCSR0A = 0x0b |
.equ UCSR0B = 0x0a |
.equ UBRR0L = 0x09 |
.equ ACSR = 0x08 |
.equ PORTE = 0x07 |
.equ DDRE = 0x06 |
.equ PINE = 0x05 |
.equ OSCCAL = 0x04 |
.equ OCDR = 0x04 |
.equ UDR1 = 0x03 |
.equ UCSR1A = 0x02 |
.equ UCSR1B = 0x01 |
.equ UBRR1L = 0x00 |
; ***** BIT DEFINITIONS ************************************************** |
; ***** TIMER_COUNTER_1 ************** |
; TIMSK - Timer/Counter Interrupt Mask Register |
.equ TICIE1 = 3 ; Timer/Counter1 Input Capture Interrupt Enable |
.equ OCIE1B = 5 ; Timer/Counter1 Output CompareB Match Interrupt Enable |
.equ OCIE1A = 6 ; Timer/Counter1 Output CompareA Match Interrupt Enable |
.equ TOIE1 = 7 ; Timer/Counter1 Overflow Interrupt Enable |
; TIFR - Timer/Counter Interrupt Flag register |
.equ ICF1 = 3 ; Input Capture Flag 1 |
.equ OCF1B = 5 ; Output Compare Flag 1B |
.equ OCF1A = 6 ; Output Compare Flag 1A |
.equ TOV1 = 7 ; Timer/Counter1 Overflow Flag |
; TCCR1A - Timer/Counter1 Control Register A |
.equ WGM10 = 0 ; Pulse Width Modulator Select Bit 0 |
.equ PWM10 = WGM10 ; For compatibility |
.equ WGM11 = 1 ; Pulse Width Modulator Select Bit 1 |
.equ PWM11 = WGM11 ; For compatibility |
.equ FOC1B = 2 ; Force Output Compare for Channel B |
.equ FOC1A = 3 ; Force Output Compare for Channel A |
.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0 |
.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1 |
.equ COM1A0 = 6 ; Compare Ouput Mode 1A, bit 0 |
.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1 |
; TCCR1B - Timer/Counter1 Control Register B |
.equ CS10 = 0 ; Clock Select1 bit 0 |
.equ CS11 = 1 ; Clock Select1 bit 1 |
.equ CS12 = 2 ; Clock Select1 bit 2 |
.equ WGM12 = 3 ; Pulse Width Modulator Select Bit 2 |
.equ CTC10 = WGM12 ; For compatibility |
.equ WGM13 = 4 ; Pulse Width Modulator Select Bit 3 |
.equ CTC11 = WGM13 ; For compatibility |
.equ ICES1 = 6 ; Input Capture 1 Edge Select |
.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler |
; ***** TIMER_COUNTER_2 ************** |
; TCCR2 - Timer/Counter Control Register |
.equ CS20 = 0 ; Clock Select |
.equ CS21 = 1 ; Clock Select |
.equ CS22 = 2 ; Clock Select |
.equ WGM21 = 3 ; Pulse Width Modulator Select Bit 1 |
.equ CTC2 = WGM21 ; For compatibility |
.equ COM20 = 4 ; Compare Match Output Mode |
.equ COM21 = 5 ; Compare Match Output Mode |
.equ WGM20 = 6 ; Pulse Width Modulator Select Bit 0 |
.equ PWM2 = WGM20 ; For compatibility |
.equ FOC2 = 7 ; Forde Output Compare |
; TCNT2 - Timer/Counter Register |
.equ TCNT2_0 = 0 ; Timer/Counter Register Bit 0 |
.equ TCNT2_1 = 1 ; Timer/Counter Register Bit 1 |
.equ TCNT2_2 = 2 ; Timer/Counter Register Bit 2 |
.equ TCNT2_3 = 3 ; Timer/Counter Register Bit 3 |
.equ TCNT2_4 = 4 ; Timer/Counter Register Bit 4 |
.equ TCNT2_5 = 5 ; Timer/Counter Register Bit 5 |
.equ TCNT2_6 = 6 ; Timer/Counter Register Bit 6 |
.equ TCNT2_7 = 7 ; Timer/Counter Register Bit 7 |
; OCR2 - Output Compare Register |
.equ OCR2_0 = 0 ; Output Compare Register Bit 0 |
.equ OCR2_1 = 1 ; Output Compare Register Bit 1 |
.equ OCR2_2 = 2 ; Output Compare Register Bit 2 |
.equ OCR2_3 = 3 ; Output Compare Register Bit 3 |
.equ OCR2_4 = 4 ; Output Compare Register Bit 4 |
.equ OCR2_5 = 5 ; Output Compare Register Bit 5 |
.equ OCR2_6 = 6 ; Output Compare Register Bit 6 |
.equ OCR2_7 = 7 ; Output Compare Register Bit 7 |
; TIMSK - Timer/Counter Interrupt Mask Register |
.equ TOIE2 = 2 ; Timer/Counter2 Overflow Interrupt Enable |
.equ OCIE2 = 4 ; Timer/Counter2 Output Compare Match Interrupt Enable |
; TIFR - Timer/Counter Interrupt Flag Register |
.equ TOV2 = 2 ; Timer/Counter2 Overflow Flag |
.equ OCF2 = 4 ; Output Compare Flag 2 |
; ASSR - Asynchronous Status Register |
.equ TCR2UB = 0 ; Timer/Counter Control Register2 Update Busy |
.equ OCR2UB = 1 ; Output Compare Register2 Update Busy |
.equ TCN2UB = 2 ; Timer/Counter2 Update Busy |
.equ AS2 = 3 ; Asynchronous Timer 2 |
; ***** TIMER_COUNTER_3 ************** |
; ETIMSK - Extended Timer/Counter Interrupt Mask Register |
.equ TOIE3 = 2 ; Timer/Counter3 Overflow Interrupt Enable |
.equ OCIE3B = 3 ; Timer/Counter3 Output CompareB Match Interrupt Enable |
.equ OCIE3A = 4 ; Timer/Counter3 Output CompareA Match Interrupt Enable |
.equ TICIE3 = 5 ; Timer/Counter3 Input Capture Interrupt Enable |
; ETIFR - Extended Timer/Counter Interrupt Flag register |
.equ TOV3 = 2 ; Timer/Counter3 Overflow Flag |
.equ OCF3B = 3 ; Output Compare Flag 3B |
.equ OCF3A = 4 ; Output Compare Flag 3A |
.equ ICF3 = 5 ; Input Capture Flag 3 |
; TCCR3A - Timer/Counter3 Control Register A |
.equ WGM30 = 0 ; Pulse Width Modulator Select Bit 0 |
.equ WGM31 = 1 ; Pulse Width Modulator Select Bit 1 |
.equ FOC3B = 2 ; Force Output Compare for Channel B |
.equ FOC3A = 3 ; Force Output Compare for Channel A |
.equ COM3B0 = 4 ; Compare Output Mode 3B, bit 0 |
.equ COM3B1 = 5 ; Compare Output Mode 3B, bit 1 |
.equ COM3A0 = 6 ; Compare Ouput Mode 3A, bit 0 |
.equ COM3A1 = 7 ; Compare Output Mode 3A, bit 1 |
; TCCR3B - Timer/Counter3 Control Register B |
.equ CS30 = 0 ; Clock Select3 bit 0 |
.equ CS31 = 1 ; Clock Select3 bit 1 |
.equ CS32 = 2 ; Clock Select3 bit 2 |
.equ WGM32 = 3 ; Pulse Width Modulator Select Bit 2 |
.equ WGM33 = 4 ; Pulse Width Modulator Select Bit 3 |
.equ ICES3 = 6 ; Input Capture 3 Edge Select |
.equ ICNC3 = 7 ; Input Capture 3 Noise Canceler |
; ***** ANALOG_COMPARATOR ************ |
; ACSR - Analog Comparator Control And Status Register |
.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 |
.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 |
.equ ACIC = 2 ; Analog Comparator Input Capture Enable |
.equ ACIE = 3 ; Analog Comparator Interrupt Enable |
.equ ACI = 4 ; Analog Comparator Interrupt Flag |
.equ ACO = 5 ; Analog Compare Output |
.equ ACBG = 6 ; Analog Comparator Bandgap Select |
.equ AINBG = ACBG ; For compatibility |
.equ ACD = 7 ; Analog Comparator Disable |
; ***** USART0 *********************** |
; UDR0 - USART I/O Data Register |
.equ UDR = UDR0 ; For compatibility |
.equ UDR0_0 = 0 ; USART I/O Data Register bit 0 |
.equ UDR0_1 = 1 ; USART I/O Data Register bit 1 |
.equ UDR0_2 = 2 ; USART I/O Data Register bit 2 |
.equ UDR0_3 = 3 ; USART I/O Data Register bit 3 |
.equ UDR0_4 = 4 ; USART I/O Data Register bit 4 |
.equ UDR0_5 = 5 ; USART I/O Data Register bit 5 |
.equ UDR0_6 = 6 ; USART I/O Data Register bit 6 |
.equ UDR0_7 = 7 ; USART I/O Data Register bit 7 |
; UCSR0A - USART Control and Status Register A |
.equ USR = UCSR0A ; For compatibility |
.equ MPCM0 = 0 ; Multi-processor Communication Mode |
.equ U2X0 = 1 ; Double the USART transmission speed |
.equ U2X = U2X0 ; For compatibility |
.equ UPE0 = 2 ; Parity Error |
.equ DOR0 = 3 ; Data overRun |
.equ DOR = DOR0 ; For compatibility |
.equ FE0 = 4 ; Framing Error |
.equ FE = FE0 ; For compatibility |
.equ UDRE0 = 5 ; USART Data Register Empty |
.equ UDRE = UDRE0 ; For compatibility |
.equ TXC0 = 6 ; USART Transmitt Complete |
.equ TXC = TXC0 ; For compatibility |
.equ RXC0 = 7 ; USART Receive Complete |
.equ RXC = RXC0 ; For compatibility |
; UCSR0B - USART Control and Status Register B |
.equ UCR = UCSR0B ; For compatibility |
.equ TXB80 = 0 ; Transmit Data Bit 8 |
.equ TXB8 = TXB80 ; For compatibility |
.equ RXB80 = 1 ; Receive Data Bit 8 |
.equ RXB8 = RXB80 ; For compatibility |
.equ UCSZ02 = 2 ; Character Size |
.equ UCSZ2 = UCSZ02 ; For compatibility |
.equ TXEN0 = 3 ; Transmitter Enable |
.equ TXEN = TXEN0 ; For compatibility |
.equ RXEN0 = 4 ; Receiver Enable |
.equ RXEN = RXEN0 ; For compatibility |
.equ UDRIE0 = 5 ; USART Data register Empty Interrupt Enable |
.equ UDRIE = UDRIE0 ; For compatibility |
.equ TXCIE0 = 6 ; TX Complete Interrupt Enable |
.equ TXCIE = TXCIE0 ; For compatibility |
.equ RXCIE0 = 7 ; RX Complete Interrupt Enable |
.equ RXCIE = RXCIE0 ; For compatibility |
; UCSR0C - USART Control and Status Register C |
.equ UBRRHI = UCSR0C ; For compatibility |
.equ UCPOL0 = 0 ; Clock Polarity |
.equ UCSZ00 = 1 ; Character Size |
.equ UCSZ01 = 2 ; Character Size |
.equ USBS0 = 3 ; Stop Bit Select |
.equ UPM00 = 4 ; Parity Mode Bit 0 |
.equ UPM01 = 5 ; Parity Mode Bit 1 |
.equ UMSEL0 = 6 ; USART Mode Select |
.equ URSEL = 7 ; Register Select |
.equ UBRR0 = UBRR0L ; For compatibility |
.equ UBRR = UBRR0L ; For compatibility |
; ***** USART1 *********************** |
; UDR1 - USART I/O Data Register |
.equ UDR1_0 = 0 ; USART1 I/O Data Register bit 0 |
.equ UDR1_1 = 1 ; USART1 I/O Data Register bit 1 |
.equ UDR1_2 = 2 ; USART1 I/O Data Register bit 2 |
.equ UDR1_3 = 3 ; USART1 I/O Data Register bit 3 |
.equ UDR1_4 = 4 ; USART1 I/O Data Register bit 4 |
.equ UDR1_5 = 5 ; USART1 I/O Data Register bit 5 |
.equ UDR1_6 = 6 ; USART1 I/O Data Register bit 6 |
.equ UDR1_7 = 7 ; USART1 I/O Data Register bit 7 |
; UCSR1A - USART Control and Status Register A |
.equ MPCM1 = 0 ; Multi-processor Communication Mode |
.equ U2X1 = 1 ; Double the USART transmission speed |
.equ UPE1 = 2 ; Parity Error |
.equ DOR1 = 3 ; Data overRun |
.equ FE1 = 4 ; Framing Error |
.equ UDRE1 = 5 ; USART Data Register Empty |
.equ TXC1 = 6 ; USART Transmitt Complete |
.equ RXC1 = 7 ; USART Receive Complete |
; UCSR1B - USART Control and Status Register B |
.equ TXB81 = 0 ; Transmit Data Bit 8 |
.equ RXB81 = 1 ; Receive Data Bit 8 |
.equ UCSZ12 = 2 ; Character Size |
.equ CHR91 = UCSZ12 ; For compatibility |
.equ TXEN1 = 3 ; Transmitter Enable |
.equ RXEN1 = 4 ; Receiver Enable |
.equ UDRIE1 = 5 ; USART Data register Empty Interrupt Enable |
.equ TXCIE1 = 6 ; TX Complete Interrupt Enable |
.equ RXCIE1 = 7 ; RX Complete Interrupt Enable |
; UCSR1C - USART Control and Status Register C |
.equ UCPOL = 0 ; Clock Polarity |
.equ UCSZ0 = 1 ; Character Size |
.equ UCSZ1 = 2 ; Character Size |
.equ USBS = 3 ; Stop Bit Select |
.equ UPM0 = 4 ; Parity Mode Bit 0 |
.equ UPM1 = 5 ; Parity Mode Bit 1 |
.equ UMSEL = 6 ; USART Mode Select |
;.equ URSEL = 7 ; Register Select |
.equ UBRR1 = UBRR1L ; For compatibility |
; ***** SPI ************************** |
; SPDR - SPI Data Register |
.equ SPDR0 = 0 ; SPI Data Register bit 0 |
.equ SPDR1 = 1 ; SPI Data Register bit 1 |
.equ SPDR2 = 2 ; SPI Data Register bit 2 |
.equ SPDR3 = 3 ; SPI Data Register bit 3 |
.equ SPDR4 = 4 ; SPI Data Register bit 4 |
.equ SPDR5 = 5 ; SPI Data Register bit 5 |
.equ SPDR6 = 6 ; SPI Data Register bit 6 |
.equ SPDR7 = 7 ; SPI Data Register bit 7 |
; SPSR - SPI Status Register |
.equ SPI2X = 0 ; Double SPI Speed Bit |
.equ WCOL = 6 ; Write Collision Flag |
.equ SPIF = 7 ; SPI Interrupt Flag |
; SPCR - SPI Control Register |
.equ SPR0 = 0 ; SPI Clock Rate Select 0 |
.equ SPR1 = 1 ; SPI Clock Rate Select 1 |
.equ CPHA = 2 ; Clock Phase |
.equ CPOL = 3 ; Clock polarity |
.equ MSTR = 4 ; Master/Slave Select |
.equ DORD = 5 ; Data Order |
.equ SPE = 6 ; SPI Enable |
.equ SPIE = 7 ; SPI Interrupt Enable |
; ***** CPU ************************** |
; SREG - Status Register |
.equ SREG_C = 0 ; Carry Flag |
.equ SREG_Z = 1 ; Zero Flag |
.equ SREG_N = 2 ; Negative Flag |
.equ SREG_V = 3 ; Two's Complement Overflow Flag |
.equ SREG_S = 4 ; Sign Bit |
.equ SREG_H = 5 ; Half Carry Flag |
.equ SREG_T = 6 ; Bit Copy Storage |
.equ SREG_I = 7 ; Global Interrupt Enable |
; MCUCR - MCU Control Register |
.equ ISC00 = 0 ; Interrupt Sense Control 0 bit 0 |
.equ ISC01 = 1 ; Interrupt Sense Control 0 bit 1 |
.equ ISC10 = 2 ; Interrupt Sense Control 1 bit 1 |
.equ ISC11 = 3 ; Interrupt Sense Control 1 bit 1 |
.equ SM1 = 4 ; Sleep Mode Select |
.equ SM = SM1 ; For compatibility |
.equ SE = 5 ; Sleep Enable |
.equ SRW10 = 6 ; External SRAM Wait State Select |
.equ SRW = SRW10 ; For compatibility |
.equ SRE = 7 ; External SRAM Enable |
; MCUCSR - MCU Control And Status Register |
.equ MCUSR = MCUCSR ; For compatibility |
.equ PORF = 0 ; Power-on reset flag |
.equ EXTRF = 1 ; External Reset Flag |
.equ BORF = 2 ; Brown-out Reset Flag |
.equ WDRF = 3 ; Watchdog Reset Flag |
.equ JTRF = 4 ; JTAG Reset Flag |
.equ SM2 = 5 ; Sleep Mode Select Bit 2 |
.equ JDT = 7 ; JTAG Interface Disable |
; EMCUCR - Extended MCU Control Register |
.equ ISC2 = 0 ; Interrupt Sense Control 2 |
.equ SRW11 = 1 ; Wait State Select Bit 1 for Upper Sector |
.equ SRW00 = 2 ; Wait State Select Bit 0 for Lower Sector |
.equ SRW01 = 3 ; Wait State Select Bit 1 for Lower Sector |
.equ SRL0 = 4 ; Wait State Sector Limit Bit 0 |
.equ SRL1 = 5 ; Wait State Sector Limit Bit 1 |
.equ SRL2 = 6 ; Wait State Sector Limit Bit 2 |
.equ SM0 = 7 ; Sleep mode Select Bit 0 |
; OSCCAL - Oscillator Calibration Value |
.equ CAL0 = 0 ; Oscillator Calibration Value Bit0 |
.equ CAL1 = 1 ; Oscillator Calibration Value Bit1 |
.equ CAL2 = 2 ; Oscillator Calibration Value Bit2 |
.equ CAL3 = 3 ; Oscillator Calibration Value Bit3 |
.equ CAL4 = 4 ; Oscillator Calibration Value Bit4 |
.equ CAL5 = 5 ; Oscillator Calibration Value Bit5 |
.equ CAL6 = 6 ; Oscillator Calibration Value Bit6 |
; CLKPR - Oscillator Calibration Value |
.equ CLKPS0 = 0 ; Clock Prescaler Select Bit 0 |
.equ CLKPS1 = 1 ; Clock Prescaler Select Bit 1 |
.equ CLKPS2 = 2 ; Clock Prescaler Select Bit 2 |
.equ CLKPS3 = 3 ; Clock Prescaler Select Bit 3 |
.equ CLKPCE = 7 ; Clock Prescaler Change Enable |
; SFIOR - Special Function IO Register |
.equ PSR310 = 0 ; Prescaler Reset Timer/Counter3, Timer/Counter1 and Timer/Counter0 |
.equ PSR10 = PSR310 ; For compatibility |
.equ PSR0 = PSR310 ; For compatibility |
.equ PSR1 = PSR310 ; For compatibility |
.equ PSR2 = 1 ; Prescaler Reset Timer/Counter2 |
.equ PUD = 2 ; Pull-up Disable |
.equ XMM0 = 3 ; External Memory High Mask Bit 0 |
.equ XMM1 = 4 ; External Memory High Mask Bit 1 |
.equ XMM2 = 5 ; External Memory High Mask Bit 2 |
.equ XMBK = 6 ; External Memory Bus Keeper Enable |
.equ TSM = 7 ; Timer/Counter Synchronization Mode |
; ***** JTAG ************************* |
; OCDR - On-Chip Debug Related Register in I/O Memory |
.equ OCDR0 = 0 ; On-Chip Debug Register Bit 0 |
.equ OCDR1 = 1 ; On-Chip Debug Register Bit 1 |
.equ OCDR2 = 2 ; On-Chip Debug Register Bit 2 |
.equ OCDR3 = 3 ; On-Chip Debug Register Bit 3 |
.equ OCDR4 = 4 ; On-Chip Debug Register Bit 4 |
.equ OCDR5 = 5 ; On-Chip Debug Register Bit 5 |
.equ OCDR6 = 6 ; On-Chip Debug Register Bit 6 |
.equ OCDR7 = 7 ; On-Chip Debug Register Bit 7 |
.equ IDRD = OCDR7 ; For compatibility |
; MCUCSR - MCU Control And Status Register |
;.equ JTRF = 4 ; JTAG Reset Flag |
.equ JTD = 7 ; JTAG Interface Disable |
; ***** BOOT_LOAD ******************** |
; SPMCR - Store Program Memory Control Register |
.equ SPMEN = 0 ; Store Program Memory Enable |
.equ PGERS = 1 ; Page Erase |
.equ PGWRT = 2 ; Page Write |
.equ BLBSET = 3 ; Boot Lock Bit Set |
.equ RWWSRE = 4 ; Read While Write secion read enable |
.equ ASRE = RWWSRE ; For compatibility |
.equ RWWSB = 6 ; Read While Write Section Busy |
.equ ASB = RWWSB ; For compatibility |
.equ SPMIE = 7 ; SPM Interrupt Enable |
; ***** EEPROM *********************** |
; EEDR - EEPROM Data Register |
.equ EEDR0 = 0 ; EEPROM Data Register bit 0 |
.equ EEDR1 = 1 ; EEPROM Data Register bit 1 |
.equ EEDR2 = 2 ; EEPROM Data Register bit 2 |
.equ EEDR3 = 3 ; EEPROM Data Register bit 3 |
.equ EEDR4 = 4 ; EEPROM Data Register bit 4 |
.equ EEDR5 = 5 ; EEPROM Data Register bit 5 |
.equ EEDR6 = 6 ; EEPROM Data Register bit 6 |
.equ EEDR7 = 7 ; EEPROM Data Register bit 7 |
; EECR - EEPROM Control Register |
.equ EERE = 0 ; EEPROM Read Enable |
.equ EEWE = 1 ; EEPROM Write Enable |
.equ EEMWE = 2 ; EEPROM Master Write Enable |
.equ EEWEE = EEMWE ; For compatibility |
.equ EERIE = 3 ; EEPROM Ready Interrupt Enable |
; ***** PORTA ************************ |
; PORTA - Port A Data Register |
.equ PORTA0 = 0 ; Port A Data Register bit 0 |
.equ PA0 = 0 ; For compatibility |
.equ PORTA1 = 1 ; Port A Data Register bit 1 |
.equ PA1 = 1 ; For compatibility |
.equ PORTA2 = 2 ; Port A Data Register bit 2 |
.equ PA2 = 2 ; For compatibility |
.equ PORTA3 = 3 ; Port A Data Register bit 3 |
.equ PA3 = 3 ; For compatibility |
.equ PORTA4 = 4 ; Port A Data Register bit 4 |
.equ PA4 = 4 ; For compatibility |
.equ PORTA5 = 5 ; Port A Data Register bit 5 |
.equ PA5 = 5 ; For compatibility |
.equ PORTA6 = 6 ; Port A Data Register bit 6 |
.equ PA6 = 6 ; For compatibility |
.equ PORTA7 = 7 ; Port A Data Register bit 7 |
.equ PA7 = 7 ; For compatibility |
; DDRA - Port A Data Direction Register |
.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0 |
.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1 |
.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2 |
.equ DDA3 = 3 ; Data Direction Register, Port A, bit 3 |
.equ DDA4 = 4 ; Data Direction Register, Port A, bit 4 |
.equ DDA5 = 5 ; Data Direction Register, Port A, bit 5 |
.equ DDA6 = 6 ; Data Direction Register, Port A, bit 6 |
.equ DDA7 = 7 ; Data Direction Register, Port A, bit 7 |
; PINA - Port A Input Pins |
.equ PINA0 = 0 ; Input Pins, Port A bit 0 |
.equ PINA1 = 1 ; Input Pins, Port A bit 1 |
.equ PINA2 = 2 ; Input Pins, Port A bit 2 |
.equ PINA3 = 3 ; Input Pins, Port A bit 3 |
.equ PINA4 = 4 ; Input Pins, Port A bit 4 |
.equ PINA5 = 5 ; Input Pins, Port A bit 5 |
.equ PINA6 = 6 ; Input Pins, Port A bit 6 |
.equ PINA7 = 7 ; Input Pins, Port A bit 7 |
; ***** PORTB ************************ |
; PORTB - Port B Data Register |
.equ PORTB0 = 0 ; Port B Data Register bit 0 |
.equ PB0 = 0 ; For compatibility |
.equ PORTB1 = 1 ; Port B Data Register bit 1 |
.equ PB1 = 1 ; For compatibility |
.equ PORTB2 = 2 ; Port B Data Register bit 2 |
.equ PB2 = 2 ; For compatibility |
.equ PORTB3 = 3 ; Port B Data Register bit 3 |
.equ PB3 = 3 ; For compatibility |
.equ PORTB4 = 4 ; Port B Data Register bit 4 |
.equ PB4 = 4 ; For compatibility |
.equ PORTB5 = 5 ; Port B Data Register bit 5 |
.equ PB5 = 5 ; For compatibility |
.equ PORTB6 = 6 ; Port B Data Register bit 6 |
.equ PB6 = 6 ; For compatibility |
.equ PORTB7 = 7 ; Port B Data Register bit 7 |
.equ PB7 = 7 ; For compatibility |
; DDRB - Port B Data Direction Register |
.equ DDB0 = 0 ; Port B Data Direction Register bit 0 |
.equ DDB1 = 1 ; Port B Data Direction Register bit 1 |
.equ DDB2 = 2 ; Port B Data Direction Register bit 2 |
.equ DDB3 = 3 ; Port B Data Direction Register bit 3 |
.equ DDB4 = 4 ; Port B Data Direction Register bit 4 |
.equ DDB5 = 5 ; Port B Data Direction Register bit 5 |
.equ DDB6 = 6 ; Port B Data Direction Register bit 6 |
.equ DDB7 = 7 ; Port B Data Direction Register bit 7 |
; PINB - Port B Input Pins |
.equ PINB0 = 0 ; Port B Input Pins bit 0 |
.equ PINB1 = 1 ; Port B Input Pins bit 1 |
.equ PINB2 = 2 ; Port B Input Pins bit 2 |
.equ PINB3 = 3 ; Port B Input Pins bit 3 |
.equ PINB4 = 4 ; Port B Input Pins bit 4 |
.equ PINB5 = 5 ; Port B Input Pins bit 5 |
.equ PINB6 = 6 ; Port B Input Pins bit 6 |
.equ PINB7 = 7 ; Port B Input Pins bit 7 |
; ***** PORTC ************************ |
; PORTC - Port C Data Register |
.equ PORTC0 = 0 ; Port C Data Register bit 0 |
.equ PC0 = 0 ; For compatibility |
.equ PORTC1 = 1 ; Port C Data Register bit 1 |
.equ PC1 = 1 ; For compatibility |
.equ PORTC2 = 2 ; Port C Data Register bit 2 |
.equ PC2 = 2 ; For compatibility |
.equ PORTC3 = 3 ; Port C Data Register bit 3 |
.equ PC3 = 3 ; For compatibility |
.equ PORTC4 = 4 ; Port C Data Register bit 4 |
.equ PC4 = 4 ; For compatibility |
.equ PORTC5 = 5 ; Port C Data Register bit 5 |
.equ PC5 = 5 ; For compatibility |
.equ PORTC6 = 6 ; Port C Data Register bit 6 |
.equ PC6 = 6 ; For compatibility |
.equ PORTC7 = 7 ; Port C Data Register bit 7 |
.equ PC7 = 7 ; For compatibility |
; DDRC - Port C Data Direction Register |
.equ DDC0 = 0 ; Port C Data Direction Register bit 0 |
.equ DDC1 = 1 ; Port C Data Direction Register bit 1 |
.equ DDC2 = 2 ; Port C Data Direction Register bit 2 |
.equ DDC3 = 3 ; Port C Data Direction Register bit 3 |
.equ DDC4 = 4 ; Port C Data Direction Register bit 4 |
.equ DDC5 = 5 ; Port C Data Direction Register bit 5 |
.equ DDC6 = 6 ; Port C Data Direction Register bit 6 |
.equ DDC7 = 7 ; Port C Data Direction Register bit 7 |
; PINC - Port C Input Pins |
.equ PINC0 = 0 ; Port C Input Pins bit 0 |
.equ PINC1 = 1 ; Port C Input Pins bit 1 |
.equ PINC2 = 2 ; Port C Input Pins bit 2 |
.equ PINC3 = 3 ; Port C Input Pins bit 3 |
.equ PINC4 = 4 ; Port C Input Pins bit 4 |
.equ PINC5 = 5 ; Port C Input Pins bit 5 |
.equ PINC6 = 6 ; Port C Input Pins bit 6 |
.equ PINC7 = 7 ; Port C Input Pins bit 7 |
; ***** PORTD ************************ |
; PORTD - Port D Data Register |
.equ PORTD0 = 0 ; Port D Data Register bit 0 |
.equ PD0 = 0 ; For compatibility |
.equ PORTD1 = 1 ; Port D Data Register bit 1 |
.equ PD1 = 1 ; For compatibility |
.equ PORTD2 = 2 ; Port D Data Register bit 2 |
.equ PD2 = 2 ; For compatibility |
.equ PORTD3 = 3 ; Port D Data Register bit 3 |
.equ PD3 = 3 ; For compatibility |
.equ PORTD4 = 4 ; Port D Data Register bit 4 |
.equ PD4 = 4 ; For compatibility |
.equ PORTD5 = 5 ; Port D Data Register bit 5 |
.equ PD5 = 5 ; For compatibility |
.equ PORTD6 = 6 ; Port D Data Register bit 6 |
.equ PD6 = 6 ; For compatibility |
.equ PORTD7 = 7 ; Port D Data Register bit 7 |
.equ PD7 = 7 ; For compatibility |
; DDRD - Port D Data Direction Register |
.equ DDD0 = 0 ; Port D Data Direction Register bit 0 |
.equ DDD1 = 1 ; Port D Data Direction Register bit 1 |
.equ DDD2 = 2 ; Port D Data Direction Register bit 2 |
.equ DDD3 = 3 ; Port D Data Direction Register bit 3 |
.equ DDD4 = 4 ; Port D Data Direction Register bit 4 |
.equ DDD5 = 5 ; Port D Data Direction Register bit 5 |
.equ DDD6 = 6 ; Port D Data Direction Register bit 6 |
.equ DDD7 = 7 ; Port D Data Direction Register bit 7 |
; PIND - Port D Input Pins |
.equ PIND0 = 0 ; Port D Input Pins bit 0 |
.equ PIND1 = 1 ; Port D Input Pins bit 1 |
.equ PIND2 = 2 ; Port D Input Pins bit 2 |
.equ PIND3 = 3 ; Port D Input Pins bit 3 |
.equ PIND4 = 4 ; Port D Input Pins bit 4 |
.equ PIND5 = 5 ; Port D Input Pins bit 5 |
.equ PIND6 = 6 ; Port D Input Pins bit 6 |
.equ PIND7 = 7 ; Port D Input Pins bit 7 |
; ***** TIMER_COUNTER_0 ************** |
; TCCR0 - Timer/Counter 0 Control Register |
.equ CS00 = 0 ; Clock Select 1 |
.equ CS01 = 1 ; Clock Select 1 |
.equ CS02 = 2 ; Clock Select 2 |
.equ WGM01 = 3 ; Waveform Generation Mode 1 |
.equ CTC0 = WGM01 ; For compatibility |
.equ COM00 = 4 ; Compare match Output Mode 0 |
.equ COM01 = 5 ; Compare Match Output Mode 1 |
.equ WGM00 = 6 ; Waveform Generation Mode 0 |
.equ PWM0 = WGM00 ; For compatibility |
.equ FOC0 = 7 ; Force Output Compare |
; TCNT0 - Timer/Counter 0 Register |
.equ TCNT0_0 = 0 ; |
.equ TCNT0_1 = 1 ; |
.equ TCNT0_2 = 2 ; |
.equ TCNT0_3 = 3 ; |
.equ TCNT0_4 = 4 ; |
.equ TCNT0_5 = 5 ; |
.equ TCNT0_6 = 6 ; |
.equ TCNT0_7 = 7 ; |
; OCR0 - Timer/Counter 0 Output Compare Register |
.equ OCR0_0 = 0 ; |
.equ OCR0_1 = 1 ; |
.equ OCR0_2 = 2 ; |
.equ OCR0_3 = 3 ; |
.equ OCR0_4 = 4 ; |
.equ OCR0_5 = 5 ; |
.equ OCR0_6 = 6 ; |
.equ OCR0_7 = 7 ; |
; TIMSK - Timer/Counter Interrupt Mask Register |
.equ OCIE0 = 0 ; Timer/Counter0 Output Compare Match Interrupt register |
.equ TOIE0 = 1 ; Timer/Counter0 Overflow Interrupt Enable |
; TIFR - Timer/Counter Interrupt Flag register |
.equ OCF0 = 0 ; Output Compare Flag 0 |
.equ TOV0 = 1 ; Timer/Counter0 Overflow Flag |
; ***** WATCHDOG ********************* |
; WDTCR - Watchdog Timer Control Register |
.equ WDTCSR = WDTCR ; For compatibility |
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 |
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 |
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 |
.equ WDE = 3 ; Watch Dog Enable |
.equ WDCE = 4 ; Watchdog Change Enable |
.equ WDTOE = WDCE ; For compatibility |
; ***** PORTE ************************ |
; PORTE - Data Register, Port E |
.equ PORTE0 = 0 ; |
.equ PE0 = 0 ; For compatibility |
.equ PORTE1 = 1 ; |
.equ PE1 = 1 ; For compatibility |
.equ PORTE2 = 2 ; |
.equ PE2 = 2 ; For compatibility |
; DDRE |
.equ DDE0 = 0 ; |
.equ DDE1 = 1 ; |
.equ DDE2 = 2 ; |
; PINE - Input Pins, Port E |
.equ PINE0 = 0 ; |
.equ PINE1 = 1 ; |
.equ PINE2 = 2 ; |
.equ PINE3 = 3 ; |
; ***** EXTERNAL_INTERRUPT *********** |
; MCUCR - MCU Control Register |
;.equ ISC00 = 0 ; Interrupt Sense Control 0 Bit 0 |
;.equ ISC01 = 1 ; Interrupt Sense Control 0 Bit 1 |
;.equ ISC10 = 2 ; Interrupt Sense Control 1 Bit 0 |
;.equ ISC11 = 3 ; Interrupt Sense Control 1 Bit 1 |
; EMCUCR - Extended MCU Control Register |
;.equ ISC2 = 0 ; Interrupt Sense Control 2 |
; GICR - General Interrupt Control Register |
.equ EIMSK = GICR ; For compatibility |
.equ GIMSK = GICR ; For compatibility |
.equ IVCE = 0 ; Interrupt Vector Change Enable |
.equ IVSEL = 1 ; Interrupt Vector Select |
.equ PCIE0 = 3 ; Pin Change Interrupt Enable 0 |
.equ PCIE1 = 4 ; Pin Change Interrupt Enable 1 |
.equ INT2 = 5 ; External Interrupt Request 2 Enable |
.equ INT0 = 6 ; External Interrupt Request 0 Enable |
.equ INT1 = 7 ; External Interrupt Request 1 Enable |
; GIFR - General Interrupt Flag Register |
.equ PCIF0 = 3 ; Pin Change Interrupt Flag 0 |
.equ PCIF1 = 4 ; Pin Change Interrupt Flag 1 |
.equ INTF2 = 5 ; External Interrupt Flag 2 |
.equ INTF0 = 6 ; External Interrupt Flag 0 |
.equ INTF1 = 7 ; External Interrupt Flag 1 |
; PCMSK1 - Pin Change Mask Register 1 |
.equ PCINT8 = 0 ; Pin Change Enable Mask 8 |
.equ PCINT9 = 1 ; Pin Change Enable Mask 9 |
.equ PCINT10 = 2 ; Pin Change Enable Mask 10 |
.equ PCINT11 = 3 ; Pin Change Enable Mask 11 |
.equ PCINT12 = 4 ; Pin Change Enable Mask 12 |
.equ PCINT13 = 5 ; Pin Change Enable Mask 13 |
.equ PCINT14 = 6 ; Pin Change Enable Mask 14 |
.equ PCINT15 = 7 ; Pin Change Enable Mask 15 |
; PCMSK0 - Pin Change Enable Mask |
.equ PCINT0 = 0 ; Pin Change Enable Mask 0 |
.equ PCINT1 = 1 ; Pin Change Enable Mask 1 |
.equ PCINT2 = 2 ; Pin Change Enable Mask 2 |
.equ PCINT3 = 3 ; Pin Change Enable Mask 3 |
.equ PCINT4 = 4 ; Pin Change Enable Mask 4 |
.equ PCINT5 = 5 ; Pin Change Enable Mask 5 |
.equ PCINT6 = 6 ; Pin Change Enable Mask 6 |
.equ PCINT7 = 7 ; Pin Change Enable Mask 7 |
; ***** LOCKSBITS ******************************************************** |
.equ LB1 = 0 ; Lock bit |
.equ LB2 = 1 ; Lock bit |
.equ BLB01 = 2 ; Boot Lock bit |
.equ BLB02 = 3 ; Boot Lock bit |
.equ BLB11 = 4 ; Boot lock bit |
.equ BLB12 = 5 ; Boot lock bit |
; ***** FUSES ************************************************************ |
; LOW fuse bits |
.equ CKSEL0 = 0 ; Select Clock Source |
.equ CKSEL1 = 1 ; Select Clock Source |
.equ CKSEL2 = 2 ; Select Clock Source |
.equ CKSEL3 = 3 ; Select Clock Source |
.equ SUT0 = 4 ; Select start-up time |
.equ SUT1 = 5 ; Select start-up time |
.equ CKOUT = 6 ; Oscillator options |
.equ CLKDIV8 = 7 ; Divide clock by 8 |
; HIGH fuse bits |
.equ BOOTRST = 0 ; Select Reset Vector |
.equ BOOTSZ0 = 1 ; Select Boot Size |
.equ BOOTSZ1 = 2 ; Select Boot Size |
.equ EESAVE = 3 ; EEPROM memory is preserved through chip erase |
.equ WDTON = 4 ; Watchdog timer always on |
.equ SPIEN = 5 ; Enable Serial programming and Data Downloading |
.equ JTAGEN = 6 ; Enable JTAG |
.equ OCDEN = 7 ; Enable OCD |
; EXTENDED fuse bits |
.equ BODLEVEL0 = 1 ; Brown out detector trigger level |
.equ BODLEVEL1 = 2 ; Brown out detector trigger level |
.equ BODLEVEL2 = 3 ; Brown out detector trigger level |
.equ M161C = 4 ; ATMega 161 compatibility mode |
; ***** CPU REGISTER DEFINITIONS ***************************************** |
.def XH = r27 |
.def XL = r26 |
.def YH = r29 |
.def YL = r28 |
.def ZH = r31 |
.def ZL = r30 |
; ***** DATA MEMORY DECLARATIONS ***************************************** |
.equ FLASHEND = 0x1fff ; Note: Word address |
.equ IOEND = 0x00ff |
.equ SRAM_START = 0x0100 |
.equ SRAM_SIZE = 1024 |
.equ RAMEND = 0x04ff |
.equ XRAMEND = 0xffff |
.equ E2END = 0x01ff |
.equ EEPROMEND = 0x01ff |
.equ EEADRBITS = 9 |
#pragma AVRPART MEMORY PROG_FLASH 16384 |
#pragma AVRPART MEMORY EEPROM 512 |
#pragma AVRPART MEMORY INT_SRAM SIZE 1024 |
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x100 |
; ***** BOOTLOADER DECLARATIONS ****************************************** |
.equ NRWW_START_ADDR = 0x1c00 |
.equ NRWW_STOP_ADDR = 0x1fff |
.equ RWW_START_ADDR = 0x0 |
.equ RWW_STOP_ADDR = 0x1bff |
.equ PAGESIZE = 64 |
.equ FIRSTBOOTSTART = 0x1f80 |
.equ SECONDBOOTSTART = 0x1f00 |
.equ THIRDBOOTSTART = 0x1e00 |
.equ FOURTHBOOTSTART = 0x1c00 |
.equ SMALLBOOTSTART = FIRSTBOOTSTART |
.equ LARGEBOOTSTART = FOURTHBOOTSTART |
; ***** INTERRUPT VECTORS ************************************************ |
.equ INT0addr = 0x0002 ; External Interrupt Request 0 |
.equ INT1addr = 0x0004 ; External Interrupt Request 1 |
.equ INT2addr = 0x0006 ; External Interrupt Request 2 |
.equ PCI0addr = 0x0008 ; Pin Change Interrupt Request 0 |
.equ PCI1addr = 0x000a ; Pin Change Interrupt Request 1 |
.equ ICP3addr = 0x000c ; Timer/Counter3 Capture Event |
.equ OC3Aaddr = 0x000e ; Timer/Counter3 Compare Match A |
.equ OC3Baddr = 0x0010 ; Timer/Counter3 Compare Match B |
.equ OVF3addr = 0x0012 ; Timer/Counter3 Overflow |
.equ OC2addr = 0x0014 ; Timer/Counter2 Compare Match |
.equ OVF2addr = 0x0016 ; Timer/Counter2 Overflow |
.equ ICP1addr = 0x0018 ; Timer/Counter1 Capture Event |
.equ OC1Aaddr = 0x001a ; Timer/Counter1 Compare Match A |
.equ OC1Baddr = 0x001c ; Timer/Counter Compare Match B |
.equ OVF1addr = 0x001e ; Timer/Counter1 Overflow |
.equ OC0addr = 0x0020 ; Timer/Counter0 Compare Match |
.equ OVF0addr = 0x0022 ; Timer/Counter0 Overflow |
.equ SPIaddr = 0x0024 ; SPI Serial Transfer Complete |
.equ URXC0addr = 0x0026 ; USART0, Rx Complete |
.equ URXC1addr = 0x0028 ; USART1, Rx Complete |
.equ UDRE0addr = 0x002a ; USART0 Data register Empty |
.equ UDRE1addr = 0x002c ; USART1, Data register Empty |
.equ UTXC0addr = 0x002e ; USART0, Tx Complete |
.equ UTXC1addr = 0x0030 ; USART1, Tx Complete |
.equ ERDYaddr = 0x0032 ; EEPROM Ready |
.equ ACIaddr = 0x0034 ; Analog Comparator |
.equ SPMRaddr = 0x0036 ; Store Program Memory Read |
.equ INT_VECTORS_SIZE = 56 ; size in words |
#endif /* _M162DEF_INC_ */ |
; ***** END OF FILE ****************************************************** |
/contrib/toolchain/avra/includes/m163def.inc |
---|
0,0 → 1,743 |
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** |
;***** Created: 2005-01-11 10:30 ******* Source: ATmega163.xml *********** |
;************************************************************************* |
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y |
;* |
;* Number : AVR000 |
;* File Name : "m163def.inc" |
;* Title : Register/Bit Definitions for the ATmega163 |
;* Date : 2005-01-11 |
;* Version : 2.14 |
;* Support E-mail : avr@atmel.com |
;* Target MCU : ATmega163 |
;* |
;* DESCRIPTION |
;* When including this file in the assembly program file, all I/O register |
;* names and I/O register bit names appearing in the data book can be used. |
;* In addition, the six registers forming the three data pointers X, Y and |
;* Z have been assigned names XL - ZH. Highest RAM address for Internal |
;* SRAM is also defined |
;* |
;* The Register names are represented by their hexadecimal address. |
;* |
;* The Register Bit names are represented by their bit number (0-7). |
;* |
;* Please observe the difference in using the bit names with instructions |
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" |
;* (skip if bit in register set/cleared). The following example illustrates |
;* this: |
;* |
;* in r16,PORTB ;read PORTB latch |
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) |
;* out PORTB,r16 ;output to PORTB |
;* |
;* in r16,TIFR ;read the Timer Interrupt Flag Register |
;* sbrc r16,TOV0 ;test the overflow flag (use bit#) |
;* rjmp TOV0_is_set ;jump if set |
;* ... ;otherwise do something else |
;************************************************************************* |
#ifndef _M163DEF_INC_ |
#define _M163DEF_INC_ |
#pragma partinc 0 |
; ***** SPECIFY DEVICE *************************************************** |
.device ATmega163 |
#pragma AVRPART ADMIN PART_NAME ATmega163 |
.equ SIGNATURE_000 = 0x1e |
.equ SIGNATURE_001 = 0x94 |
.equ SIGNATURE_002 = 0x02 |
#pragma AVRPART CORE CORE_VERSION V2E |
; ***** I/O REGISTER DEFINITIONS ***************************************** |
; NOTE: |
; Definitions marked "MEMORY MAPPED"are extended I/O ports |
; and cannot be used with IN/OUT instructions |
.equ SREG = 0x3f |
.equ SPH = 0x3e |
.equ SPL = 0x3d |
.equ GIMSK = 0x3b |
.equ GIFR = 0x3a |
.equ TIMSK = 0x39 |
.equ TIFR = 0x38 |
.equ SPMCR = 0x37 |
.equ TWCR = 0x36 |
.equ MCUCR = 0x35 |
.equ MCUSR = 0x34 |
.equ TCCR0 = 0x33 |
.equ TCNT0 = 0x32 |
.equ OSCCAL = 0x31 |
.equ SFIOR = 0x30 |
.equ TCCR1A = 0x2f |
.equ TCCR1B = 0x2e |
.equ TCNT1H = 0x2d |
.equ TCNT1L = 0x2c |
.equ OCR1AH = 0x2b |
.equ OCR1AL = 0x2a |
.equ OCR1BH = 0x29 |
.equ OCR1BL = 0x28 |
.equ ICR1H = 0x27 |
.equ ICR1L = 0x26 |
.equ TCCR2 = 0x25 |
.equ TCNT2 = 0x24 |
.equ OCR2 = 0x23 |
.equ ASSR = 0x22 |
.equ WDTCR = 0x21 |
.equ UBRRHI = 0x20 |
.equ EEARH = 0x1f |
.equ EEARL = 0x1e |
.equ EEDR = 0x1d |
.equ EECR = 0x1c |
.equ PORTA = 0x1b |
.equ DDRA = 0x1a |
.equ PINA = 0x19 |
.equ PORTB = 0x18 |
.equ DDRB = 0x17 |
.equ PINB = 0x16 |
.equ PORTC = 0x15 |
.equ DDRC = 0x14 |
.equ PINC = 0x13 |
.equ PORTD = 0x12 |
.equ DDRD = 0x11 |
.equ PIND = 0x10 |
.equ SPDR = 0x0f |
.equ SPSR = 0x0e |
.equ SPCR = 0x0d |
.equ UDR = 0x0c |
.equ UCSRA = 0x0b |
.equ UCSRB = 0x0a |
.equ UBRR = 0x09 |
.equ ACSR = 0x08 |
.equ ADMUX = 0x07 |
.equ ADCSRA = 0x06 |
.equ ADCH = 0x05 |
.equ ADCL = 0x04 |
.equ TWDR = 0x03 |
.equ TWAR = 0x02 |
.equ TWSR = 0x01 |
.equ TWBR = 0x00 |
; ***** BIT DEFINITIONS ************************************************** |
; ***** TIMER_COUNTER_0 ************** |
; TIMSK - Timer/Counter Interrupt Mask Register |
.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable |
; TIFR - Timer/Counter Interrupt Flag register |
.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag |
; TCCR0 - Timer/Counter0 Control Register |
.equ CS00 = 0 ; Clock Select0 bit 0 |
.equ CS01 = 1 ; Clock Select0 bit 1 |
.equ CS02 = 2 ; Clock Select0 bit 2 |
; TCNT0 - Timer Counter 0 |
.equ TCNT00 = 0 ; Timer Counter 0 bit 0 |
.equ TCNT01 = 1 ; Timer Counter 0 bit 1 |
.equ TCNT02 = 2 ; Timer Counter 0 bit 2 |
.equ TCNT03 = 3 ; Timer Counter 0 bit 3 |
.equ TCNT04 = 4 ; Timer Counter 0 bit 4 |
.equ TCNT05 = 5 ; Timer Counter 0 bit 5 |
.equ TCNT06 = 6 ; Timer Counter 0 bit 6 |
.equ TCNT07 = 7 ; Timer Counter 0 bit 7 |
; ***** CPU ************************** |
; SREG - Status Register |
.equ SREG_C = 0 ; Carry Flag |
.equ SREG_Z = 1 ; Zero Flag |
.equ SREG_N = 2 ; Negative Flag |
.equ SREG_V = 3 ; Two's Complement Overflow Flag |
.equ SREG_S = 4 ; Sign Bit |
.equ SREG_H = 5 ; Half Carry Flag |
.equ SREG_T = 6 ; Bit Copy Storage |
.equ SREG_I = 7 ; Global Interrupt Enable |
; OSCCAL - Oscillator Calibration Value |
.equ CAL0 = 0 ; Oscillator Calibration Value Bit0 |
.equ CAL1 = 1 ; Oscillator Calibration Value Bit1 |
.equ CAL2 = 2 ; Oscillator Calibration Value Bit2 |
.equ CAL3 = 3 ; Oscillator Calibration Value Bit3 |
.equ CAL4 = 4 ; Oscillator Calibration Value Bit4 |
.equ CAL5 = 5 ; Oscillator Calibration Value Bit5 |
.equ CAL6 = 6 ; Oscillator Calibration Value Bit6 |
.equ CAL7 = 7 ; Oscillator Calibration Value Bit7 |
; MCUCR - MCU Control register |
.equ ISC00 = 0 ; Interrupt Sense Control 0 Bit 0 |
.equ ISC01 = 1 ; Interrupt Sense Control 0 Bit 1 |
.equ ISC10 = 2 ; Interrupt Sense Control 1 Bit 0 |
.equ ISC11 = 3 ; Interrupt Sense Control 1 Bit 1 |
.equ SM0 = 4 ; Sleep Mode Select Bit 1 |
.equ SM1 = 5 ; Sleep Mode Select Bit 1 |
.equ SE = 6 ; Sleep enable |
; MCUSR - MCU Status Register |
.equ PORF = 0 ; Power-on reset flag |
.equ EXTRF = 1 ; External Reset Flag |
.equ EXTREF = EXTRF ; For compatibility |
.equ BORF = 2 ; Brown-out Reset Flag |
.equ WDRF = 3 ; Watchdog Reset Flag |
; SFIOR - MCU Status Register |
.equ PSR10 = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0 |
.equ PSR2 = 1 ; Prescaler Reset Timer/Counter2 |
.equ PUD = 2 ; Pull-up Disable |
.equ ACME = 3 ; Analog Comparator multiplexer Enable |
; ***** TIMER_COUNTER_1 ************** |
; TIMSK - Timer/Counter Interrupt Mask Register |
.equ TOIE1 = 2 ; Timer/Counter1 Overflow Interrupt Enable |
.equ OCIE1B = 3 ; Timer/Counter1 Output CompareB Match Interrupt Enable |
.equ OCIE1A = 4 ; Timer/Counter1 Output CompareA Match Interrupt Enable |
.equ TICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable |
; TIFR - Timer/Counter Interrupt Flag register |
.equ TOV1 = 2 ; Timer/Counter1 Overflow Flag |
.equ OCF1B = 3 ; Output Compare Flag 1B |
.equ OCF1A = 4 ; Output Compare Flag 1A |
.equ ICF1 = 5 ; Input Capture Flag 1 |
; TCCR1A - Timer/Counter1 Control Register A |
.equ PWM10 = 0 ; Pulse Width Modulator Select Bits |
.equ PWM11 = 1 ; Pulse Width Modulator Select Bits |
.equ FOC1B = 2 ; Force Output Compare 1B |
.equ FOC1A = 3 ; Force Output Compare 1A |
.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0 |
.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1 |
.equ COM1A0 = 6 ; Comparet Ouput Mode 1A, bit 0 |
.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1 |
; TCCR1B - Timer/Counter1 Control Register B |
.equ CS10 = 0 ; Prescaler source of Timer/Counter 1 |
.equ CS11 = 1 ; Prescaler source of Timer/Counter 1 |
.equ CS12 = 2 ; Prescaler source of Timer/Counter 1 |
.equ CTC1 = 3 ; Clear Timer/Counter1 on Compare Match |
.equ ICES1 = 6 ; Input Capture 1 Edge Select |
.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler |
; ***** TIMER_COUNTER_2 ************** |
; TIMSK - Timer/Counter Interrupt Mask register |
.equ TOIE2 = 6 ; Timer/Counter2 Overflow Interrupt Enable |
.equ OCIE2 = 7 ; Timer/Counter2 Output Compare Match Interrupt Enable |
; TIFR - Timer/Counter Interrupt Flag Register |
.equ TOV2 = 6 ; Timer/Counter2 Overflow Flag |
.equ OCF2 = 7 ; Output Compare Flag 2 |
; TCCR2 - Timer/Counter2 Control Register |
.equ CS20 = 0 ; Clock Select bit 0 |
.equ CS21 = 1 ; Clock Select bit 1 |
.equ CS22 = 2 ; Clock Select bit 2 |
.equ CTC2 = 3 ; Clear Timer/Counter2 on Compare Match |
.equ COM20 = 4 ; Compare Output Mode bit 0 |
.equ COM21 = 5 ; Compare Output Mode bit 1 |
.equ PWM2 = 6 ; Pulse Width Modulator Enable |
.equ FOC2 = 7 ; Force Output Compare |
; TCNT2 - Timer/Counter2 |
.equ TCNT2_0 = 0 ; Timer/Counter 2 bit 0 |
.equ TCNT2_1 = 1 ; Timer/Counter 2 bit 1 |
.equ TCNT2_2 = 2 ; Timer/Counter 2 bit 2 |
.equ TCNT2_3 = 3 ; Timer/Counter 2 bit 3 |
.equ TCNT2_4 = 4 ; Timer/Counter 2 bit 4 |
.equ TCNT2_5 = 5 ; Timer/Counter 2 bit 5 |
.equ TCNT2_6 = 6 ; Timer/Counter 2 bit 6 |
.equ TCNT2_7 = 7 ; Timer/Counter 2 bit 7 |
; OCR2 - Timer/Counter2 Output Compare Register |
.equ OCR2_0 = 0 ; Timer/Counter2 Output Compare Register Bit 0 |
.equ OCR2_1 = 1 ; Timer/Counter2 Output Compare Register Bit 1 |
.equ OCR2_2 = 2 ; Timer/Counter2 Output Compare Register Bit 2 |
.equ OCR2_3 = 3 ; Timer/Counter2 Output Compare Register Bit 3 |
.equ OCR2_4 = 4 ; Timer/Counter2 Output Compare Register Bit 4 |
.equ OCR2_5 = 5 ; Timer/Counter2 Output Compare Register Bit 5 |
.equ OCR2_6 = 6 ; Timer/Counter2 Output Compare Register Bit 6 |
.equ OCR2_7 = 7 ; Timer/Counter2 Output Compare Register Bit 7 |
; ASSR - Asynchronous Status Register |
.equ TCR2UB = 0 ; Timer/counter Control Register2 Update Busy |
.equ OCR2UB = 1 ; Output Compare Register2 Update Busy |
.equ TCN2UB = 2 ; Timer/Counter2 Update Busy |
.equ AS2 = 3 ; Asynchronous Timer/counter2 |
; ***** WATCHDOG ********************* |
; WDTCR - Watchdog Timer Control Register |
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 |
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 |
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 |
.equ WDE = 3 ; Watch Dog Enable |
.equ WDTOE = 4 ; RW |
.equ WDDE = WDTOE ; For compatibility |
; ***** EEPROM *********************** |
; EEDR - EEPROM Data Register |
.equ EEDR0 = 0 ; EEPROM Data Register bit 0 |
.equ EEDR1 = 1 ; EEPROM Data Register bit 1 |
.equ EEDR2 = 2 ; EEPROM Data Register bit 2 |
.equ EEDR3 = 3 ; EEPROM Data Register bit 3 |
.equ EEDR4 = 4 ; EEPROM Data Register bit 4 |
.equ EEDR5 = 5 ; EEPROM Data Register bit 5 |
.equ EEDR6 = 6 ; EEPROM Data Register bit 6 |
.equ EEDR7 = 7 ; EEPROM Data Register bit 7 |
; EECR - EEPROM Control Register |
.equ EERE = 0 ; EEPROM Read Enable |
.equ EEWE = 1 ; EEPROM Write Enable |
.equ EEMWE = 2 ; EEPROM Master Write Enable |
.equ EEWEE = EEMWE ; For compatibility |
.equ EERIE = 3 ; EEPROM Ready Interrupt Enable |
; ***** SPI ************************** |
; SPDR - SPI Data Register |
.equ SPDR0 = 0 ; SPI Data Register bit 0 |
.equ SPDR1 = 1 ; SPI Data Register bit 1 |
.equ SPDR2 = 2 ; SPI Data Register bit 2 |
.equ SPDR3 = 3 ; SPI Data Register bit 3 |
.equ SPDR4 = 4 ; SPI Data Register bit 4 |
.equ SPDR5 = 5 ; SPI Data Register bit 5 |
.equ SPDR6 = 6 ; SPI Data Register bit 6 |
.equ SPDR7 = 7 ; SPI Data Register bit 7 |
; SPSR - SPI Status Register |
.equ SPI2X = 0 ; Double SPI Speed Bit |
.equ WCOL = 6 ; Write Collision Flag |
.equ SPIF = 7 ; SPI Interrupt Flag |
; SPCR - SPI Control Register |
.equ SPR0 = 0 ; SPI Clock Rate Select 0 |
.equ SPR1 = 1 ; SPI Clock Rate Select 1 |
.equ CPHA = 2 ; Clock Phase |
.equ CPOL = 3 ; Clock polarity |
.equ MSTR = 4 ; Master/Slave Select |
.equ DORD = 5 ; Data Order |
.equ SPE = 6 ; SPI Enable |
.equ SPIE = 7 ; SPI Interrupt Enable |
; ***** UART ************************* |
; UDR - UART I/O Data Register |
.equ UDR0 = 0 ; UART I/O Data Register bit 0 |
.equ UDR1 = 1 ; UART I/O Data Register bit 1 |
.equ UDR2 = 2 ; UART I/O Data Register bit 2 |
.equ UDR3 = 3 ; UART I/O Data Register bit 3 |
.equ UDR4 = 4 ; UART I/O Data Register bit 4 |
.equ UDR5 = 5 ; UART I/O Data Register bit 5 |
.equ UDR6 = 6 ; UART I/O Data Register bit 6 |
.equ UDR7 = 7 ; UART I/O Data Register bit 7 |
; UCSRA - UART Control and Status register A |
.equ MPCM = 0 ; Multi Processor Communication Mode |
.equ U2X = 1 ; Double the UART Transmission Speed |
.equ DOR = 3 ; Data overRun |
.equ FE = 4 ; Framing Error |
.equ UDRE = 5 ; UART Data Register Empty |
.equ TXC = 6 ; UART Transmitt Complete |
.equ RXC = 7 ; UART Receive Complete |
; UCSRB - UART Control an Status register B |
.equ TXB8 = 0 ; Transmit Data Bit 8 |
.equ RXB8 = 1 ; Receive Data Bit 8 |
.equ CHR9 = 2 ; 9-bit Characters |
.equ TXEN = 3 ; Transmitter Enable |
.equ RXEN = 4 ; Receiver Enable |
.equ UDRIE = 5 ; UART Data Register Empty Interrupt Enable |
.equ TXCIE = 6 ; TX Complete Interrupt Enable |
.equ RXCIE = 7 ; RX Complete Interrupt Enable |
; UBRRHI - UART Baud Rate Register High Byte |
.equ UBRRHI0 = 0 ; UART Baud Rate Register High Byte bit 0 |
.equ UBRRHI1 = 1 ; UART Baud Rate Register High Byte bit 1 |
.equ UBRRHI2 = 2 ; UART Baud Rate Register High Byte bit 2 |
.equ UBRRHI3 = 3 ; UART Baud Rate Register High Byte bit 3 |
; UBRR - UART Baud Rate Register |
.equ UBRR0 = 0 ; UART Baud Rate Register bit 0 |
.equ UBRR1 = 1 ; UART Baud Rate Register bit 1 |
.equ UBRR2 = 2 ; UART Baud Rate Register bit 2 |
.equ UBRR3 = 3 ; UART Baud Rate Register bit 3 |
.equ UBRR4 = 4 ; UART Baud Rate Register bit 4 |
.equ UBRR5 = 5 ; UART Baud Rate Register bit 5 |
.equ UBRR6 = 6 ; UART Baud Rate Register bit 6 |
.equ UBRR7 = 7 ; UART Baud Rate Register bit 7 |
; ***** TWI ************************** |
; TWBR - TWI Bit Rate register |
.equ TWBR0 = 0 ; |
.equ TWBR1 = 1 ; |
.equ TWBR2 = 2 ; |
.equ TWBR3 = 3 ; |
.equ TWBR4 = 4 ; |
.equ TWBR5 = 5 ; |
.equ TWBR6 = 6 ; |
.equ TWBR7 = 7 ; |
; TWCR - TWI Control Register |
.equ TWIE = 0 ; TWI Interrupt Enable |
.equ TWEN = 2 ; TWI Enable Bit |
.equ TWWC = 3 ; TWI Write Collition Flag |
.equ TWSTO = 4 ; TWI Stop Condition Bit |
.equ TWSTA = 5 ; TWI Start Condition Bit |
.equ TWEA = 6 ; TWI Enable Acknowledge Bit |
.equ TWINT = 7 ; TWI Interrupt Flag |
; TWSR - TWI Status Register |
.equ TWS3 = 3 ; TWI Status |
.equ TWS4 = 4 ; TWI Status |
.equ TWS5 = 5 ; TWI Status |
.equ TWS6 = 6 ; TWI Status |
.equ TWS7 = 7 ; TWI Status |
; TWDR - TWI Data register |
.equ TWD0 = 0 ; TWI Data Register Bit 0 |
.equ TWD1 = 1 ; TWI Data Register Bit 1 |
.equ TWD2 = 2 ; TWI Data Register Bit 2 |
.equ TWD3 = 3 ; TWI Data Register Bit 3 |
.equ TWD4 = 4 ; TWI Data Register Bit 4 |
.equ TWD5 = 5 ; TWI Data Register Bit 5 |
.equ TWD6 = 6 ; TWI Data Register Bit 6 |
.equ TWD7 = 7 ; TWI Data Register Bit 7 |
; TWAR - TWI (Slave) Address register |
.equ TWGCE = 0 ; TWI General Call Recognition Enable Bit |
.equ TWA0 = 1 ; TWI (Slave) Address register Bit 0 |
.equ TWA1 = 2 ; TWI (Slave) Address register Bit 1 |
.equ TWA2 = 3 ; TWI (Slave) Address register Bit 2 |
.equ TWA3 = 4 ; TWI (Slave) Address register Bit 3 |
.equ TWA4 = 5 ; TWI (Slave) Address register Bit 4 |
.equ TWA5 = 6 ; TWI (Slave) Address register Bit 5 |
.equ TWA6 = 7 ; TWI (Slave) Address register Bit 6 |
; ***** PORTA ************************ |
; PORTA - Port A Data Register |
.equ PORTA0 = 0 ; Port A Data Register bit 0 |
.equ PA0 = 0 ; For compatibility |
.equ PORTA1 = 1 ; Port A Data Register bit 1 |
.equ PA1 = 1 ; For compatibility |
.equ PORTA2 = 2 ; Port A Data Register bit 2 |
.equ PA2 = 2 ; For compatibility |
.equ PORTA3 = 3 ; Port A Data Register bit 3 |
.equ PA3 = 3 ; For compatibility |
.equ PORTA4 = 4 ; Port A Data Register bit 4 |
.equ PA4 = 4 ; For compatibility |
.equ PORTA5 = 5 ; Port A Data Register bit 5 |
.equ PA5 = 5 ; For compatibility |
.equ PORTA6 = 6 ; Port A Data Register bit 6 |
.equ PA6 = 6 ; For compatibility |
.equ PORTA7 = 7 ; Port A Data Register bit 7 |
.equ PA7 = 7 ; For compatibility |
; DDRA - Port A Data Direction Register |
.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0 |
.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1 |
.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2 |
.equ DDA3 = 3 ; Data Direction Register, Port A, bit 3 |
.equ DDA4 = 4 ; Data Direction Register, Port A, bit 4 |
.equ DDA5 = 5 ; Data Direction Register, Port A, bit 5 |
.equ DDA6 = 6 ; Data Direction Register, Port A, bit 6 |
.equ DDA7 = 7 ; Data Direction Register, Port A, bit 7 |
; PINA - Port A Input Pins |
.equ PINA0 = 0 ; Input Pins, Port A bit 0 |
.equ PINA1 = 1 ; Input Pins, Port A bit 1 |
.equ PINA2 = 2 ; Input Pins, Port A bit 2 |
.equ PINA3 = 3 ; Input Pins, Port A bit 3 |
.equ PINA4 = 4 ; Input Pins, Port A bit 4 |
.equ PINA5 = 5 ; Input Pins, Port A bit 5 |
.equ PINA6 = 6 ; Input Pins, Port A bit 6 |
.equ PINA7 = 7 ; Input Pins, Port A bit 7 |
; ***** PORTB ************************ |
; PORTB - Port B Data Register |
.equ PORTB0 = 0 ; Port B Data Register bit 0 |
.equ PB0 = 0 ; For compatibility |
.equ PORTB1 = 1 ; Port B Data Register bit 1 |
.equ PB1 = 1 ; For compatibility |
.equ PORTB2 = 2 ; Port B Data Register bit 2 |
.equ PB2 = 2 ; For compatibility |
.equ PORTB3 = 3 ; Port B Data Register bit 3 |
.equ PB3 = 3 ; For compatibility |
.equ PORTB4 = 4 ; Port B Data Register bit 4 |
.equ PB4 = 4 ; For compatibility |
.equ PORTB5 = 5 ; Port B Data Register bit 5 |
.equ PB5 = 5 ; For compatibility |
.equ PORTB6 = 6 ; Port B Data Register bit 6 |
.equ PB6 = 6 ; For compatibility |
.equ PORTB7 = 7 ; Port B Data Register bit 7 |
.equ PB7 = 7 ; For compatibility |
; DDRB - Port B Data Direction Register |
.equ DDB0 = 0 ; Port B Data Direction Register bit 0 |
.equ DDB1 = 1 ; Port B Data Direction Register bit 1 |
.equ DDB2 = 2 ; Port B Data Direction Register bit 2 |
.equ DDB3 = 3 ; Port B Data Direction Register bit 3 |
.equ DDB4 = 4 ; Port B Data Direction Register bit 4 |
.equ DDB5 = 5 ; Port B Data Direction Register bit 5 |
.equ DDB6 = 6 ; Port B Data Direction Register bit 6 |
.equ DDB7 = 7 ; Port B Data Direction Register bit 7 |
; PINB - Port B Input Pins |
.equ PINB0 = 0 ; Port B Input Pins bit 0 |
.equ PINB1 = 1 ; Port B Input Pins bit 1 |
.equ PINB2 = 2 ; Port B Input Pins bit 2 |
.equ PINB3 = 3 ; Port B Input Pins bit 3 |
.equ PINB4 = 4 ; Port B Input Pins bit 4 |
.equ PINB5 = 5 ; Port B Input Pins bit 5 |
.equ PINB6 = 6 ; Port B Input Pins bit 6 |
.equ PINB7 = 7 ; Port B Input Pins bit 7 |
; ***** PORTC ************************ |
; PORTC - Port C Data Register |
.equ PORTC0 = 0 ; Port C Data Register bit 0 |
.equ PC0 = 0 ; For compatibility |
.equ PORTC1 = 1 ; Port C Data Register bit 1 |
.equ PC1 = 1 ; For compatibility |
.equ PORTC2 = 2 ; Port C Data Register bit 2 |
.equ PC2 = 2 ; For compatibility |
.equ PORTC3 = 3 ; Port C Data Register bit 3 |
.equ PC3 = 3 ; For compatibility |
.equ PORTC4 = 4 ; Port C Data Register bit 4 |
.equ PC4 = 4 ; For compatibility |
.equ PORTC5 = 5 ; Port C Data Register bit 5 |
.equ PC5 = 5 ; For compatibility |
.equ PORTC6 = 6 ; Port C Data Register bit 6 |
.equ PC6 = 6 ; For compatibility |
.equ PORTC7 = 7 ; Port C Data Register bit 7 |
.equ PC7 = 7 ; For compatibility |
; DDRC - Port C Data Direction Register |
.equ DDC0 = 0 ; Port C Data Direction Register bit 0 |
.equ DDC1 = 1 ; Port C Data Direction Register bit 1 |
.equ DDC2 = 2 ; Port C Data Direction Register bit 2 |
.equ DDC3 = 3 ; Port C Data Direction Register bit 3 |
.equ DDC4 = 4 ; Port C Data Direction Register bit 4 |
.equ DDC5 = 5 ; Port C Data Direction Register bit 5 |
.equ DDC6 = 6 ; Port C Data Direction Register bit 6 |
.equ DDC7 = 7 ; Port C Data Direction Register bit 7 |
; PINC - Port C Input Pins |
.equ PINC0 = 0 ; Port C Input Pins bit 0 |
.equ PINC1 = 1 ; Port C Input Pins bit 1 |
.equ PINC2 = 2 ; Port C Input Pins bit 2 |
.equ PINC3 = 3 ; Port C Input Pins bit 3 |
.equ PINC4 = 4 ; Port C Input Pins bit 4 |
.equ PINC5 = 5 ; Port C Input Pins bit 5 |
.equ PINC6 = 6 ; Port C Input Pins bit 6 |
.equ PINC7 = 7 ; Port C Input Pins bit 7 |
; ***** PORTD ************************ |
; PORTD - Port D Data Register |
.equ PORTD0 = 0 ; Port D Data Register bit 0 |
.equ PD0 = 0 ; For compatibility |
.equ PORTD1 = 1 ; Port D Data Register bit 1 |
.equ PD1 = 1 ; For compatibility |
.equ PORTD2 = 2 ; Port D Data Register bit 2 |
.equ PD2 = 2 ; For compatibility |
.equ PORTD3 = 3 ; Port D Data Register bit 3 |
.equ PD3 = 3 ; For compatibility |
.equ PORTD4 = 4 ; Port D Data Register bit 4 |
.equ PD4 = 4 ; For compatibility |
.equ PORTD5 = 5 ; Port D Data Register bit 5 |
.equ PD5 = 5 ; For compatibility |
.equ PORTD6 = 6 ; Port D Data Register bit 6 |
.equ PD6 = 6 ; For compatibility |
.equ PORTD7 = 7 ; Port D Data Register bit 7 |
.equ PD7 = 7 ; For compatibility |
; DDRD - Port D Data Direction Register |
.equ DDD0 = 0 ; Port D Data Direction Register bit 0 |
.equ DDD1 = 1 ; Port D Data Direction Register bit 1 |
.equ DDD2 = 2 ; Port D Data Direction Register bit 2 |
.equ DDD3 = 3 ; Port D Data Direction Register bit 3 |
.equ DDD4 = 4 ; Port D Data Direction Register bit 4 |
.equ DDD5 = 5 ; Port D Data Direction Register bit 5 |
.equ DDD6 = 6 ; Port D Data Direction Register bit 6 |
.equ DDD7 = 7 ; Port D Data Direction Register bit 7 |
; PIND - Port D Input Pins |
.equ PIND0 = 0 ; Port D Input Pins bit 0 |
.equ PIND1 = 1 ; Port D Input Pins bit 1 |
.equ PIND2 = 2 ; Port D Input Pins bit 2 |
.equ PIND3 = 3 ; Port D Input Pins bit 3 |
.equ PIND4 = 4 ; Port D Input Pins bit 4 |
.equ PIND5 = 5 ; Port D Input Pins bit 5 |
.equ PIND6 = 6 ; Port D Input Pins bit 6 |
.equ PIND7 = 7 ; Port D Input Pins bit 7 |
; ***** ANALOG_COMPARATOR ************ |
; SFIOR - Special Function IO Register |
;.equ ACME = 3 ; Analog Comparator Multiplexer Enable |
; ACSR - Analog Comparator Control And Status Register |
.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 |
.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 |
.equ ACIC = 2 ; Analog Comparator Input Capture Enable |
.equ ACIE = 3 ; Analog Comparator Interrupt Enable |
.equ ACI = 4 ; Analog Comparator Interrupt Flag |
.equ ACO = 5 ; Analog Compare Output |
.equ ACBG = 6 ; Analog Comparator Bandgap Select |
.equ ACD = 7 ; Analog Comparator Disable |
; ***** AD_CONVERTER ***************** |
; ADMUX - The ADC multiplexer Selection Register |
.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits |
.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits |
.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits |
.equ MUX3 = 3 ; Analog Channel and Gain Selection Bits |
.equ MUX4 = 4 ; Analog Channel and Gain Selection Bits |
.equ ADLAR = 5 ; Left Adjust Result |
.equ REFS0 = 6 ; Reference Selection Bit 0 |
.equ REFS1 = 7 ; Reference Selection Bit 1 |
; ADCSRA - The ADC Control and Status register |
.equ ADCSR = ADCSRA ; For compatibility |
.equ ADPS0 = 0 ; ADC Prescaler Select Bits |
.equ ADPS1 = 1 ; ADC Prescaler Select Bits |
.equ ADPS2 = 2 ; ADC Prescaler Select Bits |
.equ ADIE = 3 ; ADC Interrupt Enable |
.equ ADIF = 4 ; ADC Interrupt Flag |
.equ ADFR = 5 ; ADC Free Running Select |
.equ ADSC = 6 ; ADC Start Conversion |
.equ ADEN = 7 ; ADC Enable |
; ADCH - ADC Data Register High Byte |
.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0 |
.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1 |
.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2 |
.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3 |
.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4 |
.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5 |
.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6 |
.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7 |
; ADCL - ADC Data Register Low Byte |
.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0 |
.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1 |
.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2 |
.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3 |
.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4 |
.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5 |
.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6 |
.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7 |
; ***** EXTERNAL_INTERRUPT *********** |
; GIMSK - General Interrupt Mask Register |
.equ INT0 = 6 ; External Interrupt Request 0 Enable |
.equ INT1 = 7 ; External Interrupt Request 1 Enable |
; GIFR - General Interrupt Flag register |
.equ INTF0 = 6 ; External Interrupt Flag 0 |
.equ INTF1 = 7 ; External Interrupt Flag 1 |
; ***** BOOT_LOAD ******************** |
; SPMCR - Store Program Memory Control Register |
.equ SPMEN = 0 ; Store Program Memory Enable |
.equ PGERS = 1 ; Page Erase |
.equ PGWRT = 2 ; Page Write |
.equ BLBSET = 3 ; Boot Lock Bit Set |
.equ ASRE = 4 ; Application section read enable |
.equ ASB = 6 ; Application section busy |
; ***** LOCKSBITS ******************************************************** |
.equ LB1 = 0 ; Lock bit |
.equ LB2 = 1 ; Lock bit |
.equ BLB01 = 2 ; Boot Lock bit |
.equ BLB02 = 3 ; Boot Lock bit |
.equ BLB11 = 4 ; Boot lock bit |
.equ BLB12 = 5 ; Boot lock bit |
; ***** FUSES ************************************************************ |
; LOW fuse bits |
; HIGH fuse bits |
; ***** CPU REGISTER DEFINITIONS ***************************************** |
.def XH = r27 |
.def XL = r26 |
.def YH = r29 |
.def YL = r28 |
.def ZH = r31 |
.def ZL = r30 |
; ***** DATA MEMORY DECLARATIONS ***************************************** |
.equ FLASHEND = 0x1fff ; Note: Word address |
.equ IOEND = 0x003f |
.equ SRAM_START = 0x0060 |
.equ SRAM_SIZE = 1024 |
.equ RAMEND = 0x045f |
.equ XRAMEND = 0x0000 |
.equ E2END = 0x01ff |
.equ EEPROMEND = 0x01ff |
.equ EEADRBITS = 9 |
#pragma AVRPART MEMORY PROG_FLASH 16384 |
#pragma AVRPART MEMORY EEPROM 512 |
#pragma AVRPART MEMORY INT_SRAM SIZE 1024 |
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60 |
; ***** BOOTLOADER DECLARATIONS ****************************************** |
.equ NRWW_START_ADDR = 0x0 |
.equ NRWW_STOP_ADDR = 0x1fff |
.equ PAGESIZE = 64 |
.equ FIRSTBOOTSTART = 0x1f80 |
.equ SECONDBOOTSTART = 0x1f00 |
.equ THIRDBOOTSTART = 0x1e00 |
.equ FOURTHBOOTSTART = 0x1c00 |
.equ SMALLBOOTSTART = FIRSTBOOTSTART |
.equ LARGEBOOTSTART = FOURTHBOOTSTART |
; ***** INTERRUPT VECTORS ************************************************ |
.equ INT0addr = 0x0002 ; External Interrupt 0 |
.equ INT1addr = 0x0004 ; External Interrupt 1 |
.equ OC2addr = 0x0006 ; Timer/Counter2 Compare Match |
.equ OVF2addr = 0x0008 ; Timer/Counter2 Overflow |
.equ ICP1addr = 0x000a ; Timer/Counter1 Capture Event |
.equ OC1Aaddr = 0x000c ; Timer/Counter1 Compare Match A |
.equ OC1Baddr = 0x000e ; Timer/Counter1 Compare Match B |
.equ OVF1addr = 0x0010 ; Timer/Counter1 Overflow |
.equ OVF0addr = 0x0012 ; Timer/Counter0 Overflow |
.equ SPIaddr = 0x0014 ; SPI Serial Transfer Complete |
.equ URXCaddr = 0x0016 ; UART, RX Complete |
.equ UDREaddr = 0x0018 ; UART Data Register Empty |
.equ UTXCaddr = 0x001a ; UART, TX Complete |
.equ ADCCaddr = 0x001c ; ADC Conversion Complete |
.equ ERDYaddr = 0x001e ; EEPROM Ready |
.equ ACIaddr = 0x0020 ; Analog Comparator |
.equ TWIaddr = 0x0022 ; 2-Wire Serial Interface |
.equ INT_VECTORS_SIZE = 36 ; size in words |
#pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED break |
#endif /* _M163DEF_INC_ */ |
; ***** END OF FILE ****************************************************** |
/contrib/toolchain/avra/includes/m165def.inc |
---|
0,0 → 1,1059 |
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** |
;***** Created: 2005-01-11 10:30 ******* Source: ATmega165.xml *********** |
;************************************************************************* |
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y |
;* |
;* Number : AVR000 |
;* File Name : "m165def.inc" |
;* Title : Register/Bit Definitions for the ATmega165 |
;* Date : 2005-01-11 |
;* Version : 2.14 |
;* Support E-mail : avr@atmel.com |
;* Target MCU : ATmega165 |
;* |
;* DESCRIPTION |
;* When including this file in the assembly program file, all I/O register |
;* names and I/O register bit names appearing in the data book can be used. |
;* In addition, the six registers forming the three data pointers X, Y and |
;* Z have been assigned names XL - ZH. Highest RAM address for Internal |
;* SRAM is also defined |
;* |
;* The Register names are represented by their hexadecimal address. |
;* |
;* The Register Bit names are represented by their bit number (0-7). |
;* |
;* Please observe the difference in using the bit names with instructions |
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" |
;* (skip if bit in register set/cleared). The following example illustrates |
;* this: |
;* |
;* in r16,PORTB ;read PORTB latch |
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) |
;* out PORTB,r16 ;output to PORTB |
;* |
;* in r16,TIFR ;read the Timer Interrupt Flag Register |
;* sbrc r16,TOV0 ;test the overflow flag (use bit#) |
;* rjmp TOV0_is_set ;jump if set |
;* ... ;otherwise do something else |
;************************************************************************* |
#ifndef _M165DEF_INC_ |
#define _M165DEF_INC_ |
#pragma partinc 0 |
; ***** SPECIFY DEVICE *************************************************** |
.device ATmega165 |
#pragma AVRPART ADMIN PART_NAME ATmega165 |
.equ SIGNATURE_000 = 0x1e |
.equ SIGNATURE_001 = 0x94 |
.equ SIGNATURE_002 = 0x07 |
#pragma AVRPART CORE CORE_VERSION V2E |
; ***** I/O REGISTER DEFINITIONS ***************************************** |
; NOTE: |
; Definitions marked "MEMORY MAPPED"are extended I/O ports |
; and cannot be used with IN/OUT instructions |
.equ UDR = 0xc6 ; MEMORY MAPPED |
.equ UBRRH = 0xc5 ; MEMORY MAPPED |
.equ UBRRL = 0xc4 ; MEMORY MAPPED |
.equ UCSRC = 0xc2 ; MEMORY MAPPED |
.equ UCSRB = 0xc1 ; MEMORY MAPPED |
.equ UCSRA = 0xc0 ; MEMORY MAPPED |
.equ USIDR = 0xba ; MEMORY MAPPED |
.equ USISR = 0xb9 ; MEMORY MAPPED |
.equ USICR = 0xb8 ; MEMORY MAPPED |
.equ ASSR = 0xb6 ; MEMORY MAPPED |
.equ OCR2A = 0xb3 ; MEMORY MAPPED |
.equ TCNT2 = 0xb2 ; MEMORY MAPPED |
.equ TCCR2B = 0xb1 ; MEMORY MAPPED |
.equ TCCR2A = 0xb0 ; MEMORY MAPPED |
.equ OCR1BH = 0x8b ; MEMORY MAPPED |
.equ OCR1BL = 0x8a ; MEMORY MAPPED |
.equ OCR1AH = 0x89 ; MEMORY MAPPED |
.equ OCR1AL = 0x88 ; MEMORY MAPPED |
.equ ICR1H = 0x87 ; MEMORY MAPPED |
.equ ICR1L = 0x86 ; MEMORY MAPPED |
.equ TCNT1H = 0x85 ; MEMORY MAPPED |
.equ TCNT1L = 0x84 ; MEMORY MAPPED |
.equ TCCR1C = 0x82 ; MEMORY MAPPED |
.equ TCCR1B = 0x81 ; MEMORY MAPPED |
.equ TCCR1A = 0x80 ; MEMORY MAPPED |
.equ DIDR1 = 0x7f ; MEMORY MAPPED |
.equ DIDR0 = 0x7e ; MEMORY MAPPED |
.equ ADMUX = 0x7c ; MEMORY MAPPED |
.equ ADCSRB = 0x7b ; MEMORY MAPPED |
.equ ADCSRA = 0x7a ; MEMORY MAPPED |
.equ ADCH = 0x79 ; MEMORY MAPPED |
.equ ADCL = 0x78 ; MEMORY MAPPED |
.equ TIMSK2 = 0x70 ; MEMORY MAPPED |
.equ TIMSK1 = 0x6f ; MEMORY MAPPED |
.equ TIMSK0 = 0x6e ; MEMORY MAPPED |
.equ PCMSK1 = 0x6c ; MEMORY MAPPED |
.equ PCMSK0 = 0x6b ; MEMORY MAPPED |
.equ EICRA = 0x69 ; MEMORY MAPPED |
.equ OSCCAL = 0x66 ; MEMORY MAPPED |
.equ PRR = 0x64 ; MEMORY MAPPED |
.equ CLKPR = 0x61 ; MEMORY MAPPED |
.equ WDTCR = 0x60 ; MEMORY MAPPED |
.equ SREG = 0x3f |
.equ SPH = 0x3e |
.equ SPL = 0x3d |
.equ SPMCSR = 0x37 |
.equ MCUCR = 0x35 |
.equ MCUSR = 0x34 |
.equ SMCR = 0x33 |
.equ OCDR = 0x31 |
.equ ACSR = 0x30 |
.equ SPDR = 0x2e |
.equ SPSR = 0x2d |
.equ SPCR = 0x2c |
.equ GPIOR2 = 0x2b |
.equ GPIOR1 = 0x2a |
.equ OCR0A = 0x27 |
.equ TCNT0 = 0x26 |
.equ TCCR0A = 0x24 |
.equ GTCCR = 0x23 |
.equ EEARH = 0x22 |
.equ EEARL = 0x21 |
.equ EEDR = 0x20 |
.equ EECR = 0x1f |
.equ GPIOR0 = 0x1e |
.equ EIMSK = 0x1d |
.equ EIFR = 0x1c |
.equ TIFR2 = 0x17 |
.equ TIFR1 = 0x16 |
.equ TIFR0 = 0x15 |
.equ PORTG = 0x14 |
.equ DDRG = 0x13 |
.equ PING = 0x12 |
.equ PORTF = 0x11 |
.equ DDRF = 0x10 |
.equ PINF = 0x0f |
.equ PORTE = 0x0e |
.equ DDRE = 0x0d |
.equ PINE = 0x0c |
.equ PORTD = 0x0b |
.equ DDRD = 0x0a |
.equ PIND = 0x09 |
.equ PORTC = 0x08 |
.equ DDRC = 0x07 |
.equ PINC = 0x06 |
.equ PORTB = 0x05 |
.equ DDRB = 0x04 |
.equ PINB = 0x03 |
.equ PORTA = 0x02 |
.equ DDRA = 0x01 |
.equ PINA = 0x00 |
; ***** BIT DEFINITIONS ************************************************** |
; ***** TIMER_COUNTER_0 ************** |
; TCCR0A - Timer/Counter0 Control Register |
.equ CS00 = 0 ; Clock Select 1 |
.equ CS01 = 1 ; Clock Select 1 |
.equ CS02 = 2 ; Clock Select 2 |
.equ WGM01 = 3 ; Waveform Generation Mode 1 |
.equ COM0A0 = 4 ; Compare match Output Mode 0 |
.equ COM0A1 = 5 ; Compare Match Output Mode 1 |
.equ WGM00 = 6 ; Waveform Generation Mode 0 |
.equ FOC0A = 7 ; Force Output Compare |
; TCNT0 - Timer/Counter0 |
.equ TCNT0_0 = 0 ; |
.equ TCNT0_1 = 1 ; |
.equ TCNT0_2 = 2 ; |
.equ TCNT0_3 = 3 ; |
.equ TCNT0_4 = 4 ; |
.equ TCNT0_5 = 5 ; |
.equ TCNT0_6 = 6 ; |
.equ TCNT0_7 = 7 ; |
; OCR0A - Timer/Counter0 Output Compare Register |
.equ OCR0A0 = 0 ; |
.equ OCR0A1 = 1 ; |
.equ OCR0A2 = 2 ; |
.equ OCR0A3 = 3 ; |
.equ OCR0A4 = 4 ; |
.equ OCR0A5 = 5 ; |
.equ OCR0A6 = 6 ; |
.equ OCR0A7 = 7 ; |
; TIMSK0 - Timer/Counter0 Interrupt Mask Register |
.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable |
.equ OCIE0A = 1 ; Timer/Counter0 Output Compare Match Interrupt Enable |
; TIFR0 - Timer/Counter0 Interrupt Flag register |
.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag |
.equ OCF0A = 1 ; Timer/Counter0 Output Compare Flag 0 |
; GTCCR - General Timer/Control Register |
.equ PSR310 = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0 |
.equ PSR10 = PSR310 ; For compatibility |
.equ PSR0 = PSR310 ; For compatibility |
.equ PSR1 = PSR310 ; For compatibility |
.equ PSR3 = PSR310 ; For compatibility |
.equ TSM = 7 ; Timer/Counter Synchronization Mode |
; ***** TIMER_COUNTER_1 ************** |
; TIMSK1 - Timer/Counter1 Interrupt Mask Register |
.equ TOIE1 = 0 ; Timer/Counter1 Overflow Interrupt Enable |
.equ OCIE1A = 1 ; Timer/Counter1 Output Compare A Match Interrupt Enable |
.equ OCIE1B = 2 ; Timer/Counter1 Output Compare B Match Interrupt Enable |
.equ ICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable |
; TIFR1 - Timer/Counter1 Interrupt Flag register |
.equ TOV1 = 0 ; Timer/Counter1 Overflow Flag |
.equ OCF1A = 1 ; Output Compare Flag 1A |
.equ OCF1B = 2 ; Output Compare Flag 1B |
.equ ICF1 = 5 ; Input Capture Flag 1 |
; TCCR1A - Timer/Counter1 Control Register A |
.equ WGM10 = 0 ; Waveform Generation Mode |
.equ WGM11 = 1 ; Waveform Generation Mode |
.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0 |
.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1 |
.equ COM1A0 = 6 ; Compare Output Mode 1A, bit 0 |
.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1 |
; TCCR1B - Timer/Counter1 Control Register B |
.equ CS10 = 0 ; Prescaler source of Timer/Counter 1 |
.equ CS11 = 1 ; Prescaler source of Timer/Counter 1 |
.equ CS12 = 2 ; Prescaler source of Timer/Counter 1 |
.equ WGM12 = 3 ; Waveform Generation Mode |
.equ WGM13 = 4 ; Waveform Generation Mode |
.equ ICES1 = 6 ; Input Capture 1 Edge Select |
.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler |
; TCCR1C - Timer/Counter 1 Control Register C |
.equ FOC1B = 6 ; Force Output Compare 1B |
.equ FOC1A = 7 ; Force Output Compare 1A |
; ***** TIMER_COUNTER_2 ************** |
; TIMSK2 - Timer/Counter2 Interrupt Mask register |
.equ TOIE2 = 0 ; Timer/Counter2 Overflow Interrupt Enable |
.equ OCIE2A = 1 ; Timer/Counter2 Output Compare Match Interrupt Enable |
; TIFR2 - Timer/Counter2 Interrupt Flag Register |
.equ TOV2 = 0 ; Timer/Counter2 Overflow Flag |
.equ OCF2A = 1 ; Timer/Counter2 Output Compare Flag 2 |
; TCCR2A - Timer/Counter2 Control Register |
.equ CS20 = 0 ; Clock Select bit 0 |
.equ CS21 = 1 ; Clock Select bit 1 |
.equ CS22 = 2 ; Clock Select bit 2 |
.equ WGM21 = 3 ; Waveform Generation Mode |
.equ COM2A0 = 4 ; Compare Output Mode bit 0 |
.equ COM2A1 = 5 ; Compare Output Mode bit 1 |
.equ WGM20 = 6 ; Waveform Generation Mode |
.equ FOC2A = 7 ; Force Output Compare A |
; TCNT2 - Timer/Counter2 |
.equ TCNT2_0 = 0 ; Timer/Counter 2 bit 0 |
.equ TCNT2_1 = 1 ; Timer/Counter 2 bit 1 |
.equ TCNT2_2 = 2 ; Timer/Counter 2 bit 2 |
.equ TCNT2_3 = 3 ; Timer/Counter 2 bit 3 |
.equ TCNT2_4 = 4 ; Timer/Counter 2 bit 4 |
.equ TCNT2_5 = 5 ; Timer/Counter 2 bit 5 |
.equ TCNT2_6 = 6 ; Timer/Counter 2 bit 6 |
.equ TCNT2_7 = 7 ; Timer/Counter 2 bit 7 |
; OCR2A - Timer/Counter2 Output Compare Register |
.equ OCR2A0 = 0 ; Timer/Counter2 Output Compare Register Bit 0 |
.equ OCR2A1 = 1 ; Timer/Counter2 Output Compare Register Bit 1 |
.equ OCR2A2 = 2 ; Timer/Counter2 Output Compare Register Bit 2 |
.equ OCR2A3 = 3 ; Timer/Counter2 Output Compare Register Bit 3 |
.equ OCR2A4 = 4 ; Timer/Counter2 Output Compare Register Bit 4 |
.equ OCR2A5 = 5 ; Timer/Counter2 Output Compare Register Bit 5 |
.equ OCR2A6 = 6 ; Timer/Counter2 Output Compare Register Bit 6 |
.equ OCR2A7 = 7 ; Timer/Counter2 Output Compare Register Bit 7 |
; GTCCR - General Timer/Counter Control Register |
.equ PSR2 = 1 ; Prescaler Reset Timer/Counter2 |
; ASSR - Asynchronous Status Register |
.equ TCR2UB = 0 ; TCR2UB: Timer/Counter Control Register2 Update Busy |
.equ OCR2UB = 1 ; Output Compare Register2 Update Busy |
.equ TCN2UB = 2 ; TCN2UB: Timer/Counter2 Update Busy |
.equ AS2 = 3 ; AS2: Asynchronous Timer/Counter2 |
.equ EXCLK = 4 ; Enable External Clock Interrupt |
; ***** WATCHDOG ********************* |
; WDTCR - Watchdog Timer Control Register |
.equ WDTCSR = WDTCR ; For compatibility |
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 |
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 |
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 |
.equ WDE = 3 ; Watch Dog Enable |
.equ WDCE = 4 ; Watchdog Change Enable |
.equ WDTOE = WDCE ; For compatibility |
; ***** EEPROM *********************** |
; EEDR - EEPROM Data Register |
.equ EEDR0 = 0 ; EEPROM Data Register bit 0 |
.equ EEDR1 = 1 ; EEPROM Data Register bit 1 |
.equ EEDR2 = 2 ; EEPROM Data Register bit 2 |
.equ EEDR3 = 3 ; EEPROM Data Register bit 3 |
.equ EEDR4 = 4 ; EEPROM Data Register bit 4 |
.equ EEDR5 = 5 ; EEPROM Data Register bit 5 |
.equ EEDR6 = 6 ; EEPROM Data Register bit 6 |
.equ EEDR7 = 7 ; EEPROM Data Register bit 7 |
; EECR - EEPROM Control Register |
.equ EERE = 0 ; EEPROM Read Enable |
.equ EEWE = 1 ; EEPROM Write Enable |
.equ EEMWE = 2 ; EEPROM Master Write Enable |
.equ EEWEE = EEMWE ; For compatibility |
.equ EERIE = 3 ; EEPROM Ready Interrupt Enable |
; ***** SPI ************************** |
; SPDR - SPI Data Register |
.equ SPDR0 = 0 ; SPI Data Register bit 0 |
.equ SPDR1 = 1 ; SPI Data Register bit 1 |
.equ SPDR2 = 2 ; SPI Data Register bit 2 |
.equ SPDR3 = 3 ; SPI Data Register bit 3 |
.equ SPDR4 = 4 ; SPI Data Register bit 4 |
.equ SPDR5 = 5 ; SPI Data Register bit 5 |
.equ SPDR6 = 6 ; SPI Data Register bit 6 |
.equ SPDR7 = 7 ; SPI Data Register bit 7 |
; SPSR - SPI Status Register |
.equ SPI2X = 0 ; Double SPI Speed Bit |
.equ WCOL = 6 ; Write Collision Flag |
.equ SPIF = 7 ; SPI Interrupt Flag |
; SPCR - SPI Control Register |
.equ SPR0 = 0 ; SPI Clock Rate Select 0 |
.equ SPR1 = 1 ; SPI Clock Rate Select 1 |
.equ CPHA = 2 ; Clock Phase |
.equ CPOL = 3 ; Clock polarity |
.equ MSTR = 4 ; Master/Slave Select |
.equ DORD = 5 ; Data Order |
.equ SPE = 6 ; SPI Enable |
.equ SPIE = 7 ; SPI Interrupt Enable |
; ***** PORTA ************************ |
; PORTA - Port A Data Register |
.equ PORTA0 = 0 ; Port A Data Register bit 0 |
.equ PA0 = 0 ; For compatibility |
.equ PORTA1 = 1 ; Port A Data Register bit 1 |
.equ PA1 = 1 ; For compatibility |
.equ PORTA2 = 2 ; Port A Data Register bit 2 |
.equ PA2 = 2 ; For compatibility |
.equ PORTA3 = 3 ; Port A Data Register bit 3 |
.equ PA3 = 3 ; For compatibility |
.equ PORTA4 = 4 ; Port A Data Register bit 4 |
.equ PA4 = 4 ; For compatibility |
.equ PORTA5 = 5 ; Port A Data Register bit 5 |
.equ PA5 = 5 ; For compatibility |
.equ PORTA6 = 6 ; Port A Data Register bit 6 |
.equ PA6 = 6 ; For compatibility |
.equ PORTA7 = 7 ; Port A Data Register bit 7 |
.equ PA7 = 7 ; For compatibility |
; DDRA - Port A Data Direction Register |
.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0 |
.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1 |
.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2 |
.equ DDA3 = 3 ; Data Direction Register, Port A, bit 3 |
.equ DDA4 = 4 ; Data Direction Register, Port A, bit 4 |
.equ DDA5 = 5 ; Data Direction Register, Port A, bit 5 |
.equ DDA6 = 6 ; Data Direction Register, Port A, bit 6 |
.equ DDA7 = 7 ; Data Direction Register, Port A, bit 7 |
; PINA - Port A Input Pins |
.equ PINA0 = 0 ; Input Pins, Port A bit 0 |
.equ PINA1 = 1 ; Input Pins, Port A bit 1 |
.equ PINA2 = 2 ; Input Pins, Port A bit 2 |
.equ PINA3 = 3 ; Input Pins, Port A bit 3 |
.equ PINA4 = 4 ; Input Pins, Port A bit 4 |
.equ PINA5 = 5 ; Input Pins, Port A bit 5 |
.equ PINA6 = 6 ; Input Pins, Port A bit 6 |
.equ PINA7 = 7 ; Input Pins, Port A bit 7 |
; ***** PORTB ************************ |
; PORTB - Port B Data Register |
.equ PORTB0 = 0 ; Port B Data Register bit 0 |
.equ PB0 = 0 ; For compatibility |
.equ PORTB1 = 1 ; Port B Data Register bit 1 |
.equ PB1 = 1 ; For compatibility |
.equ PORTB2 = 2 ; Port B Data Register bit 2 |
.equ PB2 = 2 ; For compatibility |
.equ PORTB3 = 3 ; Port B Data Register bit 3 |
.equ PB3 = 3 ; For compatibility |
.equ PORTB4 = 4 ; Port B Data Register bit 4 |
.equ PB4 = 4 ; For compatibility |
.equ PORTB5 = 5 ; Port B Data Register bit 5 |
.equ PB5 = 5 ; For compatibility |
.equ PORTB6 = 6 ; Port B Data Register bit 6 |
.equ PB6 = 6 ; For compatibility |
.equ PORTB7 = 7 ; Port B Data Register bit 7 |
.equ PB7 = 7 ; For compatibility |
; DDRB - Port B Data Direction Register |
.equ DDB0 = 0 ; Port B Data Direction Register bit 0 |
.equ DDB1 = 1 ; Port B Data Direction Register bit 1 |
.equ DDB2 = 2 ; Port B Data Direction Register bit 2 |
.equ DDB3 = 3 ; Port B Data Direction Register bit 3 |
.equ DDB4 = 4 ; Port B Data Direction Register bit 4 |
.equ DDB5 = 5 ; Port B Data Direction Register bit 5 |
.equ DDB6 = 6 ; Port B Data Direction Register bit 6 |
.equ DDB7 = 7 ; Port B Data Direction Register bit 7 |
; PINB - Port B Input Pins |
.equ PINB0 = 0 ; Port B Input Pins bit 0 |
.equ PINB1 = 1 ; Port B Input Pins bit 1 |
.equ PINB2 = 2 ; Port B Input Pins bit 2 |
.equ PINB3 = 3 ; Port B Input Pins bit 3 |
.equ PINB4 = 4 ; Port B Input Pins bit 4 |
.equ PINB5 = 5 ; Port B Input Pins bit 5 |
.equ PINB6 = 6 ; Port B Input Pins bit 6 |
.equ PINB7 = 7 ; Port B Input Pins bit 7 |
; ***** PORTC ************************ |
; PORTC - Port C Data Register |
.equ PORTC0 = 0 ; Port C Data Register bit 0 |
.equ PC0 = 0 ; For compatibility |
.equ PORTC1 = 1 ; Port C Data Register bit 1 |
.equ PC1 = 1 ; For compatibility |
.equ PORTC2 = 2 ; Port C Data Register bit 2 |
.equ PC2 = 2 ; For compatibility |
.equ PORTC3 = 3 ; Port C Data Register bit 3 |
.equ PC3 = 3 ; For compatibility |
.equ PORTC4 = 4 ; Port C Data Register bit 4 |
.equ PC4 = 4 ; For compatibility |
.equ PORTC5 = 5 ; Port C Data Register bit 5 |
.equ PC5 = 5 ; For compatibility |
.equ PORTC6 = 6 ; Port C Data Register bit 6 |
.equ PC6 = 6 ; For compatibility |
.equ PORTC7 = 7 ; Port C Data Register bit 7 |
.equ PC7 = 7 ; For compatibility |
; DDRC - Port C Data Direction Register |
.equ DDC0 = 0 ; Port C Data Direction Register bit 0 |
.equ DDC1 = 1 ; Port C Data Direction Register bit 1 |
.equ DDC2 = 2 ; Port C Data Direction Register bit 2 |
.equ DDC3 = 3 ; Port C Data Direction Register bit 3 |
.equ DDC4 = 4 ; Port C Data Direction Register bit 4 |
.equ DDC5 = 5 ; Port C Data Direction Register bit 5 |
.equ DDC6 = 6 ; Port C Data Direction Register bit 6 |
.equ DDC7 = 7 ; Port C Data Direction Register bit 7 |
; PINC - Port C Input Pins |
.equ PINC0 = 0 ; Port C Input Pins bit 0 |
.equ PINC1 = 1 ; Port C Input Pins bit 1 |
.equ PINC2 = 2 ; Port C Input Pins bit 2 |
.equ PINC3 = 3 ; Port C Input Pins bit 3 |
.equ PINC4 = 4 ; Port C Input Pins bit 4 |
.equ PINC5 = 5 ; Port C Input Pins bit 5 |
.equ PINC6 = 6 ; Port C Input Pins bit 6 |
.equ PINC7 = 7 ; Port C Input Pins bit 7 |
; ***** PORTD ************************ |
; PORTD - Port D Data Register |
.equ PORTD0 = 0 ; Port D Data Register bit 0 |
.equ PD0 = 0 ; For compatibility |
.equ PORTD1 = 1 ; Port D Data Register bit 1 |
.equ PD1 = 1 ; For compatibility |
.equ PORTD2 = 2 ; Port D Data Register bit 2 |
.equ PD2 = 2 ; For compatibility |
.equ PORTD3 = 3 ; Port D Data Register bit 3 |
.equ PD3 = 3 ; For compatibility |
.equ PORTD4 = 4 ; Port D Data Register bit 4 |
.equ PD4 = 4 ; For compatibility |
.equ PORTD5 = 5 ; Port D Data Register bit 5 |
.equ PD5 = 5 ; For compatibility |
.equ PORTD6 = 6 ; Port D Data Register bit 6 |
.equ PD6 = 6 ; For compatibility |
.equ PORTD7 = 7 ; Port D Data Register bit 7 |
.equ PD7 = 7 ; For compatibility |
; DDRD - Port D Data Direction Register |
.equ DDD0 = 0 ; Port D Data Direction Register bit 0 |
.equ DDD1 = 1 ; Port D Data Direction Register bit 1 |
.equ DDD2 = 2 ; Port D Data Direction Register bit 2 |
.equ DDD3 = 3 ; Port D Data Direction Register bit 3 |
.equ DDD4 = 4 ; Port D Data Direction Register bit 4 |
.equ DDD5 = 5 ; Port D Data Direction Register bit 5 |
.equ DDD6 = 6 ; Port D Data Direction Register bit 6 |
.equ DDD7 = 7 ; Port D Data Direction Register bit 7 |
; PIND - Port D Input Pins |
.equ PIND0 = 0 ; Port D Input Pins bit 0 |
.equ PIND1 = 1 ; Port D Input Pins bit 1 |
.equ PIND2 = 2 ; Port D Input Pins bit 2 |
.equ PIND3 = 3 ; Port D Input Pins bit 3 |
.equ PIND4 = 4 ; Port D Input Pins bit 4 |
.equ PIND5 = 5 ; Port D Input Pins bit 5 |
.equ PIND6 = 6 ; Port D Input Pins bit 6 |
.equ PIND7 = 7 ; Port D Input Pins bit 7 |
; ***** ANALOG_COMPARATOR ************ |
; ADCSRB - ADC Control and Status Register B |
.equ ACME = 6 ; Analog Comparator Multiplexer Enable |
; ACSR - Analog Comparator Control And Status Register |
.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 |
.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 |
.equ ACIC = 2 ; Analog Comparator Input Capture Enable |
.equ ACIE = 3 ; Analog Comparator Interrupt Enable |
.equ ACI = 4 ; Analog Comparator Interrupt Flag |
.equ ACO = 5 ; Analog Compare Output |
.equ ACBG = 6 ; Analog Comparator Bandgap Select |
.equ ACD = 7 ; Analog Comparator Disable |
; DIDR1 - Digital Input Disable Register 1 |
.equ AIN0D = 0 ; AIN0 Digital Input Disable |
.equ AIN1D = 1 ; AIN1 Digital Input Disable |
; ***** PORTE ************************ |
; PORTE - Data Register, Port E |
.equ PORTE0 = 0 ; |
.equ PE0 = 0 ; For compatibility |
.equ PORTE1 = 1 ; |
.equ PE1 = 1 ; For compatibility |
.equ PORTE2 = 2 ; |
.equ PE2 = 2 ; For compatibility |
.equ PORTE3 = 3 ; |
.equ PE3 = 3 ; For compatibility |
.equ PORTE4 = 4 ; |
.equ PE4 = 4 ; For compatibility |
.equ PORTE5 = 5 ; |
.equ PE5 = 5 ; For compatibility |
.equ PORTE6 = 6 ; |
.equ PE6 = 6 ; For compatibility |
.equ PORTE7 = 7 ; |
.equ PE7 = 7 ; For compatibility |
; DDRE - Data Direction Register, Port E |
.equ DDE0 = 0 ; |
.equ DDE1 = 1 ; |
.equ DDE2 = 2 ; |
.equ DDE3 = 3 ; |
.equ DDE4 = 4 ; |
.equ DDE5 = 5 ; |
.equ DDE6 = 6 ; |
.equ DDE7 = 7 ; |
; PINE - Input Pins, Port E |
.equ PINE0 = 0 ; |
.equ PINE1 = 1 ; |
.equ PINE2 = 2 ; |
.equ PINE3 = 3 ; |
.equ PINE4 = 4 ; |
.equ PINE5 = 5 ; |
.equ PINE6 = 6 ; |
.equ PINE7 = 7 ; |
; ***** PORTF ************************ |
; PORTF - Data Register, Port F |
.equ PORTF0 = 0 ; |
.equ PF0 = 0 ; For compatibility |
.equ PORTF1 = 1 ; |
.equ PF1 = 1 ; For compatibility |
.equ PORTF2 = 2 ; |
.equ PF2 = 2 ; For compatibility |
.equ PORTF3 = 3 ; |
.equ PF3 = 3 ; For compatibility |
.equ PORTF4 = 4 ; |
.equ PF4 = 4 ; For compatibility |
.equ PORTF5 = 5 ; |
.equ PF5 = 5 ; For compatibility |
.equ PORTF6 = 6 ; |
.equ PF6 = 6 ; For compatibility |
.equ PORTF7 = 7 ; |
.equ PF7 = 7 ; For compatibility |
; DDRF - Data Direction Register, Port F |
.equ DDF0 = 0 ; |
.equ DDF1 = 1 ; |
.equ DDF2 = 2 ; |
.equ DDF3 = 3 ; |
.equ DDF4 = 4 ; |
.equ DDF5 = 5 ; |
.equ DDF6 = 6 ; |
.equ DDF7 = 7 ; |
; PINF - Input Pins, Port F |
.equ PINF0 = 0 ; |
.equ PINF1 = 1 ; |
.equ PINF2 = 2 ; |
.equ PINF3 = 3 ; |
.equ PINF4 = 4 ; |
.equ PINF5 = 5 ; |
.equ PINF6 = 6 ; |
.equ PINF7 = 7 ; |
; ***** PORTG ************************ |
; PORTG - Port G Data Register |
.equ PORTG0 = 0 ; |
.equ PG0 = 0 ; For compatibility |
.equ PORTG1 = 1 ; |
.equ PG1 = 1 ; For compatibility |
.equ PORTG2 = 2 ; |
.equ PG2 = 2 ; For compatibility |
.equ PORTG3 = 3 ; |
.equ PG3 = 3 ; For compatibility |
.equ PORTG4 = 4 ; |
.equ PG4 = 4 ; For compatibility |
; DDRG - Port G Data Direction Register |
.equ DDG0 = 0 ; |
.equ DDG1 = 1 ; |
.equ DDG2 = 2 ; |
.equ DDG3 = 3 ; |
.equ DDG4 = 4 ; |
; PING - Port G Input Pins |
.equ PING0 = 0 ; |
.equ PING1 = 1 ; |
.equ PING2 = 2 ; |
.equ PING3 = 3 ; |
.equ PING4 = 4 ; |
.equ PING5 = 5 ; |
; ***** JTAG ************************* |
; OCDR - On-Chip Debug Related Register in I/O Memory |
.equ OCDR0 = 0 ; On-Chip Debug Register Bit 0 |
.equ OCDR1 = 1 ; On-Chip Debug Register Bit 1 |
.equ OCDR2 = 2 ; On-Chip Debug Register Bit 2 |
.equ OCDR3 = 3 ; On-Chip Debug Register Bit 3 |
.equ OCDR4 = 4 ; On-Chip Debug Register Bit 4 |
.equ OCDR5 = 5 ; On-Chip Debug Register Bit 5 |
.equ OCDR6 = 6 ; On-Chip Debug Register Bit 6 |
.equ OCDR7 = 7 ; On-Chip Debug Register Bit 7 |
.equ IDRD = OCDR7 ; For compatibility |
; MCUCR - MCU Control Register |
.equ JTD = 7 ; JTAG Interface Disable |
; MCUSR - MCU Status Register |
.equ JTRF = 4 ; JTAG Reset Flag |
; ***** EXTERNAL_INTERRUPT *********** |
; EICRA - External Interrupt Control Register |
.equ ISC00 = 0 ; External Interrupt Sense Control 0 Bit 0 |
.equ ISC01 = 1 ; External Interrupt Sense Control 0 Bit 1 |
; EIMSK - External Interrupt Mask Register |
.equ INT0 = 0 ; External Interrupt Request 0 Enable |
.equ PCIE0 = 6 ; Pin Change Interrupt Enable 0 |
.equ PCIE1 = 7 ; Pin Change Interrupt Enable 1 |
; EIFR - External Interrupt Flag Register |
.equ INTF0 = 0 ; External Interrupt Flag 0 |
.equ PCIF0 = 6 ; Pin Change Interrupt Flag 0 |
.equ PCIF1 = 7 ; Pin Change Interrupt Flag 1 |
; PCMSK1 - Pin Change Mask Register 1 |
.equ PCINT8 = 0 ; Pin Change Enable Mask 8 |
.equ PCINT9 = 1 ; Pin Change Enable Mask 9 |
.equ PCINT10 = 2 ; Pin Change Enable Mask 10 |
.equ PCINT11 = 3 ; Pin Change Enable Mask 11 |
.equ PCINT12 = 4 ; Pin Change Enable Mask 12 |
.equ PCINT13 = 5 ; Pin Change Enable Mask 13 |
.equ PCINT14 = 6 ; Pin Change Enable Mask 14 |
.equ PCINT15 = 7 ; Pin Change Enable Mask 15 |
; PCMSK0 - Pin Change Mask Register 0 |
.equ PCINT0 = 0 ; Pin Change Enable Mask 0 |
.equ PCINT1 = 1 ; Pin Change Enable Mask 1 |
.equ PCINT2 = 2 ; Pin Change Enable Mask 2 |
.equ PCINT3 = 3 ; Pin Change Enable Mask 3 |
.equ PCINT4 = 4 ; Pin Change Enable Mask 4 |
.equ PCINT5 = 5 ; Pin Change Enable Mask 5 |
.equ PCINT6 = 6 ; Pin Change Enable Mask 6 |
.equ PCINT7 = 7 ; Pin Change Enable Mask 7 |
; ***** USI ************************** |
; USIDR - USI Data Register |
.equ USIDR0 = 0 ; USI Data Register bit 0 |
.equ USIDR1 = 1 ; USI Data Register bit 1 |
.equ USIDR2 = 2 ; USI Data Register bit 2 |
.equ USIDR3 = 3 ; USI Data Register bit 3 |
.equ USIDR4 = 4 ; USI Data Register bit 4 |
.equ USIDR5 = 5 ; USI Data Register bit 5 |
.equ USIDR6 = 6 ; USI Data Register bit 6 |
.equ USIDR7 = 7 ; USI Data Register bit 7 |
; USISR - USI Status Register |
.equ USICNT0 = 0 ; USI Counter Value Bit 0 |
.equ USICNT1 = 1 ; USI Counter Value Bit 1 |
.equ USICNT2 = 2 ; USI Counter Value Bit 2 |
.equ USICNT3 = 3 ; USI Counter Value Bit 3 |
.equ USIDC = 4 ; Data Output Collision |
.equ USIPF = 5 ; Stop Condition Flag |
.equ USIOIF = 6 ; Counter Overflow Interrupt Flag |
.equ USISIF = 7 ; Start Condition Interrupt Flag |
; USICR - USI Control Register |
.equ USITC = 0 ; Toggle Clock Port Pin |
.equ USICLK = 1 ; Clock Strobe |
.equ USICS0 = 2 ; USI Clock Source Select Bit 0 |
.equ USICS1 = 3 ; USI Clock Source Select Bit 1 |
.equ USIWM0 = 4 ; USI Wire Mode Bit 0 |
.equ USIWM1 = 5 ; USI Wire Mode Bit 1 |
.equ USIOIE = 6 ; Counter Overflow Interrupt Enable |
.equ USISIE = 7 ; Start Condition Interrupt Enable |
; ***** AD_CONVERTER ***************** |
; ADMUX - The ADC multiplexer Selection Register |
.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits |
.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits |
.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits |
.equ MUX3 = 3 ; Analog Channel and Gain Selection Bits |
.equ MUX4 = 4 ; Analog Channel and Gain Selection Bits |
.equ ADLAR = 5 ; Left Adjust Result |
.equ REFS0 = 6 ; Reference Selection Bit 0 |
.equ REFS1 = 7 ; Reference Selection Bit 1 |
; ADCSRA - The ADC Control and Status register |
.equ ADPS0 = 0 ; ADC Prescaler Select Bits |
.equ ADPS1 = 1 ; ADC Prescaler Select Bits |
.equ ADPS2 = 2 ; ADC Prescaler Select Bits |
.equ ADIE = 3 ; ADC Interrupt Enable |
.equ ADIF = 4 ; ADC Interrupt Flag |
.equ ADATE = 5 ; ADC Auto Trigger Enable |
.equ ADSC = 6 ; ADC Start Conversion |
.equ ADEN = 7 ; ADC Enable |
; ADCH - ADC Data Register High Byte |
.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0 |
.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1 |
.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2 |
.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3 |
.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4 |
.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5 |
.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6 |
.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7 |
; ADCL - ADC Data Register Low Byte |
.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0 |
.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1 |
.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2 |
.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3 |
.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4 |
.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5 |
.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6 |
.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7 |
; ADCSRB - ADC Control and Status Register B |
.equ ADTS0 = 0 ; ADC Auto Trigger Source 0 |
.equ ADTS1 = 1 ; ADC Auto Trigger Source 1 |
.equ ADTS2 = 2 ; ADC Auto Trigger Source 2 |
; DIDR0 - Digital Input Disable Register 0 |
.equ ADC0D = 0 ; ADC0 Digital input Disable |
.equ ADC1D = 1 ; ADC1 Digital input Disable |
.equ ADC2D = 2 ; ADC2 Digital input Disable |
.equ ADC3D = 3 ; ADC3 Digital input Disable |
.equ ADC4D = 4 ; ADC4 Digital input Disable |
.equ ADC5D = 5 ; ADC5 Digital input Disable |
.equ ADC6D = 6 ; ADC6 Digital input Disable |
.equ ADC7D = 7 ; ADC7 Digital input Disable |
; ***** BOOT_LOAD ******************** |
; SPMCSR - Store Program Memory Control Register |
.equ SPMCR = SPMCSR ; For compatibility |
.equ SPMEN = 0 ; Store Program Memory Enable |
.equ PGERS = 1 ; Page Erase |
.equ PGWRT = 2 ; Page Write |
.equ BLBSET = 3 ; Boot Lock Bit Set |
.equ RWWSRE = 4 ; Read While Write section read enable |
.equ ASRE = RWWSRE ; For compatibility |
.equ RWWSB = 6 ; Read While Write Section Busy |
.equ ASB = RWWSB ; For compatibility |
.equ SPMIE = 7 ; SPM Interrupt Enable |
; ***** USART0 *********************** |
; UDR - USART I/O Data Register |
.equ UDR0 = UDR ; For compatibility |
.equ UDR00 = 0 ; USART I/O Data Register bit 0 |
.equ UDR01 = 1 ; USART I/O Data Register bit 1 |
.equ UDR02 = 2 ; USART I/O Data Register bit 2 |
.equ UDR03 = 3 ; USART I/O Data Register bit 3 |
.equ UDR04 = 4 ; USART I/O Data Register bit 4 |
.equ UDR05 = 5 ; USART I/O Data Register bit 5 |
.equ UDR06 = 6 ; USART I/O Data Register bit 6 |
.equ UDR07 = 7 ; USART I/O Data Register bit 7 |
; UCSRA - USART Control and Status Register A |
.equ UCSR0A = UCSRA ; For compatibility |
.equ USR = UCSRA ; For compatibility |
.equ MPCM = 0 ; Multi-processor Communication Mode |
.equ MPCM0 = MPCM ; For compatibility |
.equ U2X = 1 ; Double the USART Transmission Speed |
.equ U2X0 = U2X ; For compatibility |
.equ UPE = 2 ; USART Parity Error |
.equ UPE0 = UPE ; For compatibility |
.equ DOR = 3 ; Data OverRun |
.equ DOR0 = DOR ; For compatibility |
.equ FE = 4 ; Framing Error |
.equ FE0 = FE ; For compatibility |
.equ UDRE = 5 ; USART Data Register Empty |
.equ UDRE0 = UDRE ; For compatibility |
.equ TXC = 6 ; USART Transmit Complete |
.equ TXC0 = TXC ; For compatibility |
.equ RXC = 7 ; USART Receive Complete |
.equ RXC0 = RXC ; For compatibility |
; UCSRB - USART Control and Status Register B |
.equ UCSR0B = UCSRB ; For compatibility |
.equ UCR = UCSRB ; For compatibility |
.equ TXB8 = 0 ; Transmit Data Bit 8 |
.equ TXB80 = TXB8 ; For compatibility |
.equ RXB8 = 1 ; Receive Data Bit 8 |
.equ RXB80 = RXB8 ; For compatibility |
.equ UCSZ2 = 2 ; Character Size |
.equ UCSZ02 = UCSZ2 ; For compatibility |
.equ TXEN = 3 ; Transmitter Enable |
.equ TXEN0 = TXEN ; For compatibility |
.equ RXEN = 4 ; Receiver Enable |
.equ RXEN0 = RXEN ; For compatibility |
.equ UDRIE = 5 ; USART Data Register Empty Interrupt Enable |
.equ UDRIE0 = UDRIE ; For compatibility |
.equ TXCIE = 6 ; TX Complete Interrupt Enable |
.equ TXCIE0 = TXCIE ; For compatibility |
.equ RXCIE = 7 ; RX Complete Interrupt Enable |
.equ RXCIE0 = RXCIE ; For compatibility |
; UCSRC - USART Control and Status Register C |
.equ UCSR0C = UCSRC ; For compatibility |
.equ UCPOL = 0 ; Clock Polarity |
.equ UCPOL0 = UCPOL ; For compatibility |
.equ UCSZ0 = 1 ; Character Size |
.equ UCSZ00 = UCSZ0 ; For compatibility |
.equ UCSZ1 = 2 ; Character Size |
.equ UCSZ01 = UCSZ1 ; For compatibility |
.equ USBS = 3 ; Stop Bit Select |
.equ USBS0 = USBS ; For compatibility |
.equ UPM0 = 4 ; Parity Mode Bit 0 |
.equ UPM00 = UPM0 ; For compatibility |
.equ UPM1 = 5 ; Parity Mode Bit 1 |
.equ UPM01 = UPM1 ; For compatibility |
.equ UMSEL = 6 ; USART Mode Select |
.equ UMSEL0 = UMSEL ; For compatibility |
.equ UBRR0H = UBRRH ; For compatibility |
.equ UBRR0L = UBRRL ; For compatibility |
.equ UBRR0 = UBRRL ; For compatibility |
.equ UBRR = UBRRL ; For compatibility |
; ***** CPU ************************** |
; SREG - Status Register |
.equ SREG_C = 0 ; Carry Flag |
.equ SREG_Z = 1 ; Zero Flag |
.equ SREG_N = 2 ; Negative Flag |
.equ SREG_V = 3 ; Two's Complement Overflow Flag |
.equ SREG_S = 4 ; Sign Bit |
.equ SREG_H = 5 ; Half Carry Flag |
.equ SREG_T = 6 ; Bit Copy Storage |
.equ SREG_I = 7 ; Global Interrupt Enable |
; MCUCR - MCU Control Register |
.equ IVCE = 0 ; Interrupt Vector Change Enable |
.equ IVSEL = 1 ; Interrupt Vector Select |
.equ PUD = 4 ; Pull-up disable |
; MCUSR - MCU Status Register |
.equ PORF = 0 ; Power-on reset flag |
.equ EXTRF = 1 ; External Reset Flag |
.equ BORF = 2 ; Brown-out Reset Flag |
.equ WDRF = 3 ; Watchdog Reset Flag |
;.equ JTRF = 4 ; JTAG Reset Flag |
; OSCCAL - Oscillator Calibration Value |
.equ CAL0 = 0 ; Oscillator Calibration Value Bit0 |
.equ CAL1 = 1 ; Oscillator Calibration Value Bit1 |
.equ CAL2 = 2 ; Oscillator Calibration Value Bit2 |
.equ CAL3 = 3 ; Oscillator Calibration Value Bit3 |
.equ CAL4 = 4 ; Oscillator Calibration Value Bit4 |
.equ CAL5 = 5 ; Oscillator Calibration Value Bit5 |
.equ CAL6 = 6 ; Oscillator Calibration Value Bit6 |
.equ CAL7 = 7 ; Oscillator Calibration Value Bit7 |
; CLKPR - Clock Prescale Register |
.equ CLKPS0 = 0 ; Clock Prescaler Select Bit 0 |
.equ CLKPS1 = 1 ; Clock Prescaler Select Bit 1 |
.equ CLKPS2 = 2 ; Clock Prescaler Select Bit 2 |
.equ CLKPS3 = 3 ; Clock Prescaler Select Bit 3 |
.equ CLKPCE = 7 ; Clock Prescaler Change Enable |
; PRR - Power Reduction Register |
.equ PRADC = 0 ; Power Reduction ADC |
.equ PRUSART0 = 1 ; Power Reduction USART |
.equ PRSPI = 2 ; Power Reduction Serial Peripheral Interface |
.equ PRTIM1 = 3 ; Power Reduction Timer/Counter1 |
; SMCR - Sleep Mode Control Register |
.equ SE = 0 ; Sleep Enable |
.equ SM0 = 1 ; Sleep Mode Select bit 0 |
.equ SM1 = 2 ; Sleep Mode Select bit 1 |
.equ SM2 = 3 ; Sleep Mode Select bit 2 |
; GPIOR2 - General Purpose IO Register 2 |
.equ GPIOR20 = 0 ; General Purpose IO Register 2 bit 0 |
.equ GPIOR21 = 1 ; General Purpose IO Register 2 bit 1 |
.equ GPIOR22 = 2 ; General Purpose IO Register 2 bit 2 |
.equ GPIOR23 = 3 ; General Purpose IO Register 2 bit 3 |
.equ GPIOR24 = 4 ; General Purpose IO Register 2 bit 4 |
.equ GPIOR25 = 5 ; General Purpose IO Register 2 bit 5 |
.equ GPIOR26 = 6 ; General Purpose IO Register 2 bit 6 |
.equ GPIOR27 = 7 ; General Purpose IO Register 2 bit 7 |
; GPIOR1 - General Purpose IO Register 1 |
.equ GPIOR10 = 0 ; General Purpose IO Register 1 bit 0 |
.equ GPIOR11 = 1 ; General Purpose IO Register 1 bit 1 |
.equ GPIOR12 = 2 ; General Purpose IO Register 1 bit 2 |
.equ GPIOR13 = 3 ; General Purpose IO Register 1 bit 3 |
.equ GPIOR14 = 4 ; General Purpose IO Register 1 bit 4 |
.equ GPIOR15 = 5 ; General Purpose IO Register 1 bit 5 |
.equ GPIOR16 = 6 ; General Purpose IO Register 1 bit 6 |
.equ GPIOR17 = 7 ; General Purpose IO Register 1 bit 7 |
; GPIOR0 - General Purpose IO Register 0 |
.equ GPIOR00 = 0 ; General Purpose IO Register 0 bit 0 |
.equ GPIOR01 = 1 ; General Purpose IO Register 0 bit 1 |
.equ GPIOR02 = 2 ; General Purpose IO Register 0 bit 2 |
.equ GPIOR03 = 3 ; General Purpose IO Register 0 bit 3 |
.equ GPIOR04 = 4 ; General Purpose IO Register 0 bit 4 |
.equ GPIOR05 = 5 ; General Purpose IO Register 0 bit 5 |
.equ GPIOR06 = 6 ; General Purpose IO Register 0 bit 6 |
.equ GPIOR07 = 7 ; General Purpose IO Register 0 bit 7 |
; ***** LOCKSBITS ******************************************************** |
.equ LB1 = 0 ; Lock bit |
.equ LB2 = 1 ; Lock bit |
.equ BLB01 = 2 ; Boot Lock bit |
.equ BLB02 = 3 ; Boot Lock bit |
.equ BLB11 = 4 ; Boot lock bit |
.equ BLB12 = 5 ; Boot lock bit |
; ***** FUSES ************************************************************ |
; LOW fuse bits |
.equ CKSEL0 = 0 ; Select Clock Source |
.equ CKSEL1 = 1 ; Select Clock Source |
.equ CKSEL2 = 2 ; Select Clock Source |
.equ CKSEL3 = 3 ; Select Clock Source |
.equ SUT0 = 4 ; Select start-up time |
.equ SUT1 = 5 ; Select start-up time |
.equ CKOUT = 6 ; Oscillator options |
.equ CLKDIV8 = 7 ; Divide clock by 8 |
; HIGH fuse bits |
.equ BOOTRST = 0 ; Select Reset Vector |
.equ BOOTSZ0 = 1 ; Select Boot Size |
.equ BOOTSZ1 = 2 ; Select Boot Size |
.equ EESAVE = 3 ; EEPROM memory is preserved through chip erase |
.equ WDTON = 4 ; Watchdog timer always on |
.equ SPIEN = 5 ; Enable Serial programming and Data Downloading |
.equ JTAGEN = 6 ; Enable JTAG |
.equ OCDEN = 7 ; Enable OCD |
; EXTENDED fuse bits |
.equ RESERVED = 0 ; Reserved for future use |
.equ BODLEVEL0 = 1 ; Brown-out Detector trigger level |
.equ BODLEVEL1 = 2 ; Brown-out Detector trigger level |
.equ BODLEVEL2 = 3 ; Brown out detector trigger level |
; ***** CPU REGISTER DEFINITIONS ***************************************** |
.def XH = r27 |
.def XL = r26 |
.def YH = r29 |
.def YL = r28 |
.def ZH = r31 |
.def ZL = r30 |
; ***** DATA MEMORY DECLARATIONS ***************************************** |
.equ FLASHEND = 0x1fff ; Note: Word address |
.equ IOEND = 0x00ff |
.equ SRAM_START = 0x0100 |
.equ SRAM_SIZE = 1024 |
.equ RAMEND = 0x04ff |
.equ XRAMEND = 0x0000 |
.equ E2END = 0x01ff |
.equ EEPROMEND = 0x01ff |
.equ EEADRBITS = 9 |
#pragma AVRPART MEMORY PROG_FLASH 16384 |
#pragma AVRPART MEMORY EEPROM 512 |
#pragma AVRPART MEMORY INT_SRAM SIZE 1024 |
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x100 |
; ***** BOOTLOADER DECLARATIONS ****************************************** |
.equ NRWW_START_ADDR = 0x1c00 |
.equ NRWW_STOP_ADDR = 0x1fff |
.equ RWW_START_ADDR = 0x0 |
.equ RWW_STOP_ADDR = 0x1bff |
.equ PAGESIZE = 64 |
.equ FIRSTBOOTSTART = 0x1f80 |
.equ SECONDBOOTSTART = 0x1f00 |
.equ THIRDBOOTSTART = 0x1e00 |
.equ FOURTHBOOTSTART = 0x1c00 |
.equ SMALLBOOTSTART = FIRSTBOOTSTART |
.equ LARGEBOOTSTART = FOURTHBOOTSTART |
; ***** INTERRUPT VECTORS ************************************************ |
.equ INT0addr = 0x0002 ; External Interrupt Request 0 |
.equ PCI0addr = 0x0004 ; Pin Change Interrupt Request 0 |
.equ PCI1addr = 0x0006 ; Pin Change Interrupt Request 1 |
.equ OC2addr = 0x0008 ; Timer/Counter2 Compare Match |
.equ OVF2addr = 0x000a ; Timer/Counter2 Overflow |
.equ ICP1addr = 0x000c ; Timer/Counter1 Capture Event |
.equ OC1Aaddr = 0x000e ; Timer/Counter1 Compare Match A |
.equ OC1Baddr = 0x0010 ; Timer/Counter Compare Match B |
.equ OVF1addr = 0x0012 ; Timer/Counter1 Overflow |
.equ OC0addr = 0x0014 ; Timer/Counter0 Compare Match |
.equ OVF0addr = 0x0016 ; Timer/Counter0 Overflow |
.equ SPIaddr = 0x0018 ; SPI Serial Transfer Complete |
.equ URXC0addr = 0x001a ; USART0, Rx Complete |
.equ URXCaddr = 0x001a ; For compatibility |
.equ UDRE0addr = 0x001c ; USART0 Data register Empty |
.equ UDREaddr = 0x001c ; For compatibility |
.equ UTXC0addr = 0x001e ; USART0, Tx Complete |
.equ UTXCaddr = 0x001e ; For compatibility |
.equ USI_STARTaddr = 0x0020 ; USI Start Condition |
.equ USI_OVFaddr = 0x0022 ; USI Overflow |
.equ ACIaddr = 0x0024 ; Analog Comparator |
.equ ADCCaddr = 0x0026 ; ADC Conversion Complete |
.equ ERDYaddr = 0x0028 ; EEPROM Ready |
.equ SPMRaddr = 0x002a ; Store Program Memory Read |
.equ INT_VECTORS_SIZE = 44 ; size in words |
#endif /* _M165DEF_INC_ */ |
; ***** END OF FILE ****************************************************** |
/contrib/toolchain/avra/includes/m168def.inc |
---|
0,0 → 1,958 |
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** |
;***** Created: 2005-01-11 10:30 ******* Source: ATmega168.xml *********** |
;************************************************************************* |
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y |
;* |
;* Number : AVR000 |
;* File Name : "m168def.inc" |
;* Title : Register/Bit Definitions for the ATmega168 |
;* Date : 2005-01-11 |
;* Version : 2.14 |
;* Support E-mail : avr@atmel.com |
;* Target MCU : ATmega168 |
;* |
;* DESCRIPTION |
;* When including this file in the assembly program file, all I/O register |
;* names and I/O register bit names appearing in the data book can be used. |
;* In addition, the six registers forming the three data pointers X, Y and |
;* Z have been assigned names XL - ZH. Highest RAM address for Internal |
;* SRAM is also defined |
;* |
;* The Register names are represented by their hexadecimal address. |
;* |
;* The Register Bit names are represented by their bit number (0-7). |
;* |
;* Please observe the difference in using the bit names with instructions |
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" |
;* (skip if bit in register set/cleared). The following example illustrates |
;* this: |
;* |
;* in r16,PORTB ;read PORTB latch |
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) |
;* out PORTB,r16 ;output to PORTB |
;* |
;* in r16,TIFR ;read the Timer Interrupt Flag Register |
;* sbrc r16,TOV0 ;test the overflow flag (use bit#) |
;* rjmp TOV0_is_set ;jump if set |
;* ... ;otherwise do something else |
;************************************************************************* |
#ifndef _M168DEF_INC_ |
#define _M168DEF_INC_ |
#pragma partinc 0 |
; ***** SPECIFY DEVICE *************************************************** |
.device ATmega168 |
#pragma AVRPART ADMIN PART_NAME ATmega168 |
.equ SIGNATURE_000 = 0x1e |
.equ SIGNATURE_001 = 0x94 |
.equ SIGNATURE_002 = 0x06 |
#pragma AVRPART CORE CORE_VERSION V2E |
; ***** I/O REGISTER DEFINITIONS ***************************************** |
; NOTE: |
; Definitions marked "MEMORY MAPPED"are extended I/O ports |
; and cannot be used with IN/OUT instructions |
.equ UDR0 = 0xc6 ; MEMORY MAPPED |
.equ UBRR0H = 0xc5 ; MEMORY MAPPED |
.equ UBRR0L = 0xc4 ; MEMORY MAPPED |
.equ UCSR0C = 0xc2 ; MEMORY MAPPED |
.equ UCSR0B = 0xc1 ; MEMORY MAPPED |
.equ UCSR0A = 0xc0 ; MEMORY MAPPED |
.equ TWAMR = 0xbd ; MEMORY MAPPED |
.equ TWCR = 0xbc ; MEMORY MAPPED |
.equ TWDR = 0xbb ; MEMORY MAPPED |
.equ TWAR = 0xba ; MEMORY MAPPED |
.equ TWSR = 0xb9 ; MEMORY MAPPED |
.equ TWBR = 0xb8 ; MEMORY MAPPED |
.equ ASSR = 0xb6 ; MEMORY MAPPED |
.equ OCR2B = 0xb4 ; MEMORY MAPPED |
.equ OCR2A = 0xb3 ; MEMORY MAPPED |
.equ TCNT2 = 0xb2 ; MEMORY MAPPED |
.equ TCCR2B = 0xb1 ; MEMORY MAPPED |
.equ TCCR2A = 0xb0 ; MEMORY MAPPED |
.equ OCR1BH = 0x8b ; MEMORY MAPPED |
.equ OCR1BL = 0x8a ; MEMORY MAPPED |
.equ OCR1AH = 0x89 ; MEMORY MAPPED |
.equ OCR1AL = 0x88 ; MEMORY MAPPED |
.equ ICR1H = 0x87 ; MEMORY MAPPED |
.equ ICR1L = 0x86 ; MEMORY MAPPED |
.equ TCNT1H = 0x85 ; MEMORY MAPPED |
.equ TCNT1L = 0x84 ; MEMORY MAPPED |
.equ TCCR1C = 0x82 ; MEMORY MAPPED |
.equ TCCR1B = 0x81 ; MEMORY MAPPED |
.equ TCCR1A = 0x80 ; MEMORY MAPPED |
.equ DIDR1 = 0x7f ; MEMORY MAPPED |
.equ DIDR0 = 0x7e ; MEMORY MAPPED |
.equ ADMUX = 0x7c ; MEMORY MAPPED |
.equ ADCSRB = 0x7b ; MEMORY MAPPED |
.equ ADCSRA = 0x7a ; MEMORY MAPPED |
.equ ADCH = 0x79 ; MEMORY MAPPED |
.equ ADCL = 0x78 ; MEMORY MAPPED |
.equ TIMSK2 = 0x70 ; MEMORY MAPPED |
.equ TIMSK1 = 0x6f ; MEMORY MAPPED |
.equ TIMSK0 = 0x6e ; MEMORY MAPPED |
.equ PCMSK2 = 0x6d ; MEMORY MAPPED |
.equ PCMSK1 = 0x6c ; MEMORY MAPPED |
.equ PCMSK0 = 0x6b ; MEMORY MAPPED |
.equ EICRA = 0x69 ; MEMORY MAPPED |
.equ PCICR = 0x68 ; MEMORY MAPPED |
.equ OSCCAL = 0x66 ; MEMORY MAPPED |
.equ PRR = 0x64 ; MEMORY MAPPED |
.equ CLKPR = 0x61 ; MEMORY MAPPED |
.equ WDTCSR = 0x60 ; MEMORY MAPPED |
.equ SREG = 0x3f |
.equ SPH = 0x3e |
.equ SPL = 0x3d |
.equ SPMCSR = 0x37 |
.equ MCUCR = 0x35 |
.equ MCUSR = 0x34 |
.equ SMCR = 0x33 |
.equ ACSR = 0x30 |
.equ SPDR = 0x2e |
.equ SPSR = 0x2d |
.equ SPCR = 0x2c |
.equ GPIOR2 = 0x2b |
.equ GPIOR1 = 0x2a |
.equ OCR0B = 0x28 |
.equ OCR0A = 0x27 |
.equ TCNT0 = 0x26 |
.equ TCCR0B = 0x25 |
.equ TCCR0A = 0x24 |
.equ GTCCR = 0x23 |
.equ EEARH = 0x22 |
.equ EEARL = 0x21 |
.equ EEDR = 0x20 |
.equ EECR = 0x1f |
.equ GPIOR0 = 0x1e |
.equ EIMSK = 0x1d |
.equ EIFR = 0x1c |
.equ PCIFR = 0x1b |
.equ TIFR2 = 0x17 |
.equ TIFR1 = 0x16 |
.equ TIFR0 = 0x15 |
.equ PORTD = 0x0b |
.equ DDRD = 0x0a |
.equ PIND = 0x09 |
.equ PORTC = 0x08 |
.equ DDRC = 0x07 |
.equ PINC = 0x06 |
.equ PORTB = 0x05 |
.equ DDRB = 0x04 |
.equ PINB = 0x03 |
; ***** BIT DEFINITIONS ************************************************** |
; ***** USART0 *********************** |
; UDR0 - USART I/O Data Register |
.equ UDR0_0 = 0 ; USART I/O Data Register bit 0 |
.equ UDR0_1 = 1 ; USART I/O Data Register bit 1 |
.equ UDR0_2 = 2 ; USART I/O Data Register bit 2 |
.equ UDR0_3 = 3 ; USART I/O Data Register bit 3 |
.equ UDR0_4 = 4 ; USART I/O Data Register bit 4 |
.equ UDR0_5 = 5 ; USART I/O Data Register bit 5 |
.equ UDR0_6 = 6 ; USART I/O Data Register bit 6 |
.equ UDR0_7 = 7 ; USART I/O Data Register bit 7 |
; UCSR0A - USART Control and Status Register A |
.equ MPCM0 = 0 ; Multi-processor Communication Mode |
.equ U2X0 = 1 ; Double the USART transmission speed |
.equ UPE0 = 2 ; Parity Error |
.equ DOR0 = 3 ; Data overRun |
.equ FE0 = 4 ; Framing Error |
.equ UDRE0 = 5 ; USART Data Register Empty |
.equ TXC0 = 6 ; USART Transmitt Complete |
.equ RXC0 = 7 ; USART Receive Complete |
; UCSR0B - USART Control and Status Register B |
.equ TXB80 = 0 ; Transmit Data Bit 8 |
.equ RXB80 = 1 ; Receive Data Bit 8 |
.equ UCSZ02 = 2 ; Character Size |
.equ TXEN0 = 3 ; Transmitter Enable |
.equ RXEN0 = 4 ; Receiver Enable |
.equ UDRIE0 = 5 ; USART Data register Empty Interrupt Enable |
.equ TXCIE0 = 6 ; TX Complete Interrupt Enable |
.equ RXCIE0 = 7 ; RX Complete Interrupt Enable |
; UCSR0C - USART Control and Status Register C |
.equ UCPOL0 = 0 ; Clock Polarity |
.equ UCSZ00 = 1 ; Character Size |
.equ UCPHA0 = UCSZ00 ; For compatibility |
.equ UCSZ01 = 2 ; Character Size |
.equ UDORD0 = UCSZ01 ; For compatibility |
.equ USBS0 = 3 ; Stop Bit Select |
.equ UPM00 = 4 ; Parity Mode Bit 0 |
.equ UPM01 = 5 ; Parity Mode Bit 1 |
.equ UMSEL00 = 6 ; USART Mode Select |
.equ UMSEL0 = UMSEL00 ; For compatibility |
.equ UMSEL01 = 7 ; USART Mode Select |
.equ UMSEL1 = UMSEL01 ; For compatibility |
; ***** TWI ************************** |
; TWAMR - TWI (Slave) Address Mask Register |
.equ TWAM0 = 1 ; |
.equ TWAMR0 = TWAM0 ; For compatibility |
.equ TWAM1 = 2 ; |
.equ TWAMR1 = TWAM1 ; For compatibility |
.equ TWAM2 = 3 ; |
.equ TWAMR2 = TWAM2 ; For compatibility |
.equ TWAM3 = 4 ; |
.equ TWAMR3 = TWAM3 ; For compatibility |
.equ TWAM4 = 5 ; |
.equ TWAMR4 = TWAM4 ; For compatibility |
.equ TWAM5 = 6 ; |
.equ TWAMR5 = TWAM5 ; For compatibility |
.equ TWAM6 = 7 ; |
.equ TWAMR6 = TWAM6 ; For compatibility |
; TWBR - TWI Bit Rate register |
.equ TWBR0 = 0 ; |
.equ TWBR1 = 1 ; |
.equ TWBR2 = 2 ; |
.equ TWBR3 = 3 ; |
.equ TWBR4 = 4 ; |
.equ TWBR5 = 5 ; |
.equ TWBR6 = 6 ; |
.equ TWBR7 = 7 ; |
; TWCR - TWI Control Register |
.equ TWIE = 0 ; TWI Interrupt Enable |
.equ TWEN = 2 ; TWI Enable Bit |
.equ TWWC = 3 ; TWI Write Collition Flag |
.equ TWSTO = 4 ; TWI Stop Condition Bit |
.equ TWSTA = 5 ; TWI Start Condition Bit |
.equ TWEA = 6 ; TWI Enable Acknowledge Bit |
.equ TWINT = 7 ; TWI Interrupt Flag |
; TWSR - TWI Status Register |
.equ TWPS0 = 0 ; TWI Prescaler |
.equ TWPS1 = 1 ; TWI Prescaler |
.equ TWS3 = 3 ; TWI Status |
.equ TWS4 = 4 ; TWI Status |
.equ TWS5 = 5 ; TWI Status |
.equ TWS6 = 6 ; TWI Status |
.equ TWS7 = 7 ; TWI Status |
; TWDR - TWI Data register |
.equ TWD0 = 0 ; TWI Data Register Bit 0 |
.equ TWD1 = 1 ; TWI Data Register Bit 1 |
.equ TWD2 = 2 ; TWI Data Register Bit 2 |
.equ TWD3 = 3 ; TWI Data Register Bit 3 |
.equ TWD4 = 4 ; TWI Data Register Bit 4 |
.equ TWD5 = 5 ; TWI Data Register Bit 5 |
.equ TWD6 = 6 ; TWI Data Register Bit 6 |
.equ TWD7 = 7 ; TWI Data Register Bit 7 |
; TWAR - TWI (Slave) Address register |
.equ TWGCE = 0 ; TWI General Call Recognition Enable Bit |
.equ TWA0 = 1 ; TWI (Slave) Address register Bit 0 |
.equ TWA1 = 2 ; TWI (Slave) Address register Bit 1 |
.equ TWA2 = 3 ; TWI (Slave) Address register Bit 2 |
.equ TWA3 = 4 ; TWI (Slave) Address register Bit 3 |
.equ TWA4 = 5 ; TWI (Slave) Address register Bit 4 |
.equ TWA5 = 6 ; TWI (Slave) Address register Bit 5 |
.equ TWA6 = 7 ; TWI (Slave) Address register Bit 6 |
; ***** TIMER_COUNTER_1 ************** |
; TIMSK1 - Timer/Counter Interrupt Mask Register |
.equ TOIE1 = 0 ; Timer/Counter1 Overflow Interrupt Enable |
.equ OCIE1A = 1 ; Timer/Counter1 Output CompareA Match Interrupt Enable |
.equ OCIE1B = 2 ; Timer/Counter1 Output CompareB Match Interrupt Enable |
.equ ICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable |
; TIFR1 - Timer/Counter Interrupt Flag register |
.equ TOV1 = 0 ; Timer/Counter1 Overflow Flag |
.equ OCF1A = 1 ; Output Compare Flag 1A |
.equ OCF1B = 2 ; Output Compare Flag 1B |
.equ ICF1 = 5 ; Input Capture Flag 1 |
; TCCR1A - Timer/Counter1 Control Register A |
.equ WGM10 = 0 ; Waveform Generation Mode |
.equ WGM11 = 1 ; Waveform Generation Mode |
.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0 |
.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1 |
.equ COM1A0 = 6 ; Comparet Ouput Mode 1A, bit 0 |
.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1 |
; TCCR1B - Timer/Counter1 Control Register B |
.equ CS10 = 0 ; Prescaler source of Timer/Counter 1 |
.equ CS11 = 1 ; Prescaler source of Timer/Counter 1 |
.equ CS12 = 2 ; Prescaler source of Timer/Counter 1 |
.equ WGM12 = 3 ; Waveform Generation Mode |
.equ WGM13 = 4 ; Waveform Generation Mode |
.equ ICES1 = 6 ; Input Capture 1 Edge Select |
.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler |
; TCCR1C - Timer/Counter1 Control Register C |
.equ FOC1B = 6 ; |
.equ FOC1A = 7 ; |
; GTCCR - General Timer/Counter Control Register |
.equ PSRSYNC = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0 |
.equ TSM = 7 ; Timer/Counter Synchronization Mode |
; ***** TIMER_COUNTER_2 ************** |
; TIMSK2 - Timer/Counter Interrupt Mask register |
.equ TOIE2 = 0 ; Timer/Counter2 Overflow Interrupt Enable |
.equ TOIE2A = TOIE2 ; For compatibility |
.equ OCIE2A = 1 ; Timer/Counter2 Output Compare Match A Interrupt Enable |
.equ OCIE2B = 2 ; Timer/Counter2 Output Compare Match B Interrupt Enable |
; TIFR2 - Timer/Counter Interrupt Flag Register |
.equ TOV2 = 0 ; Timer/Counter2 Overflow Flag |
.equ OCF2A = 1 ; Output Compare Flag 2A |
.equ OCF2B = 2 ; Output Compare Flag 2B |
; TCCR2A - Timer/Counter2 Control Register A |
.equ WGM20 = 0 ; Waveform Genration Mode |
.equ WGM21 = 1 ; Waveform Genration Mode |
.equ COM2B0 = 4 ; Compare Output Mode bit 0 |
.equ COM2B1 = 5 ; Compare Output Mode bit 1 |
.equ COM2A0 = 6 ; Compare Output Mode bit 1 |
.equ COM2A1 = 7 ; Compare Output Mode bit 1 |
; TCCR2B - Timer/Counter2 Control Register B |
.equ CS20 = 0 ; Clock Select bit 0 |
.equ CS21 = 1 ; Clock Select bit 1 |
.equ CS22 = 2 ; Clock Select bit 2 |
.equ WGM22 = 3 ; Waveform Generation Mode |
.equ FOC2B = 6 ; Force Output Compare B |
.equ FOC2A = 7 ; Force Output Compare A |
; TCNT2 - Timer/Counter2 |
.equ TCNT2_0 = 0 ; Timer/Counter 2 bit 0 |
.equ TCNT2_1 = 1 ; Timer/Counter 2 bit 1 |
.equ TCNT2_2 = 2 ; Timer/Counter 2 bit 2 |
.equ TCNT2_3 = 3 ; Timer/Counter 2 bit 3 |
.equ TCNT2_4 = 4 ; Timer/Counter 2 bit 4 |
.equ TCNT2_5 = 5 ; Timer/Counter 2 bit 5 |
.equ TCNT2_6 = 6 ; Timer/Counter 2 bit 6 |
.equ TCNT2_7 = 7 ; Timer/Counter 2 bit 7 |
; OCR2A - Timer/Counter2 Output Compare Register A |
.equ OCR2_0 = 0 ; Timer/Counter2 Output Compare Register Bit 0 |
.equ OCR2_1 = 1 ; Timer/Counter2 Output Compare Register Bit 1 |
.equ OCR2_2 = 2 ; Timer/Counter2 Output Compare Register Bit 2 |
.equ OCR2_3 = 3 ; Timer/Counter2 Output Compare Register Bit 3 |
.equ OCR2_4 = 4 ; Timer/Counter2 Output Compare Register Bit 4 |
.equ OCR2_5 = 5 ; Timer/Counter2 Output Compare Register Bit 5 |
.equ OCR2_6 = 6 ; Timer/Counter2 Output Compare Register Bit 6 |
.equ OCR2_7 = 7 ; Timer/Counter2 Output Compare Register Bit 7 |
; OCR2B - Timer/Counter2 Output Compare Register B |
;.equ OCR2_0 = 0 ; Timer/Counter2 Output Compare Register Bit 0 |
;.equ OCR2_1 = 1 ; Timer/Counter2 Output Compare Register Bit 1 |
;.equ OCR2_2 = 2 ; Timer/Counter2 Output Compare Register Bit 2 |
;.equ OCR2_3 = 3 ; Timer/Counter2 Output Compare Register Bit 3 |
;.equ OCR2_4 = 4 ; Timer/Counter2 Output Compare Register Bit 4 |
;.equ OCR2_5 = 5 ; Timer/Counter2 Output Compare Register Bit 5 |
;.equ OCR2_6 = 6 ; Timer/Counter2 Output Compare Register Bit 6 |
;.equ OCR2_7 = 7 ; Timer/Counter2 Output Compare Register Bit 7 |
; ASSR - Asynchronous Status Register |
.equ TCR2BUB = 0 ; Timer/Counter Control Register2 Update Busy |
.equ TCR2AUB = 1 ; Timer/Counter Control Register2 Update Busy |
.equ OCR2BUB = 2 ; Output Compare Register 2 Update Busy |
.equ OCR2AUB = 3 ; Output Compare Register2 Update Busy |
.equ TCN2UB = 4 ; Timer/Counter2 Update Busy |
.equ AS2 = 5 ; Asynchronous Timer/Counter2 |
.equ EXCLK = 6 ; Enable External Clock Input |
; GTCCR - General Timer Counter Control register |
.equ PSRASY = 1 ; Prescaler Reset Timer/Counter2 |
.equ PSR2 = PSRASY ; For compatibility |
;.equ TSM = 7 ; Timer/Counter Synchronization Mode |
; ***** AD_CONVERTER ***************** |
; ADMUX - The ADC multiplexer Selection Register |
.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits |
.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits |
.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits |
.equ MUX3 = 3 ; Analog Channel and Gain Selection Bits |
.equ ADLAR = 5 ; Left Adjust Result |
.equ REFS0 = 6 ; Reference Selection Bit 0 |
.equ REFS1 = 7 ; Reference Selection Bit 1 |
; ADCSRA - The ADC Control and Status register A |
.equ ADPS0 = 0 ; ADC Prescaler Select Bits |
.equ ADPS1 = 1 ; ADC Prescaler Select Bits |
.equ ADPS2 = 2 ; ADC Prescaler Select Bits |
.equ ADIE = 3 ; ADC Interrupt Enable |
.equ ADIF = 4 ; ADC Interrupt Flag |
.equ ADATE = 5 ; ADC Auto Trigger Enable |
.equ ADSC = 6 ; ADC Start Conversion |
.equ ADEN = 7 ; ADC Enable |
; ADCSRB - The ADC Control and Status register B |
.equ ADTS0 = 0 ; ADC Auto Trigger Source bit 0 |
.equ ADTS1 = 1 ; ADC Auto Trigger Source bit 1 |
.equ ADTS2 = 2 ; ADC Auto Trigger Source bit 2 |
.equ ACME = 6 ; |
; ADCH - ADC Data Register High Byte |
.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0 |
.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1 |
.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2 |
.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3 |
.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4 |
.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5 |
.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6 |
.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7 |
; ADCL - ADC Data Register Low Byte |
.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0 |
.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1 |
.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2 |
.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3 |
.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4 |
.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5 |
.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6 |
.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7 |
; DIDR0 - Digital Input Disable Register |
.equ ADC0D = 0 ; |
.equ ADC1D = 1 ; |
.equ ADC2D = 2 ; |
.equ ADC3D = 3 ; |
.equ ADC4D = 4 ; |
.equ ADC5D = 5 ; |
; ***** ANALOG_COMPARATOR ************ |
; ACSR - Analog Comparator Control And Status Register |
.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 |
.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 |
.equ ACIC = 2 ; |
.equ ACIE = 3 ; Analog Comparator Interrupt Enable |
.equ ACI = 4 ; Analog Comparator Interrupt Flag |
.equ ACO = 5 ; Analog Compare Output |
.equ ACBG = 6 ; Analog Comparator Bandgap Select |
.equ ACD = 7 ; Analog Comparator Disable |
; DIDR1 - Digital Input Disable Register 1 |
.equ AIN0D = 0 ; AIN0 Digital Input Disable |
.equ AIN1D = 1 ; AIN1 Digital Input Disable |
; ***** PORTB ************************ |
; PORTB - Port B Data Register |
.equ PORTB0 = 0 ; Port B Data Register bit 0 |
.equ PB0 = 0 ; For compatibility |
.equ PORTB1 = 1 ; Port B Data Register bit 1 |
.equ PB1 = 1 ; For compatibility |
.equ PORTB2 = 2 ; Port B Data Register bit 2 |
.equ PB2 = 2 ; For compatibility |
.equ PORTB3 = 3 ; Port B Data Register bit 3 |
.equ PB3 = 3 ; For compatibility |
.equ PORTB4 = 4 ; Port B Data Register bit 4 |
.equ PB4 = 4 ; For compatibility |
.equ PORTB5 = 5 ; Port B Data Register bit 5 |
.equ PB5 = 5 ; For compatibility |
.equ PORTB6 = 6 ; Port B Data Register bit 6 |
.equ PB6 = 6 ; For compatibility |
.equ PORTB7 = 7 ; Port B Data Register bit 7 |
.equ PB7 = 7 ; For compatibility |
; DDRB - Port B Data Direction Register |
.equ DDB0 = 0 ; Port B Data Direction Register bit 0 |
.equ DDB1 = 1 ; Port B Data Direction Register bit 1 |
.equ DDB2 = 2 ; Port B Data Direction Register bit 2 |
.equ DDB3 = 3 ; Port B Data Direction Register bit 3 |
.equ DDB4 = 4 ; Port B Data Direction Register bit 4 |
.equ DDB5 = 5 ; Port B Data Direction Register bit 5 |
.equ DDB6 = 6 ; Port B Data Direction Register bit 6 |
.equ DDB7 = 7 ; Port B Data Direction Register bit 7 |
; PINB - Port B Input Pins |
.equ PINB0 = 0 ; Port B Input Pins bit 0 |
.equ PINB1 = 1 ; Port B Input Pins bit 1 |
.equ PINB2 = 2 ; Port B Input Pins bit 2 |
.equ PINB3 = 3 ; Port B Input Pins bit 3 |
.equ PINB4 = 4 ; Port B Input Pins bit 4 |
.equ PINB5 = 5 ; Port B Input Pins bit 5 |
.equ PINB6 = 6 ; Port B Input Pins bit 6 |
.equ PINB7 = 7 ; Port B Input Pins bit 7 |
; ***** PORTC ************************ |
; PORTC - Port C Data Register |
.equ PORTC0 = 0 ; Port C Data Register bit 0 |
.equ PC0 = 0 ; For compatibility |
.equ PORTC1 = 1 ; Port C Data Register bit 1 |
.equ PC1 = 1 ; For compatibility |
.equ PORTC2 = 2 ; Port C Data Register bit 2 |
.equ PC2 = 2 ; For compatibility |
.equ PORTC3 = 3 ; Port C Data Register bit 3 |
.equ PC3 = 3 ; For compatibility |
.equ PORTC4 = 4 ; Port C Data Register bit 4 |
.equ PC4 = 4 ; For compatibility |
.equ PORTC5 = 5 ; Port C Data Register bit 5 |
.equ PC5 = 5 ; For compatibility |
.equ PORTC6 = 6 ; Port C Data Register bit 6 |
.equ PC6 = 6 ; For compatibility |
; DDRC - Port C Data Direction Register |
.equ DDC0 = 0 ; Port C Data Direction Register bit 0 |
.equ DDC1 = 1 ; Port C Data Direction Register bit 1 |
.equ DDC2 = 2 ; Port C Data Direction Register bit 2 |
.equ DDC3 = 3 ; Port C Data Direction Register bit 3 |
.equ DDC4 = 4 ; Port C Data Direction Register bit 4 |
.equ DDC5 = 5 ; Port C Data Direction Register bit 5 |
.equ DDC6 = 6 ; Port C Data Direction Register bit 6 |
; PINC - Port C Input Pins |
.equ PINC0 = 0 ; Port C Input Pins bit 0 |
.equ PINC1 = 1 ; Port C Input Pins bit 1 |
.equ PINC2 = 2 ; Port C Input Pins bit 2 |
.equ PINC3 = 3 ; Port C Input Pins bit 3 |
.equ PINC4 = 4 ; Port C Input Pins bit 4 |
.equ PINC5 = 5 ; Port C Input Pins bit 5 |
.equ PINC6 = 6 ; Port C Input Pins bit 6 |
; ***** PORTD ************************ |
; PORTD - Port D Data Register |
.equ PORTD0 = 0 ; Port D Data Register bit 0 |
.equ PD0 = 0 ; For compatibility |
.equ PORTD1 = 1 ; Port D Data Register bit 1 |
.equ PD1 = 1 ; For compatibility |
.equ PORTD2 = 2 ; Port D Data Register bit 2 |
.equ PD2 = 2 ; For compatibility |
.equ PORTD3 = 3 ; Port D Data Register bit 3 |
.equ PD3 = 3 ; For compatibility |
.equ PORTD4 = 4 ; Port D Data Register bit 4 |
.equ PD4 = 4 ; For compatibility |
.equ PORTD5 = 5 ; Port D Data Register bit 5 |
.equ PD5 = 5 ; For compatibility |
.equ PORTD6 = 6 ; Port D Data Register bit 6 |
.equ PD6 = 6 ; For compatibility |
.equ PORTD7 = 7 ; Port D Data Register bit 7 |
.equ PD7 = 7 ; For compatibility |
; DDRD - Port D Data Direction Register |
.equ DDD0 = 0 ; Port D Data Direction Register bit 0 |
.equ DDD1 = 1 ; Port D Data Direction Register bit 1 |
.equ DDD2 = 2 ; Port D Data Direction Register bit 2 |
.equ DDD3 = 3 ; Port D Data Direction Register bit 3 |
.equ DDD4 = 4 ; Port D Data Direction Register bit 4 |
.equ DDD5 = 5 ; Port D Data Direction Register bit 5 |
.equ DDD6 = 6 ; Port D Data Direction Register bit 6 |
.equ DDD7 = 7 ; Port D Data Direction Register bit 7 |
; PIND - Port D Input Pins |
.equ PIND0 = 0 ; Port D Input Pins bit 0 |
.equ PIND1 = 1 ; Port D Input Pins bit 1 |
.equ PIND2 = 2 ; Port D Input Pins bit 2 |
.equ PIND3 = 3 ; Port D Input Pins bit 3 |
.equ PIND4 = 4 ; Port D Input Pins bit 4 |
.equ PIND5 = 5 ; Port D Input Pins bit 5 |
.equ PIND6 = 6 ; Port D Input Pins bit 6 |
.equ PIND7 = 7 ; Port D Input Pins bit 7 |
; ***** TIMER_COUNTER_0 ************** |
; TIMSK0 - Timer/Counter0 Interrupt Mask Register |
.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable |
.equ OCIE0A = 1 ; Timer/Counter0 Output Compare Match A Interrupt Enable |
.equ OCIE0B = 2 ; Timer/Counter0 Output Compare Match B Interrupt Enable |
; TIFR0 - Timer/Counter0 Interrupt Flag register |
.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag |
.equ OCF0A = 1 ; Timer/Counter0 Output Compare Flag 0A |
.equ OCF0B = 2 ; Timer/Counter0 Output Compare Flag 0B |
; TCCR0A - Timer/Counter Control Register A |
.equ WGM00 = 0 ; Waveform Generation Mode |
.equ WGM01 = 1 ; Waveform Generation Mode |
.equ COM0B0 = 4 ; Compare Output Mode, Fast PWm |
.equ COM0B1 = 5 ; Compare Output Mode, Fast PWm |
.equ COM0A0 = 6 ; Compare Output Mode, Phase Correct PWM Mode |
.equ COM0A1 = 7 ; Compare Output Mode, Phase Correct PWM Mode |
; TCCR0B - Timer/Counter Control Register B |
.equ CS00 = 0 ; Clock Select |
.equ CS01 = 1 ; Clock Select |
.equ CS02 = 2 ; Clock Select |
.equ WGM02 = 3 ; |
.equ FOC0B = 6 ; Force Output Compare B |
.equ FOC0A = 7 ; Force Output Compare A |
; TCNT0 - Timer/Counter0 |
.equ TCNT0_0 = 0 ; |
.equ TCNT0_1 = 1 ; |
.equ TCNT0_2 = 2 ; |
.equ TCNT0_3 = 3 ; |
.equ TCNT0_4 = 4 ; |
.equ TCNT0_5 = 5 ; |
.equ TCNT0_6 = 6 ; |
.equ TCNT0_7 = 7 ; |
; OCR0A - Timer/Counter0 Output Compare Register |
.equ OCROA_0 = 0 ; |
.equ OCROA_1 = 1 ; |
.equ OCROA_2 = 2 ; |
.equ OCROA_3 = 3 ; |
.equ OCROA_4 = 4 ; |
.equ OCROA_5 = 5 ; |
.equ OCROA_6 = 6 ; |
.equ OCROA_7 = 7 ; |
; OCR0B - Timer/Counter0 Output Compare Register |
.equ OCR0B_0 = 0 ; |
.equ OCR0B_1 = 1 ; |
.equ OCR0B_2 = 2 ; |
.equ OCR0B_3 = 3 ; |
.equ OCR0B_4 = 4 ; |
.equ OCR0B_5 = 5 ; |
.equ OCR0B_6 = 6 ; |
.equ OCR0B_7 = 7 ; |
; GTCCR - General Timer/Counter Control Register |
;.equ PSRSYNC = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0 |
.equ PSR10 = PSRSYNC ; For compatibility |
;.equ TSM = 7 ; Timer/Counter Synchronization Mode |
; ***** EXTERNAL_INTERRUPT *********** |
; EICRA - External Interrupt Control Register |
.equ ISC00 = 0 ; External Interrupt Sense Control 0 Bit 0 |
.equ ISC01 = 1 ; External Interrupt Sense Control 0 Bit 1 |
.equ ISC10 = 2 ; External Interrupt Sense Control 1 Bit 0 |
.equ ISC11 = 3 ; External Interrupt Sense Control 1 Bit 1 |
; EIMSK - External Interrupt Mask Register |
.equ INT0 = 0 ; External Interrupt Request 0 Enable |
.equ INT1 = 1 ; External Interrupt Request 1 Enable |
; EIFR - External Interrupt Flag Register |
.equ INTF0 = 0 ; External Interrupt Flag 0 |
.equ INTF1 = 1 ; External Interrupt Flag 1 |
; PCMSK2 - Pin Change Mask Register 2 |
.equ PCINT16 = 0 ; Pin Change Enable Mask 16 |
.equ PCINT17 = 1 ; Pin Change Enable Mask 17 |
.equ PCINT18 = 2 ; Pin Change Enable Mask 18 |
.equ PCINT19 = 3 ; Pin Change Enable Mask 19 |
.equ PCINT20 = 4 ; Pin Change Enable Mask 20 |
.equ PCINT21 = 5 ; Pin Change Enable Mask 21 |
.equ PCINT22 = 6 ; Pin Change Enable Mask 22 |
.equ PCINT23 = 7 ; Pin Change Enable Mask 23 |
; PCMSK1 - Pin Change Mask Register 1 |
.equ PCINT8 = 0 ; Pin Change Enable Mask 8 |
.equ PCINT9 = 1 ; Pin Change Enable Mask 9 |
.equ PCINT10 = 2 ; Pin Change Enable Mask 10 |
.equ PCINT11 = 3 ; Pin Change Enable Mask 11 |
.equ PCINT12 = 4 ; Pin Change Enable Mask 12 |
.equ PCINT13 = 5 ; Pin Change Enable Mask 13 |
.equ PCINT14 = 6 ; Pin Change Enable Mask 14 |
; PCMSK0 - Pin Change Mask Register 0 |
.equ PCINT0 = 0 ; Pin Change Enable Mask 0 |
.equ PCINT1 = 1 ; Pin Change Enable Mask 1 |
.equ PCINT2 = 2 ; Pin Change Enable Mask 2 |
.equ PCINT3 = 3 ; Pin Change Enable Mask 3 |
.equ PCINT4 = 4 ; Pin Change Enable Mask 4 |
.equ PCINT5 = 5 ; Pin Change Enable Mask 5 |
.equ PCINT6 = 6 ; Pin Change Enable Mask 6 |
.equ PCINT7 = 7 ; Pin Change Enable Mask 7 |
; PCIFR - Pin Change Interrupt Flag Register |
.equ PCIF0 = 0 ; Pin Change Interrupt Flag 0 |
.equ PCIF1 = 1 ; Pin Change Interrupt Flag 1 |
.equ PCIF2 = 2 ; Pin Change Interrupt Flag 2 |
; ***** SPI ************************** |
; SPDR - SPI Data Register |
.equ SPDR0 = 0 ; SPI Data Register bit 0 |
.equ SPDR1 = 1 ; SPI Data Register bit 1 |
.equ SPDR2 = 2 ; SPI Data Register bit 2 |
.equ SPDR3 = 3 ; SPI Data Register bit 3 |
.equ SPDR4 = 4 ; SPI Data Register bit 4 |
.equ SPDR5 = 5 ; SPI Data Register bit 5 |
.equ SPDR6 = 6 ; SPI Data Register bit 6 |
.equ SPDR7 = 7 ; SPI Data Register bit 7 |
; SPSR - SPI Status Register |
.equ SPI2X = 0 ; Double SPI Speed Bit |
.equ WCOL = 6 ; Write Collision Flag |
.equ SPIF = 7 ; SPI Interrupt Flag |
; SPCR - SPI Control Register |
.equ SPR0 = 0 ; SPI Clock Rate Select 0 |
.equ SPR1 = 1 ; SPI Clock Rate Select 1 |
.equ CPHA = 2 ; Clock Phase |
.equ CPOL = 3 ; Clock polarity |
.equ MSTR = 4 ; Master/Slave Select |
.equ DORD = 5 ; Data Order |
.equ SPE = 6 ; SPI Enable |
.equ SPIE = 7 ; SPI Interrupt Enable |
; ***** CPU ************************** |
; SREG - Status Register |
.equ SREG_C = 0 ; Carry Flag |
.equ SREG_Z = 1 ; Zero Flag |
.equ SREG_N = 2 ; Negative Flag |
.equ SREG_V = 3 ; Two's Complement Overflow Flag |
.equ SREG_S = 4 ; Sign Bit |
.equ SREG_H = 5 ; Half Carry Flag |
.equ SREG_T = 6 ; Bit Copy Storage |
.equ SREG_I = 7 ; Global Interrupt Enable |
; OSCCAL - Oscillator Calibration Value |
.equ CAL0 = 0 ; Oscillator Calibration Value Bit0 |
.equ CAL1 = 1 ; Oscillator Calibration Value Bit1 |
.equ CAL2 = 2 ; Oscillator Calibration Value Bit2 |
.equ CAL3 = 3 ; Oscillator Calibration Value Bit3 |
.equ CAL4 = 4 ; Oscillator Calibration Value Bit4 |
.equ CAL5 = 5 ; Oscillator Calibration Value Bit5 |
.equ CAL6 = 6 ; Oscillator Calibration Value Bit6 |
.equ CAL7 = 7 ; Oscillator Calibration Value Bit7 |
; CLKPR - Clock Prescale Register |
.equ CLKPS0 = 0 ; Clock Prescaler Select Bit 0 |
.equ CLKPS1 = 1 ; Clock Prescaler Select Bit 1 |
.equ CLKPS2 = 2 ; Clock Prescaler Select Bit 2 |
.equ CLKPS3 = 3 ; Clock Prescaler Select Bit 3 |
.equ CLKPCE = 7 ; Clock Prescaler Change Enable |
; SPMCSR - Store Program Memory Control Register |
.equ SELFPRGEN = 0 ; Self Programming Enable |
.equ PGERS = 1 ; Page Erase |
.equ PGWRT = 2 ; Page Write |
.equ BLBSET = 3 ; Boot Lock Bit Set |
.equ RWWSRE = 4 ; Read-While-Write section read enable |
.equ RWWSB = 6 ; Read-While-Write Section Busy |
.equ SPMIE = 7 ; SPM Interrupt Enable |
; MCUCR - MCU Control Register |
.equ IVCE = 0 ; |
.equ IVSEL = 1 ; |
.equ PUD = 4 ; |
; MCUSR - MCU Status Register |
.equ PORF = 0 ; Power-on reset flag |
.equ EXTRF = 1 ; External Reset Flag |
.equ EXTREF = EXTRF ; For compatibility |
.equ BORF = 2 ; Brown-out Reset Flag |
.equ WDRF = 3 ; Watchdog Reset Flag |
; SMCR - |
.equ SE = 0 ; |
.equ SM0 = 1 ; |
.equ SM1 = 2 ; |
.equ SM2 = 3 ; |
; GPIOR2 - General Purpose I/O Register 2 |
.equ GPIOR20 = 0 ; |
.equ GPIOR21 = 1 ; |
.equ GPIOR22 = 2 ; |
.equ GPIOR23 = 3 ; |
.equ GPIOR24 = 4 ; |
.equ GPIOR25 = 5 ; |
.equ GPIOR26 = 6 ; |
.equ GPIOR27 = 7 ; |
; GPIOR1 - General Purpose I/O Register 1 |
.equ GPIOR10 = 0 ; |
.equ GPIOR11 = 1 ; |
.equ GPIOR12 = 2 ; |
.equ GPIOR13 = 3 ; |
.equ GPIOR14 = 4 ; |
.equ GPIOR15 = 5 ; |
.equ GPIOR16 = 6 ; |
.equ GPIOR17 = 7 ; |
; GPIOR0 - General Purpose I/O Register 0 |
.equ GPIOR00 = 0 ; |
.equ GPIOR01 = 1 ; |
.equ GPIOR02 = 2 ; |
.equ GPIOR03 = 3 ; |
.equ GPIOR04 = 4 ; |
.equ GPIOR05 = 5 ; |
.equ GPIOR06 = 6 ; |
.equ GPIOR07 = 7 ; |
; PRR - Power Reduction Register |
.equ PRADC = 0 ; Power Reduction ADC |
.equ PRUSART0 = 1 ; Power Reduction USART |
.equ PRSPI = 2 ; Power Reduction Serial Peripheral Interface |
.equ PRTIM1 = 3 ; Power Reduction Timer/Counter1 |
.equ PRTIM0 = 5 ; Power Reduction Timer/Counter0 |
.equ PRTIM2 = 6 ; Power Reduction Timer/Counter2 |
.equ PRTWI = 7 ; Power Reduction TWI |
; PCICR - |
.equ PCIE0 = 0 ; |
.equ PCIE1 = 1 ; |
.equ PCIE2 = 2 ; |
; ***** WATCHDOG ********************* |
; WDTCSR - Watchdog Timer Control Register |
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 |
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 |
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 |
.equ WDE = 3 ; Watch Dog Enable |
.equ WDCE = 4 ; Watchdog Change Enable |
.equ WDP3 = 5 ; Watchdog Timer Prescaler Bit 3 |
.equ WDIE = 6 ; Watchdog Timeout Interrupt Enable |
.equ WDIF = 7 ; Watchdog Timeout Interrupt Flag |
; ***** EEPROM *********************** |
; EEARL - EEPROM Address Register Low Byte |
.equ EEAR0 = 0 ; EEPROM Read/Write Access Bit 0 |
.equ EEAR1 = 1 ; EEPROM Read/Write Access Bit 1 |
.equ EEAR2 = 2 ; EEPROM Read/Write Access Bit 2 |
.equ EEAR3 = 3 ; EEPROM Read/Write Access Bit 3 |
.equ EEAR4 = 4 ; EEPROM Read/Write Access Bit 4 |
.equ EEAR5 = 5 ; EEPROM Read/Write Access Bit 5 |
.equ EEAR6 = 6 ; EEPROM Read/Write Access Bit 6 |
.equ EEAR7 = 7 ; EEPROM Read/Write Access Bit 7 |
; EEARH - EEPROM Address Register High Byte |
.equ EEAR8 = 0 ; EEPROM Read/Write Access Bit 0 |
; EEDR - EEPROM Data Register |
.equ EEDR0 = 0 ; EEPROM Data Register bit 0 |
.equ EEDR1 = 1 ; EEPROM Data Register bit 1 |
.equ EEDR2 = 2 ; EEPROM Data Register bit 2 |
.equ EEDR3 = 3 ; EEPROM Data Register bit 3 |
.equ EEDR4 = 4 ; EEPROM Data Register bit 4 |
.equ EEDR5 = 5 ; EEPROM Data Register bit 5 |
.equ EEDR6 = 6 ; EEPROM Data Register bit 6 |
.equ EEDR7 = 7 ; EEPROM Data Register bit 7 |
; EECR - EEPROM Control Register |
.equ EERE = 0 ; EEPROM Read Enable |
.equ EEPE = 1 ; EEPROM Write Enable |
.equ EEMPE = 2 ; EEPROM Master Write Enable |
.equ EERIE = 3 ; EEPROM Ready Interrupt Enable |
.equ EEPM0 = 4 ; EEPROM Programming Mode Bit 0 |
.equ EEPM1 = 5 ; EEPROM Programming Mode Bit 1 |
; ***** LOCKSBITS ******************************************************** |
.equ LB1 = 0 ; Lock bit |
.equ LB2 = 1 ; Lock bit |
.equ BLB01 = 2 ; Boot Lock bit |
.equ BLB02 = 3 ; Boot Lock bit |
.equ BLB11 = 4 ; Boot lock bit |
.equ BLB12 = 5 ; Boot lock bit |
; ***** FUSES ************************************************************ |
; LOW fuse bits |
.equ CKSEL0 = 0 ; Select Clock Source |
.equ CKSEL1 = 1 ; Select Clock Source |
.equ CKSEL2 = 2 ; Select Clock Source |
.equ CKSEL3 = 3 ; Select Clock Source |
.equ SUT0 = 4 ; Select start-up time |
.equ SUT1 = 5 ; Select start-up time |
.equ CKOUT = 6 ; Clock output |
.equ CKDIV8 = 7 ; Divide clock by 8 |
; HIGH fuse bits |
.equ BODLEVEL0 = 0 ; Brown-out Detector trigger level |
.equ BODLEVEL1 = 1 ; Brown-out Detector trigger level |
.equ BODLEVEL2 = 2 ; Brown-out Detector trigger level |
.equ EESAVE = 3 ; EEPROM memory is preserved through chip erase |
.equ WDTON = 4 ; Watchdog Timer Always On |
.equ SPIEN = 5 ; Enable Serial programming and Data Downloading |
.equ DWEN = 6 ; debugWIRE Enable |
.equ RSTDISBL = 7 ; External reset disable |
; EXTENDED fuse bits |
.equ BOOTRST = 0 ; Select reset vector |
.equ BOOTSZ0 = 1 ; Select boot size |
.equ BOOTSZ1 = 2 ; Select boot size |
; ***** CPU REGISTER DEFINITIONS ***************************************** |
.def XH = r27 |
.def XL = r26 |
.def YH = r29 |
.def YL = r28 |
.def ZH = r31 |
.def ZL = r30 |
; ***** DATA MEMORY DECLARATIONS ***************************************** |
.equ FLASHEND = 0x1fff ; Note: Word address |
.equ IOEND = 0x00ff |
.equ SRAM_START = 0x0100 |
.equ SRAM_SIZE = 1024 |
.equ RAMEND = 0x04ff |
.equ XRAMEND = 0x0000 |
.equ E2END = 0x01ff |
.equ EEPROMEND = 0x01ff |
.equ EEADRBITS = 9 |
#pragma AVRPART MEMORY PROG_FLASH 16384 |
#pragma AVRPART MEMORY EEPROM 512 |
#pragma AVRPART MEMORY INT_SRAM SIZE 1024 |
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x100 |
; ***** BOOTLOADER DECLARATIONS ****************************************** |
.equ NRWW_START_ADDR = 0x1c00 |
.equ NRWW_STOP_ADDR = 0x1fff |
.equ RWW_START_ADDR = 0x0 |
.equ RWW_STOP_ADDR = 0x1bff |
.equ PAGESIZE = 64 |
.equ FIRSTBOOTSTART = 0x1f80 |
.equ SECONDBOOTSTART = 0x1f00 |
.equ THIRDBOOTSTART = 0x1e00 |
.equ FOURTHBOOTSTART = 0x1c00 |
.equ SMALLBOOTSTART = FIRSTBOOTSTART |
.equ LARGEBOOTSTART = FOURTHBOOTSTART |
; ***** INTERRUPT VECTORS ************************************************ |
.equ INT0addr = 0x0002 ; External Interrupt Request 0 |
.equ INT1addr = 0x0004 ; External Interrupt Request 1 |
.equ PCI0addr = 0x0006 ; Pin Change Interrupt Request 0 |
.equ PCI1addr = 0x0008 ; Pin Change Interrupt Request 0 |
.equ PCI2addr = 0x000a ; Pin Change Interrupt Request 1 |
.equ WDTaddr = 0x000c ; Watchdog Time-out Interrupt |
.equ OC2Aaddr = 0x000e ; Timer/Counter2 Compare Match A |
.equ OC2Baddr = 0x0010 ; Timer/Counter2 Compare Match A |
.equ OVF2addr = 0x0012 ; Timer/Counter2 Overflow |
.equ ICP1addr = 0x0014 ; Timer/Counter1 Capture Event |
.equ OC1Aaddr = 0x0016 ; Timer/Counter1 Compare Match A |
.equ OC1Baddr = 0x0018 ; Timer/Counter1 Compare Match B |
.equ OVF1addr = 0x001a ; Timer/Counter1 Overflow |
.equ OC0Aaddr = 0x001c ; TimerCounter0 Compare Match A |
.equ OC0Baddr = 0x001e ; TimerCounter0 Compare Match B |
.equ OVF0addr = 0x0020 ; Timer/Couner0 Overflow |
.equ SPIaddr = 0x0022 ; SPI Serial Transfer Complete |
.equ URXCaddr = 0x0024 ; USART Rx Complete |
.equ UDREaddr = 0x0026 ; USART, Data Register Empty |
.equ UTXCaddr = 0x0028 ; USART Tx Complete |
.equ ADCCaddr = 0x002a ; ADC Conversion Complete |
.equ ERDYaddr = 0x002c ; EEPROM Ready |
.equ ACIaddr = 0x002e ; Analog Comparator |
.equ TWIaddr = 0x0030 ; Two-wire Serial Interface |
.equ SPMRaddr = 0x0032 ; Store Program Memory Read |
.equ INT_VECTORS_SIZE = 52 ; size in words |
#endif /* _M168DEF_INC_ */ |
; ***** END OF FILE ****************************************************** |
/contrib/toolchain/avra/includes/m169def.inc |
---|
0,0 → 1,1248 |
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** |
;***** Created: 2005-01-11 10:30 ******* Source: ATmega169.xml *********** |
;************************************************************************* |
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y |
;* |
;* Number : AVR000 |
;* File Name : "m169def.inc" |
;* Title : Register/Bit Definitions for the ATmega169 |
;* Date : 2005-01-11 |
;* Version : 2.14 |
;* Support E-mail : avr@atmel.com |
;* Target MCU : ATmega169 |
;* |
;* DESCRIPTION |
;* When including this file in the assembly program file, all I/O register |
;* names and I/O register bit names appearing in the data book can be used. |
;* In addition, the six registers forming the three data pointers X, Y and |
;* Z have been assigned names XL - ZH. Highest RAM address for Internal |
;* SRAM is also defined |
;* |
;* The Register names are represented by their hexadecimal address. |
;* |
;* The Register Bit names are represented by their bit number (0-7). |
;* |
;* Please observe the difference in using the bit names with instructions |
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" |
;* (skip if bit in register set/cleared). The following example illustrates |
;* this: |
;* |
;* in r16,PORTB ;read PORTB latch |
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) |
;* out PORTB,r16 ;output to PORTB |
;* |
;* in r16,TIFR ;read the Timer Interrupt Flag Register |
;* sbrc r16,TOV0 ;test the overflow flag (use bit#) |
;* rjmp TOV0_is_set ;jump if set |
;* ... ;otherwise do something else |
;************************************************************************* |
#ifndef _M169DEF_INC_ |
#define _M169DEF_INC_ |
#pragma partinc 0 |
; ***** SPECIFY DEVICE *************************************************** |
.device ATmega169 |
#pragma AVRPART ADMIN PART_NAME ATmega169 |
.equ SIGNATURE_000 = 0x1e |
.equ SIGNATURE_001 = 0x94 |
.equ SIGNATURE_002 = 0x05 |
#pragma AVRPART CORE CORE_VERSION V2E |
; ***** I/O REGISTER DEFINITIONS ***************************************** |
; NOTE: |
; Definitions marked "MEMORY MAPPED"are extended I/O ports |
; and cannot be used with IN/OUT instructions |
.equ LCDDR18 = 0xfe ; MEMORY MAPPED |
.equ LCDDR17 = 0xfd ; MEMORY MAPPED |
.equ LCDDR16 = 0xfc ; MEMORY MAPPED |
.equ LCDDR15 = 0xfb ; MEMORY MAPPED |
.equ LCDDR13 = 0xf9 ; MEMORY MAPPED |
.equ LCDDR12 = 0xf8 ; MEMORY MAPPED |
.equ LCDDR11 = 0xf7 ; MEMORY MAPPED |
.equ LCDDR10 = 0xf6 ; MEMORY MAPPED |
.equ LCDDR8 = 0xf4 ; MEMORY MAPPED |
.equ LCDDR7 = 0xf3 ; MEMORY MAPPED |
.equ LCDDR6 = 0xf2 ; MEMORY MAPPED |
.equ LCDDR5 = 0xf1 ; MEMORY MAPPED |
.equ LCDDR3 = 0xef ; MEMORY MAPPED |
.equ LCDDR2 = 0xee ; MEMORY MAPPED |
.equ LCDDR1 = 0xed ; MEMORY MAPPED |
.equ LCDDR0 = 0xec ; MEMORY MAPPED |
.equ LCDCCR = 0xe7 ; MEMORY MAPPED |
.equ LCDFRR = 0xe6 ; MEMORY MAPPED |
.equ LCDCRB = 0xe5 ; MEMORY MAPPED |
.equ LCDCRA = 0xe4 ; MEMORY MAPPED |
.equ UDR = 0xc6 ; MEMORY MAPPED |
.equ UBRRH = 0xc5 ; MEMORY MAPPED |
.equ UBRRL = 0xc4 ; MEMORY MAPPED |
.equ UCSRC = 0xc2 ; MEMORY MAPPED |
.equ UCSRB = 0xc1 ; MEMORY MAPPED |
.equ UCSRA = 0xc0 ; MEMORY MAPPED |
.equ USIDR = 0xba ; MEMORY MAPPED |
.equ USISR = 0xb9 ; MEMORY MAPPED |
.equ USICR = 0xb8 ; MEMORY MAPPED |
.equ ASSR = 0xb6 ; MEMORY MAPPED |
.equ OCR2A = 0xb3 ; MEMORY MAPPED |
.equ TCNT2 = 0xb2 ; MEMORY MAPPED |
.equ TCCR2B = 0xb1 ; MEMORY MAPPED |
.equ TCCR2A = 0xb0 ; MEMORY MAPPED |
.equ OCR1BH = 0x8b ; MEMORY MAPPED |
.equ OCR1BL = 0x8a ; MEMORY MAPPED |
.equ OCR1AH = 0x89 ; MEMORY MAPPED |
.equ OCR1AL = 0x88 ; MEMORY MAPPED |
.equ ICR1H = 0x87 ; MEMORY MAPPED |
.equ ICR1L = 0x86 ; MEMORY MAPPED |
.equ TCNT1H = 0x85 ; MEMORY MAPPED |
.equ TCNT1L = 0x84 ; MEMORY MAPPED |
.equ TCCR1C = 0x82 ; MEMORY MAPPED |
.equ TCCR1B = 0x81 ; MEMORY MAPPED |
.equ TCCR1A = 0x80 ; MEMORY MAPPED |
.equ DIDR1 = 0x7f ; MEMORY MAPPED |
.equ DIDR0 = 0x7e ; MEMORY MAPPED |
.equ ADMUX = 0x7c ; MEMORY MAPPED |
.equ ADCSRB = 0x7b ; MEMORY MAPPED |
.equ ADCSRA = 0x7a ; MEMORY MAPPED |
.equ ADCH = 0x79 ; MEMORY MAPPED |
.equ ADCL = 0x78 ; MEMORY MAPPED |
.equ TIMSK2 = 0x70 ; MEMORY MAPPED |
.equ TIMSK1 = 0x6f ; MEMORY MAPPED |
.equ TIMSK0 = 0x6e ; MEMORY MAPPED |
.equ PCMSK1 = 0x6c ; MEMORY MAPPED |
.equ PCMSK0 = 0x6b ; MEMORY MAPPED |
.equ EICRA = 0x69 ; MEMORY MAPPED |
.equ OSCCAL = 0x66 ; MEMORY MAPPED |
.equ PRR = 0x64 ; MEMORY MAPPED |
.equ CLKPR = 0x61 ; MEMORY MAPPED |
.equ WDTCR = 0x60 ; MEMORY MAPPED |
.equ SREG = 0x3f |
.equ SPH = 0x3e |
.equ SPL = 0x3d |
.equ SPMCSR = 0x37 |
.equ MCUCR = 0x35 |
.equ MCUSR = 0x34 |
.equ SMCR = 0x33 |
.equ OCDR = 0x31 |
.equ ACSR = 0x30 |
.equ SPDR = 0x2e |
.equ SPSR = 0x2d |
.equ SPCR = 0x2c |
.equ GPIOR2 = 0x2b |
.equ GPIOR1 = 0x2a |
.equ OCR0A = 0x27 |
.equ TCNT0 = 0x26 |
.equ TCCR0A = 0x24 |
.equ GTCCR = 0x23 |
.equ EEARH = 0x22 |
.equ EEARL = 0x21 |
.equ EEDR = 0x20 |
.equ EECR = 0x1f |
.equ GPIOR0 = 0x1e |
.equ EIMSK = 0x1d |
.equ EIFR = 0x1c |
.equ TIFR2 = 0x17 |
.equ TIFR1 = 0x16 |
.equ TIFR0 = 0x15 |
.equ PORTG = 0x14 |
.equ DDRG = 0x13 |
.equ PING = 0x12 |
.equ PORTF = 0x11 |
.equ DDRF = 0x10 |
.equ PINF = 0x0f |
.equ PORTE = 0x0e |
.equ DDRE = 0x0d |
.equ PINE = 0x0c |
.equ PORTD = 0x0b |
.equ DDRD = 0x0a |
.equ PIND = 0x09 |
.equ PORTC = 0x08 |
.equ DDRC = 0x07 |
.equ PINC = 0x06 |
.equ PORTB = 0x05 |
.equ DDRB = 0x04 |
.equ PINB = 0x03 |
.equ PORTA = 0x02 |
.equ DDRA = 0x01 |
.equ PINA = 0x00 |
; ***** BIT DEFINITIONS ************************************************** |
; ***** TIMER_COUNTER_0 ************** |
; TCCR0A - Timer/Counter0 Control Register |
.equ CS00 = 0 ; Clock Select 1 |
.equ CS01 = 1 ; Clock Select 1 |
.equ CS02 = 2 ; Clock Select 2 |
.equ WGM01 = 3 ; Waveform Generation Mode 1 |
.equ COM0A0 = 4 ; Compare match Output Mode 0 |
.equ COM0A1 = 5 ; Compare Match Output Mode 1 |
.equ WGM00 = 6 ; Waveform Generation Mode 0 |
.equ FOC0A = 7 ; Force Output Compare |
; TCNT0 - Timer/Counter0 |
.equ TCNT0_0 = 0 ; |
.equ TCNT0_1 = 1 ; |
.equ TCNT0_2 = 2 ; |
.equ TCNT0_3 = 3 ; |
.equ TCNT0_4 = 4 ; |
.equ TCNT0_5 = 5 ; |
.equ TCNT0_6 = 6 ; |
.equ TCNT0_7 = 7 ; |
; OCR0A - Timer/Counter0 Output Compare Register |
.equ OCR0A0 = 0 ; |
.equ OCR0A1 = 1 ; |
.equ OCR0A2 = 2 ; |
.equ OCR0A3 = 3 ; |
.equ OCR0A4 = 4 ; |
.equ OCR0A5 = 5 ; |
.equ OCR0A6 = 6 ; |
.equ OCR0A7 = 7 ; |
; TIMSK0 - Timer/Counter0 Interrupt Mask Register |
.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable |
.equ OCIE0A = 1 ; Timer/Counter0 Output Compare Match Interrupt Enable |
; TIFR0 - Timer/Counter0 Interrupt Flag register |
.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag |
.equ OCF0A = 1 ; Timer/Counter0 Output Compare Flag 0 |
; GTCCR - General Timer/Control Register |
.equ PSR310 = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0 |
.equ PSR10 = PSR310 ; For compatibility |
.equ PSR0 = PSR310 ; For compatibility |
.equ PSR1 = PSR310 ; For compatibility |
.equ PSR3 = PSR310 ; For compatibility |
.equ TSM = 7 ; Timer/Counter Synchronization Mode |
; ***** TIMER_COUNTER_1 ************** |
; TIMSK1 - Timer/Counter1 Interrupt Mask Register |
.equ TOIE1 = 0 ; Timer/Counter1 Overflow Interrupt Enable |
.equ OCIE1A = 1 ; Timer/Counter1 Output Compare A Match Interrupt Enable |
.equ OCIE1B = 2 ; Timer/Counter1 Output Compare B Match Interrupt Enable |
.equ ICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable |
; TIFR1 - Timer/Counter1 Interrupt Flag register |
.equ TOV1 = 0 ; Timer/Counter1 Overflow Flag |
.equ OCF1A = 1 ; Output Compare Flag 1A |
.equ OCF1B = 2 ; Output Compare Flag 1B |
.equ ICF1 = 5 ; Input Capture Flag 1 |
; TCCR1A - Timer/Counter1 Control Register A |
.equ WGM10 = 0 ; Waveform Generation Mode |
.equ WGM11 = 1 ; Waveform Generation Mode |
.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0 |
.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1 |
.equ COM1A0 = 6 ; Compare Output Mode 1A, bit 0 |
.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1 |
; TCCR1B - Timer/Counter1 Control Register B |
.equ CS10 = 0 ; Prescaler source of Timer/Counter 1 |
.equ CS11 = 1 ; Prescaler source of Timer/Counter 1 |
.equ CS12 = 2 ; Prescaler source of Timer/Counter 1 |
.equ WGM12 = 3 ; Waveform Generation Mode |
.equ WGM13 = 4 ; Waveform Generation Mode |
.equ ICES1 = 6 ; Input Capture 1 Edge Select |
.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler |
; TCCR1C - Timer/Counter 1 Control Register C |
.equ FOC1B = 6 ; Force Output Compare 1B |
.equ FOC1A = 7 ; Force Output Compare 1A |
; ***** TIMER_COUNTER_2 ************** |
; TIMSK2 - Timer/Counter2 Interrupt Mask register |
.equ TOIE2 = 0 ; Timer/Counter2 Overflow Interrupt Enable |
.equ OCIE2A = 1 ; Timer/Counter2 Output Compare Match Interrupt Enable |
; TIFR2 - Timer/Counter2 Interrupt Flag Register |
.equ TOV2 = 0 ; Timer/Counter2 Overflow Flag |
.equ OCF2A = 1 ; Timer/Counter2 Output Compare Flag 2 |
; TCCR2A - Timer/Counter2 Control Register |
.equ CS20 = 0 ; Clock Select bit 0 |
.equ CS21 = 1 ; Clock Select bit 1 |
.equ CS22 = 2 ; Clock Select bit 2 |
.equ WGM21 = 3 ; Waveform Generation Mode |
.equ COM2A0 = 4 ; Compare Output Mode bit 0 |
.equ COM2A1 = 5 ; Compare Output Mode bit 1 |
.equ WGM20 = 6 ; Waveform Generation Mode |
.equ FOC2A = 7 ; Force Output Compare A |
; TCNT2 - Timer/Counter2 |
.equ TCNT2_0 = 0 ; Timer/Counter 2 bit 0 |
.equ TCNT2_1 = 1 ; Timer/Counter 2 bit 1 |
.equ TCNT2_2 = 2 ; Timer/Counter 2 bit 2 |
.equ TCNT2_3 = 3 ; Timer/Counter 2 bit 3 |
.equ TCNT2_4 = 4 ; Timer/Counter 2 bit 4 |
.equ TCNT2_5 = 5 ; Timer/Counter 2 bit 5 |
.equ TCNT2_6 = 6 ; Timer/Counter 2 bit 6 |
.equ TCNT2_7 = 7 ; Timer/Counter 2 bit 7 |
; OCR2A - Timer/Counter2 Output Compare Register |
.equ OCR2A0 = 0 ; Timer/Counter2 Output Compare Register Bit 0 |
.equ OCR2A1 = 1 ; Timer/Counter2 Output Compare Register Bit 1 |
.equ OCR2A2 = 2 ; Timer/Counter2 Output Compare Register Bit 2 |
.equ OCR2A3 = 3 ; Timer/Counter2 Output Compare Register Bit 3 |
.equ OCR2A4 = 4 ; Timer/Counter2 Output Compare Register Bit 4 |
.equ OCR2A5 = 5 ; Timer/Counter2 Output Compare Register Bit 5 |
.equ OCR2A6 = 6 ; Timer/Counter2 Output Compare Register Bit 6 |
.equ OCR2A7 = 7 ; Timer/Counter2 Output Compare Register Bit 7 |
; GTCCR - General Timer/Counter Control Register |
.equ PSR2 = 1 ; Prescaler Reset Timer/Counter2 |
; ASSR - Asynchronous Status Register |
.equ TCR2UB = 0 ; TCR2UB: Timer/Counter Control Register2 Update Busy |
.equ OCR2UB = 1 ; Output Compare Register2 Update Busy |
.equ TCN2UB = 2 ; TCN2UB: Timer/Counter2 Update Busy |
.equ AS2 = 3 ; AS2: Asynchronous Timer/Counter2 |
.equ EXCLK = 4 ; Enable External Clock Interrupt |
; ***** WATCHDOG ********************* |
; WDTCR - Watchdog Timer Control Register |
.equ WDTCSR = WDTCR ; For compatibility |
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 |
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 |
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 |
.equ WDE = 3 ; Watch Dog Enable |
.equ WDCE = 4 ; Watchdog Change Enable |
.equ WDTOE = WDCE ; For compatibility |
; ***** EEPROM *********************** |
; EEDR - EEPROM Data Register |
.equ EEDR0 = 0 ; EEPROM Data Register bit 0 |
.equ EEDR1 = 1 ; EEPROM Data Register bit 1 |
.equ EEDR2 = 2 ; EEPROM Data Register bit 2 |
.equ EEDR3 = 3 ; EEPROM Data Register bit 3 |
.equ EEDR4 = 4 ; EEPROM Data Register bit 4 |
.equ EEDR5 = 5 ; EEPROM Data Register bit 5 |
.equ EEDR6 = 6 ; EEPROM Data Register bit 6 |
.equ EEDR7 = 7 ; EEPROM Data Register bit 7 |
; EECR - EEPROM Control Register |
.equ EERE = 0 ; EEPROM Read Enable |
.equ EEWE = 1 ; EEPROM Write Enable |
.equ EEMWE = 2 ; EEPROM Master Write Enable |
.equ EEWEE = EEMWE ; For compatibility |
.equ EERIE = 3 ; EEPROM Ready Interrupt Enable |
; ***** SPI ************************** |
; SPDR - SPI Data Register |
.equ SPDR0 = 0 ; SPI Data Register bit 0 |
.equ SPDR1 = 1 ; SPI Data Register bit 1 |
.equ SPDR2 = 2 ; SPI Data Register bit 2 |
.equ SPDR3 = 3 ; SPI Data Register bit 3 |
.equ SPDR4 = 4 ; SPI Data Register bit 4 |
.equ SPDR5 = 5 ; SPI Data Register bit 5 |
.equ SPDR6 = 6 ; SPI Data Register bit 6 |
.equ SPDR7 = 7 ; SPI Data Register bit 7 |
; SPSR - SPI Status Register |
.equ SPI2X = 0 ; Double SPI Speed Bit |
.equ WCOL = 6 ; Write Collision Flag |
.equ SPIF = 7 ; SPI Interrupt Flag |
; SPCR - SPI Control Register |
.equ SPR0 = 0 ; SPI Clock Rate Select 0 |
.equ SPR1 = 1 ; SPI Clock Rate Select 1 |
.equ CPHA = 2 ; Clock Phase |
.equ CPOL = 3 ; Clock polarity |
.equ MSTR = 4 ; Master/Slave Select |
.equ DORD = 5 ; Data Order |
.equ SPE = 6 ; SPI Enable |
.equ SPIE = 7 ; SPI Interrupt Enable |
; ***** PORTA ************************ |
; PORTA - Port A Data Register |
.equ PORTA0 = 0 ; Port A Data Register bit 0 |
.equ PA0 = 0 ; For compatibility |
.equ PORTA1 = 1 ; Port A Data Register bit 1 |
.equ PA1 = 1 ; For compatibility |
.equ PORTA2 = 2 ; Port A Data Register bit 2 |
.equ PA2 = 2 ; For compatibility |
.equ PORTA3 = 3 ; Port A Data Register bit 3 |
.equ PA3 = 3 ; For compatibility |
.equ PORTA4 = 4 ; Port A Data Register bit 4 |
.equ PA4 = 4 ; For compatibility |
.equ PORTA5 = 5 ; Port A Data Register bit 5 |
.equ PA5 = 5 ; For compatibility |
.equ PORTA6 = 6 ; Port A Data Register bit 6 |
.equ PA6 = 6 ; For compatibility |
.equ PORTA7 = 7 ; Port A Data Register bit 7 |
.equ PA7 = 7 ; For compatibility |
; DDRA - Port A Data Direction Register |
.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0 |
.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1 |
.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2 |
.equ DDA3 = 3 ; Data Direction Register, Port A, bit 3 |
.equ DDA4 = 4 ; Data Direction Register, Port A, bit 4 |
.equ DDA5 = 5 ; Data Direction Register, Port A, bit 5 |
.equ DDA6 = 6 ; Data Direction Register, Port A, bit 6 |
.equ DDA7 = 7 ; Data Direction Register, Port A, bit 7 |
; PINA - Port A Input Pins |
.equ PINA0 = 0 ; Input Pins, Port A bit 0 |
.equ PINA1 = 1 ; Input Pins, Port A bit 1 |
.equ PINA2 = 2 ; Input Pins, Port A bit 2 |
.equ PINA3 = 3 ; Input Pins, Port A bit 3 |
.equ PINA4 = 4 ; Input Pins, Port A bit 4 |
.equ PINA5 = 5 ; Input Pins, Port A bit 5 |
.equ PINA6 = 6 ; Input Pins, Port A bit 6 |
.equ PINA7 = 7 ; Input Pins, Port A bit 7 |
; ***** PORTB ************************ |
; PORTB - Port B Data Register |
.equ PORTB0 = 0 ; Port B Data Register bit 0 |
.equ PB0 = 0 ; For compatibility |
.equ PORTB1 = 1 ; Port B Data Register bit 1 |
.equ PB1 = 1 ; For compatibility |
.equ PORTB2 = 2 ; Port B Data Register bit 2 |
.equ PB2 = 2 ; For compatibility |
.equ PORTB3 = 3 ; Port B Data Register bit 3 |
.equ PB3 = 3 ; For compatibility |
.equ PORTB4 = 4 ; Port B Data Register bit 4 |
.equ PB4 = 4 ; For compatibility |
.equ PORTB5 = 5 ; Port B Data Register bit 5 |
.equ PB5 = 5 ; For compatibility |
.equ PORTB6 = 6 ; Port B Data Register bit 6 |
.equ PB6 = 6 ; For compatibility |
.equ PORTB7 = 7 ; Port B Data Register bit 7 |
.equ PB7 = 7 ; For compatibility |
; DDRB - Port B Data Direction Register |
.equ DDB0 = 0 ; Port B Data Direction Register bit 0 |
.equ DDB1 = 1 ; Port B Data Direction Register bit 1 |
.equ DDB2 = 2 ; Port B Data Direction Register bit 2 |
.equ DDB3 = 3 ; Port B Data Direction Register bit 3 |
.equ DDB4 = 4 ; Port B Data Direction Register bit 4 |
.equ DDB5 = 5 ; Port B Data Direction Register bit 5 |
.equ DDB6 = 6 ; Port B Data Direction Register bit 6 |
.equ DDB7 = 7 ; Port B Data Direction Register bit 7 |
; PINB - Port B Input Pins |
.equ PINB0 = 0 ; Port B Input Pins bit 0 |
.equ PINB1 = 1 ; Port B Input Pins bit 1 |
.equ PINB2 = 2 ; Port B Input Pins bit 2 |
.equ PINB3 = 3 ; Port B Input Pins bit 3 |
.equ PINB4 = 4 ; Port B Input Pins bit 4 |
.equ PINB5 = 5 ; Port B Input Pins bit 5 |
.equ PINB6 = 6 ; Port B Input Pins bit 6 |
.equ PINB7 = 7 ; Port B Input Pins bit 7 |
; ***** PORTC ************************ |
; PORTC - Port C Data Register |
.equ PORTC0 = 0 ; Port C Data Register bit 0 |
.equ PC0 = 0 ; For compatibility |
.equ PORTC1 = 1 ; Port C Data Register bit 1 |
.equ PC1 = 1 ; For compatibility |
.equ PORTC2 = 2 ; Port C Data Register bit 2 |
.equ PC2 = 2 ; For compatibility |
.equ PORTC3 = 3 ; Port C Data Register bit 3 |
.equ PC3 = 3 ; For compatibility |
.equ PORTC4 = 4 ; Port C Data Register bit 4 |
.equ PC4 = 4 ; For compatibility |
.equ PORTC5 = 5 ; Port C Data Register bit 5 |
.equ PC5 = 5 ; For compatibility |
.equ PORTC6 = 6 ; Port C Data Register bit 6 |
.equ PC6 = 6 ; For compatibility |
.equ PORTC7 = 7 ; Port C Data Register bit 7 |
.equ PC7 = 7 ; For compatibility |
; DDRC - Port C Data Direction Register |
.equ DDC0 = 0 ; Port C Data Direction Register bit 0 |
.equ DDC1 = 1 ; Port C Data Direction Register bit 1 |
.equ DDC2 = 2 ; Port C Data Direction Register bit 2 |
.equ DDC3 = 3 ; Port C Data Direction Register bit 3 |
.equ DDC4 = 4 ; Port C Data Direction Register bit 4 |
.equ DDC5 = 5 ; Port C Data Direction Register bit 5 |
.equ DDC6 = 6 ; Port C Data Direction Register bit 6 |
.equ DDC7 = 7 ; Port C Data Direction Register bit 7 |
; PINC - Port C Input Pins |
.equ PINC0 = 0 ; Port C Input Pins bit 0 |
.equ PINC1 = 1 ; Port C Input Pins bit 1 |
.equ PINC2 = 2 ; Port C Input Pins bit 2 |
.equ PINC3 = 3 ; Port C Input Pins bit 3 |
.equ PINC4 = 4 ; Port C Input Pins bit 4 |
.equ PINC5 = 5 ; Port C Input Pins bit 5 |
.equ PINC6 = 6 ; Port C Input Pins bit 6 |
.equ PINC7 = 7 ; Port C Input Pins bit 7 |
; ***** PORTD ************************ |
; PORTD - Port D Data Register |
.equ PORTD0 = 0 ; Port D Data Register bit 0 |
.equ PD0 = 0 ; For compatibility |
.equ PORTD1 = 1 ; Port D Data Register bit 1 |
.equ PD1 = 1 ; For compatibility |
.equ PORTD2 = 2 ; Port D Data Register bit 2 |
.equ PD2 = 2 ; For compatibility |
.equ PORTD3 = 3 ; Port D Data Register bit 3 |
.equ PD3 = 3 ; For compatibility |
.equ PORTD4 = 4 ; Port D Data Register bit 4 |
.equ PD4 = 4 ; For compatibility |
.equ PORTD5 = 5 ; Port D Data Register bit 5 |
.equ PD5 = 5 ; For compatibility |
.equ PORTD6 = 6 ; Port D Data Register bit 6 |
.equ PD6 = 6 ; For compatibility |
.equ PORTD7 = 7 ; Port D Data Register bit 7 |
.equ PD7 = 7 ; For compatibility |
; DDRD - Port D Data Direction Register |
.equ DDD0 = 0 ; Port D Data Direction Register bit 0 |
.equ DDD1 = 1 ; Port D Data Direction Register bit 1 |
.equ DDD2 = 2 ; Port D Data Direction Register bit 2 |
.equ DDD3 = 3 ; Port D Data Direction Register bit 3 |
.equ DDD4 = 4 ; Port D Data Direction Register bit 4 |
.equ DDD5 = 5 ; Port D Data Direction Register bit 5 |
.equ DDD6 = 6 ; Port D Data Direction Register bit 6 |
.equ DDD7 = 7 ; Port D Data Direction Register bit 7 |
; PIND - Port D Input Pins |
.equ PIND0 = 0 ; Port D Input Pins bit 0 |
.equ PIND1 = 1 ; Port D Input Pins bit 1 |
.equ PIND2 = 2 ; Port D Input Pins bit 2 |
.equ PIND3 = 3 ; Port D Input Pins bit 3 |
.equ PIND4 = 4 ; Port D Input Pins bit 4 |
.equ PIND5 = 5 ; Port D Input Pins bit 5 |
.equ PIND6 = 6 ; Port D Input Pins bit 6 |
.equ PIND7 = 7 ; Port D Input Pins bit 7 |
; ***** ANALOG_COMPARATOR ************ |
; ADCSRB - ADC Control and Status Register B |
.equ ACME = 6 ; Analog Comparator Multiplexer Enable |
; ACSR - Analog Comparator Control And Status Register |
.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 |
.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 |
.equ ACIC = 2 ; Analog Comparator Input Capture Enable |
.equ ACIE = 3 ; Analog Comparator Interrupt Enable |
.equ ACI = 4 ; Analog Comparator Interrupt Flag |
.equ ACO = 5 ; Analog Compare Output |
.equ ACBG = 6 ; Analog Comparator Bandgap Select |
.equ ACD = 7 ; Analog Comparator Disable |
; DIDR1 - Digital Input Disable Register 1 |
.equ AIN0D = 0 ; AIN0 Digital Input Disable |
.equ AIN1D = 1 ; AIN1 Digital Input Disable |
; ***** PORTE ************************ |
; PORTE - Data Register, Port E |
.equ PORTE0 = 0 ; |
.equ PE0 = 0 ; For compatibility |
.equ PORTE1 = 1 ; |
.equ PE1 = 1 ; For compatibility |
.equ PORTE2 = 2 ; |
.equ PE2 = 2 ; For compatibility |
.equ PORTE3 = 3 ; |
.equ PE3 = 3 ; For compatibility |
.equ PORTE4 = 4 ; |
.equ PE4 = 4 ; For compatibility |
.equ PORTE5 = 5 ; |
.equ PE5 = 5 ; For compatibility |
.equ PORTE6 = 6 ; |
.equ PE6 = 6 ; For compatibility |
.equ PORTE7 = 7 ; |
.equ PE7 = 7 ; For compatibility |
; DDRE - Data Direction Register, Port E |
.equ DDE0 = 0 ; |
.equ DDE1 = 1 ; |
.equ DDE2 = 2 ; |
.equ DDE3 = 3 ; |
.equ DDE4 = 4 ; |
.equ DDE5 = 5 ; |
.equ DDE6 = 6 ; |
.equ DDE7 = 7 ; |
; PINE - Input Pins, Port E |
.equ PINE0 = 0 ; |
.equ PINE1 = 1 ; |
.equ PINE2 = 2 ; |
.equ PINE3 = 3 ; |
.equ PINE4 = 4 ; |
.equ PINE5 = 5 ; |
.equ PINE6 = 6 ; |
.equ PINE7 = 7 ; |
; ***** PORTF ************************ |
; PORTF - Data Register, Port F |
.equ PORTF0 = 0 ; |
.equ PF0 = 0 ; For compatibility |
.equ PORTF1 = 1 ; |
.equ PF1 = 1 ; For compatibility |
.equ PORTF2 = 2 ; |
.equ PF2 = 2 ; For compatibility |
.equ PORTF3 = 3 ; |
.equ PF3 = 3 ; For compatibility |
.equ PORTF4 = 4 ; |
.equ PF4 = 4 ; For compatibility |
.equ PORTF5 = 5 ; |
.equ PF5 = 5 ; For compatibility |
.equ PORTF6 = 6 ; |
.equ PF6 = 6 ; For compatibility |
.equ PORTF7 = 7 ; |
.equ PF7 = 7 ; For compatibility |
; DDRF - Data Direction Register, Port F |
.equ DDF0 = 0 ; |
.equ DDF1 = 1 ; |
.equ DDF2 = 2 ; |
.equ DDF3 = 3 ; |
.equ DDF4 = 4 ; |
.equ DDF5 = 5 ; |
.equ DDF6 = 6 ; |
.equ DDF7 = 7 ; |
; PINF - Input Pins, Port F |
.equ PINF0 = 0 ; |
.equ PINF1 = 1 ; |
.equ PINF2 = 2 ; |
.equ PINF3 = 3 ; |
.equ PINF4 = 4 ; |
.equ PINF5 = 5 ; |
.equ PINF6 = 6 ; |
.equ PINF7 = 7 ; |
; ***** PORTG ************************ |
; PORTG - Port G Data Register |
.equ PORTG0 = 0 ; |
.equ PG0 = 0 ; For compatibility |
.equ PORTG1 = 1 ; |
.equ PG1 = 1 ; For compatibility |
.equ PORTG2 = 2 ; |
.equ PG2 = 2 ; For compatibility |
.equ PORTG3 = 3 ; |
.equ PG3 = 3 ; For compatibility |
.equ PORTG4 = 4 ; |
.equ PG4 = 4 ; For compatibility |
; DDRG - Port G Data Direction Register |
.equ DDG0 = 0 ; |
.equ DDG1 = 1 ; |
.equ DDG2 = 2 ; |
.equ DDG3 = 3 ; |
.equ DDG4 = 4 ; |
; PING - Port G Input Pins |
.equ PING0 = 0 ; |
.equ PING1 = 1 ; |
.equ PING2 = 2 ; |
.equ PING3 = 3 ; |
.equ PING4 = 4 ; |
.equ PING5 = 5 ; |
; ***** JTAG ************************* |
; OCDR - On-Chip Debug Related Register in I/O Memory |
.equ OCDR0 = 0 ; On-Chip Debug Register Bit 0 |
.equ OCDR1 = 1 ; On-Chip Debug Register Bit 1 |
.equ OCDR2 = 2 ; On-Chip Debug Register Bit 2 |
.equ OCDR3 = 3 ; On-Chip Debug Register Bit 3 |
.equ OCDR4 = 4 ; On-Chip Debug Register Bit 4 |
.equ OCDR5 = 5 ; On-Chip Debug Register Bit 5 |
.equ OCDR6 = 6 ; On-Chip Debug Register Bit 6 |
.equ OCDR7 = 7 ; On-Chip Debug Register Bit 7 |
.equ IDRD = OCDR7 ; For compatibility |
; MCUCR - MCU Control Register |
.equ JTD = 7 ; JTAG Interface Disable |
; MCUSR - MCU Status Register |
.equ JTRF = 4 ; JTAG Reset Flag |
; ***** MISC ************************* |
; LCDCRA - LCD Control Register A |
.equ LCDBL = 0 ; LCD Blanking |
.equ LCDIE = 3 ; LCD Interrupt Enable |
.equ LCDIF = 4 ; LCD Interrupt Flag |
.equ LCDAB = 6 ; LCD A or B waveform |
.equ LCDEN = 7 ; LCD Enable |
; LCDCRB - LCD Control and Status Register B |
.equ LCDPM0 = 0 ; LCD Port Mask 0 |
.equ LCDPM1 = 1 ; LCD Port Mask 1 |
.equ LCDPM2 = 2 ; LCD Port Mask 2 |
.equ LCDMUX0 = 4 ; LCD Mux Select 0 |
.equ LCDMUX1 = 5 ; LCD Mux Select 1 |
.equ LCD2B = 6 ; LCD 1/2 Bias Select |
.equ LCDCS = 7 ; LCD CLock Select |
; LCDFRR - LCD Frame Rate Register |
.equ LCDCD0 = 0 ; LCD Clock Divider 0 |
.equ LCDCD1 = 1 ; LCD Clock Divider 1 |
.equ LCDCD2 = 2 ; LCD Clock Divider 2 |
.equ LCDPS0 = 4 ; LCD Prescaler Select 0 |
.equ LCDPS1 = 5 ; LCD Prescaler Select 1 |
.equ LCDPS2 = 6 ; LCD Prescaler Select 2 |
; LCDCCR - LCD Contrast Control Register |
.equ LCDCC0 = 0 ; LCD Contrast Control 0 |
.equ LCDCC1 = 1 ; LCD Contrast Control 1 |
.equ LCDCC2 = 2 ; LCD Contrast Control 2 |
.equ LCDCC3 = 3 ; LCD Contrast Control 3 |
.equ LCDDC0 = 5 ; LCD Display Configuration Bit 0 |
.equ LCDDC1 = 6 ; LCD Display Configuration Bit 1 |
.equ LCDDC2 = 7 ; LCD Display Configuration Bit 2 |
; LCDDR18 - LCD Data Register 18 |
.equ SEG324 = 0 ; |
; LCDDR17 - LCD Data Register 17 |
.equ SEG316 = 0 ; |
.equ SEG317 = 1 ; |
.equ SEG318 = 2 ; |
.equ SEG319 = 3 ; |
.equ SEG320 = 4 ; |
.equ SEG321 = 5 ; |
.equ SEG322 = 6 ; |
.equ SEG323 = 7 ; |
; LCDDR16 - LCD Data Register 16 |
.equ SEG308 = 0 ; |
.equ SEG309 = 1 ; |
.equ SEG310 = 2 ; |
.equ SEG311 = 3 ; |
.equ SEG312 = 4 ; |
.equ SEG313 = 5 ; |
.equ SEG314 = 6 ; |
.equ SEG315 = 7 ; |
; LCDDR15 - LCD Data Register 15 |
.equ SEG300 = 0 ; |
.equ SEG301 = 1 ; |
.equ SEG302 = 2 ; |
.equ SEG303 = 3 ; |
.equ SEG304 = 4 ; |
.equ SEG305 = 5 ; |
.equ SEG306 = 6 ; |
.equ SEG307 = 7 ; |
; LCDDR13 - LCD Data Register 13 |
.equ SEG224 = 0 ; |
; LCDDR12 - LCD Data Register 12 |
.equ SEG216 = 0 ; |
.equ SEG217 = 1 ; |
.equ SEG218 = 2 ; |
.equ SEG219 = 3 ; |
.equ SEG220 = 4 ; |
.equ SEG221 = 5 ; |
.equ SEG222 = 6 ; |
.equ SEG223 = 7 ; |
; LCDDR11 - LCD Data Register 11 |
.equ SEG208 = 0 ; |
.equ SEG209 = 1 ; |
.equ SEG210 = 2 ; |
.equ SEG211 = 3 ; |
.equ SEG212 = 4 ; |
.equ SEG213 = 5 ; |
.equ SEG214 = 6 ; |
.equ SEG215 = 7 ; |
; LCDDR10 - LCD Data Register 10 |
.equ SEG200 = 0 ; |
.equ SEG201 = 1 ; |
.equ SEG202 = 2 ; |
.equ SEG203 = 3 ; |
.equ SEG204 = 4 ; |
.equ SEG205 = 5 ; |
.equ SEG206 = 6 ; |
.equ SEG207 = 7 ; |
; LCDDR8 - LCD Data Register 8 |
.equ SEG124 = 0 ; |
; LCDDR7 - LCD Data Register 7 |
.equ SEG116 = 0 ; |
.equ SEG117 = 1 ; |
.equ SEG118 = 2 ; |
.equ SEG119 = 3 ; |
.equ SEG120 = 4 ; |
.equ SEG121 = 5 ; |
.equ SEG122 = 6 ; |
.equ SEG123 = 7 ; |
; LCDDR6 - LCD Data Register 6 |
.equ SEG108 = 0 ; |
.equ SEG109 = 1 ; |
.equ SEG110 = 2 ; |
.equ SEG111 = 3 ; |
.equ SEG112 = 4 ; |
.equ SEG113 = 5 ; |
.equ SEG114 = 6 ; |
.equ SEG115 = 7 ; |
; LCDDR5 - LCD Data Register 5 |
.equ SEG100 = 0 ; |
.equ SEG101 = 1 ; |
.equ SEG102 = 2 ; |
.equ SEG103 = 3 ; |
.equ SEG104 = 4 ; |
.equ SEG105 = 5 ; |
.equ SEG106 = 6 ; |
.equ SEG107 = 7 ; |
; LCDDR3 - LCD Data Register 3 |
.equ SEG024 = 0 ; |
; LCDDR2 - LCD Data Register 2 |
.equ SEG016 = 0 ; |
.equ SEG017 = 1 ; |
.equ SEG018 = 2 ; |
.equ SEG019 = 3 ; |
.equ SEG020 = 4 ; |
.equ SEG021 = 5 ; |
.equ SEG022 = 6 ; |
.equ SEG023 = 7 ; |
; LCDDR1 - LCD Data Register 1 |
.equ SEG008 = 0 ; |
.equ SEG009 = 1 ; |
.equ SEG010 = 2 ; |
.equ SEG011 = 3 ; |
.equ SEG012 = 4 ; |
.equ SEG013 = 5 ; |
.equ SEG014 = 6 ; |
.equ SEG015 = 7 ; |
; LCDDR0 - LCD Data Register 0 |
.equ SEG000 = 0 ; |
.equ SEG001 = 1 ; |
.equ SEG002 = 2 ; |
.equ SEG003 = 3 ; |
.equ SEG004 = 4 ; |
.equ SEG005 = 5 ; |
.equ SEG006 = 6 ; |
.equ SEG007 = 7 ; |
; ***** EXTERNAL_INTERRUPT *********** |
; EICRA - External Interrupt Control Register |
.equ ISC00 = 0 ; External Interrupt Sense Control 0 Bit 0 |
.equ ISC01 = 1 ; External Interrupt Sense Control 0 Bit 1 |
; EIMSK - External Interrupt Mask Register |
.equ INT0 = 0 ; External Interrupt Request 0 Enable |
.equ PCIE0 = 6 ; Pin Change Interrupt Enable 0 |
.equ PCIE1 = 7 ; Pin Change Interrupt Enable 1 |
; EIFR - External Interrupt Flag Register |
.equ INTF0 = 0 ; External Interrupt Flag 0 |
.equ PCIF0 = 6 ; Pin Change Interrupt Flag 0 |
.equ PCIF1 = 7 ; Pin Change Interrupt Flag 1 |
; PCMSK1 - Pin Change Mask Register 1 |
.equ PCINT8 = 0 ; Pin Change Enable Mask 8 |
.equ PCINT9 = 1 ; Pin Change Enable Mask 9 |
.equ PCINT10 = 2 ; Pin Change Enable Mask 10 |
.equ PCINT11 = 3 ; Pin Change Enable Mask 11 |
.equ PCINT12 = 4 ; Pin Change Enable Mask 12 |
.equ PCINT13 = 5 ; Pin Change Enable Mask 13 |
.equ PCINT14 = 6 ; Pin Change Enable Mask 14 |
.equ PCINT15 = 7 ; Pin Change Enable Mask 15 |
; PCMSK0 - Pin Change Mask Register 0 |
.equ PCINT0 = 0 ; Pin Change Enable Mask 0 |
.equ PCINT1 = 1 ; Pin Change Enable Mask 1 |
.equ PCINT2 = 2 ; Pin Change Enable Mask 2 |
.equ PCINT3 = 3 ; Pin Change Enable Mask 3 |
.equ PCINT4 = 4 ; Pin Change Enable Mask 4 |
.equ PCINT5 = 5 ; Pin Change Enable Mask 5 |
.equ PCINT6 = 6 ; Pin Change Enable Mask 6 |
.equ PCINT7 = 7 ; Pin Change Enable Mask 7 |
; ***** CPU ************************** |
; SREG - Status Register |
.equ SREG_C = 0 ; Carry Flag |
.equ SREG_Z = 1 ; Zero Flag |
.equ SREG_N = 2 ; Negative Flag |
.equ SREG_V = 3 ; Two's Complement Overflow Flag |
.equ SREG_S = 4 ; Sign Bit |
.equ SREG_H = 5 ; Half Carry Flag |
.equ SREG_T = 6 ; Bit Copy Storage |
.equ SREG_I = 7 ; Global Interrupt Enable |
; MCUCR - MCU Control Register |
.equ IVCE = 0 ; Interrupt Vector Change Enable |
.equ IVSEL = 1 ; Interrupt Vector Select |
.equ PUD = 4 ; Pull-up disable |
; MCUSR - MCU Status Register |
.equ PORF = 0 ; Power-on reset flag |
.equ EXTRF = 1 ; External Reset Flag |
.equ BORF = 2 ; Brown-out Reset Flag |
.equ WDRF = 3 ; Watchdog Reset Flag |
;.equ JTRF = 4 ; JTAG Reset Flag |
; OSCCAL - Oscillator Calibration Value |
.equ CAL0 = 0 ; Oscillator Calibration Value Bit0 |
.equ CAL1 = 1 ; Oscillator Calibration Value Bit1 |
.equ CAL2 = 2 ; Oscillator Calibration Value Bit2 |
.equ CAL3 = 3 ; Oscillator Calibration Value Bit3 |
.equ CAL4 = 4 ; Oscillator Calibration Value Bit4 |
.equ CAL5 = 5 ; Oscillator Calibration Value Bit5 |
.equ CAL6 = 6 ; Oscillator Calibration Value Bit6 |
.equ CAL7 = 7 ; Oscillator Calibration Value Bit7 |
; CLKPR - Clock Prescale Register |
.equ CLKPS0 = 0 ; Clock Prescaler Select Bit 0 |
.equ CLKPS1 = 1 ; Clock Prescaler Select Bit 1 |
.equ CLKPS2 = 2 ; Clock Prescaler Select Bit 2 |
.equ CLKPS3 = 3 ; Clock Prescaler Select Bit 3 |
.equ CLKPCE = 7 ; Clock Prescaler Change Enable |
; PRR - Power Reduction Register |
.equ PRADC = 0 ; Power Reduction ADC |
.equ PRUSART0 = 1 ; Power Reduction USART |
.equ PRSPI = 2 ; Power Reduction Serial Peripheral Interface |
.equ PRTIM1 = 3 ; Power Reduction Timer/Counter1 |
.equ PRLCD = 4 ; Power Reduction LCD |
; SMCR - Sleep Mode Control Register |
.equ SE = 0 ; Sleep Enable |
.equ SM0 = 1 ; Sleep Mode Select bit 0 |
.equ SM1 = 2 ; Sleep Mode Select bit 1 |
.equ SM2 = 3 ; Sleep Mode Select bit 2 |
; GPIOR2 - General Purpose IO Register 2 |
.equ GPIOR20 = 0 ; General Purpose IO Register 2 bit 0 |
.equ GPIOR21 = 1 ; General Purpose IO Register 2 bit 1 |
.equ GPIOR22 = 2 ; General Purpose IO Register 2 bit 2 |
.equ GPIOR23 = 3 ; General Purpose IO Register 2 bit 3 |
.equ GPIOR24 = 4 ; General Purpose IO Register 2 bit 4 |
.equ GPIOR25 = 5 ; General Purpose IO Register 2 bit 5 |
.equ GPIOR26 = 6 ; General Purpose IO Register 2 bit 6 |
.equ GPIOR27 = 7 ; General Purpose IO Register 2 bit 7 |
; GPIOR1 - General Purpose IO Register 1 |
.equ GPIOR10 = 0 ; General Purpose IO Register 1 bit 0 |
.equ GPIOR11 = 1 ; General Purpose IO Register 1 bit 1 |
.equ GPIOR12 = 2 ; General Purpose IO Register 1 bit 2 |
.equ GPIOR13 = 3 ; General Purpose IO Register 1 bit 3 |
.equ GPIOR14 = 4 ; General Purpose IO Register 1 bit 4 |
.equ GPIOR15 = 5 ; General Purpose IO Register 1 bit 5 |
.equ GPIOR16 = 6 ; General Purpose IO Register 1 bit 6 |
.equ GPIOR17 = 7 ; General Purpose IO Register 1 bit 7 |
; GPIOR0 - General Purpose IO Register 0 |
.equ GPIOR00 = 0 ; General Purpose IO Register 0 bit 0 |
.equ GPIOR01 = 1 ; General Purpose IO Register 0 bit 1 |
.equ GPIOR02 = 2 ; General Purpose IO Register 0 bit 2 |
.equ GPIOR03 = 3 ; General Purpose IO Register 0 bit 3 |
.equ GPIOR04 = 4 ; General Purpose IO Register 0 bit 4 |
.equ GPIOR05 = 5 ; General Purpose IO Register 0 bit 5 |
.equ GPIOR06 = 6 ; General Purpose IO Register 0 bit 6 |
.equ GPIOR07 = 7 ; General Purpose IO Register 0 bit 7 |
; ***** USI ************************** |
; USIDR - USI Data Register |
.equ USIDR0 = 0 ; USI Data Register bit 0 |
.equ USIDR1 = 1 ; USI Data Register bit 1 |
.equ USIDR2 = 2 ; USI Data Register bit 2 |
.equ USIDR3 = 3 ; USI Data Register bit 3 |
.equ USIDR4 = 4 ; USI Data Register bit 4 |
.equ USIDR5 = 5 ; USI Data Register bit 5 |
.equ USIDR6 = 6 ; USI Data Register bit 6 |
.equ USIDR7 = 7 ; USI Data Register bit 7 |
; USISR - USI Status Register |
.equ USICNT0 = 0 ; USI Counter Value Bit 0 |
.equ USICNT1 = 1 ; USI Counter Value Bit 1 |
.equ USICNT2 = 2 ; USI Counter Value Bit 2 |
.equ USICNT3 = 3 ; USI Counter Value Bit 3 |
.equ USIDC = 4 ; Data Output Collision |
.equ USIPF = 5 ; Stop Condition Flag |
.equ USIOIF = 6 ; Counter Overflow Interrupt Flag |
.equ USISIF = 7 ; Start Condition Interrupt Flag |
; USICR - USI Control Register |
.equ USITC = 0 ; Toggle Clock Port Pin |
.equ USICLK = 1 ; Clock Strobe |
.equ USICS0 = 2 ; USI Clock Source Select Bit 0 |
.equ USICS1 = 3 ; USI Clock Source Select Bit 1 |
.equ USIWM0 = 4 ; USI Wire Mode Bit 0 |
.equ USIWM1 = 5 ; USI Wire Mode Bit 1 |
.equ USIOIE = 6 ; Counter Overflow Interrupt Enable |
.equ USISIE = 7 ; Start Condition Interrupt Enable |
; ***** AD_CONVERTER ***************** |
; ADMUX - The ADC multiplexer Selection Register |
.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits |
.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits |
.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits |
.equ MUX3 = 3 ; Analog Channel and Gain Selection Bits |
.equ MUX4 = 4 ; Analog Channel and Gain Selection Bits |
.equ ADLAR = 5 ; Left Adjust Result |
.equ REFS0 = 6 ; Reference Selection Bit 0 |
.equ REFS1 = 7 ; Reference Selection Bit 1 |
; ADCSRA - The ADC Control and Status register |
.equ ADPS0 = 0 ; ADC Prescaler Select Bits |
.equ ADPS1 = 1 ; ADC Prescaler Select Bits |
.equ ADPS2 = 2 ; ADC Prescaler Select Bits |
.equ ADIE = 3 ; ADC Interrupt Enable |
.equ ADIF = 4 ; ADC Interrupt Flag |
.equ ADATE = 5 ; ADC Auto Trigger Enable |
.equ ADSC = 6 ; ADC Start Conversion |
.equ ADEN = 7 ; ADC Enable |
; ADCH - ADC Data Register High Byte |
.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0 |
.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1 |
.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2 |
.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3 |
.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4 |
.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5 |
.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6 |
.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7 |
; ADCL - ADC Data Register Low Byte |
.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0 |
.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1 |
.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2 |
.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3 |
.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4 |
.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5 |
.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6 |
.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7 |
; ADCSRB - ADC Control and Status Register B |
.equ ADTS0 = 0 ; ADC Auto Trigger Source 0 |
.equ ADTS1 = 1 ; ADC Auto Trigger Source 1 |
.equ ADTS2 = 2 ; ADC Auto Trigger Source 2 |
; DIDR0 - Digital Input Disable Register 0 |
.equ ADC0D = 0 ; ADC0 Digital input Disable |
.equ ADC1D = 1 ; ADC1 Digital input Disable |
.equ ADC2D = 2 ; ADC2 Digital input Disable |
.equ ADC3D = 3 ; ADC3 Digital input Disable |
.equ ADC4D = 4 ; ADC4 Digital input Disable |
.equ ADC5D = 5 ; ADC5 Digital input Disable |
.equ ADC6D = 6 ; ADC6 Digital input Disable |
.equ ADC7D = 7 ; ADC7 Digital input Disable |
; ***** BOOT_LOAD ******************** |
; SPMCSR - Store Program Memory Control Register |
.equ SPMCR = SPMCSR ; For compatibility |
.equ SPMEN = 0 ; Store Program Memory Enable |
.equ PGERS = 1 ; Page Erase |
.equ PGWRT = 2 ; Page Write |
.equ BLBSET = 3 ; Boot Lock Bit Set |
.equ RWWSRE = 4 ; Read While Write section read enable |
.equ ASRE = RWWSRE ; For compatibility |
.equ RWWSB = 6 ; Read While Write Section Busy |
.equ ASB = RWWSB ; For compatibility |
.equ SPMIE = 7 ; SPM Interrupt Enable |
; ***** USART0 *********************** |
; UDR - USART I/O Data Register |
.equ UDR0 = UDR ; For compatibility |
.equ UDR00 = 0 ; USART I/O Data Register bit 0 |
.equ UDR01 = 1 ; USART I/O Data Register bit 1 |
.equ UDR02 = 2 ; USART I/O Data Register bit 2 |
.equ UDR03 = 3 ; USART I/O Data Register bit 3 |
.equ UDR04 = 4 ; USART I/O Data Register bit 4 |
.equ UDR05 = 5 ; USART I/O Data Register bit 5 |
.equ UDR06 = 6 ; USART I/O Data Register bit 6 |
.equ UDR07 = 7 ; USART I/O Data Register bit 7 |
; UCSRA - USART Control and Status Register A |
.equ UCSR0A = UCSRA ; For compatibility |
.equ USR = UCSRA ; For compatibility |
.equ MPCM = 0 ; Multi-processor Communication Mode |
.equ MPCM0 = MPCM ; For compatibility |
.equ U2X = 1 ; Double the USART Transmission Speed |
.equ U2X0 = U2X ; For compatibility |
.equ UPE = 2 ; USART Parity Error |
.equ UPE0 = UPE ; For compatibility |
.equ DOR = 3 ; Data OverRun |
.equ DOR0 = DOR ; For compatibility |
.equ FE = 4 ; Framing Error |
.equ FE0 = FE ; For compatibility |
.equ UDRE = 5 ; USART Data Register Empty |
.equ UDRE0 = UDRE ; For compatibility |
.equ TXC = 6 ; USART Transmit Complete |
.equ TXC0 = TXC ; For compatibility |
.equ RXC = 7 ; USART Receive Complete |
.equ RXC0 = RXC ; For compatibility |
; UCSRB - USART Control and Status Register B |
.equ UCSR0B = UCSRB ; For compatibility |
.equ UCR = UCSRB ; For compatibility |
.equ TXB8 = 0 ; Transmit Data Bit 8 |
.equ TXB80 = TXB8 ; For compatibility |
.equ RXB8 = 1 ; Receive Data Bit 8 |
.equ RXB80 = RXB8 ; For compatibility |
.equ UCSZ2 = 2 ; Character Size |
.equ UCSZ02 = UCSZ2 ; For compatibility |
.equ TXEN = 3 ; Transmitter Enable |
.equ TXEN0 = TXEN ; For compatibility |
.equ RXEN = 4 ; Receiver Enable |
.equ RXEN0 = RXEN ; For compatibility |
.equ UDRIE = 5 ; USART Data Register Empty Interrupt Enable |
.equ UDRIE0 = UDRIE ; For compatibility |
.equ TXCIE = 6 ; TX Complete Interrupt Enable |
.equ TXCIE0 = TXCIE ; For compatibility |
.equ RXCIE = 7 ; RX Complete Interrupt Enable |
.equ RXCIE0 = RXCIE ; For compatibility |
; UCSRC - USART Control and Status Register C |
.equ UCSR0C = UCSRC ; For compatibility |
.equ UCPOL = 0 ; Clock Polarity |
.equ UCPOL0 = UCPOL ; For compatibility |
.equ UCSZ0 = 1 ; Character Size |
.equ UCSZ00 = UCSZ0 ; For compatibility |
.equ UCSZ1 = 2 ; Character Size |
.equ UCSZ01 = UCSZ1 ; For compatibility |
.equ USBS = 3 ; Stop Bit Select |
.equ USBS0 = USBS ; For compatibility |
.equ UPM0 = 4 ; Parity Mode Bit 0 |
.equ UPM00 = UPM0 ; For compatibility |
.equ UPM1 = 5 ; Parity Mode Bit 1 |
.equ UPM01 = UPM1 ; For compatibility |
.equ UMSEL = 6 ; USART Mode Select |
.equ UMSEL0 = UMSEL ; For compatibility |
.equ UBRR0H = UBRRH ; For compatibility |
.equ UBRR0L = UBRRL ; For compatibility |
.equ UBRR0 = UBRRL ; For compatibility |
.equ UBRR = UBRRL ; For compatibility |
; ***** LOCKSBITS ******************************************************** |
.equ LB1 = 0 ; Lock bit |
.equ LB2 = 1 ; Lock bit |
.equ BLB01 = 2 ; Boot Lock bit |
.equ BLB02 = 3 ; Boot Lock bit |
.equ BLB11 = 4 ; Boot lock bit |
.equ BLB12 = 5 ; Boot lock bit |
; ***** FUSES ************************************************************ |
; LOW fuse bits |
.equ CKSEL0 = 0 ; Select Clock Source |
.equ CKSEL1 = 1 ; Select Clock Source |
.equ CKSEL2 = 2 ; Select Clock Source |
.equ CKSEL3 = 3 ; Select Clock Source |
.equ SUT0 = 4 ; Select start-up time |
.equ SUT1 = 5 ; Select start-up time |
.equ CKOUT = 6 ; Oscillator options |
.equ CLKDIV8 = 7 ; Divide clock by 8 |
; HIGH fuse bits |
.equ BOOTRST = 0 ; Select Reset Vector |
.equ BOOTSZ0 = 1 ; Select Boot Size |
.equ BOOTSZ1 = 2 ; Select Boot Size |
.equ EESAVE = 3 ; EEPROM memory is preserved through chip erase |
.equ WDTON = 4 ; Watchdog timer always on |
.equ SPIEN = 5 ; Enable Serial programming and Data Downloading |
.equ JTAGEN = 6 ; Enable JTAG |
.equ OCDEN = 7 ; Enable OCD |
; EXTENDED fuse bits |
.equ RESERVED = 0 ; Reserved for future use |
.equ BODLEVEL0 = 1 ; Brown-out Detector trigger level |
.equ BODLEVEL1 = 2 ; Brown-out Detector trigger level |
.equ BODLEVEL2 = 3 ; Brown out detector trigger level |
; ***** CPU REGISTER DEFINITIONS ***************************************** |
.def XH = r27 |
.def XL = r26 |
.def YH = r29 |
.def YL = r28 |
.def ZH = r31 |
.def ZL = r30 |
; ***** DATA MEMORY DECLARATIONS ***************************************** |
.equ FLASHEND = 0x1fff ; Note: Word address |
.equ IOEND = 0x00ff |
.equ SRAM_START = 0x0100 |
.equ SRAM_SIZE = 1024 |
.equ RAMEND = 0x04ff |
.equ XRAMEND = 0x0000 |
.equ E2END = 0x01ff |
.equ EEPROMEND = 0x01ff |
.equ EEADRBITS = 9 |
#pragma AVRPART MEMORY PROG_FLASH 16384 |
#pragma AVRPART MEMORY EEPROM 512 |
#pragma AVRPART MEMORY INT_SRAM SIZE 1024 |
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x100 |
; ***** BOOTLOADER DECLARATIONS ****************************************** |
.equ NRWW_START_ADDR = 0x1c00 |
.equ NRWW_STOP_ADDR = 0x1fff |
.equ RWW_START_ADDR = 0x0 |
.equ RWW_STOP_ADDR = 0x1bff |
.equ PAGESIZE = 64 |
.equ FIRSTBOOTSTART = 0x1f80 |
.equ SECONDBOOTSTART = 0x1f00 |
.equ THIRDBOOTSTART = 0x1e00 |
.equ FOURTHBOOTSTART = 0x1c00 |
.equ SMALLBOOTSTART = FIRSTBOOTSTART |
.equ LARGEBOOTSTART = FOURTHBOOTSTART |
; ***** INTERRUPT VECTORS ************************************************ |
.equ INT0addr = 0x0002 ; External Interrupt Request 0 |
.equ PCI0addr = 0x0004 ; Pin Change Interrupt Request 0 |
.equ PCI1addr = 0x0006 ; Pin Change Interrupt Request 1 |
.equ OC2addr = 0x0008 ; Timer/Counter2 Compare Match |
.equ OVF2addr = 0x000a ; Timer/Counter2 Overflow |
.equ ICP1addr = 0x000c ; Timer/Counter1 Capture Event |
.equ OC1Aaddr = 0x000e ; Timer/Counter1 Compare Match A |
.equ OC1Baddr = 0x0010 ; Timer/Counter Compare Match B |
.equ OVF1addr = 0x0012 ; Timer/Counter1 Overflow |
.equ OC0addr = 0x0014 ; Timer/Counter0 Compare Match |
.equ OVF0addr = 0x0016 ; Timer/Counter0 Overflow |
.equ SPIaddr = 0x0018 ; SPI Serial Transfer Complete |
.equ URXC0addr = 0x001a ; USART0, Rx Complete |
.equ URXCaddr = 0x001a ; For compatibility |
.equ UDRE0addr = 0x001c ; USART0 Data register Empty |
.equ UDREaddr = 0x001c ; For compatibility |
.equ UTXC0addr = 0x001e ; USART0, Tx Complete |
.equ UTXCaddr = 0x001e ; For compatibility |
.equ USI_STARTaddr = 0x0020 ; USI Start Condition |
.equ USI_OVFaddr = 0x0022 ; USI Overflow |
.equ ACIaddr = 0x0024 ; Analog Comparator |
.equ ADCCaddr = 0x0026 ; ADC Conversion Complete |
.equ ERDYaddr = 0x0028 ; EEPROM Ready |
.equ SPMRaddr = 0x002a ; Store Program Memory Read |
.equ LCDSFaddr = 0x002c ; LCD Start of Frame |
.equ INT_VECTORS_SIZE = 46 ; size in words |
#endif /* _M169DEF_INC_ */ |
; ***** END OF FILE ****************************************************** |
/contrib/toolchain/avra/includes/m16def.inc |
---|
0,0 → 1,863 |
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** |
;***** Created: 2005-01-11 10:30 ******* Source: ATmega16.xml ************ |
;************************************************************************* |
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y |
;* |
;* Number : AVR000 |
;* File Name : "m16def.inc" |
;* Title : Register/Bit Definitions for the ATmega16 |
;* Date : 2005-01-11 |
;* Version : 2.14 |
;* Support E-mail : avr@atmel.com |
;* Target MCU : ATmega16 |
;* |
;* DESCRIPTION |
;* When including this file in the assembly program file, all I/O register |
;* names and I/O register bit names appearing in the data book can be used. |
;* In addition, the six registers forming the three data pointers X, Y and |
;* Z have been assigned names XL - ZH. Highest RAM address for Internal |
;* SRAM is also defined |
;* |
;* The Register names are represented by their hexadecimal address. |
;* |
;* The Register Bit names are represented by their bit number (0-7). |
;* |
;* Please observe the difference in using the bit names with instructions |
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" |
;* (skip if bit in register set/cleared). The following example illustrates |
;* this: |
;* |
;* in r16,PORTB ;read PORTB latch |
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) |
;* out PORTB,r16 ;output to PORTB |
;* |
;* in r16,TIFR ;read the Timer Interrupt Flag Register |
;* sbrc r16,TOV0 ;test the overflow flag (use bit#) |
;* rjmp TOV0_is_set ;jump if set |
;* ... ;otherwise do something else |
;************************************************************************* |
#ifndef _M16DEF_INC_ |
#define _M16DEF_INC_ |
#pragma partinc 0 |
; ***** SPECIFY DEVICE *************************************************** |
.device ATmega16 |
#pragma AVRPART ADMIN PART_NAME ATmega16 |
.equ SIGNATURE_000 = 0x1e |
.equ SIGNATURE_001 = 0x94 |
.equ SIGNATURE_002 = 0x03 |
#pragma AVRPART CORE CORE_VERSION V2E |
; ***** I/O REGISTER DEFINITIONS ***************************************** |
; NOTE: |
; Definitions marked "MEMORY MAPPED"are extended I/O ports |
; and cannot be used with IN/OUT instructions |
.equ SREG = 0x3f |
.equ SPH = 0x3e |
.equ SPL = 0x3d |
.equ OCR0 = 0x3c |
.equ GICR = 0x3b |
.equ GIFR = 0x3a |
.equ TIMSK = 0x39 |
.equ TIFR = 0x38 |
.equ SPMCSR = 0x37 |
.equ TWCR = 0x36 |
.equ MCUCR = 0x35 |
.equ MCUCSR = 0x34 |
.equ TCCR0 = 0x33 |
.equ TCNT0 = 0x32 |
.equ OSCCAL = 0x31 |
.equ OCDR = 0x31 |
.equ SFIOR = 0x30 |
.equ TCCR1A = 0x2f |
.equ TCCR1B = 0x2e |
.equ TCNT1H = 0x2d |
.equ TCNT1L = 0x2c |
.equ OCR1AH = 0x2b |
.equ OCR1AL = 0x2a |
.equ OCR1BH = 0x29 |
.equ OCR1BL = 0x28 |
.equ ICR1H = 0x27 |
.equ ICR1L = 0x26 |
.equ TCCR2 = 0x25 |
.equ TCNT2 = 0x24 |
.equ OCR2 = 0x23 |
.equ ASSR = 0x22 |
.equ WDTCR = 0x21 |
.equ UBRRH = 0x20 |
.equ UCSRC = 0x20 |
.equ EEARH = 0x1f |
.equ EEARL = 0x1e |
.equ EEDR = 0x1d |
.equ EECR = 0x1c |
.equ PORTA = 0x1b |
.equ DDRA = 0x1a |
.equ PINA = 0x19 |
.equ PORTB = 0x18 |
.equ DDRB = 0x17 |
.equ PINB = 0x16 |
.equ PORTC = 0x15 |
.equ DDRC = 0x14 |
.equ PINC = 0x13 |
.equ PORTD = 0x12 |
.equ DDRD = 0x11 |
.equ PIND = 0x10 |
.equ SPDR = 0x0f |
.equ SPSR = 0x0e |
.equ SPCR = 0x0d |
.equ UDR = 0x0c |
.equ UCSRA = 0x0b |
.equ UCSRB = 0x0a |
.equ UBRRL = 0x09 |
.equ ACSR = 0x08 |
.equ ADMUX = 0x07 |
.equ ADCSRA = 0x06 |
.equ ADCH = 0x05 |
.equ ADCL = 0x04 |
.equ TWDR = 0x03 |
.equ TWAR = 0x02 |
.equ TWSR = 0x01 |
.equ TWBR = 0x00 |
; ***** BIT DEFINITIONS ************************************************** |
; ***** TIMER_COUNTER_0 ************** |
; TCCR0 - Timer/Counter Control Register |
.equ CS00 = 0 ; Clock Select 1 |
.equ CS01 = 1 ; Clock Select 1 |
.equ CS02 = 2 ; Clock Select 2 |
.equ WGM01 = 3 ; Waveform Generation Mode 1 |
.equ CTC0 = WGM01 ; For compatibility |
.equ COM00 = 4 ; Compare match Output Mode 0 |
.equ COM01 = 5 ; Compare Match Output Mode 1 |
.equ WGM00 = 6 ; Waveform Generation Mode 0 |
.equ PWM0 = WGM00 ; For compatibility |
.equ FOC0 = 7 ; Force Output Compare |
; TCNT0 - Timer/Counter Register |
.equ TCNT0_0 = 0 ; |
.equ TCNT0_1 = 1 ; |
.equ TCNT0_2 = 2 ; |
.equ TCNT0_3 = 3 ; |
.equ TCNT0_4 = 4 ; |
.equ TCNT0_5 = 5 ; |
.equ TCNT0_6 = 6 ; |
.equ TCNT0_7 = 7 ; |
; OCR0 - Output Compare Register |
.equ OCR0_0 = 0 ; |
.equ OCR0_1 = 1 ; |
.equ OCR0_2 = 2 ; |
.equ OCR0_3 = 3 ; |
.equ OCR0_4 = 4 ; |
.equ OCR0_5 = 5 ; |
.equ OCR0_6 = 6 ; |
.equ OCR0_7 = 7 ; |
; TIMSK - Timer/Counter Interrupt Mask Register |
.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable |
.equ OCIE0 = 1 ; Timer/Counter0 Output Compare Match Interrupt register |
; TIFR - Timer/Counter Interrupt Flag register |
.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag |
.equ OCF0 = 1 ; Output Compare Flag 0 |
; SFIOR - Special Function IO Register |
.equ PSR10 = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0 |
; ***** TIMER_COUNTER_1 ************** |
; TIMSK - Timer/Counter Interrupt Mask Register |
.equ TOIE1 = 2 ; Timer/Counter1 Overflow Interrupt Enable |
.equ OCIE1B = 3 ; Timer/Counter1 Output CompareB Match Interrupt Enable |
.equ OCIE1A = 4 ; Timer/Counter1 Output CompareA Match Interrupt Enable |
.equ TICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable |
; TIFR - Timer/Counter Interrupt Flag register |
.equ TOV1 = 2 ; Timer/Counter1 Overflow Flag |
.equ OCF1B = 3 ; Output Compare Flag 1B |
.equ OCF1A = 4 ; Output Compare Flag 1A |
.equ ICF1 = 5 ; Input Capture Flag 1 |
; TCCR1A - Timer/Counter1 Control Register A |
.equ WGM10 = 0 ; Waveform Generation Mode |
.equ PWM10 = WGM10 ; For compatibility |
.equ WGM11 = 1 ; Waveform Generation Mode |
.equ PWM11 = WGM11 ; For compatibility |
.equ FOC1B = 2 ; Force Output Compare 1B |
.equ FOC1A = 3 ; Force Output Compare 1A |
.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0 |
.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1 |
.equ COM1A0 = 6 ; Comparet Ouput Mode 1A, bit 0 |
.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1 |
; TCCR1B - Timer/Counter1 Control Register B |
.equ CS10 = 0 ; Prescaler source of Timer/Counter 1 |
.equ CS11 = 1 ; Prescaler source of Timer/Counter 1 |
.equ CS12 = 2 ; Prescaler source of Timer/Counter 1 |
.equ WGM12 = 3 ; Waveform Generation Mode |
.equ CTC10 = WGM12 ; For compatibility |
.equ CTC1 = WGM12 ; For compatibility |
.equ WGM13 = 4 ; Waveform Generation Mode |
.equ CTC11 = WGM13 ; For compatibility |
.equ ICES1 = 6 ; Input Capture 1 Edge Select |
.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler |
; ***** EXTERNAL_INTERRUPT *********** |
; GICR - General Interrupt Control Register |
.equ GIMSK = GICR ; For compatibility |
.equ IVCE = 0 ; Interrupt Vector Change Enable |
.equ IVSEL = 1 ; Interrupt Vector Select |
.equ INT2 = 5 ; External Interrupt Request 2 Enable |
.equ INT0 = 6 ; External Interrupt Request 0 Enable |
.equ INT1 = 7 ; External Interrupt Request 1 Enable |
; GIFR - General Interrupt Flag Register |
.equ INTF2 = 5 ; External Interrupt Flag 2 |
.equ INTF0 = 6 ; External Interrupt Flag 0 |
.equ INTF1 = 7 ; External Interrupt Flag 1 |
; MCUCR - General Interrupt Control Register |
.equ ISC00 = 0 ; Interrupt Sense Control 0 Bit 0 |
.equ ISC01 = 1 ; Interrupt Sense Control 0 Bit 1 |
.equ ISC10 = 2 ; Interrupt Sense Control 1 Bit 0 |
.equ ISC11 = 3 ; Interrupt Sense Control 1 Bit 1 |
; MCUCSR - MCU Control And Status Register |
.equ ISC2 = 6 ; Interrupt Sense Control 2 |
; ***** EEPROM *********************** |
; EEDR - EEPROM Data Register |
.equ EEDR0 = 0 ; EEPROM Data Register bit 0 |
.equ EEDR1 = 1 ; EEPROM Data Register bit 1 |
.equ EEDR2 = 2 ; EEPROM Data Register bit 2 |
.equ EEDR3 = 3 ; EEPROM Data Register bit 3 |
.equ EEDR4 = 4 ; EEPROM Data Register bit 4 |
.equ EEDR5 = 5 ; EEPROM Data Register bit 5 |
.equ EEDR6 = 6 ; EEPROM Data Register bit 6 |
.equ EEDR7 = 7 ; EEPROM Data Register bit 7 |
; EECR - EEPROM Control Register |
.equ EERE = 0 ; EEPROM Read Enable |
.equ EEWE = 1 ; EEPROM Write Enable |
.equ EEMWE = 2 ; EEPROM Master Write Enable |
.equ EEWEE = EEMWE ; For compatibility |
.equ EERIE = 3 ; EEPROM Ready Interrupt Enable |
; ***** CPU ************************** |
; SREG - Status Register |
.equ SREG_C = 0 ; Carry Flag |
.equ SREG_Z = 1 ; Zero Flag |
.equ SREG_N = 2 ; Negative Flag |
.equ SREG_V = 3 ; Two's Complement Overflow Flag |
.equ SREG_S = 4 ; Sign Bit |
.equ SREG_H = 5 ; Half Carry Flag |
.equ SREG_T = 6 ; Bit Copy Storage |
.equ SREG_I = 7 ; Global Interrupt Enable |
; MCUCR - MCU Control Register |
;.equ ISC00 = 0 ; Interrupt Sense Control 0 Bit 0 |
;.equ ISC01 = 1 ; Interrupt Sense Control 0 Bit 1 |
;.equ ISC10 = 2 ; Interrupt Sense Control 1 Bit 0 |
;.equ ISC11 = 3 ; Interrupt Sense Control 1 Bit 1 |
.equ SM0 = 4 ; Sleep Mode Select |
.equ SM1 = 5 ; Sleep Mode Select |
.equ SE = 6 ; Sleep Enable |
.equ SM2 = 7 ; Sleep Mode Select |
; MCUCSR - MCU Control And Status Register |
.equ MCUSR = MCUCSR ; For compatibility |
.equ PORF = 0 ; Power-on reset flag |
.equ EXTRF = 1 ; External Reset Flag |
.equ EXTREF = EXTRF ; For compatibility |
.equ BORF = 2 ; Brown-out Reset Flag |
.equ WDRF = 3 ; Watchdog Reset Flag |
.equ JTRF = 4 ; JTAG Reset Flag |
.equ JTD = 7 ; JTAG Interface Disable |
; OSCCAL - Oscillator Calibration Value |
.equ CAL0 = 0 ; Oscillator Calibration Value Bit0 |
.equ CAL1 = 1 ; Oscillator Calibration Value Bit1 |
.equ CAL2 = 2 ; Oscillator Calibration Value Bit2 |
.equ CAL3 = 3 ; Oscillator Calibration Value Bit3 |
.equ CAL4 = 4 ; Oscillator Calibration Value Bit4 |
.equ CAL5 = 5 ; Oscillator Calibration Value Bit5 |
.equ CAL6 = 6 ; Oscillator Calibration Value Bit6 |
.equ CAL7 = 7 ; Oscillator Calibration Value Bit7 |
; SFIOR - Special function I/O register |
;.equ PSR10 = 0 ; Prescaler reset |
.equ PSR2 = 1 ; Prescaler reset |
.equ PUD = 2 ; Pull-up Disable |
.equ ADHSM = 3 ; ADC High Speed Mode |
.equ ADTS0 = 5 ; ADC High Speed Mode |
.equ ADTS1 = 6 ; ADC Auto Trigger Source |
.equ ADTS2 = 7 ; ADC Auto Trigger Source |
; ***** TIMER_COUNTER_2 ************** |
; TIMSK - Timer/Counter Interrupt Mask register |
.equ TOIE2 = 6 ; Timer/Counter2 Overflow Interrupt Enable |
.equ OCIE2 = 7 ; Timer/Counter2 Output Compare Match Interrupt Enable |
; TIFR - Timer/Counter Interrupt Flag Register |
.equ TOV2 = 6 ; Timer/Counter2 Overflow Flag |
.equ OCF2 = 7 ; Output Compare Flag 2 |
; TCCR2 - Timer/Counter2 Control Register |
.equ CS20 = 0 ; Clock Select bit 0 |
.equ CS21 = 1 ; Clock Select bit 1 |
.equ CS22 = 2 ; Clock Select bit 2 |
.equ WGM21 = 3 ; Waveform Generation Mode |
.equ CTC2 = WGM21 ; For compatibility |
.equ COM20 = 4 ; Compare Output Mode bit 0 |
.equ COM21 = 5 ; Compare Output Mode bit 1 |
.equ WGM20 = 6 ; Waveform Genration Mode |
.equ PWM2 = WGM20 ; For compatibility |
.equ FOC2 = 7 ; Force Output Compare |
; TCNT2 - Timer/Counter2 |
.equ TCNT2_0 = 0 ; Timer/Counter 2 bit 0 |
.equ TCNT2_1 = 1 ; Timer/Counter 2 bit 1 |
.equ TCNT2_2 = 2 ; Timer/Counter 2 bit 2 |
.equ TCNT2_3 = 3 ; Timer/Counter 2 bit 3 |
.equ TCNT2_4 = 4 ; Timer/Counter 2 bit 4 |
.equ TCNT2_5 = 5 ; Timer/Counter 2 bit 5 |
.equ TCNT2_6 = 6 ; Timer/Counter 2 bit 6 |
.equ TCNT2_7 = 7 ; Timer/Counter 2 bit 7 |
; OCR2 - Timer/Counter2 Output Compare Register |
.equ OCR2_0 = 0 ; Timer/Counter2 Output Compare Register Bit 0 |
.equ OCR2_1 = 1 ; Timer/Counter2 Output Compare Register Bit 1 |
.equ OCR2_2 = 2 ; Timer/Counter2 Output Compare Register Bit 2 |
.equ OCR2_3 = 3 ; Timer/Counter2 Output Compare Register Bit 3 |
.equ OCR2_4 = 4 ; Timer/Counter2 Output Compare Register Bit 4 |
.equ OCR2_5 = 5 ; Timer/Counter2 Output Compare Register Bit 5 |
.equ OCR2_6 = 6 ; Timer/Counter2 Output Compare Register Bit 6 |
.equ OCR2_7 = 7 ; Timer/Counter2 Output Compare Register Bit 7 |
; ASSR - Asynchronous Status Register |
.equ TCR2UB = 0 ; Timer/counter Control Register2 Update Busy |
.equ OCR2UB = 1 ; Output Compare Register2 Update Busy |
.equ TCN2UB = 2 ; Timer/Counter2 Update Busy |
.equ AS2 = 3 ; Asynchronous Timer/counter2 |
; SFIOR - Special Function IO Register |
;.equ PSR2 = 1 ; Prescaler Reset Timer/Counter2 |
; ***** SPI ************************** |
; SPDR - SPI Data Register |
.equ SPDR0 = 0 ; SPI Data Register bit 0 |
.equ SPDR1 = 1 ; SPI Data Register bit 1 |
.equ SPDR2 = 2 ; SPI Data Register bit 2 |
.equ SPDR3 = 3 ; SPI Data Register bit 3 |
.equ SPDR4 = 4 ; SPI Data Register bit 4 |
.equ SPDR5 = 5 ; SPI Data Register bit 5 |
.equ SPDR6 = 6 ; SPI Data Register bit 6 |
.equ SPDR7 = 7 ; SPI Data Register bit 7 |
; SPSR - SPI Status Register |
.equ SPI2X = 0 ; Double SPI Speed Bit |
.equ WCOL = 6 ; Write Collision Flag |
.equ SPIF = 7 ; SPI Interrupt Flag |
; SPCR - SPI Control Register |
.equ SPR0 = 0 ; SPI Clock Rate Select 0 |
.equ SPR1 = 1 ; SPI Clock Rate Select 1 |
.equ CPHA = 2 ; Clock Phase |
.equ CPOL = 3 ; Clock polarity |
.equ MSTR = 4 ; Master/Slave Select |
.equ DORD = 5 ; Data Order |
.equ SPE = 6 ; SPI Enable |
.equ SPIE = 7 ; SPI Interrupt Enable |
; ***** USART ************************ |
; UDR - USART I/O Data Register |
.equ UDR0 = 0 ; USART I/O Data Register bit 0 |
.equ UDR1 = 1 ; USART I/O Data Register bit 1 |
.equ UDR2 = 2 ; USART I/O Data Register bit 2 |
.equ UDR3 = 3 ; USART I/O Data Register bit 3 |
.equ UDR4 = 4 ; USART I/O Data Register bit 4 |
.equ UDR5 = 5 ; USART I/O Data Register bit 5 |
.equ UDR6 = 6 ; USART I/O Data Register bit 6 |
.equ UDR7 = 7 ; USART I/O Data Register bit 7 |
; UCSRA - USART Control and Status Register A |
.equ USR = UCSRA ; For compatibility |
.equ MPCM = 0 ; Multi-processor Communication Mode |
.equ U2X = 1 ; Double the USART transmission speed |
.equ UPE = 2 ; Parity Error |
.equ PE = UPE ; For compatibility |
.equ DOR = 3 ; Data overRun |
.equ FE = 4 ; Framing Error |
.equ UDRE = 5 ; USART Data Register Empty |
.equ TXC = 6 ; USART Transmitt Complete |
.equ RXC = 7 ; USART Receive Complete |
; UCSRB - USART Control and Status Register B |
.equ UCR = UCSRB ; For compatibility |
.equ TXB8 = 0 ; Transmit Data Bit 8 |
.equ RXB8 = 1 ; Receive Data Bit 8 |
.equ UCSZ2 = 2 ; Character Size |
.equ CHR9 = UCSZ2 ; For compatibility |
.equ TXEN = 3 ; Transmitter Enable |
.equ RXEN = 4 ; Receiver Enable |
.equ UDRIE = 5 ; USART Data register Empty Interrupt Enable |
.equ TXCIE = 6 ; TX Complete Interrupt Enable |
.equ RXCIE = 7 ; RX Complete Interrupt Enable |
; UCSRC - USART Control and Status Register C |
.equ UCPOL = 0 ; Clock Polarity |
.equ UCSZ0 = 1 ; Character Size |
.equ UCSZ1 = 2 ; Character Size |
.equ USBS = 3 ; Stop Bit Select |
.equ UPM0 = 4 ; Parity Mode Bit 0 |
.equ UPM1 = 5 ; Parity Mode Bit 1 |
.equ UMSEL = 6 ; USART Mode Select |
.equ URSEL = 7 ; Register Select |
.equ UBRRHI = UBRRH ; For compatibility |
; ***** TWI ************************** |
; TWBR - TWI Bit Rate register |
.equ I2BR = TWBR ; For compatibility |
.equ TWBR0 = 0 ; |
.equ TWBR1 = 1 ; |
.equ TWBR2 = 2 ; |
.equ TWBR3 = 3 ; |
.equ TWBR4 = 4 ; |
.equ TWBR5 = 5 ; |
.equ TWBR6 = 6 ; |
.equ TWBR7 = 7 ; |
; TWCR - TWI Control Register |
.equ I2CR = TWCR ; For compatibility |
.equ TWIE = 0 ; TWI Interrupt Enable |
.equ I2IE = TWIE ; For compatibility |
.equ TWEN = 2 ; TWI Enable Bit |
.equ I2EN = TWEN ; For compatibility |
.equ ENI2C = TWEN ; For compatibility |
.equ TWWC = 3 ; TWI Write Collition Flag |
.equ I2WC = TWWC ; For compatibility |
.equ TWSTO = 4 ; TWI Stop Condition Bit |
.equ I2STO = TWSTO ; For compatibility |
.equ TWSTA = 5 ; TWI Start Condition Bit |
.equ I2STA = TWSTA ; For compatibility |
.equ TWEA = 6 ; TWI Enable Acknowledge Bit |
.equ I2EA = TWEA ; For compatibility |
.equ TWINT = 7 ; TWI Interrupt Flag |
.equ I2INT = TWINT ; For compatibility |
; TWSR - TWI Status Register |
.equ I2SR = TWSR ; For compatibility |
.equ TWPS0 = 0 ; TWI Prescaler |
.equ TWS0 = TWPS0 ; For compatibility |
.equ I2GCE = TWPS0 ; For compatibility |
.equ TWPS1 = 1 ; TWI Prescaler |
.equ TWS1 = TWPS1 ; For compatibility |
.equ TWS3 = 3 ; TWI Status |
.equ I2S3 = TWS3 ; For compatibility |
.equ TWS4 = 4 ; TWI Status |
.equ I2S4 = TWS4 ; For compatibility |
.equ TWS5 = 5 ; TWI Status |
.equ I2S5 = TWS5 ; For compatibility |
.equ TWS6 = 6 ; TWI Status |
.equ I2S6 = TWS6 ; For compatibility |
.equ TWS7 = 7 ; TWI Status |
.equ I2S7 = TWS7 ; For compatibility |
; TWDR - TWI Data register |
.equ I2DR = TWDR ; For compatibility |
.equ TWD0 = 0 ; TWI Data Register Bit 0 |
.equ TWD1 = 1 ; TWI Data Register Bit 1 |
.equ TWD2 = 2 ; TWI Data Register Bit 2 |
.equ TWD3 = 3 ; TWI Data Register Bit 3 |
.equ TWD4 = 4 ; TWI Data Register Bit 4 |
.equ TWD5 = 5 ; TWI Data Register Bit 5 |
.equ TWD6 = 6 ; TWI Data Register Bit 6 |
.equ TWD7 = 7 ; TWI Data Register Bit 7 |
; TWAR - TWI (Slave) Address register |
.equ I2AR = TWAR ; For compatibility |
.equ TWGCE = 0 ; TWI General Call Recognition Enable Bit |
.equ TWA0 = 1 ; TWI (Slave) Address register Bit 0 |
.equ TWA1 = 2 ; TWI (Slave) Address register Bit 1 |
.equ TWA2 = 3 ; TWI (Slave) Address register Bit 2 |
.equ TWA3 = 4 ; TWI (Slave) Address register Bit 3 |
.equ TWA4 = 5 ; TWI (Slave) Address register Bit 4 |
.equ TWA5 = 6 ; TWI (Slave) Address register Bit 5 |
.equ TWA6 = 7 ; TWI (Slave) Address register Bit 6 |
; ***** ANALOG_COMPARATOR ************ |
; SFIOR - Special Function IO Register |
.equ ACME = 3 ; Analog Comparator Multiplexer Enable |
; ACSR - Analog Comparator Control And Status Register |
.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 |
.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 |
.equ ACIC = 2 ; Analog Comparator Input Capture Enable |
.equ ACIE = 3 ; Analog Comparator Interrupt Enable |
.equ ACI = 4 ; Analog Comparator Interrupt Flag |
.equ ACO = 5 ; Analog Compare Output |
.equ ACBG = 6 ; Analog Comparator Bandgap Select |
.equ ACD = 7 ; Analog Comparator Disable |
; ***** AD_CONVERTER ***************** |
; ADMUX - The ADC multiplexer Selection Register |
.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits |
.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits |
.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits |
.equ MUX3 = 3 ; Analog Channel and Gain Selection Bits |
.equ MUX4 = 4 ; Analog Channel and Gain Selection Bits |
.equ ADLAR = 5 ; Left Adjust Result |
.equ REFS0 = 6 ; Reference Selection Bit 0 |
.equ REFS1 = 7 ; Reference Selection Bit 1 |
; ADCSRA - The ADC Control and Status register |
.equ ADPS0 = 0 ; ADC Prescaler Select Bits |
.equ ADPS1 = 1 ; ADC Prescaler Select Bits |
.equ ADPS2 = 2 ; ADC Prescaler Select Bits |
.equ ADIE = 3 ; ADC Interrupt Enable |
.equ ADIF = 4 ; ADC Interrupt Flag |
.equ ADATE = 5 ; When this bit is written to one,the Timer/Counter2 prescaler will be reset.The bit will be cleared by hardware after the operation is performed.Writing a zero to this bit will have no effect.This bit will always be read as zero if Timer/Counter2 is clocked by the internal CPU clock.If this bit is written when Timer/Counter2 is operating in asynchronous mode,the bit will remain one until the prescaler has been reset. |
.equ ADFR = ADATE ; For compatibility |
.equ ADSC = 6 ; ADC Start Conversion |
.equ ADEN = 7 ; ADC Enable |
; ADCH - ADC Data Register High Byte |
.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0 |
.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1 |
.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2 |
.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3 |
.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4 |
.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5 |
.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6 |
.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7 |
; ADCL - ADC Data Register Low Byte |
.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0 |
.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1 |
.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2 |
.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3 |
.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4 |
.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5 |
.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6 |
.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7 |
; ***** JTAG ************************* |
; OCDR - On-Chip Debug Related Register in I/O Memory |
.equ OCDR0 = 0 ; On-Chip Debug Register Bit 0 |
.equ OCDR1 = 1 ; On-Chip Debug Register Bit 1 |
.equ OCDR2 = 2 ; On-Chip Debug Register Bit 2 |
.equ OCDR3 = 3 ; On-Chip Debug Register Bit 3 |
.equ OCDR4 = 4 ; On-Chip Debug Register Bit 4 |
.equ OCDR5 = 5 ; On-Chip Debug Register Bit 5 |
.equ OCDR6 = 6 ; On-Chip Debug Register Bit 6 |
.equ OCDR7 = 7 ; On-Chip Debug Register Bit 7 |
.equ IDRD = OCDR7 ; For compatibility |
; MCUCSR - MCU Control And Status Register |
;.equ JTRF = 4 ; JTAG Reset Flag |
;.equ JTD = 7 ; JTAG Interface Disable |
; ***** BOOT_LOAD ******************** |
; SPMCSR - Store Program Memory Control Register |
.equ SPMCR = SPMCSR ; For compatibility |
.equ SPMEN = 0 ; Store Program Memory Enable |
.equ PGERS = 1 ; Page Erase |
.equ PGWRT = 2 ; Page Write |
.equ BLBSET = 3 ; Boot Lock Bit Set |
.equ RWWSRE = 4 ; Read While Write section read enable |
.equ ASRE = RWWSRE ; For compatibility |
.equ RWWSB = 6 ; Read While Write Section Busy |
.equ ASB = RWWSB ; For compatibility |
.equ SPMIE = 7 ; SPM Interrupt Enable |
; ***** PORTA ************************ |
; PORTA - Port A Data Register |
.equ PORTA0 = 0 ; Port A Data Register bit 0 |
.equ PA0 = 0 ; For compatibility |
.equ PORTA1 = 1 ; Port A Data Register bit 1 |
.equ PA1 = 1 ; For compatibility |
.equ PORTA2 = 2 ; Port A Data Register bit 2 |
.equ PA2 = 2 ; For compatibility |
.equ PORTA3 = 3 ; Port A Data Register bit 3 |
.equ PA3 = 3 ; For compatibility |
.equ PORTA4 = 4 ; Port A Data Register bit 4 |
.equ PA4 = 4 ; For compatibility |
.equ PORTA5 = 5 ; Port A Data Register bit 5 |
.equ PA5 = 5 ; For compatibility |
.equ PORTA6 = 6 ; Port A Data Register bit 6 |
.equ PA6 = 6 ; For compatibility |
.equ PORTA7 = 7 ; Port A Data Register bit 7 |
.equ PA7 = 7 ; For compatibility |
; DDRA - Port A Data Direction Register |
.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0 |
.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1 |
.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2 |
.equ DDA3 = 3 ; Data Direction Register, Port A, bit 3 |
.equ DDA4 = 4 ; Data Direction Register, Port A, bit 4 |
.equ DDA5 = 5 ; Data Direction Register, Port A, bit 5 |
.equ DDA6 = 6 ; Data Direction Register, Port A, bit 6 |
.equ DDA7 = 7 ; Data Direction Register, Port A, bit 7 |
; PINA - Port A Input Pins |
.equ PINA0 = 0 ; Input Pins, Port A bit 0 |
.equ PINA1 = 1 ; Input Pins, Port A bit 1 |
.equ PINA2 = 2 ; Input Pins, Port A bit 2 |
.equ PINA3 = 3 ; Input Pins, Port A bit 3 |
.equ PINA4 = 4 ; Input Pins, Port A bit 4 |
.equ PINA5 = 5 ; Input Pins, Port A bit 5 |
.equ PINA6 = 6 ; Input Pins, Port A bit 6 |
.equ PINA7 = 7 ; Input Pins, Port A bit 7 |
; ***** PORTB ************************ |
; PORTB - Port B Data Register |
.equ PORTB0 = 0 ; Port B Data Register bit 0 |
.equ PB0 = 0 ; For compatibility |
.equ PORTB1 = 1 ; Port B Data Register bit 1 |
.equ PB1 = 1 ; For compatibility |
.equ PORTB2 = 2 ; Port B Data Register bit 2 |
.equ PB2 = 2 ; For compatibility |
.equ PORTB3 = 3 ; Port B Data Register bit 3 |
.equ PB3 = 3 ; For compatibility |
.equ PORTB4 = 4 ; Port B Data Register bit 4 |
.equ PB4 = 4 ; For compatibility |
.equ PORTB5 = 5 ; Port B Data Register bit 5 |
.equ PB5 = 5 ; For compatibility |
.equ PORTB6 = 6 ; Port B Data Register bit 6 |
.equ PB6 = 6 ; For compatibility |
.equ PORTB7 = 7 ; Port B Data Register bit 7 |
.equ PB7 = 7 ; For compatibility |
; DDRB - Port B Data Direction Register |
.equ DDB0 = 0 ; Port B Data Direction Register bit 0 |
.equ DDB1 = 1 ; Port B Data Direction Register bit 1 |
.equ DDB2 = 2 ; Port B Data Direction Register bit 2 |
.equ DDB3 = 3 ; Port B Data Direction Register bit 3 |
.equ DDB4 = 4 ; Port B Data Direction Register bit 4 |
.equ DDB5 = 5 ; Port B Data Direction Register bit 5 |
.equ DDB6 = 6 ; Port B Data Direction Register bit 6 |
.equ DDB7 = 7 ; Port B Data Direction Register bit 7 |
; PINB - Port B Input Pins |
.equ PINB0 = 0 ; Port B Input Pins bit 0 |
.equ PINB1 = 1 ; Port B Input Pins bit 1 |
.equ PINB2 = 2 ; Port B Input Pins bit 2 |
.equ PINB3 = 3 ; Port B Input Pins bit 3 |
.equ PINB4 = 4 ; Port B Input Pins bit 4 |
.equ PINB5 = 5 ; Port B Input Pins bit 5 |
.equ PINB6 = 6 ; Port B Input Pins bit 6 |
.equ PINB7 = 7 ; Port B Input Pins bit 7 |
; ***** PORTC ************************ |
; PORTC - Port C Data Register |
.equ PORTC0 = 0 ; Port C Data Register bit 0 |
.equ PC0 = 0 ; For compatibility |
.equ PORTC1 = 1 ; Port C Data Register bit 1 |
.equ PC1 = 1 ; For compatibility |
.equ PORTC2 = 2 ; Port C Data Register bit 2 |
.equ PC2 = 2 ; For compatibility |
.equ PORTC3 = 3 ; Port C Data Register bit 3 |
.equ PC3 = 3 ; For compatibility |
.equ PORTC4 = 4 ; Port C Data Register bit 4 |
.equ PC4 = 4 ; For compatibility |
.equ PORTC5 = 5 ; Port C Data Register bit 5 |
.equ PC5 = 5 ; For compatibility |
.equ PORTC6 = 6 ; Port C Data Register bit 6 |
.equ PC6 = 6 ; For compatibility |
.equ PORTC7 = 7 ; Port C Data Register bit 7 |
.equ PC7 = 7 ; For compatibility |
; DDRC - Port C Data Direction Register |
.equ DDC0 = 0 ; Port C Data Direction Register bit 0 |
.equ DDC1 = 1 ; Port C Data Direction Register bit 1 |
.equ DDC2 = 2 ; Port C Data Direction Register bit 2 |
.equ DDC3 = 3 ; Port C Data Direction Register bit 3 |
.equ DDC4 = 4 ; Port C Data Direction Register bit 4 |
.equ DDC5 = 5 ; Port C Data Direction Register bit 5 |
.equ DDC6 = 6 ; Port C Data Direction Register bit 6 |
.equ DDC7 = 7 ; Port C Data Direction Register bit 7 |
; PINC - Port C Input Pins |
.equ PINC0 = 0 ; Port C Input Pins bit 0 |
.equ PINC1 = 1 ; Port C Input Pins bit 1 |
.equ PINC2 = 2 ; Port C Input Pins bit 2 |
.equ PINC3 = 3 ; Port C Input Pins bit 3 |
.equ PINC4 = 4 ; Port C Input Pins bit 4 |
.equ PINC5 = 5 ; Port C Input Pins bit 5 |
.equ PINC6 = 6 ; Port C Input Pins bit 6 |
.equ PINC7 = 7 ; Port C Input Pins bit 7 |
; ***** PORTD ************************ |
; PORTD - Port D Data Register |
.equ PORTD0 = 0 ; Port D Data Register bit 0 |
.equ PD0 = 0 ; For compatibility |
.equ PORTD1 = 1 ; Port D Data Register bit 1 |
.equ PD1 = 1 ; For compatibility |
.equ PORTD2 = 2 ; Port D Data Register bit 2 |
.equ PD2 = 2 ; For compatibility |
.equ PORTD3 = 3 ; Port D Data Register bit 3 |
.equ PD3 = 3 ; For compatibility |
.equ PORTD4 = 4 ; Port D Data Register bit 4 |
.equ PD4 = 4 ; For compatibility |
.equ PORTD5 = 5 ; Port D Data Register bit 5 |
.equ PD5 = 5 ; For compatibility |
.equ PORTD6 = 6 ; Port D Data Register bit 6 |
.equ PD6 = 6 ; For compatibility |
.equ PORTD7 = 7 ; Port D Data Register bit 7 |
.equ PD7 = 7 ; For compatibility |
; DDRD - Port D Data Direction Register |
.equ DDD0 = 0 ; Port D Data Direction Register bit 0 |
.equ DDD1 = 1 ; Port D Data Direction Register bit 1 |
.equ DDD2 = 2 ; Port D Data Direction Register bit 2 |
.equ DDD3 = 3 ; Port D Data Direction Register bit 3 |
.equ DDD4 = 4 ; Port D Data Direction Register bit 4 |
.equ DDD5 = 5 ; Port D Data Direction Register bit 5 |
.equ DDD6 = 6 ; Port D Data Direction Register bit 6 |
.equ DDD7 = 7 ; Port D Data Direction Register bit 7 |
; PIND - Port D Input Pins |
.equ PIND0 = 0 ; Port D Input Pins bit 0 |
.equ PIND1 = 1 ; Port D Input Pins bit 1 |
.equ PIND2 = 2 ; Port D Input Pins bit 2 |
.equ PIND3 = 3 ; Port D Input Pins bit 3 |
.equ PIND4 = 4 ; Port D Input Pins bit 4 |
.equ PIND5 = 5 ; Port D Input Pins bit 5 |
.equ PIND6 = 6 ; Port D Input Pins bit 6 |
.equ PIND7 = 7 ; Port D Input Pins bit 7 |
; ***** WATCHDOG ********************* |
; WDTCR - Watchdog Timer Control Register |
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 |
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 |
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 |
.equ WDE = 3 ; Watch Dog Enable |
.equ WDTOE = 4 ; RW |
.equ WDDE = WDTOE ; For compatibility |
; ***** LOCKSBITS ******************************************************** |
.equ LB1 = 0 ; Lock bit |
.equ LB2 = 1 ; Lock bit |
.equ BLB01 = 2 ; Boot Lock bit |
.equ BLB02 = 3 ; Boot Lock bit |
.equ BLB11 = 4 ; Boot lock bit |
.equ BLB12 = 5 ; Boot lock bit |
; ***** FUSES ************************************************************ |
; LOW fuse bits |
.equ CKSEL0 = 0 ; Select Clock Source |
.equ CKSEL1 = 1 ; Select Clock Source |
.equ CKSEL2 = 2 ; Select Clock Source |
.equ CKSEL3 = 3 ; Select Clock Source |
.equ SUT0 = 4 ; Select start-up time |
.equ SUT1 = 5 ; Select start-up time |
.equ BODEN = 6 ; Brown out detector enable |
.equ BODLEVEL = 7 ; Brown out detector trigger level |
; HIGH fuse bits |
.equ BOOTRST = 0 ; Select Reset Vector |
.equ BOOTSZ0 = 1 ; Select Boot Size |
.equ BOOTSZ1 = 2 ; Select Boot Size |
.equ EESAVE = 3 ; EEPROM memory is preserved through chip erase |
.equ CKOPT = 4 ; Oscillator Options |
.equ SPIEN = 5 ; Enable Serial programming and Data Downloading |
.equ JTAGEN = 6 ; Enable JTAG |
.equ OCDEN = 7 ; Enable OCD |
; ***** CPU REGISTER DEFINITIONS ***************************************** |
.def XH = r27 |
.def XL = r26 |
.def YH = r29 |
.def YL = r28 |
.def ZH = r31 |
.def ZL = r30 |
; ***** DATA MEMORY DECLARATIONS ***************************************** |
.equ FLASHEND = 0x1fff ; Note: Word address |
.equ IOEND = 0x003f |
.equ SRAM_START = 0x0060 |
.equ SRAM_SIZE = 1024 |
.equ RAMEND = 0x045f |
.equ XRAMEND = 0x0000 |
.equ E2END = 0x01ff |
.equ EEPROMEND = 0x01ff |
.equ EEADRBITS = 9 |
#pragma AVRPART MEMORY PROG_FLASH 16384 |
#pragma AVRPART MEMORY EEPROM 512 |
#pragma AVRPART MEMORY INT_SRAM SIZE 1024 |
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60 |
; ***** BOOTLOADER DECLARATIONS ****************************************** |
.equ NRWW_START_ADDR = 0x1c00 |
.equ NRWW_STOP_ADDR = 0x1fff |
.equ RWW_START_ADDR = 0x0 |
.equ RWW_STOP_ADDR = 0x1bff |
.equ PAGESIZE = 64 |
.equ FIRSTBOOTSTART = 0x1f80 |
.equ SECONDBOOTSTART = 0x1f00 |
.equ THIRDBOOTSTART = 0x1e00 |
.equ FOURTHBOOTSTART = 0x1c00 |
.equ SMALLBOOTSTART = FIRSTBOOTSTART |
.equ LARGEBOOTSTART = FOURTHBOOTSTART |
; ***** INTERRUPT VECTORS ************************************************ |
.equ INT0addr = 0x0002 ; External Interrupt Request 0 |
.equ INT1addr = 0x0004 ; External Interrupt Request 1 |
.equ OC2addr = 0x0006 ; Timer/Counter2 Compare Match |
.equ OVF2addr = 0x0008 ; Timer/Counter2 Overflow |
.equ ICP1addr = 0x000a ; Timer/Counter1 Capture Event |
.equ OC1Aaddr = 0x000c ; Timer/Counter1 Compare Match A |
.equ OC1Baddr = 0x000e ; Timer/Counter1 Compare Match B |
.equ OVF1addr = 0x0010 ; Timer/Counter1 Overflow |
.equ OVF0addr = 0x0012 ; Timer/Counter0 Overflow |
.equ SPIaddr = 0x0014 ; Serial Transfer Complete |
.equ URXCaddr = 0x0016 ; USART, Rx Complete |
.equ UDREaddr = 0x0018 ; USART Data Register Empty |
.equ UTXCaddr = 0x001a ; USART, Tx Complete |
.equ ADCCaddr = 0x001c ; ADC Conversion Complete |
.equ ERDYaddr = 0x001e ; EEPROM Ready |
.equ ACIaddr = 0x0020 ; Analog Comparator |
.equ TWIaddr = 0x0022 ; 2-wire Serial Interface |
.equ INT2addr = 0x0024 ; External Interrupt Request 2 |
.equ OC0addr = 0x0026 ; Timer/Counter0 Compare Match |
.equ SPMRaddr = 0x0028 ; Store Program Memory Ready |
.equ INT_VECTORS_SIZE = 42 ; size in words |
#endif /* _M16DEF_INC_ */ |
; ***** END OF FILE ****************************************************** |
/contrib/toolchain/avra/includes/m2560def.inc |
---|
0,0 → 1,1760 |
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** |
;***** Created: 2005-01-11 10:30 ******* Source: ATmega2560.xml ********** |
;************************************************************************* |
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y |
;* |
;* Number : AVR000 |
;* File Name : "m2560def.inc" |
;* Title : Register/Bit Definitions for the ATmega2560 |
;* Date : 2005-01-11 |
;* Version : 2.14 |
;* Support E-mail : avr@atmel.com |
;* Target MCU : ATmega2560 |
;* |
;* DESCRIPTION |
;* When including this file in the assembly program file, all I/O register |
;* names and I/O register bit names appearing in the data book can be used. |
;* In addition, the six registers forming the three data pointers X, Y and |
;* Z have been assigned names XL - ZH. Highest RAM address for Internal |
;* SRAM is also defined |
;* |
;* The Register names are represented by their hexadecimal address. |
;* |
;* The Register Bit names are represented by their bit number (0-7). |
;* |
;* Please observe the difference in using the bit names with instructions |
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" |
;* (skip if bit in register set/cleared). The following example illustrates |
;* this: |
;* |
;* in r16,PORTB ;read PORTB latch |
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) |
;* out PORTB,r16 ;output to PORTB |
;* |
;* in r16,TIFR ;read the Timer Interrupt Flag Register |
;* sbrc r16,TOV0 ;test the overflow flag (use bit#) |
;* rjmp TOV0_is_set ;jump if set |
;* ... ;otherwise do something else |
;************************************************************************* |
#ifndef _M2560DEF_INC_ |
#define _M2560DEF_INC_ |
#pragma partinc 0 |
; ***** SPECIFY DEVICE *************************************************** |
.device ATmega2560 |
#pragma AVRPART ADMIN PART_NAME ATmega2560 |
.equ SIGNATURE_000 = 0x1e |
.equ SIGNATURE_001 = 0x98 |
.equ SIGNATURE_002 = 0x01 |
#pragma AVRPART CORE CORE_VERSION V3 |
; ***** I/O REGISTER DEFINITIONS ***************************************** |
; NOTE: |
; Definitions marked "MEMORY MAPPED"are extended I/O ports |
; and cannot be used with IN/OUT instructions |
.equ UDR3 = 0x136 ; MEMORY MAPPED |
.equ UBRR3H = 0x135 ; MEMORY MAPPED |
.equ UBRR3L = 0x134 ; MEMORY MAPPED |
.equ UCSR3C = 0x132 ; MEMORY MAPPED |
.equ UCSR3B = 0x131 ; MEMORY MAPPED |
.equ UCSR3A = 0x130 ; MEMORY MAPPED |
.equ OCR5CH = 0x12d ; MEMORY MAPPED |
.equ OCR5CL = 0x12c ; MEMORY MAPPED |
.equ OCR5BH = 0x12b ; MEMORY MAPPED |
.equ OCR5BL = 0x12a ; MEMORY MAPPED |
.equ OCR5AH = 0x129 ; MEMORY MAPPED |
.equ OCR5AL = 0x128 ; MEMORY MAPPED |
.equ ICR5H = 0x127 ; MEMORY MAPPED |
.equ ICR5L = 0x126 ; MEMORY MAPPED |
.equ TCNT5H = 0x125 ; MEMORY MAPPED |
.equ TCNT5L = 0x124 ; MEMORY MAPPED |
.equ TCCR5C = 0x122 ; MEMORY MAPPED |
.equ TCCR5B = 0x121 ; MEMORY MAPPED |
.equ TCCR5A = 0x120 ; MEMORY MAPPED |
.equ PORTL = 0x10b ; MEMORY MAPPED |
.equ DDRL = 0x10a ; MEMORY MAPPED |
.equ PINL = 0x109 ; MEMORY MAPPED |
.equ PORTK = 0x108 ; MEMORY MAPPED |
.equ DDRK = 0x107 ; MEMORY MAPPED |
.equ PINK = 0x106 ; MEMORY MAPPED |
.equ PORTJ = 0x105 ; MEMORY MAPPED |
.equ DDRJ = 0x104 ; MEMORY MAPPED |
.equ PINJ = 0x103 ; MEMORY MAPPED |
.equ PORTH = 0x102 ; MEMORY MAPPED |
.equ DDRH = 0x101 ; MEMORY MAPPED |
.equ PINH = 0x100 ; MEMORY MAPPED |
.equ UDR2 = 0xd6 ; MEMORY MAPPED |
.equ UBRR2H = 0xd5 ; MEMORY MAPPED |
.equ UBRR2L = 0xd4 ; MEMORY MAPPED |
.equ UCSR2C = 0xd2 ; MEMORY MAPPED |
.equ UCSR2B = 0xd1 ; MEMORY MAPPED |
.equ UCSR2A = 0xd0 ; MEMORY MAPPED |
.equ UDR1 = 0xce ; MEMORY MAPPED |
.equ UBRR1H = 0xcd ; MEMORY MAPPED |
.equ UBRR1L = 0xcc ; MEMORY MAPPED |
.equ UCSR1C = 0xca ; MEMORY MAPPED |
.equ UCSR1B = 0xc9 ; MEMORY MAPPED |
.equ UCSR1A = 0xc8 ; MEMORY MAPPED |
.equ UDR0 = 0xc6 ; MEMORY MAPPED |
.equ UBRR0H = 0xc5 ; MEMORY MAPPED |
.equ UBRR0L = 0xc4 ; MEMORY MAPPED |
.equ UCSR0C = 0xc2 ; MEMORY MAPPED |
.equ UCSR0B = 0xc1 ; MEMORY MAPPED |
.equ UCSR0A = 0xc0 ; MEMORY MAPPED |
.equ TWAMR = 0xbd ; MEMORY MAPPED |
.equ TWCR = 0xbc ; MEMORY MAPPED |
.equ TWDR = 0xbb ; MEMORY MAPPED |
.equ TWAR = 0xba ; MEMORY MAPPED |
.equ TWSR = 0xb9 ; MEMORY MAPPED |
.equ TWBR = 0xb8 ; MEMORY MAPPED |
.equ ASSR = 0xb6 ; MEMORY MAPPED |
.equ OCR2B = 0xb4 ; MEMORY MAPPED |
.equ OCR2A = 0xb3 ; MEMORY MAPPED |
.equ TCNT2 = 0xb2 ; MEMORY MAPPED |
.equ TCCR2B = 0xb1 ; MEMORY MAPPED |
.equ TCCR2A = 0xb0 ; MEMORY MAPPED |
.equ OCR4CH = 0xad ; MEMORY MAPPED |
.equ OCR4CL = 0xac ; MEMORY MAPPED |
.equ OCR4BH = 0xab ; MEMORY MAPPED |
.equ OCR4BL = 0xaa ; MEMORY MAPPED |
.equ OCR4AH = 0xa9 ; MEMORY MAPPED |
.equ OCR4AL = 0xa8 ; MEMORY MAPPED |
.equ ICR4H = 0xa7 ; MEMORY MAPPED |
.equ ICR4L = 0xa6 ; MEMORY MAPPED |
.equ TCNT4H = 0xa5 ; MEMORY MAPPED |
.equ TCNT4L = 0xa4 ; MEMORY MAPPED |
.equ TCCR4C = 0xa2 ; MEMORY MAPPED |
.equ TCCR4B = 0xa1 ; MEMORY MAPPED |
.equ TCCR4A = 0xa0 ; MEMORY MAPPED |
.equ OCR3CH = 0x9d ; MEMORY MAPPED |
.equ OCR3CL = 0x9c ; MEMORY MAPPED |
.equ OCR3BH = 0x9b ; MEMORY MAPPED |
.equ OCR3BL = 0x9a ; MEMORY MAPPED |
.equ OCR3AH = 0x99 ; MEMORY MAPPED |
.equ OCR3AL = 0x98 ; MEMORY MAPPED |
.equ ICR3H = 0x97 ; MEMORY MAPPED |
.equ ICR3L = 0x96 ; MEMORY MAPPED |
.equ TCNT3H = 0x95 ; MEMORY MAPPED |
.equ TCNT3L = 0x94 ; MEMORY MAPPED |
.equ TCCR3C = 0x92 ; MEMORY MAPPED |
.equ TCCR3B = 0x91 ; MEMORY MAPPED |
.equ TCCR3A = 0x90 ; MEMORY MAPPED |
.equ OCR1CH = 0x8d ; MEMORY MAPPED |
.equ OCR1CL = 0x8c ; MEMORY MAPPED |
.equ OCR1BH = 0x8b ; MEMORY MAPPED |
.equ OCR1BL = 0x8a ; MEMORY MAPPED |
.equ OCR1AH = 0x89 ; MEMORY MAPPED |
.equ OCR1AL = 0x88 ; MEMORY MAPPED |
.equ ICR1H = 0x87 ; MEMORY MAPPED |
.equ ICR1L = 0x86 ; MEMORY MAPPED |
.equ TCNT1H = 0x85 ; MEMORY MAPPED |
.equ TCNT1L = 0x84 ; MEMORY MAPPED |
.equ TCCR1C = 0x82 ; MEMORY MAPPED |
.equ TCCR1B = 0x81 ; MEMORY MAPPED |
.equ TCCR1A = 0x80 ; MEMORY MAPPED |
.equ DIDR1 = 0x7f ; MEMORY MAPPED |
.equ DIDR0 = 0x7e ; MEMORY MAPPED |
.equ DIDR2 = 0x7d ; MEMORY MAPPED |
.equ ADMUX = 0x7c ; MEMORY MAPPED |
.equ ADCSRB = 0x7b ; MEMORY MAPPED |
.equ ADCSRA = 0x7a ; MEMORY MAPPED |
.equ ADCH = 0x79 ; MEMORY MAPPED |
.equ ADCL = 0x78 ; MEMORY MAPPED |
.equ XMCRB = 0x75 ; MEMORY MAPPED |
.equ XMCRA = 0x74 ; MEMORY MAPPED |
.equ TIMSK5 = 0x73 ; MEMORY MAPPED |
.equ TIMSK4 = 0x72 ; MEMORY MAPPED |
.equ TIMSK3 = 0x71 ; MEMORY MAPPED |
.equ TIMSK2 = 0x70 ; MEMORY MAPPED |
.equ TIMSK1 = 0x6f ; MEMORY MAPPED |
.equ TIMSK0 = 0x6e ; MEMORY MAPPED |
.equ PCMSK2 = 0x6d ; MEMORY MAPPED |
.equ PCMSK1 = 0x6c ; MEMORY MAPPED |
.equ PCMSK0 = 0x6b ; MEMORY MAPPED |
.equ EICRB = 0x6a ; MEMORY MAPPED |
.equ EICRA = 0x69 ; MEMORY MAPPED |
.equ PCICR = 0x68 ; MEMORY MAPPED |
.equ OSCCAL = 0x66 ; MEMORY MAPPED |
.equ PRR1 = 0x65 ; MEMORY MAPPED |
.equ PRR0 = 0x64 ; MEMORY MAPPED |
.equ CLKPR = 0x61 ; MEMORY MAPPED |
.equ WDTCSR = 0x60 ; MEMORY MAPPED |
.equ SREG = 0x3f |
.equ SPH = 0x3e |
.equ SPL = 0x3d |
.equ EIND = 0x3c |
.equ RAMPZ = 0x3b |
.equ SPMCSR = 0x37 |
.equ MCUCR = 0x35 |
.equ MCUSR = 0x34 |
.equ SMCR = 0x33 |
.equ OCDR = 0x31 |
.equ ACSR = 0x30 |
.equ SPDR = 0x2e |
.equ SPSR = 0x2d |
.equ SPCR = 0x2c |
.equ GPIOR2 = 0x2b |
.equ GPIOR1 = 0x2a |
.equ OCR0B = 0x28 |
.equ OCR0A = 0x27 |
.equ TCNT0 = 0x26 |
.equ TCCR0B = 0x25 |
.equ TCCR0A = 0x24 |
.equ GTCCR = 0x23 |
.equ EEARH = 0x22 |
.equ EEARL = 0x21 |
.equ EEDR = 0x20 |
.equ EECR = 0x1f |
.equ GPIOR0 = 0x1e |
.equ EIMSK = 0x1d |
.equ EIFR = 0x1c |
.equ PCIFR = 0x1b |
.equ TIFR5 = 0x1a |
.equ TIFR4 = 0x19 |
.equ TIFR3 = 0x18 |
.equ TIFR2 = 0x17 |
.equ TIFR1 = 0x16 |
.equ TIFR0 = 0x15 |
.equ PORTG = 0x14 |
.equ DDRG = 0x13 |
.equ PING = 0x12 |
.equ PORTF = 0x11 |
.equ DDRF = 0x10 |
.equ PINF = 0x0f |
.equ PORTE = 0x0e |
.equ DDRE = 0x0d |
.equ PINE = 0x0c |
.equ PORTD = 0x0b |
.equ DDRD = 0x0a |
.equ PIND = 0x09 |
.equ PORTC = 0x08 |
.equ DDRC = 0x07 |
.equ PINC = 0x06 |
.equ PORTB = 0x05 |
.equ DDRB = 0x04 |
.equ PINB = 0x03 |
.equ PORTA = 0x02 |
.equ DDRA = 0x01 |
.equ PINA = 0x00 |
; ***** BIT DEFINITIONS ************************************************** |
; ***** ANALOG_COMPARATOR ************ |
; ADCSRB - ADC Control and Status Register B |
.equ ACME = 6 ; Analog Comparator Multiplexer Enable |
; ACSR - Analog Comparator Control And Status Register |
.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 |
.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 |
.equ ACIC = 2 ; Analog Comparator Input Capture Enable |
.equ ACIE = 3 ; Analog Comparator Interrupt Enable |
.equ ACI = 4 ; Analog Comparator Interrupt Flag |
.equ ACO = 5 ; Analog Compare Output |
.equ ACBG = 6 ; Analog Comparator Bandgap Select |
.equ ACD = 7 ; Analog Comparator Disable |
; DIDR1 - Digital Input Disable Register 1 |
.equ AIN0D = 0 ; AIN0 Digital Input Disable |
.equ AIN1D = 1 ; AIN1 Digital Input Disable |
; ***** USART0 *********************** |
; UDR0 - USART I/O Data Register |
.equ UDR0_0 = 0 ; USART I/O Data Register bit 0 |
.equ UDR0_1 = 1 ; USART I/O Data Register bit 1 |
.equ UDR0_2 = 2 ; USART I/O Data Register bit 2 |
.equ UDR0_3 = 3 ; USART I/O Data Register bit 3 |
.equ UDR0_4 = 4 ; USART I/O Data Register bit 4 |
.equ UDR0_5 = 5 ; USART I/O Data Register bit 5 |
.equ UDR0_6 = 6 ; USART I/O Data Register bit 6 |
.equ UDR0_7 = 7 ; USART I/O Data Register bit 7 |
; UCSR0A - USART Control and Status Register A |
.equ MPCM0 = 0 ; Multi-processor Communication Mode |
.equ U2X0 = 1 ; Double the USART transmission speed |
.equ UPE0 = 2 ; Parity Error |
.equ DOR0 = 3 ; Data overRun |
.equ FE0 = 4 ; Framing Error |
.equ UDRE0 = 5 ; USART Data Register Empty |
.equ TXC0 = 6 ; USART Transmitt Complete |
.equ RXC0 = 7 ; USART Receive Complete |
; UCSR0B - USART Control and Status Register B |
.equ TXB80 = 0 ; Transmit Data Bit 8 |
.equ RXB80 = 1 ; Receive Data Bit 8 |
.equ UCSZ02 = 2 ; Character Size |
.equ TXEN0 = 3 ; Transmitter Enable |
.equ RXEN0 = 4 ; Receiver Enable |
.equ UDRIE0 = 5 ; USART Data register Empty Interrupt Enable |
.equ TXCIE0 = 6 ; TX Complete Interrupt Enable |
.equ RXCIE0 = 7 ; RX Complete Interrupt Enable |
; UCSR0C - USART Control and Status Register C |
.equ UCPOL0 = 0 ; Clock Polarity |
.equ UCSZ00 = 1 ; Character Size |
.equ UCPHA0 = UCSZ00 ; For compatibility |
.equ UCSZ01 = 2 ; Character Size |
.equ UDORD0 = UCSZ01 ; For compatibility |
.equ USBS0 = 3 ; Stop Bit Select |
.equ UPM00 = 4 ; Parity Mode Bit 0 |
.equ UPM01 = 5 ; Parity Mode Bit 1 |
.equ UMSEL00 = 6 ; USART Mode Select |
.equ UMSEL0 = UMSEL00 ; For compatibility |
.equ UMSEL01 = 7 ; USART Mode Select |
.equ UMSEL1 = UMSEL01 ; For compatibility |
; ***** TWI ************************** |
; TWAMR - TWI (Slave) Address Mask Register |
.equ TWAM0 = 1 ; |
.equ TWAMR0 = TWAM0 ; For compatibility |
.equ TWAM1 = 2 ; |
.equ TWAMR1 = TWAM1 ; For compatibility |
.equ TWAM2 = 3 ; |
.equ TWAMR2 = TWAM2 ; For compatibility |
.equ TWAM3 = 4 ; |
.equ TWAMR3 = TWAM3 ; For compatibility |
.equ TWAM4 = 5 ; |
.equ TWAMR4 = TWAM4 ; For compatibility |
.equ TWAM5 = 6 ; |
.equ TWAMR5 = TWAM5 ; For compatibility |
.equ TWAM6 = 7 ; |
.equ TWAMR6 = TWAM6 ; For compatibility |
; TWBR - TWI Bit Rate register |
.equ TWBR0 = 0 ; |
.equ TWBR1 = 1 ; |
.equ TWBR2 = 2 ; |
.equ TWBR3 = 3 ; |
.equ TWBR4 = 4 ; |
.equ TWBR5 = 5 ; |
.equ TWBR6 = 6 ; |
.equ TWBR7 = 7 ; |
; TWCR - TWI Control Register |
.equ TWIE = 0 ; TWI Interrupt Enable |
.equ TWEN = 2 ; TWI Enable Bit |
.equ TWWC = 3 ; TWI Write Collition Flag |
.equ TWSTO = 4 ; TWI Stop Condition Bit |
.equ TWSTA = 5 ; TWI Start Condition Bit |
.equ TWEA = 6 ; TWI Enable Acknowledge Bit |
.equ TWINT = 7 ; TWI Interrupt Flag |
; TWSR - TWI Status Register |
.equ TWPS0 = 0 ; TWI Prescaler |
.equ TWPS1 = 1 ; TWI Prescaler |
.equ TWS3 = 3 ; TWI Status |
.equ TWS4 = 4 ; TWI Status |
.equ TWS5 = 5 ; TWI Status |
.equ TWS6 = 6 ; TWI Status |
.equ TWS7 = 7 ; TWI Status |
; TWDR - TWI Data register |
.equ TWD0 = 0 ; TWI Data Register Bit 0 |
.equ TWD1 = 1 ; TWI Data Register Bit 1 |
.equ TWD2 = 2 ; TWI Data Register Bit 2 |
.equ TWD3 = 3 ; TWI Data Register Bit 3 |
.equ TWD4 = 4 ; TWI Data Register Bit 4 |
.equ TWD5 = 5 ; TWI Data Register Bit 5 |
.equ TWD6 = 6 ; TWI Data Register Bit 6 |
.equ TWD7 = 7 ; TWI Data Register Bit 7 |
; TWAR - TWI (Slave) Address register |
.equ TWGCE = 0 ; TWI General Call Recognition Enable Bit |
.equ TWA0 = 1 ; TWI (Slave) Address register Bit 0 |
.equ TWA1 = 2 ; TWI (Slave) Address register Bit 1 |
.equ TWA2 = 3 ; TWI (Slave) Address register Bit 2 |
.equ TWA3 = 4 ; TWI (Slave) Address register Bit 3 |
.equ TWA4 = 5 ; TWI (Slave) Address register Bit 4 |
.equ TWA5 = 6 ; TWI (Slave) Address register Bit 5 |
.equ TWA6 = 7 ; TWI (Slave) Address register Bit 6 |
; ***** SPI ************************** |
; SPDR - SPI Data Register |
.equ SPDR0 = 0 ; SPI Data Register bit 0 |
.equ SPDR1 = 1 ; SPI Data Register bit 1 |
.equ SPDR2 = 2 ; SPI Data Register bit 2 |
.equ SPDR3 = 3 ; SPI Data Register bit 3 |
.equ SPDR4 = 4 ; SPI Data Register bit 4 |
.equ SPDR5 = 5 ; SPI Data Register bit 5 |
.equ SPDR6 = 6 ; SPI Data Register bit 6 |
.equ SPDR7 = 7 ; SPI Data Register bit 7 |
; SPSR - SPI Status Register |
.equ SPI2X = 0 ; Double SPI Speed Bit |
.equ WCOL = 6 ; Write Collision Flag |
.equ SPIF = 7 ; SPI Interrupt Flag |
; SPCR - SPI Control Register |
.equ SPR0 = 0 ; SPI Clock Rate Select 0 |
.equ SPR1 = 1 ; SPI Clock Rate Select 1 |
.equ CPHA = 2 ; Clock Phase |
.equ CPOL = 3 ; Clock polarity |
.equ MSTR = 4 ; Master/Slave Select |
.equ DORD = 5 ; Data Order |
.equ SPE = 6 ; SPI Enable |
.equ SPIE = 7 ; SPI Interrupt Enable |
; ***** PORTA ************************ |
; PORTA - Port A Data Register |
.equ PORTA0 = 0 ; Port A Data Register bit 0 |
.equ PA0 = 0 ; For compatibility |
.equ PORTA1 = 1 ; Port A Data Register bit 1 |
.equ PA1 = 1 ; For compatibility |
.equ PORTA2 = 2 ; Port A Data Register bit 2 |
.equ PA2 = 2 ; For compatibility |
.equ PORTA3 = 3 ; Port A Data Register bit 3 |
.equ PA3 = 3 ; For compatibility |
.equ PORTA4 = 4 ; Port A Data Register bit 4 |
.equ PA4 = 4 ; For compatibility |
.equ PORTA5 = 5 ; Port A Data Register bit 5 |
.equ PA5 = 5 ; For compatibility |
.equ PORTA6 = 6 ; Port A Data Register bit 6 |
.equ PA6 = 6 ; For compatibility |
.equ PORTA7 = 7 ; Port A Data Register bit 7 |
.equ PA7 = 7 ; For compatibility |
; DDRA - Port A Data Direction Register |
.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0 |
.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1 |
.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2 |
.equ DDA3 = 3 ; Data Direction Register, Port A, bit 3 |
.equ DDA4 = 4 ; Data Direction Register, Port A, bit 4 |
.equ DDA5 = 5 ; Data Direction Register, Port A, bit 5 |
.equ DDA6 = 6 ; Data Direction Register, Port A, bit 6 |
.equ DDA7 = 7 ; Data Direction Register, Port A, bit 7 |
; PINA - Port A Input Pins |
.equ PINA0 = 0 ; Input Pins, Port A bit 0 |
.equ PINA1 = 1 ; Input Pins, Port A bit 1 |
.equ PINA2 = 2 ; Input Pins, Port A bit 2 |
.equ PINA3 = 3 ; Input Pins, Port A bit 3 |
.equ PINA4 = 4 ; Input Pins, Port A bit 4 |
.equ PINA5 = 5 ; Input Pins, Port A bit 5 |
.equ PINA6 = 6 ; Input Pins, Port A bit 6 |
.equ PINA7 = 7 ; Input Pins, Port A bit 7 |
; ***** PORTB ************************ |
; PORTB - Port B Data Register |
.equ PORTB0 = 0 ; Port B Data Register bit 0 |
.equ PB0 = 0 ; For compatibility |
.equ PORTB1 = 1 ; Port B Data Register bit 1 |
.equ PB1 = 1 ; For compatibility |
.equ PORTB2 = 2 ; Port B Data Register bit 2 |
.equ PB2 = 2 ; For compatibility |
.equ PORTB3 = 3 ; Port B Data Register bit 3 |
.equ PB3 = 3 ; For compatibility |
.equ PORTB4 = 4 ; Port B Data Register bit 4 |
.equ PB4 = 4 ; For compatibility |
.equ PORTB5 = 5 ; Port B Data Register bit 5 |
.equ PB5 = 5 ; For compatibility |
.equ PORTB6 = 6 ; Port B Data Register bit 6 |
.equ PB6 = 6 ; For compatibility |
.equ PORTB7 = 7 ; Port B Data Register bit 7 |
.equ PB7 = 7 ; For compatibility |
; DDRB - Port B Data Direction Register |
.equ DDB0 = 0 ; Port B Data Direction Register bit 0 |
.equ DDB1 = 1 ; Port B Data Direction Register bit 1 |
.equ DDB2 = 2 ; Port B Data Direction Register bit 2 |
.equ DDB3 = 3 ; Port B Data Direction Register bit 3 |
.equ DDB4 = 4 ; Port B Data Direction Register bit 4 |
.equ DDB5 = 5 ; Port B Data Direction Register bit 5 |
.equ DDB6 = 6 ; Port B Data Direction Register bit 6 |
.equ DDB7 = 7 ; Port B Data Direction Register bit 7 |
; PINB - Port B Input Pins |
.equ PINB0 = 0 ; Port B Input Pins bit 0 |
.equ PINB1 = 1 ; Port B Input Pins bit 1 |
.equ PINB2 = 2 ; Port B Input Pins bit 2 |
.equ PINB3 = 3 ; Port B Input Pins bit 3 |
.equ PINB4 = 4 ; Port B Input Pins bit 4 |
.equ PINB5 = 5 ; Port B Input Pins bit 5 |
.equ PINB6 = 6 ; Port B Input Pins bit 6 |
.equ PINB7 = 7 ; Port B Input Pins bit 7 |
; ***** PORTC ************************ |
; PORTC - Port C Data Register |
.equ PORTC0 = 0 ; Port C Data Register bit 0 |
.equ PC0 = 0 ; For compatibility |
.equ PORTC1 = 1 ; Port C Data Register bit 1 |
.equ PC1 = 1 ; For compatibility |
.equ PORTC2 = 2 ; Port C Data Register bit 2 |
.equ PC2 = 2 ; For compatibility |
.equ PORTC3 = 3 ; Port C Data Register bit 3 |
.equ PC3 = 3 ; For compatibility |
.equ PORTC4 = 4 ; Port C Data Register bit 4 |
.equ PC4 = 4 ; For compatibility |
.equ PORTC5 = 5 ; Port C Data Register bit 5 |
.equ PC5 = 5 ; For compatibility |
.equ PORTC6 = 6 ; Port C Data Register bit 6 |
.equ PC6 = 6 ; For compatibility |
.equ PORTC7 = 7 ; Port C Data Register bit 7 |
.equ PC7 = 7 ; For compatibility |
; DDRC - Port C Data Direction Register |
.equ DDC0 = 0 ; Port C Data Direction Register bit 0 |
.equ DDC1 = 1 ; Port C Data Direction Register bit 1 |
.equ DDC2 = 2 ; Port C Data Direction Register bit 2 |
.equ DDC3 = 3 ; Port C Data Direction Register bit 3 |
.equ DDC4 = 4 ; Port C Data Direction Register bit 4 |
.equ DDC5 = 5 ; Port C Data Direction Register bit 5 |
.equ DDC6 = 6 ; Port C Data Direction Register bit 6 |
.equ DDC7 = 7 ; Port C Data Direction Register bit 7 |
; PINC - Port C Input Pins |
.equ PINC0 = 0 ; Port C Input Pins bit 0 |
.equ PINC1 = 1 ; Port C Input Pins bit 1 |
.equ PINC2 = 2 ; Port C Input Pins bit 2 |
.equ PINC3 = 3 ; Port C Input Pins bit 3 |
.equ PINC4 = 4 ; Port C Input Pins bit 4 |
.equ PINC5 = 5 ; Port C Input Pins bit 5 |
.equ PINC6 = 6 ; Port C Input Pins bit 6 |
.equ PINC7 = 7 ; Port C Input Pins bit 7 |
; ***** PORTD ************************ |
; PORTD - Port D Data Register |
.equ PORTD0 = 0 ; Port D Data Register bit 0 |
.equ PD0 = 0 ; For compatibility |
.equ PORTD1 = 1 ; Port D Data Register bit 1 |
.equ PD1 = 1 ; For compatibility |
.equ PORTD2 = 2 ; Port D Data Register bit 2 |
.equ PD2 = 2 ; For compatibility |
.equ PORTD3 = 3 ; Port D Data Register bit 3 |
.equ PD3 = 3 ; For compatibility |
.equ PORTD4 = 4 ; Port D Data Register bit 4 |
.equ PD4 = 4 ; For compatibility |
.equ PORTD5 = 5 ; Port D Data Register bit 5 |
.equ PD5 = 5 ; For compatibility |
.equ PORTD6 = 6 ; Port D Data Register bit 6 |
.equ PD6 = 6 ; For compatibility |
.equ PORTD7 = 7 ; Port D Data Register bit 7 |
.equ PD7 = 7 ; For compatibility |
; DDRD - Port D Data Direction Register |
.equ DDD0 = 0 ; Port D Data Direction Register bit 0 |
.equ DDD1 = 1 ; Port D Data Direction Register bit 1 |
.equ DDD2 = 2 ; Port D Data Direction Register bit 2 |
.equ DDD3 = 3 ; Port D Data Direction Register bit 3 |
.equ DDD4 = 4 ; Port D Data Direction Register bit 4 |
.equ DDD5 = 5 ; Port D Data Direction Register bit 5 |
.equ DDD6 = 6 ; Port D Data Direction Register bit 6 |
.equ DDD7 = 7 ; Port D Data Direction Register bit 7 |
; PIND - Port D Input Pins |
.equ PIND0 = 0 ; Port D Input Pins bit 0 |
.equ PIND1 = 1 ; Port D Input Pins bit 1 |
.equ PIND2 = 2 ; Port D Input Pins bit 2 |
.equ PIND3 = 3 ; Port D Input Pins bit 3 |
.equ PIND4 = 4 ; Port D Input Pins bit 4 |
.equ PIND5 = 5 ; Port D Input Pins bit 5 |
.equ PIND6 = 6 ; Port D Input Pins bit 6 |
.equ PIND7 = 7 ; Port D Input Pins bit 7 |
; ***** PORTE ************************ |
; PORTE - Data Register, Port E |
.equ PORTE0 = 0 ; |
.equ PE0 = 0 ; For compatibility |
.equ PORTE1 = 1 ; |
.equ PE1 = 1 ; For compatibility |
.equ PORTE2 = 2 ; |
.equ PE2 = 2 ; For compatibility |
.equ PORTE3 = 3 ; |
.equ PE3 = 3 ; For compatibility |
.equ PORTE4 = 4 ; |
.equ PE4 = 4 ; For compatibility |
.equ PORTE5 = 5 ; |
.equ PE5 = 5 ; For compatibility |
.equ PORTE6 = 6 ; |
.equ PE6 = 6 ; For compatibility |
.equ PORTE7 = 7 ; |
.equ PE7 = 7 ; For compatibility |
; DDRE - Data Direction Register, Port E |
.equ DDE0 = 0 ; |
.equ DDE1 = 1 ; |
.equ DDE2 = 2 ; |
.equ DDE3 = 3 ; |
.equ DDE4 = 4 ; |
.equ DDE5 = 5 ; |
.equ DDE6 = 6 ; |
.equ DDE7 = 7 ; |
; PINE - Input Pins, Port E |
.equ PINE0 = 0 ; |
.equ PINE1 = 1 ; |
.equ PINE2 = 2 ; |
.equ PINE3 = 3 ; |
.equ PINE4 = 4 ; |
.equ PINE5 = 5 ; |
.equ PINE6 = 6 ; |
.equ PINE7 = 7 ; |
; ***** PORTF ************************ |
; PORTF - Data Register, Port F |
.equ PORTF0 = 0 ; |
.equ PF0 = 0 ; For compatibility |
.equ PORTF1 = 1 ; |
.equ PF1 = 1 ; For compatibility |
.equ PORTF2 = 2 ; |
.equ PF2 = 2 ; For compatibility |
.equ PORTF3 = 3 ; |
.equ PF3 = 3 ; For compatibility |
.equ PORTF4 = 4 ; |
.equ PF4 = 4 ; For compatibility |
.equ PORTF5 = 5 ; |
.equ PF5 = 5 ; For compatibility |
.equ PORTF6 = 6 ; |
.equ PF6 = 6 ; For compatibility |
.equ PORTF7 = 7 ; |
.equ PF7 = 7 ; For compatibility |
; DDRF - Data Direction Register, Port F |
.equ DDF0 = 0 ; |
.equ DDF1 = 1 ; |
.equ DDF2 = 2 ; |
.equ DDF3 = 3 ; |
.equ DDF4 = 4 ; |
.equ DDF5 = 5 ; |
.equ DDF6 = 6 ; |
.equ DDF7 = 7 ; |
; PINF - Input Pins, Port F |
.equ PINF0 = 0 ; |
.equ PINF1 = 1 ; |
.equ PINF2 = 2 ; |
.equ PINF3 = 3 ; |
.equ PINF4 = 4 ; |
.equ PINF5 = 5 ; |
.equ PINF6 = 6 ; |
.equ PINF7 = 7 ; |
; ***** PORTG ************************ |
; PORTG - Data Register, Port G |
.equ PORTG0 = 0 ; |
.equ PG0 = 0 ; For compatibility |
.equ PORTG1 = 1 ; |
.equ PG1 = 1 ; For compatibility |
.equ PORTG2 = 2 ; |
.equ PG2 = 2 ; For compatibility |
.equ PORTG3 = 3 ; |
.equ PG3 = 3 ; For compatibility |
.equ PORTG4 = 4 ; |
.equ PG4 = 4 ; For compatibility |
.equ PORTG5 = 5 ; |
.equ PG5 = 5 ; For compatibility |
; DDRG |
.equ DDG0 = 0 ; |
.equ DDG1 = 1 ; |
.equ DDG2 = 2 ; |
.equ DDG3 = 3 ; |
.equ DDG4 = 4 ; |
.equ DDG5 = 5 ; |
; PING - Input Pins, Port G |
.equ PING0 = 0 ; |
.equ PING1 = 1 ; |
.equ PING2 = 2 ; |
.equ PING3 = 3 ; |
.equ PING4 = 4 ; |
.equ PING5 = 5 ; |
; ***** PORTH ************************ |
; PORTH - PORT H Data Register |
.equ PORTH0 = 0 ; PORT H Data Register bit 0 |
.equ PH0 = 0 ; For compatibility |
.equ PORTH1 = 1 ; PORT H Data Register bit 1 |
.equ PH1 = 1 ; For compatibility |
.equ PORTH2 = 2 ; PORT H Data Register bit 2 |
.equ PH2 = 2 ; For compatibility |
.equ PORTH3 = 3 ; PORT H Data Register bit 3 |
.equ PH3 = 3 ; For compatibility |
.equ PORTH4 = 4 ; PORT H Data Register bit 4 |
.equ PH4 = 4 ; For compatibility |
.equ PORTH5 = 5 ; PORT H Data Register bit 5 |
.equ PH5 = 5 ; For compatibility |
.equ PORTH6 = 6 ; PORT H Data Register bit 6 |
.equ PH6 = 6 ; For compatibility |
.equ PORTH7 = 7 ; PORT H Data Register bit 7 |
.equ PH7 = 7 ; For compatibility |
; DDRH - PORT H Data Direction Register |
.equ DDH0 = 0 ; PORT H Data Direction Register bit 0 |
.equ DDH1 = 1 ; PORT H Data Direction Register bit 1 |
.equ DDH2 = 2 ; PORT H Data Direction Register bit 2 |
.equ DDH3 = 3 ; PORT H Data Direction Register bit 3 |
.equ DDH4 = 4 ; PORT H Data Direction Register bit 4 |
.equ DDH5 = 5 ; PORT H Data Direction Register bit 5 |
.equ DDH6 = 6 ; PORT H Data Direction Register bit 6 |
.equ DDH7 = 7 ; PORT H Data Direction Register bit 7 |
; PINH - PORT H Input Pins |
.equ PINH0 = 0 ; PORT H Input Pins bit 0 |
.equ PINH1 = 1 ; PORT H Input Pins bit 1 |
.equ PINH2 = 2 ; PORT H Input Pins bit 2 |
.equ PINH3 = 3 ; PORT H Input Pins bit 3 |
.equ PINH4 = 4 ; PORT H Input Pins bit 4 |
.equ PINH5 = 5 ; PORT H Input Pins bit 5 |
.equ PINH6 = 6 ; PORT H Input Pins bit 6 |
.equ PINH7 = 7 ; PORT H Input Pins bit 7 |
; ***** PORTJ ************************ |
; PORTJ - PORT J Data Register |
.equ PORTJ0 = 0 ; PORT J Data Register bit 0 |
.equ PJ0 = 0 ; For compatibility |
.equ PORTJ1 = 1 ; PORT J Data Register bit 1 |
.equ PJ1 = 1 ; For compatibility |
.equ PORTJ2 = 2 ; PORT J Data Register bit 2 |
.equ PJ2 = 2 ; For compatibility |
.equ PORTJ3 = 3 ; PORT J Data Register bit 3 |
.equ PJ3 = 3 ; For compatibility |
.equ PORTJ4 = 4 ; PORT J Data Register bit 4 |
.equ PJ4 = 4 ; For compatibility |
.equ PORTJ5 = 5 ; PORT J Data Register bit 5 |
.equ PJ5 = 5 ; For compatibility |
.equ PORTJ6 = 6 ; PORT J Data Register bit 6 |
.equ PJ6 = 6 ; For compatibility |
.equ PORTJ7 = 7 ; PORT J Data Register bit 7 |
.equ PJ7 = 7 ; For compatibility |
; DDRJ - PORT J Data Direction Register |
.equ DDJ0 = 0 ; PORT J Data Direction Register bit 0 |
.equ DDJ1 = 1 ; PORT J Data Direction Register bit 1 |
.equ DDJ2 = 2 ; PORT J Data Direction Register bit 2 |
.equ DDJ3 = 3 ; PORT J Data Direction Register bit 3 |
.equ DDJ4 = 4 ; PORT J Data Direction Register bit 4 |
.equ DDJ5 = 5 ; PORT J Data Direction Register bit 5 |
.equ DDJ6 = 6 ; PORT J Data Direction Register bit 6 |
.equ DDJ7 = 7 ; PORT J Data Direction Register bit 7 |
; PINJ - PORT J Input Pins |
.equ PINJ0 = 0 ; PORT J Input Pins bit 0 |
.equ PINJ1 = 1 ; PORT J Input Pins bit 1 |
.equ PINJ2 = 2 ; PORT J Input Pins bit 2 |
.equ PINJ3 = 3 ; PORT J Input Pins bit 3 |
.equ PINJ4 = 4 ; PORT J Input Pins bit 4 |
.equ PINJ5 = 5 ; PORT J Input Pins bit 5 |
.equ PINJ6 = 6 ; PORT J Input Pins bit 6 |
.equ PINJ7 = 7 ; PORT J Input Pins bit 7 |
; ***** PORTK ************************ |
; PORTK - PORT K Data Register |
.equ PORTK0 = 0 ; PORT K Data Register bit 0 |
.equ PK0 = 0 ; For compatibility |
.equ PORTK1 = 1 ; PORT K Data Register bit 1 |
.equ PK1 = 1 ; For compatibility |
.equ PORTK2 = 2 ; PORT K Data Register bit 2 |
.equ PK2 = 2 ; For compatibility |
.equ PORTK3 = 3 ; PORT K Data Register bit 3 |
.equ PK3 = 3 ; For compatibility |
.equ PORTK4 = 4 ; PORT K Data Register bit 4 |
.equ PK4 = 4 ; For compatibility |
.equ PORTK5 = 5 ; PORT K Data Register bit 5 |
.equ PK5 = 5 ; For compatibility |
.equ PORTK6 = 6 ; PORT K Data Register bit 6 |
.equ PK6 = 6 ; For compatibility |
.equ PORTK7 = 7 ; PORT K Data Register bit 7 |
.equ PK7 = 7 ; For compatibility |
; DDRK - PORT K Data Direction Register |
.equ DDK0 = 0 ; PORT K Data Direction Register bit 0 |
.equ DDK1 = 1 ; PORT K Data Direction Register bit 1 |
.equ DDK2 = 2 ; PORT K Data Direction Register bit 2 |
.equ DDK3 = 3 ; PORT K Data Direction Register bit 3 |
.equ DDK4 = 4 ; PORT K Data Direction Register bit 4 |
.equ DDK5 = 5 ; PORT K Data Direction Register bit 5 |
.equ DDK6 = 6 ; PORT K Data Direction Register bit 6 |
.equ DDK7 = 7 ; PORT K Data Direction Register bit 7 |
; PINK - PORT K Input Pins |
.equ PINK0 = 0 ; PORT K Input Pins bit 0 |
.equ PINK1 = 1 ; PORT K Input Pins bit 1 |
.equ PINK2 = 2 ; PORT K Input Pins bit 2 |
.equ PINK3 = 3 ; PORT K Input Pins bit 3 |
.equ PINK4 = 4 ; PORT K Input Pins bit 4 |
.equ PINK5 = 5 ; PORT K Input Pins bit 5 |
.equ PINK6 = 6 ; PORT K Input Pins bit 6 |
.equ PINK7 = 7 ; PORT K Input Pins bit 7 |
; ***** PORTL ************************ |
; PORTL - PORT L Data Register |
.equ PORTL0 = 0 ; PORT L Data Register bit 0 |
.equ PL0 = 0 ; For compatibility |
.equ PORTL1 = 1 ; PORT L Data Register bit 1 |
.equ PL1 = 1 ; For compatibility |
.equ PORTL2 = 2 ; PORT L Data Register bit 2 |
.equ PL2 = 2 ; For compatibility |
.equ PORTL3 = 3 ; PORT L Data Register bit 3 |
.equ PL3 = 3 ; For compatibility |
.equ PORTL4 = 4 ; PORT L Data Register bit 4 |
.equ PL4 = 4 ; For compatibility |
.equ PORTL5 = 5 ; PORT L Data Register bit 5 |
.equ PL5 = 5 ; For compatibility |
.equ PORTL6 = 6 ; PORT L Data Register bit 6 |
.equ PL6 = 6 ; For compatibility |
.equ PORTL7 = 7 ; PORT L Data Register bit 7 |
.equ PL7 = 7 ; For compatibility |
; DDRL - PORT L Data Direction Register |
.equ DDL0 = 0 ; PORT L Data Direction Register bit 0 |
.equ DDL1 = 1 ; PORT L Data Direction Register bit 1 |
.equ DDL2 = 2 ; PORT L Data Direction Register bit 2 |
.equ DDL3 = 3 ; PORT L Data Direction Register bit 3 |
.equ DDL4 = 4 ; PORT L Data Direction Register bit 4 |
.equ DDL5 = 5 ; PORT L Data Direction Register bit 5 |
.equ DDL6 = 6 ; PORT L Data Direction Register bit 6 |
.equ DDL7 = 7 ; PORT L Data Direction Register bit 7 |
; PINL - PORT L Input Pins |
.equ PINL0 = 0 ; PORT L Input Pins bit 0 |
.equ PINL1 = 1 ; PORT L Input Pins bit 1 |
.equ PINL2 = 2 ; PORT L Input Pins bit 2 |
.equ PINL3 = 3 ; PORT L Input Pins bit 3 |
.equ PINL4 = 4 ; PORT L Input Pins bit 4 |
.equ PINL5 = 5 ; PORT L Input Pins bit 5 |
.equ PINL6 = 6 ; PORT L Input Pins bit 6 |
.equ PINL7 = 7 ; PORT L Input Pins bit 7 |
; ***** TIMER_COUNTER_0 ************** |
; TIMSK0 - Timer/Counter0 Interrupt Mask Register |
.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable |
.equ OCIE0A = 1 ; Timer/Counter0 Output Compare Match A Interrupt Enable |
.equ OCIE0B = 2 ; Timer/Counter0 Output Compare Match B Interrupt Enable |
; TIFR0 - Timer/Counter0 Interrupt Flag register |
.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag |
.equ OCF0A = 1 ; Timer/Counter0 Output Compare Flag 0A |
.equ OCF0B = 2 ; Timer/Counter0 Output Compare Flag 0B |
; TCCR0A - Timer/Counter Control Register A |
.equ WGM00 = 0 ; Waveform Generation Mode |
.equ WGM01 = 1 ; Waveform Generation Mode |
.equ COM0B0 = 4 ; Compare Output Mode, Fast PWm |
.equ COM0B1 = 5 ; Compare Output Mode, Fast PWm |
.equ COM0A0 = 6 ; Compare Output Mode, Phase Correct PWM Mode |
.equ COM0A1 = 7 ; Compare Output Mode, Phase Correct PWM Mode |
; TCCR0B - Timer/Counter Control Register B |
.equ CS00 = 0 ; Clock Select |
.equ CS01 = 1 ; Clock Select |
.equ CS02 = 2 ; Clock Select |
.equ WGM02 = 3 ; |
.equ FOC0B = 6 ; Force Output Compare B |
.equ FOC0A = 7 ; Force Output Compare A |
; TCNT0 - Timer/Counter0 |
.equ TCNT0_0 = 0 ; |
.equ TCNT0_1 = 1 ; |
.equ TCNT0_2 = 2 ; |
.equ TCNT0_3 = 3 ; |
.equ TCNT0_4 = 4 ; |
.equ TCNT0_5 = 5 ; |
.equ TCNT0_6 = 6 ; |
.equ TCNT0_7 = 7 ; |
; OCR0A - Timer/Counter0 Output Compare Register |
.equ OCROA_0 = 0 ; |
.equ OCROA_1 = 1 ; |
.equ OCROA_2 = 2 ; |
.equ OCROA_3 = 3 ; |
.equ OCROA_4 = 4 ; |
.equ OCROA_5 = 5 ; |
.equ OCROA_6 = 6 ; |
.equ OCROA_7 = 7 ; |
; OCR0B - Timer/Counter0 Output Compare Register |
.equ OCR0B_0 = 0 ; |
.equ OCR0B_1 = 1 ; |
.equ OCR0B_2 = 2 ; |
.equ OCR0B_3 = 3 ; |
.equ OCR0B_4 = 4 ; |
.equ OCR0B_5 = 5 ; |
.equ OCR0B_6 = 6 ; |
.equ OCR0B_7 = 7 ; |
; GTCCR - General Timer/Counter Control Register |
.equ PSRSYNC = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0 |
.equ PSR10 = PSRSYNC ; For compatibility |
.equ TSM = 7 ; Timer/Counter Synchronization Mode |
; ***** TIMER_COUNTER_2 ************** |
; TIMSK2 - Timer/Counter Interrupt Mask register |
.equ TOIE2 = 0 ; Timer/Counter2 Overflow Interrupt Enable |
.equ TOIE2A = TOIE2 ; For compatibility |
.equ OCIE2A = 1 ; Timer/Counter2 Output Compare Match A Interrupt Enable |
.equ OCIE2B = 2 ; Timer/Counter2 Output Compare Match B Interrupt Enable |
; TIFR2 - Timer/Counter Interrupt Flag Register |
.equ TOV2 = 0 ; Timer/Counter2 Overflow Flag |
.equ OCF2A = 1 ; Output Compare Flag 2A |
.equ OCF2B = 2 ; Output Compare Flag 2B |
; TCCR2A - Timer/Counter2 Control Register A |
.equ WGM20 = 0 ; Waveform Genration Mode |
.equ WGM21 = 1 ; Waveform Genration Mode |
.equ COM2B0 = 4 ; Compare Output Mode bit 0 |
.equ COM2B1 = 5 ; Compare Output Mode bit 1 |
.equ COM2A0 = 6 ; Compare Output Mode bit 1 |
.equ COM2A1 = 7 ; Compare Output Mode bit 1 |
; TCCR2B - Timer/Counter2 Control Register B |
.equ CS20 = 0 ; Clock Select bit 0 |
.equ CS21 = 1 ; Clock Select bit 1 |
.equ CS22 = 2 ; Clock Select bit 2 |
.equ WGM22 = 3 ; Waveform Generation Mode |
.equ FOC2B = 6 ; Force Output Compare B |
.equ FOC2A = 7 ; Force Output Compare A |
; TCNT2 - Timer/Counter2 |
.equ TCNT2_0 = 0 ; Timer/Counter 2 bit 0 |
.equ TCNT2_1 = 1 ; Timer/Counter 2 bit 1 |
.equ TCNT2_2 = 2 ; Timer/Counter 2 bit 2 |
.equ TCNT2_3 = 3 ; Timer/Counter 2 bit 3 |
.equ TCNT2_4 = 4 ; Timer/Counter 2 bit 4 |
.equ TCNT2_5 = 5 ; Timer/Counter 2 bit 5 |
.equ TCNT2_6 = 6 ; Timer/Counter 2 bit 6 |
.equ TCNT2_7 = 7 ; Timer/Counter 2 bit 7 |
; OCR2A - Timer/Counter2 Output Compare Register A |
.equ OCR2_0 = 0 ; Timer/Counter2 Output Compare Register Bit 0 |
.equ OCR2_1 = 1 ; Timer/Counter2 Output Compare Register Bit 1 |
.equ OCR2_2 = 2 ; Timer/Counter2 Output Compare Register Bit 2 |
.equ OCR2_3 = 3 ; Timer/Counter2 Output Compare Register Bit 3 |
.equ OCR2_4 = 4 ; Timer/Counter2 Output Compare Register Bit 4 |
.equ OCR2_5 = 5 ; Timer/Counter2 Output Compare Register Bit 5 |
.equ OCR2_6 = 6 ; Timer/Counter2 Output Compare Register Bit 6 |
.equ OCR2_7 = 7 ; Timer/Counter2 Output Compare Register Bit 7 |
; OCR2B - Timer/Counter2 Output Compare Register B |
;.equ OCR2_0 = 0 ; Timer/Counter2 Output Compare Register Bit 0 |
;.equ OCR2_1 = 1 ; Timer/Counter2 Output Compare Register Bit 1 |
;.equ OCR2_2 = 2 ; Timer/Counter2 Output Compare Register Bit 2 |
;.equ OCR2_3 = 3 ; Timer/Counter2 Output Compare Register Bit 3 |
;.equ OCR2_4 = 4 ; Timer/Counter2 Output Compare Register Bit 4 |
;.equ OCR2_5 = 5 ; Timer/Counter2 Output Compare Register Bit 5 |
;.equ OCR2_6 = 6 ; Timer/Counter2 Output Compare Register Bit 6 |
;.equ OCR2_7 = 7 ; Timer/Counter2 Output Compare Register Bit 7 |
; ASSR - Asynchronous Status Register |
.equ TCR2BUB = 0 ; Timer/Counter Control Register2 Update Busy |
.equ TCR2AUB = 1 ; Timer/Counter Control Register2 Update Busy |
.equ OCR2BUB = 2 ; Output Compare Register 2 Update Busy |
.equ OCR2AUB = 3 ; Output Compare Register2 Update Busy |
.equ TCN2UB = 4 ; Timer/Counter2 Update Busy |
.equ AS2 = 5 ; Asynchronous Timer/Counter2 |
.equ EXCLK = 6 ; Enable External Clock Input |
; GTCCR - General Timer Counter Control register |
.equ PSRASY = 1 ; Prescaler Reset Timer/Counter2 |
.equ PSR2 = PSRASY ; For compatibility |
;.equ TSM = 7 ; Timer/Counter Synchronization Mode |
; ***** WATCHDOG ********************* |
; WDTCSR - Watchdog Timer Control Register |
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 |
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 |
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 |
.equ WDE = 3 ; Watch Dog Enable |
.equ WDCE = 4 ; Watchdog Change Enable |
.equ WDP3 = 5 ; Watchdog Timer Prescaler Bit 3 |
.equ WDIE = 6 ; Watchdog Timeout Interrupt Enable |
.equ WDIF = 7 ; Watchdog Timeout Interrupt Flag |
; ***** USART1 *********************** |
; UDR1 - USART I/O Data Register |
.equ UDR1_0 = 0 ; USART I/O Data Register bit 0 |
.equ UDR1_1 = 1 ; USART I/O Data Register bit 1 |
.equ UDR1_2 = 2 ; USART I/O Data Register bit 2 |
.equ UDR1_3 = 3 ; USART I/O Data Register bit 3 |
.equ UDR1_4 = 4 ; USART I/O Data Register bit 4 |
.equ UDR1_5 = 5 ; USART I/O Data Register bit 5 |
.equ UDR1_6 = 6 ; USART I/O Data Register bit 6 |
.equ UDR1_7 = 7 ; USART I/O Data Register bit 7 |
; UCSR1A - USART Control and Status Register A |
.equ MPCM1 = 0 ; Multi-processor Communication Mode |
.equ U2X1 = 1 ; Double the USART transmission speed |
.equ UPE1 = 2 ; Parity Error |
.equ DOR1 = 3 ; Data overRun |
.equ FE1 = 4 ; Framing Error |
.equ UDRE1 = 5 ; USART Data Register Empty |
.equ TXC1 = 6 ; USART Transmitt Complete |
.equ RXC1 = 7 ; USART Receive Complete |
; UCSR1B - USART Control and Status Register B |
.equ TXB81 = 0 ; Transmit Data Bit 8 |
.equ RXB81 = 1 ; Receive Data Bit 8 |
.equ UCSZ12 = 2 ; Character Size |
.equ TXEN1 = 3 ; Transmitter Enable |
.equ RXEN1 = 4 ; Receiver Enable |
.equ UDRIE1 = 5 ; USART Data register Empty Interrupt Enable |
.equ TXCIE1 = 6 ; TX Complete Interrupt Enable |
.equ RXCIE1 = 7 ; RX Complete Interrupt Enable |
; UCSR1C - USART Control and Status Register C |
.equ UCPOL1 = 0 ; Clock Polarity |
.equ UCSZ10_UCPHA1 = 1 ; Character Size |
.equ UCSZ11_UDORD1 = 2 ; Character Size |
.equ USBS1 = 3 ; Stop Bit Select |
.equ UPM10 = 4 ; Parity Mode Bit 0 |
.equ UPM11 = 5 ; Parity Mode Bit 1 |
.equ UMSEL10 = 6 ; USART Mode Select |
.equ UMSEL11 = 7 ; USART Mode Select |
; ***** EEPROM *********************** |
; EEARH - EEPROM Address Register Low Byte |
.equ EEAR8 = 0 ; EEPROM Read/Write Access Bit 8 |
.equ EEAR9 = 1 ; EEPROM Read/Write Access Bit 9 |
.equ EEAR10 = 2 ; EEPROM Read/Write Access Bit 10 |
.equ EEAR11 = 3 ; EEPROM Read/Write Access Bit 11 |
; EEARL - EEPROM Address Register Low Byte |
.equ EEAR0 = 0 ; EEPROM Read/Write Access Bit 0 |
.equ EEAR1 = 1 ; EEPROM Read/Write Access Bit 1 |
.equ EEAR2 = 2 ; EEPROM Read/Write Access Bit 2 |
.equ EEAR3 = 3 ; EEPROM Read/Write Access Bit 3 |
.equ EEAR4 = 4 ; EEPROM Read/Write Access Bit 4 |
.equ EEAR5 = 5 ; EEPROM Read/Write Access Bit 5 |
.equ EEAR6 = 6 ; EEPROM Read/Write Access Bit 6 |
.equ EEAR7 = 7 ; EEPROM Read/Write Access Bit 7 |
; EEDR - EEPROM Data Register |
.equ EEDR0 = 0 ; EEPROM Data Register bit 0 |
.equ EEDR1 = 1 ; EEPROM Data Register bit 1 |
.equ EEDR2 = 2 ; EEPROM Data Register bit 2 |
.equ EEDR3 = 3 ; EEPROM Data Register bit 3 |
.equ EEDR4 = 4 ; EEPROM Data Register bit 4 |
.equ EEDR5 = 5 ; EEPROM Data Register bit 5 |
.equ EEDR6 = 6 ; EEPROM Data Register bit 6 |
.equ EEDR7 = 7 ; EEPROM Data Register bit 7 |
; EECR - EEPROM Control Register |
.equ EERE = 0 ; EEPROM Read Enable |
.equ EEPE = 1 ; EEPROM Write Enable |
.equ EEMPE = 2 ; EEPROM Master Write Enable |
.equ EERIE = 3 ; EEPROM Ready Interrupt Enable |
.equ EEPM0 = 4 ; EEPROM Programming Mode Bit 0 |
.equ EEPM1 = 5 ; EEPROM Programming Mode Bit 1 |
; ***** TIMER_COUNTER_5 ************** |
; TIMSK5 - Timer/Counter5 Interrupt Mask Register |
.equ TOIE5 = 0 ; Timer/Counter5 Overflow Interrupt Enable |
.equ OCIE5A = 1 ; Timer/Counter5 Output Compare A Match Interrupt Enable |
.equ OCIE5B = 2 ; Timer/Counter5 Output Compare B Match Interrupt Enable |
.equ OCIE5C = 3 ; Timer/Counter5 Output Compare C Match Interrupt Enable |
.equ ICIE5 = 5 ; Timer/Counter5 Input Capture Interrupt Enable |
; TIFR5 - Timer/Counter5 Interrupt Flag register |
.equ TOV5 = 0 ; Timer/Counter5 Overflow Flag |
.equ OCF5A = 1 ; Output Compare Flag 5A |
.equ OCF5B = 2 ; Output Compare Flag 5B |
.equ OCF5C = 3 ; Output Compare Flag 5C |
.equ ICF5 = 5 ; Input Capture Flag 5 |
; TCCR5A - Timer/Counter5 Control Register A |
.equ WGM50 = 0 ; Waveform Generation Mode |
.equ WGM51 = 1 ; Waveform Generation Mode |
.equ COM5C0 = 2 ; Compare Output Mode 5C, bit 0 |
.equ COM5C1 = 3 ; Compare Output Mode 5C, bit 1 |
.equ COM5B0 = 4 ; Compare Output Mode 5B, bit 0 |
.equ COM5B1 = 5 ; Compare Output Mode 5B, bit 1 |
.equ COM5A0 = 6 ; Compare Output Mode 5A, bit 0 |
.equ COM5A1 = 7 ; Compare Output Mode 1A, bit 1 |
; TCCR5B - Timer/Counter5 Control Register B |
.equ CS50 = 0 ; Prescaler source of Timer/Counter 5 |
.equ CS51 = 1 ; Prescaler source of Timer/Counter 5 |
.equ CS52 = 2 ; Prescaler source of Timer/Counter 5 |
.equ WGM52 = 3 ; Waveform Generation Mode |
.equ WGM53 = 4 ; Waveform Generation Mode |
.equ ICES5 = 6 ; Input Capture 5 Edge Select |
.equ ICNC5 = 7 ; Input Capture 5 Noise Canceler |
; TCCR5C - Timer/Counter 5 Control Register C |
.equ FOC5C = 5 ; Force Output Compare 5C |
.equ FOC5B = 6 ; Force Output Compare 5B |
.equ FOC5A = 7 ; Force Output Compare 5A |
; ICR5L - Timer/Counter5 Input Capture Register Low Byte |
.equ ICR5L0 = 0 ; Timer/Counter5 Input Capture Register Low Byte bit 0 |
.equ ICR5L1 = 1 ; Timer/Counter5 Input Capture Register Low Byte bit 1 |
.equ ICR5L2 = 2 ; Timer/Counter5 Input Capture Register Low Byte bit 2 |
.equ ICR5L3 = 3 ; Timer/Counter5 Input Capture Register Low Byte bit 3 |
.equ ICR5L4 = 4 ; Timer/Counter5 Input Capture Register Low Byte bit 4 |
.equ ICR5L5 = 5 ; Timer/Counter5 Input Capture Register Low Byte bit 5 |
.equ ICR5L6 = 6 ; Timer/Counter5 Input Capture Register Low Byte bit 6 |
.equ ICR5L7 = 7 ; Timer/Counter5 Input Capture Register Low Byte bit 7 |
; ***** TIMER_COUNTER_4 ************** |
; TIMSK4 - Timer/Counter4 Interrupt Mask Register |
.equ TOIE4 = 0 ; Timer/Counter4 Overflow Interrupt Enable |
.equ OCIE4A = 1 ; Timer/Counter4 Output Compare A Match Interrupt Enable |
.equ OCIE4B = 2 ; Timer/Counter4 Output Compare B Match Interrupt Enable |
.equ OCIE4C = 3 ; Timer/Counter4 Output Compare C Match Interrupt Enable |
.equ ICIE4 = 5 ; Timer/Counter4 Input Capture Interrupt Enable |
; TIFR4 - Timer/Counter4 Interrupt Flag register |
.equ TOV4 = 0 ; Timer/Counter4 Overflow Flag |
.equ OCF4A = 1 ; Output Compare Flag 4A |
.equ OCF4B = 2 ; Output Compare Flag 4B |
.equ OCF4C = 3 ; Output Compare Flag 4C |
.equ ICF4 = 5 ; Input Capture Flag 4 |
; TCCR4A - Timer/Counter4 Control Register A |
.equ WGM40 = 0 ; Waveform Generation Mode |
.equ WGM41 = 1 ; Waveform Generation Mode |
.equ COM4C0 = 2 ; Compare Output Mode 4C, bit 0 |
.equ COM4C1 = 3 ; Compare Output Mode 4C, bit 1 |
.equ COM4B0 = 4 ; Compare Output Mode 4B, bit 0 |
.equ COM4B1 = 5 ; Compare Output Mode 4B, bit 1 |
.equ COM4A0 = 6 ; Compare Output Mode 4A, bit 0 |
.equ COM4A1 = 7 ; Compare Output Mode 1A, bit 1 |
; TCCR4B - Timer/Counter4 Control Register B |
.equ CS40 = 0 ; Prescaler source of Timer/Counter 4 |
.equ CS41 = 1 ; Prescaler source of Timer/Counter 4 |
.equ CS42 = 2 ; Prescaler source of Timer/Counter 4 |
.equ WGM42 = 3 ; Waveform Generation Mode |
.equ WGM43 = 4 ; Waveform Generation Mode |
.equ ICES4 = 6 ; Input Capture 4 Edge Select |
.equ ICNC4 = 7 ; Input Capture 4 Noise Canceler |
; TCCR4C - Timer/Counter 4 Control Register C |
.equ FOC4C = 5 ; Force Output Compare 4C |
.equ FOC4B = 6 ; Force Output Compare 4B |
.equ FOC4A = 7 ; Force Output Compare 4A |
; ***** TIMER_COUNTER_3 ************** |
; TIMSK3 - Timer/Counter3 Interrupt Mask Register |
.equ TOIE3 = 0 ; Timer/Counter3 Overflow Interrupt Enable |
.equ OCIE3A = 1 ; Timer/Counter3 Output Compare A Match Interrupt Enable |
.equ OCIE3B = 2 ; Timer/Counter3 Output Compare B Match Interrupt Enable |
.equ OCIE3C = 3 ; Timer/Counter3 Output Compare C Match Interrupt Enable |
.equ ICIE3 = 5 ; Timer/Counter3 Input Capture Interrupt Enable |
; TIFR3 - Timer/Counter3 Interrupt Flag register |
.equ TOV3 = 0 ; Timer/Counter3 Overflow Flag |
.equ OCF3A = 1 ; Output Compare Flag 3A |
.equ OCF3B = 2 ; Output Compare Flag 3B |
.equ OCF3C = 3 ; Output Compare Flag 3C |
.equ ICF3 = 5 ; Input Capture Flag 3 |
; TCCR3A - Timer/Counter3 Control Register A |
.equ WGM30 = 0 ; Waveform Generation Mode |
.equ WGM31 = 1 ; Waveform Generation Mode |
.equ COM3C0 = 2 ; Compare Output Mode 3C, bit 0 |
.equ COM3C1 = 3 ; Compare Output Mode 3C, bit 1 |
.equ COM3B0 = 4 ; Compare Output Mode 3B, bit 0 |
.equ COM3B1 = 5 ; Compare Output Mode 3B, bit 1 |
.equ COM3A0 = 6 ; Compare Output Mode 3A, bit 0 |
.equ COM3A1 = 7 ; Compare Output Mode 1A, bit 1 |
; TCCR3B - Timer/Counter3 Control Register B |
.equ CS30 = 0 ; Prescaler source of Timer/Counter 3 |
.equ CS31 = 1 ; Prescaler source of Timer/Counter 3 |
.equ CS32 = 2 ; Prescaler source of Timer/Counter 3 |
.equ WGM32 = 3 ; Waveform Generation Mode |
.equ WGM33 = 4 ; Waveform Generation Mode |
.equ ICES3 = 6 ; Input Capture 3 Edge Select |
.equ ICNC3 = 7 ; Input Capture 3 Noise Canceler |
; TCCR3C - Timer/Counter 3 Control Register C |
.equ FOC3C = 5 ; Force Output Compare 3C |
.equ FOC3B = 6 ; Force Output Compare 3B |
.equ FOC3A = 7 ; Force Output Compare 3A |
; ***** TIMER_COUNTER_1 ************** |
; TIMSK1 - Timer/Counter1 Interrupt Mask Register |
.equ TOIE1 = 0 ; Timer/Counter1 Overflow Interrupt Enable |
.equ OCIE1A = 1 ; Timer/Counter1 Output Compare A Match Interrupt Enable |
.equ OCIE1B = 2 ; Timer/Counter1 Output Compare B Match Interrupt Enable |
.equ OCIE1C = 3 ; Timer/Counter1 Output Compare C Match Interrupt Enable |
.equ ICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable |
; TIFR1 - Timer/Counter1 Interrupt Flag register |
.equ TOV1 = 0 ; Timer/Counter1 Overflow Flag |
.equ OCF1A = 1 ; Output Compare Flag 1A |
.equ OCF1B = 2 ; Output Compare Flag 1B |
.equ OCF1C = 3 ; Output Compare Flag 1C |
.equ ICF1 = 5 ; Input Capture Flag 1 |
; TCCR1A - Timer/Counter1 Control Register A |
.equ WGM10 = 0 ; Waveform Generation Mode |
.equ WGM11 = 1 ; Waveform Generation Mode |
.equ COM1C0 = 2 ; Compare Output Mode 1C, bit 0 |
.equ COM1C1 = 3 ; Compare Output Mode 1C, bit 1 |
.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0 |
.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1 |
.equ COM1A0 = 6 ; Compare Output Mode 1A, bit 0 |
.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1 |
; TCCR1B - Timer/Counter1 Control Register B |
.equ CS10 = 0 ; Prescaler source of Timer/Counter 1 |
.equ CS11 = 1 ; Prescaler source of Timer/Counter 1 |
.equ CS12 = 2 ; Prescaler source of Timer/Counter 1 |
.equ WGM12 = 3 ; Waveform Generation Mode |
.equ WGM13 = 4 ; Waveform Generation Mode |
.equ ICES1 = 6 ; Input Capture 1 Edge Select |
.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler |
; TCCR1C - Timer/Counter 1 Control Register C |
.equ FOC1C = 5 ; Force Output Compare 1C |
.equ FOC1B = 6 ; Force Output Compare 1B |
.equ FOC1A = 7 ; Force Output Compare 1A |
; ***** JTAG ************************* |
; OCDR - On-Chip Debug Related Register in I/O Memory |
.equ OCDR0 = 0 ; On-Chip Debug Register Bit 0 |
.equ OCDR1 = 1 ; On-Chip Debug Register Bit 1 |
.equ OCDR2 = 2 ; On-Chip Debug Register Bit 2 |
.equ OCDR3 = 3 ; On-Chip Debug Register Bit 3 |
.equ OCDR4 = 4 ; On-Chip Debug Register Bit 4 |
.equ OCDR5 = 5 ; On-Chip Debug Register Bit 5 |
.equ OCDR6 = 6 ; On-Chip Debug Register Bit 6 |
.equ OCDR7 = 7 ; On-Chip Debug Register Bit 7 |
.equ IDRD = OCDR7 ; For compatibility |
; MCUCR - MCU Control Register |
.equ JTD = 7 ; JTAG Interface Disable |
; MCUSR - MCU Status Register |
.equ JTRF = 4 ; JTAG Reset Flag |
; ***** EXTERNAL_INTERRUPT *********** |
; EICRA - External Interrupt Control Register A |
.equ ISC00 = 0 ; External Interrupt Sense Control Bit |
.equ ISC01 = 1 ; External Interrupt Sense Control Bit |
.equ ISC10 = 2 ; External Interrupt Sense Control Bit |
.equ ISC11 = 3 ; External Interrupt Sense Control Bit |
.equ ISC20 = 4 ; External Interrupt Sense Control Bit |
.equ ISC21 = 5 ; External Interrupt Sense Control Bit |
.equ ISC30 = 6 ; External Interrupt Sense Control Bit |
.equ ISC31 = 7 ; External Interrupt Sense Control Bit |
; EICRB - External Interrupt Control Register B |
.equ ISC40 = 0 ; External Interrupt 7-4 Sense Control Bit |
.equ ISC41 = 1 ; External Interrupt 7-4 Sense Control Bit |
.equ ISC50 = 2 ; External Interrupt 7-4 Sense Control Bit |
.equ ISC51 = 3 ; External Interrupt 7-4 Sense Control Bit |
.equ ISC60 = 4 ; External Interrupt 7-4 Sense Control Bit |
.equ ISC61 = 5 ; External Interrupt 7-4 Sense Control Bit |
.equ ISC70 = 6 ; External Interrupt 7-4 Sense Control Bit |
.equ ISC71 = 7 ; External Interrupt 7-4 Sense Control Bit |
; EIMSK - External Interrupt Mask Register |
.equ INT0 = 0 ; External Interrupt Request 0 Enable |
.equ INT1 = 1 ; External Interrupt Request 1 Enable |
.equ INT2 = 2 ; External Interrupt Request 2 Enable |
.equ INT3 = 3 ; External Interrupt Request 3 Enable |
.equ INT4 = 4 ; External Interrupt Request 4 Enable |
.equ INT5 = 5 ; External Interrupt Request 5 Enable |
.equ INT6 = 6 ; External Interrupt Request 6 Enable |
.equ INT7 = 7 ; External Interrupt Request 7 Enable |
; EIFR - External Interrupt Flag Register |
.equ INTF0 = 0 ; External Interrupt Flag 0 |
.equ INTF1 = 1 ; External Interrupt Flag 1 |
.equ INTF2 = 2 ; External Interrupt Flag 2 |
.equ INTF3 = 3 ; External Interrupt Flag 3 |
.equ INTF4 = 4 ; External Interrupt Flag 4 |
.equ INTF5 = 5 ; External Interrupt Flag 5 |
.equ INTF6 = 6 ; External Interrupt Flag 6 |
.equ INTF7 = 7 ; External Interrupt Flag 7 |
; PCICR - Pin Change Interrupt Control Register |
.equ PCIE0 = 0 ; Pin Change Interrupt Enable 0 |
.equ PCIE1 = 1 ; Pin Change Interrupt Enable 1 |
.equ PCIE2 = 2 ; Pin Change Interrupt Enable 2 |
; PCIFR - Pin Change Interrupt Flag Register |
.equ PCIF0 = 0 ; Pin Change Interrupt Flag 0 |
.equ PCIF1 = 1 ; Pin Change Interrupt Flag 1 |
.equ PCIF2 = 2 ; Pin Change Interrupt Flag 2 |
; PCMSK2 - Pin Change Mask Register 2 |
.equ PCINT16 = 0 ; Pin Change Enable Mask 16 |
.equ PCINT17 = 1 ; Pin Change Enable Mask 17 |
.equ PCINT18 = 2 ; Pin Change Enable Mask 18 |
.equ PCINT19 = 3 ; Pin Change Enable Mask 19 |
.equ PCINT20 = 4 ; Pin Change Enable Mask 20 |
.equ PCINT21 = 5 ; Pin Change Enable Mask 21 |
.equ PCINT22 = 6 ; Pin Change Enable Mask 22 |
.equ PCINT23 = 7 ; Pin Change Enable Mask 23 |
; PCMSK1 - Pin Change Mask Register 1 |
.equ PCINT8 = 0 ; Pin Change Enable Mask 8 |
.equ PCINT9 = 1 ; Pin Change Enable Mask 9 |
.equ PCINT10 = 2 ; Pin Change Enable Mask 10 |
.equ PCINT11 = 3 ; Pin Change Enable Mask 11 |
.equ PCINT12 = 4 ; Pin Change Enable Mask 12 |
.equ PCINT13 = 5 ; Pin Change Enable Mask 13 |
.equ PCINT14 = 6 ; Pin Change Enable Mask 14 |
.equ PCINT15 = 7 ; Pin Change Enable Mask 15 |
; PCMSK0 - Pin Change Mask Register 0 |
.equ PCINT0 = 0 ; Pin Change Enable Mask 0 |
.equ PCINT1 = 1 ; Pin Change Enable Mask 1 |
.equ PCINT2 = 2 ; Pin Change Enable Mask 2 |
.equ PCINT3 = 3 ; Pin Change Enable Mask 3 |
.equ PCINT4 = 4 ; Pin Change Enable Mask 4 |
.equ PCINT5 = 5 ; Pin Change Enable Mask 5 |
.equ PCINT6 = 6 ; Pin Change Enable Mask 6 |
.equ PCINT7 = 7 ; Pin Change Enable Mask 7 |
; ***** CPU ************************** |
; SREG - Status Register |
.equ SREG_C = 0 ; Carry Flag |
.equ SREG_Z = 1 ; Zero Flag |
.equ SREG_N = 2 ; Negative Flag |
.equ SREG_V = 3 ; Two's Complement Overflow Flag |
.equ SREG_S = 4 |
.equ SREG_H = 5 ; Half Carry Flag |
.equ SREG_T = 6 ; Bit Copy Storage |
.equ SREG_I = 7 ; Global Interrupt Enable |
; MCUCR - MCU Control Register |
.equ IVCE = 0 ; Interrupt Vector Change Enable |
.equ IVSEL = 1 ; Interrupt Vector Select |
.equ PUD = 4 ; Pull-up disable |
;.equ JTD = 7 ; JTAG Interface Disable |
; MCUSR - MCU Status Register |
.equ PORF = 0 ; Power-on reset flag |
.equ EXTRF = 1 ; External Reset Flag |
.equ BORF = 2 ; Brown-out Reset Flag |
.equ WDRF = 3 ; Watchdog Reset Flag |
;.equ JTRF = 4 ; JTAG Reset Flag |
; XMCRA - External Memory Control Register A |
.equ SRW00 = 0 ; Wait state select bit lower page |
.equ SRW01 = 1 ; Wait state select bit lower page |
.equ SRW10 = 2 ; Wait state select bit upper page |
.equ SRW11 = 3 ; Wait state select bit upper page |
.equ SRL0 = 4 ; Wait state page limit |
.equ SRL1 = 5 ; Wait state page limit |
.equ SRL2 = 6 ; Wait state page limit |
.equ SRE = 7 ; External SRAM Enable |
; XMCRB - External Memory Control Register B |
.equ XMM0 = 0 ; External Memory High Mask |
.equ XMM1 = 1 ; External Memory High Mask |
.equ XMM2 = 2 ; External Memory High Mask |
.equ XMBK = 7 ; External Memory Bus Keeper Enable |
; OSCCAL - Oscillator Calibration Value |
.equ CAL0 = 0 ; Oscillator Calibration Value Bit0 |
.equ CAL1 = 1 ; Oscillator Calibration Value Bit1 |
.equ CAL2 = 2 ; Oscillator Calibration Value Bit2 |
.equ CAL3 = 3 ; Oscillator Calibration Value Bit3 |
.equ CAL4 = 4 ; Oscillator Calibration Value Bit4 |
.equ CAL5 = 5 ; Oscillator Calibration Value Bit5 |
.equ CAL6 = 6 ; Oscillator Calibration Value Bit6 |
.equ CAL7 = 7 ; Oscillator Calibration Value Bit7 |
; CLKPR - |
.equ CLKPS0 = 0 ; |
.equ CLKPS1 = 1 ; |
.equ CLKPS2 = 2 ; |
.equ CLKPS3 = 3 ; |
.equ CPKPCE = 7 ; |
; SMCR - Sleep Mode Control Register |
.equ SE = 0 ; Sleep Enable |
.equ SM0 = 1 ; Sleep Mode Select bit 0 |
.equ SM1 = 2 ; Sleep Mode Select bit 1 |
.equ SM2 = 3 ; Sleep Mode Select bit 2 |
; RAMPZ - RAM Page Z Select Register |
.equ RAMPZ0 = 0 ; RAM Page Z Select Register Bit 0 |
.equ RAMPZ1 = 1 ; RAM Page Z Select Register Bit 1 |
; EIND - Extended Indirect Register |
.equ EIND0 = 0 ; Bit 0 |
; GPIOR2 - General Purpose IO Register 2 |
.equ GPIOR20 = 0 ; General Purpose IO Register 2 bit 0 |
.equ GPIOR21 = 1 ; General Purpose IO Register 2 bit 1 |
.equ GPIOR22 = 2 ; General Purpose IO Register 2 bit 2 |
.equ GPIOR23 = 3 ; General Purpose IO Register 2 bit 3 |
.equ GPIOR24 = 4 ; General Purpose IO Register 2 bit 4 |
.equ GPIOR25 = 5 ; General Purpose IO Register 2 bit 5 |
.equ GPIOR26 = 6 ; General Purpose IO Register 2 bit 6 |
.equ GPIOR27 = 7 ; General Purpose IO Register 2 bit 7 |
; GPIOR1 - General Purpose IO Register 1 |
.equ GPIOR10 = 0 ; General Purpose IO Register 1 bit 0 |
.equ GPIOR11 = 1 ; General Purpose IO Register 1 bit 1 |
.equ GPIOR12 = 2 ; General Purpose IO Register 1 bit 2 |
.equ GPIOR13 = 3 ; General Purpose IO Register 1 bit 3 |
.equ GPIOR14 = 4 ; General Purpose IO Register 1 bit 4 |
.equ GPIOR15 = 5 ; General Purpose IO Register 1 bit 5 |
.equ GPIOR16 = 6 ; General Purpose IO Register 1 bit 6 |
.equ GPIOR17 = 7 ; General Purpose IO Register 1 bit 7 |
; GPIOR0 - General Purpose IO Register 0 |
.equ GPIOR00 = 0 ; General Purpose IO Register 0 bit 0 |
.equ GPIOR01 = 1 ; General Purpose IO Register 0 bit 1 |
.equ GPIOR02 = 2 ; General Purpose IO Register 0 bit 2 |
.equ GPIOR03 = 3 ; General Purpose IO Register 0 bit 3 |
.equ GPIOR04 = 4 ; General Purpose IO Register 0 bit 4 |
.equ GPIOR05 = 5 ; General Purpose IO Register 0 bit 5 |
.equ GPIOR06 = 6 ; General Purpose IO Register 0 bit 6 |
.equ GPIOR07 = 7 ; General Purpose IO Register 0 bit 7 |
; PRR1 - Power Reduction Register1 |
.equ PRUSART1 = 0 ; Power Reduction USART1 |
.equ PRUSART2 = 1 ; Power Reduction USART2 |
.equ PRUSART3 = 2 ; Power Reduction USART3 |
.equ PRTIM3 = 3 ; Power Reduction Timer/Counter3 |
.equ PRTIM4 = 4 ; Power Reduction Timer/Counter4 |
.equ PRTIM5 = 5 ; Power Reduction Timer/Counter5 |
; PRR0 - Power Reduction Register0 |
.equ PRADC = 0 ; Power Reduction ADC |
.equ PRUSART0 = 1 ; Power Reduction USART |
.equ PRSPI = 2 ; Power Reduction Serial Peripheral Interface |
.equ PRTIM1 = 3 ; Power Reduction Timer/Counter1 |
.equ PRTIM0 = 5 ; Power Reduction Timer/Counter0 |
.equ PRTIM2 = 6 ; Power Reduction Timer/Counter2 |
.equ PRTWI = 7 ; Power Reduction TWI |
; ***** AD_CONVERTER ***************** |
; ADMUX - The ADC multiplexer Selection Register |
.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits |
.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits |
.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits |
.equ MUX3 = 3 ; Analog Channel and Gain Selection Bits |
.equ MUX4 = 4 ; Analog Channel and Gain Selection Bits |
.equ ADLAR = 5 ; Left Adjust Result |
.equ REFS0 = 6 ; Reference Selection Bit 0 |
.equ REFS1 = 7 ; Reference Selection Bit 1 |
; ADCSRA - The ADC Control and Status register A |
.equ ADPS0 = 0 ; ADC Prescaler Select Bits |
.equ ADPS1 = 1 ; ADC Prescaler Select Bits |
.equ ADPS2 = 2 ; ADC Prescaler Select Bits |
.equ ADIE = 3 ; ADC Interrupt Enable |
.equ ADIF = 4 ; ADC Interrupt Flag |
.equ ADATE = 5 ; ADC Auto Trigger Enable |
.equ ADSC = 6 ; ADC Start Conversion |
.equ ADEN = 7 ; ADC Enable |
; ADCSRB - The ADC Control and Status register B |
.equ ADTS0 = 0 ; ADC Auto Trigger Source bit 0 |
.equ ADTS1 = 1 ; ADC Auto Trigger Source bit 1 |
.equ ADTS2 = 2 ; ADC Auto Trigger Source bit 2 |
.equ MUX5 = 3 ; Analog Channel and Gain Selection Bits |
;.equ ACME = 6 ; |
; ADCH - ADC Data Register High Byte |
.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0 |
.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1 |
.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2 |
.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3 |
.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4 |
.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5 |
.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6 |
.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7 |
; ADCL - ADC Data Register Low Byte |
.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0 |
.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1 |
.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2 |
.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3 |
.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4 |
.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5 |
.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6 |
.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7 |
; DIDR0 - Digital Input Disable Register |
.equ ADC0D = 0 ; |
.equ ADC1D = 1 ; |
.equ ADC2D = 2 ; |
.equ ADC3D = 3 ; |
.equ ADC4D = 4 ; |
.equ ADC5D = 5 ; |
.equ ADC6D = 6 ; |
.equ ADC7D = 7 ; |
; DIDR2 - Digital Input Disable Register |
.equ ADC8D = 0 ; |
.equ ADC9D = 1 ; |
.equ ADC10D = 2 ; |
.equ ADC11D = 3 ; |
.equ ADC12D = 4 ; |
.equ ADC13D = 5 ; |
.equ ADC14D = 6 ; |
.equ ADC15D = 7 ; |
; ***** BOOT_LOAD ******************** |
; SPMCSR - Store Program Memory Control Register |
.equ SPMEN = 0 ; Store Program Memory Enable |
.equ PGERS = 1 ; Page Erase |
.equ PGWRT = 2 ; Page Write |
.equ BLBSET = 3 ; Boot Lock Bit Set |
.equ RWWSRE = 4 ; Read While Write section read enable |
.equ SIGRD = 5 ; Signature Row Read |
.equ RWWSB = 6 ; Read While Write Section Busy |
.equ SPMIE = 7 ; SPM Interrupt Enable |
; ***** USART2 *********************** |
; UDR2 - USART I/O Data Register |
.equ UDR2_0 = 0 ; USART I/O Data Register bit 0 |
.equ UDR2_1 = 1 ; USART I/O Data Register bit 1 |
.equ UDR2_2 = 2 ; USART I/O Data Register bit 2 |
.equ UDR2_3 = 3 ; USART I/O Data Register bit 3 |
.equ UDR2_4 = 4 ; USART I/O Data Register bit 4 |
.equ UDR2_5 = 5 ; USART I/O Data Register bit 5 |
.equ UDR2_6 = 6 ; USART I/O Data Register bit 6 |
.equ UDR2_7 = 7 ; USART I/O Data Register bit 7 |
; UCSR2A - USART Control and Status Register A |
.equ MPCM2 = 0 ; Multi-processor Communication Mode |
.equ U2X2 = 1 ; Double the USART transmission speed |
.equ UPE2 = 2 ; Parity Error |
.equ DOR2 = 3 ; Data overRun |
.equ FE2 = 4 ; Framing Error |
.equ UDRE2 = 5 ; USART Data Register Empty |
.equ TXC2 = 6 ; USART Transmitt Complete |
.equ RXC2 = 7 ; USART Receive Complete |
; UCSR2B - USART Control and Status Register B |
.equ TXB82 = 0 ; Transmit Data Bit 8 |
.equ RXB82 = 1 ; Receive Data Bit 8 |
.equ UCSZ22 = 2 ; Character Size |
.equ TXEN2 = 3 ; Transmitter Enable |
.equ RXEN2 = 4 ; Receiver Enable |
.equ UDRIE2 = 5 ; USART Data register Empty Interrupt Enable |
.equ TXCIE2 = 6 ; TX Complete Interrupt Enable |
.equ RXCIE2 = 7 ; RX Complete Interrupt Enable |
; UCSR2C - USART Control and Status Register C |
.equ UCPOL2 = 0 ; Clock Polarity |
.equ UCSZ20_UCPHA2 = 1 ; Character Size |
.equ UCSZ21_UDORD2 = 2 ; Character Size |
.equ USBS2 = 3 ; Stop Bit Select |
.equ UPM20 = 4 ; Parity Mode Bit 0 |
.equ UPM21 = 5 ; Parity Mode Bit 1 |
.equ UMSEL20 = 6 ; USART Mode Select |
.equ UMSEL21 = 7 ; USART Mode Select |
; ***** USART3 *********************** |
; UDR3 - USART I/O Data Register |
.equ UDR3_0 = 0 ; USART I/O Data Register bit 0 |
.equ UDR3_1 = 1 ; USART I/O Data Register bit 1 |
.equ UDR3_2 = 2 ; USART I/O Data Register bit 2 |
.equ UDR3_3 = 3 ; USART I/O Data Register bit 3 |
.equ UDR3_4 = 4 ; USART I/O Data Register bit 4 |
.equ UDR3_5 = 5 ; USART I/O Data Register bit 5 |
.equ UDR3_6 = 6 ; USART I/O Data Register bit 6 |
.equ UDR3_7 = 7 ; USART I/O Data Register bit 7 |
; UCSR3A - USART Control and Status Register A |
.equ MPCM3 = 0 ; Multi-processor Communication Mode |
.equ U2X3 = 1 ; Double the USART transmission speed |
.equ UPE3 = 2 ; Parity Error |
.equ DOR3 = 3 ; Data overRun |
.equ FE3 = 4 ; Framing Error |
.equ UDRE3 = 5 ; USART Data Register Empty |
.equ TXC3 = 6 ; USART Transmitt Complete |
.equ RXC3 = 7 ; USART Receive Complete |
; UCSR3B - USART Control and Status Register B |
.equ TXB83 = 0 ; Transmit Data Bit 8 |
.equ RXB83 = 1 ; Receive Data Bit 8 |
.equ UCSZ32 = 2 ; Character Size |
.equ TXEN3 = 3 ; Transmitter Enable |
.equ RXEN3 = 4 ; Receiver Enable |
.equ UDRIE3 = 5 ; USART Data register Empty Interrupt Enable |
.equ TXCIE3 = 6 ; TX Complete Interrupt Enable |
.equ RXCIE3 = 7 ; RX Complete Interrupt Enable |
; UCSR3C - USART Control and Status Register C |
.equ UCPOL3 = 0 ; Clock Polarity |
.equ UCSZ30_UCPHA3 = 1 ; Character Size |
.equ UCSZ31_UDORD3 = 2 ; Character Size |
.equ USBS3 = 3 ; Stop Bit Select |
.equ UPM30 = 4 ; Parity Mode Bit 0 |
.equ UPM31 = 5 ; Parity Mode Bit 1 |
.equ UMSEL30 = 6 ; USART Mode Select |
.equ UMSEL31 = 7 ; USART Mode Select |
; ***** LOCKSBITS ******************************************************** |
.equ LB1 = 0 ; Lock bit |
.equ LB2 = 1 ; Lock bit |
.equ BLB01 = 2 ; Boot Lock bit |
.equ BLB02 = 3 ; Boot Lock bit |
.equ BLB11 = 4 ; Boot lock bit |
.equ BLB12 = 5 ; Boot lock bit |
; ***** FUSES ************************************************************ |
; LOW fuse bits |
.equ CKSEL0 = 0 ; Select Clock Source |
.equ CKSEL1 = 1 ; Select Clock Source |
.equ CKSEL2 = 2 ; Select Clock Source |
.equ CKSEL3 = 3 ; Select Clock Source |
.equ SUT0 = 4 ; Select start-up time |
.equ SUT1 = 5 ; Select start-up time |
.equ CKOUT = 6 ; Oscillator options |
.equ CLKDIV8 = 7 ; Divide clock by 8 |
; HIGH fuse bits |
.equ BOOTRST = 0 ; Select Reset Vector |
.equ BOOTSZ0 = 1 ; Select Boot Size |
.equ BOOTSZ1 = 2 ; Select Boot Size |
.equ EESAVE = 3 ; EEPROM memory is preserved through chip erase |
.equ WDTON = 4 ; Watchdog timer always on |
.equ SPIEN = 5 ; Enable Serial programming and Data Downloading |
.equ JTAGEN = 6 ; Enable JTAG |
.equ OCDEN = 7 ; Enable OCD |
; EXTENDED fuse bits |
.equ BODLEVEL0 = 0 ; Brown-out Detector trigger level |
.equ BODLEVEL1 = 1 ; Brown-out Detector trigger level |
.equ BODLEVEL2 = 2 ; Brown-out Detector trigger level |
; ***** CPU REGISTER DEFINITIONS ***************************************** |
.def XH = r27 |
.def XL = r26 |
.def YH = r29 |
.def YL = r28 |
.def ZH = r31 |
.def ZL = r30 |
; ***** DATA MEMORY DECLARATIONS ***************************************** |
.equ FLASHEND = 0x1ffff ; Note: Word address |
.equ IOEND = 0x01ff |
.equ SRAM_START = 0x0200 |
.equ SRAM_SIZE = 8192 |
.equ RAMEND = 0x21ff |
.equ XRAMEND = 0xffff |
.equ E2END = 0x0fff |
.equ EEPROMEND = 0x0fff |
.equ EEADRBITS = 12 |
#pragma AVRPART MEMORY PROG_FLASH 262144 |
#pragma AVRPART MEMORY EEPROM 4096 |
#pragma AVRPART MEMORY INT_SRAM SIZE 8192 |
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x200 |
; ***** BOOTLOADER DECLARATIONS ****************************************** |
.equ NRWW_START_ADDR = 0x1f000 |
.equ NRWW_STOP_ADDR = 0x1ffff |
.equ RWW_START_ADDR = 0x0 |
.equ RWW_STOP_ADDR = 0x1efff |
.equ PAGESIZE = 128 |
.equ FIRSTBOOTSTART = 0x1fe00 |
.equ SECONDBOOTSTART = 0x1fc00 |
.equ THIRDBOOTSTART = 0x1f800 |
.equ FOURTHBOOTSTART = 0x1f000 |
.equ SMALLBOOTSTART = FIRSTBOOTSTART |
.equ LARGEBOOTSTART = FOURTHBOOTSTART |
; ***** INTERRUPT VECTORS ************************************************ |
.equ INT0addr = 0x0002 ; External Interrupt Request 0 |
.equ INT1addr = 0x0004 ; External Interrupt Request 1 |
.equ INT2addr = 0x0006 ; External Interrupt Request 2 |
.equ INT3addr = 0x0008 ; External Interrupt Request 3 |
.equ INT4addr = 0x000a ; External Interrupt Request 4 |
.equ INT5addr = 0x000c ; External Interrupt Request 5 |
.equ INT6addr = 0x000e ; External Interrupt Request 6 |
.equ INT7addr = 0x0010 ; External Interrupt Request 7 |
.equ PCI0addr = 0x0012 ; Pin Change Interrupt Request 0 |
.equ PCI1addr = 0x0014 ; Pin Change Interrupt Request 1 |
.equ PCI2addr = 0x0016 ; Pin Change Interrupt Request 2 |
.equ WDTaddr = 0x0018 ; Watchdog Time-out Interrupt |
.equ OC2Aaddr = 0x001a ; Timer/Counter2 Compare Match A |
.equ OC2Baddr = 0x001c ; Timer/Counter2 Compare Match B |
.equ OVF2addr = 0x001e ; Timer/Counter2 Overflow |
.equ ICP1addr = 0x0020 ; Timer/Counter1 Capture Event |
.equ OC1Aaddr = 0x0022 ; Timer/Counter1 Compare Match A |
.equ OC1Baddr = 0x0024 ; Timer/Counter1 Compare Match B |
.equ OC1Caddr = 0x0026 ; Timer/Counter1 Compare Match C |
.equ OVF1addr = 0x0028 ; Timer/Counter1 Overflow |
.equ OC0Aaddr = 0x002a ; Timer/Counter0 Compare Match A |
.equ OC0Baddr = 0x002c ; Timer/Counter0 Compare Match B |
.equ OVF0addr = 0x002e ; Timer/Counter0 Overflow |
.equ SPIaddr = 0x0030 ; SPI Serial Transfer Complete |
.equ URXC0addr = 0x0032 ; USART0, Rx Complete |
.equ UDRE0addr = 0x0034 ; USART0 Data register Empty |
.equ UTXC0addr = 0x0036 ; USART0, Tx Complete |
.equ ACIaddr = 0x0038 ; Analog Comparator |
.equ ADCCaddr = 0x003a ; ADC Conversion Complete |
.equ ERDYaddr = 0x003c ; EEPROM Ready |
.equ ICP3addr = 0x003e ; Timer/Counter3 Capture Event |
.equ OC3Aaddr = 0x0040 ; Timer/Counter3 Compare Match A |
.equ OC3Baddr = 0x0042 ; Timer/Counter3 Compare Match B |
.equ OC3Caddr = 0x0044 ; Timer/Counter3 Compare Match C |
.equ OVF3addr = 0x0046 ; Timer/Counter3 Overflow |
.equ URXC1addr = 0x0048 ; USART1, Rx Complete |
.equ UDRE1addr = 0x004a ; USART1 Data register Empty |
.equ UTXC1addr = 0x004c ; USART1, Tx Complete |
.equ TWIaddr = 0x004e ; 2-wire Serial Interface |
.equ SPMRaddr = 0x0050 ; Store Program Memory Read |
.equ ICP4addr = 0x0052 ; Timer/Counter4 Capture Event |
.equ OC4Aaddr = 0x0054 ; Timer/Counter4 Compare Match A |
.equ OC4Baddr = 0x0056 ; Timer/Counter4 Compare Match B |
.equ OC4Caddr = 0x0058 ; Timer/Counter4 Compare Match C |
.equ OVF4addr = 0x005a ; Timer/Counter4 Overflow |
.equ ICP5addr = 0x005c ; Timer/Counter5 Capture Event |
.equ OC5Aaddr = 0x005e ; Timer/Counter5 Compare Match A |
.equ OC5Baddr = 0x0060 ; Timer/Counter5 Compare Match B |
.equ OC5Caddr = 0x0062 ; Timer/Counter5 Compare Match C |
.equ OVF5addr = 0x0064 ; Timer/Counter5 Overflow |
.equ URXC2addr = 0x0066 ; USART2, Rx Complete |
.equ UDRE2addr = 0x0068 ; USART2 Data register Empty |
.equ UTXC2addr = 0x006a ; USART2, Tx Complete |
.equ URXC3addr = 0x006c ; USART3, Rx Complete |
.equ UDRE3addr = 0x006e ; USART3 Data register Empty |
.equ UTXC3addr = 0x0070 ; USART3, Tx Complete |
.equ INT_VECTORS_SIZE = 114 ; size in words |
#endif /* _M2560DEF_INC_ */ |
; ***** END OF FILE ****************************************************** |
/contrib/toolchain/avra/includes/m2561def.inc |
---|
0,0 → 1,1516 |
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** |
;***** Created: 2005-01-11 10:31 ******* Source: ATmega2561.xml ********** |
;************************************************************************* |
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y |
;* |
;* Number : AVR000 |
;* File Name : "m2561def.inc" |
;* Title : Register/Bit Definitions for the ATmega2561 |
;* Date : 2005-01-11 |
;* Version : 2.14 |
;* Support E-mail : avr@atmel.com |
;* Target MCU : ATmega2561 |
;* |
;* DESCRIPTION |
;* When including this file in the assembly program file, all I/O register |
;* names and I/O register bit names appearing in the data book can be used. |
;* In addition, the six registers forming the three data pointers X, Y and |
;* Z have been assigned names XL - ZH. Highest RAM address for Internal |
;* SRAM is also defined |
;* |
;* The Register names are represented by their hexadecimal address. |
;* |
;* The Register Bit names are represented by their bit number (0-7). |
;* |
;* Please observe the difference in using the bit names with instructions |
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" |
;* (skip if bit in register set/cleared). The following example illustrates |
;* this: |
;* |
;* in r16,PORTB ;read PORTB latch |
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) |
;* out PORTB,r16 ;output to PORTB |
;* |
;* in r16,TIFR ;read the Timer Interrupt Flag Register |
;* sbrc r16,TOV0 ;test the overflow flag (use bit#) |
;* rjmp TOV0_is_set ;jump if set |
;* ... ;otherwise do something else |
;************************************************************************* |
#ifndef _M2561DEF_INC_ |
#define _M2561DEF_INC_ |
#pragma partinc 0 |
; ***** SPECIFY DEVICE *************************************************** |
.device ATmega2561 |
#pragma AVRPART ADMIN PART_NAME ATmega2561 |
.equ SIGNATURE_000 = 0x1e |
.equ SIGNATURE_001 = 0x98 |
.equ SIGNATURE_002 = 0x02 |
#pragma AVRPART CORE CORE_VERSION V3 |
; ***** I/O REGISTER DEFINITIONS ***************************************** |
; NOTE: |
; Definitions marked "MEMORY MAPPED"are extended I/O ports |
; and cannot be used with IN/OUT instructions |
.equ UDR3 = 0x136 ; MEMORY MAPPED |
.equ UBRR3H = 0x135 ; MEMORY MAPPED |
.equ UBRR3L = 0x134 ; MEMORY MAPPED |
.equ UCSR3C = 0x132 ; MEMORY MAPPED |
.equ UCSR3B = 0x131 ; MEMORY MAPPED |
.equ UCSR3A = 0x130 ; MEMORY MAPPED |
.equ OCR5CH = 0x12d ; MEMORY MAPPED |
.equ OCR5CL = 0x12c ; MEMORY MAPPED |
.equ OCR5BH = 0x12b ; MEMORY MAPPED |
.equ OCR5BL = 0x12a ; MEMORY MAPPED |
.equ OCR5AH = 0x129 ; MEMORY MAPPED |
.equ OCR5AL = 0x128 ; MEMORY MAPPED |
.equ ICR5H = 0x127 ; MEMORY MAPPED |
.equ ICR5L = 0x126 ; MEMORY MAPPED |
.equ TCNT5H = 0x125 ; MEMORY MAPPED |
.equ TCNT5L = 0x124 ; MEMORY MAPPED |
.equ TCCR5C = 0x122 ; MEMORY MAPPED |
.equ TCCR5B = 0x121 ; MEMORY MAPPED |
.equ TCCR5A = 0x120 ; MEMORY MAPPED |
.equ PORTL = 0x10b ; MEMORY MAPPED |
.equ DDRL = 0x10a ; MEMORY MAPPED |
.equ PINL = 0x109 ; MEMORY MAPPED |
.equ PORTK = 0x108 ; MEMORY MAPPED |
.equ DDRK = 0x107 ; MEMORY MAPPED |
.equ PINK = 0x106 ; MEMORY MAPPED |
.equ PORTJ = 0x105 ; MEMORY MAPPED |
.equ DDRJ = 0x104 ; MEMORY MAPPED |
.equ PINJ = 0x103 ; MEMORY MAPPED |
.equ PORTH = 0x102 ; MEMORY MAPPED |
.equ DDRH = 0x101 ; MEMORY MAPPED |
.equ PINH = 0x100 ; MEMORY MAPPED |
.equ UDR2 = 0xd6 ; MEMORY MAPPED |
.equ UBRR2H = 0xd5 ; MEMORY MAPPED |
.equ UBRR2L = 0xd4 ; MEMORY MAPPED |
.equ UCSR2C = 0xd2 ; MEMORY MAPPED |
.equ UCSR2B = 0xd1 ; MEMORY MAPPED |
.equ UCSR2A = 0xd0 ; MEMORY MAPPED |
.equ UDR1 = 0xce ; MEMORY MAPPED |
.equ UBRR1H = 0xcd ; MEMORY MAPPED |
.equ UBRR1L = 0xcc ; MEMORY MAPPED |
.equ UCSR1C = 0xca ; MEMORY MAPPED |
.equ UCSR1B = 0xc9 ; MEMORY MAPPED |
.equ UCSR1A = 0xc8 ; MEMORY MAPPED |
.equ UDR0 = 0xc6 ; MEMORY MAPPED |
.equ UBRR0H = 0xc5 ; MEMORY MAPPED |
.equ UBRR0L = 0xc4 ; MEMORY MAPPED |
.equ UCSR0C = 0xc2 ; MEMORY MAPPED |
.equ UCSR0B = 0xc1 ; MEMORY MAPPED |
.equ UCSR0A = 0xc0 ; MEMORY MAPPED |
.equ TWAMR = 0xbd ; MEMORY MAPPED |
.equ TWCR = 0xbc ; MEMORY MAPPED |
.equ TWDR = 0xbb ; MEMORY MAPPED |
.equ TWAR = 0xba ; MEMORY MAPPED |
.equ TWSR = 0xb9 ; MEMORY MAPPED |
.equ TWBR = 0xb8 ; MEMORY MAPPED |
.equ ASSR = 0xb6 ; MEMORY MAPPED |
.equ OCR2B = 0xb4 ; MEMORY MAPPED |
.equ OCR2A = 0xb3 ; MEMORY MAPPED |
.equ TCNT2 = 0xb2 ; MEMORY MAPPED |
.equ TCCR2B = 0xb1 ; MEMORY MAPPED |
.equ TCCR2A = 0xb0 ; MEMORY MAPPED |
.equ OCR4CH = 0xad ; MEMORY MAPPED |
.equ OCR4CL = 0xac ; MEMORY MAPPED |
.equ OCR4BH = 0xab ; MEMORY MAPPED |
.equ OCR4BL = 0xaa ; MEMORY MAPPED |
.equ OCR4AH = 0xa9 ; MEMORY MAPPED |
.equ OCR4AL = 0xa8 ; MEMORY MAPPED |
.equ ICR4H = 0xa7 ; MEMORY MAPPED |
.equ ICR4L = 0xa6 ; MEMORY MAPPED |
.equ TCNT4H = 0xa5 ; MEMORY MAPPED |
.equ TCNT4L = 0xa4 ; MEMORY MAPPED |
.equ TCCR4C = 0xa2 ; MEMORY MAPPED |
.equ TCCR4B = 0xa1 ; MEMORY MAPPED |
.equ TCCR4A = 0xa0 ; MEMORY MAPPED |
.equ OCR3CH = 0x9d ; MEMORY MAPPED |
.equ OCR3CL = 0x9c ; MEMORY MAPPED |
.equ OCR3BH = 0x9b ; MEMORY MAPPED |
.equ OCR3BL = 0x9a ; MEMORY MAPPED |
.equ OCR3AH = 0x99 ; MEMORY MAPPED |
.equ OCR3AL = 0x98 ; MEMORY MAPPED |
.equ ICR3H = 0x97 ; MEMORY MAPPED |
.equ ICR3L = 0x96 ; MEMORY MAPPED |
.equ TCNT3H = 0x95 ; MEMORY MAPPED |
.equ TCNT3L = 0x94 ; MEMORY MAPPED |
.equ TCCR3C = 0x92 ; MEMORY MAPPED |
.equ TCCR3B = 0x91 ; MEMORY MAPPED |
.equ TCCR3A = 0x90 ; MEMORY MAPPED |
.equ OCR1CH = 0x8d ; MEMORY MAPPED |
.equ OCR1CL = 0x8c ; MEMORY MAPPED |
.equ OCR1BH = 0x8b ; MEMORY MAPPED |
.equ OCR1BL = 0x8a ; MEMORY MAPPED |
.equ OCR1AH = 0x89 ; MEMORY MAPPED |
.equ OCR1AL = 0x88 ; MEMORY MAPPED |
.equ ICR1H = 0x87 ; MEMORY MAPPED |
.equ ICR1L = 0x86 ; MEMORY MAPPED |
.equ TCNT1H = 0x85 ; MEMORY MAPPED |
.equ TCNT1L = 0x84 ; MEMORY MAPPED |
.equ TCCR1C = 0x82 ; MEMORY MAPPED |
.equ TCCR1B = 0x81 ; MEMORY MAPPED |
.equ TCCR1A = 0x80 ; MEMORY MAPPED |
.equ DIDR1 = 0x7f ; MEMORY MAPPED |
.equ DIDR0 = 0x7e ; MEMORY MAPPED |
.equ DIDR2 = 0x7d ; MEMORY MAPPED |
.equ ADMUX = 0x7c ; MEMORY MAPPED |
.equ ADCSRB = 0x7b ; MEMORY MAPPED |
.equ ADCSRA = 0x7a ; MEMORY MAPPED |
.equ ADCH = 0x79 ; MEMORY MAPPED |
.equ ADCL = 0x78 ; MEMORY MAPPED |
.equ XMCRB = 0x75 ; MEMORY MAPPED |
.equ XMCRA = 0x74 ; MEMORY MAPPED |
.equ TIMSK5 = 0x73 ; MEMORY MAPPED |
.equ TIMSK4 = 0x72 ; MEMORY MAPPED |
.equ TIMSK3 = 0x71 ; MEMORY MAPPED |
.equ TIMSK2 = 0x70 ; MEMORY MAPPED |
.equ TIMSK1 = 0x6f ; MEMORY MAPPED |
.equ TIMSK0 = 0x6e ; MEMORY MAPPED |
.equ PCMSK2 = 0x6d ; MEMORY MAPPED |
.equ PCMSK1 = 0x6c ; MEMORY MAPPED |
.equ PCMSK0 = 0x6b ; MEMORY MAPPED |
.equ EICRB = 0x6a ; MEMORY MAPPED |
.equ EICRA = 0x69 ; MEMORY MAPPED |
.equ PCICR = 0x68 ; MEMORY MAPPED |
.equ OSCCAL = 0x66 ; MEMORY MAPPED |
.equ PRR1 = 0x65 ; MEMORY MAPPED |
.equ PRR0 = 0x64 ; MEMORY MAPPED |
.equ CLKPR = 0x61 ; MEMORY MAPPED |
.equ WDTCSR = 0x60 ; MEMORY MAPPED |
.equ SREG = 0x3f |
.equ SPH = 0x3e |
.equ SPL = 0x3d |
.equ EIND = 0x3c |
.equ RAMPZ = 0x3b |
.equ SPMCSR = 0x37 |
.equ MCUCR = 0x35 |
.equ MCUSR = 0x34 |
.equ SMCR = 0x33 |
.equ OCDR = 0x31 |
.equ ACSR = 0x30 |
.equ SPDR = 0x2e |
.equ SPSR = 0x2d |
.equ SPCR = 0x2c |
.equ GPIOR2 = 0x2b |
.equ GPIOR1 = 0x2a |
.equ OCR0B = 0x28 |
.equ OCR0A = 0x27 |
.equ TCNT0 = 0x26 |
.equ TCCR0B = 0x25 |
.equ TCCR0A = 0x24 |
.equ GTCCR = 0x23 |
.equ EEARH = 0x22 |
.equ EEARL = 0x21 |
.equ EEDR = 0x20 |
.equ EECR = 0x1f |
.equ GPIOR0 = 0x1e |
.equ EIMSK = 0x1d |
.equ EIFR = 0x1c |
.equ PCIFR = 0x1b |
.equ TIFR5 = 0x1a |
.equ TIFR4 = 0x19 |
.equ TIFR3 = 0x18 |
.equ TIFR2 = 0x17 |
.equ TIFR1 = 0x16 |
.equ TIFR0 = 0x15 |
.equ PORTG = 0x14 |
.equ DDRG = 0x13 |
.equ PING = 0x12 |
.equ PORTF = 0x11 |
.equ DDRF = 0x10 |
.equ PINF = 0x0f |
.equ PORTE = 0x0e |
.equ DDRE = 0x0d |
.equ PINE = 0x0c |
.equ PORTD = 0x0b |
.equ DDRD = 0x0a |
.equ PIND = 0x09 |
.equ PORTC = 0x08 |
.equ DDRC = 0x07 |
.equ PINC = 0x06 |
.equ PORTB = 0x05 |
.equ DDRB = 0x04 |
.equ PINB = 0x03 |
.equ PORTA = 0x02 |
.equ DDRA = 0x01 |
.equ PINA = 0x00 |
; ***** BIT DEFINITIONS ************************************************** |
; ***** ANALOG_COMPARATOR ************ |
; ADCSRB - ADC Control and Status Register B |
.equ ACME = 6 ; Analog Comparator Multiplexer Enable |
; ACSR - Analog Comparator Control And Status Register |
.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 |
.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 |
.equ ACIC = 2 ; Analog Comparator Input Capture Enable |
.equ ACIE = 3 ; Analog Comparator Interrupt Enable |
.equ ACI = 4 ; Analog Comparator Interrupt Flag |
.equ ACO = 5 ; Analog Compare Output |
.equ ACBG = 6 ; Analog Comparator Bandgap Select |
.equ ACD = 7 ; Analog Comparator Disable |
; DIDR1 - Digital Input Disable Register 1 |
.equ AIN0D = 0 ; AIN0 Digital Input Disable |
.equ AIN1D = 1 ; AIN1 Digital Input Disable |
; ***** USART0 *********************** |
; UDR0 - USART I/O Data Register |
.equ UDR0_0 = 0 ; USART I/O Data Register bit 0 |
.equ UDR0_1 = 1 ; USART I/O Data Register bit 1 |
.equ UDR0_2 = 2 ; USART I/O Data Register bit 2 |
.equ UDR0_3 = 3 ; USART I/O Data Register bit 3 |
.equ UDR0_4 = 4 ; USART I/O Data Register bit 4 |
.equ UDR0_5 = 5 ; USART I/O Data Register bit 5 |
.equ UDR0_6 = 6 ; USART I/O Data Register bit 6 |
.equ UDR0_7 = 7 ; USART I/O Data Register bit 7 |
; UCSR0A - USART Control and Status Register A |
.equ MPCM0 = 0 ; Multi-processor Communication Mode |
.equ U2X0 = 1 ; Double the USART transmission speed |
.equ UPE0 = 2 ; Parity Error |
.equ DOR0 = 3 ; Data overRun |
.equ FE0 = 4 ; Framing Error |
.equ UDRE0 = 5 ; USART Data Register Empty |
.equ TXC0 = 6 ; USART Transmitt Complete |
.equ RXC0 = 7 ; USART Receive Complete |
; UCSR0B - USART Control and Status Register B |
.equ TXB80 = 0 ; Transmit Data Bit 8 |
.equ RXB80 = 1 ; Receive Data Bit 8 |
.equ UCSZ02 = 2 ; Character Size |
.equ TXEN0 = 3 ; Transmitter Enable |
.equ RXEN0 = 4 ; Receiver Enable |
.equ UDRIE0 = 5 ; USART Data register Empty Interrupt Enable |
.equ TXCIE0 = 6 ; TX Complete Interrupt Enable |
.equ RXCIE0 = 7 ; RX Complete Interrupt Enable |
; UCSR0C - USART Control and Status Register C |
.equ UCPOL0 = 0 ; Clock Polarity |
.equ UCSZ00 = 1 ; Character Size |
.equ UCPHA0 = UCSZ00 ; For compatibility |
.equ UCSZ01 = 2 ; Character Size |
.equ UDORD0 = UCSZ01 ; For compatibility |
.equ USBS0 = 3 ; Stop Bit Select |
.equ UPM00 = 4 ; Parity Mode Bit 0 |
.equ UPM01 = 5 ; Parity Mode Bit 1 |
.equ UMSEL00 = 6 ; USART Mode Select |
.equ UMSEL0 = UMSEL00 ; For compatibility |
.equ UMSEL01 = 7 ; USART Mode Select |
.equ UMSEL1 = UMSEL01 ; For compatibility |
; ***** TWI ************************** |
; TWAMR - TWI (Slave) Address Mask Register |
.equ TWAM0 = 1 ; |
.equ TWAMR0 = TWAM0 ; For compatibility |
.equ TWAM1 = 2 ; |
.equ TWAMR1 = TWAM1 ; For compatibility |
.equ TWAM2 = 3 ; |
.equ TWAMR2 = TWAM2 ; For compatibility |
.equ TWAM3 = 4 ; |
.equ TWAMR3 = TWAM3 ; For compatibility |
.equ TWAM4 = 5 ; |
.equ TWAMR4 = TWAM4 ; For compatibility |
.equ TWAM5 = 6 ; |
.equ TWAMR5 = TWAM5 ; For compatibility |
.equ TWAM6 = 7 ; |
.equ TWAMR6 = TWAM6 ; For compatibility |
; TWBR - TWI Bit Rate register |
.equ TWBR0 = 0 ; |
.equ TWBR1 = 1 ; |
.equ TWBR2 = 2 ; |
.equ TWBR3 = 3 ; |
.equ TWBR4 = 4 ; |
.equ TWBR5 = 5 ; |
.equ TWBR6 = 6 ; |
.equ TWBR7 = 7 ; |
; TWCR - TWI Control Register |
.equ TWIE = 0 ; TWI Interrupt Enable |
.equ TWEN = 2 ; TWI Enable Bit |
.equ TWWC = 3 ; TWI Write Collition Flag |
.equ TWSTO = 4 ; TWI Stop Condition Bit |
.equ TWSTA = 5 ; TWI Start Condition Bit |
.equ TWEA = 6 ; TWI Enable Acknowledge Bit |
.equ TWINT = 7 ; TWI Interrupt Flag |
; TWSR - TWI Status Register |
.equ TWPS0 = 0 ; TWI Prescaler |
.equ TWPS1 = 1 ; TWI Prescaler |
.equ TWS3 = 3 ; TWI Status |
.equ TWS4 = 4 ; TWI Status |
.equ TWS5 = 5 ; TWI Status |
.equ TWS6 = 6 ; TWI Status |
.equ TWS7 = 7 ; TWI Status |
; TWDR - TWI Data register |
.equ TWD0 = 0 ; TWI Data Register Bit 0 |
.equ TWD1 = 1 ; TWI Data Register Bit 1 |
.equ TWD2 = 2 ; TWI Data Register Bit 2 |
.equ TWD3 = 3 ; TWI Data Register Bit 3 |
.equ TWD4 = 4 ; TWI Data Register Bit 4 |
.equ TWD5 = 5 ; TWI Data Register Bit 5 |
.equ TWD6 = 6 ; TWI Data Register Bit 6 |
.equ TWD7 = 7 ; TWI Data Register Bit 7 |
; TWAR - TWI (Slave) Address register |
.equ TWGCE = 0 ; TWI General Call Recognition Enable Bit |
.equ TWA0 = 1 ; TWI (Slave) Address register Bit 0 |
.equ TWA1 = 2 ; TWI (Slave) Address register Bit 1 |
.equ TWA2 = 3 ; TWI (Slave) Address register Bit 2 |
.equ TWA3 = 4 ; TWI (Slave) Address register Bit 3 |
.equ TWA4 = 5 ; TWI (Slave) Address register Bit 4 |
.equ TWA5 = 6 ; TWI (Slave) Address register Bit 5 |
.equ TWA6 = 7 ; TWI (Slave) Address register Bit 6 |
; ***** SPI ************************** |
; SPDR - SPI Data Register |
.equ SPDR0 = 0 ; SPI Data Register bit 0 |
.equ SPDR1 = 1 ; SPI Data Register bit 1 |
.equ SPDR2 = 2 ; SPI Data Register bit 2 |
.equ SPDR3 = 3 ; SPI Data Register bit 3 |
.equ SPDR4 = 4 ; SPI Data Register bit 4 |
.equ SPDR5 = 5 ; SPI Data Register bit 5 |
.equ SPDR6 = 6 ; SPI Data Register bit 6 |
.equ SPDR7 = 7 ; SPI Data Register bit 7 |
; SPSR - SPI Status Register |
.equ SPI2X = 0 ; Double SPI Speed Bit |
.equ WCOL = 6 ; Write Collision Flag |
.equ SPIF = 7 ; SPI Interrupt Flag |
; SPCR - SPI Control Register |
.equ SPR0 = 0 ; SPI Clock Rate Select 0 |
.equ SPR1 = 1 ; SPI Clock Rate Select 1 |
.equ CPHA = 2 ; Clock Phase |
.equ CPOL = 3 ; Clock polarity |
.equ MSTR = 4 ; Master/Slave Select |
.equ DORD = 5 ; Data Order |
.equ SPE = 6 ; SPI Enable |
.equ SPIE = 7 ; SPI Interrupt Enable |
; ***** PORTA ************************ |
; PORTA - Port A Data Register |
.equ PORTA0 = 0 ; Port A Data Register bit 0 |
.equ PA0 = 0 ; For compatibility |
.equ PORTA1 = 1 ; Port A Data Register bit 1 |
.equ PA1 = 1 ; For compatibility |
.equ PORTA2 = 2 ; Port A Data Register bit 2 |
.equ PA2 = 2 ; For compatibility |
.equ PORTA3 = 3 ; Port A Data Register bit 3 |
.equ PA3 = 3 ; For compatibility |
.equ PORTA4 = 4 ; Port A Data Register bit 4 |
.equ PA4 = 4 ; For compatibility |
.equ PORTA5 = 5 ; Port A Data Register bit 5 |
.equ PA5 = 5 ; For compatibility |
.equ PORTA6 = 6 ; Port A Data Register bit 6 |
.equ PA6 = 6 ; For compatibility |
.equ PORTA7 = 7 ; Port A Data Register bit 7 |
.equ PA7 = 7 ; For compatibility |
; DDRA - Port A Data Direction Register |
.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0 |
.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1 |
.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2 |
.equ DDA3 = 3 ; Data Direction Register, Port A, bit 3 |
.equ DDA4 = 4 ; Data Direction Register, Port A, bit 4 |
.equ DDA5 = 5 ; Data Direction Register, Port A, bit 5 |
.equ DDA6 = 6 ; Data Direction Register, Port A, bit 6 |
.equ DDA7 = 7 ; Data Direction Register, Port A, bit 7 |
; PINA - Port A Input Pins |
.equ PINA0 = 0 ; Input Pins, Port A bit 0 |
.equ PINA1 = 1 ; Input Pins, Port A bit 1 |
.equ PINA2 = 2 ; Input Pins, Port A bit 2 |
.equ PINA3 = 3 ; Input Pins, Port A bit 3 |
.equ PINA4 = 4 ; Input Pins, Port A bit 4 |
.equ PINA5 = 5 ; Input Pins, Port A bit 5 |
.equ PINA6 = 6 ; Input Pins, Port A bit 6 |
.equ PINA7 = 7 ; Input Pins, Port A bit 7 |
; ***** PORTB ************************ |
; PORTB - Port B Data Register |
.equ PORTB0 = 0 ; Port B Data Register bit 0 |
.equ PB0 = 0 ; For compatibility |
.equ PORTB1 = 1 ; Port B Data Register bit 1 |
.equ PB1 = 1 ; For compatibility |
.equ PORTB2 = 2 ; Port B Data Register bit 2 |
.equ PB2 = 2 ; For compatibility |
.equ PORTB3 = 3 ; Port B Data Register bit 3 |
.equ PB3 = 3 ; For compatibility |
.equ PORTB4 = 4 ; Port B Data Register bit 4 |
.equ PB4 = 4 ; For compatibility |
.equ PORTB5 = 5 ; Port B Data Register bit 5 |
.equ PB5 = 5 ; For compatibility |
.equ PORTB6 = 6 ; Port B Data Register bit 6 |
.equ PB6 = 6 ; For compatibility |
.equ PORTB7 = 7 ; Port B Data Register bit 7 |
.equ PB7 = 7 ; For compatibility |
; DDRB - Port B Data Direction Register |
.equ DDB0 = 0 ; Port B Data Direction Register bit 0 |
.equ DDB1 = 1 ; Port B Data Direction Register bit 1 |
.equ DDB2 = 2 ; Port B Data Direction Register bit 2 |
.equ DDB3 = 3 ; Port B Data Direction Register bit 3 |
.equ DDB4 = 4 ; Port B Data Direction Register bit 4 |
.equ DDB5 = 5 ; Port B Data Direction Register bit 5 |
.equ DDB6 = 6 ; Port B Data Direction Register bit 6 |
.equ DDB7 = 7 ; Port B Data Direction Register bit 7 |
; PINB - Port B Input Pins |
.equ PINB0 = 0 ; Port B Input Pins bit 0 |
.equ PINB1 = 1 ; Port B Input Pins bit 1 |
.equ PINB2 = 2 ; Port B Input Pins bit 2 |
.equ PINB3 = 3 ; Port B Input Pins bit 3 |
.equ PINB4 = 4 ; Port B Input Pins bit 4 |
.equ PINB5 = 5 ; Port B Input Pins bit 5 |
.equ PINB6 = 6 ; Port B Input Pins bit 6 |
.equ PINB7 = 7 ; Port B Input Pins bit 7 |
; ***** PORTC ************************ |
; PORTC - Port C Data Register |
.equ PORTC0 = 0 ; Port C Data Register bit 0 |
.equ PC0 = 0 ; For compatibility |
.equ PORTC1 = 1 ; Port C Data Register bit 1 |
.equ PC1 = 1 ; For compatibility |
.equ PORTC2 = 2 ; Port C Data Register bit 2 |
.equ PC2 = 2 ; For compatibility |
.equ PORTC3 = 3 ; Port C Data Register bit 3 |
.equ PC3 = 3 ; For compatibility |
.equ PORTC4 = 4 ; Port C Data Register bit 4 |
.equ PC4 = 4 ; For compatibility |
.equ PORTC5 = 5 ; Port C Data Register bit 5 |
.equ PC5 = 5 ; For compatibility |
.equ PORTC6 = 6 ; Port C Data Register bit 6 |
.equ PC6 = 6 ; For compatibility |
.equ PORTC7 = 7 ; Port C Data Register bit 7 |
.equ PC7 = 7 ; For compatibility |
; DDRC - Port C Data Direction Register |
.equ DDC0 = 0 ; Port C Data Direction Register bit 0 |
.equ DDC1 = 1 ; Port C Data Direction Register bit 1 |
.equ DDC2 = 2 ; Port C Data Direction Register bit 2 |
.equ DDC3 = 3 ; Port C Data Direction Register bit 3 |
.equ DDC4 = 4 ; Port C Data Direction Register bit 4 |
.equ DDC5 = 5 ; Port C Data Direction Register bit 5 |
.equ DDC6 = 6 ; Port C Data Direction Register bit 6 |
.equ DDC7 = 7 ; Port C Data Direction Register bit 7 |
; PINC - Port C Input Pins |
.equ PINC0 = 0 ; Port C Input Pins bit 0 |
.equ PINC1 = 1 ; Port C Input Pins bit 1 |
.equ PINC2 = 2 ; Port C Input Pins bit 2 |
.equ PINC3 = 3 ; Port C Input Pins bit 3 |
.equ PINC4 = 4 ; Port C Input Pins bit 4 |
.equ PINC5 = 5 ; Port C Input Pins bit 5 |
.equ PINC6 = 6 ; Port C Input Pins bit 6 |
.equ PINC7 = 7 ; Port C Input Pins bit 7 |
; ***** PORTD ************************ |
; PORTD - Port D Data Register |
.equ PORTD0 = 0 ; Port D Data Register bit 0 |
.equ PD0 = 0 ; For compatibility |
.equ PORTD1 = 1 ; Port D Data Register bit 1 |
.equ PD1 = 1 ; For compatibility |
.equ PORTD2 = 2 ; Port D Data Register bit 2 |
.equ PD2 = 2 ; For compatibility |
.equ PORTD3 = 3 ; Port D Data Register bit 3 |
.equ PD3 = 3 ; For compatibility |
.equ PORTD4 = 4 ; Port D Data Register bit 4 |
.equ PD4 = 4 ; For compatibility |
.equ PORTD5 = 5 ; Port D Data Register bit 5 |
.equ PD5 = 5 ; For compatibility |
.equ PORTD6 = 6 ; Port D Data Register bit 6 |
.equ PD6 = 6 ; For compatibility |
.equ PORTD7 = 7 ; Port D Data Register bit 7 |
.equ PD7 = 7 ; For compatibility |
; DDRD - Port D Data Direction Register |
.equ DDD0 = 0 ; Port D Data Direction Register bit 0 |
.equ DDD1 = 1 ; Port D Data Direction Register bit 1 |
.equ DDD2 = 2 ; Port D Data Direction Register bit 2 |
.equ DDD3 = 3 ; Port D Data Direction Register bit 3 |
.equ DDD4 = 4 ; Port D Data Direction Register bit 4 |
.equ DDD5 = 5 ; Port D Data Direction Register bit 5 |
.equ DDD6 = 6 ; Port D Data Direction Register bit 6 |
.equ DDD7 = 7 ; Port D Data Direction Register bit 7 |
; PIND - Port D Input Pins |
.equ PIND0 = 0 ; Port D Input Pins bit 0 |
.equ PIND1 = 1 ; Port D Input Pins bit 1 |
.equ PIND2 = 2 ; Port D Input Pins bit 2 |
.equ PIND3 = 3 ; Port D Input Pins bit 3 |
.equ PIND4 = 4 ; Port D Input Pins bit 4 |
.equ PIND5 = 5 ; Port D Input Pins bit 5 |
.equ PIND6 = 6 ; Port D Input Pins bit 6 |
.equ PIND7 = 7 ; Port D Input Pins bit 7 |
; ***** PORTE ************************ |
; PORTE - Data Register, Port E |
.equ PORTE0 = 0 ; |
.equ PE0 = 0 ; For compatibility |
.equ PORTE1 = 1 ; |
.equ PE1 = 1 ; For compatibility |
.equ PORTE2 = 2 ; |
.equ PE2 = 2 ; For compatibility |
.equ PORTE3 = 3 ; |
.equ PE3 = 3 ; For compatibility |
.equ PORTE4 = 4 ; |
.equ PE4 = 4 ; For compatibility |
.equ PORTE5 = 5 ; |
.equ PE5 = 5 ; For compatibility |
.equ PORTE6 = 6 ; |
.equ PE6 = 6 ; For compatibility |
.equ PORTE7 = 7 ; |
.equ PE7 = 7 ; For compatibility |
; DDRE - Data Direction Register, Port E |
.equ DDE0 = 0 ; |
.equ DDE1 = 1 ; |
.equ DDE2 = 2 ; |
.equ DDE3 = 3 ; |
.equ DDE4 = 4 ; |
.equ DDE5 = 5 ; |
.equ DDE6 = 6 ; |
.equ DDE7 = 7 ; |
; PINE - Input Pins, Port E |
.equ PINE0 = 0 ; |
.equ PINE1 = 1 ; |
.equ PINE2 = 2 ; |
.equ PINE3 = 3 ; |
.equ PINE4 = 4 ; |
.equ PINE5 = 5 ; |
.equ PINE6 = 6 ; |
.equ PINE7 = 7 ; |
; ***** PORTF ************************ |
; PORTF - Data Register, Port F |
.equ PORTF0 = 0 ; |
.equ PF0 = 0 ; For compatibility |
.equ PORTF1 = 1 ; |
.equ PF1 = 1 ; For compatibility |
.equ PORTF2 = 2 ; |
.equ PF2 = 2 ; For compatibility |
.equ PORTF3 = 3 ; |
.equ PF3 = 3 ; For compatibility |
.equ PORTF4 = 4 ; |
.equ PF4 = 4 ; For compatibility |
.equ PORTF5 = 5 ; |
.equ PF5 = 5 ; For compatibility |
.equ PORTF6 = 6 ; |
.equ PF6 = 6 ; For compatibility |
.equ PORTF7 = 7 ; |
.equ PF7 = 7 ; For compatibility |
; DDRF - Data Direction Register, Port F |
.equ DDF0 = 0 ; |
.equ DDF1 = 1 ; |
.equ DDF2 = 2 ; |
.equ DDF3 = 3 ; |
.equ DDF4 = 4 ; |
.equ DDF5 = 5 ; |
.equ DDF6 = 6 ; |
.equ DDF7 = 7 ; |
; PINF - Input Pins, Port F |
.equ PINF0 = 0 ; |
.equ PINF1 = 1 ; |
.equ PINF2 = 2 ; |
.equ PINF3 = 3 ; |
.equ PINF4 = 4 ; |
.equ PINF5 = 5 ; |
.equ PINF6 = 6 ; |
.equ PINF7 = 7 ; |
; ***** PORTG ************************ |
; PORTG - Data Register, Port G |
.equ PORTG0 = 0 ; |
.equ PG0 = 0 ; For compatibility |
.equ PORTG1 = 1 ; |
.equ PG1 = 1 ; For compatibility |
.equ PORTG2 = 2 ; |
.equ PG2 = 2 ; For compatibility |
.equ PORTG3 = 3 ; |
.equ PG3 = 3 ; For compatibility |
.equ PORTG4 = 4 ; |
.equ PG4 = 4 ; For compatibility |
.equ PORTG5 = 5 ; |
.equ PG5 = 5 ; For compatibility |
; DDRG |
.equ DDG0 = 0 ; |
.equ DDG1 = 1 ; |
.equ DDG2 = 2 ; |
.equ DDG3 = 3 ; |
.equ DDG4 = 4 ; |
.equ DDG5 = 5 ; |
; PING - Input Pins, Port G |
.equ PING0 = 0 ; |
.equ PING1 = 1 ; |
.equ PING2 = 2 ; |
.equ PING3 = 3 ; |
.equ PING4 = 4 ; |
.equ PING5 = 5 ; |
; ***** TIMER_COUNTER_0 ************** |
; TIMSK0 - Timer/Counter0 Interrupt Mask Register |
.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable |
.equ OCIE0A = 1 ; Timer/Counter0 Output Compare Match A Interrupt Enable |
.equ OCIE0B = 2 ; Timer/Counter0 Output Compare Match B Interrupt Enable |
; TIFR0 - Timer/Counter0 Interrupt Flag register |
.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag |
.equ OCF0A = 1 ; Timer/Counter0 Output Compare Flag 0A |
.equ OCF0B = 2 ; Timer/Counter0 Output Compare Flag 0B |
; TCCR0A - Timer/Counter Control Register A |
.equ WGM00 = 0 ; Waveform Generation Mode |
.equ WGM01 = 1 ; Waveform Generation Mode |
.equ COM0B0 = 4 ; Compare Output Mode, Fast PWm |
.equ COM0B1 = 5 ; Compare Output Mode, Fast PWm |
.equ COM0A0 = 6 ; Compare Output Mode, Phase Correct PWM Mode |
.equ COM0A1 = 7 ; Compare Output Mode, Phase Correct PWM Mode |
; TCCR0B - Timer/Counter Control Register B |
.equ CS00 = 0 ; Clock Select |
.equ CS01 = 1 ; Clock Select |
.equ CS02 = 2 ; Clock Select |
.equ WGM02 = 3 ; |
.equ FOC0B = 6 ; Force Output Compare B |
.equ FOC0A = 7 ; Force Output Compare A |
; TCNT0 - Timer/Counter0 |
.equ TCNT0_0 = 0 ; |
.equ TCNT0_1 = 1 ; |
.equ TCNT0_2 = 2 ; |
.equ TCNT0_3 = 3 ; |
.equ TCNT0_4 = 4 ; |
.equ TCNT0_5 = 5 ; |
.equ TCNT0_6 = 6 ; |
.equ TCNT0_7 = 7 ; |
; OCR0A - Timer/Counter0 Output Compare Register |
.equ OCROA_0 = 0 ; |
.equ OCROA_1 = 1 ; |
.equ OCROA_2 = 2 ; |
.equ OCROA_3 = 3 ; |
.equ OCROA_4 = 4 ; |
.equ OCROA_5 = 5 ; |
.equ OCROA_6 = 6 ; |
.equ OCROA_7 = 7 ; |
; OCR0B - Timer/Counter0 Output Compare Register |
.equ OCR0B_0 = 0 ; |
.equ OCR0B_1 = 1 ; |
.equ OCR0B_2 = 2 ; |
.equ OCR0B_3 = 3 ; |
.equ OCR0B_4 = 4 ; |
.equ OCR0B_5 = 5 ; |
.equ OCR0B_6 = 6 ; |
.equ OCR0B_7 = 7 ; |
; GTCCR - General Timer/Counter Control Register |
.equ PSRSYNC = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0 |
.equ PSR10 = PSRSYNC ; For compatibility |
.equ TSM = 7 ; Timer/Counter Synchronization Mode |
; ***** TIMER_COUNTER_2 ************** |
; TIMSK2 - Timer/Counter Interrupt Mask register |
.equ TOIE2 = 0 ; Timer/Counter2 Overflow Interrupt Enable |
.equ TOIE2A = TOIE2 ; For compatibility |
.equ OCIE2A = 1 ; Timer/Counter2 Output Compare Match A Interrupt Enable |
.equ OCIE2B = 2 ; Timer/Counter2 Output Compare Match B Interrupt Enable |
; TIFR2 - Timer/Counter Interrupt Flag Register |
.equ TOV2 = 0 ; Timer/Counter2 Overflow Flag |
.equ OCF2A = 1 ; Output Compare Flag 2A |
.equ OCF2B = 2 ; Output Compare Flag 2B |
; TCCR2A - Timer/Counter2 Control Register A |
.equ WGM20 = 0 ; Waveform Genration Mode |
.equ WGM21 = 1 ; Waveform Genration Mode |
.equ COM2B0 = 4 ; Compare Output Mode bit 0 |
.equ COM2B1 = 5 ; Compare Output Mode bit 1 |
.equ COM2A0 = 6 ; Compare Output Mode bit 1 |
.equ COM2A1 = 7 ; Compare Output Mode bit 1 |
; TCCR2B - Timer/Counter2 Control Register B |
.equ CS20 = 0 ; Clock Select bit 0 |
.equ CS21 = 1 ; Clock Select bit 1 |
.equ CS22 = 2 ; Clock Select bit 2 |
.equ WGM22 = 3 ; Waveform Generation Mode |
.equ FOC2B = 6 ; Force Output Compare B |
.equ FOC2A = 7 ; Force Output Compare A |
; TCNT2 - Timer/Counter2 |
.equ TCNT2_0 = 0 ; Timer/Counter 2 bit 0 |
.equ TCNT2_1 = 1 ; Timer/Counter 2 bit 1 |
.equ TCNT2_2 = 2 ; Timer/Counter 2 bit 2 |
.equ TCNT2_3 = 3 ; Timer/Counter 2 bit 3 |
.equ TCNT2_4 = 4 ; Timer/Counter 2 bit 4 |
.equ TCNT2_5 = 5 ; Timer/Counter 2 bit 5 |
.equ TCNT2_6 = 6 ; Timer/Counter 2 bit 6 |
.equ TCNT2_7 = 7 ; Timer/Counter 2 bit 7 |
; OCR2A - Timer/Counter2 Output Compare Register A |
.equ OCR2_0 = 0 ; Timer/Counter2 Output Compare Register Bit 0 |
.equ OCR2_1 = 1 ; Timer/Counter2 Output Compare Register Bit 1 |
.equ OCR2_2 = 2 ; Timer/Counter2 Output Compare Register Bit 2 |
.equ OCR2_3 = 3 ; Timer/Counter2 Output Compare Register Bit 3 |
.equ OCR2_4 = 4 ; Timer/Counter2 Output Compare Register Bit 4 |
.equ OCR2_5 = 5 ; Timer/Counter2 Output Compare Register Bit 5 |
.equ OCR2_6 = 6 ; Timer/Counter2 Output Compare Register Bit 6 |
.equ OCR2_7 = 7 ; Timer/Counter2 Output Compare Register Bit 7 |
; OCR2B - Timer/Counter2 Output Compare Register B |
;.equ OCR2_0 = 0 ; Timer/Counter2 Output Compare Register Bit 0 |
;.equ OCR2_1 = 1 ; Timer/Counter2 Output Compare Register Bit 1 |
;.equ OCR2_2 = 2 ; Timer/Counter2 Output Compare Register Bit 2 |
;.equ OCR2_3 = 3 ; Timer/Counter2 Output Compare Register Bit 3 |
;.equ OCR2_4 = 4 ; Timer/Counter2 Output Compare Register Bit 4 |
;.equ OCR2_5 = 5 ; Timer/Counter2 Output Compare Register Bit 5 |
;.equ OCR2_6 = 6 ; Timer/Counter2 Output Compare Register Bit 6 |
;.equ OCR2_7 = 7 ; Timer/Counter2 Output Compare Register Bit 7 |
; ASSR - Asynchronous Status Register |
.equ TCR2BUB = 0 ; Timer/Counter Control Register2 Update Busy |
.equ TCR2AUB = 1 ; Timer/Counter Control Register2 Update Busy |
.equ OCR2BUB = 2 ; Output Compare Register 2 Update Busy |
.equ OCR2AUB = 3 ; Output Compare Register2 Update Busy |
.equ TCN2UB = 4 ; Timer/Counter2 Update Busy |
.equ AS2 = 5 ; Asynchronous Timer/Counter2 |
.equ EXCLK = 6 ; Enable External Clock Input |
; GTCCR - General Timer Counter Control register |
.equ PSRASY = 1 ; Prescaler Reset Timer/Counter2 |
.equ PSR2 = PSRASY ; For compatibility |
;.equ TSM = 7 ; Timer/Counter Synchronization Mode |
; ***** WATCHDOG ********************* |
; WDTCSR - Watchdog Timer Control Register |
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 |
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 |
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 |
.equ WDE = 3 ; Watch Dog Enable |
.equ WDCE = 4 ; Watchdog Change Enable |
.equ WDP3 = 5 ; Watchdog Timer Prescaler Bit 3 |
.equ WDIE = 6 ; Watchdog Timeout Interrupt Enable |
.equ WDIF = 7 ; Watchdog Timeout Interrupt Flag |
; ***** USART1 *********************** |
; UDR1 - USART I/O Data Register |
.equ UDR1_0 = 0 ; USART I/O Data Register bit 0 |
.equ UDR1_1 = 1 ; USART I/O Data Register bit 1 |
.equ UDR1_2 = 2 ; USART I/O Data Register bit 2 |
.equ UDR1_3 = 3 ; USART I/O Data Register bit 3 |
.equ UDR1_4 = 4 ; USART I/O Data Register bit 4 |
.equ UDR1_5 = 5 ; USART I/O Data Register bit 5 |
.equ UDR1_6 = 6 ; USART I/O Data Register bit 6 |
.equ UDR1_7 = 7 ; USART I/O Data Register bit 7 |
; UCSR1A - USART Control and Status Register A |
.equ MPCM1 = 0 ; Multi-processor Communication Mode |
.equ U2X1 = 1 ; Double the USART transmission speed |
.equ UPE1 = 2 ; Parity Error |
.equ DOR1 = 3 ; Data overRun |
.equ FE1 = 4 ; Framing Error |
.equ UDRE1 = 5 ; USART Data Register Empty |
.equ TXC1 = 6 ; USART Transmitt Complete |
.equ RXC1 = 7 ; USART Receive Complete |
; UCSR1B - USART Control and Status Register B |
.equ TXB81 = 0 ; Transmit Data Bit 8 |
.equ RXB81 = 1 ; Receive Data Bit 8 |
.equ UCSZ12 = 2 ; Character Size |
.equ TXEN1 = 3 ; Transmitter Enable |
.equ RXEN1 = 4 ; Receiver Enable |
.equ UDRIE1 = 5 ; USART Data register Empty Interrupt Enable |
.equ TXCIE1 = 6 ; TX Complete Interrupt Enable |
.equ RXCIE1 = 7 ; RX Complete Interrupt Enable |
; UCSR1C - USART Control and Status Register C |
.equ UCPOL1 = 0 ; Clock Polarity |
.equ UCSZ10_UCPHA1 = 1 ; Character Size |
.equ UCSZ11_UDORD1 = 2 ; Character Size |
.equ USBS1 = 3 ; Stop Bit Select |
.equ UPM10 = 4 ; Parity Mode Bit 0 |
.equ UPM11 = 5 ; Parity Mode Bit 1 |
.equ UMSEL10 = 6 ; USART Mode Select |
.equ UMSEL11 = 7 ; USART Mode Select |
; ***** EEPROM *********************** |
; EEARH - EEPROM Address Register Low Byte |
.equ EEAR8 = 0 ; EEPROM Read/Write Access Bit 8 |
.equ EEAR9 = 1 ; EEPROM Read/Write Access Bit 9 |
.equ EEAR10 = 2 ; EEPROM Read/Write Access Bit 10 |
.equ EEAR11 = 3 ; EEPROM Read/Write Access Bit 11 |
; EEARL - EEPROM Address Register Low Byte |
.equ EEAR0 = 0 ; EEPROM Read/Write Access Bit 0 |
.equ EEAR1 = 1 ; EEPROM Read/Write Access Bit 1 |
.equ EEAR2 = 2 ; EEPROM Read/Write Access Bit 2 |
.equ EEAR3 = 3 ; EEPROM Read/Write Access Bit 3 |
.equ EEAR4 = 4 ; EEPROM Read/Write Access Bit 4 |
.equ EEAR5 = 5 ; EEPROM Read/Write Access Bit 5 |
.equ EEAR6 = 6 ; EEPROM Read/Write Access Bit 6 |
.equ EEAR7 = 7 ; EEPROM Read/Write Access Bit 7 |
; EEDR - EEPROM Data Register |
.equ EEDR0 = 0 ; EEPROM Data Register bit 0 |
.equ EEDR1 = 1 ; EEPROM Data Register bit 1 |
.equ EEDR2 = 2 ; EEPROM Data Register bit 2 |
.equ EEDR3 = 3 ; EEPROM Data Register bit 3 |
.equ EEDR4 = 4 ; EEPROM Data Register bit 4 |
.equ EEDR5 = 5 ; EEPROM Data Register bit 5 |
.equ EEDR6 = 6 ; EEPROM Data Register bit 6 |
.equ EEDR7 = 7 ; EEPROM Data Register bit 7 |
; EECR - EEPROM Control Register |
.equ EERE = 0 ; EEPROM Read Enable |
.equ EEPE = 1 ; EEPROM Write Enable |
.equ EEMPE = 2 ; EEPROM Master Write Enable |
.equ EERIE = 3 ; EEPROM Ready Interrupt Enable |
.equ EEPM0 = 4 ; EEPROM Programming Mode Bit 0 |
.equ EEPM1 = 5 ; EEPROM Programming Mode Bit 1 |
; ***** TIMER_COUNTER_5 ************** |
; TIMSK5 - Timer/Counter5 Interrupt Mask Register |
.equ TOIE5 = 0 ; Timer/Counter5 Overflow Interrupt Enable |
.equ OCIE5A = 1 ; Timer/Counter5 Output Compare A Match Interrupt Enable |
.equ OCIE5B = 2 ; Timer/Counter5 Output Compare B Match Interrupt Enable |
.equ OCIE5C = 3 ; Timer/Counter5 Output Compare C Match Interrupt Enable |
.equ ICIE5 = 5 ; Timer/Counter5 Input Capture Interrupt Enable |
; TIFR5 - Timer/Counter5 Interrupt Flag register |
.equ TOV5 = 0 ; Timer/Counter5 Overflow Flag |
.equ OCF5A = 1 ; Output Compare Flag 5A |
.equ OCF5B = 2 ; Output Compare Flag 5B |
.equ OCF5C = 3 ; Output Compare Flag 5C |
.equ ICF5 = 5 ; Input Capture Flag 5 |
; TCCR5A - Timer/Counter5 Control Register A |
.equ WGM50 = 0 ; Waveform Generation Mode |
.equ WGM51 = 1 ; Waveform Generation Mode |
.equ COM5C0 = 2 ; Compare Output Mode 5C, bit 0 |
.equ COM5C1 = 3 ; Compare Output Mode 5C, bit 1 |
.equ COM5B0 = 4 ; Compare Output Mode 5B, bit 0 |
.equ COM5B1 = 5 ; Compare Output Mode 5B, bit 1 |
.equ COM5A0 = 6 ; Compare Output Mode 5A, bit 0 |
.equ COM5A1 = 7 ; Compare Output Mode 1A, bit 1 |
; TCCR5B - Timer/Counter5 Control Register B |
.equ CS50 = 0 ; Prescaler source of Timer/Counter 5 |
.equ CS51 = 1 ; Prescaler source of Timer/Counter 5 |
.equ CS52 = 2 ; Prescaler source of Timer/Counter 5 |
.equ WGM52 = 3 ; Waveform Generation Mode |
.equ WGM53 = 4 ; Waveform Generation Mode |
.equ ICES5 = 6 ; Input Capture 5 Edge Select |
.equ ICNC5 = 7 ; Input Capture 5 Noise Canceler |
; TCCR5C - Timer/Counter 5 Control Register C |
.equ FOC5C = 5 ; Force Output Compare 5C |
.equ FOC5B = 6 ; Force Output Compare 5B |
.equ FOC5A = 7 ; Force Output Compare 5A |
; ICR5L - Timer/Counter5 Input Capture Register Low Byte |
.equ ICR5L0 = 0 ; Timer/Counter5 Input Capture Register Low Byte bit 0 |
.equ ICR5L1 = 1 ; Timer/Counter5 Input Capture Register Low Byte bit 1 |
.equ ICR5L2 = 2 ; Timer/Counter5 Input Capture Register Low Byte bit 2 |
.equ ICR5L3 = 3 ; Timer/Counter5 Input Capture Register Low Byte bit 3 |
.equ ICR5L4 = 4 ; Timer/Counter5 Input Capture Register Low Byte bit 4 |
.equ ICR5L5 = 5 ; Timer/Counter5 Input Capture Register Low Byte bit 5 |
.equ ICR5L6 = 6 ; Timer/Counter5 Input Capture Register Low Byte bit 6 |
.equ ICR5L7 = 7 ; Timer/Counter5 Input Capture Register Low Byte bit 7 |
; ***** TIMER_COUNTER_4 ************** |
; TIMSK4 - Timer/Counter4 Interrupt Mask Register |
.equ TOIE4 = 0 ; Timer/Counter4 Overflow Interrupt Enable |
.equ OCIE4A = 1 ; Timer/Counter4 Output Compare A Match Interrupt Enable |
.equ OCIE4B = 2 ; Timer/Counter4 Output Compare B Match Interrupt Enable |
.equ OCIE4C = 3 ; Timer/Counter4 Output Compare C Match Interrupt Enable |
.equ ICIE4 = 5 ; Timer/Counter4 Input Capture Interrupt Enable |
; TIFR4 - Timer/Counter4 Interrupt Flag register |
.equ TOV4 = 0 ; Timer/Counter4 Overflow Flag |
.equ OCF4A = 1 ; Output Compare Flag 4A |
.equ OCF4B = 2 ; Output Compare Flag 4B |
.equ OCF4C = 3 ; Output Compare Flag 4C |
.equ ICF4 = 5 ; Input Capture Flag 4 |
; TCCR4A - Timer/Counter4 Control Register A |
.equ WGM40 = 0 ; Waveform Generation Mode |
.equ WGM41 = 1 ; Waveform Generation Mode |
.equ COM4C0 = 2 ; Compare Output Mode 4C, bit 0 |
.equ COM4C1 = 3 ; Compare Output Mode 4C, bit 1 |
.equ COM4B0 = 4 ; Compare Output Mode 4B, bit 0 |
.equ COM4B1 = 5 ; Compare Output Mode 4B, bit 1 |
.equ COM4A0 = 6 ; Compare Output Mode 4A, bit 0 |
.equ COM4A1 = 7 ; Compare Output Mode 1A, bit 1 |
; TCCR4B - Timer/Counter4 Control Register B |
.equ CS40 = 0 ; Prescaler source of Timer/Counter 4 |
.equ CS41 = 1 ; Prescaler source of Timer/Counter 4 |
.equ CS42 = 2 ; Prescaler source of Timer/Counter 4 |
.equ WGM42 = 3 ; Waveform Generation Mode |
.equ WGM43 = 4 ; Waveform Generation Mode |
.equ ICES4 = 6 ; Input Capture 4 Edge Select |
.equ ICNC4 = 7 ; Input Capture 4 Noise Canceler |
; TCCR4C - Timer/Counter 4 Control Register C |
.equ FOC4C = 5 ; Force Output Compare 4C |
.equ FOC4B = 6 ; Force Output Compare 4B |
.equ FOC4A = 7 ; Force Output Compare 4A |
; ***** TIMER_COUNTER_3 ************** |
; TIMSK3 - Timer/Counter3 Interrupt Mask Register |
.equ TOIE3 = 0 ; Timer/Counter3 Overflow Interrupt Enable |
.equ OCIE3A = 1 ; Timer/Counter3 Output Compare A Match Interrupt Enable |
.equ OCIE3B = 2 ; Timer/Counter3 Output Compare B Match Interrupt Enable |
.equ OCIE3C = 3 ; Timer/Counter3 Output Compare C Match Interrupt Enable |
.equ ICIE3 = 5 ; Timer/Counter3 Input Capture Interrupt Enable |
; TIFR3 - Timer/Counter3 Interrupt Flag register |
.equ TOV3 = 0 ; Timer/Counter3 Overflow Flag |
.equ OCF3A = 1 ; Output Compare Flag 3A |
.equ OCF3B = 2 ; Output Compare Flag 3B |
.equ OCF3C = 3 ; Output Compare Flag 3C |
.equ ICF3 = 5 ; Input Capture Flag 3 |
; TCCR3A - Timer/Counter3 Control Register A |
.equ WGM30 = 0 ; Waveform Generation Mode |
.equ WGM31 = 1 ; Waveform Generation Mode |
.equ COM3C0 = 2 ; Compare Output Mode 3C, bit 0 |
.equ COM3C1 = 3 ; Compare Output Mode 3C, bit 1 |
.equ COM3B0 = 4 ; Compare Output Mode 3B, bit 0 |
.equ COM3B1 = 5 ; Compare Output Mode 3B, bit 1 |
.equ COM3A0 = 6 ; Compare Output Mode 3A, bit 0 |
.equ COM3A1 = 7 ; Compare Output Mode 1A, bit 1 |
; TCCR3B - Timer/Counter3 Control Register B |
.equ CS30 = 0 ; Prescaler source of Timer/Counter 3 |
.equ CS31 = 1 ; Prescaler source of Timer/Counter 3 |
.equ CS32 = 2 ; Prescaler source of Timer/Counter 3 |
.equ WGM32 = 3 ; Waveform Generation Mode |
.equ WGM33 = 4 ; Waveform Generation Mode |
.equ ICES3 = 6 ; Input Capture 3 Edge Select |
.equ ICNC3 = 7 ; Input Capture 3 Noise Canceler |
; TCCR3C - Timer/Counter 3 Control Register C |
.equ FOC3C = 5 ; Force Output Compare 3C |
.equ FOC3B = 6 ; Force Output Compare 3B |
.equ FOC3A = 7 ; Force Output Compare 3A |
; ***** TIMER_COUNTER_1 ************** |
; TIMSK1 - Timer/Counter1 Interrupt Mask Register |
.equ TOIE1 = 0 ; Timer/Counter1 Overflow Interrupt Enable |
.equ OCIE1A = 1 ; Timer/Counter1 Output Compare A Match Interrupt Enable |
.equ OCIE1B = 2 ; Timer/Counter1 Output Compare B Match Interrupt Enable |
.equ OCIE1C = 3 ; Timer/Counter1 Output Compare C Match Interrupt Enable |
.equ ICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable |
; TIFR1 - Timer/Counter1 Interrupt Flag register |
.equ TOV1 = 0 ; Timer/Counter1 Overflow Flag |
.equ OCF1A = 1 ; Output Compare Flag 1A |
.equ OCF1B = 2 ; Output Compare Flag 1B |
.equ OCF1C = 3 ; Output Compare Flag 1C |
.equ ICF1 = 5 ; Input Capture Flag 1 |
; TCCR1A - Timer/Counter1 Control Register A |
.equ WGM10 = 0 ; Waveform Generation Mode |
.equ WGM11 = 1 ; Waveform Generation Mode |
.equ COM1C0 = 2 ; Compare Output Mode 1C, bit 0 |
.equ COM1C1 = 3 ; Compare Output Mode 1C, bit 1 |
.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0 |
.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1 |
.equ COM1A0 = 6 ; Compare Output Mode 1A, bit 0 |
.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1 |
; TCCR1B - Timer/Counter1 Control Register B |
.equ CS10 = 0 ; Prescaler source of Timer/Counter 1 |
.equ CS11 = 1 ; Prescaler source of Timer/Counter 1 |
.equ CS12 = 2 ; Prescaler source of Timer/Counter 1 |
.equ WGM12 = 3 ; Waveform Generation Mode |
.equ WGM13 = 4 ; Waveform Generation Mode |
.equ ICES1 = 6 ; Input Capture 1 Edge Select |
.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler |
; TCCR1C - Timer/Counter 1 Control Register C |
.equ FOC1C = 5 ; Force Output Compare 1C |
.equ FOC1B = 6 ; Force Output Compare 1B |
.equ FOC1A = 7 ; Force Output Compare 1A |
; ***** JTAG ************************* |
; OCDR - On-Chip Debug Related Register in I/O Memory |
.equ OCDR0 = 0 ; On-Chip Debug Register Bit 0 |
.equ OCDR1 = 1 ; On-Chip Debug Register Bit 1 |
.equ OCDR2 = 2 ; On-Chip Debug Register Bit 2 |
.equ OCDR3 = 3 ; On-Chip Debug Register Bit 3 |
.equ OCDR4 = 4 ; On-Chip Debug Register Bit 4 |
.equ OCDR5 = 5 ; On-Chip Debug Register Bit 5 |
.equ OCDR6 = 6 ; On-Chip Debug Register Bit 6 |
.equ OCDR7 = 7 ; On-Chip Debug Register Bit 7 |
.equ IDRD = OCDR7 ; For compatibility |
; MCUCR - MCU Control Register |
.equ JTD = 7 ; JTAG Interface Disable |
; MCUSR - MCU Status Register |
.equ JTRF = 4 ; JTAG Reset Flag |
; ***** EXTERNAL_INTERRUPT *********** |
; EICRA - External Interrupt Control Register A |
.equ ISC00 = 0 ; External Interrupt Sense Control Bit |
.equ ISC01 = 1 ; External Interrupt Sense Control Bit |
.equ ISC10 = 2 ; External Interrupt Sense Control Bit |
.equ ISC11 = 3 ; External Interrupt Sense Control Bit |
.equ ISC20 = 4 ; External Interrupt Sense Control Bit |
.equ ISC21 = 5 ; External Interrupt Sense Control Bit |
.equ ISC30 = 6 ; External Interrupt Sense Control Bit |
.equ ISC31 = 7 ; External Interrupt Sense Control Bit |
; EICRB - External Interrupt Control Register B |
.equ ISC40 = 0 ; External Interrupt 7-4 Sense Control Bit |
.equ ISC41 = 1 ; External Interrupt 7-4 Sense Control Bit |
.equ ISC50 = 2 ; External Interrupt 7-4 Sense Control Bit |
.equ ISC51 = 3 ; External Interrupt 7-4 Sense Control Bit |
.equ ISC60 = 4 ; External Interrupt 7-4 Sense Control Bit |
.equ ISC61 = 5 ; External Interrupt 7-4 Sense Control Bit |
.equ ISC70 = 6 ; External Interrupt 7-4 Sense Control Bit |
.equ ISC71 = 7 ; External Interrupt 7-4 Sense Control Bit |
; EIMSK - External Interrupt Mask Register |
.equ INT0 = 0 ; External Interrupt Request 0 Enable |
.equ INT1 = 1 ; External Interrupt Request 1 Enable |
.equ INT2 = 2 ; External Interrupt Request 2 Enable |
.equ INT3 = 3 ; External Interrupt Request 3 Enable |
.equ INT4 = 4 ; External Interrupt Request 4 Enable |
.equ INT5 = 5 ; External Interrupt Request 5 Enable |
.equ INT6 = 6 ; External Interrupt Request 6 Enable |
.equ INT7 = 7 ; External Interrupt Request 7 Enable |
; EIFR - External Interrupt Flag Register |
.equ INTF0 = 0 ; External Interrupt Flag 0 |
.equ INTF1 = 1 ; External Interrupt Flag 1 |
.equ INTF2 = 2 ; External Interrupt Flag 2 |
.equ INTF3 = 3 ; External Interrupt Flag 3 |
.equ INTF4 = 4 ; External Interrupt Flag 4 |
.equ INTF5 = 5 ; External Interrupt Flag 5 |
.equ INTF6 = 6 ; External Interrupt Flag 6 |
.equ INTF7 = 7 ; External Interrupt Flag 7 |
; PCICR - Pin Change Interrupt Control Register |
.equ PCIE0 = 0 ; Pin Change Interrupt Enable 0 |
.equ PCIE1 = 1 ; Pin Change Interrupt Enable 1 |
.equ PCIE2 = 2 ; Pin Change Interrupt Enable 2 |
; PCIFR - Pin Change Interrupt Flag Register |
.equ PCIF0 = 0 ; Pin Change Interrupt Flag 0 |
.equ PCIF1 = 1 ; Pin Change Interrupt Flag 1 |
.equ PCIF2 = 2 ; Pin Change Interrupt Flag 2 |
; PCMSK2 - Pin Change Mask Register 2 |
.equ PCINT16 = 0 ; Pin Change Enable Mask 16 |
.equ PCINT17 = 1 ; Pin Change Enable Mask 17 |
.equ PCINT18 = 2 ; Pin Change Enable Mask 18 |
.equ PCINT19 = 3 ; Pin Change Enable Mask 19 |
.equ PCINT20 = 4 ; Pin Change Enable Mask 20 |
.equ PCINT21 = 5 ; Pin Change Enable Mask 21 |
.equ PCINT22 = 6 ; Pin Change Enable Mask 22 |
.equ PCINT23 = 7 ; Pin Change Enable Mask 23 |
; PCMSK1 - Pin Change Mask Register 1 |
.equ PCINT8 = 0 ; Pin Change Enable Mask 8 |
.equ PCINT9 = 1 ; Pin Change Enable Mask 9 |
.equ PCINT10 = 2 ; Pin Change Enable Mask 10 |
.equ PCINT11 = 3 ; Pin Change Enable Mask 11 |
.equ PCINT12 = 4 ; Pin Change Enable Mask 12 |
.equ PCINT13 = 5 ; Pin Change Enable Mask 13 |
.equ PCINT14 = 6 ; Pin Change Enable Mask 14 |
.equ PCINT15 = 7 ; Pin Change Enable Mask 15 |
; PCMSK0 - Pin Change Mask Register 0 |
.equ PCINT0 = 0 ; Pin Change Enable Mask 0 |
.equ PCINT1 = 1 ; Pin Change Enable Mask 1 |
.equ PCINT2 = 2 ; Pin Change Enable Mask 2 |
.equ PCINT3 = 3 ; Pin Change Enable Mask 3 |
.equ PCINT4 = 4 ; Pin Change Enable Mask 4 |
.equ PCINT5 = 5 ; Pin Change Enable Mask 5 |
.equ PCINT6 = 6 ; Pin Change Enable Mask 6 |
.equ PCINT7 = 7 ; Pin Change Enable Mask 7 |
; ***** CPU ************************** |
; SREG - Status Register |
.equ SREG_C = 0 ; Carry Flag |
.equ SREG_Z = 1 ; Zero Flag |
.equ SREG_N = 2 ; Negative Flag |
.equ SREG_V = 3 ; Two's Complement Overflow Flag |
.equ SREG_S = 4 |
.equ SREG_H = 5 ; Half Carry Flag |
.equ SREG_T = 6 ; Bit Copy Storage |
.equ SREG_I = 7 ; Global Interrupt Enable |
; MCUCR - MCU Control Register |
.equ IVCE = 0 ; Interrupt Vector Change Enable |
.equ IVSEL = 1 ; Interrupt Vector Select |
.equ PUD = 4 ; Pull-up disable |
;.equ JTD = 7 ; JTAG Interface Disable |
; MCUSR - MCU Status Register |
.equ PORF = 0 ; Power-on reset flag |
.equ EXTRF = 1 ; External Reset Flag |
.equ BORF = 2 ; Brown-out Reset Flag |
.equ WDRF = 3 ; Watchdog Reset Flag |
;.equ JTRF = 4 ; JTAG Reset Flag |
; XMCRA - External Memory Control Register A |
.equ SRW00 = 0 ; Wait state select bit lower page |
.equ SRW01 = 1 ; Wait state select bit lower page |
.equ SRW10 = 2 ; Wait state select bit upper page |
.equ SRW11 = 3 ; Wait state select bit upper page |
.equ SRL0 = 4 ; Wait state page limit |
.equ SRL1 = 5 ; Wait state page limit |
.equ SRL2 = 6 ; Wait state page limit |
.equ SRE = 7 ; External SRAM Enable |
; XMCRB - External Memory Control Register B |
.equ XMM0 = 0 ; External Memory High Mask |
.equ XMM1 = 1 ; External Memory High Mask |
.equ XMM2 = 2 ; External Memory High Mask |
.equ XMBK = 7 ; External Memory Bus Keeper Enable |
; OSCCAL - Oscillator Calibration Value |
.equ CAL0 = 0 ; Oscillator Calibration Value Bit0 |
.equ CAL1 = 1 ; Oscillator Calibration Value Bit1 |
.equ CAL2 = 2 ; Oscillator Calibration Value Bit2 |
.equ CAL3 = 3 ; Oscillator Calibration Value Bit3 |
.equ CAL4 = 4 ; Oscillator Calibration Value Bit4 |
.equ CAL5 = 5 ; Oscillator Calibration Value Bit5 |
.equ CAL6 = 6 ; Oscillator Calibration Value Bit6 |
.equ CAL7 = 7 ; Oscillator Calibration Value Bit7 |
; CLKPR - |
.equ CLKPS0 = 0 ; |
.equ CLKPS1 = 1 ; |
.equ CLKPS2 = 2 ; |
.equ CLKPS3 = 3 ; |
.equ CPKPCE = 7 ; |
; SMCR - Sleep Mode Control Register |
.equ SE = 0 ; Sleep Enable |
.equ SM0 = 1 ; Sleep Mode Select bit 0 |
.equ SM1 = 2 ; Sleep Mode Select bit 1 |
.equ SM2 = 3 ; Sleep Mode Select bit 2 |
; RAMPZ - RAM Page Z Select Register |
.equ RAMPZ0 = 0 ; RAM Page Z Select Register Bit 0 |
.equ RAMPZ1 = 1 ; RAM Page Z Select Register Bit 1 |
; EIND - Extended Indirect Register |
.equ EIND0 = 0 ; Bit 0 |
; GPIOR2 - General Purpose IO Register 2 |
.equ GPIOR20 = 0 ; General Purpose IO Register 2 bit 0 |
.equ GPIOR21 = 1 ; General Purpose IO Register 2 bit 1 |
.equ GPIOR22 = 2 ; General Purpose IO Register 2 bit 2 |
.equ GPIOR23 = 3 ; General Purpose IO Register 2 bit 3 |
.equ GPIOR24 = 4 ; General Purpose IO Register 2 bit 4 |
.equ GPIOR25 = 5 ; General Purpose IO Register 2 bit 5 |
.equ GPIOR26 = 6 ; General Purpose IO Register 2 bit 6 |
.equ GPIOR27 = 7 ; General Purpose IO Register 2 bit 7 |
; GPIOR1 - General Purpose IO Register 1 |
.equ GPIOR10 = 0 ; General Purpose IO Register 1 bit 0 |
.equ GPIOR11 = 1 ; General Purpose IO Register 1 bit 1 |
.equ GPIOR12 = 2 ; General Purpose IO Register 1 bit 2 |
.equ GPIOR13 = 3 ; General Purpose IO Register 1 bit 3 |
.equ GPIOR14 = 4 ; General Purpose IO Register 1 bit 4 |
.equ GPIOR15 = 5 ; General Purpose IO Register 1 bit 5 |
.equ GPIOR16 = 6 ; General Purpose IO Register 1 bit 6 |
.equ GPIOR17 = 7 ; General Purpose IO Register 1 bit 7 |
; GPIOR0 - General Purpose IO Register 0 |
.equ GPIOR00 = 0 ; General Purpose IO Register 0 bit 0 |
.equ GPIOR01 = 1 ; General Purpose IO Register 0 bit 1 |
.equ GPIOR02 = 2 ; General Purpose IO Register 0 bit 2 |
.equ GPIOR03 = 3 ; General Purpose IO Register 0 bit 3 |
.equ GPIOR04 = 4 ; General Purpose IO Register 0 bit 4 |
.equ GPIOR05 = 5 ; General Purpose IO Register 0 bit 5 |
.equ GPIOR06 = 6 ; General Purpose IO Register 0 bit 6 |
.equ GPIOR07 = 7 ; General Purpose IO Register 0 bit 7 |
; PRR1 - Power Reduction Register1 |
.equ PRUSART1 = 0 ; Power Reduction USART1 |
.equ PRUSART2 = 1 ; Power Reduction USART2 |
.equ PRUSART3 = 2 ; Power Reduction USART3 |
.equ PRTIM3 = 3 ; Power Reduction Timer/Counter3 |
.equ PRTIM4 = 4 ; Power Reduction Timer/Counter4 |
.equ PRTIM5 = 5 ; Power Reduction Timer/Counter5 |
; PRR0 - Power Reduction Register0 |
.equ PRADC = 0 ; Power Reduction ADC |
.equ PRUSART0 = 1 ; Power Reduction USART |
.equ PRSPI = 2 ; Power Reduction Serial Peripheral Interface |
.equ PRTIM1 = 3 ; Power Reduction Timer/Counter1 |
.equ PRTIM0 = 5 ; Power Reduction Timer/Counter0 |
.equ PRTIM2 = 6 ; Power Reduction Timer/Counter2 |
.equ PRTWI = 7 ; Power Reduction TWI |
; ***** AD_CONVERTER ***************** |
; ADMUX - The ADC multiplexer Selection Register |
.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits |
.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits |
.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits |
.equ MUX3 = 3 ; Analog Channel and Gain Selection Bits |
.equ MUX4 = 4 ; Analog Channel and Gain Selection Bits |
.equ ADLAR = 5 ; Left Adjust Result |
.equ REFS0 = 6 ; Reference Selection Bit 0 |
.equ REFS1 = 7 ; Reference Selection Bit 1 |
; ADCSRA - The ADC Control and Status register A |
.equ ADPS0 = 0 ; ADC Prescaler Select Bits |
.equ ADPS1 = 1 ; ADC Prescaler Select Bits |
.equ ADPS2 = 2 ; ADC Prescaler Select Bits |
.equ ADIE = 3 ; ADC Interrupt Enable |
.equ ADIF = 4 ; ADC Interrupt Flag |
.equ ADATE = 5 ; ADC Auto Trigger Enable |
.equ ADSC = 6 ; ADC Start Conversion |
.equ ADEN = 7 ; ADC Enable |
; ADCSRB - The ADC Control and Status register B |
.equ ADTS0 = 0 ; ADC Auto Trigger Source bit 0 |
.equ ADTS1 = 1 ; ADC Auto Trigger Source bit 1 |
.equ ADTS2 = 2 ; ADC Auto Trigger Source bit 2 |
.equ MUX5 = 3 ; Analog Channel and Gain Selection Bits |
;.equ ACME = 6 ; |
; ADCH - ADC Data Register High Byte |
.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0 |
.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1 |
.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2 |
.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3 |
.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4 |
.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5 |
.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6 |
.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7 |
; ADCL - ADC Data Register Low Byte |
.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0 |
.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1 |
.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2 |
.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3 |
.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4 |
.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5 |
.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6 |
.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7 |
; DIDR0 - Digital Input Disable Register |
.equ ADC0D = 0 ; |
.equ ADC1D = 1 ; |
.equ ADC2D = 2 ; |
.equ ADC3D = 3 ; |
.equ ADC4D = 4 ; |
.equ ADC5D = 5 ; |
.equ ADC6D = 6 ; |
.equ ADC7D = 7 ; |
; DIDR2 - Digital Input Disable Register |
.equ ADC8D = 0 ; |
.equ ADC9D = 1 ; |
.equ ADC10D = 2 ; |
.equ ADC11D = 3 ; |
.equ ADC12D = 4 ; |
.equ ADC13D = 5 ; |
.equ ADC14D = 6 ; |
.equ ADC15D = 7 ; |
; ***** BOOT_LOAD ******************** |
; SPMCSR - Store Program Memory Control Register |
.equ SPMEN = 0 ; Store Program Memory Enable |
.equ PGERS = 1 ; Page Erase |
.equ PGWRT = 2 ; Page Write |
.equ BLBSET = 3 ; Boot Lock Bit Set |
.equ RWWSRE = 4 ; Read While Write section read enable |
.equ SIGRD = 5 ; Signature Row Read |
.equ RWWSB = 6 ; Read While Write Section Busy |
.equ SPMIE = 7 ; SPM Interrupt Enable |
; ***** LOCKSBITS ******************************************************** |
.equ LB1 = 0 ; Lock bit |
.equ LB2 = 1 ; Lock bit |
.equ BLB01 = 2 ; Boot Lock bit |
.equ BLB02 = 3 ; Boot Lock bit |
.equ BLB11 = 4 ; Boot lock bit |
.equ BLB12 = 5 ; Boot lock bit |
; ***** FUSES ************************************************************ |
; LOW fuse bits |
.equ CKSEL0 = 0 ; Select Clock Source |
.equ CKSEL1 = 1 ; Select Clock Source |
.equ CKSEL2 = 2 ; Select Clock Source |
.equ CKSEL3 = 3 ; Select Clock Source |
.equ SUT0 = 4 ; Select start-up time |
.equ SUT1 = 5 ; Select start-up time |
.equ CKOUT = 6 ; Oscillator options |
.equ CLKDIV8 = 7 ; Divide clock by 8 |
; HIGH fuse bits |
.equ BOOTRST = 0 ; Select Reset Vector |
.equ BOOTSZ0 = 1 ; Select Boot Size |
.equ BOOTSZ1 = 2 ; Select Boot Size |
.equ EESAVE = 3 ; EEPROM memory is preserved through chip erase |
.equ WDTON = 4 ; Watchdog timer always on |
.equ SPIEN = 5 ; Enable Serial programming and Data Downloading |
.equ JTAGEN = 6 ; Enable JTAG |
.equ OCDEN = 7 ; Enable OCD |
; EXTENDED fuse bits |
.equ BODLEVEL0 = 0 ; Brown-out Detector trigger level |
.equ BODLEVEL1 = 1 ; Brown-out Detector trigger level |
.equ BODLEVEL2 = 2 ; Brown-out Detector trigger level |
; ***** CPU REGISTER DEFINITIONS ***************************************** |
.def XH = r27 |
.def XL = r26 |
.def YH = r29 |
.def YL = r28 |
.def ZH = r31 |
.def ZL = r30 |
; ***** DATA MEMORY DECLARATIONS ***************************************** |
.equ FLASHEND = 0x1ffff ; Note: Word address |
.equ IOEND = 0x01ff |
.equ SRAM_START = 0x0200 |
.equ SRAM_SIZE = 8192 |
.equ RAMEND = 0x21ff |
.equ XRAMEND = 0xffff |
.equ E2END = 0x0fff |
.equ EEPROMEND = 0x0fff |
.equ EEADRBITS = 12 |
#pragma AVRPART MEMORY PROG_FLASH 262144 |
#pragma AVRPART MEMORY EEPROM 4096 |
#pragma AVRPART MEMORY INT_SRAM SIZE 8192 |
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x200 |
; ***** BOOTLOADER DECLARATIONS ****************************************** |
.equ NRWW_START_ADDR = 0x1f000 |
.equ NRWW_STOP_ADDR = 0x1ffff |
.equ RWW_START_ADDR = 0x0 |
.equ RWW_STOP_ADDR = 0x1efff |
.equ PAGESIZE = 128 |
.equ FIRSTBOOTSTART = 0x1fe00 |
.equ SECONDBOOTSTART = 0x1fc00 |
.equ THIRDBOOTSTART = 0x1f800 |
.equ FOURTHBOOTSTART = 0x1f000 |
.equ SMALLBOOTSTART = FIRSTBOOTSTART |
.equ LARGEBOOTSTART = FOURTHBOOTSTART |
; ***** INTERRUPT VECTORS ************************************************ |
.equ INT0addr = 0x0002 ; External Interrupt Request 0 |
.equ INT1addr = 0x0004 ; External Interrupt Request 1 |
.equ INT2addr = 0x0006 ; External Interrupt Request 2 |
.equ INT3addr = 0x0008 ; External Interrupt Request 3 |
.equ INT4addr = 0x000a ; External Interrupt Request 4 |
.equ INT5addr = 0x000c ; External Interrupt Request 5 |
.equ INT6addr = 0x000e ; External Interrupt Request 6 |
.equ INT7addr = 0x0010 ; External Interrupt Request 7 |
.equ PCI0addr = 0x0012 ; Pin Change Interrupt Request 0 |
.equ PCI1addr = 0x0014 ; Pin Change Interrupt Request 1 |
.equ PCI2addr = 0x0016 ; Pin Change Interrupt Request 2 |
.equ WDTaddr = 0x0018 ; Watchdog Time-out Interrupt |
.equ OC2Aaddr = 0x001a ; Timer/Counter2 Compare Match A |
.equ OC2Baddr = 0x001c ; Timer/Counter2 Compare Match B |
.equ OVF2addr = 0x001e ; Timer/Counter2 Overflow |
.equ ICP1addr = 0x0020 ; Timer/Counter1 Capture Event |
.equ OC1Aaddr = 0x0022 ; Timer/Counter1 Compare Match A |
.equ OC1Baddr = 0x0024 ; Timer/Counter1 Compare Match B |
.equ OC1Caddr = 0x0026 ; Timer/Counter1 Compare Match C |
.equ OVF1addr = 0x0028 ; Timer/Counter1 Overflow |
.equ OC0Aaddr = 0x002a ; Timer/Counter0 Compare Match A |
.equ OC0Baddr = 0x002c ; Timer/Counter0 Compare Match B |
.equ OVF0addr = 0x002e ; Timer/Counter0 Overflow |
.equ SPIaddr = 0x0030 ; SPI Serial Transfer Complete |
.equ URXC0addr = 0x0032 ; USART0, Rx Complete |
.equ UDRE0addr = 0x0034 ; USART0 Data register Empty |
.equ UTXC0addr = 0x0036 ; USART0, Tx Complete |
.equ ACIaddr = 0x0038 ; Analog Comparator |
.equ ADCCaddr = 0x003a ; ADC Conversion Complete |
.equ ERDYaddr = 0x003c ; EEPROM Ready |
.equ ICP3addr = 0x003e ; Timer/Counter3 Capture Event |
.equ OC3Aaddr = 0x0040 ; Timer/Counter3 Compare Match A |
.equ OC3Baddr = 0x0042 ; Timer/Counter3 Compare Match B |
.equ OC3Caddr = 0x0044 ; Timer/Counter3 Compare Match C |
.equ OVF3addr = 0x0046 ; Timer/Counter3 Overflow |
.equ URXC1addr = 0x0048 ; USART1, Rx Complete |
.equ UDRE1addr = 0x004a ; USART1 Data register Empty |
.equ UTXC1addr = 0x004c ; USART1, Tx Complete |
.equ TWIaddr = 0x004e ; 2-wire Serial Interface |
.equ SPMRaddr = 0x0050 ; Store Program Memory Read |
.equ ICP4addr = 0x0052 ; Timer/Counter4 Capture Event |
.equ OC4Aaddr = 0x0054 ; Timer/Counter4 Compare Match A |
.equ OC4Baddr = 0x0056 ; Timer/Counter4 Compare Match B |
.equ OC4Caddr = 0x0058 ; Timer/Counter4 Compare Match C |
.equ OVF4addr = 0x005a ; Timer/Counter4 Overflow |
.equ ICP5addr = 0x005c ; Timer/Counter5 Capture Event |
.equ OC5Aaddr = 0x005e ; Timer/Counter5 Compare Match A |
.equ OC5Baddr = 0x0060 ; Timer/Counter5 Compare Match B |
.equ OC5Caddr = 0x0062 ; Timer/Counter5 Compare Match C |
.equ OVF5addr = 0x0064 ; Timer/Counter5 Overflow |
.equ URXC2addr = 0x0066 ; USART2, Rx Complete |
.equ UDRE2addr = 0x0068 ; USART2 Data register Empty |
.equ UTXC2addr = 0x006a ; USART2, Tx Complete |
.equ URXC3addr = 0x006c ; USART3, Rx Complete |
.equ UDRE3addr = 0x006e ; USART3 Data register Empty |
.equ UTXC3addr = 0x0070 ; USART3, Tx Complete |
.equ INT_VECTORS_SIZE = 114 ; size in words |
#endif /* _M2561DEF_INC_ */ |
; ***** END OF FILE ****************************************************** |
/contrib/toolchain/avra/includes/m323def.inc |
---|
0,0 → 1,793 |
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** |
;***** Created: 2005-01-11 10:31 ******* Source: ATmega323.xml *********** |
;************************************************************************* |
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y |
;* |
;* Number : AVR000 |
;* File Name : "m323def.inc" |
;* Title : Register/Bit Definitions for the ATmega323 |
;* Date : 2005-01-11 |
;* Version : 2.14 |
;* Support E-mail : avr@atmel.com |
;* Target MCU : ATmega323 |
;* |
;* DESCRIPTION |
;* When including this file in the assembly program file, all I/O register |
;* names and I/O register bit names appearing in the data book can be used. |
;* In addition, the six registers forming the three data pointers X, Y and |
;* Z have been assigned names XL - ZH. Highest RAM address for Internal |
;* SRAM is also defined |
;* |
;* The Register names are represented by their hexadecimal address. |
;* |
;* The Register Bit names are represented by their bit number (0-7). |
;* |
;* Please observe the difference in using the bit names with instructions |
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" |
;* (skip if bit in register set/cleared). The following example illustrates |
;* this: |
;* |
;* in r16,PORTB ;read PORTB latch |
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) |
;* out PORTB,r16 ;output to PORTB |
;* |
;* in r16,TIFR ;read the Timer Interrupt Flag Register |
;* sbrc r16,TOV0 ;test the overflow flag (use bit#) |
;* rjmp TOV0_is_set ;jump if set |
;* ... ;otherwise do something else |
;************************************************************************* |
#ifndef _M323DEF_INC_ |
#define _M323DEF_INC_ |
#pragma partinc 0 |
; ***** SPECIFY DEVICE *************************************************** |
.device ATmega323 |
#pragma AVRPART ADMIN PART_NAME ATmega323 |
.equ SIGNATURE_000 = 0x1e |
.equ SIGNATURE_001 = 0x95 |
.equ SIGNATURE_002 = 0x01 |
#pragma AVRPART CORE CORE_VERSION V2E |
; ***** I/O REGISTER DEFINITIONS ***************************************** |
; NOTE: |
; Definitions marked "MEMORY MAPPED"are extended I/O ports |
; and cannot be used with IN/OUT instructions |
.equ SREG = 0x3f |
.equ SPH = 0x3e |
.equ SPL = 0x3d |
.equ OCR0 = 0x3c |
.equ GICR = 0x3b |
.equ GIFR = 0x3a |
.equ TIMSK = 0x39 |
.equ TIFR = 0x38 |
.equ SPMCR = 0x37 |
.equ TWCR = 0x36 |
.equ MCUCR = 0x35 |
.equ MCUCSR = 0x34 |
.equ TCCR0 = 0x33 |
.equ TCNT0 = 0x32 |
.equ OSCCAL = 0x31 |
.equ OCDR = 0x31 |
.equ SFIOR = 0x30 |
.equ TCCR1A = 0x2f |
.equ TCCR1B = 0x2e |
.equ TCNT1H = 0x2d |
.equ TCNT1L = 0x2c |
.equ OCR1AH = 0x2b |
.equ OCR1AL = 0x2a |
.equ OCR1BH = 0x29 |
.equ OCR1BL = 0x28 |
.equ ICR1H = 0x27 |
.equ ICR1L = 0x26 |
.equ TCCR2 = 0x25 |
.equ TCNT2 = 0x24 |
.equ OCR2 = 0x23 |
.equ ASSR = 0x22 |
.equ WDTCR = 0x21 |
.equ UBRRH = 0x20 |
.equ UCSRC = 0x20 |
.equ EEARH = 0x1f |
.equ EEARL = 0x1e |
.equ EEDR = 0x1d |
.equ EECR = 0x1c |
.equ PORTA = 0x1b |
.equ DDRA = 0x1a |
.equ PINA = 0x19 |
.equ PORTB = 0x18 |
.equ DDRB = 0x17 |
.equ PINB = 0x16 |
.equ PORTC = 0x15 |
.equ DDRC = 0x14 |
.equ PINC = 0x13 |
.equ PORTD = 0x12 |
.equ DDRD = 0x11 |
.equ PIND = 0x10 |
.equ SPDR = 0x0f |
.equ SPSR = 0x0e |
.equ SPCR = 0x0d |
.equ UDR = 0x0c |
.equ UCSRA = 0x0b |
.equ UCSRB = 0x0a |
.equ UBRRL = 0x09 |
.equ ACSR = 0x08 |
.equ ADMUX = 0x07 |
.equ ADCSR = 0x06 |
.equ ADCH = 0x05 |
.equ ADCL = 0x04 |
.equ TWDR = 0x03 |
.equ TWAR = 0x02 |
.equ TWSR = 0x01 |
.equ TWBR = 0x00 |
; ***** BIT DEFINITIONS ************************************************** |
; ***** PORTA ************************ |
; PORTA - Port A Data Register |
.equ PORTA0 = 0 ; Port A Data Register bit 0 |
.equ PA0 = 0 ; For compatibility |
.equ PORTA1 = 1 ; Port A Data Register bit 1 |
.equ PA1 = 1 ; For compatibility |
.equ PORTA2 = 2 ; Port A Data Register bit 2 |
.equ PA2 = 2 ; For compatibility |
.equ PORTA3 = 3 ; Port A Data Register bit 3 |
.equ PA3 = 3 ; For compatibility |
.equ PORTA4 = 4 ; Port A Data Register bit 4 |
.equ PA4 = 4 ; For compatibility |
.equ PORTA5 = 5 ; Port A Data Register bit 5 |
.equ PA5 = 5 ; For compatibility |
.equ PORTA6 = 6 ; Port A Data Register bit 6 |
.equ PA6 = 6 ; For compatibility |
.equ PORTA7 = 7 ; Port A Data Register bit 7 |
.equ PA7 = 7 ; For compatibility |
; DDRA - Port A Data Direction Register |
.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0 |
.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1 |
.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2 |
.equ DDA3 = 3 ; Data Direction Register, Port A, bit 3 |
.equ DDA4 = 4 ; Data Direction Register, Port A, bit 4 |
.equ DDA5 = 5 ; Data Direction Register, Port A, bit 5 |
.equ DDA6 = 6 ; Data Direction Register, Port A, bit 6 |
.equ DDA7 = 7 ; Data Direction Register, Port A, bit 7 |
; PINA - Port A Input Pins |
.equ PINA0 = 0 ; Input Pins, Port A bit 0 |
.equ PINA1 = 1 ; Input Pins, Port A bit 1 |
.equ PINA2 = 2 ; Input Pins, Port A bit 2 |
.equ PINA3 = 3 ; Input Pins, Port A bit 3 |
.equ PINA4 = 4 ; Input Pins, Port A bit 4 |
.equ PINA5 = 5 ; Input Pins, Port A bit 5 |
.equ PINA6 = 6 ; Input Pins, Port A bit 6 |
.equ PINA7 = 7 ; Input Pins, Port A bit 7 |
; ***** PORTB ************************ |
; PORTB - Port B Data Register |
.equ PORTB0 = 0 ; Port B Data Register bit 0 |
.equ PB0 = 0 ; For compatibility |
.equ PORTB1 = 1 ; Port B Data Register bit 1 |
.equ PB1 = 1 ; For compatibility |
.equ PORTB2 = 2 ; Port B Data Register bit 2 |
.equ PB2 = 2 ; For compatibility |
.equ PORTB3 = 3 ; Port B Data Register bit 3 |
.equ PB3 = 3 ; For compatibility |
.equ PORTB4 = 4 ; Port B Data Register bit 4 |
.equ PB4 = 4 ; For compatibility |
.equ PORTB5 = 5 ; Port B Data Register bit 5 |
.equ PB5 = 5 ; For compatibility |
.equ PORTB6 = 6 ; Port B Data Register bit 6 |
.equ PB6 = 6 ; For compatibility |
.equ PORTB7 = 7 ; Port B Data Register bit 7 |
.equ PB7 = 7 ; For compatibility |
; DDRB - Port B Data Direction Register |
.equ DDB0 = 0 ; Port B Data Direction Register bit 0 |
.equ DDB1 = 1 ; Port B Data Direction Register bit 1 |
.equ DDB2 = 2 ; Port B Data Direction Register bit 2 |
.equ DDB3 = 3 ; Port B Data Direction Register bit 3 |
.equ DDB4 = 4 ; Port B Data Direction Register bit 4 |
.equ DDB5 = 5 ; Port B Data Direction Register bit 5 |
.equ DDB6 = 6 ; Port B Data Direction Register bit 6 |
.equ DDB7 = 7 ; Port B Data Direction Register bit 7 |
; PINB - Port B Input Pins |
.equ PINB0 = 0 ; Port B Input Pins bit 0 |
.equ PINB1 = 1 ; Port B Input Pins bit 1 |
.equ PINB2 = 2 ; Port B Input Pins bit 2 |
.equ PINB3 = 3 ; Port B Input Pins bit 3 |
.equ PINB4 = 4 ; Port B Input Pins bit 4 |
.equ PINB5 = 5 ; Port B Input Pins bit 5 |
.equ PINB6 = 6 ; Port B Input Pins bit 6 |
.equ PINB7 = 7 ; Port B Input Pins bit 7 |
; ***** PORTC ************************ |
; PORTC - Port C Data Register |
.equ PORTC0 = 0 ; Port C Data Register bit 0 |
.equ PC0 = 0 ; For compatibility |
.equ PORTC1 = 1 ; Port C Data Register bit 1 |
.equ PC1 = 1 ; For compatibility |
.equ PORTC2 = 2 ; Port C Data Register bit 2 |
.equ PC2 = 2 ; For compatibility |
.equ PORTC3 = 3 ; Port C Data Register bit 3 |
.equ PC3 = 3 ; For compatibility |
.equ PORTC4 = 4 ; Port C Data Register bit 4 |
.equ PC4 = 4 ; For compatibility |
.equ PORTC5 = 5 ; Port C Data Register bit 5 |
.equ PC5 = 5 ; For compatibility |
.equ PORTC6 = 6 ; Port C Data Register bit 6 |
.equ PC6 = 6 ; For compatibility |
.equ PORTC7 = 7 ; Port C Data Register bit 7 |
.equ PC7 = 7 ; For compatibility |
; DDRC - Port C Data Direction Register |
.equ DDC0 = 0 ; Port C Data Direction Register bit 0 |
.equ DDC1 = 1 ; Port C Data Direction Register bit 1 |
.equ DDC2 = 2 ; Port C Data Direction Register bit 2 |
.equ DDC3 = 3 ; Port C Data Direction Register bit 3 |
.equ DDC4 = 4 ; Port C Data Direction Register bit 4 |
.equ DDC5 = 5 ; Port C Data Direction Register bit 5 |
.equ DDC6 = 6 ; Port C Data Direction Register bit 6 |
.equ DDC7 = 7 ; Port C Data Direction Register bit 7 |
; PINC - Port C Input Pins |
.equ PINC0 = 0 ; Port C Input Pins bit 0 |
.equ PINC1 = 1 ; Port C Input Pins bit 1 |
.equ PINC2 = 2 ; Port C Input Pins bit 2 |
.equ PINC3 = 3 ; Port C Input Pins bit 3 |
.equ PINC4 = 4 ; Port C Input Pins bit 4 |
.equ PINC5 = 5 ; Port C Input Pins bit 5 |
.equ PINC6 = 6 ; Port C Input Pins bit 6 |
.equ PINC7 = 7 ; Port C Input Pins bit 7 |
; ***** PORTD ************************ |
; PORTD - Port D Data Register |
.equ PORTD0 = 0 ; Port D Data Register bit 0 |
.equ PD0 = 0 ; For compatibility |
.equ PORTD1 = 1 ; Port D Data Register bit 1 |
.equ PD1 = 1 ; For compatibility |
.equ PORTD2 = 2 ; Port D Data Register bit 2 |
.equ PD2 = 2 ; For compatibility |
.equ PORTD3 = 3 ; Port D Data Register bit 3 |
.equ PD3 = 3 ; For compatibility |
.equ PORTD4 = 4 ; Port D Data Register bit 4 |
.equ PD4 = 4 ; For compatibility |
.equ PORTD5 = 5 ; Port D Data Register bit 5 |
.equ PD5 = 5 ; For compatibility |
.equ PORTD6 = 6 ; Port D Data Register bit 6 |
.equ PD6 = 6 ; For compatibility |
.equ PORTD7 = 7 ; Port D Data Register bit 7 |
.equ PD7 = 7 ; For compatibility |
; DDRD - Port D Data Direction Register |
.equ DDD0 = 0 ; Port D Data Direction Register bit 0 |
.equ DDD1 = 1 ; Port D Data Direction Register bit 1 |
.equ DDD2 = 2 ; Port D Data Direction Register bit 2 |
.equ DDD3 = 3 ; Port D Data Direction Register bit 3 |
.equ DDD4 = 4 ; Port D Data Direction Register bit 4 |
.equ DDD5 = 5 ; Port D Data Direction Register bit 5 |
.equ DDD6 = 6 ; Port D Data Direction Register bit 6 |
.equ DDD7 = 7 ; Port D Data Direction Register bit 7 |
; PIND - Port D Input Pins |
.equ PIND0 = 0 ; Port D Input Pins bit 0 |
.equ PIND1 = 1 ; Port D Input Pins bit 1 |
.equ PIND2 = 2 ; Port D Input Pins bit 2 |
.equ PIND3 = 3 ; Port D Input Pins bit 3 |
.equ PIND4 = 4 ; Port D Input Pins bit 4 |
.equ PIND5 = 5 ; Port D Input Pins bit 5 |
.equ PIND6 = 6 ; Port D Input Pins bit 6 |
.equ PIND7 = 7 ; Port D Input Pins bit 7 |
; ***** WATCHDOG ********************* |
; WDTCR - Watchdog Timer Control Register |
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 |
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 |
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 |
.equ WDE = 3 ; Watch Dog Enable |
.equ WDTOE = 4 ; RW |
.equ WDDE = WDTOE ; For compatibility |
; ***** SPI ************************** |
; SPDR - SPI Data Register |
.equ SPDR0 = 0 ; SPI Data Register bit 0 |
.equ SPDR1 = 1 ; SPI Data Register bit 1 |
.equ SPDR2 = 2 ; SPI Data Register bit 2 |
.equ SPDR3 = 3 ; SPI Data Register bit 3 |
.equ SPDR4 = 4 ; SPI Data Register bit 4 |
.equ SPDR5 = 5 ; SPI Data Register bit 5 |
.equ SPDR6 = 6 ; SPI Data Register bit 6 |
.equ SPDR7 = 7 ; SPI Data Register bit 7 |
; SPSR - SPI Status Register |
.equ SPI2X = 0 ; Double SPI Speed Bit |
.equ WCOL = 6 ; Write Collision Flag |
.equ SPIF = 7 ; SPI Interrupt Flag |
; SPCR - SPI Control Register |
.equ SPR0 = 0 ; SPI Clock Rate Select 0 |
.equ SPR1 = 1 ; SPI Clock Rate Select 1 |
.equ CPHA = 2 ; Clock Phase |
.equ CPOL = 3 ; Clock polarity |
.equ MSTR = 4 ; Master/Slave Select |
.equ DORD = 5 ; Data Order |
.equ SPE = 6 ; SPI Enable |
.equ SPIE = 7 ; SPI Interrupt Enable |
; ***** USART ************************ |
; UDR - USART I/O Data Register |
.equ UDR0 = 0 ; USART I/O Data Register bit 0 |
.equ UDR1 = 1 ; USART I/O Data Register bit 1 |
.equ UDR2 = 2 ; USART I/O Data Register bit 2 |
.equ UDR3 = 3 ; USART I/O Data Register bit 3 |
.equ UDR4 = 4 ; USART I/O Data Register bit 4 |
.equ UDR5 = 5 ; USART I/O Data Register bit 5 |
.equ UDR6 = 6 ; USART I/O Data Register bit 6 |
.equ UDR7 = 7 ; USART I/O Data Register bit 7 |
; UCSRA - USART Control and Status Register A |
.equ USR = UCSRA ; For compatibility |
.equ MPCM = 0 ; Multi-processor Communication Mode |
.equ U2X = 1 ; Double the USART transmission speed |
.equ UPE = 2 ; Parity Error |
.equ PE = UPE ; For compatibility |
.equ DOR = 3 ; Data overRun |
.equ FE = 4 ; Framing Error |
.equ UDRE = 5 ; USART Data Register Empty |
.equ TXC = 6 ; USART Transmitt Complete |
.equ RXC = 7 ; USART Receive Complete |
; UCSRB - USART Control and Status Register B |
.equ UCR = UCSRB ; For compatibility |
.equ TXB8 = 0 ; Transmit Data Bit 8 |
.equ RXB8 = 1 ; Receive Data Bit 8 |
.equ UCSZ2 = 2 ; Character Size |
.equ CHR9 = UCSZ2 ; For compatibility |
.equ TXEN = 3 ; Transmitter Enable |
.equ RXEN = 4 ; Receiver Enable |
.equ UDRIE = 5 ; USART Data register Empty Interrupt Enable |
.equ TXCIE = 6 ; TX Complete Interrupt Enable |
.equ RXCIE = 7 ; RX Complete Interrupt Enable |
; UCSRC - USART Control and Status Register C |
.equ UCPOL = 0 ; Clock Polarity |
.equ UCSZ0 = 1 ; Character Size |
.equ UCSZ1 = 2 ; Character Size |
.equ USBS = 3 ; Stop Bit Select |
.equ UPM0 = 4 ; Parity Mode Bit 0 |
.equ UPM1 = 5 ; Parity Mode Bit 1 |
.equ UMSEL = 6 ; USART Mode Select |
.equ URSEL = 7 ; Register Select |
.equ UBRRHI = UBRRH ; For compatibility |
; ***** AD_CONVERTER ***************** |
; ADMUX - The ADC multiplexer Selection Register |
.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits |
.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits |
.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits |
.equ MUX3 = 3 ; Analog Channel and Gain Selection Bits |
.equ MUX4 = 4 ; Analog Channel and Gain Selection Bits |
.equ ADLAR = 5 ; Left Adjust Result |
.equ REFS0 = 6 ; Reference Selection Bit 0 |
.equ REFS1 = 7 ; Reference Selection Bit 1 |
; ADCSR - The ADC Control and Status register |
.equ ADPS0 = 0 ; ADC Prescaler Select Bits |
.equ ADPS1 = 1 ; ADC Prescaler Select Bits |
.equ ADPS2 = 2 ; ADC Prescaler Select Bits |
.equ ADIE = 3 ; ADC Interrupt Enable |
.equ ADIF = 4 ; ADC Interrupt Flag |
.equ ADATE = 5 ; When this bit is written to one,the Timer/Counter2 prescaler will be reset.The bit will be cleared by hardware after the operation is performed.Writing a zero to this bit will have no effect.This bit will always be read as zero if Timer/Counter2 is clocked by the internal CPU clock.If this bit is written when Timer/Counter2 is operating in asynchronous mode,the bit will remain one until the prescaler has been reset. |
.equ ADSC = 6 ; ADC Start Conversion |
.equ ADEN = 7 ; ADC Enable |
; ADCH - ADC Data Register High Byte |
.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0 |
.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1 |
.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2 |
.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3 |
.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4 |
.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5 |
.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6 |
.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7 |
; ADCL - ADC Data Register Low Byte |
.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0 |
.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1 |
.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2 |
.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3 |
.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4 |
.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5 |
.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6 |
.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7 |
; ***** ANALOG_COMPARATOR ************ |
; SFIOR - Special Function IO Register |
.equ ACME = 3 ; Analog Comparator Multiplexer Enable |
; ACSR - Analog Comparator Control And Status Register |
.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 |
.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 |
.equ ACIC = 2 ; Analog Comparator Input Capture Enable |
.equ ACIE = 3 ; Analog Comparator Interrupt Enable |
.equ ACI = 4 ; Analog Comparator Interrupt Flag |
.equ ACO = 5 ; Analog Compare Output |
.equ ACBG = 6 ; Analog Comparator Bandgap Select |
.equ ACD = 7 ; Analog Comparator Disable |
; ***** TWI ************************** |
; TWBR - TWI Bit Rate register |
.equ TWBR0 = 0 ; |
.equ TWBR1 = 1 ; |
.equ TWBR2 = 2 ; |
.equ TWBR3 = 3 ; |
.equ TWBR4 = 4 ; |
.equ TWBR5 = 5 ; |
.equ TWBR6 = 6 ; |
.equ TWBR7 = 7 ; |
; TWCR - TWI Control Register |
.equ TWIE = 0 ; TWI Interrupt Enable |
.equ TWEN = 2 ; TWI Enable Bit |
.equ TWWC = 3 ; TWI Write Collition Flag |
.equ TWSTO = 4 ; TWI Stop Condition Bit |
.equ TWSTA = 5 ; TWI Start Condition Bit |
.equ TWEA = 6 ; TWI Enable Acknowledge Bit |
.equ TWINT = 7 ; TWI Interrupt Flag |
; TWSR - TWI Status Register |
.equ TWS3 = 3 ; TWI Status |
.equ TWS4 = 4 ; TWI Status |
.equ TWS5 = 5 ; TWI Status |
.equ TWS6 = 6 ; TWI Status |
.equ TWS7 = 7 ; TWI Status |
; TWDR - TWI Data register |
.equ TWD0 = 0 ; TWI Data Register Bit 0 |
.equ TWD1 = 1 ; TWI Data Register Bit 1 |
.equ TWD2 = 2 ; TWI Data Register Bit 2 |
.equ TWD3 = 3 ; TWI Data Register Bit 3 |
.equ TWD4 = 4 ; TWI Data Register Bit 4 |
.equ TWD5 = 5 ; TWI Data Register Bit 5 |
.equ TWD6 = 6 ; TWI Data Register Bit 6 |
.equ TWD7 = 7 ; TWI Data Register Bit 7 |
; TWAR - TWI (Slave) Address register |
.equ TWGCE = 0 ; TWI General Call Recognition Enable Bit |
.equ TWA0 = 1 ; TWI (Slave) Address register Bit 0 |
.equ TWA1 = 2 ; TWI (Slave) Address register Bit 1 |
.equ TWA2 = 3 ; TWI (Slave) Address register Bit 2 |
.equ TWA3 = 4 ; TWI (Slave) Address register Bit 3 |
.equ TWA4 = 5 ; TWI (Slave) Address register Bit 4 |
.equ TWA5 = 6 ; TWI (Slave) Address register Bit 5 |
.equ TWA6 = 7 ; TWI (Slave) Address register Bit 6 |
; ***** EEPROM *********************** |
; EEDR - EEPROM Data Register |
.equ EEDR0 = 0 ; EEPROM Data Register bit 0 |
.equ EEDR1 = 1 ; EEPROM Data Register bit 1 |
.equ EEDR2 = 2 ; EEPROM Data Register bit 2 |
.equ EEDR3 = 3 ; EEPROM Data Register bit 3 |
.equ EEDR4 = 4 ; EEPROM Data Register bit 4 |
.equ EEDR5 = 5 ; EEPROM Data Register bit 5 |
.equ EEDR6 = 6 ; EEPROM Data Register bit 6 |
.equ EEDR7 = 7 ; EEPROM Data Register bit 7 |
; EECR - EEPROM Control Register |
.equ EERE = 0 ; EEPROM Read Enable |
.equ EEWE = 1 ; EEPROM Write Enable |
.equ EEMWE = 2 ; EEPROM Master Write Enable |
.equ EERIE = 3 ; EEPROM Ready Interrupt Enable |
; ***** CPU ************************** |
; SREG - Status Register |
.equ SREG_C = 0 ; Carry Flag |
.equ SREG_Z = 1 ; Zero Flag |
.equ SREG_N = 2 ; Negative Flag |
.equ SREG_V = 3 ; Two's Complement Overflow Flag |
.equ SREG_S = 4 ; Sign Bit |
.equ SREG_H = 5 ; Half Carry Flag |
.equ SREG_T = 6 ; Bit Copy Storage |
.equ SREG_I = 7 ; Global Interrupt Enable |
; MCUCR - MCU Control Register |
.equ ISC00 = 0 ; Interrupt Sense Control 0 Bit 0 |
.equ ISC01 = 1 ; Interrupt Sense Control 0 Bit 1 |
.equ ISC10 = 2 ; Interrupt Sense Control 1 Bit 0 |
.equ ISC11 = 3 ; Interrupt Sense Control 1 Bit 1 |
.equ SM0 = 4 ; Sleep Mode Select |
.equ SM1 = 5 ; Sleep Mode Select |
.equ SM2 = 6 ; Sleep Mode Select |
.equ SE = 7 ; Sleep Enable |
; MCUCSR - MCU Control And Status Register |
.equ PORF = 0 ; Power-on reset flag |
.equ EXTRF = 1 ; External Reset Flag |
.equ BORF = 2 ; Brown-out Reset Flag |
.equ WDRF = 3 ; Watchdog Reset Flag |
.equ JTRF = 4 ; JTAG Reset Flag |
.equ ISC2 = 6 ; Interrupt Sense Control 2 |
.equ JDT = 7 ; |
; OSCCAL - Oscillator Calibration Value |
.equ CAL0 = 0 ; Oscillator Calibration Value Bit0 |
.equ CAL1 = 1 ; Oscillator Calibration Value Bit1 |
.equ CAL2 = 2 ; Oscillator Calibration Value Bit2 |
.equ CAL3 = 3 ; Oscillator Calibration Value Bit3 |
.equ CAL4 = 4 ; Oscillator Calibration Value Bit4 |
.equ CAL5 = 5 ; Oscillator Calibration Value Bit5 |
.equ CAL6 = 6 ; Oscillator Calibration Value Bit6 |
.equ CAL7 = 7 ; Oscillator Calibration Value Bit7 |
; SPMCR - Store Program Memory Control Register |
.equ SPMEN = 0 ; Store Program Memory Enable |
.equ PGERS = 1 ; Page Erase |
.equ PGWRT = 2 ; Page Write |
.equ BLBSET = 3 |
.equ ASRE = 4 ; Application Section Read Enable |
.equ ASB = 6 ; Applcaiton Section Busy |
; SFIOR - Special Function IO Register |
.equ PSR10 = 0 ; |
.equ PSR2 = 1 ; Prescaler Reset Timer/Counter2 |
.equ PUD = 2 ; Pull-up Disable |
;.equ ACME = 3 ; |
; ***** TIMER_COUNTER_0 ************** |
; TCCR0 - Timer/Counter Control Register |
.equ CS00 = 0 ; Clock Select 1 |
.equ CS01 = 1 ; Clock Select 1 |
.equ CS02 = 2 ; Clock Select 2 |
.equ WGM01 = 3 ; Waveform Generation Mode 1 |
.equ COM00 = 4 ; Compare match Output Mode 0 |
.equ COM01 = 5 ; Compare Match Output Mode 1 |
.equ PWM0 = 6 ; Pulse Width Modulator Enable |
.equ FOC0 = 7 ; Force Output Compare |
; TCNT0 - Timer/Counter Register |
.equ TCNT0_0 = 0 ; |
.equ TCNT0_1 = 1 ; |
.equ TCNT0_2 = 2 ; |
.equ TCNT0_3 = 3 ; |
.equ TCNT0_4 = 4 ; |
.equ TCNT0_5 = 5 ; |
.equ TCNT0_6 = 6 ; |
.equ TCNT0_7 = 7 ; |
; OCR0 - Output Compare Register |
.equ OCR0_0 = 0 ; |
.equ OCR0_1 = 1 ; |
.equ OCR0_2 = 2 ; |
.equ OCR0_3 = 3 ; |
.equ OCR0_4 = 4 ; |
.equ OCR0_5 = 5 ; |
.equ OCR0_6 = 6 ; |
.equ OCR0_7 = 7 ; |
; TIMSK - Timer/Counter Interrupt Mask Register |
.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable |
.equ OCIE0 = 1 ; Timer/Counter0 Output Compare Match Interrupt register |
; TIFR - Timer/Counter Interrupt Flag register |
.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag |
.equ OCF0 = 1 ; Output Compare Flag 0 |
; SFIOR - Special Function IO Register |
;.equ PSR10 = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0 |
; ***** EXTERNAL_INTERRUPT *********** |
; GICR - General Interrupt Control Register |
.equ GIMSK = GICR ; For compatibility |
.equ IVCE = 0 ; Interrupt Vector Change Enable |
.equ IVSEL = 1 ; Interrupt Vector Select |
.equ INT2 = 5 ; External Interrupt Request 2 Enable |
.equ INT0 = 6 ; External Interrupt Request 0 Enable |
.equ INT1 = 7 ; External Interrupt Request 1 Enable |
; GIFR - General Interrupt Flag Register |
.equ INTF2 = 5 ; External Interrupt Flag 2 |
.equ INTF0 = 6 ; External Interrupt Flag 0 |
.equ INTF1 = 7 ; External Interrupt Flag 1 |
; MCUCR - General Interrupt Control Register |
;.equ ISC00 = 0 ; Interrupt Sense Control 0 Bit 0 |
;.equ ISC01 = 1 ; Interrupt Sense Control 0 Bit 1 |
;.equ ISC10 = 2 ; Interrupt Sense Control 1 Bit 0 |
;.equ ISC11 = 3 ; Interrupt Sense Control 1 Bit 1 |
; MCUCSR - MCU Control And Status Register |
;.equ ISC2 = 6 ; Interrupt Sense Control 2 |
; ***** TIMER_COUNTER_1 ************** |
; TIMSK - Timer/Counter Interrupt Mask Register |
.equ TOIE1 = 2 ; Timer/Counter1 Overflow Interrupt Enable |
.equ OCIE1B = 3 ; Timer/Counter1 Output CompareB Match Interrupt Enable |
.equ OCIE1A = 4 ; Timer/Counter1 Output CompareA Match Interrupt Enable |
.equ TICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable |
; TIFR - Timer/Counter Interrupt Flag register |
.equ TOV1 = 2 ; Timer/Counter1 Overflow Flag |
.equ OCF1B = 3 ; Output Compare Flag 1B |
.equ OCF1A = 4 ; Output Compare Flag 1A |
.equ ICF1 = 5 ; Input Capture Flag 1 |
; TCCR1A - Timer/Counter1 Control Register A |
.equ WGM10 = 0 ; Waveform Generation Mode |
.equ WGM11 = 1 ; Waveform Generation Mode |
.equ FOC1B = 2 ; Force Output Compare 1B |
.equ FOC1A = 3 ; Force Output Compare 1A |
.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0 |
.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1 |
.equ COM1A0 = 6 ; Comparet Ouput Mode 1A, bit 0 |
.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1 |
; TCCR1B - Timer/Counter1 Control Register B |
.equ CS10 = 0 ; Prescaler source of Timer/Counter 1 |
.equ CS11 = 1 ; Prescaler source of Timer/Counter 1 |
.equ CS12 = 2 ; Prescaler source of Timer/Counter 1 |
.equ CTC1 = 3 ; Clear Timer/Counter1 on Compare Match |
.equ ICES1 = 6 ; Input Capture 1 Edge Select |
.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler |
; ***** TIMER_COUNTER_2 ************** |
; TIMSK - Timer/Counter Interrupt Mask register |
.equ TOIE2 = 6 ; Timer/Counter2 Overflow Interrupt Enable |
.equ OCIE2 = 7 ; Timer/Counter2 Output Compare Match Interrupt Enable |
; TIFR - Timer/Counter Interrupt Flag Register |
.equ TOV2 = 6 ; Timer/Counter2 Overflow Flag |
.equ OCF2 = 7 ; Output Compare Flag 2 |
; TCCR2 - Timer/Counter2 Control Register |
.equ CS20 = 0 ; Clock Select bit 0 |
.equ CS21 = 1 ; Clock Select bit 1 |
.equ CS22 = 2 ; Clock Select bit 2 |
.equ CTC2 = 3 ; Clear Timer/Counter2 on Compare Match |
.equ COM20 = 4 ; Compare Output Mode bit 0 |
.equ COM21 = 5 ; Compare Output Mode bit 1 |
.equ PWM2 = 6 ; Pulse Width Modulator Enable |
.equ FOC2 = 7 ; Force Output Compare |
; TCNT2 - Timer/Counter2 |
.equ TCNT2_0 = 0 ; Timer/Counter 2 bit 0 |
.equ TCNT2_1 = 1 ; Timer/Counter 2 bit 1 |
.equ TCNT2_2 = 2 ; Timer/Counter 2 bit 2 |
.equ TCNT2_3 = 3 ; Timer/Counter 2 bit 3 |
.equ TCNT2_4 = 4 ; Timer/Counter 2 bit 4 |
.equ TCNT2_5 = 5 ; Timer/Counter 2 bit 5 |
.equ TCNT2_6 = 6 ; Timer/Counter 2 bit 6 |
.equ TCNT2_7 = 7 ; Timer/Counter 2 bit 7 |
; OCR2 - Timer/Counter2 Output Compare Register |
.equ OCR2_0 = 0 ; Timer/Counter2 Output Compare Register Bit 0 |
.equ OCR2_1 = 1 ; Timer/Counter2 Output Compare Register Bit 1 |
.equ OCR2_2 = 2 ; Timer/Counter2 Output Compare Register Bit 2 |
.equ OCR2_3 = 3 ; Timer/Counter2 Output Compare Register Bit 3 |
.equ OCR2_4 = 4 ; Timer/Counter2 Output Compare Register Bit 4 |
.equ OCR2_5 = 5 ; Timer/Counter2 Output Compare Register Bit 5 |
.equ OCR2_6 = 6 ; Timer/Counter2 Output Compare Register Bit 6 |
.equ OCR2_7 = 7 ; Timer/Counter2 Output Compare Register Bit 7 |
; ASSR - Asynchronous Status Register |
.equ TCR2UB = 0 ; Timer/counter Control Register2 Update Busy |
.equ OCR2UB = 1 ; Output Compare Register2 Update Busy |
.equ TCN2UB = 2 ; Timer/Counter2 Update Busy |
.equ AS2 = 3 ; Asynchronous Timer/counter2 |
; ***** LOCKSBITS ******************************************************** |
.equ LB1 = 0 ; Lock bit |
.equ LB2 = 1 ; Lock bit |
.equ BLB01 = 2 ; Boot Lock bit |
.equ BLB02 = 3 ; Boot Lock bit |
.equ BLB11 = 4 ; Boot lock bit |
.equ BLB12 = 5 ; Boot lock bit |
; ***** FUSES ************************************************************ |
; LOW fuse bits |
.equ CKSEL0 = 0 ; Select Clock Source |
.equ CKSEL1 = 1 ; Select Clock Source |
.equ CKSEL2 = 2 ; Select Clock Source |
.equ CKSEL3 = 3 ; Select Clock Source |
.equ BODEN = 6 ; Brown out detector enable |
.equ BODLEVEL = 7 ; Brown out detector trigger level |
; HIGH fuse bits |
.equ BOOTRST = 0 ; Select Reset Vector |
.equ BOOTSZ0 = 1 ; Select Boot Size |
.equ BOOTSZ1 = 2 ; Select Boot Size |
.equ EESAVE = 3 ; EEPROM memory is preserved through chip erase |
.equ SPIEN = 5 ; Enable Serial programming and Data Downloading |
.equ JTAGEN = 6 ; Enable JTAG |
.equ OCDEN = 7 ; Enable OCD |
; ***** CPU REGISTER DEFINITIONS ***************************************** |
.def XH = r27 |
.def XL = r26 |
.def YH = r29 |
.def YL = r28 |
.def ZH = r31 |
.def ZL = r30 |
; ***** DATA MEMORY DECLARATIONS ***************************************** |
.equ FLASHEND = 0x3fff ; Note: Word address |
.equ IOEND = 0x003f |
.equ SRAM_START = 0x0060 |
.equ SRAM_SIZE = 2048 |
.equ RAMEND = 0x085f |
.equ XRAMEND = 0x0000 |
.equ E2END = 0x03ff |
.equ EEPROMEND = 0x03ff |
.equ EEADRBITS = 10 |
#pragma AVRPART MEMORY PROG_FLASH 32768 |
#pragma AVRPART MEMORY EEPROM 1024 |
#pragma AVRPART MEMORY INT_SRAM SIZE 2048 |
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60 |
; ***** BOOTLOADER DECLARATIONS ****************************************** |
.equ NRWW_START_ADDR = 0x0 |
.equ NRWW_STOP_ADDR = 0x3fff |
.equ PAGESIZE = 64 |
.equ FIRSTBOOTSTART = 0x3f00 |
.equ SECONDBOOTSTART = 0x3e00 |
.equ THIRDBOOTSTART = 0x3c00 |
.equ FOURTHBOOTSTART = 0x3800 |
.equ SMALLBOOTSTART = FIRSTBOOTSTART |
.equ LARGEBOOTSTART = FOURTHBOOTSTART |
; ***** INTERRUPT VECTORS ************************************************ |
.equ INT0addr = 0x0002 ; External Interrupt Request 0 |
.equ INT1addr = 0x0004 ; External Interrupt Request 1 |
.equ INT2addr = 0x0006 ; External Interrupt Request 2 |
.equ OC2addr = 0x0008 ; Timer/Counter2 Compare Match |
.equ OVF2addr = 0x000a ; Timer/Counter2 Overflow |
.equ ICP1addr = 0x000c ; Timer/Counter1 Capture Event |
.equ OC1Aaddr = 0x000e ; Timer/Counter1 Compare Match A |
.equ OC1Baddr = 0x0010 ; Timer/Counter1 Compare Match B |
.equ OVF1addr = 0x0012 ; Timer/Counter1 Overflow |
.equ OC0addr = 0x0014 ; Timer/Counter0 Compare Match |
.equ OVF0addr = 0x0016 ; Timer/Counter0 Overflow |
.equ SPIaddr = 0x0018 ; Serial Transfer Complete |
.equ URXCaddr = 0x001a ; USART, Rx Complete |
.equ UDREaddr = 0x001c ; USART Data Register Empty |
.equ UTXCaddr = 0x001e ; USART, Tx Complete |
.equ ADCCaddr = 0x0020 ; ADC Conversion Complete |
.equ ERDYaddr = 0x0022 ; EEPROM Ready |
.equ ACIaddr = 0x0024 ; Analog Comparator |
.equ TWIaddr = 0x0026 ; 2-wire Serial Interface |
.equ SPMRaddr = 0x0028 ; Store Program Memory Ready |
.equ INT_VECTORS_SIZE = 42 ; size in words |
#endif /* _M323DEF_INC_ */ |
; ***** END OF FILE ****************************************************** |
/contrib/toolchain/avra/includes/m3250def.inc |
---|
0,0 → 1,1167 |
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** |
;***** Created: 2005-01-11 10:31 ******* Source: ATmega3250.xml ********** |
;************************************************************************* |
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y |
;* |
;* Number : AVR000 |
;* File Name : "m3250def.inc" |
;* Title : Register/Bit Definitions for the ATmega3250 |
;* Date : 2005-01-11 |
;* Version : 2.14 |
;* Support E-mail : avr@atmel.com |
;* Target MCU : ATmega3250 |
;* |
;* DESCRIPTION |
;* When including this file in the assembly program file, all I/O register |
;* names and I/O register bit names appearing in the data book can be used. |
;* In addition, the six registers forming the three data pointers X, Y and |
;* Z have been assigned names XL - ZH. Highest RAM address for Internal |
;* SRAM is also defined |
;* |
;* The Register names are represented by their hexadecimal address. |
;* |
;* The Register Bit names are represented by their bit number (0-7). |
;* |
;* Please observe the difference in using the bit names with instructions |
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" |
;* (skip if bit in register set/cleared). The following example illustrates |
;* this: |
;* |
;* in r16,PORTB ;read PORTB latch |
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) |
;* out PORTB,r16 ;output to PORTB |
;* |
;* in r16,TIFR ;read the Timer Interrupt Flag Register |
;* sbrc r16,TOV0 ;test the overflow flag (use bit#) |
;* rjmp TOV0_is_set ;jump if set |
;* ... ;otherwise do something else |
;************************************************************************* |
#ifndef _M3250DEF_INC_ |
#define _M3250DEF_INC_ |
#pragma partinc 0 |
; ***** SPECIFY DEVICE *************************************************** |
.device ATmega3250 |
#pragma AVRPART ADMIN PART_NAME ATmega3250 |
.equ SIGNATURE_000 = 0x1e |
.equ SIGNATURE_001 = 0x95 |
.equ SIGNATURE_002 = 0x06 |
#pragma AVRPART CORE CORE_VERSION V2E |
; ***** I/O REGISTER DEFINITIONS ***************************************** |
; NOTE: |
; Definitions marked "MEMORY MAPPED"are extended I/O ports |
; and cannot be used with IN/OUT instructions |
.equ PORTJ = 0xdd ; MEMORY MAPPED |
.equ DDRJ = 0xdc ; MEMORY MAPPED |
.equ PINJ = 0xdb ; MEMORY MAPPED |
.equ PORTH = 0xda ; MEMORY MAPPED |
.equ DDRH = 0xd9 ; MEMORY MAPPED |
.equ PINH = 0xd8 ; MEMORY MAPPED |
.equ UDR = 0xc6 ; MEMORY MAPPED |
.equ UBRRH = 0xc5 ; MEMORY MAPPED |
.equ UBRRL = 0xc4 ; MEMORY MAPPED |
.equ UCSRC = 0xc2 ; MEMORY MAPPED |
.equ UCSRB = 0xc1 ; MEMORY MAPPED |
.equ UCSRA = 0xc0 ; MEMORY MAPPED |
.equ USIDR = 0xba ; MEMORY MAPPED |
.equ USISR = 0xb9 ; MEMORY MAPPED |
.equ USICR = 0xb8 ; MEMORY MAPPED |
.equ ASSR = 0xb6 ; MEMORY MAPPED |
.equ OCR2A = 0xb3 ; MEMORY MAPPED |
.equ TCNT2 = 0xb2 ; MEMORY MAPPED |
.equ TCCR2A = 0xb0 ; MEMORY MAPPED |
.equ OCR1BH = 0x8b ; MEMORY MAPPED |
.equ OCR1BL = 0x8a ; MEMORY MAPPED |
.equ OCR1AH = 0x89 ; MEMORY MAPPED |
.equ OCR1AL = 0x88 ; MEMORY MAPPED |
.equ ICR1H = 0x87 ; MEMORY MAPPED |
.equ ICR1L = 0x86 ; MEMORY MAPPED |
.equ TCNT1H = 0x85 ; MEMORY MAPPED |
.equ TCNT1L = 0x84 ; MEMORY MAPPED |
.equ TCCR1C = 0x82 ; MEMORY MAPPED |
.equ TCCR1B = 0x81 ; MEMORY MAPPED |
.equ TCCR1A = 0x80 ; MEMORY MAPPED |
.equ DIDR1 = 0x7f ; MEMORY MAPPED |
.equ DIDR0 = 0x7e ; MEMORY MAPPED |
.equ ADMUX = 0x7c ; MEMORY MAPPED |
.equ ADCSRB = 0x7b ; MEMORY MAPPED |
.equ ADCSRA = 0x7a ; MEMORY MAPPED |
.equ ADCH = 0x79 ; MEMORY MAPPED |
.equ ADCL = 0x78 ; MEMORY MAPPED |
.equ PCMSK3 = 0x73 ; MEMORY MAPPED |
.equ TIMSK2 = 0x70 ; MEMORY MAPPED |
.equ TIMSK1 = 0x6f ; MEMORY MAPPED |
.equ TIMSK0 = 0x6e ; MEMORY MAPPED |
.equ PCMSK2 = 0x6d ; MEMORY MAPPED |
.equ PCMSK1 = 0x6c ; MEMORY MAPPED |
.equ PCMSK0 = 0x6b ; MEMORY MAPPED |
.equ EICRA = 0x69 ; MEMORY MAPPED |
.equ OSCCAL = 0x66 ; MEMORY MAPPED |
.equ PRR = 0x64 ; MEMORY MAPPED |
.equ CLKPR = 0x61 ; MEMORY MAPPED |
.equ WDTCR = 0x60 ; MEMORY MAPPED |
.equ SREG = 0x3f |
.equ SPH = 0x3e |
.equ SPL = 0x3d |
.equ SPMCSR = 0x37 |
.equ MCUCR = 0x35 |
.equ MCUSR = 0x34 |
.equ SMCR = 0x33 |
.equ OCDR = 0x31 |
.equ ACSR = 0x30 |
.equ SPDR = 0x2e |
.equ SPSR = 0x2d |
.equ SPCR = 0x2c |
.equ GPIOR2 = 0x2b |
.equ GPIOR1 = 0x2a |
.equ OCR0A = 0x27 |
.equ TCNT0 = 0x26 |
.equ TCCR0A = 0x24 |
.equ GTCCR = 0x23 |
.equ EEARH = 0x22 |
.equ EEARL = 0x21 |
.equ EEDR = 0x20 |
.equ EECR = 0x1f |
.equ GPIOR0 = 0x1e |
.equ EIMSK = 0x1d |
.equ EIFR = 0x1c |
.equ TIFR2 = 0x17 |
.equ TIFR1 = 0x16 |
.equ TIFR0 = 0x15 |
.equ PORTG = 0x14 |
.equ DDRG = 0x13 |
.equ PING = 0x12 |
.equ PORTF = 0x11 |
.equ DDRF = 0x10 |
.equ PINF = 0x0f |
.equ PORTE = 0x0e |
.equ DDRE = 0x0d |
.equ PINE = 0x0c |
.equ PORTD = 0x0b |
.equ DDRD = 0x0a |
.equ PIND = 0x09 |
.equ PORTC = 0x08 |
.equ DDRC = 0x07 |
.equ PINC = 0x06 |
.equ PORTB = 0x05 |
.equ DDRB = 0x04 |
.equ PINB = 0x03 |
.equ PORTA = 0x02 |
.equ DDRA = 0x01 |
.equ PINA = 0x00 |
; ***** BIT DEFINITIONS ************************************************** |
; ***** TIMER_COUNTER_0 ************** |
; TCCR0A - Timer/Counter0 Control Register |
.equ CS00 = 0 ; Clock Select 1 |
.equ CS01 = 1 ; Clock Select 1 |
.equ CS02 = 2 ; Clock Select 2 |
.equ WGM01 = 3 ; Waveform Generation Mode 1 |
.equ COM0A0 = 4 ; Compare match Output Mode 0 |
.equ COM0A1 = 5 ; Compare Match Output Mode 1 |
.equ WGM00 = 6 ; Waveform Generation Mode 0 |
.equ FOC0A = 7 ; Force Output Compare |
; TCNT0 - Timer/Counter0 |
.equ TCNT0_0 = 0 ; |
.equ TCNT0_1 = 1 ; |
.equ TCNT0_2 = 2 ; |
.equ TCNT0_3 = 3 ; |
.equ TCNT0_4 = 4 ; |
.equ TCNT0_5 = 5 ; |
.equ TCNT0_6 = 6 ; |
.equ TCNT0_7 = 7 ; |
; OCR0A - Timer/Counter0 Output Compare Register |
.equ OCR0A0 = 0 ; |
.equ OCR0A1 = 1 ; |
.equ OCR0A2 = 2 ; |
.equ OCR0A3 = 3 ; |
.equ OCR0A4 = 4 ; |
.equ OCR0A5 = 5 ; |
.equ OCR0A6 = 6 ; |
.equ OCR0A7 = 7 ; |
; TIMSK0 - Timer/Counter0 Interrupt Mask Register |
.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable |
.equ OCIE0A = 1 ; Timer/Counter0 Output Compare Match Interrupt Enable |
; TIFR0 - Timer/Counter0 Interrupt Flag register |
.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag |
.equ OCF0A = 1 ; Timer/Counter0 Output Compare Flag 0 |
; GTCCR - General Timer/Control Register |
.equ PSR310 = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0 |
.equ PSR10 = PSR310 ; For compatibility |
.equ PSR0 = PSR310 ; For compatibility |
.equ PSR1 = PSR310 ; For compatibility |
.equ PSR3 = PSR310 ; For compatibility |
.equ TSM = 7 ; Timer/Counter Synchronization Mode |
; ***** TIMER_COUNTER_1 ************** |
; TIMSK1 - Timer/Counter1 Interrupt Mask Register |
.equ TOIE1 = 0 ; Timer/Counter1 Overflow Interrupt Enable |
.equ OCIE1A = 1 ; Timer/Counter1 Output Compare A Match Interrupt Enable |
.equ OCIE1B = 2 ; Timer/Counter1 Output Compare B Match Interrupt Enable |
.equ ICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable |
; TIFR1 - Timer/Counter1 Interrupt Flag register |
.equ TOV1 = 0 ; Timer/Counter1 Overflow Flag |
.equ OCF1A = 1 ; Output Compare Flag 1A |
.equ OCF1B = 2 ; Output Compare Flag 1B |
.equ ICF1 = 5 ; Input Capture Flag 1 |
; TCCR1A - Timer/Counter1 Control Register A |
.equ WGM10 = 0 ; Waveform Generation Mode |
.equ WGM11 = 1 ; Waveform Generation Mode |
.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0 |
.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1 |
.equ COM1A0 = 6 ; Compare Output Mode 1A, bit 0 |
.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1 |
; TCCR1B - Timer/Counter1 Control Register B |
.equ CS10 = 0 ; Prescaler source of Timer/Counter 1 |
.equ CS11 = 1 ; Prescaler source of Timer/Counter 1 |
.equ CS12 = 2 ; Prescaler source of Timer/Counter 1 |
.equ WGM12 = 3 ; Waveform Generation Mode |
.equ WGM13 = 4 ; Waveform Generation Mode |
.equ ICES1 = 6 ; Input Capture 1 Edge Select |
.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler |
; TCCR1C - Timer/Counter 1 Control Register C |
.equ FOC1B = 6 ; Force Output Compare 1B |
.equ FOC1A = 7 ; Force Output Compare 1A |
; ***** TIMER_COUNTER_2 ************** |
; TIMSK2 - Timer/Counter2 Interrupt Mask register |
.equ TOIE2 = 0 ; Timer/Counter2 Overflow Interrupt Enable |
.equ OCIE2A = 1 ; Timer/Counter2 Output Compare Match Interrupt Enable |
; TIFR2 - Timer/Counter2 Interrupt Flag Register |
.equ TOV2 = 0 ; Timer/Counter2 Overflow Flag |
.equ OCF2A = 1 ; Timer/Counter2 Output Compare Flag 2 |
; TCCR2A - Timer/Counter2 Control Register |
.equ CS20 = 0 ; Clock Select bit 0 |
.equ CS21 = 1 ; Clock Select bit 1 |
.equ CS22 = 2 ; Clock Select bit 2 |
.equ WGM21 = 3 ; Waveform Generation Mode |
.equ COM2A0 = 4 ; Compare Output Mode bit 0 |
.equ COM2A1 = 5 ; Compare Output Mode bit 1 |
.equ WGM20 = 6 ; Waveform Generation Mode |
.equ FOC2A = 7 ; Force Output Compare A |
; TCNT2 - Timer/Counter2 |
.equ TCNT2_0 = 0 ; Timer/Counter 2 bit 0 |
.equ TCNT2_1 = 1 ; Timer/Counter 2 bit 1 |
.equ TCNT2_2 = 2 ; Timer/Counter 2 bit 2 |
.equ TCNT2_3 = 3 ; Timer/Counter 2 bit 3 |
.equ TCNT2_4 = 4 ; Timer/Counter 2 bit 4 |
.equ TCNT2_5 = 5 ; Timer/Counter 2 bit 5 |
.equ TCNT2_6 = 6 ; Timer/Counter 2 bit 6 |
.equ TCNT2_7 = 7 ; Timer/Counter 2 bit 7 |
; OCR2A - Timer/Counter2 Output Compare Register |
.equ OCR2A0 = 0 ; Timer/Counter2 Output Compare Register Bit 0 |
.equ OCR2A1 = 1 ; Timer/Counter2 Output Compare Register Bit 1 |
.equ OCR2A2 = 2 ; Timer/Counter2 Output Compare Register Bit 2 |
.equ OCR2A3 = 3 ; Timer/Counter2 Output Compare Register Bit 3 |
.equ OCR2A4 = 4 ; Timer/Counter2 Output Compare Register Bit 4 |
.equ OCR2A5 = 5 ; Timer/Counter2 Output Compare Register Bit 5 |
.equ OCR2A6 = 6 ; Timer/Counter2 Output Compare Register Bit 6 |
.equ OCR2A7 = 7 ; Timer/Counter2 Output Compare Register Bit 7 |
; GTCCR - General Timer/Counter Control Register |
.equ PSR2 = 1 ; Prescaler Reset Timer/Counter2 |
; ASSR - Asynchronous Status Register |
.equ TCR2UB = 0 ; TCR2UB: Timer/Counter Control Register2 Update Busy |
.equ OCR2UB = 1 ; Output Compare Register2 Update Busy |
.equ TCN2UB = 2 ; TCN2UB: Timer/Counter2 Update Busy |
.equ AS2 = 3 ; AS2: Asynchronous Timer/Counter2 |
.equ EXCLK = 4 ; Enable External Clock Interrupt |
; ***** WATCHDOG ********************* |
; WDTCR - Watchdog Timer Control Register |
.equ WDTCSR = WDTCR ; For compatibility |
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 |
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 |
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 |
.equ WDE = 3 ; Watch Dog Enable |
.equ WDCE = 4 ; Watchdog Change Enable |
.equ WDTOE = WDCE ; For compatibility |
; ***** EEPROM *********************** |
; EEDR - EEPROM Data Register |
.equ EEDR0 = 0 ; EEPROM Data Register bit 0 |
.equ EEDR1 = 1 ; EEPROM Data Register bit 1 |
.equ EEDR2 = 2 ; EEPROM Data Register bit 2 |
.equ EEDR3 = 3 ; EEPROM Data Register bit 3 |
.equ EEDR4 = 4 ; EEPROM Data Register bit 4 |
.equ EEDR5 = 5 ; EEPROM Data Register bit 5 |
.equ EEDR6 = 6 ; EEPROM Data Register bit 6 |
.equ EEDR7 = 7 ; EEPROM Data Register bit 7 |
; EECR - EEPROM Control Register |
.equ EERE = 0 ; EEPROM Read Enable |
.equ EEWE = 1 ; EEPROM Write Enable |
.equ EEMWE = 2 ; EEPROM Master Write Enable |
.equ EERIE = 3 ; EEPROM Ready Interrupt Enable |
; ***** SPI ************************** |
; SPDR - SPI Data Register |
.equ SPDR0 = 0 ; SPI Data Register bit 0 |
.equ SPDR1 = 1 ; SPI Data Register bit 1 |
.equ SPDR2 = 2 ; SPI Data Register bit 2 |
.equ SPDR3 = 3 ; SPI Data Register bit 3 |
.equ SPDR4 = 4 ; SPI Data Register bit 4 |
.equ SPDR5 = 5 ; SPI Data Register bit 5 |
.equ SPDR6 = 6 ; SPI Data Register bit 6 |
.equ SPDR7 = 7 ; SPI Data Register bit 7 |
; SPSR - SPI Status Register |
.equ SPI2X = 0 ; Double SPI Speed Bit |
.equ WCOL = 6 ; Write Collision Flag |
.equ SPIF = 7 ; SPI Interrupt Flag |
; SPCR - SPI Control Register |
.equ SPR0 = 0 ; SPI Clock Rate Select 0 |
.equ SPR1 = 1 ; SPI Clock Rate Select 1 |
.equ CPHA = 2 ; Clock Phase |
.equ CPOL = 3 ; Clock polarity |
.equ MSTR = 4 ; Master/Slave Select |
.equ DORD = 5 ; Data Order |
.equ SPE = 6 ; SPI Enable |
.equ SPIE = 7 ; SPI Interrupt Enable |
; ***** PORTA ************************ |
; PORTA - Port A Data Register |
.equ PORTA0 = 0 ; Port A Data Register bit 0 |
.equ PA0 = 0 ; For compatibility |
.equ PORTA1 = 1 ; Port A Data Register bit 1 |
.equ PA1 = 1 ; For compatibility |
.equ PORTA2 = 2 ; Port A Data Register bit 2 |
.equ PA2 = 2 ; For compatibility |
.equ PORTA3 = 3 ; Port A Data Register bit 3 |
.equ PA3 = 3 ; For compatibility |
.equ PORTA4 = 4 ; Port A Data Register bit 4 |
.equ PA4 = 4 ; For compatibility |
.equ PORTA5 = 5 ; Port A Data Register bit 5 |
.equ PA5 = 5 ; For compatibility |
.equ PORTA6 = 6 ; Port A Data Register bit 6 |
.equ PA6 = 6 ; For compatibility |
.equ PORTA7 = 7 ; Port A Data Register bit 7 |
.equ PA7 = 7 ; For compatibility |
; DDRA - Port A Data Direction Register |
.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0 |
.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1 |
.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2 |
.equ DDA3 = 3 ; Data Direction Register, Port A, bit 3 |
.equ DDA4 = 4 ; Data Direction Register, Port A, bit 4 |
.equ DDA5 = 5 ; Data Direction Register, Port A, bit 5 |
.equ DDA6 = 6 ; Data Direction Register, Port A, bit 6 |
.equ DDA7 = 7 ; Data Direction Register, Port A, bit 7 |
; PINA - Port A Input Pins |
.equ PINA0 = 0 ; Input Pins, Port A bit 0 |
.equ PINA1 = 1 ; Input Pins, Port A bit 1 |
.equ PINA2 = 2 ; Input Pins, Port A bit 2 |
.equ PINA3 = 3 ; Input Pins, Port A bit 3 |
.equ PINA4 = 4 ; Input Pins, Port A bit 4 |
.equ PINA5 = 5 ; Input Pins, Port A bit 5 |
.equ PINA6 = 6 ; Input Pins, Port A bit 6 |
.equ PINA7 = 7 ; Input Pins, Port A bit 7 |
; ***** PORTB ************************ |
; PORTB - Port B Data Register |
.equ PORTB0 = 0 ; Port B Data Register bit 0 |
.equ PB0 = 0 ; For compatibility |
.equ PORTB1 = 1 ; Port B Data Register bit 1 |
.equ PB1 = 1 ; For compatibility |
.equ PORTB2 = 2 ; Port B Data Register bit 2 |
.equ PB2 = 2 ; For compatibility |
.equ PORTB3 = 3 ; Port B Data Register bit 3 |
.equ PB3 = 3 ; For compatibility |
.equ PORTB4 = 4 ; Port B Data Register bit 4 |
.equ PB4 = 4 ; For compatibility |
.equ PORTB5 = 5 ; Port B Data Register bit 5 |
.equ PB5 = 5 ; For compatibility |
.equ PORTB6 = 6 ; Port B Data Register bit 6 |
.equ PB6 = 6 ; For compatibility |
.equ PORTB7 = 7 ; Port B Data Register bit 7 |
.equ PB7 = 7 ; For compatibility |
; DDRB - Port B Data Direction Register |
.equ DDB0 = 0 ; Port B Data Direction Register bit 0 |
.equ DDB1 = 1 ; Port B Data Direction Register bit 1 |
.equ DDB2 = 2 ; Port B Data Direction Register bit 2 |
.equ DDB3 = 3 ; Port B Data Direction Register bit 3 |
.equ DDB4 = 4 ; Port B Data Direction Register bit 4 |
.equ DDB5 = 5 ; Port B Data Direction Register bit 5 |
.equ DDB6 = 6 ; Port B Data Direction Register bit 6 |
.equ DDB7 = 7 ; Port B Data Direction Register bit 7 |
; PINB - Port B Input Pins |
.equ PINB0 = 0 ; Port B Input Pins bit 0 |
.equ PINB1 = 1 ; Port B Input Pins bit 1 |
.equ PINB2 = 2 ; Port B Input Pins bit 2 |
.equ PINB3 = 3 ; Port B Input Pins bit 3 |
.equ PINB4 = 4 ; Port B Input Pins bit 4 |
.equ PINB5 = 5 ; Port B Input Pins bit 5 |
.equ PINB6 = 6 ; Port B Input Pins bit 6 |
.equ PINB7 = 7 ; Port B Input Pins bit 7 |
; ***** PORTC ************************ |
; PORTC - Port C Data Register |
.equ PORTC0 = 0 ; Port C Data Register bit 0 |
.equ PC0 = 0 ; For compatibility |
.equ PORTC1 = 1 ; Port C Data Register bit 1 |
.equ PC1 = 1 ; For compatibility |
.equ PORTC2 = 2 ; Port C Data Register bit 2 |
.equ PC2 = 2 ; For compatibility |
.equ PORTC3 = 3 ; Port C Data Register bit 3 |
.equ PC3 = 3 ; For compatibility |
.equ PORTC4 = 4 ; Port C Data Register bit 4 |
.equ PC4 = 4 ; For compatibility |
.equ PORTC5 = 5 ; Port C Data Register bit 5 |
.equ PC5 = 5 ; For compatibility |
.equ PORTC6 = 6 ; Port C Data Register bit 6 |
.equ PC6 = 6 ; For compatibility |
.equ PORTC7 = 7 ; Port C Data Register bit 7 |
.equ PC7 = 7 ; For compatibility |
; DDRC - Port C Data Direction Register |
.equ DDC0 = 0 ; Port C Data Direction Register bit 0 |
.equ DDC1 = 1 ; Port C Data Direction Register bit 1 |
.equ DDC2 = 2 ; Port C Data Direction Register bit 2 |
.equ DDC3 = 3 ; Port C Data Direction Register bit 3 |
.equ DDC4 = 4 ; Port C Data Direction Register bit 4 |
.equ DDC5 = 5 ; Port C Data Direction Register bit 5 |
.equ DDC6 = 6 ; Port C Data Direction Register bit 6 |
.equ DDC7 = 7 ; Port C Data Direction Register bit 7 |
; PINC - Port C Input Pins |
.equ PINC0 = 0 ; Port C Input Pins bit 0 |
.equ PINC1 = 1 ; Port C Input Pins bit 1 |
.equ PINC2 = 2 ; Port C Input Pins bit 2 |
.equ PINC3 = 3 ; Port C Input Pins bit 3 |
.equ PINC4 = 4 ; Port C Input Pins bit 4 |
.equ PINC5 = 5 ; Port C Input Pins bit 5 |
.equ PINC6 = 6 ; Port C Input Pins bit 6 |
.equ PINC7 = 7 ; Port C Input Pins bit 7 |
; ***** PORTD ************************ |
; PORTD - Port D Data Register |
.equ PORTD0 = 0 ; Port D Data Register bit 0 |
.equ PD0 = 0 ; For compatibility |
.equ PORTD1 = 1 ; Port D Data Register bit 1 |
.equ PD1 = 1 ; For compatibility |
.equ PORTD2 = 2 ; Port D Data Register bit 2 |
.equ PD2 = 2 ; For compatibility |
.equ PORTD3 = 3 ; Port D Data Register bit 3 |
.equ PD3 = 3 ; For compatibility |
.equ PORTD4 = 4 ; Port D Data Register bit 4 |
.equ PD4 = 4 ; For compatibility |
.equ PORTD5 = 5 ; Port D Data Register bit 5 |
.equ PD5 = 5 ; For compatibility |
.equ PORTD6 = 6 ; Port D Data Register bit 6 |
.equ PD6 = 6 ; For compatibility |
.equ PORTD7 = 7 ; Port D Data Register bit 7 |
.equ PD7 = 7 ; For compatibility |
; DDRD - Port D Data Direction Register |
.equ DDD0 = 0 ; Port D Data Direction Register bit 0 |
.equ DDD1 = 1 ; Port D Data Direction Register bit 1 |
.equ DDD2 = 2 ; Port D Data Direction Register bit 2 |
.equ DDD3 = 3 ; Port D Data Direction Register bit 3 |
.equ DDD4 = 4 ; Port D Data Direction Register bit 4 |
.equ DDD5 = 5 ; Port D Data Direction Register bit 5 |
.equ DDD6 = 6 ; Port D Data Direction Register bit 6 |
.equ DDD7 = 7 ; Port D Data Direction Register bit 7 |
; PIND - Port D Input Pins |
.equ PIND0 = 0 ; Port D Input Pins bit 0 |
.equ PIND1 = 1 ; Port D Input Pins bit 1 |
.equ PIND2 = 2 ; Port D Input Pins bit 2 |
.equ PIND3 = 3 ; Port D Input Pins bit 3 |
.equ PIND4 = 4 ; Port D Input Pins bit 4 |
.equ PIND5 = 5 ; Port D Input Pins bit 5 |
.equ PIND6 = 6 ; Port D Input Pins bit 6 |
.equ PIND7 = 7 ; Port D Input Pins bit 7 |
; ***** ANALOG_COMPARATOR ************ |
; ADCSRB - ADC Control and Status Register B |
.equ ACME = 6 ; Analog Comparator Multiplexer Enable |
; ACSR - Analog Comparator Control And Status Register |
.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 |
.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 |
.equ ACIC = 2 ; Analog Comparator Input Capture Enable |
.equ ACIE = 3 ; Analog Comparator Interrupt Enable |
.equ ACI = 4 ; Analog Comparator Interrupt Flag |
.equ ACO = 5 ; Analog Compare Output |
.equ ACBG = 6 ; Analog Comparator Bandgap Select |
.equ ACD = 7 ; Analog Comparator Disable |
; DIDR1 - Digital Input Disable Register 1 |
.equ AIN0D = 0 ; AIN0 Digital Input Disable |
.equ AIN1D = 1 ; AIN1 Digital Input Disable |
; ***** PORTE ************************ |
; PORTE - Data Register, Port E |
.equ PORTE0 = 0 ; |
.equ PE0 = 0 ; For compatibility |
.equ PORTE1 = 1 ; |
.equ PE1 = 1 ; For compatibility |
.equ PORTE2 = 2 ; |
.equ PE2 = 2 ; For compatibility |
.equ PORTE3 = 3 ; |
.equ PE3 = 3 ; For compatibility |
.equ PORTE4 = 4 ; |
.equ PE4 = 4 ; For compatibility |
.equ PORTE5 = 5 ; |
.equ PE5 = 5 ; For compatibility |
.equ PORTE6 = 6 ; |
.equ PE6 = 6 ; For compatibility |
.equ PORTE7 = 7 ; |
.equ PE7 = 7 ; For compatibility |
; DDRE - Data Direction Register, Port E |
.equ DDE0 = 0 ; |
.equ DDE1 = 1 ; |
.equ DDE2 = 2 ; |
.equ DDE3 = 3 ; |
.equ DDE4 = 4 ; |
.equ DDE5 = 5 ; |
.equ DDE6 = 6 ; |
.equ DDE7 = 7 ; |
; PINE - Input Pins, Port E |
.equ PINE0 = 0 ; |
.equ PINE1 = 1 ; |
.equ PINE2 = 2 ; |
.equ PINE3 = 3 ; |
.equ PINE4 = 4 ; |
.equ PINE5 = 5 ; |
.equ PINE6 = 6 ; |
.equ PINE7 = 7 ; |
; ***** PORTF ************************ |
; PORTF - Data Register, Port F |
.equ PORTF0 = 0 ; |
.equ PF0 = 0 ; For compatibility |
.equ PORTF1 = 1 ; |
.equ PF1 = 1 ; For compatibility |
.equ PORTF2 = 2 ; |
.equ PF2 = 2 ; For compatibility |
.equ PORTF3 = 3 ; |
.equ PF3 = 3 ; For compatibility |
.equ PORTF4 = 4 ; |
.equ PF4 = 4 ; For compatibility |
.equ PORTF5 = 5 ; |
.equ PF5 = 5 ; For compatibility |
.equ PORTF6 = 6 ; |
.equ PF6 = 6 ; For compatibility |
.equ PORTF7 = 7 ; |
.equ PF7 = 7 ; For compatibility |
; DDRF - Data Direction Register, Port F |
.equ DDF0 = 0 ; |
.equ DDF1 = 1 ; |
.equ DDF2 = 2 ; |
.equ DDF3 = 3 ; |
.equ DDF4 = 4 ; |
.equ DDF5 = 5 ; |
.equ DDF6 = 6 ; |
.equ DDF7 = 7 ; |
; PINF - Input Pins, Port F |
.equ PINF0 = 0 ; |
.equ PINF1 = 1 ; |
.equ PINF2 = 2 ; |
.equ PINF3 = 3 ; |
.equ PINF4 = 4 ; |
.equ PINF5 = 5 ; |
.equ PINF6 = 6 ; |
.equ PINF7 = 7 ; |
; ***** PORTG ************************ |
; PORTG - Port G Data Register |
.equ PORTG0 = 0 ; |
.equ PG0 = 0 ; For compatibility |
.equ PORTG1 = 1 ; |
.equ PG1 = 1 ; For compatibility |
.equ PORTG2 = 2 ; |
.equ PG2 = 2 ; For compatibility |
.equ PORTG3 = 3 ; |
.equ PG3 = 3 ; For compatibility |
.equ PORTG4 = 4 ; |
.equ PG4 = 4 ; For compatibility |
; DDRG - Port G Data Direction Register |
.equ DDG0 = 0 ; |
.equ DDG1 = 1 ; |
.equ DDG2 = 2 ; |
.equ DDG3 = 3 ; |
.equ DDG4 = 4 ; |
; PING - Port G Input Pins |
.equ PING0 = 0 ; |
.equ PING1 = 1 ; |
.equ PING2 = 2 ; |
.equ PING3 = 3 ; |
.equ PING4 = 4 ; |
.equ PING5 = 5 ; |
; ***** JTAG ************************* |
; OCDR - On-Chip Debug Related Register in I/O Memory |
.equ OCDR0 = 0 ; On-Chip Debug Register Bit 0 |
.equ OCDR1 = 1 ; On-Chip Debug Register Bit 1 |
.equ OCDR2 = 2 ; On-Chip Debug Register Bit 2 |
.equ OCDR3 = 3 ; On-Chip Debug Register Bit 3 |
.equ OCDR4 = 4 ; On-Chip Debug Register Bit 4 |
.equ OCDR5 = 5 ; On-Chip Debug Register Bit 5 |
.equ OCDR6 = 6 ; On-Chip Debug Register Bit 6 |
.equ OCDR7 = 7 ; On-Chip Debug Register Bit 7 |
.equ IDRD = OCDR7 ; For compatibility |
; MCUCR - MCU Control Register |
.equ JTD = 7 ; JTAG Interface Disable |
; MCUSR - MCU Status Register |
.equ JTRF = 4 ; JTAG Reset Flag |
; ***** EXTERNAL_INTERRUPT *********** |
; EICRA - External Interrupt Control Register A |
.equ ISC00 = 0 ; External Interrupt Sense Control 0 Bit 0 |
.equ ISC01 = 1 ; External Interrupt Sense Control 0 Bit 1 |
; EIMSK - External Interrupt Mask Register |
.equ INT0 = 0 ; External Interrupt Request 0 Enable |
.equ PCIE0 = 4 ; Pin Change Interrupt Enable 0 |
.equ PCIE1 = 5 ; Pin Change Interrupt Enable 1 |
.equ PCIE2 = 6 ; Pin Change Interrupt Enable 2 |
.equ PCIE3 = 7 ; Pin Change Interrupt Enable 3 |
; EIFR - External Interrupt Flag Register |
.equ INTF0 = 0 ; External Interrupt Flag 0 |
.equ PCIF0 = 4 ; Pin Change Interrupt Flag 0 |
.equ PCIF1 = 5 ; Pin Change Interrupt Flag 1 |
.equ PCIF2 = 6 ; Pin Change Interrupt Flag 2 |
.equ PCIF3 = 7 ; Pin Change Interrupt Flag 3 |
; PCMSK3 - Pin Change Mask Register 3 |
.equ PCINT24 = 0 ; Pin Change Enable Mask 24 |
.equ PCINT25 = 1 ; Pin Change Enable Mask 25 |
.equ PCINT26 = 2 ; Pin Change Enable Mask 26 |
.equ PCINT27 = 3 ; Pin Change Enable Mask 27 |
.equ PCINT28 = 4 ; Pin Change Enable Mask 28 |
.equ PCINT29 = 5 ; Pin Change Enable Mask 29 |
.equ PCINT30 = 6 ; Pin Change Enable Mask 30 |
; PCMSK2 - Pin Change Mask Register 2 |
.equ PCINT16 = 0 ; Pin Change Enable Mask 16 |
.equ PCINT17 = 1 ; Pin Change Enable Mask 17 |
.equ PCINT18 = 2 ; Pin Change Enable Mask 18 |
.equ PCINT19 = 3 ; Pin Change Enable Mask 19 |
.equ PCINT20 = 4 ; Pin Change Enable Mask 20 |
.equ PCINT21 = 5 ; Pin Change Enable Mask 21 |
.equ PCINT22 = 6 ; Pin Change Enable Mask 22 |
.equ PCINT23 = 7 ; Pin Change Enable Mask 23 |
; PCMSK1 - Pin Change Mask Register 1 |
.equ PCINT8 = 0 ; Pin Change Enable Mask 8 |
.equ PCINT9 = 1 ; Pin Change Enable Mask 9 |
.equ PCINT10 = 2 ; Pin Change Enable Mask 10 |
.equ PCINT11 = 3 ; Pin Change Enable Mask 11 |
.equ PCINT12 = 4 ; Pin Change Enable Mask 12 |
.equ PCINT13 = 5 ; Pin Change Enable Mask 13 |
.equ PCINT14 = 6 ; Pin Change Enable Mask 14 |
.equ PCINT15 = 7 ; Pin Change Enable Mask 15 |
; PCMSK0 - Pin Change Mask Register 0 |
.equ PCINT0 = 0 ; Pin Change Enable Mask 0 |
.equ PCINT1 = 1 ; Pin Change Enable Mask 1 |
.equ PCINT2 = 2 ; Pin Change Enable Mask 2 |
.equ PCINT3 = 3 ; Pin Change Enable Mask 3 |
.equ PCINT4 = 4 ; Pin Change Enable Mask 4 |
.equ PCINT5 = 5 ; Pin Change Enable Mask 5 |
.equ PCINT6 = 6 ; Pin Change Enable Mask 6 |
.equ PCINT7 = 7 ; Pin Change Enable Mask 7 |
; ***** CPU ************************** |
; SREG - Status Register |
.equ SREG_C = 0 ; Carry Flag |
.equ SREG_Z = 1 ; Zero Flag |
.equ SREG_N = 2 ; Negative Flag |
.equ SREG_V = 3 ; Two's Complement Overflow Flag |
.equ SREG_S = 4 ; Sign Bit |
.equ SREG_H = 5 ; Half Carry Flag |
.equ SREG_T = 6 ; Bit Copy Storage |
.equ SREG_I = 7 ; Global Interrupt Enable |
; MCUCR - MCU Control Register |
.equ IVCE = 0 ; Interrupt Vector Change Enable |
.equ IVSEL = 1 ; Interrupt Vector Select |
.equ PUD = 4 ; Pull-up disable |
; MCUSR - MCU Status Register |
.equ PORF = 0 ; Power-on reset flag |
.equ EXTRF = 1 ; External Reset Flag |
.equ BORF = 2 ; Brown-out Reset Flag |
.equ WDRF = 3 ; Watchdog Reset Flag |
;.equ JTRF = 4 ; JTAG Reset Flag |
; OSCCAL - Oscillator Calibration Value |
.equ CAL0 = 0 ; Oscillator Calibration Value Bit0 |
.equ CAL1 = 1 ; Oscillator Calibration Value Bit1 |
.equ CAL2 = 2 ; Oscillator Calibration Value Bit2 |
.equ CAL3 = 3 ; Oscillator Calibration Value Bit3 |
.equ CAL4 = 4 ; Oscillator Calibration Value Bit4 |
.equ CAL5 = 5 ; Oscillator Calibration Value Bit5 |
.equ CAL6 = 6 ; Oscillator Calibration Value Bit6 |
.equ CAL7 = 7 ; Oscillator Calibration Value Bit7 |
; CLKPR - Clock Prescale Register |
.equ CLKPS0 = 0 ; Clock Prescaler Select Bit 0 |
.equ CLKPS1 = 1 ; Clock Prescaler Select Bit 1 |
.equ CLKPS2 = 2 ; Clock Prescaler Select Bit 2 |
.equ CLKPS3 = 3 ; Clock Prescaler Select Bit 3 |
.equ CLKPCE = 7 ; Clock Prescaler Change Enable |
; PRR - Power Reduction Register |
.equ PRADC = 0 ; Power Reduction ADC |
.equ PRUSART0 = 1 ; Power Reduction USART |
.equ PRSPI = 2 ; Power Reduction Serial Peripheral Interface |
.equ PRTIM1 = 3 ; Power Reduction Timer/Counter1 |
.equ PRLCD = 4 ; Power Reduction LCD |
; SMCR - Sleep Mode Control Register |
.equ SE = 0 ; Sleep Enable |
.equ SM0 = 1 ; Sleep Mode Select bit 0 |
.equ SM1 = 2 ; Sleep Mode Select bit 1 |
.equ SM2 = 3 ; Sleep Mode Select bit 2 |
; GPIOR2 - General Purpose IO Register 2 |
.equ GPIOR20 = 0 ; General Purpose IO Register 2 bit 0 |
.equ GPIOR21 = 1 ; General Purpose IO Register 2 bit 1 |
.equ GPIOR22 = 2 ; General Purpose IO Register 2 bit 2 |
.equ GPIOR23 = 3 ; General Purpose IO Register 2 bit 3 |
.equ GPIOR24 = 4 ; General Purpose IO Register 2 bit 4 |
.equ GPIOR25 = 5 ; General Purpose IO Register 2 bit 5 |
.equ GPIOR26 = 6 ; General Purpose IO Register 2 bit 6 |
.equ GPIOR27 = 7 ; General Purpose IO Register 2 bit 7 |
; GPIOR1 - General Purpose IO Register 1 |
.equ GPIOR10 = 0 ; General Purpose IO Register 1 bit 0 |
.equ GPIOR11 = 1 ; General Purpose IO Register 1 bit 1 |
.equ GPIOR12 = 2 ; General Purpose IO Register 1 bit 2 |
.equ GPIOR13 = 3 ; General Purpose IO Register 1 bit 3 |
.equ GPIOR14 = 4 ; General Purpose IO Register 1 bit 4 |
.equ GPIOR15 = 5 ; General Purpose IO Register 1 bit 5 |
.equ GPIOR16 = 6 ; General Purpose IO Register 1 bit 6 |
.equ GPIOR17 = 7 ; General Purpose IO Register 1 bit 7 |
; GPIOR0 - General Purpose IO Register 0 |
.equ GPIOR00 = 0 ; General Purpose IO Register 0 bit 0 |
.equ GPIOR01 = 1 ; General Purpose IO Register 0 bit 1 |
.equ GPIOR02 = 2 ; General Purpose IO Register 0 bit 2 |
.equ GPIOR03 = 3 ; General Purpose IO Register 0 bit 3 |
.equ GPIOR04 = 4 ; General Purpose IO Register 0 bit 4 |
.equ GPIOR05 = 5 ; General Purpose IO Register 0 bit 5 |
.equ GPIOR06 = 6 ; General Purpose IO Register 0 bit 6 |
.equ GPIOR07 = 7 ; General Purpose IO Register 0 bit 7 |
; ***** USI ************************** |
; USIDR - USI Data Register |
.equ USIDR0 = 0 ; USI Data Register bit 0 |
.equ USIDR1 = 1 ; USI Data Register bit 1 |
.equ USIDR2 = 2 ; USI Data Register bit 2 |
.equ USIDR3 = 3 ; USI Data Register bit 3 |
.equ USIDR4 = 4 ; USI Data Register bit 4 |
.equ USIDR5 = 5 ; USI Data Register bit 5 |
.equ USIDR6 = 6 ; USI Data Register bit 6 |
.equ USIDR7 = 7 ; USI Data Register bit 7 |
; USISR - USI Status Register |
.equ USICNT0 = 0 ; USI Counter Value Bit 0 |
.equ USICNT1 = 1 ; USI Counter Value Bit 1 |
.equ USICNT2 = 2 ; USI Counter Value Bit 2 |
.equ USICNT3 = 3 ; USI Counter Value Bit 3 |
.equ USIDC = 4 ; Data Output Collision |
.equ USIPF = 5 ; Stop Condition Flag |
.equ USIOIF = 6 ; Counter Overflow Interrupt Flag |
.equ USISIF = 7 ; Start Condition Interrupt Flag |
; USICR - USI Control Register |
.equ USITC = 0 ; Toggle Clock Port Pin |
.equ USICLK = 1 ; Clock Strobe |
.equ USICS0 = 2 ; USI Clock Source Select Bit 0 |
.equ USICS1 = 3 ; USI Clock Source Select Bit 1 |
.equ USIWM0 = 4 ; USI Wire Mode Bit 0 |
.equ USIWM1 = 5 ; USI Wire Mode Bit 1 |
.equ USIOIE = 6 ; Counter Overflow Interrupt Enable |
.equ USISIE = 7 ; Start Condition Interrupt Enable |
; ***** AD_CONVERTER ***************** |
; ADMUX - The ADC multiplexer Selection Register |
.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits |
.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits |
.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits |
.equ MUX3 = 3 ; Analog Channel and Gain Selection Bits |
.equ MUX4 = 4 ; Analog Channel and Gain Selection Bits |
.equ ADLAR = 5 ; Left Adjust Result |
.equ REFS0 = 6 ; Reference Selection Bit 0 |
.equ REFS1 = 7 ; Reference Selection Bit 1 |
; ADCSRA - The ADC Control and Status register |
.equ ADPS0 = 0 ; ADC Prescaler Select Bits |
.equ ADPS1 = 1 ; ADC Prescaler Select Bits |
.equ ADPS2 = 2 ; ADC Prescaler Select Bits |
.equ ADIE = 3 ; ADC Interrupt Enable |
.equ ADIF = 4 ; ADC Interrupt Flag |
.equ ADATE = 5 ; ADC Auto Trigger Enable |
.equ ADSC = 6 ; ADC Start Conversion |
.equ ADEN = 7 ; ADC Enable |
; ADCH - ADC Data Register High Byte |
.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0 |
.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1 |
.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2 |
.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3 |
.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4 |
.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5 |
.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6 |
.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7 |
; ADCL - ADC Data Register Low Byte |
.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0 |
.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1 |
.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2 |
.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3 |
.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4 |
.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5 |
.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6 |
.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7 |
; ADCSRB - ADC Control and Status Register B |
.equ ADTS0 = 0 ; ADC Auto Trigger Source 0 |
.equ ADTS1 = 1 ; ADC Auto Trigger Source 1 |
.equ ADTS2 = 2 ; ADC Auto Trigger Source 2 |
; DIDR0 - Digital Input Disable Register 0 |
.equ ADC0D = 0 ; ADC0 Digital input Disable |
.equ ADC1D = 1 ; ADC1 Digital input Disable |
.equ ADC2D = 2 ; ADC2 Digital input Disable |
.equ ADC3D = 3 ; ADC3 Digital input Disable |
.equ ADC4D = 4 ; ADC4 Digital input Disable |
.equ ADC5D = 5 ; ADC5 Digital input Disable |
.equ ADC6D = 6 ; ADC6 Digital input Disable |
.equ ADC7D = 7 ; ADC7 Digital input Disable |
; ***** BOOT_LOAD ******************** |
; SPMCSR - Store Program Memory Control Register |
.equ SPMCR = SPMCSR ; For compatibility |
.equ SPMEN = 0 ; Store Program Memory Enable |
.equ PGERS = 1 ; Page Erase |
.equ PGWRT = 2 ; Page Write |
.equ BLBSET = 3 ; Boot Lock Bit Set |
.equ RWWSRE = 4 ; Read While Write section read enable |
.equ ASRE = RWWSRE ; For compatibility |
.equ RWWSB = 6 ; Read While Write Section Busy |
.equ ASB = RWWSB ; For compatibility |
.equ SPMIE = 7 ; SPM Interrupt Enable |
; ***** USART0 *********************** |
; UDR - USART I/O Data Register |
.equ UDR0 = UDR ; For compatibility |
.equ UDR00 = 0 ; USART I/O Data Register bit 0 |
.equ UDR01 = 1 ; USART I/O Data Register bit 1 |
.equ UDR02 = 2 ; USART I/O Data Register bit 2 |
.equ UDR03 = 3 ; USART I/O Data Register bit 3 |
.equ UDR04 = 4 ; USART I/O Data Register bit 4 |
.equ UDR05 = 5 ; USART I/O Data Register bit 5 |
.equ UDR06 = 6 ; USART I/O Data Register bit 6 |
.equ UDR07 = 7 ; USART I/O Data Register bit 7 |
; UCSRA - USART Control and Status Register A |
.equ UCSR0A = UCSRA ; For compatibility |
.equ USR = UCSRA ; For compatibility |
.equ MPCM = 0 ; Multi-processor Communication Mode |
.equ MPCM0 = MPCM ; For compatibility |
.equ U2X = 1 ; Double the USART Transmission Speed |
.equ U2X0 = U2X ; For compatibility |
.equ UPE = 2 ; USART Parity Error |
.equ UPE0 = UPE ; For compatibility |
.equ DOR = 3 ; Data OverRun |
.equ DOR0 = DOR ; For compatibility |
.equ FE = 4 ; Framing Error |
.equ FE0 = FE ; For compatibility |
.equ UDRE = 5 ; USART Data Register Empty |
.equ UDRE0 = UDRE ; For compatibility |
.equ TXC = 6 ; USART Transmit Complete |
.equ TXC0 = TXC ; For compatibility |
.equ RXC = 7 ; USART Receive Complete |
.equ RXC0 = RXC ; For compatibility |
; UCSRB - USART Control and Status Register B |
.equ UCSR0B = UCSRB ; For compatibility |
.equ UCR = UCSRB ; For compatibility |
.equ TXB8 = 0 ; Transmit Data Bit 8 |
.equ TXB80 = TXB8 ; For compatibility |
.equ RXB8 = 1 ; Receive Data Bit 8 |
.equ RXB80 = RXB8 ; For compatibility |
.equ UCSZ2 = 2 ; Character Size |
.equ UCSZ02 = UCSZ2 ; For compatibility |
.equ TXEN = 3 ; Transmitter Enable |
.equ TXEN0 = TXEN ; For compatibility |
.equ RXEN = 4 ; Receiver Enable |
.equ RXEN0 = RXEN ; For compatibility |
.equ UDRIE = 5 ; USART Data Register Empty Interrupt Enable |
.equ UDRIE0 = UDRIE ; For compatibility |
.equ TXCIE = 6 ; TX Complete Interrupt Enable |
.equ TXCIE0 = TXCIE ; For compatibility |
.equ RXCIE = 7 ; RX Complete Interrupt Enable |
.equ RXCIE0 = RXCIE ; For compatibility |
; UCSRC - USART Control and Status Register C |
.equ UCSR0C = UCSRC ; For compatibility |
.equ UCPOL = 0 ; Clock Polarity |
.equ UCPOL0 = UCPOL ; For compatibility |
.equ UCSZ0 = 1 ; Character Size |
.equ UCSZ00 = UCSZ0 ; For compatibility |
.equ UCSZ1 = 2 ; Character Size |
.equ UCSZ01 = UCSZ1 ; For compatibility |
.equ USBS = 3 ; Stop Bit Select |
.equ USBS0 = USBS ; For compatibility |
.equ UPM0 = 4 ; Parity Mode Bit 0 |
.equ UPM00 = UPM0 ; For compatibility |
.equ UPM1 = 5 ; Parity Mode Bit 1 |
.equ UPM01 = UPM1 ; For compatibility |
.equ UMSEL = 6 ; USART Mode Select |
.equ UMSEL0 = UMSEL ; For compatibility |
.equ UBRR0H = UBRRH ; For compatibility |
.equ UBRR0L = UBRRL ; For compatibility |
.equ UBRR0 = UBRRL ; For compatibility |
.equ UBRR = UBRRL ; For compatibility |
; ***** PORTH ************************ |
; PORTH - PORT H Data Register |
.equ PORTH0 = 0 ; PORT H Data Register bit 0 |
.equ PH0 = 0 ; For compatibility |
.equ PORTH1 = 1 ; PORT H Data Register bit 1 |
.equ PH1 = 1 ; For compatibility |
.equ PORTH2 = 2 ; PORT H Data Register bit 2 |
.equ PH2 = 2 ; For compatibility |
.equ PORTH3 = 3 ; PORT H Data Register bit 3 |
.equ PH3 = 3 ; For compatibility |
.equ PORTH4 = 4 ; PORT H Data Register bit 4 |
.equ PH4 = 4 ; For compatibility |
.equ PORTH5 = 5 ; PORT H Data Register bit 5 |
.equ PH5 = 5 ; For compatibility |
.equ PORTH6 = 6 ; PORT H Data Register bit 6 |
.equ PH6 = 6 ; For compatibility |
.equ PORTH7 = 7 ; PORT H Data Register bit 7 |
.equ PH7 = 7 ; For compatibility |
; DDRH - PORT H Data Direction Register |
.equ DDH0 = 0 ; PORT H Data Direction Register bit 0 |
.equ DDH1 = 1 ; PORT H Data Direction Register bit 1 |
.equ DDH2 = 2 ; PORT H Data Direction Register bit 2 |
.equ DDH3 = 3 ; PORT H Data Direction Register bit 3 |
.equ DDH4 = 4 ; PORT H Data Direction Register bit 4 |
.equ DDH5 = 5 ; PORT H Data Direction Register bit 5 |
.equ DDH6 = 6 ; PORT H Data Direction Register bit 6 |
.equ DDH7 = 7 ; PORT H Data Direction Register bit 7 |
; PINH - PORT H Input Pins |
.equ PINH0 = 0 ; PORT H Input Pins bit 0 |
.equ PINH1 = 1 ; PORT H Input Pins bit 1 |
.equ PINH2 = 2 ; PORT H Input Pins bit 2 |
.equ PINH3 = 3 ; PORT H Input Pins bit 3 |
.equ PINH4 = 4 ; PORT H Input Pins bit 4 |
.equ PINH5 = 5 ; PORT H Input Pins bit 5 |
.equ PINH6 = 6 ; PORT H Input Pins bit 6 |
.equ PINH7 = 7 ; PORT H Input Pins bit 7 |
; ***** PORTJ ************************ |
; PORTJ - PORT J Data Register |
.equ PORTJ0 = 0 ; PORT J Data Register bit 0 |
.equ PJ0 = 0 ; For compatibility |
.equ PORTJ1 = 1 ; PORT J Data Register bit 1 |
.equ PJ1 = 1 ; For compatibility |
.equ PORTJ2 = 2 ; PORT J Data Register bit 2 |
.equ PJ2 = 2 ; For compatibility |
.equ PORTJ3 = 3 ; PORT J Data Register bit 3 |
.equ PJ3 = 3 ; For compatibility |
.equ PORTJ4 = 4 ; PORT J Data Register bit 4 |
.equ PJ4 = 4 ; For compatibility |
.equ PORTJ5 = 5 ; PORT J Data Register bit 5 |
.equ PJ5 = 5 ; For compatibility |
.equ PORTJ6 = 6 ; PORT J Data Register bit 6 |
.equ PJ6 = 6 ; For compatibility |
; DDRJ - PORT J Data Direction Register |
.equ DDJ0 = 0 ; PORT J Data Direction Register bit 0 |
.equ DDJ1 = 1 ; PORT J Data Direction Register bit 1 |
.equ DDJ2 = 2 ; PORT J Data Direction Register bit 2 |
.equ DDJ3 = 3 ; PORT J Data Direction Register bit 3 |
.equ DDJ4 = 4 ; PORT J Data Direction Register bit 4 |
.equ DDJ5 = 5 ; PORT J Data Direction Register bit 5 |
.equ DDJ6 = 6 ; PORT J Data Direction Register bit 6 |
; PINJ - PORT J Input Pins |
.equ PINJ0 = 0 ; PORT J Input Pins bit 0 |
.equ PINJ1 = 1 ; PORT J Input Pins bit 1 |
.equ PINJ2 = 2 ; PORT J Input Pins bit 2 |
.equ PINJ3 = 3 ; PORT J Input Pins bit 3 |
.equ PINJ4 = 4 ; PORT J Input Pins bit 4 |
.equ PINJ5 = 5 ; PORT J Input Pins bit 5 |
.equ PINJ6 = 6 ; PORT J Input Pins bit 6 |
; ***** LOCKSBITS ******************************************************** |
.equ LB1 = 0 ; Lock bit |
.equ LB2 = 1 ; Lock bit |
.equ BLB01 = 2 ; Boot Lock bit |
.equ BLB02 = 3 ; Boot Lock bit |
.equ BLB11 = 4 ; Boot lock bit |
.equ BLB12 = 5 ; Boot lock bit |
; ***** FUSES ************************************************************ |
; LOW fuse bits |
.equ CKSEL0 = 0 ; Select Clock Source |
.equ CKSEL1 = 1 ; Select Clock Source |
.equ CKSEL2 = 2 ; Select Clock Source |
.equ CKSEL3 = 3 ; Select Clock Source |
.equ SUT0 = 4 ; Select start-up time |
.equ SUT1 = 5 ; Select start-up time |
.equ CKOUT = 6 ; Oscillator options |
.equ CLKDIV8 = 7 ; Divide clock by 8 |
; HIGH fuse bits |
.equ BOOTRST = 0 ; Select Reset Vector |
.equ BOOTSZ0 = 1 ; Select Boot Size |
.equ BOOTSZ1 = 2 ; Select Boot Size |
.equ EESAVE = 3 ; EEPROM memory is preserved through chip erase |
.equ WDTON = 4 ; Watchdog timer always on |
.equ SPIEN = 5 ; Enable Serial programming and Data Downloading |
.equ JTAGEN = 6 ; Enable JTAG |
.equ OCDEN = 7 ; Enable OCD |
; EXTENDED fuse bits |
.equ RSTDISBL = 0 ; External Reset Disable |
.equ BODLEVEL0 = 1 ; Brown-out Detector trigger level |
.equ BODLEVEL1 = 2 ; Brown-out Detector trigger level |
; ***** CPU REGISTER DEFINITIONS ***************************************** |
.def XH = r27 |
.def XL = r26 |
.def YH = r29 |
.def YL = r28 |
.def ZH = r31 |
.def ZL = r30 |
; ***** DATA MEMORY DECLARATIONS ***************************************** |
.equ FLASHEND = 0x3fff ; Note: Word address |
.equ IOEND = 0x00ff |
.equ SRAM_START = 0x0100 |
.equ SRAM_SIZE = 2048 |
.equ RAMEND = 0x08ff |
.equ XRAMEND = 0x0000 |
.equ E2END = 0x03ff |
.equ EEPROMEND = 0x03ff |
.equ EEADRBITS = 10 |
#pragma AVRPART MEMORY PROG_FLASH 32768 |
#pragma AVRPART MEMORY EEPROM 1024 |
#pragma AVRPART MEMORY INT_SRAM SIZE 2048 |
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x100 |
; ***** BOOTLOADER DECLARATIONS ****************************************** |
.equ NRWW_START_ADDR = 0x3800 |
.equ NRWW_STOP_ADDR = 0x3fff |
.equ RWW_START_ADDR = 0x0 |
.equ RWW_STOP_ADDR = 0x37ff |
.equ PAGESIZE = 64 |
.equ FIRSTBOOTSTART = 0x3f00 |
.equ SECONDBOOTSTART = 0x3e00 |
.equ THIRDBOOTSTART = 0x3c00 |
.equ FOURTHBOOTSTART = 0x3800 |
.equ SMALLBOOTSTART = FIRSTBOOTSTART |
.equ LARGEBOOTSTART = FOURTHBOOTSTART |
; ***** INTERRUPT VECTORS ************************************************ |
.equ INT0addr = 0x0002 ; External Interrupt Request 0 |
.equ PCI0addr = 0x0004 ; Pin Change Interrupt Request 0 |
.equ PCI1addr = 0x0006 ; Pin Change Interrupt Request 1 |
.equ OC2addr = 0x0008 ; Timer/Counter2 Compare Match |
.equ OVF2addr = 0x000a ; Timer/Counter2 Overflow |
.equ ICP1addr = 0x000c ; Timer/Counter1 Capture Event |
.equ OC1Aaddr = 0x000e ; Timer/Counter1 Compare Match A |
.equ OC1Baddr = 0x0010 ; Timer/Counter Compare Match B |
.equ OVF1addr = 0x0012 ; Timer/Counter1 Overflow |
.equ OC0addr = 0x0014 ; Timer/Counter0 Compare Match |
.equ OVF0addr = 0x0016 ; Timer/Counter0 Overflow |
.equ SPIaddr = 0x0018 ; SPI Serial Transfer Complete |
.equ URXCaddr = 0x001a ; USART, Rx Complete |
.equ URXC0addr = 0x001a ; For compatibility |
.equ UDREaddr = 0x001c ; USART Data register Empty |
.equ UDRE0addr = 0x001c ; For compatibility |
.equ UTXC0addr = 0x001e ; USART0, Tx Complete |
.equ UTXCaddr = 0x001e ; For compatibility |
.equ USI_STARTaddr = 0x0020 ; USI Start Condition |
.equ USI_OVFaddr = 0x0022 ; USI Overflow |
.equ ACIaddr = 0x0024 ; Analog Comparator |
.equ ADCCaddr = 0x0026 ; ADC Conversion Complete |
.equ ERDYaddr = 0x0028 ; EEPROM Ready |
.equ SPMRaddr = 0x002a ; Store Program Memory Read |
.equ RESERVEDaddr = 0x002c ; RESERVED |
.equ PCI2addr = 0x002e ; Pin Change Interrupt Request 2 |
.equ PCI3addr = 0x0030 ; Pin Change Interrupt Request 3 |
.equ INT_VECTORS_SIZE = 50 ; size in words |
#endif /* _M3250DEF_INC_ */ |
; ***** END OF FILE ****************************************************** |
/contrib/toolchain/avra/includes/m325def.inc |
---|
0,0 → 1,1048 |
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** |
;***** Created: 2005-01-11 10:31 ******* Source: ATmega325.xml *********** |
;************************************************************************* |
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y |
;* |
;* Number : AVR000 |
;* File Name : "m325def.inc" |
;* Title : Register/Bit Definitions for the ATmega325 |
;* Date : 2005-01-11 |
;* Version : 2.14 |
;* Support E-mail : avr@atmel.com |
;* Target MCU : ATmega325 |
;* |
;* DESCRIPTION |
;* When including this file in the assembly program file, all I/O register |
;* names and I/O register bit names appearing in the data book can be used. |
;* In addition, the six registers forming the three data pointers X, Y and |
;* Z have been assigned names XL - ZH. Highest RAM address for Internal |
;* SRAM is also defined |
;* |
;* The Register names are represented by their hexadecimal address. |
;* |
;* The Register Bit names are represented by their bit number (0-7). |
;* |
;* Please observe the difference in using the bit names with instructions |
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" |
;* (skip if bit in register set/cleared). The following example illustrates |
;* this: |
;* |
;* in r16,PORTB ;read PORTB latch |
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) |
;* out PORTB,r16 ;output to PORTB |
;* |
;* in r16,TIFR ;read the Timer Interrupt Flag Register |
;* sbrc r16,TOV0 ;test the overflow flag (use bit#) |
;* rjmp TOV0_is_set ;jump if set |
;* ... ;otherwise do something else |
;************************************************************************* |
#ifndef _M325DEF_INC_ |
#define _M325DEF_INC_ |
#pragma partinc 0 |
; ***** SPECIFY DEVICE *************************************************** |
.device ATmega325 |
#pragma AVRPART ADMIN PART_NAME ATmega325 |
.equ SIGNATURE_000 = 0x1e |
.equ SIGNATURE_001 = 0x95 |
.equ SIGNATURE_002 = 0x05 |
#pragma AVRPART CORE CORE_VERSION V2E |
; ***** I/O REGISTER DEFINITIONS ***************************************** |
; NOTE: |
; Definitions marked "MEMORY MAPPED"are extended I/O ports |
; and cannot be used with IN/OUT instructions |
.equ PORTJ = 0xdd ; MEMORY MAPPED |
.equ DDRJ = 0xdc ; MEMORY MAPPED |
.equ PINJ = 0xdb ; MEMORY MAPPED |
.equ PORTH = 0xda ; MEMORY MAPPED |
.equ DDRH = 0xd9 ; MEMORY MAPPED |
.equ PINH = 0xd8 ; MEMORY MAPPED |
.equ UDR = 0xc6 ; MEMORY MAPPED |
.equ UBRRH = 0xc5 ; MEMORY MAPPED |
.equ UBRRL = 0xc4 ; MEMORY MAPPED |
.equ UCSRC = 0xc2 ; MEMORY MAPPED |
.equ UCSRB = 0xc1 ; MEMORY MAPPED |
.equ UCSRA = 0xc0 ; MEMORY MAPPED |
.equ USIDR = 0xba ; MEMORY MAPPED |
.equ USISR = 0xb9 ; MEMORY MAPPED |
.equ USICR = 0xb8 ; MEMORY MAPPED |
.equ ASSR = 0xb6 ; MEMORY MAPPED |
.equ OCR2A = 0xb3 ; MEMORY MAPPED |
.equ TCNT2 = 0xb2 ; MEMORY MAPPED |
.equ TCCR2A = 0xb0 ; MEMORY MAPPED |
.equ OCR1BH = 0x8b ; MEMORY MAPPED |
.equ OCR1BL = 0x8a ; MEMORY MAPPED |
.equ OCR1AH = 0x89 ; MEMORY MAPPED |
.equ OCR1AL = 0x88 ; MEMORY MAPPED |
.equ ICR1H = 0x87 ; MEMORY MAPPED |
.equ ICR1L = 0x86 ; MEMORY MAPPED |
.equ TCNT1H = 0x85 ; MEMORY MAPPED |
.equ TCNT1L = 0x84 ; MEMORY MAPPED |
.equ TCCR1C = 0x82 ; MEMORY MAPPED |
.equ TCCR1B = 0x81 ; MEMORY MAPPED |
.equ TCCR1A = 0x80 ; MEMORY MAPPED |
.equ DIDR1 = 0x7f ; MEMORY MAPPED |
.equ DIDR0 = 0x7e ; MEMORY MAPPED |
.equ ADMUX = 0x7c ; MEMORY MAPPED |
.equ ADCSRB = 0x7b ; MEMORY MAPPED |
.equ ADCSRA = 0x7a ; MEMORY MAPPED |
.equ ADCH = 0x79 ; MEMORY MAPPED |
.equ ADCL = 0x78 ; MEMORY MAPPED |
.equ PCMSK3 = 0x73 ; MEMORY MAPPED |
.equ TIMSK2 = 0x70 ; MEMORY MAPPED |
.equ TIMSK1 = 0x6f ; MEMORY MAPPED |
.equ TIMSK0 = 0x6e ; MEMORY MAPPED |
.equ PCMSK2 = 0x6d ; MEMORY MAPPED |
.equ PCMSK1 = 0x6c ; MEMORY MAPPED |
.equ PCMSK0 = 0x6b ; MEMORY MAPPED |
.equ EICRA = 0x69 ; MEMORY MAPPED |
.equ OSCCAL = 0x66 ; MEMORY MAPPED |
.equ PRR = 0x64 ; MEMORY MAPPED |
.equ CLKPR = 0x61 ; MEMORY MAPPED |
.equ WDTCR = 0x60 ; MEMORY MAPPED |
.equ SREG = 0x3f |
.equ SPH = 0x3e |
.equ SPL = 0x3d |
.equ SPMCSR = 0x37 |
.equ MCUCR = 0x35 |
.equ MCUSR = 0x34 |
.equ SMCR = 0x33 |
.equ OCDR = 0x31 |
.equ ACSR = 0x30 |
.equ SPDR = 0x2e |
.equ SPSR = 0x2d |
.equ SPCR = 0x2c |
.equ GPIOR2 = 0x2b |
.equ GPIOR1 = 0x2a |
.equ OCR0A = 0x27 |
.equ TCNT0 = 0x26 |
.equ TCCR0A = 0x24 |
.equ GTCCR = 0x23 |
.equ EEARH = 0x22 |
.equ EEARL = 0x21 |
.equ EEDR = 0x20 |
.equ EECR = 0x1f |
.equ GPIOR0 = 0x1e |
.equ EIMSK = 0x1d |
.equ EIFR = 0x1c |
.equ TIFR2 = 0x17 |
.equ TIFR1 = 0x16 |
.equ TIFR0 = 0x15 |
.equ PORTG = 0x14 |
.equ DDRG = 0x13 |
.equ PING = 0x12 |
.equ PORTF = 0x11 |
.equ DDRF = 0x10 |
.equ PINF = 0x0f |
.equ PORTE = 0x0e |
.equ DDRE = 0x0d |
.equ PINE = 0x0c |
.equ PORTD = 0x0b |
.equ DDRD = 0x0a |
.equ PIND = 0x09 |
.equ PORTC = 0x08 |
.equ DDRC = 0x07 |
.equ PINC = 0x06 |
.equ PORTB = 0x05 |
.equ DDRB = 0x04 |
.equ PINB = 0x03 |
.equ PORTA = 0x02 |
.equ DDRA = 0x01 |
.equ PINA = 0x00 |
; ***** BIT DEFINITIONS ************************************************** |
; ***** AD_CONVERTER ***************** |
; ADMUX - The ADC multiplexer Selection Register |
.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits |
.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits |
.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits |
.equ MUX3 = 3 ; Analog Channel and Gain Selection Bits |
.equ MUX4 = 4 ; Analog Channel and Gain Selection Bits |
.equ ADLAR = 5 ; Left Adjust Result |
.equ REFS0 = 6 ; Reference Selection Bit 0 |
.equ REFS1 = 7 ; Reference Selection Bit 1 |
; ADCSRA - The ADC Control and Status register |
.equ ADPS0 = 0 ; ADC Prescaler Select Bits |
.equ ADPS1 = 1 ; ADC Prescaler Select Bits |
.equ ADPS2 = 2 ; ADC Prescaler Select Bits |
.equ ADIE = 3 ; ADC Interrupt Enable |
.equ ADIF = 4 ; ADC Interrupt Flag |
.equ ADATE = 5 ; ADC Auto Trigger Enable |
.equ ADSC = 6 ; ADC Start Conversion |
.equ ADEN = 7 ; ADC Enable |
; ADCH - ADC Data Register High Byte |
.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0 |
.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1 |
.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2 |
.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3 |
.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4 |
.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5 |
.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6 |
.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7 |
; ADCL - ADC Data Register Low Byte |
.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0 |
.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1 |
.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2 |
.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3 |
.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4 |
.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5 |
.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6 |
.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7 |
; ADCSRB - ADC Control and Status Register B |
.equ ADTS0 = 0 ; ADC Auto Trigger Source 0 |
.equ ADTS1 = 1 ; ADC Auto Trigger Source 1 |
.equ ADTS2 = 2 ; ADC Auto Trigger Source 2 |
; DIDR0 - Digital Input Disable Register 0 |
.equ ADC0D = 0 ; ADC0 Digital input Disable |
.equ ADC1D = 1 ; ADC1 Digital input Disable |
.equ ADC2D = 2 ; ADC2 Digital input Disable |
.equ ADC3D = 3 ; ADC3 Digital input Disable |
.equ ADC4D = 4 ; ADC4 Digital input Disable |
.equ ADC5D = 5 ; ADC5 Digital input Disable |
.equ ADC6D = 6 ; ADC6 Digital input Disable |
.equ ADC7D = 7 ; ADC7 Digital input Disable |
; ***** ANALOG_COMPARATOR ************ |
; ADCSRB - ADC Control and Status Register B |
.equ ACME = 6 ; Analog Comparator Multiplexer Enable |
; ACSR - Analog Comparator Control And Status Register |
.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 |
.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 |
.equ ACIC = 2 ; Analog Comparator Input Capture Enable |
.equ ACIE = 3 ; Analog Comparator Interrupt Enable |
.equ ACI = 4 ; Analog Comparator Interrupt Flag |
.equ ACO = 5 ; Analog Compare Output |
.equ ACBG = 6 ; Analog Comparator Bandgap Select |
.equ ACD = 7 ; Analog Comparator Disable |
; DIDR1 - Digital Input Disable Register 1 |
.equ AIN0D = 0 ; AIN0 Digital Input Disable |
.equ AIN1D = 1 ; AIN1 Digital Input Disable |
; ***** USART0 *********************** |
; UDR - USART I/O Data Register |
.equ UDR0 = UDR ; For compatibility |
.equ UDR00 = 0 ; USART I/O Data Register bit 0 |
.equ UDR01 = 1 ; USART I/O Data Register bit 1 |
.equ UDR02 = 2 ; USART I/O Data Register bit 2 |
.equ UDR03 = 3 ; USART I/O Data Register bit 3 |
.equ UDR04 = 4 ; USART I/O Data Register bit 4 |
.equ UDR05 = 5 ; USART I/O Data Register bit 5 |
.equ UDR06 = 6 ; USART I/O Data Register bit 6 |
.equ UDR07 = 7 ; USART I/O Data Register bit 7 |
; UCSRA - USART Control and Status Register A |
.equ UCSR0A = UCSRA ; For compatibility |
.equ USR = UCSRA ; For compatibility |
.equ MPCM = 0 ; Multi-processor Communication Mode |
.equ MPCM0 = MPCM ; For compatibility |
.equ U2X = 1 ; Double the USART Transmission Speed |
.equ U2X0 = U2X ; For compatibility |
.equ UPE = 2 ; USART Parity Error |
.equ UPE0 = UPE ; For compatibility |
.equ DOR = 3 ; Data OverRun |
.equ DOR0 = DOR ; For compatibility |
.equ FE = 4 ; Framing Error |
.equ FE0 = FE ; For compatibility |
.equ UDRE = 5 ; USART Data Register Empty |
.equ UDRE0 = UDRE ; For compatibility |
.equ TXC = 6 ; USART Transmit Complete |
.equ TXC0 = TXC ; For compatibility |
.equ RXC = 7 ; USART Receive Complete |
.equ RXC0 = RXC ; For compatibility |
; UCSRB - USART Control and Status Register B |
.equ UCSR0B = UCSRB ; For compatibility |
.equ UCR = UCSRB ; For compatibility |
.equ TXB8 = 0 ; Transmit Data Bit 8 |
.equ TXB80 = TXB8 ; For compatibility |
.equ RXB8 = 1 ; Receive Data Bit 8 |
.equ RXB80 = RXB8 ; For compatibility |
.equ UCSZ2 = 2 ; Character Size |
.equ UCSZ02 = UCSZ2 ; For compatibility |
.equ TXEN = 3 ; Transmitter Enable |
.equ TXEN0 = TXEN ; For compatibility |
.equ RXEN = 4 ; Receiver Enable |
.equ RXEN0 = RXEN ; For compatibility |
.equ UDRIE = 5 ; USART Data Register Empty Interrupt Enable |
.equ UDRIE0 = UDRIE ; For compatibility |
.equ TXCIE = 6 ; TX Complete Interrupt Enable |
.equ TXCIE0 = TXCIE ; For compatibility |
.equ RXCIE = 7 ; RX Complete Interrupt Enable |
.equ RXCIE0 = RXCIE ; For compatibility |
; UCSRC - USART Control and Status Register C |
.equ UCSR0C = UCSRC ; For compatibility |
.equ UCPOL = 0 ; Clock Polarity |
.equ UCPOL0 = UCPOL ; For compatibility |
.equ UCSZ0 = 1 ; Character Size |
.equ UCSZ00 = UCSZ0 ; For compatibility |
.equ UCSZ1 = 2 ; Character Size |
.equ UCSZ01 = UCSZ1 ; For compatibility |
.equ USBS = 3 ; Stop Bit Select |
.equ USBS0 = USBS ; For compatibility |
.equ UPM0 = 4 ; Parity Mode Bit 0 |
.equ UPM00 = UPM0 ; For compatibility |
.equ UPM1 = 5 ; Parity Mode Bit 1 |
.equ UPM01 = UPM1 ; For compatibility |
.equ UMSEL = 6 ; USART Mode Select |
.equ UMSEL0 = UMSEL ; For compatibility |
.equ UBRR0H = UBRRH ; For compatibility |
.equ UBRR0L = UBRRL ; For compatibility |
.equ UBRR0 = UBRRL ; For compatibility |
.equ UBRR = UBRRL ; For compatibility |
; ***** USI ************************** |
; USIDR - USI Data Register |
.equ USIDR0 = 0 ; USI Data Register bit 0 |
.equ USIDR1 = 1 ; USI Data Register bit 1 |
.equ USIDR2 = 2 ; USI Data Register bit 2 |
.equ USIDR3 = 3 ; USI Data Register bit 3 |
.equ USIDR4 = 4 ; USI Data Register bit 4 |
.equ USIDR5 = 5 ; USI Data Register bit 5 |
.equ USIDR6 = 6 ; USI Data Register bit 6 |
.equ USIDR7 = 7 ; USI Data Register bit 7 |
; USISR - USI Status Register |
.equ USICNT0 = 0 ; USI Counter Value Bit 0 |
.equ USICNT1 = 1 ; USI Counter Value Bit 1 |
.equ USICNT2 = 2 ; USI Counter Value Bit 2 |
.equ USICNT3 = 3 ; USI Counter Value Bit 3 |
.equ USIDC = 4 ; Data Output Collision |
.equ USIPF = 5 ; Stop Condition Flag |
.equ USIOIF = 6 ; Counter Overflow Interrupt Flag |
.equ USISIF = 7 ; Start Condition Interrupt Flag |
; USICR - USI Control Register |
.equ USITC = 0 ; Toggle Clock Port Pin |
.equ USICLK = 1 ; Clock Strobe |
.equ USICS0 = 2 ; USI Clock Source Select Bit 0 |
.equ USICS1 = 3 ; USI Clock Source Select Bit 1 |
.equ USIWM0 = 4 ; USI Wire Mode Bit 0 |
.equ USIWM1 = 5 ; USI Wire Mode Bit 1 |
.equ USIOIE = 6 ; Counter Overflow Interrupt Enable |
.equ USISIE = 7 ; Start Condition Interrupt Enable |
; ***** SPI ************************** |
; SPDR - SPI Data Register |
.equ SPDR0 = 0 ; SPI Data Register bit 0 |
.equ SPDR1 = 1 ; SPI Data Register bit 1 |
.equ SPDR2 = 2 ; SPI Data Register bit 2 |
.equ SPDR3 = 3 ; SPI Data Register bit 3 |
.equ SPDR4 = 4 ; SPI Data Register bit 4 |
.equ SPDR5 = 5 ; SPI Data Register bit 5 |
.equ SPDR6 = 6 ; SPI Data Register bit 6 |
.equ SPDR7 = 7 ; SPI Data Register bit 7 |
; SPSR - SPI Status Register |
.equ SPI2X = 0 ; Double SPI Speed Bit |
.equ WCOL = 6 ; Write Collision Flag |
.equ SPIF = 7 ; SPI Interrupt Flag |
; SPCR - SPI Control Register |
.equ SPR0 = 0 ; SPI Clock Rate Select 0 |
.equ SPR1 = 1 ; SPI Clock Rate Select 1 |
.equ CPHA = 2 ; Clock Phase |
.equ CPOL = 3 ; Clock polarity |
.equ MSTR = 4 ; Master/Slave Select |
.equ DORD = 5 ; Data Order |
.equ SPE = 6 ; SPI Enable |
.equ SPIE = 7 ; SPI Interrupt Enable |
; ***** BOOT_LOAD ******************** |
; SPMCSR - Store Program Memory Control Register |
.equ SPMCR = SPMCSR ; For compatibility |
.equ SPMEN = 0 ; Store Program Memory Enable |
.equ PGERS = 1 ; Page Erase |
.equ PGWRT = 2 ; Page Write |
.equ BLBSET = 3 ; Boot Lock Bit Set |
.equ RWWSRE = 4 ; Read While Write section read enable |
.equ ASRE = RWWSRE ; For compatibility |
.equ RWWSB = 6 ; Read While Write Section Busy |
.equ ASB = RWWSB ; For compatibility |
.equ SPMIE = 7 ; SPM Interrupt Enable |
; ***** JTAG ************************* |
; OCDR - On-Chip Debug Related Register in I/O Memory |
.equ OCDR0 = 0 ; On-Chip Debug Register Bit 0 |
.equ OCDR1 = 1 ; On-Chip Debug Register Bit 1 |
.equ OCDR2 = 2 ; On-Chip Debug Register Bit 2 |
.equ OCDR3 = 3 ; On-Chip Debug Register Bit 3 |
.equ OCDR4 = 4 ; On-Chip Debug Register Bit 4 |
.equ OCDR5 = 5 ; On-Chip Debug Register Bit 5 |
.equ OCDR6 = 6 ; On-Chip Debug Register Bit 6 |
.equ OCDR7 = 7 ; On-Chip Debug Register Bit 7 |
.equ IDRD = OCDR7 ; For compatibility |
; MCUCR - MCU Control Register |
.equ JTD = 7 ; JTAG Interface Disable |
; MCUSR - MCU Status Register |
.equ JTRF = 4 ; JTAG Reset Flag |
; ***** EXTERNAL_INTERRUPT *********** |
; EICRA - External Interrupt Control Register A |
.equ ISC00 = 0 ; External Interrupt Sense Control 0 Bit 0 |
.equ ISC01 = 1 ; External Interrupt Sense Control 0 Bit 1 |
; EIMSK - External Interrupt Mask Register |
.equ INT0 = 0 ; External Interrupt Request 0 Enable |
.equ PCIE0 = 4 ; Pin Change Interrupt Enable 0 |
.equ PCIE1 = 5 ; Pin Change Interrupt Enable 1 |
.equ PCIE2 = 6 ; Pin Change Interrupt Enable 2 |
.equ PCIE3 = 7 ; Pin Change Interrupt Enable 3 |
; EIFR - External Interrupt Flag Register |
.equ INTF0 = 0 ; External Interrupt Flag 0 |
.equ PCIF0 = 4 ; Pin Change Interrupt Flag 0 |
.equ PCIF1 = 5 ; Pin Change Interrupt Flag 1 |
.equ PCIF2 = 6 ; Pin Change Interrupt Flag 2 |
.equ PCIF3 = 7 ; Pin Change Interrupt Flag 3 |
; ***** EEPROM *********************** |
; EEDR - EEPROM Data Register |
.equ EEDR0 = 0 ; EEPROM Data Register bit 0 |
.equ EEDR1 = 1 ; EEPROM Data Register bit 1 |
.equ EEDR2 = 2 ; EEPROM Data Register bit 2 |
.equ EEDR3 = 3 ; EEPROM Data Register bit 3 |
.equ EEDR4 = 4 ; EEPROM Data Register bit 4 |
.equ EEDR5 = 5 ; EEPROM Data Register bit 5 |
.equ EEDR6 = 6 ; EEPROM Data Register bit 6 |
.equ EEDR7 = 7 ; EEPROM Data Register bit 7 |
; EECR - EEPROM Control Register |
.equ EERE = 0 ; EEPROM Read Enable |
.equ EEWE = 1 ; EEPROM Write Enable |
.equ EEMWE = 2 ; EEPROM Master Write Enable |
.equ EERIE = 3 ; EEPROM Ready Interrupt Enable |
; ***** PORTA ************************ |
; PORTA - Port A Data Register |
.equ PORTA0 = 0 ; Port A Data Register bit 0 |
.equ PA0 = 0 ; For compatibility |
.equ PORTA1 = 1 ; Port A Data Register bit 1 |
.equ PA1 = 1 ; For compatibility |
.equ PORTA2 = 2 ; Port A Data Register bit 2 |
.equ PA2 = 2 ; For compatibility |
.equ PORTA3 = 3 ; Port A Data Register bit 3 |
.equ PA3 = 3 ; For compatibility |
.equ PORTA4 = 4 ; Port A Data Register bit 4 |
.equ PA4 = 4 ; For compatibility |
.equ PORTA5 = 5 ; Port A Data Register bit 5 |
.equ PA5 = 5 ; For compatibility |
.equ PORTA6 = 6 ; Port A Data Register bit 6 |
.equ PA6 = 6 ; For compatibility |
.equ PORTA7 = 7 ; Port A Data Register bit 7 |
.equ PA7 = 7 ; For compatibility |
; DDRA - Port A Data Direction Register |
.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0 |
.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1 |
.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2 |
.equ DDA3 = 3 ; Data Direction Register, Port A, bit 3 |
.equ DDA4 = 4 ; Data Direction Register, Port A, bit 4 |
.equ DDA5 = 5 ; Data Direction Register, Port A, bit 5 |
.equ DDA6 = 6 ; Data Direction Register, Port A, bit 6 |
.equ DDA7 = 7 ; Data Direction Register, Port A, bit 7 |
; PINA - Port A Input Pins |
.equ PINA0 = 0 ; Input Pins, Port A bit 0 |
.equ PINA1 = 1 ; Input Pins, Port A bit 1 |
.equ PINA2 = 2 ; Input Pins, Port A bit 2 |
.equ PINA3 = 3 ; Input Pins, Port A bit 3 |
.equ PINA4 = 4 ; Input Pins, Port A bit 4 |
.equ PINA5 = 5 ; Input Pins, Port A bit 5 |
.equ PINA6 = 6 ; Input Pins, Port A bit 6 |
.equ PINA7 = 7 ; Input Pins, Port A bit 7 |
; ***** PORTB ************************ |
; PORTB - Port B Data Register |
.equ PORTB0 = 0 ; Port B Data Register bit 0 |
.equ PB0 = 0 ; For compatibility |
.equ PORTB1 = 1 ; Port B Data Register bit 1 |
.equ PB1 = 1 ; For compatibility |
.equ PORTB2 = 2 ; Port B Data Register bit 2 |
.equ PB2 = 2 ; For compatibility |
.equ PORTB3 = 3 ; Port B Data Register bit 3 |
.equ PB3 = 3 ; For compatibility |
.equ PORTB4 = 4 ; Port B Data Register bit 4 |
.equ PB4 = 4 ; For compatibility |
.equ PORTB5 = 5 ; Port B Data Register bit 5 |
.equ PB5 = 5 ; For compatibility |
.equ PORTB6 = 6 ; Port B Data Register bit 6 |
.equ PB6 = 6 ; For compatibility |
.equ PORTB7 = 7 ; Port B Data Register bit 7 |
.equ PB7 = 7 ; For compatibility |
; DDRB - Port B Data Direction Register |
.equ DDB0 = 0 ; Port B Data Direction Register bit 0 |
.equ DDB1 = 1 ; Port B Data Direction Register bit 1 |
.equ DDB2 = 2 ; Port B Data Direction Register bit 2 |
.equ DDB3 = 3 ; Port B Data Direction Register bit 3 |
.equ DDB4 = 4 ; Port B Data Direction Register bit 4 |
.equ DDB5 = 5 ; Port B Data Direction Register bit 5 |
.equ DDB6 = 6 ; Port B Data Direction Register bit 6 |
.equ DDB7 = 7 ; Port B Data Direction Register bit 7 |
; PINB - Port B Input Pins |
.equ PINB0 = 0 ; Port B Input Pins bit 0 |
.equ PINB1 = 1 ; Port B Input Pins bit 1 |
.equ PINB2 = 2 ; Port B Input Pins bit 2 |
.equ PINB3 = 3 ; Port B Input Pins bit 3 |
.equ PINB4 = 4 ; Port B Input Pins bit 4 |
.equ PINB5 = 5 ; Port B Input Pins bit 5 |
.equ PINB6 = 6 ; Port B Input Pins bit 6 |
.equ PINB7 = 7 ; Port B Input Pins bit 7 |
; ***** PORTC ************************ |
; PORTC - Port C Data Register |
.equ PORTC0 = 0 ; Port C Data Register bit 0 |
.equ PC0 = 0 ; For compatibility |
.equ PORTC1 = 1 ; Port C Data Register bit 1 |
.equ PC1 = 1 ; For compatibility |
.equ PORTC2 = 2 ; Port C Data Register bit 2 |
.equ PC2 = 2 ; For compatibility |
.equ PORTC3 = 3 ; Port C Data Register bit 3 |
.equ PC3 = 3 ; For compatibility |
.equ PORTC4 = 4 ; Port C Data Register bit 4 |
.equ PC4 = 4 ; For compatibility |
.equ PORTC5 = 5 ; Port C Data Register bit 5 |
.equ PC5 = 5 ; For compatibility |
.equ PORTC6 = 6 ; Port C Data Register bit 6 |
.equ PC6 = 6 ; For compatibility |
.equ PORTC7 = 7 ; Port C Data Register bit 7 |
.equ PC7 = 7 ; For compatibility |
; DDRC - Port C Data Direction Register |
.equ DDC0 = 0 ; Port C Data Direction Register bit 0 |
.equ DDC1 = 1 ; Port C Data Direction Register bit 1 |
.equ DDC2 = 2 ; Port C Data Direction Register bit 2 |
.equ DDC3 = 3 ; Port C Data Direction Register bit 3 |
.equ DDC4 = 4 ; Port C Data Direction Register bit 4 |
.equ DDC5 = 5 ; Port C Data Direction Register bit 5 |
.equ DDC6 = 6 ; Port C Data Direction Register bit 6 |
.equ DDC7 = 7 ; Port C Data Direction Register bit 7 |
; PINC - Port C Input Pins |
.equ PINC0 = 0 ; Port C Input Pins bit 0 |
.equ PINC1 = 1 ; Port C Input Pins bit 1 |
.equ PINC2 = 2 ; Port C Input Pins bit 2 |
.equ PINC3 = 3 ; Port C Input Pins bit 3 |
.equ PINC4 = 4 ; Port C Input Pins bit 4 |
.equ PINC5 = 5 ; Port C Input Pins bit 5 |
.equ PINC6 = 6 ; Port C Input Pins bit 6 |
.equ PINC7 = 7 ; Port C Input Pins bit 7 |
; ***** PORTD ************************ |
; PORTD - Port D Data Register |
.equ PORTD0 = 0 ; Port D Data Register bit 0 |
.equ PD0 = 0 ; For compatibility |
.equ PORTD1 = 1 ; Port D Data Register bit 1 |
.equ PD1 = 1 ; For compatibility |
.equ PORTD2 = 2 ; Port D Data Register bit 2 |
.equ PD2 = 2 ; For compatibility |
.equ PORTD3 = 3 ; Port D Data Register bit 3 |
.equ PD3 = 3 ; For compatibility |
.equ PORTD4 = 4 ; Port D Data Register bit 4 |
.equ PD4 = 4 ; For compatibility |
.equ PORTD5 = 5 ; Port D Data Register bit 5 |
.equ PD5 = 5 ; For compatibility |
.equ PORTD6 = 6 ; Port D Data Register bit 6 |
.equ PD6 = 6 ; For compatibility |
.equ PORTD7 = 7 ; Port D Data Register bit 7 |
.equ PD7 = 7 ; For compatibility |
; DDRD - Port D Data Direction Register |
.equ DDD0 = 0 ; Port D Data Direction Register bit 0 |
.equ DDD1 = 1 ; Port D Data Direction Register bit 1 |
.equ DDD2 = 2 ; Port D Data Direction Register bit 2 |
.equ DDD3 = 3 ; Port D Data Direction Register bit 3 |
.equ DDD4 = 4 ; Port D Data Direction Register bit 4 |
.equ DDD5 = 5 ; Port D Data Direction Register bit 5 |
.equ DDD6 = 6 ; Port D Data Direction Register bit 6 |
.equ DDD7 = 7 ; Port D Data Direction Register bit 7 |
; PIND - Port D Input Pins |
.equ PIND0 = 0 ; Port D Input Pins bit 0 |
.equ PIND1 = 1 ; Port D Input Pins bit 1 |
.equ PIND2 = 2 ; Port D Input Pins bit 2 |
.equ PIND3 = 3 ; Port D Input Pins bit 3 |
.equ PIND4 = 4 ; Port D Input Pins bit 4 |
.equ PIND5 = 5 ; Port D Input Pins bit 5 |
.equ PIND6 = 6 ; Port D Input Pins bit 6 |
.equ PIND7 = 7 ; Port D Input Pins bit 7 |
; ***** PORTE ************************ |
; PORTE - Data Register, Port E |
.equ PORTE0 = 0 ; |
.equ PE0 = 0 ; For compatibility |
.equ PORTE1 = 1 ; |
.equ PE1 = 1 ; For compatibility |
.equ PORTE2 = 2 ; |
.equ PE2 = 2 ; For compatibility |
.equ PORTE3 = 3 ; |
.equ PE3 = 3 ; For compatibility |
.equ PORTE4 = 4 ; |
.equ PE4 = 4 ; For compatibility |
.equ PORTE5 = 5 ; |
.equ PE5 = 5 ; For compatibility |
.equ PORTE6 = 6 ; |
.equ PE6 = 6 ; For compatibility |
.equ PORTE7 = 7 ; |
.equ PE7 = 7 ; For compatibility |
; DDRE - Data Direction Register, Port E |
.equ DDE0 = 0 ; |
.equ DDE1 = 1 ; |
.equ DDE2 = 2 ; |
.equ DDE3 = 3 ; |
.equ DDE4 = 4 ; |
.equ DDE5 = 5 ; |
.equ DDE6 = 6 ; |
.equ DDE7 = 7 ; |
; PINE - Input Pins, Port E |
.equ PINE0 = 0 ; |
.equ PINE1 = 1 ; |
.equ PINE2 = 2 ; |
.equ PINE3 = 3 ; |
.equ PINE4 = 4 ; |
.equ PINE5 = 5 ; |
.equ PINE6 = 6 ; |
.equ PINE7 = 7 ; |
; ***** PORTF ************************ |
; PORTF - Data Register, Port F |
.equ PORTF0 = 0 ; |
.equ PF0 = 0 ; For compatibility |
.equ PORTF1 = 1 ; |
.equ PF1 = 1 ; For compatibility |
.equ PORTF2 = 2 ; |
.equ PF2 = 2 ; For compatibility |
.equ PORTF3 = 3 ; |
.equ PF3 = 3 ; For compatibility |
.equ PORTF4 = 4 ; |
.equ PF4 = 4 ; For compatibility |
.equ PORTF5 = 5 ; |
.equ PF5 = 5 ; For compatibility |
.equ PORTF6 = 6 ; |
.equ PF6 = 6 ; For compatibility |
.equ PORTF7 = 7 ; |
.equ PF7 = 7 ; For compatibility |
; DDRF - Data Direction Register, Port F |
.equ DDF0 = 0 ; |
.equ DDF1 = 1 ; |
.equ DDF2 = 2 ; |
.equ DDF3 = 3 ; |
.equ DDF4 = 4 ; |
.equ DDF5 = 5 ; |
.equ DDF6 = 6 ; |
.equ DDF7 = 7 ; |
; PINF - Input Pins, Port F |
.equ PINF0 = 0 ; |
.equ PINF1 = 1 ; |
.equ PINF2 = 2 ; |
.equ PINF3 = 3 ; |
.equ PINF4 = 4 ; |
.equ PINF5 = 5 ; |
.equ PINF6 = 6 ; |
.equ PINF7 = 7 ; |
; ***** PORTG ************************ |
; PORTG - Port G Data Register |
.equ PORTG0 = 0 ; |
.equ PG0 = 0 ; For compatibility |
.equ PORTG1 = 1 ; |
.equ PG1 = 1 ; For compatibility |
.equ PORTG2 = 2 ; |
.equ PG2 = 2 ; For compatibility |
.equ PORTG3 = 3 ; |
.equ PG3 = 3 ; For compatibility |
.equ PORTG4 = 4 ; |
.equ PG4 = 4 ; For compatibility |
; DDRG - Port G Data Direction Register |
.equ DDG0 = 0 ; |
.equ DDG1 = 1 ; |
.equ DDG2 = 2 ; |
.equ DDG3 = 3 ; |
.equ DDG4 = 4 ; |
; PING - Port G Input Pins |
.equ PING0 = 0 ; |
.equ PING1 = 1 ; |
.equ PING2 = 2 ; |
.equ PING3 = 3 ; |
.equ PING4 = 4 ; |
.equ PING5 = 5 ; |
; ***** TIMER_COUNTER_0 ************** |
; TCCR0A - Timer/Counter0 Control Register |
.equ CS00 = 0 ; Clock Select 1 |
.equ CS01 = 1 ; Clock Select 1 |
.equ CS02 = 2 ; Clock Select 2 |
.equ WGM01 = 3 ; Waveform Generation Mode 1 |
.equ COM0A0 = 4 ; Compare match Output Mode 0 |
.equ COM0A1 = 5 ; Compare Match Output Mode 1 |
.equ WGM00 = 6 ; Waveform Generation Mode 0 |
.equ FOC0A = 7 ; Force Output Compare |
; TCNT0 - Timer/Counter0 |
.equ TCNT0_0 = 0 ; |
.equ TCNT0_1 = 1 ; |
.equ TCNT0_2 = 2 ; |
.equ TCNT0_3 = 3 ; |
.equ TCNT0_4 = 4 ; |
.equ TCNT0_5 = 5 ; |
.equ TCNT0_6 = 6 ; |
.equ TCNT0_7 = 7 ; |
; OCR0A - Timer/Counter0 Output Compare Register |
.equ OCR0A0 = 0 ; |
.equ OCR0A1 = 1 ; |
.equ OCR0A2 = 2 ; |
.equ OCR0A3 = 3 ; |
.equ OCR0A4 = 4 ; |
.equ OCR0A5 = 5 ; |
.equ OCR0A6 = 6 ; |
.equ OCR0A7 = 7 ; |
; TIMSK0 - Timer/Counter0 Interrupt Mask Register |
.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable |
.equ OCIE0A = 1 ; Timer/Counter0 Output Compare Match Interrupt Enable |
; TIFR0 - Timer/Counter0 Interrupt Flag register |
.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag |
.equ OCF0A = 1 ; Timer/Counter0 Output Compare Flag 0 |
; GTCCR - General Timer/Control Register |
.equ PSR310 = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0 |
.equ PSR10 = PSR310 ; For compatibility |
.equ PSR0 = PSR310 ; For compatibility |
.equ PSR1 = PSR310 ; For compatibility |
.equ PSR3 = PSR310 ; For compatibility |
.equ TSM = 7 ; Timer/Counter Synchronization Mode |
; ***** TIMER_COUNTER_1 ************** |
; TIMSK1 - Timer/Counter1 Interrupt Mask Register |
.equ TOIE1 = 0 ; Timer/Counter1 Overflow Interrupt Enable |
.equ OCIE1A = 1 ; Timer/Counter1 Output Compare A Match Interrupt Enable |
.equ OCIE1B = 2 ; Timer/Counter1 Output Compare B Match Interrupt Enable |
.equ ICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable |
; TIFR1 - Timer/Counter1 Interrupt Flag register |
.equ TOV1 = 0 ; Timer/Counter1 Overflow Flag |
.equ OCF1A = 1 ; Output Compare Flag 1A |
.equ OCF1B = 2 ; Output Compare Flag 1B |
.equ ICF1 = 5 ; Input Capture Flag 1 |
; TCCR1A - Timer/Counter1 Control Register A |
.equ WGM10 = 0 ; Waveform Generation Mode |
.equ WGM11 = 1 ; Waveform Generation Mode |
.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0 |
.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1 |
.equ COM1A0 = 6 ; Compare Output Mode 1A, bit 0 |
.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1 |
; TCCR1B - Timer/Counter1 Control Register B |
.equ CS10 = 0 ; Prescaler source of Timer/Counter 1 |
.equ CS11 = 1 ; Prescaler source of Timer/Counter 1 |
.equ CS12 = 2 ; Prescaler source of Timer/Counter 1 |
.equ WGM12 = 3 ; Waveform Generation Mode |
.equ WGM13 = 4 ; Waveform Generation Mode |
.equ ICES1 = 6 ; Input Capture 1 Edge Select |
.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler |
; TCCR1C - Timer/Counter 1 Control Register C |
.equ FOC1B = 6 ; Force Output Compare 1B |
.equ FOC1A = 7 ; Force Output Compare 1A |
; ***** TIMER_COUNTER_2 ************** |
; TIMSK2 - Timer/Counter2 Interrupt Mask register |
.equ TOIE2 = 0 ; Timer/Counter2 Overflow Interrupt Enable |
.equ OCIE2A = 1 ; Timer/Counter2 Output Compare Match Interrupt Enable |
; TIFR2 - Timer/Counter2 Interrupt Flag Register |
.equ TOV2 = 0 ; Timer/Counter2 Overflow Flag |
.equ OCF2A = 1 ; Timer/Counter2 Output Compare Flag 2 |
; TCCR2A - Timer/Counter2 Control Register |
.equ CS20 = 0 ; Clock Select bit 0 |
.equ CS21 = 1 ; Clock Select bit 1 |
.equ CS22 = 2 ; Clock Select bit 2 |
.equ WGM21 = 3 ; Waveform Generation Mode |
.equ COM2A0 = 4 ; Compare Output Mode bit 0 |
.equ COM2A1 = 5 ; Compare Output Mode bit 1 |
.equ WGM20 = 6 ; Waveform Generation Mode |
.equ FOC2A = 7 ; Force Output Compare A |
; TCNT2 - Timer/Counter2 |
.equ TCNT2_0 = 0 ; Timer/Counter 2 bit 0 |
.equ TCNT2_1 = 1 ; Timer/Counter 2 bit 1 |
.equ TCNT2_2 = 2 ; Timer/Counter 2 bit 2 |
.equ TCNT2_3 = 3 ; Timer/Counter 2 bit 3 |
.equ TCNT2_4 = 4 ; Timer/Counter 2 bit 4 |
.equ TCNT2_5 = 5 ; Timer/Counter 2 bit 5 |
.equ TCNT2_6 = 6 ; Timer/Counter 2 bit 6 |
.equ TCNT2_7 = 7 ; Timer/Counter 2 bit 7 |
; OCR2A - Timer/Counter2 Output Compare Register |
.equ OCR2A0 = 0 ; Timer/Counter2 Output Compare Register Bit 0 |
.equ OCR2A1 = 1 ; Timer/Counter2 Output Compare Register Bit 1 |
.equ OCR2A2 = 2 ; Timer/Counter2 Output Compare Register Bit 2 |
.equ OCR2A3 = 3 ; Timer/Counter2 Output Compare Register Bit 3 |
.equ OCR2A4 = 4 ; Timer/Counter2 Output Compare Register Bit 4 |
.equ OCR2A5 = 5 ; Timer/Counter2 Output Compare Register Bit 5 |
.equ OCR2A6 = 6 ; Timer/Counter2 Output Compare Register Bit 6 |
.equ OCR2A7 = 7 ; Timer/Counter2 Output Compare Register Bit 7 |
; GTCCR - General Timer/Counter Control Register |
.equ PSR2 = 1 ; Prescaler Reset Timer/Counter2 |
; ASSR - Asynchronous Status Register |
.equ TCR2UB = 0 ; TCR2UB: Timer/Counter Control Register2 Update Busy |
.equ OCR2UB = 1 ; Output Compare Register2 Update Busy |
.equ TCN2UB = 2 ; TCN2UB: Timer/Counter2 Update Busy |
.equ AS2 = 3 ; AS2: Asynchronous Timer/Counter2 |
.equ EXCLK = 4 ; Enable External Clock Interrupt |
; ***** WATCHDOG ********************* |
; WDTCR - Watchdog Timer Control Register |
.equ WDTCSR = WDTCR ; For compatibility |
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 |
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 |
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 |
.equ WDE = 3 ; Watch Dog Enable |
.equ WDCE = 4 ; Watchdog Change Enable |
.equ WDTOE = WDCE ; For compatibility |
; ***** CPU ************************** |
; SREG - Status Register |
.equ SREG_C = 0 ; Carry Flag |
.equ SREG_Z = 1 ; Zero Flag |
.equ SREG_N = 2 ; Negative Flag |
.equ SREG_V = 3 ; Two's Complement Overflow Flag |
.equ SREG_S = 4 ; Sign Bit |
.equ SREG_H = 5 ; Half Carry Flag |
.equ SREG_T = 6 ; Bit Copy Storage |
.equ SREG_I = 7 ; Global Interrupt Enable |
; MCUCR - MCU Control Register |
.equ IVCE = 0 ; Interrupt Vector Change Enable |
.equ IVSEL = 1 ; Interrupt Vector Select |
.equ PUD = 4 ; Pull-up disable |
; MCUSR - MCU Status Register |
.equ PORF = 0 ; Power-on reset flag |
.equ EXTRF = 1 ; External Reset Flag |
.equ BORF = 2 ; Brown-out Reset Flag |
.equ WDRF = 3 ; Watchdog Reset Flag |
;.equ JTRF = 4 ; JTAG Reset Flag |
; OSCCAL - Oscillator Calibration Value |
.equ CAL0 = 0 ; Oscillator Calibration Value Bit0 |
.equ CAL1 = 1 ; Oscillator Calibration Value Bit1 |
.equ CAL2 = 2 ; Oscillator Calibration Value Bit2 |
.equ CAL3 = 3 ; Oscillator Calibration Value Bit3 |
.equ CAL4 = 4 ; Oscillator Calibration Value Bit4 |
.equ CAL5 = 5 ; Oscillator Calibration Value Bit5 |
.equ CAL6 = 6 ; Oscillator Calibration Value Bit6 |
.equ CAL7 = 7 ; Oscillator Calibration Value Bit7 |
; CLKPR - Clock Prescale Register |
.equ CLKPS0 = 0 ; Clock Prescaler Select Bit 0 |
.equ CLKPS1 = 1 ; Clock Prescaler Select Bit 1 |
.equ CLKPS2 = 2 ; Clock Prescaler Select Bit 2 |
.equ CLKPS3 = 3 ; Clock Prescaler Select Bit 3 |
.equ CLKPCE = 7 ; Clock Prescaler Change Enable |
; PRR - Power Reduction Register |
.equ PRADC = 0 ; Power Reduction ADC |
.equ PRUSART0 = 1 ; Power Reduction USART |
.equ PRSPI = 2 ; Power Reduction Serial Peripheral Interface |
.equ PRTIM1 = 3 ; Power Reduction Timer/Counter1 |
; SMCR - Sleep Mode Control Register |
.equ SE = 0 ; Sleep Enable |
.equ SM0 = 1 ; Sleep Mode Select bit 0 |
.equ SM1 = 2 ; Sleep Mode Select bit 1 |
.equ SM2 = 3 ; Sleep Mode Select bit 2 |
; GPIOR2 - General Purpose IO Register 2 |
.equ GPIOR20 = 0 ; General Purpose IO Register 2 bit 0 |
.equ GPIOR21 = 1 ; General Purpose IO Register 2 bit 1 |
.equ GPIOR22 = 2 ; General Purpose IO Register 2 bit 2 |
.equ GPIOR23 = 3 ; General Purpose IO Register 2 bit 3 |
.equ GPIOR24 = 4 ; General Purpose IO Register 2 bit 4 |
.equ GPIOR25 = 5 ; General Purpose IO Register 2 bit 5 |
.equ GPIOR26 = 6 ; General Purpose IO Register 2 bit 6 |
.equ GPIOR27 = 7 ; General Purpose IO Register 2 bit 7 |
; GPIOR1 - General Purpose IO Register 1 |
.equ GPIOR10 = 0 ; General Purpose IO Register 1 bit 0 |
.equ GPIOR11 = 1 ; General Purpose IO Register 1 bit 1 |
.equ GPIOR12 = 2 ; General Purpose IO Register 1 bit 2 |
.equ GPIOR13 = 3 ; General Purpose IO Register 1 bit 3 |
.equ GPIOR14 = 4 ; General Purpose IO Register 1 bit 4 |
.equ GPIOR15 = 5 ; General Purpose IO Register 1 bit 5 |
.equ GPIOR16 = 6 ; General Purpose IO Register 1 bit 6 |
.equ GPIOR17 = 7 ; General Purpose IO Register 1 bit 7 |
; GPIOR0 - General Purpose IO Register 0 |
.equ GPIOR00 = 0 ; General Purpose IO Register 0 bit 0 |
.equ GPIOR01 = 1 ; General Purpose IO Register 0 bit 1 |
.equ GPIOR02 = 2 ; General Purpose IO Register 0 bit 2 |
.equ GPIOR03 = 3 ; General Purpose IO Register 0 bit 3 |
.equ GPIOR04 = 4 ; General Purpose IO Register 0 bit 4 |
.equ GPIOR05 = 5 ; General Purpose IO Register 0 bit 5 |
.equ GPIOR06 = 6 ; General Purpose IO Register 0 bit 6 |
.equ GPIOR07 = 7 ; General Purpose IO Register 0 bit 7 |
; ***** LOCKSBITS ******************************************************** |
.equ LB1 = 0 ; Lock bit |
.equ LB2 = 1 ; Lock bit |
.equ BLB01 = 2 ; Boot Lock bit |
.equ BLB02 = 3 ; Boot Lock bit |
.equ BLB11 = 4 ; Boot lock bit |
.equ BLB12 = 5 ; Boot lock bit |
; ***** FUSES ************************************************************ |
; LOW fuse bits |
.equ CKSEL0 = 0 ; Select Clock Source |
.equ CKSEL1 = 1 ; Select Clock Source |
.equ CKSEL2 = 2 ; Select Clock Source |
.equ CKSEL3 = 3 ; Select Clock Source |
.equ SUT0 = 4 ; Select start-up time |
.equ SUT1 = 5 ; Select start-up time |
.equ CKOUT = 6 ; Oscillator options |
.equ CLKDIV8 = 7 ; Divide clock by 8 |
; HIGH fuse bits |
.equ BOOTRST = 0 ; Select Reset Vector |
.equ BOOTSZ0 = 1 ; Select Boot Size |
.equ BOOTSZ1 = 2 ; Select Boot Size |
.equ EESAVE = 3 ; EEPROM memory is preserved through chip erase |
.equ WDTON = 4 ; Watchdog timer always on |
.equ SPIEN = 5 ; Enable Serial programming and Data Downloading |
.equ JTAGEN = 6 ; Enable JTAG |
.equ OCDEN = 7 ; Enable OCD |
; EXTENDED fuse bits |
.equ RSTDISBL = 0 ; External Reset Disable |
.equ BODLEVEL0 = 1 ; Brown-out Detector trigger level |
.equ BODLEVEL1 = 2 ; Brown-out Detector trigger level |
; ***** CPU REGISTER DEFINITIONS ***************************************** |
.def XH = r27 |
.def XL = r26 |
.def YH = r29 |
.def YL = r28 |
.def ZH = r31 |
.def ZL = r30 |
; ***** DATA MEMORY DECLARATIONS ***************************************** |
.equ FLASHEND = 0x3fff ; Note: Word address |
.equ IOEND = 0x00ff |
.equ SRAM_START = 0x0100 |
.equ SRAM_SIZE = 2048 |
.equ RAMEND = 0x08ff |
.equ XRAMEND = 0x0000 |
.equ E2END = 0x03ff |
.equ EEPROMEND = 0x03ff |
.equ EEADRBITS = 10 |
#pragma AVRPART MEMORY PROG_FLASH 32768 |
#pragma AVRPART MEMORY EEPROM 1024 |
#pragma AVRPART MEMORY INT_SRAM SIZE 2048 |
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x100 |
; ***** BOOTLOADER DECLARATIONS ****************************************** |
.equ NRWW_START_ADDR = 0x3800 |
.equ NRWW_STOP_ADDR = 0x3fff |
.equ RWW_START_ADDR = 0x0 |
.equ RWW_STOP_ADDR = 0x37ff |
.equ PAGESIZE = 64 |
.equ FIRSTBOOTSTART = 0x3f00 |
.equ SECONDBOOTSTART = 0x3e00 |
.equ THIRDBOOTSTART = 0x3c00 |
.equ FOURTHBOOTSTART = 0x3800 |
.equ SMALLBOOTSTART = FIRSTBOOTSTART |
.equ LARGEBOOTSTART = FOURTHBOOTSTART |
; ***** INTERRUPT VECTORS ************************************************ |
.equ INT0addr = 0x0002 ; External Interrupt Request 0 |
.equ PCI0addr = 0x0004 ; Pin Change Interrupt Request 0 |
.equ PCI1addr = 0x0006 ; Pin Change Interrupt Request 1 |
.equ OC2addr = 0x0008 ; Timer/Counter2 Compare Match |
.equ OVF2addr = 0x000a ; Timer/Counter2 Overflow |
.equ ICP1addr = 0x000c ; Timer/Counter1 Capture Event |
.equ OC1Aaddr = 0x000e ; Timer/Counter1 Compare Match A |
.equ OC1Baddr = 0x0010 ; Timer/Counter Compare Match B |
.equ OVF1addr = 0x0012 ; Timer/Counter1 Overflow |
.equ OC0addr = 0x0014 ; Timer/Counter0 Compare Match |
.equ OVF0addr = 0x0016 ; Timer/Counter0 Overflow |
.equ SPIaddr = 0x0018 ; SPI Serial Transfer Complete |
.equ URXC0addr = 0x001a ; USART0, Rx Complete |
.equ URXCaddr = 0x001a ; For compatibility |
.equ UDRE0addr = 0x001c ; USART0 Data register Empty |
.equ UDREaddr = 0x001c ; For compatibility |
.equ UTXC0addr = 0x001e ; USART0, Tx Complete |
.equ UTXCaddr = 0x001e ; For compatibility |
.equ USI_STARTaddr = 0x0020 ; USI Start Condition |
.equ USI_OVFaddr = 0x0022 ; USI Overflow |
.equ ACIaddr = 0x0024 ; Analog Comparator |
.equ ADCCaddr = 0x0026 ; ADC Conversion Complete |
.equ ERDYaddr = 0x0028 ; EEPROM Ready |
.equ SPMRaddr = 0x002a ; Store Program Memory Read |
.equ INT_VECTORS_SIZE = 44 ; size in words |
#endif /* _M325DEF_INC_ */ |
; ***** END OF FILE ****************************************************** |
/contrib/toolchain/avra/includes/m3290def.inc |
---|
0,0 → 1,1427 |
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** |
;***** Created: 2005-01-11 10:31 ******* Source: ATmega3290.xml ********** |
;************************************************************************* |
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y |
;* |
;* Number : AVR000 |
;* File Name : "m3290def.inc" |
;* Title : Register/Bit Definitions for the ATmega3290 |
;* Date : 2005-01-11 |
;* Version : 2.14 |
;* Support E-mail : avr@atmel.com |
;* Target MCU : ATmega3290 |
;* |
;* DESCRIPTION |
;* When including this file in the assembly program file, all I/O register |
;* names and I/O register bit names appearing in the data book can be used. |
;* In addition, the six registers forming the three data pointers X, Y and |
;* Z have been assigned names XL - ZH. Highest RAM address for Internal |
;* SRAM is also defined |
;* |
;* The Register names are represented by their hexadecimal address. |
;* |
;* The Register Bit names are represented by their bit number (0-7). |
;* |
;* Please observe the difference in using the bit names with instructions |
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" |
;* (skip if bit in register set/cleared). The following example illustrates |
;* this: |
;* |
;* in r16,PORTB ;read PORTB latch |
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) |
;* out PORTB,r16 ;output to PORTB |
;* |
;* in r16,TIFR ;read the Timer Interrupt Flag Register |
;* sbrc r16,TOV0 ;test the overflow flag (use bit#) |
;* rjmp TOV0_is_set ;jump if set |
;* ... ;otherwise do something else |
;************************************************************************* |
#ifndef _M3290DEF_INC_ |
#define _M3290DEF_INC_ |
#pragma partinc 0 |
; ***** SPECIFY DEVICE *************************************************** |
.device ATmega3290 |
#pragma AVRPART ADMIN PART_NAME ATmega3290 |
.equ SIGNATURE_000 = 0x1e |
.equ SIGNATURE_001 = 0x95 |
.equ SIGNATURE_002 = 0x04 |
#pragma AVRPART CORE CORE_VERSION V2E |
; ***** I/O REGISTER DEFINITIONS ***************************************** |
; NOTE: |
; Definitions marked "MEMORY MAPPED"are extended I/O ports |
; and cannot be used with IN/OUT instructions |
.equ LCDDR19 = 0xff ; MEMORY MAPPED |
.equ LCDDR18 = 0xfe ; MEMORY MAPPED |
.equ LCDDR17 = 0xfd ; MEMORY MAPPED |
.equ LCDDR16 = 0xfc ; MEMORY MAPPED |
.equ LCDDR15 = 0xfb ; MEMORY MAPPED |
.equ LCDDR14 = 0xfa ; MEMORY MAPPED |
.equ LCDDR13 = 0xf9 ; MEMORY MAPPED |
.equ LCDDR12 = 0xf8 ; MEMORY MAPPED |
.equ LCDDR11 = 0xf7 ; MEMORY MAPPED |
.equ LCDDR10 = 0xf6 ; MEMORY MAPPED |
.equ LCDDR9 = 0xf5 ; MEMORY MAPPED |
.equ LCDDR8 = 0xf4 ; MEMORY MAPPED |
.equ LCDDR7 = 0xf3 ; MEMORY MAPPED |
.equ LCDDR6 = 0xf2 ; MEMORY MAPPED |
.equ LCDDR5 = 0xf1 ; MEMORY MAPPED |
.equ LCDDR4 = 0xf0 ; MEMORY MAPPED |
.equ LCDDR3 = 0xef ; MEMORY MAPPED |
.equ LCDDR2 = 0xee ; MEMORY MAPPED |
.equ LCDDR1 = 0xed ; MEMORY MAPPED |
.equ LCDDR0 = 0xec ; MEMORY MAPPED |
.equ LCDCCR = 0xe7 ; MEMORY MAPPED |
.equ LCDFRR = 0xe6 ; MEMORY MAPPED |
.equ LCDCRB = 0xe5 ; MEMORY MAPPED |
.equ LCDCRA = 0xe4 ; MEMORY MAPPED |
.equ PORTJ = 0xdd ; MEMORY MAPPED |
.equ DDRJ = 0xdc ; MEMORY MAPPED |
.equ PINJ = 0xdb ; MEMORY MAPPED |
.equ PORTH = 0xda ; MEMORY MAPPED |
.equ DDRH = 0xd9 ; MEMORY MAPPED |
.equ PINH = 0xd8 ; MEMORY MAPPED |
.equ UDR = 0xc6 ; MEMORY MAPPED |
.equ UBRRH = 0xc5 ; MEMORY MAPPED |
.equ UBRRL = 0xc4 ; MEMORY MAPPED |
.equ UCSRC = 0xc2 ; MEMORY MAPPED |
.equ UCSRB = 0xc1 ; MEMORY MAPPED |
.equ UCSRA = 0xc0 ; MEMORY MAPPED |
.equ USIDR = 0xba ; MEMORY MAPPED |
.equ USISR = 0xb9 ; MEMORY MAPPED |
.equ USICR = 0xb8 ; MEMORY MAPPED |
.equ ASSR = 0xb6 ; MEMORY MAPPED |
.equ OCR2A = 0xb3 ; MEMORY MAPPED |
.equ TCNT2 = 0xb2 ; MEMORY MAPPED |
.equ TCCR2A = 0xb0 ; MEMORY MAPPED |
.equ OCR1BH = 0x8b ; MEMORY MAPPED |
.equ OCR1BL = 0x8a ; MEMORY MAPPED |
.equ OCR1AH = 0x89 ; MEMORY MAPPED |
.equ OCR1AL = 0x88 ; MEMORY MAPPED |
.equ ICR1H = 0x87 ; MEMORY MAPPED |
.equ ICR1L = 0x86 ; MEMORY MAPPED |
.equ TCNT1H = 0x85 ; MEMORY MAPPED |
.equ TCNT1L = 0x84 ; MEMORY MAPPED |
.equ TCCR1C = 0x82 ; MEMORY MAPPED |
.equ TCCR1B = 0x81 ; MEMORY MAPPED |
.equ TCCR1A = 0x80 ; MEMORY MAPPED |
.equ DIDR1 = 0x7f ; MEMORY MAPPED |
.equ DIDR0 = 0x7e ; MEMORY MAPPED |
.equ ADMUX = 0x7c ; MEMORY MAPPED |
.equ ADCSRB = 0x7b ; MEMORY MAPPED |
.equ ADCSRA = 0x7a ; MEMORY MAPPED |
.equ ADCH = 0x79 ; MEMORY MAPPED |
.equ ADCL = 0x78 ; MEMORY MAPPED |
.equ PCMSK3 = 0x73 ; MEMORY MAPPED |
.equ TIMSK2 = 0x70 ; MEMORY MAPPED |
.equ TIMSK1 = 0x6f ; MEMORY MAPPED |
.equ TIMSK0 = 0x6e ; MEMORY MAPPED |
.equ PCMSK2 = 0x6d ; MEMORY MAPPED |
.equ PCMSK1 = 0x6c ; MEMORY MAPPED |
.equ PCMSK0 = 0x6b ; MEMORY MAPPED |
.equ EICRA = 0x69 ; MEMORY MAPPED |
.equ OSCCAL = 0x66 ; MEMORY MAPPED |
.equ PRR = 0x64 ; MEMORY MAPPED |
.equ CLKPR = 0x61 ; MEMORY MAPPED |
.equ WDTCR = 0x60 ; MEMORY MAPPED |
.equ SREG = 0x3f |
.equ SPH = 0x3e |
.equ SPL = 0x3d |
.equ SPMCSR = 0x37 |
.equ MCUCR = 0x35 |
.equ MCUSR = 0x34 |
.equ SMCR = 0x33 |
.equ OCDR = 0x31 |
.equ ACSR = 0x30 |
.equ SPDR = 0x2e |
.equ SPSR = 0x2d |
.equ SPCR = 0x2c |
.equ GPIOR2 = 0x2b |
.equ GPIOR1 = 0x2a |
.equ OCR0A = 0x27 |
.equ TCNT0 = 0x26 |
.equ TCCR0A = 0x24 |
.equ GTCCR = 0x23 |
.equ EEARH = 0x22 |
.equ EEARL = 0x21 |
.equ EEDR = 0x20 |
.equ EECR = 0x1f |
.equ GPIOR0 = 0x1e |
.equ EIMSK = 0x1d |
.equ EIFR = 0x1c |
.equ TIFR2 = 0x17 |
.equ TIFR1 = 0x16 |
.equ TIFR0 = 0x15 |
.equ PORTG = 0x14 |
.equ DDRG = 0x13 |
.equ PING = 0x12 |
.equ PORTF = 0x11 |
.equ DDRF = 0x10 |
.equ PINF = 0x0f |
.equ PORTE = 0x0e |
.equ DDRE = 0x0d |
.equ PINE = 0x0c |
.equ PORTD = 0x0b |
.equ DDRD = 0x0a |
.equ PIND = 0x09 |
.equ PORTC = 0x08 |
.equ DDRC = 0x07 |
.equ PINC = 0x06 |
.equ PORTB = 0x05 |
.equ DDRB = 0x04 |
.equ PINB = 0x03 |
.equ PORTA = 0x02 |
.equ DDRA = 0x01 |
.equ PINA = 0x00 |
; ***** BIT DEFINITIONS ************************************************** |
; ***** TIMER_COUNTER_0 ************** |
; TCCR0A - Timer/Counter0 Control Register |
.equ CS00 = 0 ; Clock Select 1 |
.equ CS01 = 1 ; Clock Select 1 |
.equ CS02 = 2 ; Clock Select 2 |
.equ WGM01 = 3 ; Waveform Generation Mode 1 |
.equ COM0A0 = 4 ; Compare match Output Mode 0 |
.equ COM0A1 = 5 ; Compare Match Output Mode 1 |
.equ WGM00 = 6 ; Waveform Generation Mode 0 |
.equ FOC0A = 7 ; Force Output Compare |
; TCNT0 - Timer/Counter0 |
.equ TCNT0_0 = 0 ; |
.equ TCNT0_1 = 1 ; |
.equ TCNT0_2 = 2 ; |
.equ TCNT0_3 = 3 ; |
.equ TCNT0_4 = 4 ; |
.equ TCNT0_5 = 5 ; |
.equ TCNT0_6 = 6 ; |
.equ TCNT0_7 = 7 ; |
; OCR0A - Timer/Counter0 Output Compare Register |
.equ OCR0A0 = 0 ; |
.equ OCR0A1 = 1 ; |
.equ OCR0A2 = 2 ; |
.equ OCR0A3 = 3 ; |
.equ OCR0A4 = 4 ; |
.equ OCR0A5 = 5 ; |
.equ OCR0A6 = 6 ; |
.equ OCR0A7 = 7 ; |
; TIMSK0 - Timer/Counter0 Interrupt Mask Register |
.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable |
.equ OCIE0A = 1 ; Timer/Counter0 Output Compare Match Interrupt Enable |
; TIFR0 - Timer/Counter0 Interrupt Flag register |
.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag |
.equ OCF0A = 1 ; Timer/Counter0 Output Compare Flag 0 |
; GTCCR - General Timer/Control Register |
.equ PSR310 = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0 |
.equ PSR10 = PSR310 ; For compatibility |
.equ PSR0 = PSR310 ; For compatibility |
.equ PSR1 = PSR310 ; For compatibility |
.equ PSR3 = PSR310 ; For compatibility |
.equ TSM = 7 ; Timer/Counter Synchronization Mode |
; ***** TIMER_COUNTER_1 ************** |
; TIMSK1 - Timer/Counter1 Interrupt Mask Register |
.equ TOIE1 = 0 ; Timer/Counter1 Overflow Interrupt Enable |
.equ OCIE1A = 1 ; Timer/Counter1 Output Compare A Match Interrupt Enable |
.equ OCIE1B = 2 ; Timer/Counter1 Output Compare B Match Interrupt Enable |
.equ ICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable |
; TIFR1 - Timer/Counter1 Interrupt Flag register |
.equ TOV1 = 0 ; Timer/Counter1 Overflow Flag |
.equ OCF1A = 1 ; Output Compare Flag 1A |
.equ OCF1B = 2 ; Output Compare Flag 1B |
.equ ICF1 = 5 ; Input Capture Flag 1 |
; TCCR1A - Timer/Counter1 Control Register A |
.equ WGM10 = 0 ; Waveform Generation Mode |
.equ WGM11 = 1 ; Waveform Generation Mode |
.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0 |
.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1 |
.equ COM1A0 = 6 ; Compare Output Mode 1A, bit 0 |
.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1 |
; TCCR1B - Timer/Counter1 Control Register B |
.equ CS10 = 0 ; Prescaler source of Timer/Counter 1 |
.equ CS11 = 1 ; Prescaler source of Timer/Counter 1 |
.equ CS12 = 2 ; Prescaler source of Timer/Counter 1 |
.equ WGM12 = 3 ; Waveform Generation Mode |
.equ WGM13 = 4 ; Waveform Generation Mode |
.equ ICES1 = 6 ; Input Capture 1 Edge Select |
.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler |
; TCCR1C - Timer/Counter 1 Control Register C |
.equ FOC1B = 6 ; Force Output Compare 1B |
.equ FOC1A = 7 ; Force Output Compare 1A |
; ***** TIMER_COUNTER_2 ************** |
; TIMSK2 - Timer/Counter2 Interrupt Mask register |
.equ TOIE2 = 0 ; Timer/Counter2 Overflow Interrupt Enable |
.equ OCIE2A = 1 ; Timer/Counter2 Output Compare Match Interrupt Enable |
; TIFR2 - Timer/Counter2 Interrupt Flag Register |
.equ TOV2 = 0 ; Timer/Counter2 Overflow Flag |
.equ OCF2A = 1 ; Timer/Counter2 Output Compare Flag 2 |
; TCCR2A - Timer/Counter2 Control Register |
.equ CS20 = 0 ; Clock Select bit 0 |
.equ CS21 = 1 ; Clock Select bit 1 |
.equ CS22 = 2 ; Clock Select bit 2 |
.equ WGM21 = 3 ; Waveform Generation Mode |
.equ COM2A0 = 4 ; Compare Output Mode bit 0 |
.equ COM2A1 = 5 ; Compare Output Mode bit 1 |
.equ WGM20 = 6 ; Waveform Generation Mode |
.equ FOC2A = 7 ; Force Output Compare A |
; TCNT2 - Timer/Counter2 |
.equ TCNT2_0 = 0 ; Timer/Counter 2 bit 0 |
.equ TCNT2_1 = 1 ; Timer/Counter 2 bit 1 |
.equ TCNT2_2 = 2 ; Timer/Counter 2 bit 2 |
.equ TCNT2_3 = 3 ; Timer/Counter 2 bit 3 |
.equ TCNT2_4 = 4 ; Timer/Counter 2 bit 4 |
.equ TCNT2_5 = 5 ; Timer/Counter 2 bit 5 |
.equ TCNT2_6 = 6 ; Timer/Counter 2 bit 6 |
.equ TCNT2_7 = 7 ; Timer/Counter 2 bit 7 |
; OCR2A - Timer/Counter2 Output Compare Register |
.equ OCR2A0 = 0 ; Timer/Counter2 Output Compare Register Bit 0 |
.equ OCR2A1 = 1 ; Timer/Counter2 Output Compare Register Bit 1 |
.equ OCR2A2 = 2 ; Timer/Counter2 Output Compare Register Bit 2 |
.equ OCR2A3 = 3 ; Timer/Counter2 Output Compare Register Bit 3 |
.equ OCR2A4 = 4 ; Timer/Counter2 Output Compare Register Bit 4 |
.equ OCR2A5 = 5 ; Timer/Counter2 Output Compare Register Bit 5 |
.equ OCR2A6 = 6 ; Timer/Counter2 Output Compare Register Bit 6 |
.equ OCR2A7 = 7 ; Timer/Counter2 Output Compare Register Bit 7 |
; GTCCR - General Timer/Counter Control Register |
.equ PSR2 = 1 ; Prescaler Reset Timer/Counter2 |
; ASSR - Asynchronous Status Register |
.equ TCR2UB = 0 ; TCR2UB: Timer/Counter Control Register2 Update Busy |
.equ OCR2UB = 1 ; Output Compare Register2 Update Busy |
.equ TCN2UB = 2 ; TCN2UB: Timer/Counter2 Update Busy |
.equ AS2 = 3 ; AS2: Asynchronous Timer/Counter2 |
.equ EXCLK = 4 ; Enable External Clock Interrupt |
; ***** WATCHDOG ********************* |
; WDTCR - Watchdog Timer Control Register |
.equ WDTCSR = WDTCR ; For compatibility |
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 |
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 |
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 |
.equ WDE = 3 ; Watch Dog Enable |
.equ WDCE = 4 ; Watchdog Change Enable |
.equ WDTOE = WDCE ; For compatibility |
; ***** EEPROM *********************** |
; EEDR - EEPROM Data Register |
.equ EEDR0 = 0 ; EEPROM Data Register bit 0 |
.equ EEDR1 = 1 ; EEPROM Data Register bit 1 |
.equ EEDR2 = 2 ; EEPROM Data Register bit 2 |
.equ EEDR3 = 3 ; EEPROM Data Register bit 3 |
.equ EEDR4 = 4 ; EEPROM Data Register bit 4 |
.equ EEDR5 = 5 ; EEPROM Data Register bit 5 |
.equ EEDR6 = 6 ; EEPROM Data Register bit 6 |
.equ EEDR7 = 7 ; EEPROM Data Register bit 7 |
; EECR - EEPROM Control Register |
.equ EERE = 0 ; EEPROM Read Enable |
.equ EEWE = 1 ; EEPROM Write Enable |
.equ EEMWE = 2 ; EEPROM Master Write Enable |
.equ EERIE = 3 ; EEPROM Ready Interrupt Enable |
; ***** SPI ************************** |
; SPDR - SPI Data Register |
.equ SPDR0 = 0 ; SPI Data Register bit 0 |
.equ SPDR1 = 1 ; SPI Data Register bit 1 |
.equ SPDR2 = 2 ; SPI Data Register bit 2 |
.equ SPDR3 = 3 ; SPI Data Register bit 3 |
.equ SPDR4 = 4 ; SPI Data Register bit 4 |
.equ SPDR5 = 5 ; SPI Data Register bit 5 |
.equ SPDR6 = 6 ; SPI Data Register bit 6 |
.equ SPDR7 = 7 ; SPI Data Register bit 7 |
; SPSR - SPI Status Register |
.equ SPI2X = 0 ; Double SPI Speed Bit |
.equ WCOL = 6 ; Write Collision Flag |
.equ SPIF = 7 ; SPI Interrupt Flag |
; SPCR - SPI Control Register |
.equ SPR0 = 0 ; SPI Clock Rate Select 0 |
.equ SPR1 = 1 ; SPI Clock Rate Select 1 |
.equ CPHA = 2 ; Clock Phase |
.equ CPOL = 3 ; Clock polarity |
.equ MSTR = 4 ; Master/Slave Select |
.equ DORD = 5 ; Data Order |
.equ SPE = 6 ; SPI Enable |
.equ SPIE = 7 ; SPI Interrupt Enable |
; ***** PORTA ************************ |
; PORTA - Port A Data Register |
.equ PORTA0 = 0 ; Port A Data Register bit 0 |
.equ PA0 = 0 ; For compatibility |
.equ PORTA1 = 1 ; Port A Data Register bit 1 |
.equ PA1 = 1 ; For compatibility |
.equ PORTA2 = 2 ; Port A Data Register bit 2 |
.equ PA2 = 2 ; For compatibility |
.equ PORTA3 = 3 ; Port A Data Register bit 3 |
.equ PA3 = 3 ; For compatibility |
.equ PORTA4 = 4 ; Port A Data Register bit 4 |
.equ PA4 = 4 ; For compatibility |
.equ PORTA5 = 5 ; Port A Data Register bit 5 |
.equ PA5 = 5 ; For compatibility |
.equ PORTA6 = 6 ; Port A Data Register bit 6 |
.equ PA6 = 6 ; For compatibility |
.equ PORTA7 = 7 ; Port A Data Register bit 7 |
.equ PA7 = 7 ; For compatibility |
; DDRA - Port A Data Direction Register |
.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0 |
.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1 |
.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2 |
.equ DDA3 = 3 ; Data Direction Register, Port A, bit 3 |
.equ DDA4 = 4 ; Data Direction Register, Port A, bit 4 |
.equ DDA5 = 5 ; Data Direction Register, Port A, bit 5 |
.equ DDA6 = 6 ; Data Direction Register, Port A, bit 6 |
.equ DDA7 = 7 ; Data Direction Register, Port A, bit 7 |
; PINA - Port A Input Pins |
.equ PINA0 = 0 ; Input Pins, Port A bit 0 |
.equ PINA1 = 1 ; Input Pins, Port A bit 1 |
.equ PINA2 = 2 ; Input Pins, Port A bit 2 |
.equ PINA3 = 3 ; Input Pins, Port A bit 3 |
.equ PINA4 = 4 ; Input Pins, Port A bit 4 |
.equ PINA5 = 5 ; Input Pins, Port A bit 5 |
.equ PINA6 = 6 ; Input Pins, Port A bit 6 |
.equ PINA7 = 7 ; Input Pins, Port A bit 7 |
; ***** PORTB ************************ |
; PORTB - Port B Data Register |
.equ PORTB0 = 0 ; Port B Data Register bit 0 |
.equ PB0 = 0 ; For compatibility |
.equ PORTB1 = 1 ; Port B Data Register bit 1 |
.equ PB1 = 1 ; For compatibility |
.equ PORTB2 = 2 ; Port B Data Register bit 2 |
.equ PB2 = 2 ; For compatibility |
.equ PORTB3 = 3 ; Port B Data Register bit 3 |
.equ PB3 = 3 ; For compatibility |
.equ PORTB4 = 4 ; Port B Data Register bit 4 |
.equ PB4 = 4 ; For compatibility |
.equ PORTB5 = 5 ; Port B Data Register bit 5 |
.equ PB5 = 5 ; For compatibility |
.equ PORTB6 = 6 ; Port B Data Register bit 6 |
.equ PB6 = 6 ; For compatibility |
.equ PORTB7 = 7 ; Port B Data Register bit 7 |
.equ PB7 = 7 ; For compatibility |
; DDRB - Port B Data Direction Register |
.equ DDB0 = 0 ; Port B Data Direction Register bit 0 |
.equ DDB1 = 1 ; Port B Data Direction Register bit 1 |
.equ DDB2 = 2 ; Port B Data Direction Register bit 2 |
.equ DDB3 = 3 ; Port B Data Direction Register bit 3 |
.equ DDB4 = 4 ; Port B Data Direction Register bit 4 |
.equ DDB5 = 5 ; Port B Data Direction Register bit 5 |
.equ DDB6 = 6 ; Port B Data Direction Register bit 6 |
.equ DDB7 = 7 ; Port B Data Direction Register bit 7 |
; PINB - Port B Input Pins |
.equ PINB0 = 0 ; Port B Input Pins bit 0 |
.equ PINB1 = 1 ; Port B Input Pins bit 1 |
.equ PINB2 = 2 ; Port B Input Pins bit 2 |
.equ PINB3 = 3 ; Port B Input Pins bit 3 |
.equ PINB4 = 4 ; Port B Input Pins bit 4 |
.equ PINB5 = 5 ; Port B Input Pins bit 5 |
.equ PINB6 = 6 ; Port B Input Pins bit 6 |
.equ PINB7 = 7 ; Port B Input Pins bit 7 |
; ***** PORTC ************************ |
; PORTC - Port C Data Register |
.equ PORTC0 = 0 ; Port C Data Register bit 0 |
.equ PC0 = 0 ; For compatibility |
.equ PORTC1 = 1 ; Port C Data Register bit 1 |
.equ PC1 = 1 ; For compatibility |
.equ PORTC2 = 2 ; Port C Data Register bit 2 |
.equ PC2 = 2 ; For compatibility |
.equ PORTC3 = 3 ; Port C Data Register bit 3 |
.equ PC3 = 3 ; For compatibility |
.equ PORTC4 = 4 ; Port C Data Register bit 4 |
.equ PC4 = 4 ; For compatibility |
.equ PORTC5 = 5 ; Port C Data Register bit 5 |
.equ PC5 = 5 ; For compatibility |
.equ PORTC6 = 6 ; Port C Data Register bit 6 |
.equ PC6 = 6 ; For compatibility |
.equ PORTC7 = 7 ; Port C Data Register bit 7 |
.equ PC7 = 7 ; For compatibility |
; DDRC - Port C Data Direction Register |
.equ DDC0 = 0 ; Port C Data Direction Register bit 0 |
.equ DDC1 = 1 ; Port C Data Direction Register bit 1 |
.equ DDC2 = 2 ; Port C Data Direction Register bit 2 |
.equ DDC3 = 3 ; Port C Data Direction Register bit 3 |
.equ DDC4 = 4 ; Port C Data Direction Register bit 4 |
.equ DDC5 = 5 ; Port C Data Direction Register bit 5 |
.equ DDC6 = 6 ; Port C Data Direction Register bit 6 |
.equ DDC7 = 7 ; Port C Data Direction Register bit 7 |
; PINC - Port C Input Pins |
.equ PINC0 = 0 ; Port C Input Pins bit 0 |
.equ PINC1 = 1 ; Port C Input Pins bit 1 |
.equ PINC2 = 2 ; Port C Input Pins bit 2 |
.equ PINC3 = 3 ; Port C Input Pins bit 3 |
.equ PINC4 = 4 ; Port C Input Pins bit 4 |
.equ PINC5 = 5 ; Port C Input Pins bit 5 |
.equ PINC6 = 6 ; Port C Input Pins bit 6 |
.equ PINC7 = 7 ; Port C Input Pins bit 7 |
; ***** PORTD ************************ |
; PORTD - Port D Data Register |
.equ PORTD0 = 0 ; Port D Data Register bit 0 |
.equ PD0 = 0 ; For compatibility |
.equ PORTD1 = 1 ; Port D Data Register bit 1 |
.equ PD1 = 1 ; For compatibility |
.equ PORTD2 = 2 ; Port D Data Register bit 2 |
.equ PD2 = 2 ; For compatibility |
.equ PORTD3 = 3 ; Port D Data Register bit 3 |
.equ PD3 = 3 ; For compatibility |
.equ PORTD4 = 4 ; Port D Data Register bit 4 |
.equ PD4 = 4 ; For compatibility |
.equ PORTD5 = 5 ; Port D Data Register bit 5 |
.equ PD5 = 5 ; For compatibility |
.equ PORTD6 = 6 ; Port D Data Register bit 6 |
.equ PD6 = 6 ; For compatibility |
.equ PORTD7 = 7 ; Port D Data Register bit 7 |
.equ PD7 = 7 ; For compatibility |
; DDRD - Port D Data Direction Register |
.equ DDD0 = 0 ; Port D Data Direction Register bit 0 |
.equ DDD1 = 1 ; Port D Data Direction Register bit 1 |
.equ DDD2 = 2 ; Port D Data Direction Register bit 2 |
.equ DDD3 = 3 ; Port D Data Direction Register bit 3 |
.equ DDD4 = 4 ; Port D Data Direction Register bit 4 |
.equ DDD5 = 5 ; Port D Data Direction Register bit 5 |
.equ DDD6 = 6 ; Port D Data Direction Register bit 6 |
.equ DDD7 = 7 ; Port D Data Direction Register bit 7 |
; PIND - Port D Input Pins |
.equ PIND0 = 0 ; Port D Input Pins bit 0 |
.equ PIND1 = 1 ; Port D Input Pins bit 1 |
.equ PIND2 = 2 ; Port D Input Pins bit 2 |
.equ PIND3 = 3 ; Port D Input Pins bit 3 |
.equ PIND4 = 4 ; Port D Input Pins bit 4 |
.equ PIND5 = 5 ; Port D Input Pins bit 5 |
.equ PIND6 = 6 ; Port D Input Pins bit 6 |
.equ PIND7 = 7 ; Port D Input Pins bit 7 |
; ***** ANALOG_COMPARATOR ************ |
; ADCSRB - ADC Control and Status Register B |
.equ ACME = 6 ; Analog Comparator Multiplexer Enable |
; ACSR - Analog Comparator Control And Status Register |
.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 |
.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 |
.equ ACIC = 2 ; Analog Comparator Input Capture Enable |
.equ ACIE = 3 ; Analog Comparator Interrupt Enable |
.equ ACI = 4 ; Analog Comparator Interrupt Flag |
.equ ACO = 5 ; Analog Compare Output |
.equ ACBG = 6 ; Analog Comparator Bandgap Select |
.equ ACD = 7 ; Analog Comparator Disable |
; DIDR1 - Digital Input Disable Register 1 |
.equ AIN0D = 0 ; AIN0 Digital Input Disable |
.equ AIN1D = 1 ; AIN1 Digital Input Disable |
; ***** PORTE ************************ |
; PORTE - Data Register, Port E |
.equ PORTE0 = 0 ; |
.equ PE0 = 0 ; For compatibility |
.equ PORTE1 = 1 ; |
.equ PE1 = 1 ; For compatibility |
.equ PORTE2 = 2 ; |
.equ PE2 = 2 ; For compatibility |
.equ PORTE3 = 3 ; |
.equ PE3 = 3 ; For compatibility |
.equ PORTE4 = 4 ; |
.equ PE4 = 4 ; For compatibility |
.equ PORTE5 = 5 ; |
.equ PE5 = 5 ; For compatibility |
.equ PORTE6 = 6 ; |
.equ PE6 = 6 ; For compatibility |
.equ PORTE7 = 7 ; |
.equ PE7 = 7 ; For compatibility |
; DDRE - Data Direction Register, Port E |
.equ DDE0 = 0 ; |
.equ DDE1 = 1 ; |
.equ DDE2 = 2 ; |
.equ DDE3 = 3 ; |
.equ DDE4 = 4 ; |
.equ DDE5 = 5 ; |
.equ DDE6 = 6 ; |
.equ DDE7 = 7 ; |
; PINE - Input Pins, Port E |
.equ PINE0 = 0 ; |
.equ PINE1 = 1 ; |
.equ PINE2 = 2 ; |
.equ PINE3 = 3 ; |
.equ PINE4 = 4 ; |
.equ PINE5 = 5 ; |
.equ PINE6 = 6 ; |
.equ PINE7 = 7 ; |
; ***** PORTF ************************ |
; PORTF - Data Register, Port F |
.equ PORTF0 = 0 ; |
.equ PF0 = 0 ; For compatibility |
.equ PORTF1 = 1 ; |
.equ PF1 = 1 ; For compatibility |
.equ PORTF2 = 2 ; |
.equ PF2 = 2 ; For compatibility |
.equ PORTF3 = 3 ; |
.equ PF3 = 3 ; For compatibility |
.equ PORTF4 = 4 ; |
.equ PF4 = 4 ; For compatibility |
.equ PORTF5 = 5 ; |
.equ PF5 = 5 ; For compatibility |
.equ PORTF6 = 6 ; |
.equ PF6 = 6 ; For compatibility |
.equ PORTF7 = 7 ; |
.equ PF7 = 7 ; For compatibility |
; DDRF - Data Direction Register, Port F |
.equ DDF0 = 0 ; |
.equ DDF1 = 1 ; |
.equ DDF2 = 2 ; |
.equ DDF3 = 3 ; |
.equ DDF4 = 4 ; |
.equ DDF5 = 5 ; |
.equ DDF6 = 6 ; |
.equ DDF7 = 7 ; |
; PINF - Input Pins, Port F |
.equ PINF0 = 0 ; |
.equ PINF1 = 1 ; |
.equ PINF2 = 2 ; |
.equ PINF3 = 3 ; |
.equ PINF4 = 4 ; |
.equ PINF5 = 5 ; |
.equ PINF6 = 6 ; |
.equ PINF7 = 7 ; |
; ***** PORTG ************************ |
; PORTG - Port G Data Register |
.equ PORTG0 = 0 ; |
.equ PG0 = 0 ; For compatibility |
.equ PORTG1 = 1 ; |
.equ PG1 = 1 ; For compatibility |
.equ PORTG2 = 2 ; |
.equ PG2 = 2 ; For compatibility |
.equ PORTG3 = 3 ; |
.equ PG3 = 3 ; For compatibility |
.equ PORTG4 = 4 ; |
.equ PG4 = 4 ; For compatibility |
; DDRG - Port G Data Direction Register |
.equ DDG0 = 0 ; |
.equ DDG1 = 1 ; |
.equ DDG2 = 2 ; |
.equ DDG3 = 3 ; |
.equ DDG4 = 4 ; |
; PING - Port G Input Pins |
.equ PING0 = 0 ; |
.equ PING1 = 1 ; |
.equ PING2 = 2 ; |
.equ PING3 = 3 ; |
.equ PING4 = 4 ; |
.equ PING5 = 5 ; |
; ***** JTAG ************************* |
; OCDR - On-Chip Debug Related Register in I/O Memory |
.equ OCDR0 = 0 ; On-Chip Debug Register Bit 0 |
.equ OCDR1 = 1 ; On-Chip Debug Register Bit 1 |
.equ OCDR2 = 2 ; On-Chip Debug Register Bit 2 |
.equ OCDR3 = 3 ; On-Chip Debug Register Bit 3 |
.equ OCDR4 = 4 ; On-Chip Debug Register Bit 4 |
.equ OCDR5 = 5 ; On-Chip Debug Register Bit 5 |
.equ OCDR6 = 6 ; On-Chip Debug Register Bit 6 |
.equ OCDR7 = 7 ; On-Chip Debug Register Bit 7 |
.equ IDRD = OCDR7 ; For compatibility |
; MCUCR - MCU Control Register |
.equ JTD = 7 ; JTAG Interface Disable |
; MCUSR - MCU Status Register |
.equ JTRF = 4 ; JTAG Reset Flag |
; ***** MISC ************************* |
; LCDCRA - LCD Control and Status Register A |
.equ LCDBL = 0 ; LCD Blanking |
.equ LCDIE = 3 ; LCD Interrupt Enable |
.equ LCDIF = 4 ; LCD Interrupt Flag |
.equ LCDAB = 6 ; LCD A or B waveform |
.equ LCDEN = 7 ; LCD Enable |
; LCDCRB - LCD Control and Status Register B |
.equ LCDPM0 = 0 ; LCD Port Mask 0 |
.equ LCDPM1 = 1 ; LCD Port Mask 1 |
.equ LCDPM2 = 2 ; LCD Port Mask 2 |
.equ LCDPM3 = 3 ; LCD Port Mask 3 |
.equ LCDMUX0 = 4 ; LCD Mux Select 0 |
.equ LCDMUX1 = 5 ; LCD Mux Select 1 |
.equ LCD2B = 6 ; LCD 1/2 Bias Select |
.equ LCDCS = 7 ; LCD CLock Select |
; LCDFRR - LCD Frame Rate Register |
.equ LCDCD0 = 0 ; LCD Clock Divider 0 |
.equ LCDCD1 = 1 ; LCD Clock Divider 1 |
.equ LCDCD2 = 2 ; LCD Clock Divider 2 |
.equ LCDPS0 = 4 ; LCD Prescaler Select 0 |
.equ LCDPS1 = 5 ; LCD Prescaler Select 1 |
.equ LCDPS2 = 6 ; LCD Prescaler Select 2 |
; LCDCCR - LCD Contrast Control Register |
.equ LCDCC0 = 0 ; LCD Contrast Control 0 |
.equ LCDCC1 = 1 ; LCD Contrast Control 1 |
.equ LCDCC2 = 2 ; LCD Contrast Control 2 |
.equ LCDCC3 = 3 ; LCD Contrast Control 3 |
.equ LCDDC0 = 5 ; LCD Display Configuration 0 |
.equ LCDDC1 = 6 ; LCD Display Configuration 1 |
.equ LCDDC2 = 7 ; LCD Display Configuration 2 |
; LCDDR19 - LCD Data Register 19 |
.equ SEG332 = 0 ; |
.equ SEG333 = 1 ; |
.equ SEG334 = 2 ; |
.equ SEG335 = 3 ; |
.equ SEG336 = 4 ; |
.equ SEG337 = 5 ; |
.equ SEG338 = 6 ; |
.equ SEG339 = 7 ; |
; LCDDR18 - LCD Data Register 18 |
.equ SEG324 = 0 ; |
.equ SEG325 = 1 ; |
.equ SEG326 = 2 ; |
.equ SEG327 = 3 ; |
.equ SEG328 = 4 ; |
.equ SEG329 = 5 ; |
.equ SEG330 = 6 ; |
.equ SEG331 = 7 ; |
; LCDDR17 - LCD Data Register 17 |
.equ SEG316 = 0 ; |
.equ SEG317 = 1 ; |
.equ SEG318 = 2 ; |
.equ SEG319 = 3 ; |
.equ SEG320 = 4 ; |
.equ SEG321 = 5 ; |
.equ SEG322 = 6 ; |
.equ SEG323 = 7 ; |
; LCDDR16 - LCD Data Register 16 |
.equ SEG308 = 0 ; |
.equ SEG309 = 1 ; |
.equ SEG310 = 2 ; |
.equ SEG311 = 3 ; |
.equ SEG312 = 4 ; |
.equ SEG313 = 5 ; |
.equ SEG314 = 6 ; |
.equ SEG315 = 7 ; |
; LCDDR15 - LCD Data Register 15 |
.equ SEG300 = 0 ; |
.equ SEG301 = 1 ; |
.equ SEG302 = 2 ; |
.equ SEG303 = 3 ; |
.equ SEG304 = 4 ; |
.equ SEG305 = 5 ; |
.equ SEG306 = 6 ; |
.equ SEG307 = 7 ; |
; LCDDR14 - LCD Data Register 14 |
.equ SEG232 = 0 ; |
.equ SEG233 = 1 ; |
.equ SEG234 = 2 ; |
.equ SEG235 = 3 ; |
.equ SEG236 = 4 ; |
.equ SEG237 = 5 ; |
.equ SEG238 = 6 ; |
.equ SEG239 = 7 ; |
; LCDDR13 - LCD Data Register 13 |
.equ SEG224 = 0 ; |
.equ SEG225 = 1 ; |
.equ SEG226 = 2 ; |
.equ SEG227 = 3 ; |
.equ SEG228 = 4 ; |
.equ SEG229 = 5 ; |
.equ SEG230 = 6 ; |
.equ SEG231 = 7 ; |
; LCDDR12 - LCD Data Register 12 |
.equ SEG216 = 0 ; |
.equ SEG217 = 1 ; |
.equ SEG218 = 2 ; |
.equ SEG219 = 3 ; |
.equ SEG220 = 4 ; |
.equ SEG221 = 5 ; |
.equ SEG222 = 6 ; |
.equ SEG223 = 7 ; |
; LCDDR11 - LCD Data Register 11 |
.equ SEG208 = 0 ; |
.equ SEG209 = 1 ; |
.equ SEG210 = 2 ; |
.equ SEG211 = 3 ; |
.equ SEG212 = 4 ; |
.equ SEG213 = 5 ; |
.equ SEG214 = 6 ; |
.equ SEG215 = 7 ; |
; LCDDR10 - LCD Data Register 10 |
.equ SEG200 = 0 ; |
.equ SEG201 = 1 ; |
.equ SEG202 = 2 ; |
.equ SEG203 = 3 ; |
.equ SEG204 = 4 ; |
.equ SEG205 = 5 ; |
.equ SEG206 = 6 ; |
.equ SEG207 = 7 ; |
; LCDDR9 - LCD Data Register 9 |
.equ SEG132 = 0 ; |
.equ SEG133 = 1 ; |
.equ SEG134 = 2 ; |
.equ SEG135 = 3 ; |
.equ SEG136 = 4 ; |
.equ SEG137 = 5 ; |
.equ SEG138 = 6 ; |
.equ SEG139 = 7 ; |
; LCDDR8 - LCD Data Register 8 |
.equ SEG124 = 0 ; |
.equ SEG125 = 1 ; |
.equ SEG126 = 2 ; |
.equ SEG127 = 3 ; |
.equ SEG128 = 4 ; |
.equ SEG129 = 5 ; |
.equ SEG130 = 6 ; |
.equ SEG131 = 7 ; |
; LCDDR7 - LCD Data Register 7 |
.equ SEG116 = 0 ; |
.equ SEG117 = 1 ; |
.equ SEG118 = 2 ; |
.equ SEG119 = 3 ; |
.equ SEG120 = 4 ; |
.equ SEG121 = 5 ; |
.equ SEG122 = 6 ; |
.equ SEG123 = 7 ; |
; LCDDR6 - LCD Data Register 6 |
.equ SEG108 = 0 ; |
.equ SEG109 = 1 ; |
.equ SEG110 = 2 ; |
.equ SEG111 = 3 ; |
.equ SEG112 = 4 ; |
.equ SEG113 = 5 ; |
.equ SEG114 = 6 ; |
.equ SEG115 = 7 ; |
; LCDDR5 - LCD Data Register 5 |
.equ SEG100 = 0 ; |
.equ SEG101 = 1 ; |
.equ SEG102 = 2 ; |
.equ SEG103 = 3 ; |
.equ SEG104 = 4 ; |
.equ SEG105 = 5 ; |
.equ SEG106 = 6 ; |
.equ SEG107 = 7 ; |
; LCDDR4 - LCD Data Register 4 |
.equ SEG032 = 0 ; |
.equ SEG033 = 1 ; |
.equ SEG034 = 2 ; |
.equ SEG035 = 3 ; |
.equ SEG036 = 4 ; |
.equ SEG037 = 5 ; |
.equ SEG038 = 6 ; |
.equ SEG039 = 7 ; |
; LCDDR3 - LCD Data Register 3 |
.equ SEG024 = 0 ; |
.equ SEG025 = 1 ; |
.equ SEG026 = 2 ; |
.equ SEG027 = 3 ; |
.equ SEG028 = 4 ; |
.equ SEG029 = 5 ; |
.equ SEG030 = 6 ; |
.equ SEG031 = 7 ; |
; LCDDR2 - LCD Data Register 2 |
.equ SEG016 = 0 ; |
.equ SEG017 = 1 ; |
.equ SEG018 = 2 ; |
.equ SEG019 = 3 ; |
.equ SEG020 = 4 ; |
.equ SEG021 = 5 ; |
.equ SEG022 = 6 ; |
.equ SEG023 = 7 ; |
; LCDDR1 - LCD Data Register 1 |
.equ SEG008 = 0 ; |
.equ SEG009 = 1 ; |
.equ SEG010 = 2 ; |
.equ SEG011 = 3 ; |
.equ SEG012 = 4 ; |
.equ SEG013 = 5 ; |
.equ SEG014 = 6 ; |
.equ SEG015 = 7 ; |
; LCDDR0 - LCD Data Register 0 |
.equ SEG000 = 0 ; |
.equ SEG001 = 1 ; |
.equ SEG002 = 2 ; |
.equ SEG003 = 3 ; |
.equ SEG004 = 4 ; |
.equ SEG005 = 5 ; |
.equ SEG006 = 6 ; |
.equ SEG007 = 7 ; |
; ***** EXTERNAL_INTERRUPT *********** |
; EICRA - External Interrupt Control Register A |
.equ ISC00 = 0 ; External Interrupt Sense Control 0 Bit 0 |
.equ ISC01 = 1 ; External Interrupt Sense Control 0 Bit 1 |
; EIMSK - External Interrupt Mask Register |
.equ INT0 = 0 ; External Interrupt Request 0 Enable |
.equ PCIE0 = 4 ; Pin Change Interrupt Enable 0 |
.equ PCIE1 = 5 ; Pin Change Interrupt Enable 1 |
.equ PCIE2 = 6 ; Pin Change Interrupt Enable 2 |
.equ PCIE3 = 7 ; Pin Change Interrupt Enable 3 |
; EIFR - External Interrupt Flag Register |
.equ INTF0 = 0 ; External Interrupt Flag 0 |
.equ PCIF0 = 4 ; Pin Change Interrupt Flag 0 |
.equ PCIF1 = 5 ; Pin Change Interrupt Flag 1 |
.equ PCIF2 = 6 ; Pin Change Interrupt Flag 2 |
.equ PCIF3 = 7 ; Pin Change Interrupt Flag 3 |
; PCMSK3 - Pin Change Mask Register 3 |
.equ PCINT24 = 0 ; Pin Change Enable Mask 24 |
.equ PCINT25 = 1 ; Pin Change Enable Mask 25 |
.equ PCINT26 = 2 ; Pin Change Enable Mask 26 |
.equ PCINT27 = 3 ; Pin Change Enable Mask 27 |
.equ PCINT28 = 4 ; Pin Change Enable Mask 28 |
.equ PCINT29 = 5 ; Pin Change Enable Mask 29 |
.equ PCINT30 = 6 ; Pin Change Enable Mask 30 |
; PCMSK2 - Pin Change Mask Register 2 |
.equ PCINT16 = 0 ; Pin Change Enable Mask 16 |
.equ PCINT17 = 1 ; Pin Change Enable Mask 17 |
.equ PCINT18 = 2 ; Pin Change Enable Mask 18 |
.equ PCINT19 = 3 ; Pin Change Enable Mask 19 |
.equ PCINT20 = 4 ; Pin Change Enable Mask 20 |
.equ PCINT21 = 5 ; Pin Change Enable Mask 21 |
.equ PCINT22 = 6 ; Pin Change Enable Mask 22 |
.equ PCINT23 = 7 ; Pin Change Enable Mask 23 |
; PCMSK1 - Pin Change Mask Register 1 |
.equ PCINT8 = 0 ; Pin Change Enable Mask 8 |
.equ PCINT9 = 1 ; Pin Change Enable Mask 9 |
.equ PCINT10 = 2 ; Pin Change Enable Mask 10 |
.equ PCINT11 = 3 ; Pin Change Enable Mask 11 |
.equ PCINT12 = 4 ; Pin Change Enable Mask 12 |
.equ PCINT13 = 5 ; Pin Change Enable Mask 13 |
.equ PCINT14 = 6 ; Pin Change Enable Mask 14 |
.equ PCINT15 = 7 ; Pin Change Enable Mask 15 |
; PCMSK0 - Pin Change Mask Register 0 |
.equ PCINT0 = 0 ; Pin Change Enable Mask 0 |
.equ PCINT1 = 1 ; Pin Change Enable Mask 1 |
.equ PCINT2 = 2 ; Pin Change Enable Mask 2 |
.equ PCINT3 = 3 ; Pin Change Enable Mask 3 |
.equ PCINT4 = 4 ; Pin Change Enable Mask 4 |
.equ PCINT5 = 5 ; Pin Change Enable Mask 5 |
.equ PCINT6 = 6 ; Pin Change Enable Mask 6 |
.equ PCINT7 = 7 ; Pin Change Enable Mask 7 |
; ***** CPU ************************** |
; SREG - Status Register |
.equ SREG_C = 0 ; Carry Flag |
.equ SREG_Z = 1 ; Zero Flag |
.equ SREG_N = 2 ; Negative Flag |
.equ SREG_V = 3 ; Two's Complement Overflow Flag |
.equ SREG_S = 4 ; Sign Bit |
.equ SREG_H = 5 ; Half Carry Flag |
.equ SREG_T = 6 ; Bit Copy Storage |
.equ SREG_I = 7 ; Global Interrupt Enable |
; MCUCR - MCU Control Register |
.equ IVCE = 0 ; Interrupt Vector Change Enable |
.equ IVSEL = 1 ; Interrupt Vector Select |
.equ PUD = 4 ; Pull-up disable |
; MCUSR - MCU Status Register |
.equ PORF = 0 ; Power-on reset flag |
.equ EXTRF = 1 ; External Reset Flag |
.equ BORF = 2 ; Brown-out Reset Flag |
.equ WDRF = 3 ; Watchdog Reset Flag |
;.equ JTRF = 4 ; JTAG Reset Flag |
; OSCCAL - Oscillator Calibration Value |
.equ CAL0 = 0 ; Oscillator Calibration Value Bit0 |
.equ CAL1 = 1 ; Oscillator Calibration Value Bit1 |
.equ CAL2 = 2 ; Oscillator Calibration Value Bit2 |
.equ CAL3 = 3 ; Oscillator Calibration Value Bit3 |
.equ CAL4 = 4 ; Oscillator Calibration Value Bit4 |
.equ CAL5 = 5 ; Oscillator Calibration Value Bit5 |
.equ CAL6 = 6 ; Oscillator Calibration Value Bit6 |
.equ CAL7 = 7 ; Oscillator Calibration Value Bit7 |
; CLKPR - Clock Prescale Register |
.equ CLKPS0 = 0 ; Clock Prescaler Select Bit 0 |
.equ CLKPS1 = 1 ; Clock Prescaler Select Bit 1 |
.equ CLKPS2 = 2 ; Clock Prescaler Select Bit 2 |
.equ CLKPS3 = 3 ; Clock Prescaler Select Bit 3 |
.equ CLKPCE = 7 ; Clock Prescaler Change Enable |
; PRR - Power Reduction Register |
.equ PRADC = 0 ; Power Reduction ADC |
.equ PRUSART0 = 1 ; Power Reduction USART |
.equ PRSPI = 2 ; Power Reduction Serial Peripheral Interface |
.equ PRTIM1 = 3 ; Power Reduction Timer/Counter1 |
.equ PRLCD = 4 ; Power Reduction LCD |
; SMCR - Sleep Mode Control Register |
.equ SE = 0 ; Sleep Enable |
.equ SM0 = 1 ; Sleep Mode Select bit 0 |
.equ SM1 = 2 ; Sleep Mode Select bit 1 |
.equ SM2 = 3 ; Sleep Mode Select bit 2 |
; GPIOR2 - General Purpose IO Register 2 |
.equ GPIOR20 = 0 ; General Purpose IO Register 2 bit 0 |
.equ GPIOR21 = 1 ; General Purpose IO Register 2 bit 1 |
.equ GPIOR22 = 2 ; General Purpose IO Register 2 bit 2 |
.equ GPIOR23 = 3 ; General Purpose IO Register 2 bit 3 |
.equ GPIOR24 = 4 ; General Purpose IO Register 2 bit 4 |
.equ GPIOR25 = 5 ; General Purpose IO Register 2 bit 5 |
.equ GPIOR26 = 6 ; General Purpose IO Register 2 bit 6 |
.equ GPIOR27 = 7 ; General Purpose IO Register 2 bit 7 |
; GPIOR1 - General Purpose IO Register 1 |
.equ GPIOR10 = 0 ; General Purpose IO Register 1 bit 0 |
.equ GPIOR11 = 1 ; General Purpose IO Register 1 bit 1 |
.equ GPIOR12 = 2 ; General Purpose IO Register 1 bit 2 |
.equ GPIOR13 = 3 ; General Purpose IO Register 1 bit 3 |
.equ GPIOR14 = 4 ; General Purpose IO Register 1 bit 4 |
.equ GPIOR15 = 5 ; General Purpose IO Register 1 bit 5 |
.equ GPIOR16 = 6 ; General Purpose IO Register 1 bit 6 |
.equ GPIOR17 = 7 ; General Purpose IO Register 1 bit 7 |
; GPIOR0 - General Purpose IO Register 0 |
.equ GPIOR00 = 0 ; General Purpose IO Register 0 bit 0 |
.equ GPIOR01 = 1 ; General Purpose IO Register 0 bit 1 |
.equ GPIOR02 = 2 ; General Purpose IO Register 0 bit 2 |
.equ GPIOR03 = 3 ; General Purpose IO Register 0 bit 3 |
.equ GPIOR04 = 4 ; General Purpose IO Register 0 bit 4 |
.equ GPIOR05 = 5 ; General Purpose IO Register 0 bit 5 |
.equ GPIOR06 = 6 ; General Purpose IO Register 0 bit 6 |
.equ GPIOR07 = 7 ; General Purpose IO Register 0 bit 7 |
; ***** USI ************************** |
; USIDR - USI Data Register |
.equ USIDR0 = 0 ; USI Data Register bit 0 |
.equ USIDR1 = 1 ; USI Data Register bit 1 |
.equ USIDR2 = 2 ; USI Data Register bit 2 |
.equ USIDR3 = 3 ; USI Data Register bit 3 |
.equ USIDR4 = 4 ; USI Data Register bit 4 |
.equ USIDR5 = 5 ; USI Data Register bit 5 |
.equ USIDR6 = 6 ; USI Data Register bit 6 |
.equ USIDR7 = 7 ; USI Data Register bit 7 |
; USISR - USI Status Register |
.equ USICNT0 = 0 ; USI Counter Value Bit 0 |
.equ USICNT1 = 1 ; USI Counter Value Bit 1 |
.equ USICNT2 = 2 ; USI Counter Value Bit 2 |
.equ USICNT3 = 3 ; USI Counter Value Bit 3 |
.equ USIDC = 4 ; Data Output Collision |
.equ USIPF = 5 ; Stop Condition Flag |
.equ USIOIF = 6 ; Counter Overflow Interrupt Flag |
.equ USISIF = 7 ; Start Condition Interrupt Flag |
; USICR - USI Control Register |
.equ USITC = 0 ; Toggle Clock Port Pin |
.equ USICLK = 1 ; Clock Strobe |
.equ USICS0 = 2 ; USI Clock Source Select Bit 0 |
.equ USICS1 = 3 ; USI Clock Source Select Bit 1 |
.equ USIWM0 = 4 ; USI Wire Mode Bit 0 |
.equ USIWM1 = 5 ; USI Wire Mode Bit 1 |
.equ USIOIE = 6 ; Counter Overflow Interrupt Enable |
.equ USISIE = 7 ; Start Condition Interrupt Enable |
; ***** AD_CONVERTER ***************** |
; ADMUX - The ADC multiplexer Selection Register |
.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits |
.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits |
.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits |
.equ MUX3 = 3 ; Analog Channel and Gain Selection Bits |
.equ MUX4 = 4 ; Analog Channel and Gain Selection Bits |
.equ ADLAR = 5 ; Left Adjust Result |
.equ REFS0 = 6 ; Reference Selection Bit 0 |
.equ REFS1 = 7 ; Reference Selection Bit 1 |
; ADCSRA - The ADC Control and Status register |
.equ ADPS0 = 0 ; ADC Prescaler Select Bits |
.equ ADPS1 = 1 ; ADC Prescaler Select Bits |
.equ ADPS2 = 2 ; ADC Prescaler Select Bits |
.equ ADIE = 3 ; ADC Interrupt Enable |
.equ ADIF = 4 ; ADC Interrupt Flag |
.equ ADATE = 5 ; ADC Auto Trigger Enable |
.equ ADSC = 6 ; ADC Start Conversion |
.equ ADEN = 7 ; ADC Enable |
; ADCH - ADC Data Register High Byte |
.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0 |
.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1 |
.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2 |
.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3 |
.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4 |
.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5 |
.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6 |
.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7 |
; ADCL - ADC Data Register Low Byte |
.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0 |
.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1 |
.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2 |
.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3 |
.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4 |
.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5 |
.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6 |
.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7 |
; ADCSRB - ADC Control and Status Register B |
.equ ADTS0 = 0 ; ADC Auto Trigger Source 0 |
.equ ADTS1 = 1 ; ADC Auto Trigger Source 1 |
.equ ADTS2 = 2 ; ADC Auto Trigger Source 2 |
; DIDR0 - Digital Input Disable Register 0 |
.equ ADC0D = 0 ; ADC0 Digital input Disable |
.equ ADC1D = 1 ; ADC1 Digital input Disable |
.equ ADC2D = 2 ; ADC2 Digital input Disable |
.equ ADC3D = 3 ; ADC3 Digital input Disable |
.equ ADC4D = 4 ; ADC4 Digital input Disable |
.equ ADC5D = 5 ; ADC5 Digital input Disable |
.equ ADC6D = 6 ; ADC6 Digital input Disable |
.equ ADC7D = 7 ; ADC7 Digital input Disable |
; ***** BOOT_LOAD ******************** |
; SPMCSR - Store Program Memory Control Register |
.equ SPMCR = SPMCSR ; For compatibility |
.equ SPMEN = 0 ; Store Program Memory Enable |
.equ PGERS = 1 ; Page Erase |
.equ PGWRT = 2 ; Page Write |
.equ BLBSET = 3 ; Boot Lock Bit Set |
.equ RWWSRE = 4 ; Read While Write section read enable |
.equ ASRE = RWWSRE ; For compatibility |
.equ RWWSB = 6 ; Read While Write Section Busy |
.equ ASB = RWWSB ; For compatibility |
.equ SPMIE = 7 ; SPM Interrupt Enable |
; ***** USART0 *********************** |
; UDR - USART I/O Data Register |
.equ UDR0 = UDR ; For compatibility |
.equ UDR00 = 0 ; USART I/O Data Register bit 0 |
.equ UDR01 = 1 ; USART I/O Data Register bit 1 |
.equ UDR02 = 2 ; USART I/O Data Register bit 2 |
.equ UDR03 = 3 ; USART I/O Data Register bit 3 |
.equ UDR04 = 4 ; USART I/O Data Register bit 4 |
.equ UDR05 = 5 ; USART I/O Data Register bit 5 |
.equ UDR06 = 6 ; USART I/O Data Register bit 6 |
.equ UDR07 = 7 ; USART I/O Data Register bit 7 |
; UCSRA - USART Control and Status Register A |
.equ UCSR0A = UCSRA ; For compatibility |
.equ USR = UCSRA ; For compatibility |
.equ MPCM = 0 ; Multi-processor Communication Mode |
.equ MPCM0 = MPCM ; For compatibility |
.equ U2X = 1 ; Double the USART Transmission Speed |
.equ U2X0 = U2X ; For compatibility |
.equ UPE = 2 ; USART Parity Error |
.equ UPE0 = UPE ; For compatibility |
.equ DOR = 3 ; Data OverRun |
.equ DOR0 = DOR ; For compatibility |
.equ FE = 4 ; Framing Error |
.equ FE0 = FE ; For compatibility |
.equ UDRE = 5 ; USART Data Register Empty |
.equ UDRE0 = UDRE ; For compatibility |
.equ TXC = 6 ; USART Transmit Complete |
.equ TXC0 = TXC ; For compatibility |
.equ RXC = 7 ; USART Receive Complete |
.equ RXC0 = RXC ; For compatibility |
; UCSRB - USART Control and Status Register B |
.equ UCSR0B = UCSRB ; For compatibility |
.equ UCR = UCSRB ; For compatibility |
.equ TXB8 = 0 ; Transmit Data Bit 8 |
.equ TXB80 = TXB8 ; For compatibility |
.equ RXB8 = 1 ; Receive Data Bit 8 |
.equ RXB80 = RXB8 ; For compatibility |
.equ UCSZ2 = 2 ; Character Size |
.equ UCSZ02 = UCSZ2 ; For compatibility |
.equ TXEN = 3 ; Transmitter Enable |
.equ TXEN0 = TXEN ; For compatibility |
.equ RXEN = 4 ; Receiver Enable |
.equ RXEN0 = RXEN ; For compatibility |
.equ UDRIE = 5 ; USART Data Register Empty Interrupt Enable |
.equ UDRIE0 = UDRIE ; For compatibility |
.equ TXCIE = 6 ; TX Complete Interrupt Enable |
.equ TXCIE0 = TXCIE ; For compatibility |
.equ RXCIE = 7 ; RX Complete Interrupt Enable |
.equ RXCIE0 = RXCIE ; For compatibility |
; UCSRC - USART Control and Status Register C |
.equ UCSR0C = UCSRC ; For compatibility |
.equ UCPOL = 0 ; Clock Polarity |
.equ UCPOL0 = UCPOL ; For compatibility |
.equ UCSZ0 = 1 ; Character Size |
.equ UCSZ00 = UCSZ0 ; For compatibility |
.equ UCSZ1 = 2 ; Character Size |
.equ UCSZ01 = UCSZ1 ; For compatibility |
.equ USBS = 3 ; Stop Bit Select |
.equ USBS0 = USBS ; For compatibility |
.equ UPM0 = 4 ; Parity Mode Bit 0 |
.equ UPM00 = UPM0 ; For compatibility |
.equ UPM1 = 5 ; Parity Mode Bit 1 |
.equ UPM01 = UPM1 ; For compatibility |
.equ UMSEL = 6 ; USART Mode Select |
.equ UMSEL0 = UMSEL ; For compatibility |
.equ UBRR0H = UBRRH ; For compatibility |
.equ UBRR0L = UBRRL ; For compatibility |
.equ UBRR0 = UBRRL ; For compatibility |
.equ UBRR = UBRRL ; For compatibility |
; ***** PORTH ************************ |
; PORTH - PORT H Data Register |
.equ PORTH0 = 0 ; PORT H Data Register bit 0 |
.equ PH0 = 0 ; For compatibility |
.equ PORTH1 = 1 ; PORT H Data Register bit 1 |
.equ PH1 = 1 ; For compatibility |
.equ PORTH2 = 2 ; PORT H Data Register bit 2 |
.equ PH2 = 2 ; For compatibility |
.equ PORTH3 = 3 ; PORT H Data Register bit 3 |
.equ PH3 = 3 ; For compatibility |
.equ PORTH4 = 4 ; PORT H Data Register bit 4 |
.equ PH4 = 4 ; For compatibility |
.equ PORTH5 = 5 ; PORT H Data Register bit 5 |
.equ PH5 = 5 ; For compatibility |
.equ PORTH6 = 6 ; PORT H Data Register bit 6 |
.equ PH6 = 6 ; For compatibility |
.equ PORTH7 = 7 ; PORT H Data Register bit 7 |
.equ PH7 = 7 ; For compatibility |
; DDRH - PORT H Data Direction Register |
.equ DDH0 = 0 ; PORT H Data Direction Register bit 0 |
.equ DDH1 = 1 ; PORT H Data Direction Register bit 1 |
.equ DDH2 = 2 ; PORT H Data Direction Register bit 2 |
.equ DDH3 = 3 ; PORT H Data Direction Register bit 3 |
.equ DDH4 = 4 ; PORT H Data Direction Register bit 4 |
.equ DDH5 = 5 ; PORT H Data Direction Register bit 5 |
.equ DDH6 = 6 ; PORT H Data Direction Register bit 6 |
.equ DDH7 = 7 ; PORT H Data Direction Register bit 7 |
; PINH - PORT H Input Pins |
.equ PINH0 = 0 ; PORT H Input Pins bit 0 |
.equ PINH1 = 1 ; PORT H Input Pins bit 1 |
.equ PINH2 = 2 ; PORT H Input Pins bit 2 |
.equ PINH3 = 3 ; PORT H Input Pins bit 3 |
.equ PINH4 = 4 ; PORT H Input Pins bit 4 |
.equ PINH5 = 5 ; PORT H Input Pins bit 5 |
.equ PINH6 = 6 ; PORT H Input Pins bit 6 |
.equ PINH7 = 7 ; PORT H Input Pins bit 7 |
; ***** PORTJ ************************ |
; PORTJ - PORT J Data Register |
.equ PORTJ0 = 0 ; PORT J Data Register bit 0 |
.equ PJ0 = 0 ; For compatibility |
.equ PORTJ1 = 1 ; PORT J Data Register bit 1 |
.equ PJ1 = 1 ; For compatibility |
.equ PORTJ2 = 2 ; PORT J Data Register bit 2 |
.equ PJ2 = 2 ; For compatibility |
.equ PORTJ3 = 3 ; PORT J Data Register bit 3 |
.equ PJ3 = 3 ; For compatibility |
.equ PORTJ4 = 4 ; PORT J Data Register bit 4 |
.equ PJ4 = 4 ; For compatibility |
.equ PORTJ5 = 5 ; PORT J Data Register bit 5 |
.equ PJ5 = 5 ; For compatibility |
.equ PORTJ6 = 6 ; PORT J Data Register bit 6 |
.equ PJ6 = 6 ; For compatibility |
; DDRJ - PORT J Data Direction Register |
.equ DDJ0 = 0 ; PORT J Data Direction Register bit 0 |
.equ DDJ1 = 1 ; PORT J Data Direction Register bit 1 |
.equ DDJ2 = 2 ; PORT J Data Direction Register bit 2 |
.equ DDJ3 = 3 ; PORT J Data Direction Register bit 3 |
.equ DDJ4 = 4 ; PORT J Data Direction Register bit 4 |
.equ DDJ5 = 5 ; PORT J Data Direction Register bit 5 |
.equ DDJ6 = 6 ; PORT J Data Direction Register bit 6 |
; PINJ - PORT J Input Pins |
.equ PINJ0 = 0 ; PORT J Input Pins bit 0 |
.equ PINJ1 = 1 ; PORT J Input Pins bit 1 |
.equ PINJ2 = 2 ; PORT J Input Pins bit 2 |
.equ PINJ3 = 3 ; PORT J Input Pins bit 3 |
.equ PINJ4 = 4 ; PORT J Input Pins bit 4 |
.equ PINJ5 = 5 ; PORT J Input Pins bit 5 |
.equ PINJ6 = 6 ; PORT J Input Pins bit 6 |
; ***** LOCKSBITS ******************************************************** |
.equ LB1 = 0 ; Lock bit |
.equ LB2 = 1 ; Lock bit |
.equ BLB01 = 2 ; Boot Lock bit |
.equ BLB02 = 3 ; Boot Lock bit |
.equ BLB11 = 4 ; Boot lock bit |
.equ BLB12 = 5 ; Boot lock bit |
; ***** FUSES ************************************************************ |
; LOW fuse bits |
.equ CKSEL0 = 0 ; Select Clock Source |
.equ CKSEL1 = 1 ; Select Clock Source |
.equ CKSEL2 = 2 ; Select Clock Source |
.equ CKSEL3 = 3 ; Select Clock Source |
.equ SUT0 = 4 ; Select start-up time |
.equ SUT1 = 5 ; Select start-up time |
.equ CKOUT = 6 ; Oscillator options |
.equ CLKDIV8 = 7 ; Divide clock by 8 |
; HIGH fuse bits |
.equ BOOTRST = 0 ; Select Reset Vector |
.equ BOOTSZ0 = 1 ; Select Boot Size |
.equ BOOTSZ1 = 2 ; Select Boot Size |
.equ EESAVE = 3 ; EEPROM memory is preserved through chip erase |
.equ WDTON = 4 ; Watchdog timer always on |
.equ SPIEN = 5 ; Enable Serial programming and Data Downloading |
.equ JTAGEN = 6 ; Enable JTAG |
.equ OCDEN = 7 ; Enable OCD |
; EXTENDED fuse bits |
.equ RSTDISBL = 0 ; External Reset Disable |
.equ BODLEVEL0 = 1 ; Brown-out Detector trigger level |
.equ BODLEVEL1 = 2 ; Brown-out Detector trigger level |
; ***** CPU REGISTER DEFINITIONS ***************************************** |
.def XH = r27 |
.def XL = r26 |
.def YH = r29 |
.def YL = r28 |
.def ZH = r31 |
.def ZL = r30 |
; ***** DATA MEMORY DECLARATIONS ***************************************** |
.equ FLASHEND = 0x3fff ; Note: Word address |
.equ IOEND = 0x00ff |
.equ SRAM_START = 0x0100 |
.equ SRAM_SIZE = 2048 |
.equ RAMEND = 0x08ff |
.equ XRAMEND = 0x0000 |
.equ E2END = 0x03ff |
.equ EEPROMEND = 0x03ff |
.equ EEADRBITS = 10 |
#pragma AVRPART MEMORY PROG_FLASH 32768 |
#pragma AVRPART MEMORY EEPROM 1024 |
#pragma AVRPART MEMORY INT_SRAM SIZE 2048 |
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x100 |
; ***** BOOTLOADER DECLARATIONS ****************************************** |
.equ NRWW_START_ADDR = 0x3800 |
.equ NRWW_STOP_ADDR = 0x3fff |
.equ RWW_START_ADDR = 0x0 |
.equ RWW_STOP_ADDR = 0x37ff |
.equ PAGESIZE = 64 |
.equ FIRSTBOOTSTART = 0x3f00 |
.equ SECONDBOOTSTART = 0x3e00 |
.equ THIRDBOOTSTART = 0x3c00 |
.equ FOURTHBOOTSTART = 0x3800 |
.equ SMALLBOOTSTART = FIRSTBOOTSTART |
.equ LARGEBOOTSTART = FOURTHBOOTSTART |
; ***** INTERRUPT VECTORS ************************************************ |
.equ INT0addr = 0x0002 ; External Interrupt Request 0 |
.equ PCI0addr = 0x0004 ; Pin Change Interrupt Request 0 |
.equ PCI1addr = 0x0006 ; Pin Change Interrupt Request 1 |
.equ OC2addr = 0x0008 ; Timer/Counter2 Compare Match |
.equ OVF2addr = 0x000a ; Timer/Counter2 Overflow |
.equ ICP1addr = 0x000c ; Timer/Counter1 Capture Event |
.equ OC1Aaddr = 0x000e ; Timer/Counter1 Compare Match A |
.equ OC1Baddr = 0x0010 ; Timer/Counter Compare Match B |
.equ OVF1addr = 0x0012 ; Timer/Counter1 Overflow |
.equ OC0addr = 0x0014 ; Timer/Counter0 Compare Match |
.equ OVF0addr = 0x0016 ; Timer/Counter0 Overflow |
.equ SPIaddr = 0x0018 ; SPI Serial Transfer Complete |
.equ URXCaddr = 0x001a ; USART, Rx Complete |
.equ URXC0addr = 0x001a ; For compatibility |
.equ UDREaddr = 0x001c ; USART Data register Empty |
.equ UDRE0addr = 0x001c ; For compatibility |
.equ UTXC0addr = 0x001e ; USART0, Tx Complete |
.equ UTXCaddr = 0x001e ; For compatibility |
.equ USI_STARTaddr = 0x0020 ; USI Start Condition |
.equ USI_OVFaddr = 0x0022 ; USI Overflow |
.equ ACIaddr = 0x0024 ; Analog Comparator |
.equ ADCCaddr = 0x0026 ; ADC Conversion Complete |
.equ ERDYaddr = 0x0028 ; EEPROM Ready |
.equ SPMRaddr = 0x002a ; Store Program Memory Read |
.equ LCDSFaddr = 0x002c ; LCD Start of Frame |
.equ PCI2addr = 0x002e ; Pin Change Interrupt Request 2 |
.equ PCI3addr = 0x0030 ; Pin Change Interrupt Request 3 |
.equ INT_VECTORS_SIZE = 50 ; size in words |
#endif /* _M3290DEF_INC_ */ |
; ***** END OF FILE ****************************************************** |
/contrib/toolchain/avra/includes/m329def.inc |
---|
0,0 → 1,1242 |
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** |
;***** Created: 2005-01-11 10:31 ******* Source: ATmega329.xml *********** |
;************************************************************************* |
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y |
;* |
;* Number : AVR000 |
;* File Name : "m329def.inc" |
;* Title : Register/Bit Definitions for the ATmega329 |
;* Date : 2005-01-11 |
;* Version : 2.14 |
;* Support E-mail : avr@atmel.com |
;* Target MCU : ATmega329 |
;* |
;* DESCRIPTION |
;* When including this file in the assembly program file, all I/O register |
;* names and I/O register bit names appearing in the data book can be used. |
;* In addition, the six registers forming the three data pointers X, Y and |
;* Z have been assigned names XL - ZH. Highest RAM address for Internal |
;* SRAM is also defined |
;* |
;* The Register names are represented by their hexadecimal address. |
;* |
;* The Register Bit names are represented by their bit number (0-7). |
;* |
;* Please observe the difference in using the bit names with instructions |
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" |
;* (skip if bit in register set/cleared). The following example illustrates |
;* this: |
;* |
;* in r16,PORTB ;read PORTB latch |
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) |
;* out PORTB,r16 ;output to PORTB |
;* |
;* in r16,TIFR ;read the Timer Interrupt Flag Register |
;* sbrc r16,TOV0 ;test the overflow flag (use bit#) |
;* rjmp TOV0_is_set ;jump if set |
;* ... ;otherwise do something else |
;************************************************************************* |
#ifndef _M329DEF_INC_ |
#define _M329DEF_INC_ |
#pragma partinc 0 |
; ***** SPECIFY DEVICE *************************************************** |
.device ATmega329 |
#pragma AVRPART ADMIN PART_NAME ATmega329 |
.equ SIGNATURE_000 = 0x1e |
.equ SIGNATURE_001 = 0x95 |
.equ SIGNATURE_002 = 0x03 |
#pragma AVRPART CORE CORE_VERSION V2E |
; ***** I/O REGISTER DEFINITIONS ***************************************** |
; NOTE: |
; Definitions marked "MEMORY MAPPED"are extended I/O ports |
; and cannot be used with IN/OUT instructions |
.equ LCDDR19 = 0xff ; MEMORY MAPPED |
.equ LCDDR18 = 0xfe ; MEMORY MAPPED |
.equ LCDDR17 = 0xfd ; MEMORY MAPPED |
.equ LCDDR16 = 0xfc ; MEMORY MAPPED |
.equ LCDDR15 = 0xfb ; MEMORY MAPPED |
.equ LCDDR14 = 0xfa ; MEMORY MAPPED |
.equ LCDDR13 = 0xf9 ; MEMORY MAPPED |
.equ LCDDR12 = 0xf8 ; MEMORY MAPPED |
.equ LCDDR11 = 0xf7 ; MEMORY MAPPED |
.equ LCDDR10 = 0xf6 ; MEMORY MAPPED |
.equ LCDDR9 = 0xf5 ; MEMORY MAPPED |
.equ LCDDR8 = 0xf4 ; MEMORY MAPPED |
.equ LCDDR7 = 0xf3 ; MEMORY MAPPED |
.equ LCDDR6 = 0xf2 ; MEMORY MAPPED |
.equ LCDDR5 = 0xf1 ; MEMORY MAPPED |
.equ LCDDR4 = 0xf0 ; MEMORY MAPPED |
.equ LCDDR3 = 0xef ; MEMORY MAPPED |
.equ LCDDR2 = 0xee ; MEMORY MAPPED |
.equ LCDDR1 = 0xed ; MEMORY MAPPED |
.equ LCDDR0 = 0xec ; MEMORY MAPPED |
.equ LCDCCR = 0xe7 ; MEMORY MAPPED |
.equ LCDFRR = 0xe6 ; MEMORY MAPPED |
.equ LCDCRB = 0xe5 ; MEMORY MAPPED |
.equ LCDCRA = 0xe4 ; MEMORY MAPPED |
.equ PORTJ = 0xdd ; MEMORY MAPPED |
.equ DDRJ = 0xdc ; MEMORY MAPPED |
.equ PINJ = 0xdb ; MEMORY MAPPED |
.equ PORTH = 0xda ; MEMORY MAPPED |
.equ DDRH = 0xd9 ; MEMORY MAPPED |
.equ PINH = 0xd8 ; MEMORY MAPPED |
.equ UDR = 0xc6 ; MEMORY MAPPED |
.equ UBRRH = 0xc5 ; MEMORY MAPPED |
.equ UBRRL = 0xc4 ; MEMORY MAPPED |
.equ UCSRC = 0xc2 ; MEMORY MAPPED |
.equ UCSRB = 0xc1 ; MEMORY MAPPED |
.equ UCSRA = 0xc0 ; MEMORY MAPPED |
.equ USIDR = 0xba ; MEMORY MAPPED |
.equ USISR = 0xb9 ; MEMORY MAPPED |
.equ USICR = 0xb8 ; MEMORY MAPPED |
.equ ASSR = 0xb6 ; MEMORY MAPPED |
.equ OCR2A = 0xb3 ; MEMORY MAPPED |
.equ TCNT2 = 0xb2 ; MEMORY MAPPED |
.equ TCCR2A = 0xb0 ; MEMORY MAPPED |
.equ OCR1BH = 0x8b ; MEMORY MAPPED |
.equ OCR1BL = 0x8a ; MEMORY MAPPED |
.equ OCR1AH = 0x89 ; MEMORY MAPPED |
.equ OCR1AL = 0x88 ; MEMORY MAPPED |
.equ ICR1H = 0x87 ; MEMORY MAPPED |
.equ ICR1L = 0x86 ; MEMORY MAPPED |
.equ TCNT1H = 0x85 ; MEMORY MAPPED |
.equ TCNT1L = 0x84 ; MEMORY MAPPED |
.equ TCCR1C = 0x82 ; MEMORY MAPPED |
.equ TCCR1B = 0x81 ; MEMORY MAPPED |
.equ TCCR1A = 0x80 ; MEMORY MAPPED |
.equ DIDR1 = 0x7f ; MEMORY MAPPED |
.equ DIDR0 = 0x7e ; MEMORY MAPPED |
.equ ADMUX = 0x7c ; MEMORY MAPPED |
.equ ADCSRB = 0x7b ; MEMORY MAPPED |
.equ ADCSRA = 0x7a ; MEMORY MAPPED |
.equ ADCH = 0x79 ; MEMORY MAPPED |
.equ ADCL = 0x78 ; MEMORY MAPPED |
.equ PCMSK3 = 0x73 ; MEMORY MAPPED |
.equ TIMSK2 = 0x70 ; MEMORY MAPPED |
.equ TIMSK1 = 0x6f ; MEMORY MAPPED |
.equ TIMSK0 = 0x6e ; MEMORY MAPPED |
.equ PCMSK2 = 0x6d ; MEMORY MAPPED |
.equ PCMSK1 = 0x6c ; MEMORY MAPPED |
.equ PCMSK0 = 0x6b ; MEMORY MAPPED |
.equ EICRA = 0x69 ; MEMORY MAPPED |
.equ OSCCAL = 0x66 ; MEMORY MAPPED |
.equ PRR = 0x64 ; MEMORY MAPPED |
.equ CLKPR = 0x61 ; MEMORY MAPPED |
.equ WDTCR = 0x60 ; MEMORY MAPPED |
.equ SREG = 0x3f |
.equ SPH = 0x3e |
.equ SPL = 0x3d |
.equ SPMCSR = 0x37 |
.equ MCUCR = 0x35 |
.equ MCUSR = 0x34 |
.equ SMCR = 0x33 |
.equ OCDR = 0x31 |
.equ ACSR = 0x30 |
.equ SPDR = 0x2e |
.equ SPSR = 0x2d |
.equ SPCR = 0x2c |
.equ GPIOR2 = 0x2b |
.equ GPIOR1 = 0x2a |
.equ OCR0A = 0x27 |
.equ TCNT0 = 0x26 |
.equ TCCR0A = 0x24 |
.equ GTCCR = 0x23 |
.equ EEARH = 0x22 |
.equ EEARL = 0x21 |
.equ EEDR = 0x20 |
.equ EECR = 0x1f |
.equ GPIOR0 = 0x1e |
.equ EIMSK = 0x1d |
.equ EIFR = 0x1c |
.equ TIFR2 = 0x17 |
.equ TIFR1 = 0x16 |
.equ TIFR0 = 0x15 |
.equ PORTG = 0x14 |
.equ DDRG = 0x13 |
.equ PING = 0x12 |
.equ PORTF = 0x11 |
.equ DDRF = 0x10 |
.equ PINF = 0x0f |
.equ PORTE = 0x0e |
.equ DDRE = 0x0d |
.equ PINE = 0x0c |
.equ PORTD = 0x0b |
.equ DDRD = 0x0a |
.equ PIND = 0x09 |
.equ PORTC = 0x08 |
.equ DDRC = 0x07 |
.equ PINC = 0x06 |
.equ PORTB = 0x05 |
.equ DDRB = 0x04 |
.equ PINB = 0x03 |
.equ PORTA = 0x02 |
.equ DDRA = 0x01 |
.equ PINA = 0x00 |
; ***** BIT DEFINITIONS ************************************************** |
; ***** TIMER_COUNTER_0 ************** |
; TCCR0A - Timer/Counter0 Control Register |
.equ CS00 = 0 ; Clock Select 1 |
.equ CS01 = 1 ; Clock Select 1 |
.equ CS02 = 2 ; Clock Select 2 |
.equ WGM01 = 3 ; Waveform Generation Mode 1 |
.equ COM0A0 = 4 ; Compare match Output Mode 0 |
.equ COM0A1 = 5 ; Compare Match Output Mode 1 |
.equ WGM00 = 6 ; Waveform Generation Mode 0 |
.equ FOC0A = 7 ; Force Output Compare |
; TCNT0 - Timer/Counter0 |
.equ TCNT0_0 = 0 ; |
.equ TCNT0_1 = 1 ; |
.equ TCNT0_2 = 2 ; |
.equ TCNT0_3 = 3 ; |
.equ TCNT0_4 = 4 ; |
.equ TCNT0_5 = 5 ; |
.equ TCNT0_6 = 6 ; |
.equ TCNT0_7 = 7 ; |
; OCR0A - Timer/Counter0 Output Compare Register |
.equ OCR0A0 = 0 ; |
.equ OCR0A1 = 1 ; |
.equ OCR0A2 = 2 ; |
.equ OCR0A3 = 3 ; |
.equ OCR0A4 = 4 ; |
.equ OCR0A5 = 5 ; |
.equ OCR0A6 = 6 ; |
.equ OCR0A7 = 7 ; |
; TIMSK0 - Timer/Counter0 Interrupt Mask Register |
.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable |
.equ OCIE0A = 1 ; Timer/Counter0 Output Compare Match Interrupt Enable |
; TIFR0 - Timer/Counter0 Interrupt Flag register |
.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag |
.equ OCF0A = 1 ; Timer/Counter0 Output Compare Flag 0 |
; GTCCR - General Timer/Control Register |
.equ PSR310 = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0 |
.equ PSR10 = PSR310 ; For compatibility |
.equ PSR0 = PSR310 ; For compatibility |
.equ PSR1 = PSR310 ; For compatibility |
.equ PSR3 = PSR310 ; For compatibility |
.equ TSM = 7 ; Timer/Counter Synchronization Mode |
; ***** TIMER_COUNTER_1 ************** |
; TIMSK1 - Timer/Counter1 Interrupt Mask Register |
.equ TOIE1 = 0 ; Timer/Counter1 Overflow Interrupt Enable |
.equ OCIE1A = 1 ; Timer/Counter1 Output Compare A Match Interrupt Enable |
.equ OCIE1B = 2 ; Timer/Counter1 Output Compare B Match Interrupt Enable |
.equ ICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable |
; TIFR1 - Timer/Counter1 Interrupt Flag register |
.equ TOV1 = 0 ; Timer/Counter1 Overflow Flag |
.equ OCF1A = 1 ; Output Compare Flag 1A |
.equ OCF1B = 2 ; Output Compare Flag 1B |
.equ ICF1 = 5 ; Input Capture Flag 1 |
; TCCR1A - Timer/Counter1 Control Register A |
.equ WGM10 = 0 ; Waveform Generation Mode |
.equ WGM11 = 1 ; Waveform Generation Mode |
.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0 |
.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1 |
.equ COM1A0 = 6 ; Compare Output Mode 1A, bit 0 |
.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1 |
; TCCR1B - Timer/Counter1 Control Register B |
.equ CS10 = 0 ; Prescaler source of Timer/Counter 1 |
.equ CS11 = 1 ; Prescaler source of Timer/Counter 1 |
.equ CS12 = 2 ; Prescaler source of Timer/Counter 1 |
.equ WGM12 = 3 ; Waveform Generation Mode |
.equ WGM13 = 4 ; Waveform Generation Mode |
.equ ICES1 = 6 ; Input Capture 1 Edge Select |
.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler |
; TCCR1C - Timer/Counter 1 Control Register C |
.equ FOC1B = 6 ; Force Output Compare 1B |
.equ FOC1A = 7 ; Force Output Compare 1A |
; ***** TIMER_COUNTER_2 ************** |
; TIMSK2 - Timer/Counter2 Interrupt Mask register |
.equ TOIE2 = 0 ; Timer/Counter2 Overflow Interrupt Enable |
.equ OCIE2A = 1 ; Timer/Counter2 Output Compare Match Interrupt Enable |
; TIFR2 - Timer/Counter2 Interrupt Flag Register |
.equ TOV2 = 0 ; Timer/Counter2 Overflow Flag |
.equ OCF2A = 1 ; Timer/Counter2 Output Compare Flag 2 |
; TCCR2A - Timer/Counter2 Control Register |
.equ CS20 = 0 ; Clock Select bit 0 |
.equ CS21 = 1 ; Clock Select bit 1 |
.equ CS22 = 2 ; Clock Select bit 2 |
.equ WGM21 = 3 ; Waveform Generation Mode |
.equ COM2A0 = 4 ; Compare Output Mode bit 0 |
.equ COM2A1 = 5 ; Compare Output Mode bit 1 |
.equ WGM20 = 6 ; Waveform Generation Mode |
.equ FOC2A = 7 ; Force Output Compare A |
; TCNT2 - Timer/Counter2 |
.equ TCNT2_0 = 0 ; Timer/Counter 2 bit 0 |
.equ TCNT2_1 = 1 ; Timer/Counter 2 bit 1 |
.equ TCNT2_2 = 2 ; Timer/Counter 2 bit 2 |
.equ TCNT2_3 = 3 ; Timer/Counter 2 bit 3 |
.equ TCNT2_4 = 4 ; Timer/Counter 2 bit 4 |
.equ TCNT2_5 = 5 ; Timer/Counter 2 bit 5 |
.equ TCNT2_6 = 6 ; Timer/Counter 2 bit 6 |
.equ TCNT2_7 = 7 ; Timer/Counter 2 bit 7 |
; OCR2A - Timer/Counter2 Output Compare Register |
.equ OCR2A0 = 0 ; Timer/Counter2 Output Compare Register Bit 0 |
.equ OCR2A1 = 1 ; Timer/Counter2 Output Compare Register Bit 1 |
.equ OCR2A2 = 2 ; Timer/Counter2 Output Compare Register Bit 2 |
.equ OCR2A3 = 3 ; Timer/Counter2 Output Compare Register Bit 3 |
.equ OCR2A4 = 4 ; Timer/Counter2 Output Compare Register Bit 4 |
.equ OCR2A5 = 5 ; Timer/Counter2 Output Compare Register Bit 5 |
.equ OCR2A6 = 6 ; Timer/Counter2 Output Compare Register Bit 6 |
.equ OCR2A7 = 7 ; Timer/Counter2 Output Compare Register Bit 7 |
; GTCCR - General Timer/Counter Control Register |
.equ PSR2 = 1 ; Prescaler Reset Timer/Counter2 |
; ASSR - Asynchronous Status Register |
.equ TCR2UB = 0 ; TCR2UB: Timer/Counter Control Register2 Update Busy |
.equ OCR2UB = 1 ; Output Compare Register2 Update Busy |
.equ TCN2UB = 2 ; TCN2UB: Timer/Counter2 Update Busy |
.equ AS2 = 3 ; AS2: Asynchronous Timer/Counter2 |
.equ EXCLK = 4 ; Enable External Clock Interrupt |
; ***** WATCHDOG ********************* |
; WDTCR - Watchdog Timer Control Register |
.equ WDTCSR = WDTCR ; For compatibility |
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 |
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 |
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 |
.equ WDE = 3 ; Watch Dog Enable |
.equ WDCE = 4 ; Watchdog Change Enable |
.equ WDTOE = WDCE ; For compatibility |
; ***** EEPROM *********************** |
; EEDR - EEPROM Data Register |
.equ EEDR0 = 0 ; EEPROM Data Register bit 0 |
.equ EEDR1 = 1 ; EEPROM Data Register bit 1 |
.equ EEDR2 = 2 ; EEPROM Data Register bit 2 |
.equ EEDR3 = 3 ; EEPROM Data Register bit 3 |
.equ EEDR4 = 4 ; EEPROM Data Register bit 4 |
.equ EEDR5 = 5 ; EEPROM Data Register bit 5 |
.equ EEDR6 = 6 ; EEPROM Data Register bit 6 |
.equ EEDR7 = 7 ; EEPROM Data Register bit 7 |
; EECR - EEPROM Control Register |
.equ EERE = 0 ; EEPROM Read Enable |
.equ EEWE = 1 ; EEPROM Write Enable |
.equ EEMWE = 2 ; EEPROM Master Write Enable |
.equ EERIE = 3 ; EEPROM Ready Interrupt Enable |
; ***** SPI ************************** |
; SPDR - SPI Data Register |
.equ SPDR0 = 0 ; SPI Data Register bit 0 |
.equ SPDR1 = 1 ; SPI Data Register bit 1 |
.equ SPDR2 = 2 ; SPI Data Register bit 2 |
.equ SPDR3 = 3 ; SPI Data Register bit 3 |
.equ SPDR4 = 4 ; SPI Data Register bit 4 |
.equ SPDR5 = 5 ; SPI Data Register bit 5 |
.equ SPDR6 = 6 ; SPI Data Register bit 6 |
.equ SPDR7 = 7 ; SPI Data Register bit 7 |
; SPSR - SPI Status Register |
.equ SPI2X = 0 ; Double SPI Speed Bit |
.equ WCOL = 6 ; Write Collision Flag |
.equ SPIF = 7 ; SPI Interrupt Flag |
; SPCR - SPI Control Register |
.equ SPR0 = 0 ; SPI Clock Rate Select 0 |
.equ SPR1 = 1 ; SPI Clock Rate Select 1 |
.equ CPHA = 2 ; Clock Phase |
.equ CPOL = 3 ; Clock polarity |
.equ MSTR = 4 ; Master/Slave Select |
.equ DORD = 5 ; Data Order |
.equ SPE = 6 ; SPI Enable |
.equ SPIE = 7 ; SPI Interrupt Enable |
; ***** PORTA ************************ |
; PORTA - Port A Data Register |
.equ PORTA0 = 0 ; Port A Data Register bit 0 |
.equ PA0 = 0 ; For compatibility |
.equ PORTA1 = 1 ; Port A Data Register bit 1 |
.equ PA1 = 1 ; For compatibility |
.equ PORTA2 = 2 ; Port A Data Register bit 2 |
.equ PA2 = 2 ; For compatibility |
.equ PORTA3 = 3 ; Port A Data Register bit 3 |
.equ PA3 = 3 ; For compatibility |
.equ PORTA4 = 4 ; Port A Data Register bit 4 |
.equ PA4 = 4 ; For compatibility |
.equ PORTA5 = 5 ; Port A Data Register bit 5 |
.equ PA5 = 5 ; For compatibility |
.equ PORTA6 = 6 ; Port A Data Register bit 6 |
.equ PA6 = 6 ; For compatibility |
.equ PORTA7 = 7 ; Port A Data Register bit 7 |
.equ PA7 = 7 ; For compatibility |
; DDRA - Port A Data Direction Register |
.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0 |
.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1 |
.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2 |
.equ DDA3 = 3 ; Data Direction Register, Port A, bit 3 |
.equ DDA4 = 4 ; Data Direction Register, Port A, bit 4 |
.equ DDA5 = 5 ; Data Direction Register, Port A, bit 5 |
.equ DDA6 = 6 ; Data Direction Register, Port A, bit 6 |
.equ DDA7 = 7 ; Data Direction Register, Port A, bit 7 |
; PINA - Port A Input Pins |
.equ PINA0 = 0 ; Input Pins, Port A bit 0 |
.equ PINA1 = 1 ; Input Pins, Port A bit 1 |
.equ PINA2 = 2 ; Input Pins, Port A bit 2 |
.equ PINA3 = 3 ; Input Pins, Port A bit 3 |
.equ PINA4 = 4 ; Input Pins, Port A bit 4 |
.equ PINA5 = 5 ; Input Pins, Port A bit 5 |
.equ PINA6 = 6 ; Input Pins, Port A bit 6 |
.equ PINA7 = 7 ; Input Pins, Port A bit 7 |
; ***** PORTB ************************ |
; PORTB - Port B Data Register |
.equ PORTB0 = 0 ; Port B Data Register bit 0 |
.equ PB0 = 0 ; For compatibility |
.equ PORTB1 = 1 ; Port B Data Register bit 1 |
.equ PB1 = 1 ; For compatibility |
.equ PORTB2 = 2 ; Port B Data Register bit 2 |
.equ PB2 = 2 ; For compatibility |
.equ PORTB3 = 3 ; Port B Data Register bit 3 |
.equ PB3 = 3 ; For compatibility |
.equ PORTB4 = 4 ; Port B Data Register bit 4 |
.equ PB4 = 4 ; For compatibility |
.equ PORTB5 = 5 ; Port B Data Register bit 5 |
.equ PB5 = 5 ; For compatibility |
.equ PORTB6 = 6 ; Port B Data Register bit 6 |
.equ PB6 = 6 ; For compatibility |
.equ PORTB7 = 7 ; Port B Data Register bit 7 |
.equ PB7 = 7 ; For compatibility |
; DDRB - Port B Data Direction Register |
.equ DDB0 = 0 ; Port B Data Direction Register bit 0 |
.equ DDB1 = 1 ; Port B Data Direction Register bit 1 |
.equ DDB2 = 2 ; Port B Data Direction Register bit 2 |
.equ DDB3 = 3 ; Port B Data Direction Register bit 3 |
.equ DDB4 = 4 ; Port B Data Direction Register bit 4 |
.equ DDB5 = 5 ; Port B Data Direction Register bit 5 |
.equ DDB6 = 6 ; Port B Data Direction Register bit 6 |
.equ DDB7 = 7 ; Port B Data Direction Register bit 7 |
; PINB - Port B Input Pins |
.equ PINB0 = 0 ; Port B Input Pins bit 0 |
.equ PINB1 = 1 ; Port B Input Pins bit 1 |
.equ PINB2 = 2 ; Port B Input Pins bit 2 |
.equ PINB3 = 3 ; Port B Input Pins bit 3 |
.equ PINB4 = 4 ; Port B Input Pins bit 4 |
.equ PINB5 = 5 ; Port B Input Pins bit 5 |
.equ PINB6 = 6 ; Port B Input Pins bit 6 |
.equ PINB7 = 7 ; Port B Input Pins bit 7 |
; ***** PORTC ************************ |
; PORTC - Port C Data Register |
.equ PORTC0 = 0 ; Port C Data Register bit 0 |
.equ PC0 = 0 ; For compatibility |
.equ PORTC1 = 1 ; Port C Data Register bit 1 |
.equ PC1 = 1 ; For compatibility |
.equ PORTC2 = 2 ; Port C Data Register bit 2 |
.equ PC2 = 2 ; For compatibility |
.equ PORTC3 = 3 ; Port C Data Register bit 3 |
.equ PC3 = 3 ; For compatibility |
.equ PORTC4 = 4 ; Port C Data Register bit 4 |
.equ PC4 = 4 ; For compatibility |
.equ PORTC5 = 5 ; Port C Data Register bit 5 |
.equ PC5 = 5 ; For compatibility |
.equ PORTC6 = 6 ; Port C Data Register bit 6 |
.equ PC6 = 6 ; For compatibility |
.equ PORTC7 = 7 ; Port C Data Register bit 7 |
.equ PC7 = 7 ; For compatibility |
; DDRC - Port C Data Direction Register |
.equ DDC0 = 0 ; Port C Data Direction Register bit 0 |
.equ DDC1 = 1 ; Port C Data Direction Register bit 1 |
.equ DDC2 = 2 ; Port C Data Direction Register bit 2 |
.equ DDC3 = 3 ; Port C Data Direction Register bit 3 |
.equ DDC4 = 4 ; Port C Data Direction Register bit 4 |
.equ DDC5 = 5 ; Port C Data Direction Register bit 5 |
.equ DDC6 = 6 ; Port C Data Direction Register bit 6 |
.equ DDC7 = 7 ; Port C Data Direction Register bit 7 |
; PINC - Port C Input Pins |
.equ PINC0 = 0 ; Port C Input Pins bit 0 |
.equ PINC1 = 1 ; Port C Input Pins bit 1 |
.equ PINC2 = 2 ; Port C Input Pins bit 2 |
.equ PINC3 = 3 ; Port C Input Pins bit 3 |
.equ PINC4 = 4 ; Port C Input Pins bit 4 |
.equ PINC5 = 5 ; Port C Input Pins bit 5 |
.equ PINC6 = 6 ; Port C Input Pins bit 6 |
.equ PINC7 = 7 ; Port C Input Pins bit 7 |
; ***** PORTD ************************ |
; PORTD - Port D Data Register |
.equ PORTD0 = 0 ; Port D Data Register bit 0 |
.equ PD0 = 0 ; For compatibility |
.equ PORTD1 = 1 ; Port D Data Register bit 1 |
.equ PD1 = 1 ; For compatibility |
.equ PORTD2 = 2 ; Port D Data Register bit 2 |
.equ PD2 = 2 ; For compatibility |
.equ PORTD3 = 3 ; Port D Data Register bit 3 |
.equ PD3 = 3 ; For compatibility |
.equ PORTD4 = 4 ; Port D Data Register bit 4 |
.equ PD4 = 4 ; For compatibility |
.equ PORTD5 = 5 ; Port D Data Register bit 5 |
.equ PD5 = 5 ; For compatibility |
.equ PORTD6 = 6 ; Port D Data Register bit 6 |
.equ PD6 = 6 ; For compatibility |
.equ PORTD7 = 7 ; Port D Data Register bit 7 |
.equ PD7 = 7 ; For compatibility |
; DDRD - Port D Data Direction Register |
.equ DDD0 = 0 ; Port D Data Direction Register bit 0 |
.equ DDD1 = 1 ; Port D Data Direction Register bit 1 |
.equ DDD2 = 2 ; Port D Data Direction Register bit 2 |
.equ DDD3 = 3 ; Port D Data Direction Register bit 3 |
.equ DDD4 = 4 ; Port D Data Direction Register bit 4 |
.equ DDD5 = 5 ; Port D Data Direction Register bit 5 |
.equ DDD6 = 6 ; Port D Data Direction Register bit 6 |
.equ DDD7 = 7 ; Port D Data Direction Register bit 7 |
; PIND - Port D Input Pins |
.equ PIND0 = 0 ; Port D Input Pins bit 0 |
.equ PIND1 = 1 ; Port D Input Pins bit 1 |
.equ PIND2 = 2 ; Port D Input Pins bit 2 |
.equ PIND3 = 3 ; Port D Input Pins bit 3 |
.equ PIND4 = 4 ; Port D Input Pins bit 4 |
.equ PIND5 = 5 ; Port D Input Pins bit 5 |
.equ PIND6 = 6 ; Port D Input Pins bit 6 |
.equ PIND7 = 7 ; Port D Input Pins bit 7 |
; ***** ANALOG_COMPARATOR ************ |
; ADCSRB - ADC Control and Status Register B |
.equ ACME = 6 ; Analog Comparator Multiplexer Enable |
; ACSR - Analog Comparator Control And Status Register |
.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 |
.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 |
.equ ACIC = 2 ; Analog Comparator Input Capture Enable |
.equ ACIE = 3 ; Analog Comparator Interrupt Enable |
.equ ACI = 4 ; Analog Comparator Interrupt Flag |
.equ ACO = 5 ; Analog Compare Output |
.equ ACBG = 6 ; Analog Comparator Bandgap Select |
.equ ACD = 7 ; Analog Comparator Disable |
; DIDR1 - Digital Input Disable Register 1 |
.equ AIN0D = 0 ; AIN0 Digital Input Disable |
.equ AIN1D = 1 ; AIN1 Digital Input Disable |
; ***** PORTE ************************ |
; PORTE - Data Register, Port E |
.equ PORTE0 = 0 ; |
.equ PE0 = 0 ; For compatibility |
.equ PORTE1 = 1 ; |
.equ PE1 = 1 ; For compatibility |
.equ PORTE2 = 2 ; |
.equ PE2 = 2 ; For compatibility |
.equ PORTE3 = 3 ; |
.equ PE3 = 3 ; For compatibility |
.equ PORTE4 = 4 ; |
.equ PE4 = 4 ; For compatibility |
.equ PORTE5 = 5 ; |
.equ PE5 = 5 ; For compatibility |
.equ PORTE6 = 6 ; |
.equ PE6 = 6 ; For compatibility |
.equ PORTE7 = 7 ; |
.equ PE7 = 7 ; For compatibility |
; DDRE - Data Direction Register, Port E |
.equ DDE0 = 0 ; |
.equ DDE1 = 1 ; |
.equ DDE2 = 2 ; |
.equ DDE3 = 3 ; |
.equ DDE4 = 4 ; |
.equ DDE5 = 5 ; |
.equ DDE6 = 6 ; |
.equ DDE7 = 7 ; |
; PINE - Input Pins, Port E |
.equ PINE0 = 0 ; |
.equ PINE1 = 1 ; |
.equ PINE2 = 2 ; |
.equ PINE3 = 3 ; |
.equ PINE4 = 4 ; |
.equ PINE5 = 5 ; |
.equ PINE6 = 6 ; |
.equ PINE7 = 7 ; |
; ***** PORTF ************************ |
; PORTF - Data Register, Port F |
.equ PORTF0 = 0 ; |
.equ PF0 = 0 ; For compatibility |
.equ PORTF1 = 1 ; |
.equ PF1 = 1 ; For compatibility |
.equ PORTF2 = 2 ; |
.equ PF2 = 2 ; For compatibility |
.equ PORTF3 = 3 ; |
.equ PF3 = 3 ; For compatibility |
.equ PORTF4 = 4 ; |
.equ PF4 = 4 ; For compatibility |
.equ PORTF5 = 5 ; |
.equ PF5 = 5 ; For compatibility |
.equ PORTF6 = 6 ; |
.equ PF6 = 6 ; For compatibility |
.equ PORTF7 = 7 ; |
.equ PF7 = 7 ; For compatibility |
; DDRF - Data Direction Register, Port F |
.equ DDF0 = 0 ; |
.equ DDF1 = 1 ; |
.equ DDF2 = 2 ; |
.equ DDF3 = 3 ; |
.equ DDF4 = 4 ; |
.equ DDF5 = 5 ; |
.equ DDF6 = 6 ; |
.equ DDF7 = 7 ; |
; PINF - Input Pins, Port F |
.equ PINF0 = 0 ; |
.equ PINF1 = 1 ; |
.equ PINF2 = 2 ; |
.equ PINF3 = 3 ; |
.equ PINF4 = 4 ; |
.equ PINF5 = 5 ; |
.equ PINF6 = 6 ; |
.equ PINF7 = 7 ; |
; ***** PORTG ************************ |
; PORTG - Port G Data Register |
.equ PORTG0 = 0 ; |
.equ PG0 = 0 ; For compatibility |
.equ PORTG1 = 1 ; |
.equ PG1 = 1 ; For compatibility |
.equ PORTG2 = 2 ; |
.equ PG2 = 2 ; For compatibility |
.equ PORTG3 = 3 ; |
.equ PG3 = 3 ; For compatibility |
.equ PORTG4 = 4 ; |
.equ PG4 = 4 ; For compatibility |
; DDRG - Port G Data Direction Register |
.equ DDG0 = 0 ; |
.equ DDG1 = 1 ; |
.equ DDG2 = 2 ; |
.equ DDG3 = 3 ; |
.equ DDG4 = 4 ; |
; PING - Port G Input Pins |
.equ PING0 = 0 ; |
.equ PING1 = 1 ; |
.equ PING2 = 2 ; |
.equ PING3 = 3 ; |
.equ PING4 = 4 ; |
.equ PING5 = 5 ; |
; ***** JTAG ************************* |
; OCDR - On-Chip Debug Related Register in I/O Memory |
.equ OCDR0 = 0 ; On-Chip Debug Register Bit 0 |
.equ OCDR1 = 1 ; On-Chip Debug Register Bit 1 |
.equ OCDR2 = 2 ; On-Chip Debug Register Bit 2 |
.equ OCDR3 = 3 ; On-Chip Debug Register Bit 3 |
.equ OCDR4 = 4 ; On-Chip Debug Register Bit 4 |
.equ OCDR5 = 5 ; On-Chip Debug Register Bit 5 |
.equ OCDR6 = 6 ; On-Chip Debug Register Bit 6 |
.equ OCDR7 = 7 ; On-Chip Debug Register Bit 7 |
.equ IDRD = OCDR7 ; For compatibility |
; MCUCR - MCU Control Register |
.equ JTD = 7 ; JTAG Interface Disable |
; MCUSR - MCU Status Register |
.equ JTRF = 4 ; JTAG Reset Flag |
; ***** MISC ************************* |
; LCDCRA - LCD Control Register A |
.equ LCDBL = 0 ; LCD Blanking |
.equ LCDIE = 3 ; LCD Interrupt Enable |
.equ LCDIF = 4 ; LCD Interrupt Flag |
.equ LCDAB = 6 ; LCD A or B waveform |
.equ LCDEN = 7 ; LCD Enable |
; LCDCRB - LCD Control and Status Register B |
.equ LCDPM0 = 0 ; LCD Port Mask 0 |
.equ LCDPM1 = 1 ; LCD Port Mask 1 |
.equ LCDPM2 = 2 ; LCD Port Mask 2 |
.equ LCDPM3 = 3 ; LCD Port Mask 3 |
.equ LCDMUX0 = 4 ; LCD Mux Select 0 |
.equ LCDMUX1 = 5 ; LCD Mux Select 1 |
.equ LCD2B = 6 ; LCD 1/2 Bias Select |
.equ LCDCS = 7 ; LCD CLock Select |
; LCDFRR - LCD Frame Rate Register |
.equ LCDCD0 = 0 ; LCD Clock Divider 0 |
.equ LCDCD1 = 1 ; LCD Clock Divider 1 |
.equ LCDCD2 = 2 ; LCD Clock Divider 2 |
.equ LCDPS0 = 4 ; LCD Prescaler Select 0 |
.equ LCDPS1 = 5 ; LCD Prescaler Select 1 |
.equ LCDPS2 = 6 ; LCD Prescaler Select 2 |
; LCDCCR - LCD Contrast Control Register |
.equ LCDCC0 = 0 ; LCD Contrast Control 0 |
.equ LCDCC1 = 1 ; LCD Contrast Control 1 |
.equ LCDCC2 = 2 ; LCD Contrast Control 2 |
.equ LCDCC3 = 3 ; LCD Contrast Control 3 |
.equ LCDDC0 = 5 ; |
.equ LCDDC1 = 6 ; |
.equ LCDDC2 = 7 ; |
; LCDDR18 - LCD Data Register 18 |
.equ SEG324 = 0 ; |
; LCDDR17 - LCD Data Register 17 |
.equ SEG316 = 0 ; |
.equ SEG317 = 1 ; |
.equ SEG318 = 2 ; |
.equ SEG319 = 3 ; |
.equ SEG320 = 4 ; |
.equ SEG321 = 5 ; |
.equ SEG322 = 6 ; |
.equ SEG323 = 7 ; |
; LCDDR16 - LCD Data Register 16 |
.equ SEG308 = 0 ; |
.equ SEG309 = 1 ; |
.equ SEG310 = 2 ; |
.equ SEG311 = 3 ; |
.equ SEG312 = 4 ; |
.equ SEG313 = 5 ; |
.equ SEG314 = 6 ; |
.equ SEG315 = 7 ; |
; LCDDR15 - LCD Data Register 15 |
.equ SEG300 = 0 ; |
.equ SEG301 = 1 ; |
.equ SEG302 = 2 ; |
.equ SEG303 = 3 ; |
.equ SEG304 = 4 ; |
.equ SEG305 = 5 ; |
.equ SEG306 = 6 ; |
.equ SEG307 = 7 ; |
; LCDDR13 - LCD Data Register 13 |
.equ SEG224 = 0 ; |
; LCDDR12 - LCD Data Register 12 |
.equ SEG216 = 0 ; |
.equ SEG217 = 1 ; |
.equ SEG218 = 2 ; |
.equ SEG219 = 3 ; |
.equ SEG220 = 4 ; |
.equ SEG221 = 5 ; |
.equ SEG222 = 6 ; |
.equ SEG223 = 7 ; |
; LCDDR11 - LCD Data Register 11 |
.equ SEG208 = 0 ; |
.equ SEG209 = 1 ; |
.equ SEG210 = 2 ; |
.equ SEG211 = 3 ; |
.equ SEG212 = 4 ; |
.equ SEG213 = 5 ; |
.equ SEG214 = 6 ; |
.equ SEG215 = 7 ; |
; LCDDR10 - LCD Data Register 10 |
.equ SEG200 = 0 ; |
.equ SEG201 = 1 ; |
.equ SEG202 = 2 ; |
.equ SEG203 = 3 ; |
.equ SEG204 = 4 ; |
.equ SEG205 = 5 ; |
.equ SEG206 = 6 ; |
.equ SEG207 = 7 ; |
; LCDDR8 - LCD Data Register 8 |
.equ SEG124 = 0 ; |
; LCDDR7 - LCD Data Register 7 |
.equ SEG116 = 0 ; |
.equ SEG117 = 1 ; |
.equ SEG118 = 2 ; |
.equ SEG119 = 3 ; |
.equ SEG120 = 4 ; |
.equ SEG121 = 5 ; |
.equ SEG122 = 6 ; |
.equ SEG123 = 7 ; |
; LCDDR6 - LCD Data Register 6 |
.equ SEG108 = 0 ; |
.equ SEG109 = 1 ; |
.equ SEG110 = 2 ; |
.equ SEG111 = 3 ; |
.equ SEG112 = 4 ; |
.equ SEG113 = 5 ; |
.equ SEG114 = 6 ; |
.equ SEG115 = 7 ; |
; LCDDR5 - LCD Data Register 5 |
.equ SEG100 = 0 ; |
.equ SEG101 = 1 ; |
.equ SEG102 = 2 ; |
.equ SEG103 = 3 ; |
.equ SEG104 = 4 ; |
.equ SEG105 = 5 ; |
.equ SEG106 = 6 ; |
.equ SEG107 = 7 ; |
; LCDDR3 - LCD Data Register 3 |
.equ SEG024 = 0 ; |
; LCDDR2 - LCD Data Register 2 |
.equ SEG016 = 0 ; |
.equ SEG017 = 1 ; |
.equ SEG018 = 2 ; |
.equ SEG019 = 3 ; |
.equ SEG020 = 4 ; |
.equ SEG021 = 5 ; |
.equ SEG022 = 6 ; |
.equ SEG023 = 7 ; |
; LCDDR1 - LCD Data Register 1 |
.equ SEG008 = 0 ; |
.equ SEG009 = 1 ; |
.equ SEG010 = 2 ; |
.equ SEG011 = 3 ; |
.equ SEG012 = 4 ; |
.equ SEG013 = 5 ; |
.equ SEG014 = 6 ; |
.equ SEG015 = 7 ; |
; LCDDR0 - LCD Data Register 0 |
.equ SEG000 = 0 ; |
.equ SEG001 = 1 ; |
.equ SEG002 = 2 ; |
.equ SEG003 = 3 ; |
.equ SEG004 = 4 ; |
.equ SEG005 = 5 ; |
.equ SEG006 = 6 ; |
.equ SEG007 = 7 ; |
; ***** EXTERNAL_INTERRUPT *********** |
; EICRA - External Interrupt Control Register A |
.equ ISC00 = 0 ; External Interrupt Sense Control 0 Bit 0 |
.equ ISC01 = 1 ; External Interrupt Sense Control 0 Bit 1 |
; EIMSK - External Interrupt Mask Register |
.equ INT0 = 0 ; External Interrupt Request 0 Enable |
.equ PCIE0 = 4 ; Pin Change Interrupt Enable 0 |
.equ PCIE1 = 5 ; Pin Change Interrupt Enable 1 |
.equ PCIE2 = 6 ; Pin Change Interrupt Enable 2 |
.equ PCIE3 = 7 ; Pin Change Interrupt Enable 3 |
; EIFR - External Interrupt Flag Register |
.equ INTF0 = 0 ; External Interrupt Flag 0 |
.equ PCIF0 = 4 ; Pin Change Interrupt Flag 0 |
.equ PCIF1 = 5 ; Pin Change Interrupt Flag 1 |
.equ PCIF2 = 6 ; Pin Change Interrupt Flag 2 |
.equ PCIF3 = 7 ; Pin Change Interrupt Flag 3 |
; ***** CPU ************************** |
; SREG - Status Register |
.equ SREG_C = 0 ; Carry Flag |
.equ SREG_Z = 1 ; Zero Flag |
.equ SREG_N = 2 ; Negative Flag |
.equ SREG_V = 3 ; Two's Complement Overflow Flag |
.equ SREG_S = 4 ; Sign Bit |
.equ SREG_H = 5 ; Half Carry Flag |
.equ SREG_T = 6 ; Bit Copy Storage |
.equ SREG_I = 7 ; Global Interrupt Enable |
; MCUCR - MCU Control Register |
.equ IVCE = 0 ; Interrupt Vector Change Enable |
.equ IVSEL = 1 ; Interrupt Vector Select |
.equ PUD = 4 ; Pull-up disable |
; MCUSR - MCU Status Register |
.equ PORF = 0 ; Power-on reset flag |
.equ EXTRF = 1 ; External Reset Flag |
.equ BORF = 2 ; Brown-out Reset Flag |
.equ WDRF = 3 ; Watchdog Reset Flag |
;.equ JTRF = 4 ; JTAG Reset Flag |
; OSCCAL - Oscillator Calibration Value |
.equ CAL0 = 0 ; Oscillator Calibration Value Bit0 |
.equ CAL1 = 1 ; Oscillator Calibration Value Bit1 |
.equ CAL2 = 2 ; Oscillator Calibration Value Bit2 |
.equ CAL3 = 3 ; Oscillator Calibration Value Bit3 |
.equ CAL4 = 4 ; Oscillator Calibration Value Bit4 |
.equ CAL5 = 5 ; Oscillator Calibration Value Bit5 |
.equ CAL6 = 6 ; Oscillator Calibration Value Bit6 |
.equ CAL7 = 7 ; Oscillator Calibration Value Bit7 |
; CLKPR - Clock Prescale Register |
.equ CLKPS0 = 0 ; Clock Prescaler Select Bit 0 |
.equ CLKPS1 = 1 ; Clock Prescaler Select Bit 1 |
.equ CLKPS2 = 2 ; Clock Prescaler Select Bit 2 |
.equ CLKPS3 = 3 ; Clock Prescaler Select Bit 3 |
.equ CLKPCE = 7 ; Clock Prescaler Change Enable |
; PRR - Power Reduction Register |
.equ PRADC = 0 ; Power Reduction ADC |
.equ PRUSART0 = 1 ; Power Reduction USART |
.equ PRSPI = 2 ; Power Reduction Serial Peripheral Interface |
.equ PRTIM1 = 3 ; Power Reduction Timer/Counter1 |
.equ PRLCD = 4 ; Power Reduction LCD |
; SMCR - Sleep Mode Control Register |
.equ SE = 0 ; Sleep Enable |
.equ SM0 = 1 ; Sleep Mode Select bit 0 |
.equ SM1 = 2 ; Sleep Mode Select bit 1 |
.equ SM2 = 3 ; Sleep Mode Select bit 2 |
; GPIOR2 - General Purpose IO Register 2 |
.equ GPIOR20 = 0 ; General Purpose IO Register 2 bit 0 |
.equ GPIOR21 = 1 ; General Purpose IO Register 2 bit 1 |
.equ GPIOR22 = 2 ; General Purpose IO Register 2 bit 2 |
.equ GPIOR23 = 3 ; General Purpose IO Register 2 bit 3 |
.equ GPIOR24 = 4 ; General Purpose IO Register 2 bit 4 |
.equ GPIOR25 = 5 ; General Purpose IO Register 2 bit 5 |
.equ GPIOR26 = 6 ; General Purpose IO Register 2 bit 6 |
.equ GPIOR27 = 7 ; General Purpose IO Register 2 bit 7 |
; GPIOR1 - General Purpose IO Register 1 |
.equ GPIOR10 = 0 ; General Purpose IO Register 1 bit 0 |
.equ GPIOR11 = 1 ; General Purpose IO Register 1 bit 1 |
.equ GPIOR12 = 2 ; General Purpose IO Register 1 bit 2 |
.equ GPIOR13 = 3 ; General Purpose IO Register 1 bit 3 |
.equ GPIOR14 = 4 ; General Purpose IO Register 1 bit 4 |
.equ GPIOR15 = 5 ; General Purpose IO Register 1 bit 5 |
.equ GPIOR16 = 6 ; General Purpose IO Register 1 bit 6 |
.equ GPIOR17 = 7 ; General Purpose IO Register 1 bit 7 |
; GPIOR0 - General Purpose IO Register 0 |
.equ GPIOR00 = 0 ; General Purpose IO Register 0 bit 0 |
.equ GPIOR01 = 1 ; General Purpose IO Register 0 bit 1 |
.equ GPIOR02 = 2 ; General Purpose IO Register 0 bit 2 |
.equ GPIOR03 = 3 ; General Purpose IO Register 0 bit 3 |
.equ GPIOR04 = 4 ; General Purpose IO Register 0 bit 4 |
.equ GPIOR05 = 5 ; General Purpose IO Register 0 bit 5 |
.equ GPIOR06 = 6 ; General Purpose IO Register 0 bit 6 |
.equ GPIOR07 = 7 ; General Purpose IO Register 0 bit 7 |
; ***** USI ************************** |
; USIDR - USI Data Register |
.equ USIDR0 = 0 ; USI Data Register bit 0 |
.equ USIDR1 = 1 ; USI Data Register bit 1 |
.equ USIDR2 = 2 ; USI Data Register bit 2 |
.equ USIDR3 = 3 ; USI Data Register bit 3 |
.equ USIDR4 = 4 ; USI Data Register bit 4 |
.equ USIDR5 = 5 ; USI Data Register bit 5 |
.equ USIDR6 = 6 ; USI Data Register bit 6 |
.equ USIDR7 = 7 ; USI Data Register bit 7 |
; USISR - USI Status Register |
.equ USICNT0 = 0 ; USI Counter Value Bit 0 |
.equ USICNT1 = 1 ; USI Counter Value Bit 1 |
.equ USICNT2 = 2 ; USI Counter Value Bit 2 |
.equ USICNT3 = 3 ; USI Counter Value Bit 3 |
.equ USIDC = 4 ; Data Output Collision |
.equ USIPF = 5 ; Stop Condition Flag |
.equ USIOIF = 6 ; Counter Overflow Interrupt Flag |
.equ USISIF = 7 ; Start Condition Interrupt Flag |
; USICR - USI Control Register |
.equ USITC = 0 ; Toggle Clock Port Pin |
.equ USICLK = 1 ; Clock Strobe |
.equ USICS0 = 2 ; USI Clock Source Select Bit 0 |
.equ USICS1 = 3 ; USI Clock Source Select Bit 1 |
.equ USIWM0 = 4 ; USI Wire Mode Bit 0 |
.equ USIWM1 = 5 ; USI Wire Mode Bit 1 |
.equ USIOIE = 6 ; Counter Overflow Interrupt Enable |
.equ USISIE = 7 ; Start Condition Interrupt Enable |
; ***** AD_CONVERTER ***************** |
; ADMUX - The ADC multiplexer Selection Register |
.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits |
.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits |
.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits |
.equ MUX3 = 3 ; Analog Channel and Gain Selection Bits |
.equ MUX4 = 4 ; Analog Channel and Gain Selection Bits |
.equ ADLAR = 5 ; Left Adjust Result |
.equ REFS0 = 6 ; Reference Selection Bit 0 |
.equ REFS1 = 7 ; Reference Selection Bit 1 |
; ADCSRA - The ADC Control and Status register |
.equ ADPS0 = 0 ; ADC Prescaler Select Bits |
.equ ADPS1 = 1 ; ADC Prescaler Select Bits |
.equ ADPS2 = 2 ; ADC Prescaler Select Bits |
.equ ADIE = 3 ; ADC Interrupt Enable |
.equ ADIF = 4 ; ADC Interrupt Flag |
.equ ADATE = 5 ; ADC Auto Trigger Enable |
.equ ADSC = 6 ; ADC Start Conversion |
.equ ADEN = 7 ; ADC Enable |
; ADCH - ADC Data Register High Byte |
.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0 |
.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1 |
.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2 |
.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3 |
.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4 |
.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5 |
.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6 |
.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7 |
; ADCL - ADC Data Register Low Byte |
.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0 |
.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1 |
.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2 |
.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3 |
.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4 |
.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5 |
.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6 |
.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7 |
; ADCSRB - ADC Control and Status Register B |
.equ ADTS0 = 0 ; ADC Auto Trigger Source 0 |
.equ ADTS1 = 1 ; ADC Auto Trigger Source 1 |
.equ ADTS2 = 2 ; ADC Auto Trigger Source 2 |
; DIDR0 - Digital Input Disable Register 0 |
.equ ADC0D = 0 ; ADC0 Digital input Disable |
.equ ADC1D = 1 ; ADC1 Digital input Disable |
.equ ADC2D = 2 ; ADC2 Digital input Disable |
.equ ADC3D = 3 ; ADC3 Digital input Disable |
.equ ADC4D = 4 ; ADC4 Digital input Disable |
.equ ADC5D = 5 ; ADC5 Digital input Disable |
.equ ADC6D = 6 ; ADC6 Digital input Disable |
.equ ADC7D = 7 ; ADC7 Digital input Disable |
; ***** BOOT_LOAD ******************** |
; SPMCSR - Store Program Memory Control Register |
.equ SPMCR = SPMCSR ; For compatibility |
.equ SPMEN = 0 ; Store Program Memory Enable |
.equ PGERS = 1 ; Page Erase |
.equ PGWRT = 2 ; Page Write |
.equ BLBSET = 3 ; Boot Lock Bit Set |
.equ RWWSRE = 4 ; Read While Write section read enable |
.equ ASRE = RWWSRE ; For compatibility |
.equ RWWSB = 6 ; Read While Write Section Busy |
.equ ASB = RWWSB ; For compatibility |
.equ SPMIE = 7 ; SPM Interrupt Enable |
; ***** USART0 *********************** |
; UDR - USART I/O Data Register |
.equ UDR0 = UDR ; For compatibility |
.equ UDR00 = 0 ; USART I/O Data Register bit 0 |
.equ UDR01 = 1 ; USART I/O Data Register bit 1 |
.equ UDR02 = 2 ; USART I/O Data Register bit 2 |
.equ UDR03 = 3 ; USART I/O Data Register bit 3 |
.equ UDR04 = 4 ; USART I/O Data Register bit 4 |
.equ UDR05 = 5 ; USART I/O Data Register bit 5 |
.equ UDR06 = 6 ; USART I/O Data Register bit 6 |
.equ UDR07 = 7 ; USART I/O Data Register bit 7 |
; UCSRA - USART Control and Status Register A |
.equ UCSR0A = UCSRA ; For compatibility |
.equ USR = UCSRA ; For compatibility |
.equ MPCM = 0 ; Multi-processor Communication Mode |
.equ MPCM0 = MPCM ; For compatibility |
.equ U2X = 1 ; Double the USART Transmission Speed |
.equ U2X0 = U2X ; For compatibility |
.equ UPE = 2 ; USART Parity Error |
.equ UPE0 = UPE ; For compatibility |
.equ DOR = 3 ; Data OverRun |
.equ DOR0 = DOR ; For compatibility |
.equ FE = 4 ; Framing Error |
.equ FE0 = FE ; For compatibility |
.equ UDRE = 5 ; USART Data Register Empty |
.equ UDRE0 = UDRE ; For compatibility |
.equ TXC = 6 ; USART Transmit Complete |
.equ TXC0 = TXC ; For compatibility |
.equ RXC = 7 ; USART Receive Complete |
.equ RXC0 = RXC ; For compatibility |
; UCSRB - USART Control and Status Register B |
.equ UCSR0B = UCSRB ; For compatibility |
.equ UCR = UCSRB ; For compatibility |
.equ TXB8 = 0 ; Transmit Data Bit 8 |
.equ TXB80 = TXB8 ; For compatibility |
.equ RXB8 = 1 ; Receive Data Bit 8 |
.equ RXB80 = RXB8 ; For compatibility |
.equ UCSZ2 = 2 ; Character Size |
.equ UCSZ02 = UCSZ2 ; For compatibility |
.equ TXEN = 3 ; Transmitter Enable |
.equ TXEN0 = TXEN ; For compatibility |
.equ RXEN = 4 ; Receiver Enable |
.equ RXEN0 = RXEN ; For compatibility |
.equ UDRIE = 5 ; USART Data Register Empty Interrupt Enable |
.equ UDRIE0 = UDRIE ; For compatibility |
.equ TXCIE = 6 ; TX Complete Interrupt Enable |
.equ TXCIE0 = TXCIE ; For compatibility |
.equ RXCIE = 7 ; RX Complete Interrupt Enable |
.equ RXCIE0 = RXCIE ; For compatibility |
; UCSRC - USART Control and Status Register C |
.equ UCSR0C = UCSRC ; For compatibility |
.equ UCPOL = 0 ; Clock Polarity |
.equ UCPOL0 = UCPOL ; For compatibility |
.equ UCSZ0 = 1 ; Character Size |
.equ UCSZ00 = UCSZ0 ; For compatibility |
.equ UCSZ1 = 2 ; Character Size |
.equ UCSZ01 = UCSZ1 ; For compatibility |
.equ USBS = 3 ; Stop Bit Select |
.equ USBS0 = USBS ; For compatibility |
.equ UPM0 = 4 ; Parity Mode Bit 0 |
.equ UPM00 = UPM0 ; For compatibility |
.equ UPM1 = 5 ; Parity Mode Bit 1 |
.equ UPM01 = UPM1 ; For compatibility |
.equ UMSEL = 6 ; USART Mode Select |
.equ UMSEL0 = UMSEL ; For compatibility |
.equ UBRR0H = UBRRH ; For compatibility |
.equ UBRR0L = UBRRL ; For compatibility |
.equ UBRR0 = UBRRL ; For compatibility |
.equ UBRR = UBRRL ; For compatibility |
; ***** LOCKSBITS ******************************************************** |
.equ LB1 = 0 ; Lock bit |
.equ LB2 = 1 ; Lock bit |
.equ BLB01 = 2 ; Boot Lock bit |
.equ BLB02 = 3 ; Boot Lock bit |
.equ BLB11 = 4 ; Boot lock bit |
.equ BLB12 = 5 ; Boot lock bit |
; ***** FUSES ************************************************************ |
; LOW fuse bits |
.equ CKSEL0 = 0 ; Select Clock Source |
.equ CKSEL1 = 1 ; Select Clock Source |
.equ CKSEL2 = 2 ; Select Clock Source |
.equ CKSEL3 = 3 ; Select Clock Source |
.equ SUT0 = 4 ; Select start-up time |
.equ SUT1 = 5 ; Select start-up time |
.equ CKOUT = 6 ; Oscillator options |
.equ CLKDIV8 = 7 ; Divide clock by 8 |
; HIGH fuse bits |
.equ BOOTRST = 0 ; Select Reset Vector |
.equ BOOTSZ0 = 1 ; Select Boot Size |
.equ BOOTSZ1 = 2 ; Select Boot Size |
.equ EESAVE = 3 ; EEPROM memory is preserved through chip erase |
.equ WDTON = 4 ; Watchdog timer always on |
.equ SPIEN = 5 ; Enable Serial programming and Data Downloading |
.equ JTAGEN = 6 ; Enable JTAG |
.equ OCDEN = 7 ; Enable OCD |
; EXTENDED fuse bits |
.equ RSTDISBL = 0 ; External Reset Disable |
.equ BODLEVEL0 = 1 ; Brown-out Detector trigger level |
.equ BODLEVEL1 = 2 ; Brown-out Detector trigger level |
; ***** CPU REGISTER DEFINITIONS ***************************************** |
.def XH = r27 |
.def XL = r26 |
.def YH = r29 |
.def YL = r28 |
.def ZH = r31 |
.def ZL = r30 |
; ***** DATA MEMORY DECLARATIONS ***************************************** |
.equ FLASHEND = 0x3fff ; Note: Word address |
.equ IOEND = 0x00ff |
.equ SRAM_START = 0x0100 |
.equ SRAM_SIZE = 2048 |
.equ RAMEND = 0x08ff |
.equ XRAMEND = 0x0000 |
.equ E2END = 0x03ff |
.equ EEPROMEND = 0x03ff |
.equ EEADRBITS = 10 |
#pragma AVRPART MEMORY PROG_FLASH 32768 |
#pragma AVRPART MEMORY EEPROM 1024 |
#pragma AVRPART MEMORY INT_SRAM SIZE 2048 |
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x100 |
; ***** BOOTLOADER DECLARATIONS ****************************************** |
.equ NRWW_START_ADDR = 0x3800 |
.equ NRWW_STOP_ADDR = 0x3fff |
.equ RWW_START_ADDR = 0x0 |
.equ RWW_STOP_ADDR = 0x37ff |
.equ PAGESIZE = 64 |
.equ FIRSTBOOTSTART = 0x3f00 |
.equ SECONDBOOTSTART = 0x3e00 |
.equ THIRDBOOTSTART = 0x3c00 |
.equ FOURTHBOOTSTART = 0x3800 |
.equ SMALLBOOTSTART = FIRSTBOOTSTART |
.equ LARGEBOOTSTART = FOURTHBOOTSTART |
; ***** INTERRUPT VECTORS ************************************************ |
.equ INT0addr = 0x0002 ; External Interrupt Request 0 |
.equ PCI0addr = 0x0004 ; Pin Change Interrupt Request 0 |
.equ PCI1addr = 0x0006 ; Pin Change Interrupt Request 1 |
.equ OC2addr = 0x0008 ; Timer/Counter2 Compare Match |
.equ OVF2addr = 0x000a ; Timer/Counter2 Overflow |
.equ ICP1addr = 0x000c ; Timer/Counter1 Capture Event |
.equ OC1Aaddr = 0x000e ; Timer/Counter1 Compare Match A |
.equ OC1Baddr = 0x0010 ; Timer/Counter Compare Match B |
.equ OVF1addr = 0x0012 ; Timer/Counter1 Overflow |
.equ OC0addr = 0x0014 ; Timer/Counter0 Compare Match |
.equ OVF0addr = 0x0016 ; Timer/Counter0 Overflow |
.equ SPIaddr = 0x0018 ; SPI Serial Transfer Complete |
.equ URXC0addr = 0x001a ; USART0, Rx Complete |
.equ URXCaddr = 0x001a ; For compatibility |
.equ UDRE0addr = 0x001c ; USART0 Data register Empty |
.equ UDREaddr = 0x001c ; For compatibility |
.equ UTXC0addr = 0x001e ; USART0, Tx Complete |
.equ UTXCaddr = 0x001e ; For compatibility |
.equ USI_STARTaddr = 0x0020 ; USI Start Condition |
.equ USI_OVFaddr = 0x0022 ; USI Overflow |
.equ ACIaddr = 0x0024 ; Analog Comparator |
.equ ADCCaddr = 0x0026 ; ADC Conversion Complete |
.equ ERDYaddr = 0x0028 ; EEPROM Ready |
.equ SPMRaddr = 0x002a ; Store Program Memory Read |
.equ LCDSFaddr = 0x002c ; LCD Start of Frame |
.equ INT_VECTORS_SIZE = 46 ; size in words |
#endif /* _M329DEF_INC_ */ |
; ***** END OF FILE ****************************************************** |
/contrib/toolchain/avra/includes/m32def.inc |
---|
0,0 → 1,808 |
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** |
;***** Created: 2005-01-11 10:31 ******* Source: ATmega32.xml ************ |
;************************************************************************* |
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y |
;* |
;* Number : AVR000 |
;* File Name : "m32def.inc" |
;* Title : Register/Bit Definitions for the ATmega32 |
;* Date : 2005-01-11 |
;* Version : 2.14 |
;* Support E-mail : avr@atmel.com |
;* Target MCU : ATmega32 |
;* |
;* DESCRIPTION |
;* When including this file in the assembly program file, all I/O register |
;* names and I/O register bit names appearing in the data book can be used. |
;* In addition, the six registers forming the three data pointers X, Y and |
;* Z have been assigned names XL - ZH. Highest RAM address for Internal |
;* SRAM is also defined |
;* |
;* The Register names are represented by their hexadecimal address. |
;* |
;* The Register Bit names are represented by their bit number (0-7). |
;* |
;* Please observe the difference in using the bit names with instructions |
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" |
;* (skip if bit in register set/cleared). The following example illustrates |
;* this: |
;* |
;* in r16,PORTB ;read PORTB latch |
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) |
;* out PORTB,r16 ;output to PORTB |
;* |
;* in r16,TIFR ;read the Timer Interrupt Flag Register |
;* sbrc r16,TOV0 ;test the overflow flag (use bit#) |
;* rjmp TOV0_is_set ;jump if set |
;* ... ;otherwise do something else |
;************************************************************************* |
#ifndef _M32DEF_INC_ |
#define _M32DEF_INC_ |
#pragma partinc 0 |
; ***** SPECIFY DEVICE *************************************************** |
.device ATmega32 |
#pragma AVRPART ADMIN PART_NAME ATmega32 |
.equ SIGNATURE_000 = 0x1e |
.equ SIGNATURE_001 = 0x95 |
.equ SIGNATURE_002 = 0x02 |
#pragma AVRPART CORE CORE_VERSION V2E |
; ***** I/O REGISTER DEFINITIONS ***************************************** |
; NOTE: |
; Definitions marked "MEMORY MAPPED"are extended I/O ports |
; and cannot be used with IN/OUT instructions |
.equ SREG = 0x3f |
.equ SPH = 0x3e |
.equ SPL = 0x3d |
.equ OCR0 = 0x3c |
.equ GICR = 0x3b |
.equ GIFR = 0x3a |
.equ TIMSK = 0x39 |
.equ TIFR = 0x38 |
.equ SPMCR = 0x37 |
.equ TWCR = 0x36 |
.equ MCUCR = 0x35 |
.equ MCUCSR = 0x34 |
.equ TCCR0 = 0x33 |
.equ TCNT0 = 0x32 |
.equ OSCCAL = 0x31 |
.equ OCDR = 0x31 |
.equ SFIOR = 0x30 |
.equ TCCR1A = 0x2f |
.equ TCCR1B = 0x2e |
.equ TCNT1H = 0x2d |
.equ TCNT1L = 0x2c |
.equ OCR1AH = 0x2b |
.equ OCR1AL = 0x2a |
.equ OCR1BH = 0x29 |
.equ OCR1BL = 0x28 |
.equ ICR1H = 0x27 |
.equ ICR1L = 0x26 |
.equ TCCR2 = 0x25 |
.equ TCNT2 = 0x24 |
.equ OCR2 = 0x23 |
.equ ASSR = 0x22 |
.equ WDTCR = 0x21 |
.equ UBRRH = 0x20 |
.equ UCSRC = 0x20 |
.equ EEARH = 0x1f |
.equ EEARL = 0x1e |
.equ EEDR = 0x1d |
.equ EECR = 0x1c |
.equ PORTA = 0x1b |
.equ DDRA = 0x1a |
.equ PINA = 0x19 |
.equ PORTB = 0x18 |
.equ DDRB = 0x17 |
.equ PINB = 0x16 |
.equ PORTC = 0x15 |
.equ DDRC = 0x14 |
.equ PINC = 0x13 |
.equ PORTD = 0x12 |
.equ DDRD = 0x11 |
.equ PIND = 0x10 |
.equ SPDR = 0x0f |
.equ SPSR = 0x0e |
.equ SPCR = 0x0d |
.equ UDR = 0x0c |
.equ UCSRA = 0x0b |
.equ UCSRB = 0x0a |
.equ UBRRL = 0x09 |
.equ ACSR = 0x08 |
.equ ADMUX = 0x07 |
.equ ADCSRA = 0x06 |
.equ ADCH = 0x05 |
.equ ADCL = 0x04 |
.equ TWDR = 0x03 |
.equ TWAR = 0x02 |
.equ TWSR = 0x01 |
.equ TWBR = 0x00 |
; ***** BIT DEFINITIONS ************************************************** |
; ***** EEPROM *********************** |
; EEDR - EEPROM Data Register |
.equ EEDR0 = 0 ; EEPROM Data Register bit 0 |
.equ EEDR1 = 1 ; EEPROM Data Register bit 1 |
.equ EEDR2 = 2 ; EEPROM Data Register bit 2 |
.equ EEDR3 = 3 ; EEPROM Data Register bit 3 |
.equ EEDR4 = 4 ; EEPROM Data Register bit 4 |
.equ EEDR5 = 5 ; EEPROM Data Register bit 5 |
.equ EEDR6 = 6 ; EEPROM Data Register bit 6 |
.equ EEDR7 = 7 ; EEPROM Data Register bit 7 |
; EECR - EEPROM Control Register |
.equ EERE = 0 ; EEPROM Read Enable |
.equ EEWE = 1 ; EEPROM Write Enable |
.equ EEMWE = 2 ; EEPROM Master Write Enable |
.equ EERIE = 3 ; EEPROM Ready Interrupt Enable |
; ***** WATCHDOG ********************* |
; WDTCR - Watchdog Timer Control Register |
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 |
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 |
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 |
.equ WDE = 3 ; Watch Dog Enable |
.equ WDTOE = 4 ; RW |
.equ WDDE = WDTOE ; For compatibility |
; ***** EXTERNAL_INTERRUPT *********** |
; GICR - General Interrupt Control Register |
.equ GIMSK = GICR ; For compatibility |
.equ IVCE = 0 ; Interrupt Vector Change Enable |
.equ IVSEL = 1 ; Interrupt Vector Select |
.equ INT2 = 5 ; External Interrupt Request 2 Enable |
.equ INT0 = 6 ; External Interrupt Request 0 Enable |
.equ INT1 = 7 ; External Interrupt Request 1 Enable |
; GIFR - General Interrupt Flag Register |
.equ INTF2 = 5 ; External Interrupt Flag 2 |
.equ INTF0 = 6 ; External Interrupt Flag 0 |
.equ INTF1 = 7 ; External Interrupt Flag 1 |
; MCUCR - General Interrupt Control Register |
.equ ISC00 = 0 ; Interrupt Sense Control 0 Bit 0 |
.equ ISC01 = 1 ; Interrupt Sense Control 0 Bit 1 |
.equ ISC10 = 2 ; Interrupt Sense Control 1 Bit 0 |
.equ ISC11 = 3 ; Interrupt Sense Control 1 Bit 1 |
; MCUCSR - MCU Control And Status Register |
.equ ISC2 = 6 ; Interrupt Sense Control 2 |
; ***** TIMER_COUNTER_0 ************** |
; TCCR0 - Timer/Counter Control Register |
.equ CS00 = 0 ; Clock Select 1 |
.equ CS01 = 1 ; Clock Select 1 |
.equ CS02 = 2 ; Clock Select 2 |
.equ WGM01 = 3 ; Waveform Generation Mode 1 |
.equ CTC0 = WGM01 ; For compatibility |
.equ COM00 = 4 ; Compare match Output Mode 0 |
.equ COM01 = 5 ; Compare Match Output Mode 1 |
.equ WGM00 = 6 ; Waveform Generation Mode |
.equ PWM0 = WGM00 ; For compatibility |
.equ FOC0 = 7 ; Force Output Compare |
; TCNT0 - Timer/Counter Register |
.equ TCNT0_0 = 0 ; |
.equ TCNT0_1 = 1 ; |
.equ TCNT0_2 = 2 ; |
.equ TCNT0_3 = 3 ; |
.equ TCNT0_4 = 4 ; |
.equ TCNT0_5 = 5 ; |
.equ TCNT0_6 = 6 ; |
.equ TCNT0_7 = 7 ; |
; OCR0 - Output Compare Register |
.equ OCR0_0 = 0 ; |
.equ OCR0_1 = 1 ; |
.equ OCR0_2 = 2 ; |
.equ OCR0_3 = 3 ; |
.equ OCR0_4 = 4 ; |
.equ OCR0_5 = 5 ; |
.equ OCR0_6 = 6 ; |
.equ OCR0_7 = 7 ; |
; TIMSK - Timer/Counter Interrupt Mask Register |
.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable |
.equ OCIE0 = 1 ; Timer/Counter0 Output Compare Match Interrupt register |
; TIFR - Timer/Counter Interrupt Flag register |
.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag |
.equ OCF0 = 1 ; Output Compare Flag 0 |
; ***** TIMER_COUNTER_2 ************** |
; TIMSK - Timer/Counter Interrupt Mask register |
.equ TOIE2 = 6 ; Timer/Counter2 Overflow Interrupt Enable |
.equ OCIE2 = 7 ; Timer/Counter2 Output Compare Match Interrupt Enable |
; TIFR - Timer/Counter Interrupt Flag Register |
.equ TOV2 = 6 ; Timer/Counter2 Overflow Flag |
.equ OCF2 = 7 ; Output Compare Flag 2 |
; TCCR2 - Timer/Counter2 Control Register |
.equ CS20 = 0 ; Clock Select bit 0 |
.equ CS21 = 1 ; Clock Select bit 1 |
.equ CS22 = 2 ; Clock Select bit 2 |
.equ CTC2 = 3 ; Clear Timer/Counter2 on Compare Match |
.equ COM20 = 4 ; Compare Output Mode bit 0 |
.equ COM21 = 5 ; Compare Output Mode bit 1 |
.equ PWM2 = 6 ; Pulse Width Modulator Enable |
.equ FOC2 = 7 ; Force Output Compare |
; TCNT2 - Timer/Counter2 |
.equ TCNT2_0 = 0 ; Timer/Counter 2 bit 0 |
.equ TCNT2_1 = 1 ; Timer/Counter 2 bit 1 |
.equ TCNT2_2 = 2 ; Timer/Counter 2 bit 2 |
.equ TCNT2_3 = 3 ; Timer/Counter 2 bit 3 |
.equ TCNT2_4 = 4 ; Timer/Counter 2 bit 4 |
.equ TCNT2_5 = 5 ; Timer/Counter 2 bit 5 |
.equ TCNT2_6 = 6 ; Timer/Counter 2 bit 6 |
.equ TCNT2_7 = 7 ; Timer/Counter 2 bit 7 |
; OCR2 - Timer/Counter2 Output Compare Register |
.equ OCR2_0 = 0 ; Timer/Counter2 Output Compare Register Bit 0 |
.equ OCR2_1 = 1 ; Timer/Counter2 Output Compare Register Bit 1 |
.equ OCR2_2 = 2 ; Timer/Counter2 Output Compare Register Bit 2 |
.equ OCR2_3 = 3 ; Timer/Counter2 Output Compare Register Bit 3 |
.equ OCR2_4 = 4 ; Timer/Counter2 Output Compare Register Bit 4 |
.equ OCR2_5 = 5 ; Timer/Counter2 Output Compare Register Bit 5 |
.equ OCR2_6 = 6 ; Timer/Counter2 Output Compare Register Bit 6 |
.equ OCR2_7 = 7 ; Timer/Counter2 Output Compare Register Bit 7 |
; ASSR - Asynchronous Status Register |
.equ TCR2UB = 0 ; Timer/counter Control Register2 Update Busy |
.equ OCR2UB = 1 ; Output Compare Register2 Update Busy |
.equ TCN2UB = 2 ; Timer/Counter2 Update Busy |
.equ AS2 = 3 ; Asynchronous Timer/counter2 |
; ***** TIMER_COUNTER_1 ************** |
; TIMSK - Timer/Counter Interrupt Mask Register |
.equ TOIE1 = 2 ; Timer/Counter1 Overflow Interrupt Enable |
.equ OCIE1B = 3 ; Timer/Counter1 Output CompareB Match Interrupt Enable |
.equ OCIE1A = 4 ; Timer/Counter1 Output CompareA Match Interrupt Enable |
.equ TICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable |
; TIFR - Timer/Counter Interrupt Flag register |
.equ TOV1 = 2 ; Timer/Counter1 Overflow Flag |
.equ OCF1B = 3 ; Output Compare Flag 1B |
.equ OCF1A = 4 ; Output Compare Flag 1A |
.equ ICF1 = 5 ; Input Capture Flag 1 |
; TCCR1A - Timer/Counter1 Control Register A |
.equ WGM10 = 0 ; Waveform Generation Mode |
.equ PWM10 = WGM10 ; For compatibility |
.equ WGM11 = 1 ; Waveform Generation Mode |
.equ PWM11 = WGM11 ; For compatibility |
.equ FOC1B = 2 ; Force Output Compare 1B |
.equ FOC1A = 3 ; Force Output Compare 1A |
.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0 |
.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1 |
.equ COM1A0 = 6 ; Comparet Ouput Mode 1A, bit 0 |
.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1 |
; TCCR1B - Timer/Counter1 Control Register B |
.equ CS10 = 0 ; Prescaler source of Timer/Counter 1 |
.equ CS11 = 1 ; Prescaler source of Timer/Counter 1 |
.equ CS12 = 2 ; Prescaler source of Timer/Counter 1 |
.equ WGM12 = 3 ; Waveform Generation Mode |
.equ CTC10 = WGM12 ; For compatibility |
.equ CTC1 = WGM12 ; For compatibility |
.equ WGM13 = 4 ; Waveform Generation Mode |
.equ CTC11 = WGM13 ; For compatibility |
.equ ICES1 = 6 ; Input Capture 1 Edge Select |
.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler |
; ***** SPI ************************** |
; SPDR - SPI Data Register |
.equ SPDR0 = 0 ; SPI Data Register bit 0 |
.equ SPDR1 = 1 ; SPI Data Register bit 1 |
.equ SPDR2 = 2 ; SPI Data Register bit 2 |
.equ SPDR3 = 3 ; SPI Data Register bit 3 |
.equ SPDR4 = 4 ; SPI Data Register bit 4 |
.equ SPDR5 = 5 ; SPI Data Register bit 5 |
.equ SPDR6 = 6 ; SPI Data Register bit 6 |
.equ SPDR7 = 7 ; SPI Data Register bit 7 |
; SPSR - SPI Status Register |
.equ SPI2X = 0 ; Double SPI Speed Bit |
.equ WCOL = 6 ; Write Collision Flag |
.equ SPIF = 7 ; SPI Interrupt Flag |
; SPCR - SPI Control Register |
.equ SPR0 = 0 ; SPI Clock Rate Select 0 |
.equ SPR1 = 1 ; SPI Clock Rate Select 1 |
.equ CPHA = 2 ; Clock Phase |
.equ CPOL = 3 ; Clock polarity |
.equ MSTR = 4 ; Master/Slave Select |
.equ DORD = 5 ; Data Order |
.equ SPE = 6 ; SPI Enable |
.equ SPIE = 7 ; SPI Interrupt Enable |
; ***** USART ************************ |
; UDR - USART I/O Data Register |
.equ UDR0 = 0 ; USART I/O Data Register bit 0 |
.equ UDR1 = 1 ; USART I/O Data Register bit 1 |
.equ UDR2 = 2 ; USART I/O Data Register bit 2 |
.equ UDR3 = 3 ; USART I/O Data Register bit 3 |
.equ UDR4 = 4 ; USART I/O Data Register bit 4 |
.equ UDR5 = 5 ; USART I/O Data Register bit 5 |
.equ UDR6 = 6 ; USART I/O Data Register bit 6 |
.equ UDR7 = 7 ; USART I/O Data Register bit 7 |
; UCSRA - USART Control and Status Register A |
.equ USR = UCSRA ; For compatibility |
.equ MPCM = 0 ; Multi-processor Communication Mode |
.equ U2X = 1 ; Double the USART transmission speed |
.equ UPE = 2 ; Parity Error |
.equ PE = UPE ; For compatibility |
.equ DOR = 3 ; Data overRun |
.equ FE = 4 ; Framing Error |
.equ UDRE = 5 ; USART Data Register Empty |
.equ TXC = 6 ; USART Transmitt Complete |
.equ RXC = 7 ; USART Receive Complete |
; UCSRB - USART Control and Status Register B |
.equ UCR = UCSRB ; For compatibility |
.equ TXB8 = 0 ; Transmit Data Bit 8 |
.equ RXB8 = 1 ; Receive Data Bit 8 |
.equ UCSZ2 = 2 ; Character Size |
.equ CHR9 = UCSZ2 ; For compatibility |
.equ TXEN = 3 ; Transmitter Enable |
.equ RXEN = 4 ; Receiver Enable |
.equ UDRIE = 5 ; USART Data register Empty Interrupt Enable |
.equ TXCIE = 6 ; TX Complete Interrupt Enable |
.equ RXCIE = 7 ; RX Complete Interrupt Enable |
; UCSRC - USART Control and Status Register C |
.equ UCPOL = 0 ; Clock Polarity |
.equ UCSZ0 = 1 ; Character Size |
.equ UCSZ1 = 2 ; Character Size |
.equ USBS = 3 ; Stop Bit Select |
.equ UPM0 = 4 ; Parity Mode Bit 0 |
.equ UPM1 = 5 ; Parity Mode Bit 1 |
.equ UMSEL = 6 ; USART Mode Select |
.equ URSEL = 7 ; Register Select |
.equ UBRRHI = UBRRH ; For compatibility |
; ***** TWI ************************** |
; TWBR - TWI Bit Rate register |
.equ TWBR0 = 0 ; |
.equ TWBR1 = 1 ; |
.equ TWBR2 = 2 ; |
.equ TWBR3 = 3 ; |
.equ TWBR4 = 4 ; |
.equ TWBR5 = 5 ; |
.equ TWBR6 = 6 ; |
.equ TWBR7 = 7 ; |
; TWCR - TWI Control Register |
.equ TWIE = 0 ; TWI Interrupt Enable |
.equ TWEN = 2 ; TWI Enable Bit |
.equ TWWC = 3 ; TWI Write Collition Flag |
.equ TWSTO = 4 ; TWI Stop Condition Bit |
.equ TWSTA = 5 ; TWI Start Condition Bit |
.equ TWEA = 6 ; TWI Enable Acknowledge Bit |
.equ TWINT = 7 ; TWI Interrupt Flag |
; TWSR - TWI Status Register |
.equ TWS3 = 3 ; TWI Status |
.equ TWS4 = 4 ; TWI Status |
.equ TWS5 = 5 ; TWI Status |
.equ TWS6 = 6 ; TWI Status |
.equ TWS7 = 7 ; TWI Status |
; TWDR - TWI Data register |
.equ TWD0 = 0 ; TWI Data Register Bit 0 |
.equ TWD1 = 1 ; TWI Data Register Bit 1 |
.equ TWD2 = 2 ; TWI Data Register Bit 2 |
.equ TWD3 = 3 ; TWI Data Register Bit 3 |
.equ TWD4 = 4 ; TWI Data Register Bit 4 |
.equ TWD5 = 5 ; TWI Data Register Bit 5 |
.equ TWD6 = 6 ; TWI Data Register Bit 6 |
.equ TWD7 = 7 ; TWI Data Register Bit 7 |
; TWAR - TWI (Slave) Address register |
.equ TWGCE = 0 ; TWI General Call Recognition Enable Bit |
.equ TWA0 = 1 ; TWI (Slave) Address register Bit 0 |
.equ TWA1 = 2 ; TWI (Slave) Address register Bit 1 |
.equ TWA2 = 3 ; TWI (Slave) Address register Bit 2 |
.equ TWA3 = 4 ; TWI (Slave) Address register Bit 3 |
.equ TWA4 = 5 ; TWI (Slave) Address register Bit 4 |
.equ TWA5 = 6 ; TWI (Slave) Address register Bit 5 |
.equ TWA6 = 7 ; TWI (Slave) Address register Bit 6 |
; ***** ANALOG_COMPARATOR ************ |
; SFIOR - Special Function IO Register |
.equ ACME = 3 ; Analog Comparator Multiplexer Enable |
; ACSR - Analog Comparator Control And Status Register |
.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 |
.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 |
.equ ACIC = 2 ; Analog Comparator Input Capture Enable |
.equ ACIE = 3 ; Analog Comparator Interrupt Enable |
.equ ACI = 4 ; Analog Comparator Interrupt Flag |
.equ ACO = 5 ; Analog Compare Output |
.equ ACBG = 6 ; Analog Comparator Bandgap Select |
.equ ACD = 7 ; Analog Comparator Disable |
; ***** AD_CONVERTER ***************** |
; ADMUX - The ADC multiplexer Selection Register |
.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits |
.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits |
.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits |
.equ MUX3 = 3 ; Analog Channel and Gain Selection Bits |
.equ MUX4 = 4 ; Analog Channel and Gain Selection Bits |
.equ ADLAR = 5 ; Left Adjust Result |
.equ REFS0 = 6 ; Reference Selection Bit 0 |
.equ REFS1 = 7 ; Reference Selection Bit 1 |
; ADCSRA - The ADC Control and Status register |
.equ ADPS0 = 0 ; ADC Prescaler Select Bits |
.equ ADPS1 = 1 ; ADC Prescaler Select Bits |
.equ ADPS2 = 2 ; ADC Prescaler Select Bits |
.equ ADIE = 3 ; ADC Interrupt Enable |
.equ ADIF = 4 ; ADC Interrupt Flag |
.equ ADATE = 5 ; When this bit is written to one,the Timer/Counter2 prescaler will be reset.The bit will be cleared by hardware after the operation is performed.Writing a zero to this bit will have no effect.This bit will always be read as zero if Timer/Counter2 is clocked by the internal CPU clock.If this bit is written when Timer/Counter2 is operating in asynchronous mode,the bit will remain one until the prescaler has been reset. |
.equ ADFR = ADATE ; For compatibility |
.equ ADSC = 6 ; ADC Start Conversion |
.equ ADEN = 7 ; ADC Enable |
; ADCH - ADC Data Register High Byte |
.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0 |
.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1 |
.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2 |
.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3 |
.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4 |
.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5 |
.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6 |
.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7 |
; ADCL - ADC Data Register Low Byte |
.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0 |
.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1 |
.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2 |
.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3 |
.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4 |
.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5 |
.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6 |
.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7 |
; ***** PORTA ************************ |
; PORTA - Port A Data Register |
.equ PORTA0 = 0 ; Port A Data Register bit 0 |
.equ PA0 = 0 ; For compatibility |
.equ PORTA1 = 1 ; Port A Data Register bit 1 |
.equ PA1 = 1 ; For compatibility |
.equ PORTA2 = 2 ; Port A Data Register bit 2 |
.equ PA2 = 2 ; For compatibility |
.equ PORTA3 = 3 ; Port A Data Register bit 3 |
.equ PA3 = 3 ; For compatibility |
.equ PORTA4 = 4 ; Port A Data Register bit 4 |
.equ PA4 = 4 ; For compatibility |
.equ PORTA5 = 5 ; Port A Data Register bit 5 |
.equ PA5 = 5 ; For compatibility |
.equ PORTA6 = 6 ; Port A Data Register bit 6 |
.equ PA6 = 6 ; For compatibility |
.equ PORTA7 = 7 ; Port A Data Register bit 7 |
.equ PA7 = 7 ; For compatibility |
; DDRA - Port A Data Direction Register |
.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0 |
.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1 |
.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2 |
.equ DDA3 = 3 ; Data Direction Register, Port A, bit 3 |
.equ DDA4 = 4 ; Data Direction Register, Port A, bit 4 |
.equ DDA5 = 5 ; Data Direction Register, Port A, bit 5 |
.equ DDA6 = 6 ; Data Direction Register, Port A, bit 6 |
.equ DDA7 = 7 ; Data Direction Register, Port A, bit 7 |
; PINA - Port A Input Pins |
.equ PINA0 = 0 ; Input Pins, Port A bit 0 |
.equ PINA1 = 1 ; Input Pins, Port A bit 1 |
.equ PINA2 = 2 ; Input Pins, Port A bit 2 |
.equ PINA3 = 3 ; Input Pins, Port A bit 3 |
.equ PINA4 = 4 ; Input Pins, Port A bit 4 |
.equ PINA5 = 5 ; Input Pins, Port A bit 5 |
.equ PINA6 = 6 ; Input Pins, Port A bit 6 |
.equ PINA7 = 7 ; Input Pins, Port A bit 7 |
; ***** PORTB ************************ |
; PORTB - Port B Data Register |
.equ PORTB0 = 0 ; Port B Data Register bit 0 |
.equ PB0 = 0 ; For compatibility |
.equ PORTB1 = 1 ; Port B Data Register bit 1 |
.equ PB1 = 1 ; For compatibility |
.equ PORTB2 = 2 ; Port B Data Register bit 2 |
.equ PB2 = 2 ; For compatibility |
.equ PORTB3 = 3 ; Port B Data Register bit 3 |
.equ PB3 = 3 ; For compatibility |
.equ PORTB4 = 4 ; Port B Data Register bit 4 |
.equ PB4 = 4 ; For compatibility |
.equ PORTB5 = 5 ; Port B Data Register bit 5 |
.equ PB5 = 5 ; For compatibility |
.equ PORTB6 = 6 ; Port B Data Register bit 6 |
.equ PB6 = 6 ; For compatibility |
.equ PORTB7 = 7 ; Port B Data Register bit 7 |
.equ PB7 = 7 ; For compatibility |
; DDRB - Port B Data Direction Register |
.equ DDB0 = 0 ; Port B Data Direction Register bit 0 |
.equ DDB1 = 1 ; Port B Data Direction Register bit 1 |
.equ DDB2 = 2 ; Port B Data Direction Register bit 2 |
.equ DDB3 = 3 ; Port B Data Direction Register bit 3 |
.equ DDB4 = 4 ; Port B Data Direction Register bit 4 |
.equ DDB5 = 5 ; Port B Data Direction Register bit 5 |
.equ DDB6 = 6 ; Port B Data Direction Register bit 6 |
.equ DDB7 = 7 ; Port B Data Direction Register bit 7 |
; PINB - Port B Input Pins |
.equ PINB0 = 0 ; Port B Input Pins bit 0 |
.equ PINB1 = 1 ; Port B Input Pins bit 1 |
.equ PINB2 = 2 ; Port B Input Pins bit 2 |
.equ PINB3 = 3 ; Port B Input Pins bit 3 |
.equ PINB4 = 4 ; Port B Input Pins bit 4 |
.equ PINB5 = 5 ; Port B Input Pins bit 5 |
.equ PINB6 = 6 ; Port B Input Pins bit 6 |
.equ PINB7 = 7 ; Port B Input Pins bit 7 |
; ***** PORTC ************************ |
; PORTC - Port C Data Register |
.equ PORTC0 = 0 ; Port C Data Register bit 0 |
.equ PC0 = 0 ; For compatibility |
.equ PORTC1 = 1 ; Port C Data Register bit 1 |
.equ PC1 = 1 ; For compatibility |
.equ PORTC2 = 2 ; Port C Data Register bit 2 |
.equ PC2 = 2 ; For compatibility |
.equ PORTC3 = 3 ; Port C Data Register bit 3 |
.equ PC3 = 3 ; For compatibility |
.equ PORTC4 = 4 ; Port C Data Register bit 4 |
.equ PC4 = 4 ; For compatibility |
.equ PORTC5 = 5 ; Port C Data Register bit 5 |
.equ PC5 = 5 ; For compatibility |
.equ PORTC6 = 6 ; Port C Data Register bit 6 |
.equ PC6 = 6 ; For compatibility |
.equ PORTC7 = 7 ; Port C Data Register bit 7 |
.equ PC7 = 7 ; For compatibility |
; DDRC - Port C Data Direction Register |
.equ DDC0 = 0 ; Port C Data Direction Register bit 0 |
.equ DDC1 = 1 ; Port C Data Direction Register bit 1 |
.equ DDC2 = 2 ; Port C Data Direction Register bit 2 |
.equ DDC3 = 3 ; Port C Data Direction Register bit 3 |
.equ DDC4 = 4 ; Port C Data Direction Register bit 4 |
.equ DDC5 = 5 ; Port C Data Direction Register bit 5 |
.equ DDC6 = 6 ; Port C Data Direction Register bit 6 |
.equ DDC7 = 7 ; Port C Data Direction Register bit 7 |
; PINC - Port C Input Pins |
.equ PINC0 = 0 ; Port C Input Pins bit 0 |
.equ PINC1 = 1 ; Port C Input Pins bit 1 |
.equ PINC2 = 2 ; Port C Input Pins bit 2 |
.equ PINC3 = 3 ; Port C Input Pins bit 3 |
.equ PINC4 = 4 ; Port C Input Pins bit 4 |
.equ PINC5 = 5 ; Port C Input Pins bit 5 |
.equ PINC6 = 6 ; Port C Input Pins bit 6 |
.equ PINC7 = 7 ; Port C Input Pins bit 7 |
; ***** PORTD ************************ |
; PORTD - Port D Data Register |
.equ PORTD0 = 0 ; Port D Data Register bit 0 |
.equ PD0 = 0 ; For compatibility |
.equ PORTD1 = 1 ; Port D Data Register bit 1 |
.equ PD1 = 1 ; For compatibility |
.equ PORTD2 = 2 ; Port D Data Register bit 2 |
.equ PD2 = 2 ; For compatibility |
.equ PORTD3 = 3 ; Port D Data Register bit 3 |
.equ PD3 = 3 ; For compatibility |
.equ PORTD4 = 4 ; Port D Data Register bit 4 |
.equ PD4 = 4 ; For compatibility |
.equ PORTD5 = 5 ; Port D Data Register bit 5 |
.equ PD5 = 5 ; For compatibility |
.equ PORTD6 = 6 ; Port D Data Register bit 6 |
.equ PD6 = 6 ; For compatibility |
.equ PORTD7 = 7 ; Port D Data Register bit 7 |
.equ PD7 = 7 ; For compatibility |
; DDRD - Port D Data Direction Register |
.equ DDD0 = 0 ; Port D Data Direction Register bit 0 |
.equ DDD1 = 1 ; Port D Data Direction Register bit 1 |
.equ DDD2 = 2 ; Port D Data Direction Register bit 2 |
.equ DDD3 = 3 ; Port D Data Direction Register bit 3 |
.equ DDD4 = 4 ; Port D Data Direction Register bit 4 |
.equ DDD5 = 5 ; Port D Data Direction Register bit 5 |
.equ DDD6 = 6 ; Port D Data Direction Register bit 6 |
.equ DDD7 = 7 ; Port D Data Direction Register bit 7 |
; PIND - Port D Input Pins |
.equ PIND0 = 0 ; Port D Input Pins bit 0 |
.equ PIND1 = 1 ; Port D Input Pins bit 1 |
.equ PIND2 = 2 ; Port D Input Pins bit 2 |
.equ PIND3 = 3 ; Port D Input Pins bit 3 |
.equ PIND4 = 4 ; Port D Input Pins bit 4 |
.equ PIND5 = 5 ; Port D Input Pins bit 5 |
.equ PIND6 = 6 ; Port D Input Pins bit 6 |
.equ PIND7 = 7 ; Port D Input Pins bit 7 |
; ***** CPU ************************** |
; SREG - Status Register |
.equ SREG_C = 0 ; Carry Flag |
.equ SREG_Z = 1 ; Zero Flag |
.equ SREG_N = 2 ; Negative Flag |
.equ SREG_V = 3 ; Two's Complement Overflow Flag |
.equ SREG_S = 4 ; Sign Bit |
.equ SREG_H = 5 ; Half Carry Flag |
.equ SREG_T = 6 ; Bit Copy Storage |
.equ SREG_I = 7 ; Global Interrupt Enable |
; MCUCR - MCU Control Register |
;.equ ISC00 = 0 ; Interrupt Sense Control 0 Bit 0 |
;.equ ISC01 = 1 ; Interrupt Sense Control 0 Bit 1 |
;.equ ISC10 = 2 ; Interrupt Sense Control 1 Bit 0 |
;.equ ISC11 = 3 ; Interrupt Sense Control 1 Bit 1 |
.equ SM0 = 4 ; Sleep Mode Select |
.equ SM1 = 5 ; Sleep Mode Select |
.equ SM2 = 6 ; Sleep Mode Select |
.equ SE = 7 ; Sleep Enable |
; MCUCSR - MCU Control And Status Register |
.equ MCUSR = MCUCSR ; For compatibility |
.equ PORF = 0 ; Power-on reset flag |
.equ EXTRF = 1 ; External Reset Flag |
.equ BORF = 2 ; Brown-out Reset Flag |
.equ WDRF = 3 ; Watchdog Reset Flag |
.equ JTRF = 4 ; JTAG Reset Flag |
.equ JTD = 7 ; JTAG Interface Disable |
; OSCCAL - Oscillator Calibration Value |
.equ CAL0 = 0 ; Oscillator Calibration Value Bit0 |
.equ CAL1 = 1 ; Oscillator Calibration Value Bit1 |
.equ CAL2 = 2 ; Oscillator Calibration Value Bit2 |
.equ CAL3 = 3 ; Oscillator Calibration Value Bit3 |
.equ CAL4 = 4 ; Oscillator Calibration Value Bit4 |
.equ CAL5 = 5 ; Oscillator Calibration Value Bit5 |
.equ CAL6 = 6 ; Oscillator Calibration Value Bit6 |
.equ CAL7 = 7 ; Oscillator Calibration Value Bit7 |
; SFIOR - Special Function IO Register |
.equ PSR10 = 0 ; Prescaler Reset Timer/Counter1&0 |
.equ PSR2 = 1 ; Prescaler Reset Timer/Counter2 |
.equ PUD = 2 ; Pull-up Disable |
.equ ADTS0 = 5 ; ADC Auto Trigger Source 0 |
.equ ADTS1 = 6 ; ADC Auto Trigger Source 1 |
.equ ADTS2 = 7 ; ADC Auto Trigger Source 2 |
; ***** BOOT_LOAD ******************** |
; SPMCR - Store Program Memory Control Register |
.equ SPMEN = 0 ; Store Program Memory Enable |
.equ PGERS = 1 ; Page Erase |
.equ PGWRT = 2 ; Page Write |
.equ BLBSET = 3 ; Boot Lock Bit Set |
.equ RWWSRE = 4 ; Read While Write secion read enable |
.equ ASRE = RWWSRE ; For compatibility |
.equ RWWSB = 6 ; Read While Write Section Busy |
.equ ASB = RWWSB ; For compatibility |
.equ SPMIE = 7 ; SPM Interrupt Enable |
; ***** LOCKSBITS ******************************************************** |
.equ LB1 = 0 ; Lock bit |
.equ LB2 = 1 ; Lock bit |
.equ BLB01 = 2 ; Boot Lock bit |
.equ BLB02 = 3 ; Boot Lock bit |
.equ BLB11 = 4 ; Boot lock bit |
.equ BLB12 = 5 ; Boot lock bit |
; ***** FUSES ************************************************************ |
; LOW fuse bits |
.equ CKSEL0 = 0 ; Select Clock Source |
.equ CKSEL1 = 1 ; Select Clock Source |
.equ CKSEL2 = 2 ; Select Clock Source |
.equ CKSEL3 = 3 ; Select Clock Source |
.equ BODEN = 6 ; Brown out detector enable |
.equ BODLEVEL = 7 ; Brown out detector trigger level |
; HIGH fuse bits |
.equ BOOTRST = 0 ; Select Reset Vector |
.equ BOOTSZ0 = 1 ; Select Boot Size |
.equ BOOTSZ1 = 2 ; Select Boot Size |
.equ EESAVE = 3 ; EEPROM memory is preserved through chip erase |
.equ SPIEN = 5 ; Enable Serial programming and Data Downloading |
.equ JTAGEN = 6 ; Enable JTAG |
.equ OCDEN = 7 ; Enable OCD |
; ***** CPU REGISTER DEFINITIONS ***************************************** |
.def XH = r27 |
.def XL = r26 |
.def YH = r29 |
.def YL = r28 |
.def ZH = r31 |
.def ZL = r30 |
; ***** DATA MEMORY DECLARATIONS ***************************************** |
.equ FLASHEND = 0x3fff ; Note: Word address |
.equ IOEND = 0x003f |
.equ SRAM_START = 0x0060 |
.equ SRAM_SIZE = 2048 |
.equ RAMEND = 0x085f |
.equ XRAMEND = 0x0000 |
.equ E2END = 0x03ff |
.equ EEPROMEND = 0x03ff |
.equ EEADRBITS = 10 |
#pragma AVRPART MEMORY PROG_FLASH 32768 |
#pragma AVRPART MEMORY EEPROM 1024 |
#pragma AVRPART MEMORY INT_SRAM SIZE 2048 |
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60 |
; ***** BOOTLOADER DECLARATIONS ****************************************** |
.equ NRWW_START_ADDR = 0x3800 |
.equ NRWW_STOP_ADDR = 0x3fff |
.equ RWW_START_ADDR = 0x0 |
.equ RWW_STOP_ADDR = 0x37ff |
.equ PAGESIZE = 64 |
.equ FIRSTBOOTSTART = 0x3f00 |
.equ SECONDBOOTSTART = 0x3e00 |
.equ THIRDBOOTSTART = 0x3c00 |
.equ FOURTHBOOTSTART = 0x3800 |
.equ SMALLBOOTSTART = FIRSTBOOTSTART |
.equ LARGEBOOTSTART = FOURTHBOOTSTART |
; ***** INTERRUPT VECTORS ************************************************ |
.equ INT0addr = 0x0002 ; External Interrupt Request 0 |
.equ INT1addr = 0x0004 ; External Interrupt Request 1 |
.equ INT2addr = 0x0006 ; External Interrupt Request 2 |
.equ OC2addr = 0x0008 ; Timer/Counter2 Compare Match |
.equ OVF2addr = 0x000a ; Timer/Counter2 Overflow |
.equ ICP1addr = 0x000c ; Timer/Counter1 Capture Event |
.equ OC1Aaddr = 0x000e ; Timer/Counter1 Compare Match A |
.equ OC1Baddr = 0x0010 ; Timer/Counter1 Compare Match B |
.equ OVF1addr = 0x0012 ; Timer/Counter1 Overflow |
.equ OC0addr = 0x0014 ; Timer/Counter0 Compare Match |
.equ OVF0addr = 0x0016 ; Timer/Counter0 Overflow |
.equ SPIaddr = 0x0018 ; Serial Transfer Complete |
.equ URXCaddr = 0x001a ; USART, Rx Complete |
.equ UDREaddr = 0x001c ; USART Data Register Empty |
.equ UTXCaddr = 0x001e ; USART, Tx Complete |
.equ ADCCaddr = 0x0020 ; ADC Conversion Complete |
.equ ERDYaddr = 0x0022 ; EEPROM Ready |
.equ ACIaddr = 0x0024 ; Analog Comparator |
.equ TWIaddr = 0x0026 ; 2-wire Serial Interface |
.equ SPMRaddr = 0x0028 ; Store Program Memory Ready |
.equ INT_VECTORS_SIZE = 42 ; size in words |
#endif /* _M32DEF_INC_ */ |
; ***** END OF FILE ****************************************************** |
/contrib/toolchain/avra/includes/m406def.inc |
---|
0,0 → 1,855 |
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** |
;***** Created: 2005-01-11 10:31 ******* Source: ATmega406.xml *********** |
;************************************************************************* |
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y |
;* |
;* Number : AVR000 |
;* File Name : "m406def.inc" |
;* Title : Register/Bit Definitions for the ATmega406 |
;* Date : 2005-01-11 |
;* Version : 2.14 |
;* Support E-mail : avr@atmel.com |
;* Target MCU : ATmega406 |
;* |
;* DESCRIPTION |
;* When including this file in the assembly program file, all I/O register |
;* names and I/O register bit names appearing in the data book can be used. |
;* In addition, the six registers forming the three data pointers X, Y and |
;* Z have been assigned names XL - ZH. Highest RAM address for Internal |
;* SRAM is also defined |
;* |
;* The Register names are represented by their hexadecimal address. |
;* |
;* The Register Bit names are represented by their bit number (0-7). |
;* |
;* Please observe the difference in using the bit names with instructions |
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" |
;* (skip if bit in register set/cleared). The following example illustrates |
;* this: |
;* |
;* in r16,PORTB ;read PORTB latch |
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) |
;* out PORTB,r16 ;output to PORTB |
;* |
;* in r16,TIFR ;read the Timer Interrupt Flag Register |
;* sbrc r16,TOV0 ;test the overflow flag (use bit#) |
;* rjmp TOV0_is_set ;jump if set |
;* ... ;otherwise do something else |
;************************************************************************* |
#ifndef _M406DEF_INC_ |
#define _M406DEF_INC_ |
#pragma partinc 0 |
; ***** SPECIFY DEVICE *************************************************** |
.device ATmega406 |
#pragma AVRPART ADMIN PART_NAME ATmega406 |
.equ SIGNATURE_000 = 0x1e |
.equ SIGNATURE_001 = 0x95 |
.equ SIGNATURE_002 = 0x07 |
#pragma AVRPART CORE CORE_VERSION V2E |
; ***** I/O REGISTER DEFINITIONS ***************************************** |
; NOTE: |
; Definitions marked "MEMORY MAPPED"are extended I/O ports |
; and cannot be used with IN/OUT instructions |
.equ BPPLR = 0xf8 ; MEMORY MAPPED |
.equ BPCR = 0xf7 ; MEMORY MAPPED |
.equ CBPTR = 0xf6 ; MEMORY MAPPED |
.equ BPOCD = 0xf5 ; MEMORY MAPPED |
.equ BPSCD = 0xf4 ; MEMORY MAPPED |
.equ BPDUV = 0xf3 ; MEMORY MAPPED |
.equ BPIR = 0xf2 ; MEMORY MAPPED |
.equ CBCR = 0xf1 ; MEMORY MAPPED |
.equ FCSR = 0xf0 ; MEMORY MAPPED |
.equ CADICH = 0xe9 ; MEMORY MAPPED |
.equ CADICL = 0xe8 ; MEMORY MAPPED |
.equ CADRDC = 0xe7 ; MEMORY MAPPED |
.equ CADRCC = 0xe6 ; MEMORY MAPPED |
.equ CADCSRB = 0xe5 ; MEMORY MAPPED |
.equ CADCSRA = 0xe4 ; MEMORY MAPPED |
.equ CADAC3 = 0xe3 ; MEMORY MAPPED |
.equ CADAC2 = 0xe2 ; MEMORY MAPPED |
.equ CADAC1 = 0xe1 ; MEMORY MAPPED |
.equ CADAC0 = 0xe0 ; MEMORY MAPPED |
.equ BGCRR = 0xd1 ; MEMORY MAPPED |
.equ BGCCR = 0xd0 ; MEMORY MAPPED |
.equ CCSR = 0xc0 ; MEMORY MAPPED |
.equ TWBCSR = 0xbe ; MEMORY MAPPED |
.equ TWAMR = 0xbd ; MEMORY MAPPED |
.equ TWCR = 0xbc ; MEMORY MAPPED |
.equ TWDR = 0xbb ; MEMORY MAPPED |
.equ TWAR = 0xba ; MEMORY MAPPED |
.equ TWSR = 0xb9 ; MEMORY MAPPED |
.equ TWBR = 0xb8 ; MEMORY MAPPED |
.equ OCR1AH = 0x89 ; MEMORY MAPPED |
.equ OCR1AL = 0x88 ; MEMORY MAPPED |
.equ TCNT1H = 0x85 ; MEMORY MAPPED |
.equ TCNT1L = 0x84 ; MEMORY MAPPED |
.equ TCCR1B = 0x81 ; MEMORY MAPPED |
.equ DIDR0 = 0x7e ; MEMORY MAPPED |
.equ VADMUX = 0x7c ; MEMORY MAPPED |
.equ VADCSR = 0x7a ; MEMORY MAPPED |
.equ VADCH = 0x79 ; MEMORY MAPPED |
.equ VADCL = 0x78 ; MEMORY MAPPED |
.equ TIMSK1 = 0x6f ; MEMORY MAPPED |
.equ TIMSK0 = 0x6e ; MEMORY MAPPED |
.equ PCMSK1 = 0x6c ; MEMORY MAPPED |
.equ PCMSK0 = 0x6b ; MEMORY MAPPED |
.equ EICRA = 0x69 ; MEMORY MAPPED |
.equ PCICR = 0x68 ; MEMORY MAPPED |
.equ FOSCCAL = 0x66 ; MEMORY MAPPED |
.equ PRR0 = 0x64 ; MEMORY MAPPED |
.equ WUTCSR = 0x62 ; MEMORY MAPPED |
.equ WDTCSR = 0x60 ; MEMORY MAPPED |
.equ SREG = 0x3f |
.equ SPH = 0x3e |
.equ SPL = 0x3d |
.equ SPMCSR = 0x37 |
.equ MCUCR = 0x35 |
.equ MCUSR = 0x34 |
.equ SMCR = 0x33 |
.equ OCDR = 0x31 |
.equ GPIOR2 = 0x2b |
.equ GPIOR1 = 0x2a |
.equ OCR0B = 0x28 |
.equ OCR0A = 0x27 |
.equ TCNT0 = 0x26 |
.equ TCCR0B = 0x25 |
.equ TCCR0A = 0x24 |
.equ GTCCR = 0x23 |
.equ EEARH = 0x22 |
.equ EEARL = 0x21 |
.equ EEDR = 0x20 |
.equ EECR = 0x1f |
.equ GPIOR0 = 0x1e |
.equ EIMSK = 0x1d |
.equ EIFR = 0x1c |
.equ PCIFR = 0x1b |
.equ TIFR1 = 0x16 |
.equ TIFR0 = 0x15 |
.equ PORTD = 0x0b |
.equ DDRD = 0x0a |
.equ PIND = 0x09 |
.equ PORTC = 0x08 |
.equ PORTB = 0x05 |
.equ DDRB = 0x04 |
.equ PINB = 0x03 |
.equ PORTA = 0x02 |
.equ DDRA = 0x01 |
.equ PINA = 0x00 |
; ***** BIT DEFINITIONS ************************************************** |
; ***** AD_CONVERTER ***************** |
; VADMUX - The VADC multiplexer Selection Register |
.equ VADMUX0 = 0 ; Analog Channel and Gain Selection Bits |
.equ VADMUX1 = 1 ; Analog Channel and Gain Selection Bits |
.equ VADMUX2 = 2 ; Analog Channel and Gain Selection Bits |
.equ VADMUX3 = 3 ; Analog Channel and Gain Selection Bits |
; VADCSR - The VADC Control and Status register |
.equ VADCCIE = 0 ; VADC Conversion Complete Interrupt Enable |
.equ VADCCIF = 1 ; VADC Conversion Complete Interrupt Flag |
.equ VADSC = 2 ; VADC Satrt Conversion |
.equ VADEN = 3 ; VADC Enable |
; ***** EXTERNAL_INTERRUPT *********** |
; EICRA - External Interrupt Control Register |
.equ ISC00 = 0 ; External Interrupt Sense Control 0 Bit 0 |
.equ ISC01 = 1 ; External Interrupt Sense Control 0 Bit 1 |
.equ ISC10 = 2 ; External Interrupt Sense Control 1 Bit 0 |
.equ ISC11 = 3 ; External Interrupt Sense Control 1 Bit 1 |
.equ ISC20 = 4 ; External Interrupt Sense Control 2 Bit 0 |
.equ ISC21 = 5 ; External Interrupt Sense Control 2 Bit 1 |
.equ ISC30 = 6 ; External Interrupt Sense Control 3 Bit 0 |
.equ ISC31 = 7 ; External Interrupt Sense Control 3 Bit 1 |
; EIMSK - External Interrupt Mask Register |
.equ INT0 = 0 ; External Interrupt Request 0 Enable |
.equ INT1 = 1 ; External Interrupt Request 1 Enable |
.equ INT2 = 2 ; External Interrupt Request 1 Enable |
.equ INT3 = 3 ; External Interrupt Request 1 Enable |
; EIFR - External Interrupt Flag Register |
.equ INTF0 = 0 ; External Interrupt Flag 0 |
.equ INTF1 = 1 ; External Interrupt Flag 1 |
.equ INTF2 = 2 ; External Interrupt Flag 2 |
.equ INTF3 = 3 ; External Interrupt Flag 3 |
; PCICR - Pin Change Interrupt Control Register |
.equ PCIE0 = 0 ; Pin Change Interrupt Enable 0 |
.equ PCIE1 = 1 ; Pin Change Interrupt Enable 1 |
; PCIFR - Pin Change Interrupt Flag Register |
.equ PCIF0 = 0 ; Pin Change Interrupt Flag 1 |
.equ PCIF1 = 1 ; Pin Change Interrupt Flag 1 |
; ***** TIMER_COUNTER_1 ************** |
; TCCR1B - Timer/Counter1 Control Register B |
.equ CS10 = 0 ; Clock Select1 bit 0 |
.equ CS11 = 1 ; Clock Select1 bit 1 |
.equ CS12 = 2 ; Clock Select1 bit 2 |
.equ CTC1 = 3 ; Clear Timer/Counter on Compare Match |
; TIMSK1 - Timer/Counter Interrupt Mask Register |
.equ TOIE1 = 0 ; Timer/Counter1 Overflow Interrupt Enable |
.equ OCIE1A = 1 ; Timer/Counter1 Output Compare Interrupt Enable |
; TIFR1 - Timer/Counter Interrupt Flag register |
.equ TOV1 = 0 ; Timer/Counter1 Overflow Flag |
.equ OCF1A = 1 ; Timer/Counter1 Output Compare Flag A |
; GTCCR - General Timer/Counter Control Register |
.equ PSRSYNC = 0 ; Prescaler Reset |
.equ PSRASY = 1 ; |
.equ TSM = 7 ; Timer/Counter Synchronization Mode |
; ***** WAKEUP_TIMER ***************** |
; WUTCSR - Wake-up Timer Control Register |
.equ WUTP0 = 0 ; Wake-up Timer Prescaler Bit 0 |
.equ WUTP1 = 1 ; Wake-up Timer Prescaler Bit 1 |
.equ WUTP2 = 2 ; Wake-up Timer Prescaler Bit 2 |
.equ WUTE = 3 ; Wake-up Timer Enable |
.equ WUTR = 4 ; Wake-up Timer Reset |
.equ WUTCF = 5 ; Wake-up timer Calibration Flag |
.equ WUTIE = 6 ; Wake-up Timer Interrupt Enable |
.equ WUTIF = 7 ; Wake-up Timer Interrupt Flag |
; ***** BATTERY_PROTECTION *********** |
; BPPLR - Battery Protection Parameter Lock Register |
.equ BPPL = 0 ; Battery Protection Parameter Lock |
.equ BPPLE = 1 ; Battery Protection Parameter Lock Enable |
; BPCR - Battery Protection Control Register |
.equ CCD = 0 ; |
.equ DCD = 1 ; |
.equ SCD = 2 ; |
.equ DUVD = 3 ; |
; CBPTR - Current Battery Protection Timing Register |
.equ OCPT0 = 0 ; |
.equ OCPT1 = 1 ; |
.equ OCPT2 = 2 ; |
.equ OCPT3 = 3 ; |
.equ SCPT0 = 4 ; |
.equ SCPT1 = 5 ; |
.equ SCPT2 = 6 ; |
.equ SCPT3 = 7 ; |
; BPOCD - Battery Protection OverCurrent Detection Level Register |
.equ CCDL0 = 0 ; |
.equ CCDL1 = 1 ; |
.equ CCDL2 = 2 ; |
.equ CCDL3 = 3 ; |
.equ DCDL0 = 4 ; |
.equ DCDL1 = 5 ; |
.equ DCDL2 = 6 ; |
.equ DCDL3 = 7 ; |
; BPSCD - Battery Protection Short-Circuit Detection Level Register |
.equ SCDL0 = 0 ; |
.equ SCDL1 = 1 ; |
.equ SCDL2 = 2 ; |
.equ SCDL3 = 3 ; |
; BPDUV - Battery Protection Deep Under Voltage Register |
.equ DUDL0 = 0 ; |
.equ DUDL1 = 1 ; |
.equ DUDL2 = 2 ; |
.equ DUDL3 = 3 ; |
.equ DUVT0 = 4 ; |
.equ DUVT1 = 5 ; |
; BPIR - Battery Protection Interrupt Register |
.equ SCIE = 0 ; |
.equ DOCIE = 1 ; |
.equ COCIE = 2 ; |
.equ DUVIE = 3 ; Deep Under-voltage Early Warning Interrupt Enable |
.equ SCIF = 4 ; |
.equ DOCIF = 5 ; |
.equ COCIF = 6 ; Charge Over-current Protection Activated Interrupt Flag |
.equ DUVIF = 7 ; Deep Under-voltage Early Warning Interrupt Flag |
; ***** FET ************************** |
; FCSR - |
.equ PFD = 0 ; Precharge FET disable |
.equ CFE = 1 ; Charge FET Enable |
.equ DFE = 2 ; Discharge FET Enable |
.equ CPS = 3 ; Current Protection Status |
.equ PWMOPC = 4 ; Pulse Width Modulation Modulation of OPC output |
.equ PWMOC = 5 ; Pulse Width Modulation of OC output |
; ***** COULOMB_COUNTER ************** |
; CADCSRA - CC-ADC Control and Status Register A |
.equ CADSE = 0 ; When the CADSE bit is written to one, the ongoing CC-ADC conversion is aborted, and the CC-ADC enters Regular Current detection mode. |
.equ CADSI0 = 1 ; The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. |
.equ CADSI1 = 2 ; The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. |
.equ CADAS0 = 3 ; CC_ADC Accumulate Current Select Bit 0 |
.equ CADAS1 = 4 ; CC_ADC Accumulate Current Select Bit 1 |
.equ CADUB = 5 ; CC_ADC Update Busy |
.equ CADEN = 7 ; When the CADEN bit is cleared (zero), the CC-ADC is disabled. When the CADEN bit is set (one), the CC-ADC will continuously measure the voltage drop over the external sense resistor RSENSE. In Power-down, only the Regular Current detection is active. In Power-off, the CC-ADC is always disabled. |
; CADCSRB - CC-ADC Control and Status Register B |
.equ CADICIF = 0 ; CC-ADC Instantaneous Current Interrupt Flag |
.equ CADRCIF = 1 ; CC-ADC Accumulate Current Interrupt Flag |
.equ CADACIF = 2 ; CC-ADC Accumulate Current Interrupt Flag |
.equ CADICIE = 4 ; CAD Instantenous Current Interrupt Enable |
.equ CADRCIE = 5 ; Regular Current Interrupt Enable |
.equ CADACIE = 6 ; |
; CADAC3 - ADC Accumulate Current |
.equ CADAC24 = 0 ; |
.equ CADAC25 = 1 ; |
.equ CADAC26 = 2 ; |
.equ CADAC27 = 3 ; |
.equ CADAC28 = 4 ; |
.equ CADAC29 = 5 ; |
.equ CADAC30 = 6 ; |
.equ CADAC31 = 7 ; |
; CADAC2 - ADC Accumulate Current |
.equ CADAC16 = 0 ; |
.equ CADAC17 = 1 ; |
.equ CADAC18 = 2 ; |
.equ CADAC19 = 3 ; |
.equ CADAC20 = 4 ; |
.equ CADAC21 = 5 ; |
.equ CADAC22 = 6 ; |
.equ CADAC23 = 7 ; |
; CADAC1 - ADC Accumulate Current |
.equ CADAC08 = 0 ; |
.equ CADAC09 = 1 ; |
.equ CADAC10 = 2 ; |
.equ CADAC11 = 3 ; |
.equ CADAC12 = 4 ; |
.equ CADAC13 = 5 ; |
.equ CADAC14 = 6 ; |
.equ CADAC15 = 7 ; |
; CADAC0 - ADC Accumulate Current |
.equ CADAC00 = 0 ; |
.equ CADAC01 = 1 ; |
.equ CADAC02 = 2 ; |
.equ CADAC03 = 3 ; |
.equ CADAC04 = 4 ; |
.equ CADAC05 = 5 ; |
.equ CADAC06 = 6 ; |
.equ CADAC07 = 7 ; |
; CADRCC - CC-ADC Regular Charge Current |
.equ CADRCC0 = 0 ; When the CADSE bit is written to one, the ongoing CC-ADC conversion is aborted, and the CC-ADC enters Regular Current detection mode. |
.equ CADRCC1 = 1 ; The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. |
.equ CADRCC2 = 2 ; The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. |
.equ CADRCC3 = 3 ; The CADACT bits determine the conversion time for the Accumulate Current output as shown in Table 43. |
.equ CADRCC4 = 4 ; The CADACT bits determine the conversion time for the Accumulate Current output as shown in Table 43. |
.equ CADRCC5 = 5 ; |
.equ CADRCC6 = 6 ; |
.equ CADRCC7 = 7 ; When the CADEN bit is cleared (zero), the CC-ADC is disabled. When the CADEN bit is set (one), the CC-ADC will continuously measure the voltage drop over the external sense resistor RSENSE. In Power-down, only the Regular Current detection is active. In Power-off, the CC-ADC is always disabled. |
; CADRDC - CC-ADC Regular Discharge Current |
.equ CADRDC0 = 0 ; When the CADSE bit is written to one, the ongoing CC-ADC conversion is aborted, and the CC-ADC enters Regular Current detection mode. |
.equ CADRDC1 = 1 ; The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. |
.equ CADRDC2 = 2 ; The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined. |
.equ CADRDC3 = 3 ; The CADACT bits determine the conversion time for the Accumulate Current output as shown in Table 43. |
.equ CADRDC4 = 4 ; The CADACT bits determine the conversion time for the Accumulate Current output as shown in Table 43. |
.equ CADRDC5 = 5 ; |
.equ CADRDC6 = 6 ; |
.equ CADRDC7 = 7 ; When the CADEN bit is cleared (zero), the CC-ADC is disabled. When the CADEN bit is set (one), the CC-ADC will continuously measure the voltage drop over the external sense resistor RSENSE. In Power-down, only the Regular Current detection is active. In Power-off, the CC-ADC is always disabled. |
; ***** CELL_BALANCING *************** |
; CBCR - Cell Balancing Control Register |
.equ CBE1 = 0 ; Battery Protection Parameter Lock |
.equ CBE2 = 1 ; Cell Balancing Enable 2 |
.equ CBE3 = 2 ; Cell Balancing Enable 4 |
.equ CBE4 = 3 ; Cell Balancing Enable 4 |
; ***** CPU ************************** |
; SREG - Status Register |
.equ SREG_C = 0 ; Carry Flag |
.equ SREG_Z = 1 ; Zero Flag |
.equ SREG_N = 2 ; Negative Flag |
.equ SREG_V = 3 ; Two's Complement Overflow Flag |
.equ SREG_S = 4 ; Sign Bit |
.equ SREG_H = 5 ; Half Carry Flag |
.equ SREG_T = 6 ; Bit Copy Storage |
.equ SREG_I = 7 ; Global Interrupt Enable |
; MCUCR - MCU Control Register |
.equ IVCE = 0 ; Interrupt Vector Change Enable |
.equ IVSEL = 1 ; Interrupt Vector Select |
.equ PUD = 4 ; Pull-up disable |
.equ JTD = 7 ; JTAG Disable |
; MCUSR - MCU Status Register |
.equ PORF = 0 ; Power-on reset flag |
.equ EXTRF = 1 ; External Reset Flag |
.equ BODRF = 2 ; Brown-out Reset Flag |
.equ WDRF = 3 ; Watchdog Reset Flag |
.equ JTRF = 4 ; JTAG Reset Flag |
; FOSCCAL - Fast Oscillator Calibration Value |
.equ FCAL0 = 0 ; Oscillator Calibration Value Bit0 |
.equ FCAL1 = 1 ; Oscillator Calibration Value Bit1 |
.equ FCAL2 = 2 ; Oscillator Calibration Value Bit2 |
.equ FCAL3 = 3 ; Oscillator Calibration Value Bit3 |
.equ FCAL4 = 4 ; Oscillator Calibration Value Bit4 |
.equ FCAL5 = 5 ; Oscillator Calibration Value Bit5 |
.equ FCAL6 = 6 ; Oscillator Calibration Value Bit6 |
.equ FCAL7 = 7 ; Oscillator Calibration Value Bit7 |
; SMCR - Sleep Mode Control Register |
.equ SE = 0 ; Sleep Enable |
.equ SM0 = 1 ; Sleep Mode Select bit 0 |
.equ SM1 = 2 ; Sleep Mode Select bit 1 |
.equ SM2 = 3 ; Sleep Mode Select bit 2 |
; GPIOR2 - General Purpose IO Register 2 |
.equ GPIOR20 = 0 ; General Purpose IO Register 2 bit 0 |
.equ GPIOR21 = 1 ; General Purpose IO Register 2 bit 1 |
.equ GPIOR22 = 2 ; General Purpose IO Register 2 bit 2 |
.equ GPIOR23 = 3 ; General Purpose IO Register 2 bit 3 |
.equ GPIOR24 = 4 ; General Purpose IO Register 2 bit 4 |
.equ GPIOR25 = 5 ; General Purpose IO Register 2 bit 5 |
.equ GPIOR26 = 6 ; General Purpose IO Register 2 bit 6 |
.equ GPIOR27 = 7 ; General Purpose IO Register 2 bit 7 |
; GPIOR1 - General Purpose IO Register 1 |
.equ GPIOR10 = 0 ; General Purpose IO Register 1 bit 0 |
.equ GPIOR11 = 1 ; General Purpose IO Register 1 bit 1 |
.equ GPIOR12 = 2 ; General Purpose IO Register 1 bit 2 |
.equ GPIOR13 = 3 ; General Purpose IO Register 1 bit 3 |
.equ GPIOR14 = 4 ; General Purpose IO Register 1 bit 4 |
.equ GPIOR15 = 5 ; General Purpose IO Register 1 bit 5 |
.equ GPIOR16 = 6 ; General Purpose IO Register 1 bit 6 |
.equ GPIOR17 = 7 ; General Purpose IO Register 1 bit 7 |
; GPIOR0 - General Purpose IO Register 0 |
.equ GPIOR00 = 0 ; General Purpose IO Register 0 bit 0 |
.equ GPIOR01 = 1 ; General Purpose IO Register 0 bit 1 |
.equ GPIOR02 = 2 ; General Purpose IO Register 0 bit 2 |
.equ GPIOR03 = 3 ; General Purpose IO Register 0 bit 3 |
.equ GPIOR04 = 4 ; General Purpose IO Register 0 bit 4 |
.equ GPIOR05 = 5 ; General Purpose IO Register 0 bit 5 |
.equ GPIOR06 = 6 ; General Purpose IO Register 0 bit 6 |
.equ GPIOR07 = 7 ; General Purpose IO Register 0 bit 7 |
; CCSR - Clock Control and Status Register |
.equ ACS = 0 ; Asynchronous Clock Select |
.equ XOE = 1 ; 32 kHz Crystal Oscillator Enable |
; DIDR0 - Digital Input Disable Register |
.equ VADC0D = 0 ; When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled. |
.equ VADC1D = 1 ; When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled. |
.equ VADC2D = 2 ; When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled. |
.equ VADC3D = 3 ; When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled. |
; PRR0 - Power Reduction Register 0 |
.equ PRVADC = 0 ; Power Reduction V-ADC |
.equ PRTIM0 = 1 ; Power Reduction Timer/Counter0 |
.equ PRTIM1 = 2 ; Power Reduction Timer/Counter1 |
.equ PRTWI = 3 ; Power Reduction TWI |
; ***** WATCHDOG ********************* |
; WDTCSR - Watchdog Timer Control Register |
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 |
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 |
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 |
.equ WDE = 3 ; Watch Dog Enable |
.equ WDCE = 4 ; Watchdog Change Enable |
.equ WDP3 = 5 ; Watchdog Timer Prescaler Bit 3 |
.equ WDIE = 6 ; Watchdog Timeout Interrupt Enable |
.equ WDIF = 7 ; Watchdog Timeout Interrupt Flag |
; ***** TIMER_COUNTER_0 ************** |
; TCCR0A - Timer/Counter0 Control Register |
.equ WGM00 = 0 ; Clock Select0 bit 0 |
.equ WGM01 = 1 ; Clock Select0 bit 1 |
.equ COM0B0 = 4 ; |
.equ COM0B1 = 5 ; |
.equ COM0A0 = 6 ; Waveform Generation Mode |
.equ COM0A1 = 7 ; Force Output Compare |
; TCCR0B - Timer/Counter0 Control Register |
.equ CS00 = 0 ; Clock Select0 bit 0 |
.equ CS01 = 1 ; Clock Select0 bit 1 |
.equ CS02 = 2 ; Clock Select0 bit 2 |
.equ WGM02 = 3 ; |
.equ FOC0B = 6 ; Waveform Generation Mode |
.equ FOC0A = 7 ; Force Output Compare |
; TCNT0 - Timer Counter 0 |
.equ TCNT00 = 0 ; Timer Counter 0 bit 0 |
.equ TCNT01 = 1 ; Timer Counter 0 bit 1 |
.equ TCNT02 = 2 ; Timer Counter 0 bit 2 |
.equ TCNT03 = 3 ; Timer Counter 0 bit 3 |
.equ TCNT04 = 4 ; Timer Counter 0 bit 4 |
.equ TCNT05 = 5 ; Timer Counter 0 bit 5 |
.equ TCNT06 = 6 ; Timer Counter 0 bit 6 |
.equ TCNT07 = 7 ; Timer Counter 0 bit 7 |
; OCR0A - Output compare Register A |
.equ OCR0A0 = 0 ; |
.equ OCR0A1 = 1 ; |
.equ OCR0A2 = 2 ; |
.equ OCR0A3 = 3 ; |
.equ OCR0A4 = 4 ; |
.equ OCR0A5 = 5 ; |
.equ OCR0A6 = 6 ; |
.equ OCR0A7 = 7 ; |
; OCR0B - Output compare Register B |
.equ OCR0B0 = 0 ; |
.equ OCR0B1 = 1 ; |
.equ OCR0B2 = 2 ; |
.equ OCR0B3 = 3 ; |
.equ OCR0B4 = 4 ; |
.equ OCR0B5 = 5 ; |
.equ OCR0B6 = 6 ; |
.equ OCR0B7 = 7 ; |
; TIMSK0 - Timer/Counter Interrupt Mask Register |
.equ TOIE0 = 0 ; Overflow Interrupt Enable |
.equ OCIE0A = 1 ; Output Compare Interrupt Enable |
.equ OCIE0B = 2 ; Output Compare Interrupt Enable |
; TIFR0 - Timer/Counter Interrupt Flag register |
.equ TOV0 = 0 ; Overflow Flag |
.equ OCF0A = 1 ; Output Compare Flag |
.equ OCF0B = 2 ; Output Compare Flag |
; ***** PORTA ************************ |
; PORTA - Port A Data Register |
.equ PORTA0 = 0 ; Port A Data Register bit 0 |
.equ PA0 = 0 ; For compatibility |
.equ PORTA1 = 1 ; Port A Data Register bit 1 |
.equ PA1 = 1 ; For compatibility |
.equ PORTA2 = 2 ; Port A Data Register bit 2 |
.equ PA2 = 2 ; For compatibility |
.equ PORTA3 = 3 ; Port A Data Register bit 3 |
.equ PA3 = 3 ; For compatibility |
.equ PORTA4 = 4 ; Port A Data Register bit 4 |
.equ PA4 = 4 ; For compatibility |
.equ PORTA5 = 5 ; Port A Data Register bit 5 |
.equ PA5 = 5 ; For compatibility |
.equ PORTA6 = 6 ; Port A Data Register bit 6 |
.equ PA6 = 6 ; For compatibility |
.equ PORTA7 = 7 ; Port A Data Register bit 7 |
.equ PA7 = 7 ; For compatibility |
; DDRA - Port A Data Direction Register |
.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0 |
.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1 |
.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2 |
.equ DDA3 = 3 ; Data Direction Register, Port A, bit 3 |
.equ DDA4 = 4 ; Data Direction Register, Port A, bit 4 |
.equ DDA5 = 5 ; Data Direction Register, Port A, bit 5 |
.equ DDA6 = 6 ; Data Direction Register, Port A, bit 6 |
.equ DDA7 = 7 ; Data Direction Register, Port A, bit 7 |
; PINA - Port A Input Pins |
.equ PINA0 = 0 ; Input Pins, Port A bit 0 |
.equ PINA1 = 1 ; Input Pins, Port A bit 1 |
.equ PINA2 = 2 ; Input Pins, Port A bit 2 |
.equ PINA3 = 3 ; Input Pins, Port A bit 3 |
.equ PINA4 = 4 ; Input Pins, Port A bit 4 |
.equ PINA5 = 5 ; Input Pins, Port A bit 5 |
.equ PINA6 = 6 ; Input Pins, Port A bit 6 |
.equ PINA7 = 7 ; Input Pins, Port A bit 7 |
; ***** PORTB ************************ |
; PORTB - Port B Data Register |
.equ PORTB0 = 0 ; Port B Data Register bit 0 |
.equ PB0 = 0 ; For compatibility |
.equ PORTB1 = 1 ; Port B Data Register bit 1 |
.equ PB1 = 1 ; For compatibility |
.equ PORTB2 = 2 ; Port B Data Register bit 2 |
.equ PB2 = 2 ; For compatibility |
.equ PORTB3 = 3 ; Port B Data Register bit 3 |
.equ PB3 = 3 ; For compatibility |
.equ PORTB4 = 4 ; Port B Data Register bit 4 |
.equ PB4 = 4 ; For compatibility |
.equ PORTB5 = 5 ; Port B Data Register bit 5 |
.equ PB5 = 5 ; For compatibility |
.equ PORTB6 = 6 ; Port B Data Register bit 6 |
.equ PB6 = 6 ; For compatibility |
.equ PORTB7 = 7 ; Port B Data Register bit 7 |
.equ PB7 = 7 ; For compatibility |
; DDRB - Port B Data Direction Register |
.equ DDB0 = 0 ; Port B Data Direction Register bit 0 |
.equ DDB1 = 1 ; Port B Data Direction Register bit 1 |
.equ DDB2 = 2 ; Port B Data Direction Register bit 2 |
.equ DDB3 = 3 ; Port B Data Direction Register bit 3 |
.equ DDB4 = 4 ; Port B Data Direction Register bit 4 |
.equ DDB5 = 5 ; Port B Data Direction Register bit 5 |
.equ DDB6 = 6 ; Port B Data Direction Register bit 6 |
.equ DDB7 = 7 ; Port B Data Direction Register bit 7 |
; PINB - Port B Input Pins |
.equ PINB0 = 0 ; Port B Input Pins bit 0 |
.equ PINB1 = 1 ; Port B Input Pins bit 1 |
.equ PINB2 = 2 ; Port B Input Pins bit 2 |
.equ PINB3 = 3 ; Port B Input Pins bit 3 |
.equ PINB4 = 4 ; Port B Input Pins bit 4 |
.equ PINB5 = 5 ; Port B Input Pins bit 5 |
.equ PINB6 = 6 ; Port B Input Pins bit 6 |
.equ PINB7 = 7 ; Port B Input Pins bit 7 |
; ***** PORTC ************************ |
; PORTC - Port C Data Register |
.equ PORTC0 = 0 ; Port C Data Register bit 0 |
.equ PC0 = 0 ; For compatibility |
; ***** PORTD ************************ |
; PORTD - Data Register, Port D |
.equ PORTD0 = 0 ; |
.equ PD0 = 0 ; For compatibility |
.equ PORTD1 = 1 ; |
.equ PD1 = 1 ; For compatibility |
; DDRD |
.equ DDD0 = 0 ; |
.equ DDD1 = 1 ; |
; PIND - Input Pins, Port D |
.equ PIND0 = 0 ; |
.equ PIND1 = 1 ; |
; ***** BOOT_LOAD ******************** |
; SPMCSR - Store Program Memory Control Register |
.equ SPMEN = 0 ; Store Program Memory Enable |
.equ PGERS = 1 ; Page Erase |
.equ PGWRT = 2 ; Page Write |
.equ BLBSET = 3 ; Boot Lock Bit Set |
.equ RWWSRE = 4 ; Read While Write section read enable |
.equ SIGRD = 5 ; Signature Row Read |
.equ RWWSB = 6 ; Read While Write Section Busy |
.equ SPMIE = 7 ; SPM Interrupt Enable |
; ***** TWI ************************** |
; TWBCSR - TWI Bus Control and Status Register |
.equ TWBCIP = 0 ; TWI Bus Connect/Disconnect Interrupt Polarity |
.equ TWBDT0 = 1 ; TWI Bus Disconnect Time-out Period |
.equ TWBDT1 = 2 ; TWI Bus Disconnect Time-out Period |
.equ TWBCIE = 6 ; TWI Bus Connect/Disconnect Interrupt Enable |
.equ TWBCIF = 7 ; TWI Bus Connect/Disconnect Interrupt Flag |
; TWAMR - TWI (Slave) Address Mask Register |
.equ TWAM0 = 1 ; |
.equ TWAM1 = 2 ; |
.equ TWAM2 = 3 ; |
.equ TWAM3 = 4 ; |
.equ TWAM4 = 5 ; |
.equ TWAM5 = 6 ; |
.equ TWAM6 = 7 ; |
; TWBR - TWI Bit Rate register |
.equ TWBR0 = 0 ; |
.equ TWBR1 = 1 ; |
.equ TWBR2 = 2 ; |
.equ TWBR3 = 3 ; |
.equ TWBR4 = 4 ; |
.equ TWBR5 = 5 ; |
.equ TWBR6 = 6 ; |
.equ TWBR7 = 7 ; |
; TWCR - TWI Control Register |
.equ TWIE = 0 ; TWI Interrupt Enable |
.equ TWEN = 2 ; TWI Enable Bit |
.equ TWWC = 3 ; TWI Write Collition Flag |
.equ TWSTO = 4 ; TWI Stop Condition Bit |
.equ TWSTA = 5 ; TWI Start Condition Bit |
.equ TWEA = 6 ; TWI Enable Acknowledge Bit |
.equ TWINT = 7 ; TWI Interrupt Flag |
; TWSR - TWI Status Register |
.equ TWPS0 = 0 ; TWI Prescaler |
.equ TWPS1 = 1 ; TWI Prescaler |
.equ TWS3 = 3 ; TWI Status |
.equ TWS4 = 4 ; TWI Status |
.equ TWS5 = 5 ; TWI Status |
.equ TWS6 = 6 ; TWI Status |
.equ TWS7 = 7 ; TWI Status |
; TWDR - TWI Data register |
.equ TWD0 = 0 ; TWI Data Register Bit 0 |
.equ TWD1 = 1 ; TWI Data Register Bit 1 |
.equ TWD2 = 2 ; TWI Data Register Bit 2 |
.equ TWD3 = 3 ; TWI Data Register Bit 3 |
.equ TWD4 = 4 ; TWI Data Register Bit 4 |
.equ TWD5 = 5 ; TWI Data Register Bit 5 |
.equ TWD6 = 6 ; TWI Data Register Bit 6 |
.equ TWD7 = 7 ; TWI Data Register Bit 7 |
; TWAR - TWI (Slave) Address register |
.equ TWGCE = 0 ; TWI General Call Recognition Enable Bit |
.equ TWA0 = 1 ; TWI (Slave) Address register Bit 0 |
.equ TWA1 = 2 ; TWI (Slave) Address register Bit 1 |
.equ TWA2 = 3 ; TWI (Slave) Address register Bit 2 |
.equ TWA3 = 4 ; TWI (Slave) Address register Bit 3 |
.equ TWA4 = 5 ; TWI (Slave) Address register Bit 4 |
.equ TWA5 = 6 ; TWI (Slave) Address register Bit 5 |
.equ TWA6 = 7 ; TWI (Slave) Address register Bit 6 |
; ***** BANDGAP ********************** |
; BGCRR - Bandgap Calibration of Resistor Ladder |
.equ BGCR0 = 0 ; Bandgap Calibration of Resistor Ladder Bit 0 |
.equ BGCR1 = 1 ; Bandgap Calibration of Resistor Ladder Bit 1 |
.equ BGCR2 = 2 ; Bandgap Calibration of Resistor Ladder Bit 2 |
.equ BGCR3 = 3 ; Bandgap Calibration of Resistor Ladder Bit 3 |
.equ BGCR4 = 4 ; Bandgap Calibration of Resistor Ladder Bit 4 |
.equ BGCR5 = 5 ; Bandgap Calibration of Resistor Ladder Bit 5 |
.equ BGCR6 = 6 ; Bandgap Calibration of Resistor Ladder Bit 6 |
.equ BGCR7 = 7 ; Bandgap Calibration of Resistor Ladder Bit 7 |
; BGCCR - Bandgap Calibration Register |
.equ BGCC0 = 0 ; BG Calibration of PTAT Current Bit 0 |
.equ BGCC1 = 1 ; BG Calibration of PTAT Current Bit 1 |
.equ BGCC2 = 2 ; BG Calibration of PTAT Current Bit 2 |
.equ BGCC3 = 3 ; BG Calibration of PTAT Current Bit 3 |
.equ BGCC4 = 4 ; BG Calibration of PTAT Current Bit 4 |
.equ BGCC5 = 5 ; BG Calibration of PTAT Current Bit 5 |
.equ BGEN = 7 ; Setting the BGEN bit to one will enable the bandgap voltage reference. This bit must be set before enabling the CC_ADC or V_ADC, and must remain set while either ADC is enabled. |
; ***** EEPROM *********************** |
; EEDR - EEPROM Data Register |
.equ EEDR0 = 0 ; EEPROM Data Register bit 0 |
.equ EEDR1 = 1 ; EEPROM Data Register bit 1 |
.equ EEDR2 = 2 ; EEPROM Data Register bit 2 |
.equ EEDR3 = 3 ; EEPROM Data Register bit 3 |
.equ EEDR4 = 4 ; EEPROM Data Register bit 4 |
.equ EEDR5 = 5 ; EEPROM Data Register bit 5 |
.equ EEDR6 = 6 ; EEPROM Data Register bit 6 |
.equ EEDR7 = 7 ; EEPROM Data Register bit 7 |
; EECR - EEPROM Control Register |
.equ EERE = 0 ; EEPROM Read Enable |
.equ EEWE = 1 ; EEPROM Write Enable |
.equ EEMWE = 2 ; EEPROM Master Write Enable |
.equ EERIE = 3 ; EEPROM Ready Interrupt Enable |
.equ EEPM0 = 4 ; EEPROM Programming Mode Bits |
.equ EEPM1 = 5 ; EEPROM Programming Mode Bits |
; ***** LOCKSBITS ******************************************************** |
.equ LB1 = 0 ; Lock bit |
.equ LB2 = 1 ; Lock bit |
.equ BLB01 = 2 ; Boot Lock bit |
.equ BLB02 = 3 ; Boot Lock bit |
.equ BLB11 = 4 ; Boot lock bit |
.equ BLB12 = 5 ; Boot lock bit |
; ***** FUSES ************************************************************ |
; LOW fuse bits |
.equ SUT0 = 1 ; Select start-up time |
.equ SUT1 = 2 ; Select start-up time |
.equ BOOTRST = 3 ; Select reset vector |
.equ BOOTSZ0 = 4 ; Select boot size |
.equ BOOTSZ1 = 5 ; Select boot size |
.equ EESAVE = 6 ; EEPROM memory is preserved through chip erase |
.equ WDTON = 7 ; Watchdog Timer Always On |
; HIGH fuse bits |
.equ JTAGEN = 0 ; Enable JTAG |
.equ OCDEN = 1 ; Enable OCD |
; ***** CPU REGISTER DEFINITIONS ***************************************** |
.def XH = r27 |
.def XL = r26 |
.def YH = r29 |
.def YL = r28 |
.def ZH = r31 |
.def ZL = r30 |
; ***** DATA MEMORY DECLARATIONS ***************************************** |
.equ FLASHEND = 0x4fff ; Note: Word address |
.equ IOEND = 0x00ff |
.equ SRAM_START = 0x0100 |
.equ SRAM_SIZE = 2048 |
.equ RAMEND = 0x08ff |
.equ XRAMEND = 0x07ff |
.equ E2END = 0x01ff |
.equ EEPROMEND = 0x01ff |
.equ EEADRBITS = 9 |
#pragma AVRPART MEMORY PROG_FLASH 40960 |
#pragma AVRPART MEMORY EEPROM 512 |
#pragma AVRPART MEMORY INT_SRAM SIZE 2048 |
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x100 |
; ***** BOOTLOADER DECLARATIONS ****************************************** |
.equ NRWW_START_ADDR = 0x4800 |
.equ NRWW_STOP_ADDR = 0x4fff |
.equ RWW_START_ADDR = 0x0 |
.equ RWW_STOP_ADDR = 0x47ff |
.equ PAGESIZE = 32 |
.equ FIRSTBOOTSTART = 0x4f00 |
.equ SECONDBOOTSTART = 0x4e00 |
.equ THIRDBOOTSTART = 0x4c00 |
.equ FOURTHBOOTSTART = 0x4800 |
.equ SMALLBOOTSTART = FIRSTBOOTSTART |
.equ LARGEBOOTSTART = FOURTHBOOTSTART |
; ***** INTERRUPT VECTORS ************************************************ |
.equ BPINTaddr = 0x0002 ; Battery Protection Interrupt |
.equ INT0addr = 0x0004 ; External Interrupt Request 0 |
.equ INT1addr = 0x0006 ; External Interrupt Request 1 |
.equ INT2addr = 0x0008 ; External Interrupt Request 2 |
.equ INT3addr = 0x000a ; External Interrupt Request 3 |
.equ PCI0addr = 0x000c ; Pin Change Interrupt 0 |
.equ PCI1addr = 0x000e ; Pin Change Interrupt 1 |
.equ WDTaddr = 0x0010 ; Watchdog Timeout Interrupt |
.equ WUTaddr = 0x0012 ; Wakeup timer overflow |
.equ OC1addr = 0x0014 ; Timer/Counter 1 Compare Match |
.equ OVF1addr = 0x0016 ; Timer/Counter 1 Overflow |
.equ OC0Aaddr = 0x0018 ; Timer/Counter0 Compare A Match |
.equ OC0Baddr = 0x001a ; Timer/Counter0 Compare B Match |
.equ OVF0addr = 0x001c ; Timer/Counter0 Overflow |
.equ TWICDaddr = 0x001e ; Two-Wire Bus Connect/Disconnect |
.equ TWIaddr = 0x0020 ; Two-Wire Serial Interface |
.equ VADCaddr = 0x0022 ; Voltage ADC Conversion Complete |
.equ CADICaddr = 0x0024 ; Coulomb Counter ADC Conversion Complete |
.equ CADRCaddr = 0x0026 ; Coloumb Counter ADC Regular Current |
.equ CADACaddr = 0x0028 ; Coloumb Counter ADC Accumulator |
.equ ERDYaddr = 0x002a ; EEPROM Ready |
.equ SPMRaddr = 0x002c ; Store Program Memory Ready |
.equ INT_VECTORS_SIZE = 46 ; size in words |
#endif /* _M406DEF_INC_ */ |
; ***** END OF FILE ****************************************************** |
/contrib/toolchain/avra/includes/m48def.inc |
---|
0,0 → 1,948 |
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** |
;***** Created: 2005-01-11 10:31 ******* Source: ATmega48.xml ************ |
;************************************************************************* |
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y |
;* |
;* Number : AVR000 |
;* File Name : "m48def.inc" |
;* Title : Register/Bit Definitions for the ATmega48 |
;* Date : 2005-01-11 |
;* Version : 2.14 |
;* Support E-mail : avr@atmel.com |
;* Target MCU : ATmega48 |
;* |
;* DESCRIPTION |
;* When including this file in the assembly program file, all I/O register |
;* names and I/O register bit names appearing in the data book can be used. |
;* In addition, the six registers forming the three data pointers X, Y and |
;* Z have been assigned names XL - ZH. Highest RAM address for Internal |
;* SRAM is also defined |
;* |
;* The Register names are represented by their hexadecimal address. |
;* |
;* The Register Bit names are represented by their bit number (0-7). |
;* |
;* Please observe the difference in using the bit names with instructions |
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" |
;* (skip if bit in register set/cleared). The following example illustrates |
;* this: |
;* |
;* in r16,PORTB ;read PORTB latch |
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) |
;* out PORTB,r16 ;output to PORTB |
;* |
;* in r16,TIFR ;read the Timer Interrupt Flag Register |
;* sbrc r16,TOV0 ;test the overflow flag (use bit#) |
;* rjmp TOV0_is_set ;jump if set |
;* ... ;otherwise do something else |
;************************************************************************* |
#ifndef _M48DEF_INC_ |
#define _M48DEF_INC_ |
#pragma partinc 0 |
; ***** SPECIFY DEVICE *************************************************** |
.device ATmega48 |
#pragma AVRPART ADMIN PART_NAME ATmega48 |
.equ SIGNATURE_000 = 0x1e |
.equ SIGNATURE_001 = 0x92 |
.equ SIGNATURE_002 = 0x05 |
#pragma AVRPART CORE CORE_VERSION V2E |
; ***** I/O REGISTER DEFINITIONS ***************************************** |
; NOTE: |
; Definitions marked "MEMORY MAPPED"are extended I/O ports |
; and cannot be used with IN/OUT instructions |
.equ UDR0 = 0xc6 ; MEMORY MAPPED |
.equ UBRR0H = 0xc5 ; MEMORY MAPPED |
.equ UBRR0L = 0xc4 ; MEMORY MAPPED |
.equ UCSR0C = 0xc2 ; MEMORY MAPPED |
.equ UCSR0B = 0xc1 ; MEMORY MAPPED |
.equ UCSR0A = 0xc0 ; MEMORY MAPPED |
.equ TWAMR = 0xbd ; MEMORY MAPPED |
.equ TWCR = 0xbc ; MEMORY MAPPED |
.equ TWDR = 0xbb ; MEMORY MAPPED |
.equ TWAR = 0xba ; MEMORY MAPPED |
.equ TWSR = 0xb9 ; MEMORY MAPPED |
.equ TWBR = 0xb8 ; MEMORY MAPPED |
.equ ASSR = 0xb6 ; MEMORY MAPPED |
.equ PRR = 0x64 ; MEMORY MAPPED |
.equ OCR2B = 0xb4 ; MEMORY MAPPED |
.equ OCR2A = 0xb3 ; MEMORY MAPPED |
.equ TCNT2 = 0xb2 ; MEMORY MAPPED |
.equ TCCR2B = 0xb1 ; MEMORY MAPPED |
.equ TCCR2A = 0xb0 ; MEMORY MAPPED |
.equ OCR1BH = 0x8b ; MEMORY MAPPED |
.equ OCR1BL = 0x8a ; MEMORY MAPPED |
.equ OCR1AH = 0x89 ; MEMORY MAPPED |
.equ OCR1AL = 0x88 ; MEMORY MAPPED |
.equ ICR1H = 0x87 ; MEMORY MAPPED |
.equ ICR1L = 0x86 ; MEMORY MAPPED |
.equ TCNT1H = 0x85 ; MEMORY MAPPED |
.equ TCNT1L = 0x84 ; MEMORY MAPPED |
.equ TCCR1C = 0x82 ; MEMORY MAPPED |
.equ TCCR1B = 0x81 ; MEMORY MAPPED |
.equ TCCR1A = 0x80 ; MEMORY MAPPED |
.equ DIDR1 = 0x7f ; MEMORY MAPPED |
.equ DIDR0 = 0x7e ; MEMORY MAPPED |
.equ ADMUX = 0x7c ; MEMORY MAPPED |
.equ ADCSRB = 0x7b ; MEMORY MAPPED |
.equ ADCSRA = 0x7a ; MEMORY MAPPED |
.equ ADCH = 0x79 ; MEMORY MAPPED |
.equ ADCL = 0x78 ; MEMORY MAPPED |
.equ TIMSK2 = 0x70 ; MEMORY MAPPED |
.equ TIMSK1 = 0x6f ; MEMORY MAPPED |
.equ TIMSK0 = 0x6e ; MEMORY MAPPED |
.equ PCMSK2 = 0x6d ; MEMORY MAPPED |
.equ PCMSK1 = 0x6c ; MEMORY MAPPED |
.equ PCMSK0 = 0x6b ; MEMORY MAPPED |
.equ EICRA = 0x69 ; MEMORY MAPPED |
.equ PCICR = 0x68 ; MEMORY MAPPED |
.equ OSCCAL = 0x66 ; MEMORY MAPPED |
.equ CLKPR = 0x61 ; MEMORY MAPPED |
.equ WDTCSR = 0x60 ; MEMORY MAPPED |
.equ SREG = 0x3f |
.equ SPH = 0x3e |
.equ SPL = 0x3d |
.equ SPMCSR = 0x37 |
.equ MCUCR = 0x35 |
.equ MCUSR = 0x34 |
.equ SMCR = 0x33 |
.equ ACSR = 0x30 |
.equ SPDR = 0x2e |
.equ SPSR = 0x2d |
.equ SPCR = 0x2c |
.equ GPIOR2 = 0x2b |
.equ GPIOR1 = 0x2a |
.equ OCR0B = 0x28 |
.equ OCR0A = 0x27 |
.equ TCNT0 = 0x26 |
.equ TCCR0B = 0x25 |
.equ TCCR0A = 0x24 |
.equ GTCCR = 0x23 |
.equ EEARH = 0x22 |
.equ EEARL = 0x21 |
.equ EEDR = 0x20 |
.equ EECR = 0x1f |
.equ GPIOR0 = 0x1e |
.equ EIMSK = 0x1d |
.equ EIFR = 0x1c |
.equ PCIFR = 0x1b |
.equ TIFR2 = 0x17 |
.equ TIFR1 = 0x16 |
.equ TIFR0 = 0x15 |
.equ PORTD = 0x0b |
.equ DDRD = 0x0a |
.equ PIND = 0x09 |
.equ PORTC = 0x08 |
.equ DDRC = 0x07 |
.equ PINC = 0x06 |
.equ PORTB = 0x05 |
.equ DDRB = 0x04 |
.equ PINB = 0x03 |
; ***** BIT DEFINITIONS ************************************************** |
; ***** USART0 *********************** |
; UDR0 - USART I/O Data Register |
.equ UDR0_0 = 0 ; USART I/O Data Register bit 0 |
.equ UDR0_1 = 1 ; USART I/O Data Register bit 1 |
.equ UDR0_2 = 2 ; USART I/O Data Register bit 2 |
.equ UDR0_3 = 3 ; USART I/O Data Register bit 3 |
.equ UDR0_4 = 4 ; USART I/O Data Register bit 4 |
.equ UDR0_5 = 5 ; USART I/O Data Register bit 5 |
.equ UDR0_6 = 6 ; USART I/O Data Register bit 6 |
.equ UDR0_7 = 7 ; USART I/O Data Register bit 7 |
; UCSR0A - USART Control and Status Register A |
.equ MPCM0 = 0 ; Multi-processor Communication Mode |
.equ U2X0 = 1 ; Double the USART transmission speed |
.equ UPE0 = 2 ; Parity Error |
.equ DOR0 = 3 ; Data overRun |
.equ FE0 = 4 ; Framing Error |
.equ UDRE0 = 5 ; USART Data Register Empty |
.equ TXC0 = 6 ; USART Transmitt Complete |
.equ RXC0 = 7 ; USART Receive Complete |
; UCSR0B - USART Control and Status Register B |
.equ TXB80 = 0 ; Transmit Data Bit 8 |
.equ RXB80 = 1 ; Receive Data Bit 8 |
.equ UCSZ02 = 2 ; Character Size |
.equ TXEN0 = 3 ; Transmitter Enable |
.equ RXEN0 = 4 ; Receiver Enable |
.equ UDRIE0 = 5 ; USART Data register Empty Interrupt Enable |
.equ TXCIE0 = 6 ; TX Complete Interrupt Enable |
.equ RXCIE0 = 7 ; RX Complete Interrupt Enable |
; UCSR0C - USART Control and Status Register C |
.equ UCPOL0 = 0 ; Clock Polarity |
.equ UCSZ00 = 1 ; Character Size |
.equ UCPHA0 = UCSZ00 ; For compatibility |
.equ UCSZ01 = 2 ; Character Size |
.equ UDORD0 = UCSZ01 ; For compatibility |
.equ USBS0 = 3 ; Stop Bit Select |
.equ UPM00 = 4 ; Parity Mode Bit 0 |
.equ UPM01 = 5 ; Parity Mode Bit 1 |
.equ UMSEL00 = 6 ; USART Mode Select |
.equ UMSEL0 = UMSEL00 ; For compatibility |
.equ UMSEL01 = 7 ; USART Mode Select |
.equ UMSEL1 = UMSEL01 ; For compatibility |
; ***** TWI ************************** |
; TWAMR - TWI (Slave) Address Mask Register |
.equ TWAM0 = 1 ; |
.equ TWAMR0 = TWAM0 ; For compatibility |
.equ TWAM1 = 2 ; |
.equ TWAMR1 = TWAM1 ; For compatibility |
.equ TWAM2 = 3 ; |
.equ TWAMR2 = TWAM2 ; For compatibility |
.equ TWAM3 = 4 ; |
.equ TWAMR3 = TWAM3 ; For compatibility |
.equ TWAM4 = 5 ; |
.equ TWAMR4 = TWAM4 ; For compatibility |
.equ TWAM5 = 6 ; |
.equ TWAMR5 = TWAM5 ; For compatibility |
.equ TWAM6 = 7 ; |
.equ TWAMR6 = TWAM6 ; For compatibility |
; TWBR - TWI Bit Rate register |
.equ TWBR0 = 0 ; |
.equ TWBR1 = 1 ; |
.equ TWBR2 = 2 ; |
.equ TWBR3 = 3 ; |
.equ TWBR4 = 4 ; |
.equ TWBR5 = 5 ; |
.equ TWBR6 = 6 ; |
.equ TWBR7 = 7 ; |
; TWCR - TWI Control Register |
.equ TWIE = 0 ; TWI Interrupt Enable |
.equ TWEN = 2 ; TWI Enable Bit |
.equ TWWC = 3 ; TWI Write Collition Flag |
.equ TWSTO = 4 ; TWI Stop Condition Bit |
.equ TWSTA = 5 ; TWI Start Condition Bit |
.equ TWEA = 6 ; TWI Enable Acknowledge Bit |
.equ TWINT = 7 ; TWI Interrupt Flag |
; TWSR - TWI Status Register |
.equ TWPS0 = 0 ; TWI Prescaler |
.equ TWPS1 = 1 ; TWI Prescaler |
.equ TWS3 = 3 ; TWI Status |
.equ TWS4 = 4 ; TWI Status |
.equ TWS5 = 5 ; TWI Status |
.equ TWS6 = 6 ; TWI Status |
.equ TWS7 = 7 ; TWI Status |
; TWDR - TWI Data register |
.equ TWD0 = 0 ; TWI Data Register Bit 0 |
.equ TWD1 = 1 ; TWI Data Register Bit 1 |
.equ TWD2 = 2 ; TWI Data Register Bit 2 |
.equ TWD3 = 3 ; TWI Data Register Bit 3 |
.equ TWD4 = 4 ; TWI Data Register Bit 4 |
.equ TWD5 = 5 ; TWI Data Register Bit 5 |
.equ TWD6 = 6 ; TWI Data Register Bit 6 |
.equ TWD7 = 7 ; TWI Data Register Bit 7 |
; TWAR - TWI (Slave) Address register |
.equ TWGCE = 0 ; TWI General Call Recognition Enable Bit |
.equ TWA0 = 1 ; TWI (Slave) Address register Bit 0 |
.equ TWA1 = 2 ; TWI (Slave) Address register Bit 1 |
.equ TWA2 = 3 ; TWI (Slave) Address register Bit 2 |
.equ TWA3 = 4 ; TWI (Slave) Address register Bit 3 |
.equ TWA4 = 5 ; TWI (Slave) Address register Bit 4 |
.equ TWA5 = 6 ; TWI (Slave) Address register Bit 5 |
.equ TWA6 = 7 ; TWI (Slave) Address register Bit 6 |
; ***** TIMER_COUNTER_1 ************** |
; TIMSK1 - Timer/Counter Interrupt Mask Register |
.equ TOIE1 = 0 ; Timer/Counter1 Overflow Interrupt Enable |
.equ OCIE1A = 1 ; Timer/Counter1 Output CompareA Match Interrupt Enable |
.equ OCIE1B = 2 ; Timer/Counter1 Output CompareB Match Interrupt Enable |
.equ ICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable |
; TIFR1 - Timer/Counter Interrupt Flag register |
.equ TOV1 = 0 ; Timer/Counter1 Overflow Flag |
.equ OCF1A = 1 ; Output Compare Flag 1A |
.equ OCF1B = 2 ; Output Compare Flag 1B |
.equ ICF1 = 5 ; Input Capture Flag 1 |
; TCCR1A - Timer/Counter1 Control Register A |
.equ WGM10 = 0 ; Waveform Generation Mode |
.equ WGM11 = 1 ; Waveform Generation Mode |
.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0 |
.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1 |
.equ COM1A0 = 6 ; Comparet Ouput Mode 1A, bit 0 |
.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1 |
; TCCR1B - Timer/Counter1 Control Register B |
.equ CS10 = 0 ; Prescaler source of Timer/Counter 1 |
.equ CS11 = 1 ; Prescaler source of Timer/Counter 1 |
.equ CS12 = 2 ; Prescaler source of Timer/Counter 1 |
.equ WGM12 = 3 ; Waveform Generation Mode |
.equ WGM13 = 4 ; Waveform Generation Mode |
.equ ICES1 = 6 ; Input Capture 1 Edge Select |
.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler |
; TCCR1C - Timer/Counter1 Control Register C |
.equ FOC1B = 6 ; |
.equ FOC1A = 7 ; |
; GTCCR - General Timer/Counter Control Register |
.equ PSRSYNC = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0 |
.equ TSM = 7 ; Timer/Counter Synchronization Mode |
; ***** TIMER_COUNTER_2 ************** |
; TIMSK2 - Timer/Counter Interrupt Mask register |
.equ TOIE2 = 0 ; Timer/Counter2 Overflow Interrupt Enable |
.equ TOIE2A = TOIE2 ; For compatibility |
.equ OCIE2A = 1 ; Timer/Counter2 Output Compare Match A Interrupt Enable |
.equ OCIE2B = 2 ; Timer/Counter2 Output Compare Match B Interrupt Enable |
; TIFR2 - Timer/Counter Interrupt Flag Register |
.equ TOV2 = 0 ; Timer/Counter2 Overflow Flag |
.equ OCF2A = 1 ; Output Compare Flag 2A |
.equ OCF2B = 2 ; Output Compare Flag 2B |
; TCCR2A - Timer/Counter2 Control Register A |
.equ WGM20 = 0 ; Waveform Genration Mode |
.equ WGM21 = 1 ; Waveform Genration Mode |
.equ COM2B0 = 4 ; Compare Output Mode bit 0 |
.equ COM2B1 = 5 ; Compare Output Mode bit 1 |
.equ COM2A0 = 6 ; Compare Output Mode bit 1 |
.equ COM2A1 = 7 ; Compare Output Mode bit 1 |
; TCCR2B - Timer/Counter2 Control Register B |
.equ CS20 = 0 ; Clock Select bit 0 |
.equ CS21 = 1 ; Clock Select bit 1 |
.equ CS22 = 2 ; Clock Select bit 2 |
.equ WGM22 = 3 ; Waveform Generation Mode |
.equ FOC2B = 6 ; Force Output Compare B |
.equ FOC2A = 7 ; Force Output Compare A |
; TCNT2 - Timer/Counter2 |
.equ TCNT2_0 = 0 ; Timer/Counter 2 bit 0 |
.equ TCNT2_1 = 1 ; Timer/Counter 2 bit 1 |
.equ TCNT2_2 = 2 ; Timer/Counter 2 bit 2 |
.equ TCNT2_3 = 3 ; Timer/Counter 2 bit 3 |
.equ TCNT2_4 = 4 ; Timer/Counter 2 bit 4 |
.equ TCNT2_5 = 5 ; Timer/Counter 2 bit 5 |
.equ TCNT2_6 = 6 ; Timer/Counter 2 bit 6 |
.equ TCNT2_7 = 7 ; Timer/Counter 2 bit 7 |
; OCR2A - Timer/Counter2 Output Compare Register A |
.equ OCR2_0 = 0 ; Timer/Counter2 Output Compare Register Bit 0 |
.equ OCR2_1 = 1 ; Timer/Counter2 Output Compare Register Bit 1 |
.equ OCR2_2 = 2 ; Timer/Counter2 Output Compare Register Bit 2 |
.equ OCR2_3 = 3 ; Timer/Counter2 Output Compare Register Bit 3 |
.equ OCR2_4 = 4 ; Timer/Counter2 Output Compare Register Bit 4 |
.equ OCR2_5 = 5 ; Timer/Counter2 Output Compare Register Bit 5 |
.equ OCR2_6 = 6 ; Timer/Counter2 Output Compare Register Bit 6 |
.equ OCR2_7 = 7 ; Timer/Counter2 Output Compare Register Bit 7 |
; OCR2B - Timer/Counter2 Output Compare Register B |
;.equ OCR2_0 = 0 ; Timer/Counter2 Output Compare Register Bit 0 |
;.equ OCR2_1 = 1 ; Timer/Counter2 Output Compare Register Bit 1 |
;.equ OCR2_2 = 2 ; Timer/Counter2 Output Compare Register Bit 2 |
;.equ OCR2_3 = 3 ; Timer/Counter2 Output Compare Register Bit 3 |
;.equ OCR2_4 = 4 ; Timer/Counter2 Output Compare Register Bit 4 |
;.equ OCR2_5 = 5 ; Timer/Counter2 Output Compare Register Bit 5 |
;.equ OCR2_6 = 6 ; Timer/Counter2 Output Compare Register Bit 6 |
;.equ OCR2_7 = 7 ; Timer/Counter2 Output Compare Register Bit 7 |
; ASSR - Asynchronous Status Register |
.equ TCR2BUB = 0 ; Timer/Counter Control Register2 Update Busy |
.equ TCR2AUB = 1 ; Timer/Counter Control Register2 Update Busy |
.equ OCR2BUB = 2 ; Output Compare Register 2 Update Busy |
.equ OCR2AUB = 3 ; Output Compare Register2 Update Busy |
.equ TCN2UB = 4 ; Timer/Counter2 Update Busy |
.equ AS2 = 5 ; Asynchronous Timer/Counter2 |
.equ EXCLK = 6 ; Enable External Clock Input |
; GTCCR - General Timer Counter Control register |
.equ PSRASY = 1 ; Prescaler Reset Timer/Counter2 |
.equ PSR2 = PSRASY ; For compatibility |
;.equ TSM = 7 ; Timer/Counter Synchronization Mode |
; ***** AD_CONVERTER ***************** |
; ADMUX - The ADC multiplexer Selection Register |
.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits |
.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits |
.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits |
.equ MUX3 = 3 ; Analog Channel and Gain Selection Bits |
.equ ADLAR = 5 ; Left Adjust Result |
.equ REFS0 = 6 ; Reference Selection Bit 0 |
.equ REFS1 = 7 ; Reference Selection Bit 1 |
; ADCSRA - The ADC Control and Status register A |
.equ ADPS0 = 0 ; ADC Prescaler Select Bits |
.equ ADPS1 = 1 ; ADC Prescaler Select Bits |
.equ ADPS2 = 2 ; ADC Prescaler Select Bits |
.equ ADIE = 3 ; ADC Interrupt Enable |
.equ ADIF = 4 ; ADC Interrupt Flag |
.equ ADATE = 5 ; ADC Auto Trigger Enable |
.equ ADSC = 6 ; ADC Start Conversion |
.equ ADEN = 7 ; ADC Enable |
; ADCSRB - The ADC Control and Status register B |
.equ ADTS0 = 0 ; ADC Auto Trigger Source bit 0 |
.equ ADTS1 = 1 ; ADC Auto Trigger Source bit 1 |
.equ ADTS2 = 2 ; ADC Auto Trigger Source bit 2 |
.equ ACME = 6 ; |
; ADCH - ADC Data Register High Byte |
.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0 |
.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1 |
.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2 |
.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3 |
.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4 |
.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5 |
.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6 |
.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7 |
; ADCL - ADC Data Register Low Byte |
.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0 |
.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1 |
.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2 |
.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3 |
.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4 |
.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5 |
.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6 |
.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7 |
; DIDR0 - Digital Input Disable Register |
.equ ADC0D = 0 ; |
.equ ADC1D = 1 ; |
.equ ADC2D = 2 ; |
.equ ADC3D = 3 ; |
.equ ADC4D = 4 ; |
.equ ADC5D = 5 ; |
; ***** ANALOG_COMPARATOR ************ |
; ACSR - Analog Comparator Control And Status Register |
.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 |
.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 |
.equ ACIC = 2 ; |
.equ ACIE = 3 ; Analog Comparator Interrupt Enable |
.equ ACI = 4 ; Analog Comparator Interrupt Flag |
.equ ACO = 5 ; Analog Compare Output |
.equ ACBG = 6 ; Analog Comparator Bandgap Select |
.equ ACD = 7 ; Analog Comparator Disable |
; DIDR1 - Digital Input Disable Register 1 |
.equ AIN0D = 0 ; AIN0 Digital Input Disable |
.equ AIN1D = 1 ; AIN1 Digital Input Disable |
; ***** PORTB ************************ |
; PORTB - Port B Data Register |
.equ PORTB0 = 0 ; Port B Data Register bit 0 |
.equ PB0 = 0 ; For compatibility |
.equ PORTB1 = 1 ; Port B Data Register bit 1 |
.equ PB1 = 1 ; For compatibility |
.equ PORTB2 = 2 ; Port B Data Register bit 2 |
.equ PB2 = 2 ; For compatibility |
.equ PORTB3 = 3 ; Port B Data Register bit 3 |
.equ PB3 = 3 ; For compatibility |
.equ PORTB4 = 4 ; Port B Data Register bit 4 |
.equ PB4 = 4 ; For compatibility |
.equ PORTB5 = 5 ; Port B Data Register bit 5 |
.equ PB5 = 5 ; For compatibility |
.equ PORTB6 = 6 ; Port B Data Register bit 6 |
.equ PB6 = 6 ; For compatibility |
.equ PORTB7 = 7 ; Port B Data Register bit 7 |
.equ PB7 = 7 ; For compatibility |
; DDRB - Port B Data Direction Register |
.equ DDB0 = 0 ; Port B Data Direction Register bit 0 |
.equ DDB1 = 1 ; Port B Data Direction Register bit 1 |
.equ DDB2 = 2 ; Port B Data Direction Register bit 2 |
.equ DDB3 = 3 ; Port B Data Direction Register bit 3 |
.equ DDB4 = 4 ; Port B Data Direction Register bit 4 |
.equ DDB5 = 5 ; Port B Data Direction Register bit 5 |
.equ DDB6 = 6 ; Port B Data Direction Register bit 6 |
.equ DDB7 = 7 ; Port B Data Direction Register bit 7 |
; PINB - Port B Input Pins |
.equ PINB0 = 0 ; Port B Input Pins bit 0 |
.equ PINB1 = 1 ; Port B Input Pins bit 1 |
.equ PINB2 = 2 ; Port B Input Pins bit 2 |
.equ PINB3 = 3 ; Port B Input Pins bit 3 |
.equ PINB4 = 4 ; Port B Input Pins bit 4 |
.equ PINB5 = 5 ; Port B Input Pins bit 5 |
.equ PINB6 = 6 ; Port B Input Pins bit 6 |
.equ PINB7 = 7 ; Port B Input Pins bit 7 |
; ***** PORTC ************************ |
; PORTC - Port C Data Register |
.equ PORTC0 = 0 ; Port C Data Register bit 0 |
.equ PC0 = 0 ; For compatibility |
.equ PORTC1 = 1 ; Port C Data Register bit 1 |
.equ PC1 = 1 ; For compatibility |
.equ PORTC2 = 2 ; Port C Data Register bit 2 |
.equ PC2 = 2 ; For compatibility |
.equ PORTC3 = 3 ; Port C Data Register bit 3 |
.equ PC3 = 3 ; For compatibility |
.equ PORTC4 = 4 ; Port C Data Register bit 4 |
.equ PC4 = 4 ; For compatibility |
.equ PORTC5 = 5 ; Port C Data Register bit 5 |
.equ PC5 = 5 ; For compatibility |
.equ PORTC6 = 6 ; Port C Data Register bit 6 |
.equ PC6 = 6 ; For compatibility |
; DDRC - Port C Data Direction Register |
.equ DDC0 = 0 ; Port C Data Direction Register bit 0 |
.equ DDC1 = 1 ; Port C Data Direction Register bit 1 |
.equ DDC2 = 2 ; Port C Data Direction Register bit 2 |
.equ DDC3 = 3 ; Port C Data Direction Register bit 3 |
.equ DDC4 = 4 ; Port C Data Direction Register bit 4 |
.equ DDC5 = 5 ; Port C Data Direction Register bit 5 |
.equ DDC6 = 6 ; Port C Data Direction Register bit 6 |
; PINC - Port C Input Pins |
.equ PINC0 = 0 ; Port C Input Pins bit 0 |
.equ PINC1 = 1 ; Port C Input Pins bit 1 |
.equ PINC2 = 2 ; Port C Input Pins bit 2 |
.equ PINC3 = 3 ; Port C Input Pins bit 3 |
.equ PINC4 = 4 ; Port C Input Pins bit 4 |
.equ PINC5 = 5 ; Port C Input Pins bit 5 |
.equ PINC6 = 6 ; Port C Input Pins bit 6 |
; ***** PORTD ************************ |
; PORTD - Port D Data Register |
.equ PORTD0 = 0 ; Port D Data Register bit 0 |
.equ PD0 = 0 ; For compatibility |
.equ PORTD1 = 1 ; Port D Data Register bit 1 |
.equ PD1 = 1 ; For compatibility |
.equ PORTD2 = 2 ; Port D Data Register bit 2 |
.equ PD2 = 2 ; For compatibility |
.equ PORTD3 = 3 ; Port D Data Register bit 3 |
.equ PD3 = 3 ; For compatibility |
.equ PORTD4 = 4 ; Port D Data Register bit 4 |
.equ PD4 = 4 ; For compatibility |
.equ PORTD5 = 5 ; Port D Data Register bit 5 |
.equ PD5 = 5 ; For compatibility |
.equ PORTD6 = 6 ; Port D Data Register bit 6 |
.equ PD6 = 6 ; For compatibility |
.equ PORTD7 = 7 ; Port D Data Register bit 7 |
.equ PD7 = 7 ; For compatibility |
; DDRD - Port D Data Direction Register |
.equ DDD0 = 0 ; Port D Data Direction Register bit 0 |
.equ DDD1 = 1 ; Port D Data Direction Register bit 1 |
.equ DDD2 = 2 ; Port D Data Direction Register bit 2 |
.equ DDD3 = 3 ; Port D Data Direction Register bit 3 |
.equ DDD4 = 4 ; Port D Data Direction Register bit 4 |
.equ DDD5 = 5 ; Port D Data Direction Register bit 5 |
.equ DDD6 = 6 ; Port D Data Direction Register bit 6 |
.equ DDD7 = 7 ; Port D Data Direction Register bit 7 |
; PIND - Port D Input Pins |
.equ PIND0 = 0 ; Port D Input Pins bit 0 |
.equ PIND1 = 1 ; Port D Input Pins bit 1 |
.equ PIND2 = 2 ; Port D Input Pins bit 2 |
.equ PIND3 = 3 ; Port D Input Pins bit 3 |
.equ PIND4 = 4 ; Port D Input Pins bit 4 |
.equ PIND5 = 5 ; Port D Input Pins bit 5 |
.equ PIND6 = 6 ; Port D Input Pins bit 6 |
.equ PIND7 = 7 ; Port D Input Pins bit 7 |
; ***** TIMER_COUNTER_0 ************** |
; TIMSK0 - Timer/Counter0 Interrupt Mask Register |
.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable |
.equ OCIE0A = 1 ; Timer/Counter0 Output Compare Match A Interrupt Enable |
.equ OCIE0B = 2 ; Timer/Counter0 Output Compare Match B Interrupt Enable |
; TIFR0 - Timer/Counter0 Interrupt Flag register |
.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag |
.equ OCF0A = 1 ; Timer/Counter0 Output Compare Flag 0A |
.equ OCF0B = 2 ; Timer/Counter0 Output Compare Flag 0B |
; TCCR0A - Timer/Counter Control Register A |
.equ WGM00 = 0 ; Waveform Generation Mode |
.equ WGM01 = 1 ; Waveform Generation Mode |
.equ COM0B0 = 4 ; Compare Output Mode, Fast PWm |
.equ COM0B1 = 5 ; Compare Output Mode, Fast PWm |
.equ COM0A0 = 6 ; Compare Output Mode, Phase Correct PWM Mode |
.equ COM0A1 = 7 ; Compare Output Mode, Phase Correct PWM Mode |
; TCCR0B - Timer/Counter Control Register B |
.equ CS00 = 0 ; Clock Select |
.equ CS01 = 1 ; Clock Select |
.equ CS02 = 2 ; Clock Select |
.equ WGM02 = 3 ; |
.equ FOC0B = 6 ; Force Output Compare B |
.equ FOC0A = 7 ; Force Output Compare A |
; TCNT0 - Timer/Counter0 |
.equ TCNT0_0 = 0 ; |
.equ TCNT0_1 = 1 ; |
.equ TCNT0_2 = 2 ; |
.equ TCNT0_3 = 3 ; |
.equ TCNT0_4 = 4 ; |
.equ TCNT0_5 = 5 ; |
.equ TCNT0_6 = 6 ; |
.equ TCNT0_7 = 7 ; |
; OCR0A - Timer/Counter0 Output Compare Register |
.equ OCROA_0 = 0 ; |
.equ OCROA_1 = 1 ; |
.equ OCROA_2 = 2 ; |
.equ OCROA_3 = 3 ; |
.equ OCROA_4 = 4 ; |
.equ OCROA_5 = 5 ; |
.equ OCROA_6 = 6 ; |
.equ OCROA_7 = 7 ; |
; OCR0B - Timer/Counter0 Output Compare Register |
.equ OCR0B_0 = 0 ; |
.equ OCR0B_1 = 1 ; |
.equ OCR0B_2 = 2 ; |
.equ OCR0B_3 = 3 ; |
.equ OCR0B_4 = 4 ; |
.equ OCR0B_5 = 5 ; |
.equ OCR0B_6 = 6 ; |
.equ OCR0B_7 = 7 ; |
; GTCCR - General Timer/Counter Control Register |
;.equ PSRSYNC = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0 |
.equ PSR10 = PSRSYNC ; For compatibility |
;.equ TSM = 7 ; Timer/Counter Synchronization Mode |
; ***** EXTERNAL_INTERRUPT *********** |
; EICRA - External Interrupt Control Register |
.equ ISC00 = 0 ; External Interrupt Sense Control 0 Bit 0 |
.equ ISC01 = 1 ; External Interrupt Sense Control 0 Bit 1 |
.equ ISC10 = 2 ; External Interrupt Sense Control 1 Bit 0 |
.equ ISC11 = 3 ; External Interrupt Sense Control 1 Bit 1 |
; EIMSK - External Interrupt Mask Register |
.equ INT0 = 0 ; External Interrupt Request 0 Enable |
.equ INT1 = 1 ; External Interrupt Request 1 Enable |
; EIFR - External Interrupt Flag Register |
.equ INTF0 = 0 ; External Interrupt Flag 0 |
.equ INTF1 = 1 ; External Interrupt Flag 1 |
; PCMSK2 - Pin Change Mask Register 2 |
.equ PCINT16 = 0 ; Pin Change Enable Mask 16 |
.equ PCINT17 = 1 ; Pin Change Enable Mask 17 |
.equ PCINT18 = 2 ; Pin Change Enable Mask 18 |
.equ PCINT19 = 3 ; Pin Change Enable Mask 19 |
.equ PCINT20 = 4 ; Pin Change Enable Mask 20 |
.equ PCINT21 = 5 ; Pin Change Enable Mask 21 |
.equ PCINT22 = 6 ; Pin Change Enable Mask 22 |
.equ PCINT23 = 7 ; Pin Change Enable Mask 23 |
; PCMSK1 - Pin Change Mask Register 1 |
.equ PCINT8 = 0 ; Pin Change Enable Mask 8 |
.equ PCINT9 = 1 ; Pin Change Enable Mask 9 |
.equ PCINT10 = 2 ; Pin Change Enable Mask 10 |
.equ PCINT11 = 3 ; Pin Change Enable Mask 11 |
.equ PCINT12 = 4 ; Pin Change Enable Mask 12 |
.equ PCINT13 = 5 ; Pin Change Enable Mask 13 |
.equ PCINT14 = 6 ; Pin Change Enable Mask 14 |
; PCMSK0 - Pin Change Mask Register 0 |
.equ PCINT0 = 0 ; Pin Change Enable Mask 0 |
.equ PCINT1 = 1 ; Pin Change Enable Mask 1 |
.equ PCINT2 = 2 ; Pin Change Enable Mask 2 |
.equ PCINT3 = 3 ; Pin Change Enable Mask 3 |
.equ PCINT4 = 4 ; Pin Change Enable Mask 4 |
.equ PCINT5 = 5 ; Pin Change Enable Mask 5 |
.equ PCINT6 = 6 ; Pin Change Enable Mask 6 |
.equ PCINT7 = 7 ; Pin Change Enable Mask 7 |
; PCIFR - Pin Change Interrupt Flag Register |
.equ PCIF0 = 0 ; Pin Change Interrupt Flag 0 |
.equ PCIF1 = 1 ; Pin Change Interrupt Flag 1 |
.equ PCIF2 = 2 ; Pin Change Interrupt Flag 2 |
; ***** SPI ************************** |
; SPDR - SPI Data Register |
.equ SPDR0 = 0 ; SPI Data Register bit 0 |
.equ SPDR1 = 1 ; SPI Data Register bit 1 |
.equ SPDR2 = 2 ; SPI Data Register bit 2 |
.equ SPDR3 = 3 ; SPI Data Register bit 3 |
.equ SPDR4 = 4 ; SPI Data Register bit 4 |
.equ SPDR5 = 5 ; SPI Data Register bit 5 |
.equ SPDR6 = 6 ; SPI Data Register bit 6 |
.equ SPDR7 = 7 ; SPI Data Register bit 7 |
; SPSR - SPI Status Register |
.equ SPI2X = 0 ; Double SPI Speed Bit |
.equ WCOL = 6 ; Write Collision Flag |
.equ SPIF = 7 ; SPI Interrupt Flag |
; SPCR - SPI Control Register |
.equ SPR0 = 0 ; SPI Clock Rate Select 0 |
.equ SPR1 = 1 ; SPI Clock Rate Select 1 |
.equ CPHA = 2 ; Clock Phase |
.equ CPOL = 3 ; Clock polarity |
.equ MSTR = 4 ; Master/Slave Select |
.equ DORD = 5 ; Data Order |
.equ SPE = 6 ; SPI Enable |
.equ SPIE = 7 ; SPI Interrupt Enable |
; ***** CPU ************************** |
; SREG - Status Register |
.equ SREG_C = 0 ; Carry Flag |
.equ SREG_Z = 1 ; Zero Flag |
.equ SREG_N = 2 ; Negative Flag |
.equ SREG_V = 3 ; Two's Complement Overflow Flag |
.equ SREG_S = 4 ; Sign Bit |
.equ SREG_H = 5 ; Half Carry Flag |
.equ SREG_T = 6 ; Bit Copy Storage |
.equ SREG_I = 7 ; Global Interrupt Enable |
; OSCCAL - Oscillator Calibration Value |
.equ CAL0 = 0 ; Oscillator Calibration Value Bit0 |
.equ CAL1 = 1 ; Oscillator Calibration Value Bit1 |
.equ CAL2 = 2 ; Oscillator Calibration Value Bit2 |
.equ CAL3 = 3 ; Oscillator Calibration Value Bit3 |
.equ CAL4 = 4 ; Oscillator Calibration Value Bit4 |
.equ CAL5 = 5 ; Oscillator Calibration Value Bit5 |
.equ CAL6 = 6 ; Oscillator Calibration Value Bit6 |
.equ CAL7 = 7 ; Oscillator Calibration Value Bit7 |
; CLKPR - Clock Prescale Register |
.equ CLKPS0 = 0 ; Clock Prescaler Select Bit 0 |
.equ CLKPS1 = 1 ; Clock Prescaler Select Bit 1 |
.equ CLKPS2 = 2 ; Clock Prescaler Select Bit 2 |
.equ CLKPS3 = 3 ; Clock Prescaler Select Bit 3 |
.equ CLKPCE = 7 ; Clock Prescaler Change Enable |
; SPMCSR - Store Program Memory Control Register |
.equ SELFPRGEN = 0 ; Self Programming Enable |
.equ PGERS = 1 ; Page Erase |
.equ PGWRT = 2 ; Page Write |
.equ BLBSET = 3 ; Boot Lock Bit Set |
.equ RWWSRE = 4 ; Read-While-Write section read enable |
.equ RWWSB = 6 ; Read-While-Write Section Busy |
.equ SPMIE = 7 ; SPM Interrupt Enable |
; MCUCR - MCU Control Register |
.equ IVCE = 0 ; |
.equ PUD = 4 ; |
; MCUSR - MCU Status Register |
.equ PORF = 0 ; Power-on reset flag |
.equ EXTRF = 1 ; External Reset Flag |
.equ EXTREF = EXTRF ; For compatibility |
.equ BORF = 2 ; Brown-out Reset Flag |
.equ WDRF = 3 ; Watchdog Reset Flag |
; SMCR - |
.equ SE = 0 ; |
.equ SM0 = 1 ; |
.equ SM1 = 2 ; |
.equ SM2 = 3 ; |
; GPIOR2 - General Purpose I/O Register 2 |
.equ GPIOR20 = 0 ; |
.equ GPIOR21 = 1 ; |
.equ GPIOR22 = 2 ; |
.equ GPIOR23 = 3 ; |
.equ GPIOR24 = 4 ; |
.equ GPIOR25 = 5 ; |
.equ GPIOR26 = 6 ; |
.equ GPIOR27 = 7 ; |
; GPIOR1 - General Purpose I/O Register 1 |
.equ GPIOR10 = 0 ; |
.equ GPIOR11 = 1 ; |
.equ GPIOR12 = 2 ; |
.equ GPIOR13 = 3 ; |
.equ GPIOR14 = 4 ; |
.equ GPIOR15 = 5 ; |
.equ GPIOR16 = 6 ; |
.equ GPIOR17 = 7 ; |
; GPIOR0 - General Purpose I/O Register 0 |
.equ GPIOR00 = 0 ; |
.equ GPIOR01 = 1 ; |
.equ GPIOR02 = 2 ; |
.equ GPIOR03 = 3 ; |
.equ GPIOR04 = 4 ; |
.equ GPIOR05 = 5 ; |
.equ GPIOR06 = 6 ; |
.equ GPIOR07 = 7 ; |
; PRR - Power Reduction Register |
.equ PRADC = 0 ; Power Reduction ADC |
.equ PRUSART0 = 1 ; Power Reduction USART |
.equ PRSPI = 2 ; Power Reduction Serial Peripheral Interface |
.equ PRTIM1 = 3 ; Power Reduction Timer/Counter1 |
.equ PRTIM0 = 5 ; Power Reduction Timer/Counter0 |
.equ PRTIM2 = 6 ; Power Reduction Timer/Counter2 |
.equ PRTWI = 7 ; Power Reduction TWI |
; PCICR - |
.equ PCIE0 = 0 ; |
.equ PCIE1 = 1 ; |
.equ PCIE2 = 2 ; |
; ***** WATCHDOG ********************* |
; WDTCSR - Watchdog Timer Control Register |
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 |
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 |
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 |
.equ WDE = 3 ; Watch Dog Enable |
.equ WDCE = 4 ; Watchdog Change Enable |
.equ WDP3 = 5 ; Watchdog Timer Prescaler Bit 3 |
.equ WDIE = 6 ; Watchdog Timeout Interrupt Enable |
.equ WDIF = 7 ; Watchdog Timeout Interrupt Flag |
; ***** EEPROM *********************** |
; EEARL - EEPROM Address Register Low Byte |
.equ EEAR0 = 0 ; EEPROM Read/Write Access Bit 0 |
.equ EEAR1 = 1 ; EEPROM Read/Write Access Bit 1 |
.equ EEAR2 = 2 ; EEPROM Read/Write Access Bit 2 |
.equ EEAR3 = 3 ; EEPROM Read/Write Access Bit 3 |
.equ EEAR4 = 4 ; EEPROM Read/Write Access Bit 4 |
.equ EEAR5 = 5 ; EEPROM Read/Write Access Bit 5 |
.equ EEAR6 = 6 ; EEPROM Read/Write Access Bit 6 |
.equ EEAR7 = 7 ; EEPROM Read/Write Access Bit 7 |
; EEDR - EEPROM Data Register |
.equ EEDR0 = 0 ; EEPROM Data Register bit 0 |
.equ EEDR1 = 1 ; EEPROM Data Register bit 1 |
.equ EEDR2 = 2 ; EEPROM Data Register bit 2 |
.equ EEDR3 = 3 ; EEPROM Data Register bit 3 |
.equ EEDR4 = 4 ; EEPROM Data Register bit 4 |
.equ EEDR5 = 5 ; EEPROM Data Register bit 5 |
.equ EEDR6 = 6 ; EEPROM Data Register bit 6 |
.equ EEDR7 = 7 ; EEPROM Data Register bit 7 |
; EECR - EEPROM Control Register |
.equ EERE = 0 ; EEPROM Read Enable |
.equ EEPE = 1 ; EEPROM Write Enable |
.equ EEWE = EEPE ; For compatibility |
.equ EEMPE = 2 ; EEPROM Master Write Enable |
.equ EEMWE = EEMPE ; For compatibility |
.equ EERIE = 3 ; EEPROM Ready Interrupt Enable |
.equ EEPM0 = 4 ; EEPROM Programming Mode Bit 0 |
.equ EEPM1 = 5 ; EEPROM Programming Mode Bit 1 |
; ***** LOCKSBITS ******************************************************** |
.equ LB1 = 0 ; Lock bit |
.equ LB2 = 1 ; Lock bit |
.equ BLB01 = 2 ; Boot Lock bit |
.equ BLB02 = 3 ; Boot Lock bit |
.equ BLB11 = 4 ; Boot lock bit |
.equ BLB12 = 5 ; Boot lock bit |
; ***** FUSES ************************************************************ |
; LOW fuse bits |
.equ CKSEL0 = 0 ; Select Clock Source |
.equ CKSEL1 = 1 ; Select Clock Source |
.equ CKSEL2 = 2 ; Select Clock Source |
.equ CKSEL3 = 3 ; Select Clock Source |
.equ SUT0 = 4 ; Select start-up time |
.equ SUT1 = 5 ; Select start-up time |
.equ CKOUT = 6 ; Clock output |
.equ CKDIV8 = 7 ; Divide clock by 8 |
; HIGH fuse bits |
.equ BODLEVEL0 = 0 ; Brown-out Detector trigger level |
.equ BODLEVEL1 = 1 ; Brown-out Detector trigger level |
.equ BODLEVEL2 = 2 ; Brown-out Detector trigger level |
.equ EESAVE = 3 ; EEPROM memory is preserved through chip erase |
.equ WDTON = 4 ; Watchdog Timer Always On |
.equ SPIEN = 5 ; Enable Serial programming and Data Downloading |
.equ DWEN = 6 ; debugWIRE Enable |
.equ RSTDISBL = 7 ; External reset disable |
; EXTENDED fuse bits |
;.equ SELFPRGEN = 0 ; Self Programming Enable |
; ***** CPU REGISTER DEFINITIONS ***************************************** |
.def XH = r27 |
.def XL = r26 |
.def YH = r29 |
.def YL = r28 |
.def ZH = r31 |
.def ZL = r30 |
; ***** DATA MEMORY DECLARATIONS ***************************************** |
.equ FLASHEND = 0x07ff ; Note: Word address |
.equ IOEND = 0x00ff |
.equ SRAM_START = 0x0100 |
.equ SRAM_SIZE = 512 |
.equ RAMEND = 0x02ff |
.equ XRAMEND = 0x0000 |
.equ E2END = 0x00ff |
.equ EEPROMEND = 0x00ff |
.equ EEADRBITS = 8 |
#pragma AVRPART MEMORY PROG_FLASH 4096 |
#pragma AVRPART MEMORY EEPROM 256 |
#pragma AVRPART MEMORY INT_SRAM SIZE 512 |
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x100 |
; ***** BOOTLOADER DECLARATIONS ****************************************** |
.equ NRWW_START_ADDR = 0x0 |
.equ NRWW_STOP_ADDR = 0x7ff |
.equ RWW_START_ADDR = 0x0 |
.equ RWW_STOP_ADDR = 0x0 |
.equ PAGESIZE = 32 |
; ***** INTERRUPT VECTORS ************************************************ |
.equ INT0addr = 0x0001 ; External Interrupt Request 0 |
.equ INT1addr = 0x0002 ; External Interrupt Request 1 |
.equ PCI0addr = 0x0003 ; Pin Change Interrupt Request 0 |
.equ PCI1addr = 0x0004 ; Pin Change Interrupt Request 0 |
.equ PCI2addr = 0x0005 ; Pin Change Interrupt Request 1 |
.equ WDTaddr = 0x0006 ; Watchdog Time-out Interrupt |
.equ OC2Aaddr = 0x0007 ; Timer/Counter2 Compare Match A |
.equ OC2Baddr = 0x0008 ; Timer/Counter2 Compare Match A |
.equ OVF2addr = 0x0009 ; Timer/Counter2 Overflow |
.equ ICP1addr = 0x000a ; Timer/Counter1 Capture Event |
.equ OC1Aaddr = 0x000b ; Timer/Counter1 Compare Match A |
.equ OC1Baddr = 0x000c ; Timer/Counter1 Compare Match B |
.equ OVF1addr = 0x000d ; Timer/Counter1 Overflow |
.equ OC0Aaddr = 0x000e ; TimerCounter0 Compare Match A |
.equ OC0Baddr = 0x001f ; TimerCounter0 Compare Match B |
.equ OVF0addr = 0x0010 ; Timer/Couner0 Overflow |
.equ SPIaddr = 0x0011 ; SPI Serial Transfer Complete |
.equ URXCaddr = 0x0012 ; USART Rx Complete |
.equ UDREaddr = 0x0013 ; USART, Data Register Empty |
.equ UTXCaddr = 0x0014 ; USART Tx Complete |
.equ ADCCaddr = 0x0015 ; ADC Conversion Complete |
.equ ERDYaddr = 0x0016 ; EEPROM Ready |
.equ ACIaddr = 0x0017 ; Analog Comparator |
.equ TWIaddr = 0x0018 ; Two-wire Serial Interface |
.equ SPMRaddr = 0x0019 ; Store Program Memory Read |
.equ INT_VECTORS_SIZE = 26 ; size in words |
#endif /* _M48DEF_INC_ */ |
; ***** END OF FILE ****************************************************** |
/contrib/toolchain/avra/includes/m649def.inc |
---|
0,0 → 1,1242 |
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** |
;***** Created: 2005-01-11 10:31 ******* Source: ATmega649.xml *********** |
;************************************************************************* |
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y |
;* |
;* Number : AVR000 |
;* File Name : "m649def.inc" |
;* Title : Register/Bit Definitions for the ATmega649 |
;* Date : 2005-01-11 |
;* Version : 2.14 |
;* Support E-mail : avr@atmel.com |
;* Target MCU : ATmega649 |
;* |
;* DESCRIPTION |
;* When including this file in the assembly program file, all I/O register |
;* names and I/O register bit names appearing in the data book can be used. |
;* In addition, the six registers forming the three data pointers X, Y and |
;* Z have been assigned names XL - ZH. Highest RAM address for Internal |
;* SRAM is also defined |
;* |
;* The Register names are represented by their hexadecimal address. |
;* |
;* The Register Bit names are represented by their bit number (0-7). |
;* |
;* Please observe the difference in using the bit names with instructions |
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" |
;* (skip if bit in register set/cleared). The following example illustrates |
;* this: |
;* |
;* in r16,PORTB ;read PORTB latch |
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) |
;* out PORTB,r16 ;output to PORTB |
;* |
;* in r16,TIFR ;read the Timer Interrupt Flag Register |
;* sbrc r16,TOV0 ;test the overflow flag (use bit#) |
;* rjmp TOV0_is_set ;jump if set |
;* ... ;otherwise do something else |
;************************************************************************* |
#ifndef _M649DEF_INC_ |
#define _M649DEF_INC_ |
#pragma partinc 0 |
; ***** SPECIFY DEVICE *************************************************** |
.device ATmega649 |
#pragma AVRPART ADMIN PART_NAME ATmega649 |
.equ SIGNATURE_000 = 0x1e |
.equ SIGNATURE_001 = 0x96 |
.equ SIGNATURE_002 = 0x03 |
#pragma AVRPART CORE CORE_VERSION V2E |
; ***** I/O REGISTER DEFINITIONS ***************************************** |
; NOTE: |
; Definitions marked "MEMORY MAPPED"are extended I/O ports |
; and cannot be used with IN/OUT instructions |
.equ LCDDR19 = 0xff ; MEMORY MAPPED |
.equ LCDDR18 = 0xfe ; MEMORY MAPPED |
.equ LCDDR17 = 0xfd ; MEMORY MAPPED |
.equ LCDDR16 = 0xfc ; MEMORY MAPPED |
.equ LCDDR15 = 0xfb ; MEMORY MAPPED |
.equ LCDDR14 = 0xfa ; MEMORY MAPPED |
.equ LCDDR13 = 0xf9 ; MEMORY MAPPED |
.equ LCDDR12 = 0xf8 ; MEMORY MAPPED |
.equ LCDDR11 = 0xf7 ; MEMORY MAPPED |
.equ LCDDR10 = 0xf6 ; MEMORY MAPPED |
.equ LCDDR9 = 0xf5 ; MEMORY MAPPED |
.equ LCDDR8 = 0xf4 ; MEMORY MAPPED |
.equ LCDDR7 = 0xf3 ; MEMORY MAPPED |
.equ LCDDR6 = 0xf2 ; MEMORY MAPPED |
.equ LCDDR5 = 0xf1 ; MEMORY MAPPED |
.equ LCDDR4 = 0xf0 ; MEMORY MAPPED |
.equ LCDDR3 = 0xef ; MEMORY MAPPED |
.equ LCDDR2 = 0xee ; MEMORY MAPPED |
.equ LCDDR1 = 0xed ; MEMORY MAPPED |
.equ LCDDR0 = 0xec ; MEMORY MAPPED |
.equ LCDCCR = 0xe7 ; MEMORY MAPPED |
.equ LCDFRR = 0xe6 ; MEMORY MAPPED |
.equ LCDCRB = 0xe5 ; MEMORY MAPPED |
.equ LCDCRA = 0xe4 ; MEMORY MAPPED |
.equ PORTJ = 0xdd ; MEMORY MAPPED |
.equ DDRJ = 0xdc ; MEMORY MAPPED |
.equ PINJ = 0xdb ; MEMORY MAPPED |
.equ PORTH = 0xda ; MEMORY MAPPED |
.equ DDRH = 0xd9 ; MEMORY MAPPED |
.equ PINH = 0xd8 ; MEMORY MAPPED |
.equ UDR = 0xc6 ; MEMORY MAPPED |
.equ UBRRH = 0xc5 ; MEMORY MAPPED |
.equ UBRRL = 0xc4 ; MEMORY MAPPED |
.equ UCSRC = 0xc2 ; MEMORY MAPPED |
.equ UCSRB = 0xc1 ; MEMORY MAPPED |
.equ UCSRA = 0xc0 ; MEMORY MAPPED |
.equ USIDR = 0xba ; MEMORY MAPPED |
.equ USISR = 0xb9 ; MEMORY MAPPED |
.equ USICR = 0xb8 ; MEMORY MAPPED |
.equ ASSR = 0xb6 ; MEMORY MAPPED |
.equ OCR2A = 0xb3 ; MEMORY MAPPED |
.equ TCNT2 = 0xb2 ; MEMORY MAPPED |
.equ TCCR2A = 0xb0 ; MEMORY MAPPED |
.equ OCR1BH = 0x8b ; MEMORY MAPPED |
.equ OCR1BL = 0x8a ; MEMORY MAPPED |
.equ OCR1AH = 0x89 ; MEMORY MAPPED |
.equ OCR1AL = 0x88 ; MEMORY MAPPED |
.equ ICR1H = 0x87 ; MEMORY MAPPED |
.equ ICR1L = 0x86 ; MEMORY MAPPED |
.equ TCNT1H = 0x85 ; MEMORY MAPPED |
.equ TCNT1L = 0x84 ; MEMORY MAPPED |
.equ TCCR1C = 0x82 ; MEMORY MAPPED |
.equ TCCR1B = 0x81 ; MEMORY MAPPED |
.equ TCCR1A = 0x80 ; MEMORY MAPPED |
.equ DIDR1 = 0x7f ; MEMORY MAPPED |
.equ DIDR0 = 0x7e ; MEMORY MAPPED |
.equ ADMUX = 0x7c ; MEMORY MAPPED |
.equ ADCSRB = 0x7b ; MEMORY MAPPED |
.equ ADCSRA = 0x7a ; MEMORY MAPPED |
.equ ADCH = 0x79 ; MEMORY MAPPED |
.equ ADCL = 0x78 ; MEMORY MAPPED |
.equ PCMSK3 = 0x73 ; MEMORY MAPPED |
.equ TIMSK2 = 0x70 ; MEMORY MAPPED |
.equ TIMSK1 = 0x6f ; MEMORY MAPPED |
.equ TIMSK0 = 0x6e ; MEMORY MAPPED |
.equ PCMSK2 = 0x6d ; MEMORY MAPPED |
.equ PCMSK1 = 0x6c ; MEMORY MAPPED |
.equ PCMSK0 = 0x6b ; MEMORY MAPPED |
.equ EICRA = 0x69 ; MEMORY MAPPED |
.equ OSCCAL = 0x66 ; MEMORY MAPPED |
.equ PRR = 0x64 ; MEMORY MAPPED |
.equ CLKPR = 0x61 ; MEMORY MAPPED |
.equ WDTCR = 0x60 ; MEMORY MAPPED |
.equ SREG = 0x3f |
.equ SPH = 0x3e |
.equ SPL = 0x3d |
.equ SPMCSR = 0x37 |
.equ MCUCR = 0x35 |
.equ MCUSR = 0x34 |
.equ SMCR = 0x33 |
.equ OCDR = 0x31 |
.equ ACSR = 0x30 |
.equ SPDR = 0x2e |
.equ SPSR = 0x2d |
.equ SPCR = 0x2c |
.equ GPIOR2 = 0x2b |
.equ GPIOR1 = 0x2a |
.equ OCR0A = 0x27 |
.equ TCNT0 = 0x26 |
.equ TCCR0A = 0x24 |
.equ GTCCR = 0x23 |
.equ EEARH = 0x22 |
.equ EEARL = 0x21 |
.equ EEDR = 0x20 |
.equ EECR = 0x1f |
.equ GPIOR0 = 0x1e |
.equ EIMSK = 0x1d |
.equ EIFR = 0x1c |
.equ TIFR2 = 0x17 |
.equ TIFR1 = 0x16 |
.equ TIFR0 = 0x15 |
.equ PORTG = 0x14 |
.equ DDRG = 0x13 |
.equ PING = 0x12 |
.equ PORTF = 0x11 |
.equ DDRF = 0x10 |
.equ PINF = 0x0f |
.equ PORTE = 0x0e |
.equ DDRE = 0x0d |
.equ PINE = 0x0c |
.equ PORTD = 0x0b |
.equ DDRD = 0x0a |
.equ PIND = 0x09 |
.equ PORTC = 0x08 |
.equ DDRC = 0x07 |
.equ PINC = 0x06 |
.equ PORTB = 0x05 |
.equ DDRB = 0x04 |
.equ PINB = 0x03 |
.equ PORTA = 0x02 |
.equ DDRA = 0x01 |
.equ PINA = 0x00 |
; ***** BIT DEFINITIONS ************************************************** |
; ***** AD_CONVERTER ***************** |
; ADMUX - The ADC multiplexer Selection Register |
.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits |
.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits |
.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits |
.equ MUX3 = 3 ; Analog Channel and Gain Selection Bits |
.equ MUX4 = 4 ; Analog Channel and Gain Selection Bits |
.equ ADLAR = 5 ; Left Adjust Result |
.equ REFS0 = 6 ; Reference Selection Bit 0 |
.equ REFS1 = 7 ; Reference Selection Bit 1 |
; ADCSRA - The ADC Control and Status register |
.equ ADPS0 = 0 ; ADC Prescaler Select Bits |
.equ ADPS1 = 1 ; ADC Prescaler Select Bits |
.equ ADPS2 = 2 ; ADC Prescaler Select Bits |
.equ ADIE = 3 ; ADC Interrupt Enable |
.equ ADIF = 4 ; ADC Interrupt Flag |
.equ ADATE = 5 ; ADC Auto Trigger Enable |
.equ ADSC = 6 ; ADC Start Conversion |
.equ ADEN = 7 ; ADC Enable |
; ADCH - ADC Data Register High Byte |
.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0 |
.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1 |
.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2 |
.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3 |
.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4 |
.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5 |
.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6 |
.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7 |
; ADCL - ADC Data Register Low Byte |
.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0 |
.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1 |
.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2 |
.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3 |
.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4 |
.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5 |
.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6 |
.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7 |
; ADCSRB - ADC Control and Status Register B |
.equ ADTS0 = 0 ; ADC Auto Trigger Source 0 |
.equ ADTS1 = 1 ; ADC Auto Trigger Source 1 |
.equ ADTS2 = 2 ; ADC Auto Trigger Source 2 |
; DIDR0 - Digital Input Disable Register 0 |
.equ ADC0D = 0 ; ADC0 Digital input Disable |
.equ ADC1D = 1 ; ADC1 Digital input Disable |
.equ ADC2D = 2 ; ADC2 Digital input Disable |
.equ ADC3D = 3 ; ADC3 Digital input Disable |
.equ ADC4D = 4 ; ADC4 Digital input Disable |
.equ ADC5D = 5 ; ADC5 Digital input Disable |
.equ ADC6D = 6 ; ADC6 Digital input Disable |
.equ ADC7D = 7 ; ADC7 Digital input Disable |
; ***** ANALOG_COMPARATOR ************ |
; ADCSRB - ADC Control and Status Register B |
.equ ACME = 6 ; Analog Comparator Multiplexer Enable |
; ACSR - Analog Comparator Control And Status Register |
.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 |
.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 |
.equ ACIC = 2 ; Analog Comparator Input Capture Enable |
.equ ACIE = 3 ; Analog Comparator Interrupt Enable |
.equ ACI = 4 ; Analog Comparator Interrupt Flag |
.equ ACO = 5 ; Analog Compare Output |
.equ ACBG = 6 ; Analog Comparator Bandgap Select |
.equ ACD = 7 ; Analog Comparator Disable |
; DIDR1 - Digital Input Disable Register 1 |
.equ AIN0D = 0 ; AIN0 Digital Input Disable |
.equ AIN1D = 1 ; AIN1 Digital Input Disable |
; ***** SPI ************************** |
; SPDR - SPI Data Register |
.equ SPDR0 = 0 ; SPI Data Register bit 0 |
.equ SPDR1 = 1 ; SPI Data Register bit 1 |
.equ SPDR2 = 2 ; SPI Data Register bit 2 |
.equ SPDR3 = 3 ; SPI Data Register bit 3 |
.equ SPDR4 = 4 ; SPI Data Register bit 4 |
.equ SPDR5 = 5 ; SPI Data Register bit 5 |
.equ SPDR6 = 6 ; SPI Data Register bit 6 |
.equ SPDR7 = 7 ; SPI Data Register bit 7 |
; SPSR - SPI Status Register |
.equ SPI2X = 0 ; Double SPI Speed Bit |
.equ WCOL = 6 ; Write Collision Flag |
.equ SPIF = 7 ; SPI Interrupt Flag |
; SPCR - SPI Control Register |
.equ SPR0 = 0 ; SPI Clock Rate Select 0 |
.equ SPR1 = 1 ; SPI Clock Rate Select 1 |
.equ CPHA = 2 ; Clock Phase |
.equ CPOL = 3 ; Clock polarity |
.equ MSTR = 4 ; Master/Slave Select |
.equ DORD = 5 ; Data Order |
.equ SPE = 6 ; SPI Enable |
.equ SPIE = 7 ; SPI Interrupt Enable |
; ***** USI ************************** |
; USIDR - USI Data Register |
.equ USIDR0 = 0 ; USI Data Register bit 0 |
.equ USIDR1 = 1 ; USI Data Register bit 1 |
.equ USIDR2 = 2 ; USI Data Register bit 2 |
.equ USIDR3 = 3 ; USI Data Register bit 3 |
.equ USIDR4 = 4 ; USI Data Register bit 4 |
.equ USIDR5 = 5 ; USI Data Register bit 5 |
.equ USIDR6 = 6 ; USI Data Register bit 6 |
.equ USIDR7 = 7 ; USI Data Register bit 7 |
; USISR - USI Status Register |
.equ USICNT0 = 0 ; USI Counter Value Bit 0 |
.equ USICNT1 = 1 ; USI Counter Value Bit 1 |
.equ USICNT2 = 2 ; USI Counter Value Bit 2 |
.equ USICNT3 = 3 ; USI Counter Value Bit 3 |
.equ USIDC = 4 ; Data Output Collision |
.equ USIPF = 5 ; Stop Condition Flag |
.equ USIOIF = 6 ; Counter Overflow Interrupt Flag |
.equ USISIF = 7 ; Start Condition Interrupt Flag |
; USICR - USI Control Register |
.equ USITC = 0 ; Toggle Clock Port Pin |
.equ USICLK = 1 ; Clock Strobe |
.equ USICS0 = 2 ; USI Clock Source Select Bit 0 |
.equ USICS1 = 3 ; USI Clock Source Select Bit 1 |
.equ USIWM0 = 4 ; USI Wire Mode Bit 0 |
.equ USIWM1 = 5 ; USI Wire Mode Bit 1 |
.equ USIOIE = 6 ; Counter Overflow Interrupt Enable |
.equ USISIE = 7 ; Start Condition Interrupt Enable |
; ***** USART0 *********************** |
; UDR - USART I/O Data Register |
.equ UDR0 = UDR ; For compatibility |
.equ UDR00 = 0 ; USART I/O Data Register bit 0 |
.equ UDR01 = 1 ; USART I/O Data Register bit 1 |
.equ UDR02 = 2 ; USART I/O Data Register bit 2 |
.equ UDR03 = 3 ; USART I/O Data Register bit 3 |
.equ UDR04 = 4 ; USART I/O Data Register bit 4 |
.equ UDR05 = 5 ; USART I/O Data Register bit 5 |
.equ UDR06 = 6 ; USART I/O Data Register bit 6 |
.equ UDR07 = 7 ; USART I/O Data Register bit 7 |
; UCSRA - USART Control and Status Register A |
.equ UCSR0A = UCSRA ; For compatibility |
.equ USR = UCSRA ; For compatibility |
.equ MPCM = 0 ; Multi-processor Communication Mode |
.equ MPCM0 = MPCM ; For compatibility |
.equ U2X = 1 ; Double the USART Transmission Speed |
.equ U2X0 = U2X ; For compatibility |
.equ UPE = 2 ; USART Parity Error |
.equ UPE0 = UPE ; For compatibility |
.equ DOR = 3 ; Data OverRun |
.equ DOR0 = DOR ; For compatibility |
.equ FE = 4 ; Framing Error |
.equ FE0 = FE ; For compatibility |
.equ UDRE = 5 ; USART Data Register Empty |
.equ UDRE0 = UDRE ; For compatibility |
.equ TXC = 6 ; USART Transmit Complete |
.equ TXC0 = TXC ; For compatibility |
.equ RXC = 7 ; USART Receive Complete |
.equ RXC0 = RXC ; For compatibility |
; UCSRB - USART Control and Status Register B |
.equ UCSR0B = UCSRB ; For compatibility |
.equ UCR = UCSRB ; For compatibility |
.equ TXB8 = 0 ; Transmit Data Bit 8 |
.equ TXB80 = TXB8 ; For compatibility |
.equ RXB8 = 1 ; Receive Data Bit 8 |
.equ RXB80 = RXB8 ; For compatibility |
.equ UCSZ2 = 2 ; Character Size |
.equ UCSZ02 = UCSZ2 ; For compatibility |
.equ TXEN = 3 ; Transmitter Enable |
.equ TXEN0 = TXEN ; For compatibility |
.equ RXEN = 4 ; Receiver Enable |
.equ RXEN0 = RXEN ; For compatibility |
.equ UDRIE = 5 ; USART Data Register Empty Interrupt Enable |
.equ UDRIE0 = UDRIE ; For compatibility |
.equ TXCIE = 6 ; TX Complete Interrupt Enable |
.equ TXCIE0 = TXCIE ; For compatibility |
.equ RXCIE = 7 ; RX Complete Interrupt Enable |
.equ RXCIE0 = RXCIE ; For compatibility |
; UCSRC - USART Control and Status Register C |
.equ UCSR0C = UCSRC ; For compatibility |
.equ UCPOL = 0 ; Clock Polarity |
.equ UCPOL0 = UCPOL ; For compatibility |
.equ UCSZ0 = 1 ; Character Size |
.equ UCSZ00 = UCSZ0 ; For compatibility |
.equ UCSZ1 = 2 ; Character Size |
.equ UCSZ01 = UCSZ1 ; For compatibility |
.equ USBS = 3 ; Stop Bit Select |
.equ USBS0 = USBS ; For compatibility |
.equ UPM0 = 4 ; Parity Mode Bit 0 |
.equ UPM00 = UPM0 ; For compatibility |
.equ UPM1 = 5 ; Parity Mode Bit 1 |
.equ UPM01 = UPM1 ; For compatibility |
.equ UMSEL = 6 ; USART Mode Select |
.equ UMSEL0 = UMSEL ; For compatibility |
.equ UBRR0H = UBRRH ; For compatibility |
.equ UBRR0L = UBRRL ; For compatibility |
.equ UBRR0 = UBRRL ; For compatibility |
.equ UBRR = UBRRL ; For compatibility |
; ***** CPU ************************** |
; SREG - Status Register |
.equ SREG_C = 0 ; Carry Flag |
.equ SREG_Z = 1 ; Zero Flag |
.equ SREG_N = 2 ; Negative Flag |
.equ SREG_V = 3 ; Two's Complement Overflow Flag |
.equ SREG_S = 4 ; Sign Bit |
.equ SREG_H = 5 ; Half Carry Flag |
.equ SREG_T = 6 ; Bit Copy Storage |
.equ SREG_I = 7 ; Global Interrupt Enable |
; MCUCR - MCU Control Register |
.equ IVCE = 0 ; Interrupt Vector Change Enable |
.equ IVSEL = 1 ; Interrupt Vector Select |
.equ PUD = 4 ; Pull-up disable |
; MCUSR - MCU Status Register |
.equ PORF = 0 ; Power-on reset flag |
.equ EXTRF = 1 ; External Reset Flag |
.equ BORF = 2 ; Brown-out Reset Flag |
.equ WDRF = 3 ; Watchdog Reset Flag |
.equ JTRF = 4 ; JTAG Reset Flag |
; OSCCAL - Oscillator Calibration Value |
.equ CAL0 = 0 ; Oscillator Calibration Value Bit0 |
.equ CAL1 = 1 ; Oscillator Calibration Value Bit1 |
.equ CAL2 = 2 ; Oscillator Calibration Value Bit2 |
.equ CAL3 = 3 ; Oscillator Calibration Value Bit3 |
.equ CAL4 = 4 ; Oscillator Calibration Value Bit4 |
.equ CAL5 = 5 ; Oscillator Calibration Value Bit5 |
.equ CAL6 = 6 ; Oscillator Calibration Value Bit6 |
.equ CAL7 = 7 ; Oscillator Calibration Value Bit7 |
; CLKPR - Clock Prescale Register |
.equ CLKPS0 = 0 ; Clock Prescaler Select Bit 0 |
.equ CLKPS1 = 1 ; Clock Prescaler Select Bit 1 |
.equ CLKPS2 = 2 ; Clock Prescaler Select Bit 2 |
.equ CLKPS3 = 3 ; Clock Prescaler Select Bit 3 |
.equ CLKPCE = 7 ; Clock Prescaler Change Enable |
; PRR - Power Reduction Register |
.equ PRADC = 0 ; Power Reduction ADC |
.equ PRUSART0 = 1 ; Power Reduction USART |
.equ PRSPI = 2 ; Power Reduction Serial Peripheral Interface |
.equ PRTIM1 = 3 ; Power Reduction Timer/Counter1 |
.equ PRLCD = 4 ; Power Reduction LCD |
; SMCR - Sleep Mode Control Register |
.equ SE = 0 ; Sleep Enable |
.equ SM0 = 1 ; Sleep Mode Select bit 0 |
.equ SM1 = 2 ; Sleep Mode Select bit 1 |
.equ SM2 = 3 ; Sleep Mode Select bit 2 |
; GPIOR2 - General Purpose IO Register 2 |
.equ GPIOR20 = 0 ; General Purpose IO Register 2 bit 0 |
.equ GPIOR21 = 1 ; General Purpose IO Register 2 bit 1 |
.equ GPIOR22 = 2 ; General Purpose IO Register 2 bit 2 |
.equ GPIOR23 = 3 ; General Purpose IO Register 2 bit 3 |
.equ GPIOR24 = 4 ; General Purpose IO Register 2 bit 4 |
.equ GPIOR25 = 5 ; General Purpose IO Register 2 bit 5 |
.equ GPIOR26 = 6 ; General Purpose IO Register 2 bit 6 |
.equ GPIOR27 = 7 ; General Purpose IO Register 2 bit 7 |
; GPIOR1 - General Purpose IO Register 1 |
.equ GPIOR10 = 0 ; General Purpose IO Register 1 bit 0 |
.equ GPIOR11 = 1 ; General Purpose IO Register 1 bit 1 |
.equ GPIOR12 = 2 ; General Purpose IO Register 1 bit 2 |
.equ GPIOR13 = 3 ; General Purpose IO Register 1 bit 3 |
.equ GPIOR14 = 4 ; General Purpose IO Register 1 bit 4 |
.equ GPIOR15 = 5 ; General Purpose IO Register 1 bit 5 |
.equ GPIOR16 = 6 ; General Purpose IO Register 1 bit 6 |
.equ GPIOR17 = 7 ; General Purpose IO Register 1 bit 7 |
; GPIOR0 - General Purpose IO Register 0 |
.equ GPIOR00 = 0 ; General Purpose IO Register 0 bit 0 |
.equ GPIOR01 = 1 ; General Purpose IO Register 0 bit 1 |
.equ GPIOR02 = 2 ; General Purpose IO Register 0 bit 2 |
.equ GPIOR03 = 3 ; General Purpose IO Register 0 bit 3 |
.equ GPIOR04 = 4 ; General Purpose IO Register 0 bit 4 |
.equ GPIOR05 = 5 ; General Purpose IO Register 0 bit 5 |
.equ GPIOR06 = 6 ; General Purpose IO Register 0 bit 6 |
.equ GPIOR07 = 7 ; General Purpose IO Register 0 bit 7 |
; ***** JTAG ************************* |
; OCDR - On-Chip Debug Related Register in I/O Memory |
.equ OCDR0 = 0 ; On-Chip Debug Register Bit 0 |
.equ OCDR1 = 1 ; On-Chip Debug Register Bit 1 |
.equ OCDR2 = 2 ; On-Chip Debug Register Bit 2 |
.equ OCDR3 = 3 ; On-Chip Debug Register Bit 3 |
.equ OCDR4 = 4 ; On-Chip Debug Register Bit 4 |
.equ OCDR5 = 5 ; On-Chip Debug Register Bit 5 |
.equ OCDR6 = 6 ; On-Chip Debug Register Bit 6 |
.equ OCDR7 = 7 ; On-Chip Debug Register Bit 7 |
.equ IDRD = OCDR7 ; For compatibility |
; MCUCR - MCU Control Register |
.equ JTD = 7 ; JTAG Interface Disable |
; MCUSR - MCU Status Register |
;.equ JTRF = 4 ; JTAG Reset Flag |
; ***** MISC ************************* |
; LCDCRA - LCD Control Register A |
.equ LCDBL = 0 ; LCD Blanking |
.equ LCDIE = 3 ; LCD Interrupt Enable |
.equ LCDIF = 4 ; LCD Interrupt Flag |
.equ LCDAB = 6 ; LCD A or B waveform |
.equ LCDEN = 7 ; LCD Enable |
; LCDCRB - LCD Control and Status Register B |
.equ LCDPM0 = 0 ; LCD Port Mask 0 |
.equ LCDPM1 = 1 ; LCD Port Mask 1 |
.equ LCDPM2 = 2 ; LCD Port Mask 2 |
.equ LCDPM3 = 3 ; LCD Port Mask 3 |
.equ LCDMUX0 = 4 ; LCD Mux Select 0 |
.equ LCDMUX1 = 5 ; LCD Mux Select 1 |
.equ LCD2B = 6 ; LCD 1/2 Bias Select |
.equ LCDCS = 7 ; LCD CLock Select |
; LCDFRR - LCD Frame Rate Register |
.equ LCDCD0 = 0 ; LCD Clock Divider 0 |
.equ LCDCD1 = 1 ; LCD Clock Divider 1 |
.equ LCDCD2 = 2 ; LCD Clock Divider 2 |
.equ LCDPS0 = 4 ; LCD Prescaler Select 0 |
.equ LCDPS1 = 5 ; LCD Prescaler Select 1 |
.equ LCDPS2 = 6 ; LCD Prescaler Select 2 |
; LCDCCR - LCD Contrast Control Register |
.equ LCDCC0 = 0 ; LCD Contrast Control 0 |
.equ LCDCC1 = 1 ; LCD Contrast Control 1 |
.equ LCDCC2 = 2 ; LCD Contrast Control 2 |
.equ LCDCC3 = 3 ; LCD Contrast Control 3 |
.equ LCDDC0 = 5 ; |
.equ LCDDC1 = 6 ; |
.equ LCDDC2 = 7 ; |
; LCDDR18 - LCD Data Register 18 |
.equ SEG324 = 0 ; |
; LCDDR17 - LCD Data Register 17 |
.equ SEG316 = 0 ; |
.equ SEG317 = 1 ; |
.equ SEG318 = 2 ; |
.equ SEG319 = 3 ; |
.equ SEG320 = 4 ; |
.equ SEG321 = 5 ; |
.equ SEG322 = 6 ; |
.equ SEG323 = 7 ; |
; LCDDR16 - LCD Data Register 16 |
.equ SEG308 = 0 ; |
.equ SEG309 = 1 ; |
.equ SEG310 = 2 ; |
.equ SEG311 = 3 ; |
.equ SEG312 = 4 ; |
.equ SEG313 = 5 ; |
.equ SEG314 = 6 ; |
.equ SEG315 = 7 ; |
; LCDDR15 - LCD Data Register 15 |
.equ SEG300 = 0 ; |
.equ SEG301 = 1 ; |
.equ SEG302 = 2 ; |
.equ SEG303 = 3 ; |
.equ SEG304 = 4 ; |
.equ SEG305 = 5 ; |
.equ SEG306 = 6 ; |
.equ SEG307 = 7 ; |
; LCDDR13 - LCD Data Register 13 |
.equ SEG224 = 0 ; |
; LCDDR12 - LCD Data Register 12 |
.equ SEG216 = 0 ; |
.equ SEG217 = 1 ; |
.equ SEG218 = 2 ; |
.equ SEG219 = 3 ; |
.equ SEG220 = 4 ; |
.equ SEG221 = 5 ; |
.equ SEG222 = 6 ; |
.equ SEG223 = 7 ; |
; LCDDR11 - LCD Data Register 11 |
.equ SEG208 = 0 ; |
.equ SEG209 = 1 ; |
.equ SEG210 = 2 ; |
.equ SEG211 = 3 ; |
.equ SEG212 = 4 ; |
.equ SEG213 = 5 ; |
.equ SEG214 = 6 ; |
.equ SEG215 = 7 ; |
; LCDDR10 - LCD Data Register 10 |
.equ SEG200 = 0 ; |
.equ SEG201 = 1 ; |
.equ SEG202 = 2 ; |
.equ SEG203 = 3 ; |
.equ SEG204 = 4 ; |
.equ SEG205 = 5 ; |
.equ SEG206 = 6 ; |
.equ SEG207 = 7 ; |
; LCDDR8 - LCD Data Register 8 |
.equ SEG124 = 0 ; |
; LCDDR7 - LCD Data Register 7 |
.equ SEG116 = 0 ; |
.equ SEG117 = 1 ; |
.equ SEG118 = 2 ; |
.equ SEG119 = 3 ; |
.equ SEG120 = 4 ; |
.equ SEG121 = 5 ; |
.equ SEG122 = 6 ; |
.equ SEG123 = 7 ; |
; LCDDR6 - LCD Data Register 6 |
.equ SEG108 = 0 ; |
.equ SEG109 = 1 ; |
.equ SEG110 = 2 ; |
.equ SEG111 = 3 ; |
.equ SEG112 = 4 ; |
.equ SEG113 = 5 ; |
.equ SEG114 = 6 ; |
.equ SEG115 = 7 ; |
; LCDDR5 - LCD Data Register 5 |
.equ SEG100 = 0 ; |
.equ SEG101 = 1 ; |
.equ SEG102 = 2 ; |
.equ SEG103 = 3 ; |
.equ SEG104 = 4 ; |
.equ SEG105 = 5 ; |
.equ SEG106 = 6 ; |
.equ SEG107 = 7 ; |
; LCDDR3 - LCD Data Register 3 |
.equ SEG024 = 0 ; |
; LCDDR2 - LCD Data Register 2 |
.equ SEG016 = 0 ; |
.equ SEG017 = 1 ; |
.equ SEG018 = 2 ; |
.equ SEG019 = 3 ; |
.equ SEG020 = 4 ; |
.equ SEG021 = 5 ; |
.equ SEG022 = 6 ; |
.equ SEG023 = 7 ; |
; LCDDR1 - LCD Data Register 1 |
.equ SEG008 = 0 ; |
.equ SEG009 = 1 ; |
.equ SEG010 = 2 ; |
.equ SEG011 = 3 ; |
.equ SEG012 = 4 ; |
.equ SEG013 = 5 ; |
.equ SEG014 = 6 ; |
.equ SEG015 = 7 ; |
; LCDDR0 - LCD Data Register 0 |
.equ SEG000 = 0 ; |
.equ SEG001 = 1 ; |
.equ SEG002 = 2 ; |
.equ SEG003 = 3 ; |
.equ SEG004 = 4 ; |
.equ SEG005 = 5 ; |
.equ SEG006 = 6 ; |
.equ SEG007 = 7 ; |
; ***** EXTERNAL_INTERRUPT *********** |
; EICRA - External Interrupt Control Register A |
.equ ISC00 = 0 ; External Interrupt Sense Control 0 Bit 0 |
.equ ISC01 = 1 ; External Interrupt Sense Control 0 Bit 1 |
; EIMSK - External Interrupt Mask Register |
.equ INT0 = 0 ; External Interrupt Request 0 Enable |
.equ PCIE0 = 4 ; Pin Change Interrupt Enable 0 |
.equ PCIE1 = 5 ; Pin Change Interrupt Enable 1 |
.equ PCIE2 = 6 ; Pin Change Interrupt Enable 2 |
.equ PCIE3 = 7 ; Pin Change Interrupt Enable 3 |
; EIFR - External Interrupt Flag Register |
.equ INTF0 = 0 ; External Interrupt Flag 0 |
.equ PCIF0 = 4 ; Pin Change Interrupt Flag 0 |
.equ PCIF1 = 5 ; Pin Change Interrupt Flag 1 |
.equ PCIF2 = 6 ; Pin Change Interrupt Flag 2 |
.equ PCIF3 = 7 ; Pin Change Interrupt Flag 3 |
; ***** EEPROM *********************** |
; EEDR - EEPROM Data Register |
.equ EEDR0 = 0 ; EEPROM Data Register bit 0 |
.equ EEDR1 = 1 ; EEPROM Data Register bit 1 |
.equ EEDR2 = 2 ; EEPROM Data Register bit 2 |
.equ EEDR3 = 3 ; EEPROM Data Register bit 3 |
.equ EEDR4 = 4 ; EEPROM Data Register bit 4 |
.equ EEDR5 = 5 ; EEPROM Data Register bit 5 |
.equ EEDR6 = 6 ; EEPROM Data Register bit 6 |
.equ EEDR7 = 7 ; EEPROM Data Register bit 7 |
; EECR - EEPROM Control Register |
.equ EERE = 0 ; EEPROM Read Enable |
.equ EEWE = 1 ; EEPROM Write Enable |
.equ EEMWE = 2 ; EEPROM Master Write Enable |
.equ EERIE = 3 ; EEPROM Ready Interrupt Enable |
; ***** PORTA ************************ |
; PORTA - Port A Data Register |
.equ PORTA0 = 0 ; Port A Data Register bit 0 |
.equ PA0 = 0 ; For compatibility |
.equ PORTA1 = 1 ; Port A Data Register bit 1 |
.equ PA1 = 1 ; For compatibility |
.equ PORTA2 = 2 ; Port A Data Register bit 2 |
.equ PA2 = 2 ; For compatibility |
.equ PORTA3 = 3 ; Port A Data Register bit 3 |
.equ PA3 = 3 ; For compatibility |
.equ PORTA4 = 4 ; Port A Data Register bit 4 |
.equ PA4 = 4 ; For compatibility |
.equ PORTA5 = 5 ; Port A Data Register bit 5 |
.equ PA5 = 5 ; For compatibility |
.equ PORTA6 = 6 ; Port A Data Register bit 6 |
.equ PA6 = 6 ; For compatibility |
.equ PORTA7 = 7 ; Port A Data Register bit 7 |
.equ PA7 = 7 ; For compatibility |
; DDRA - Port A Data Direction Register |
.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0 |
.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1 |
.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2 |
.equ DDA3 = 3 ; Data Direction Register, Port A, bit 3 |
.equ DDA4 = 4 ; Data Direction Register, Port A, bit 4 |
.equ DDA5 = 5 ; Data Direction Register, Port A, bit 5 |
.equ DDA6 = 6 ; Data Direction Register, Port A, bit 6 |
.equ DDA7 = 7 ; Data Direction Register, Port A, bit 7 |
; PINA - Port A Input Pins |
.equ PINA0 = 0 ; Input Pins, Port A bit 0 |
.equ PINA1 = 1 ; Input Pins, Port A bit 1 |
.equ PINA2 = 2 ; Input Pins, Port A bit 2 |
.equ PINA3 = 3 ; Input Pins, Port A bit 3 |
.equ PINA4 = 4 ; Input Pins, Port A bit 4 |
.equ PINA5 = 5 ; Input Pins, Port A bit 5 |
.equ PINA6 = 6 ; Input Pins, Port A bit 6 |
.equ PINA7 = 7 ; Input Pins, Port A bit 7 |
; ***** PORTB ************************ |
; PORTB - Port B Data Register |
.equ PORTB0 = 0 ; Port B Data Register bit 0 |
.equ PB0 = 0 ; For compatibility |
.equ PORTB1 = 1 ; Port B Data Register bit 1 |
.equ PB1 = 1 ; For compatibility |
.equ PORTB2 = 2 ; Port B Data Register bit 2 |
.equ PB2 = 2 ; For compatibility |
.equ PORTB3 = 3 ; Port B Data Register bit 3 |
.equ PB3 = 3 ; For compatibility |
.equ PORTB4 = 4 ; Port B Data Register bit 4 |
.equ PB4 = 4 ; For compatibility |
.equ PORTB5 = 5 ; Port B Data Register bit 5 |
.equ PB5 = 5 ; For compatibility |
.equ PORTB6 = 6 ; Port B Data Register bit 6 |
.equ PB6 = 6 ; For compatibility |
.equ PORTB7 = 7 ; Port B Data Register bit 7 |
.equ PB7 = 7 ; For compatibility |
; DDRB - Port B Data Direction Register |
.equ DDB0 = 0 ; Port B Data Direction Register bit 0 |
.equ DDB1 = 1 ; Port B Data Direction Register bit 1 |
.equ DDB2 = 2 ; Port B Data Direction Register bit 2 |
.equ DDB3 = 3 ; Port B Data Direction Register bit 3 |
.equ DDB4 = 4 ; Port B Data Direction Register bit 4 |
.equ DDB5 = 5 ; Port B Data Direction Register bit 5 |
.equ DDB6 = 6 ; Port B Data Direction Register bit 6 |
.equ DDB7 = 7 ; Port B Data Direction Register bit 7 |
; PINB - Port B Input Pins |
.equ PINB0 = 0 ; Port B Input Pins bit 0 |
.equ PINB1 = 1 ; Port B Input Pins bit 1 |
.equ PINB2 = 2 ; Port B Input Pins bit 2 |
.equ PINB3 = 3 ; Port B Input Pins bit 3 |
.equ PINB4 = 4 ; Port B Input Pins bit 4 |
.equ PINB5 = 5 ; Port B Input Pins bit 5 |
.equ PINB6 = 6 ; Port B Input Pins bit 6 |
.equ PINB7 = 7 ; Port B Input Pins bit 7 |
; ***** PORTC ************************ |
; PORTC - Port C Data Register |
.equ PORTC0 = 0 ; Port C Data Register bit 0 |
.equ PC0 = 0 ; For compatibility |
.equ PORTC1 = 1 ; Port C Data Register bit 1 |
.equ PC1 = 1 ; For compatibility |
.equ PORTC2 = 2 ; Port C Data Register bit 2 |
.equ PC2 = 2 ; For compatibility |
.equ PORTC3 = 3 ; Port C Data Register bit 3 |
.equ PC3 = 3 ; For compatibility |
.equ PORTC4 = 4 ; Port C Data Register bit 4 |
.equ PC4 = 4 ; For compatibility |
.equ PORTC5 = 5 ; Port C Data Register bit 5 |
.equ PC5 = 5 ; For compatibility |
.equ PORTC6 = 6 ; Port C Data Register bit 6 |
.equ PC6 = 6 ; For compatibility |
.equ PORTC7 = 7 ; Port C Data Register bit 7 |
.equ PC7 = 7 ; For compatibility |
; DDRC - Port C Data Direction Register |
.equ DDC0 = 0 ; Port C Data Direction Register bit 0 |
.equ DDC1 = 1 ; Port C Data Direction Register bit 1 |
.equ DDC2 = 2 ; Port C Data Direction Register bit 2 |
.equ DDC3 = 3 ; Port C Data Direction Register bit 3 |
.equ DDC4 = 4 ; Port C Data Direction Register bit 4 |
.equ DDC5 = 5 ; Port C Data Direction Register bit 5 |
.equ DDC6 = 6 ; Port C Data Direction Register bit 6 |
.equ DDC7 = 7 ; Port C Data Direction Register bit 7 |
; PINC - Port C Input Pins |
.equ PINC0 = 0 ; Port C Input Pins bit 0 |
.equ PINC1 = 1 ; Port C Input Pins bit 1 |
.equ PINC2 = 2 ; Port C Input Pins bit 2 |
.equ PINC3 = 3 ; Port C Input Pins bit 3 |
.equ PINC4 = 4 ; Port C Input Pins bit 4 |
.equ PINC5 = 5 ; Port C Input Pins bit 5 |
.equ PINC6 = 6 ; Port C Input Pins bit 6 |
.equ PINC7 = 7 ; Port C Input Pins bit 7 |
; ***** PORTD ************************ |
; PORTD - Port D Data Register |
.equ PORTD0 = 0 ; Port D Data Register bit 0 |
.equ PD0 = 0 ; For compatibility |
.equ PORTD1 = 1 ; Port D Data Register bit 1 |
.equ PD1 = 1 ; For compatibility |
.equ PORTD2 = 2 ; Port D Data Register bit 2 |
.equ PD2 = 2 ; For compatibility |
.equ PORTD3 = 3 ; Port D Data Register bit 3 |
.equ PD3 = 3 ; For compatibility |
.equ PORTD4 = 4 ; Port D Data Register bit 4 |
.equ PD4 = 4 ; For compatibility |
.equ PORTD5 = 5 ; Port D Data Register bit 5 |
.equ PD5 = 5 ; For compatibility |
.equ PORTD6 = 6 ; Port D Data Register bit 6 |
.equ PD6 = 6 ; For compatibility |
.equ PORTD7 = 7 ; Port D Data Register bit 7 |
.equ PD7 = 7 ; For compatibility |
; DDRD - Port D Data Direction Register |
.equ DDD0 = 0 ; Port D Data Direction Register bit 0 |
.equ DDD1 = 1 ; Port D Data Direction Register bit 1 |
.equ DDD2 = 2 ; Port D Data Direction Register bit 2 |
.equ DDD3 = 3 ; Port D Data Direction Register bit 3 |
.equ DDD4 = 4 ; Port D Data Direction Register bit 4 |
.equ DDD5 = 5 ; Port D Data Direction Register bit 5 |
.equ DDD6 = 6 ; Port D Data Direction Register bit 6 |
.equ DDD7 = 7 ; Port D Data Direction Register bit 7 |
; PIND - Port D Input Pins |
.equ PIND0 = 0 ; Port D Input Pins bit 0 |
.equ PIND1 = 1 ; Port D Input Pins bit 1 |
.equ PIND2 = 2 ; Port D Input Pins bit 2 |
.equ PIND3 = 3 ; Port D Input Pins bit 3 |
.equ PIND4 = 4 ; Port D Input Pins bit 4 |
.equ PIND5 = 5 ; Port D Input Pins bit 5 |
.equ PIND6 = 6 ; Port D Input Pins bit 6 |
.equ PIND7 = 7 ; Port D Input Pins bit 7 |
; ***** PORTE ************************ |
; PORTE - Data Register, Port E |
.equ PORTE0 = 0 ; |
.equ PE0 = 0 ; For compatibility |
.equ PORTE1 = 1 ; |
.equ PE1 = 1 ; For compatibility |
.equ PORTE2 = 2 ; |
.equ PE2 = 2 ; For compatibility |
.equ PORTE3 = 3 ; |
.equ PE3 = 3 ; For compatibility |
.equ PORTE4 = 4 ; |
.equ PE4 = 4 ; For compatibility |
.equ PORTE5 = 5 ; |
.equ PE5 = 5 ; For compatibility |
.equ PORTE6 = 6 ; |
.equ PE6 = 6 ; For compatibility |
.equ PORTE7 = 7 ; |
.equ PE7 = 7 ; For compatibility |
; DDRE - Data Direction Register, Port E |
.equ DDE0 = 0 ; |
.equ DDE1 = 1 ; |
.equ DDE2 = 2 ; |
.equ DDE3 = 3 ; |
.equ DDE4 = 4 ; |
.equ DDE5 = 5 ; |
.equ DDE6 = 6 ; |
.equ DDE7 = 7 ; |
; PINE - Input Pins, Port E |
.equ PINE0 = 0 ; |
.equ PINE1 = 1 ; |
.equ PINE2 = 2 ; |
.equ PINE3 = 3 ; |
.equ PINE4 = 4 ; |
.equ PINE5 = 5 ; |
.equ PINE6 = 6 ; |
.equ PINE7 = 7 ; |
; ***** PORTF ************************ |
; PORTF - Data Register, Port F |
.equ PORTF0 = 0 ; |
.equ PF0 = 0 ; For compatibility |
.equ PORTF1 = 1 ; |
.equ PF1 = 1 ; For compatibility |
.equ PORTF2 = 2 ; |
.equ PF2 = 2 ; For compatibility |
.equ PORTF3 = 3 ; |
.equ PF3 = 3 ; For compatibility |
.equ PORTF4 = 4 ; |
.equ PF4 = 4 ; For compatibility |
.equ PORTF5 = 5 ; |
.equ PF5 = 5 ; For compatibility |
.equ PORTF6 = 6 ; |
.equ PF6 = 6 ; For compatibility |
.equ PORTF7 = 7 ; |
.equ PF7 = 7 ; For compatibility |
; DDRF - Data Direction Register, Port F |
.equ DDF0 = 0 ; |
.equ DDF1 = 1 ; |
.equ DDF2 = 2 ; |
.equ DDF3 = 3 ; |
.equ DDF4 = 4 ; |
.equ DDF5 = 5 ; |
.equ DDF6 = 6 ; |
.equ DDF7 = 7 ; |
; PINF - Input Pins, Port F |
.equ PINF0 = 0 ; |
.equ PINF1 = 1 ; |
.equ PINF2 = 2 ; |
.equ PINF3 = 3 ; |
.equ PINF4 = 4 ; |
.equ PINF5 = 5 ; |
.equ PINF6 = 6 ; |
.equ PINF7 = 7 ; |
; ***** PORTG ************************ |
; PORTG - Port G Data Register |
.equ PORTG0 = 0 ; |
.equ PG0 = 0 ; For compatibility |
.equ PORTG1 = 1 ; |
.equ PG1 = 1 ; For compatibility |
.equ PORTG2 = 2 ; |
.equ PG2 = 2 ; For compatibility |
.equ PORTG3 = 3 ; |
.equ PG3 = 3 ; For compatibility |
.equ PORTG4 = 4 ; |
.equ PG4 = 4 ; For compatibility |
; DDRG - Port G Data Direction Register |
.equ DDG0 = 0 ; |
.equ DDG1 = 1 ; |
.equ DDG2 = 2 ; |
.equ DDG3 = 3 ; |
.equ DDG4 = 4 ; |
; PING - Port G Input Pins |
.equ PING0 = 0 ; |
.equ PING1 = 1 ; |
.equ PING2 = 2 ; |
.equ PING3 = 3 ; |
.equ PING4 = 4 ; |
.equ PING5 = 5 ; |
; ***** TIMER_COUNTER_0 ************** |
; TCCR0A - Timer/Counter0 Control Register |
.equ CS00 = 0 ; Clock Select 1 |
.equ CS01 = 1 ; Clock Select 1 |
.equ CS02 = 2 ; Clock Select 2 |
.equ WGM01 = 3 ; Waveform Generation Mode 1 |
.equ COM0A0 = 4 ; Compare match Output Mode 0 |
.equ COM0A1 = 5 ; Compare Match Output Mode 1 |
.equ WGM00 = 6 ; Waveform Generation Mode 0 |
.equ FOC0A = 7 ; Force Output Compare |
; TCNT0 - Timer/Counter0 |
.equ TCNT0_0 = 0 ; |
.equ TCNT0_1 = 1 ; |
.equ TCNT0_2 = 2 ; |
.equ TCNT0_3 = 3 ; |
.equ TCNT0_4 = 4 ; |
.equ TCNT0_5 = 5 ; |
.equ TCNT0_6 = 6 ; |
.equ TCNT0_7 = 7 ; |
; OCR0A - Timer/Counter0 Output Compare Register |
.equ OCR0A0 = 0 ; |
.equ OCR0A1 = 1 ; |
.equ OCR0A2 = 2 ; |
.equ OCR0A3 = 3 ; |
.equ OCR0A4 = 4 ; |
.equ OCR0A5 = 5 ; |
.equ OCR0A6 = 6 ; |
.equ OCR0A7 = 7 ; |
; TIMSK0 - Timer/Counter0 Interrupt Mask Register |
.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable |
.equ OCIE0A = 1 ; Timer/Counter0 Output Compare Match Interrupt Enable |
; TIFR0 - Timer/Counter0 Interrupt Flag register |
.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag |
.equ OCF0A = 1 ; Timer/Counter0 Output Compare Flag 0 |
; GTCCR - General Timer/Control Register |
.equ PSR310 = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0 |
.equ PSR10 = PSR310 ; For compatibility |
.equ PSR0 = PSR310 ; For compatibility |
.equ PSR1 = PSR310 ; For compatibility |
.equ PSR3 = PSR310 ; For compatibility |
.equ TSM = 7 ; Timer/Counter Synchronization Mode |
; ***** TIMER_COUNTER_1 ************** |
; TIMSK1 - Timer/Counter1 Interrupt Mask Register |
.equ TOIE1 = 0 ; Timer/Counter1 Overflow Interrupt Enable |
.equ OCIE1A = 1 ; Timer/Counter1 Output Compare A Match Interrupt Enable |
.equ OCIE1B = 2 ; Timer/Counter1 Output Compare B Match Interrupt Enable |
.equ ICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable |
; TIFR1 - Timer/Counter1 Interrupt Flag register |
.equ TOV1 = 0 ; Timer/Counter1 Overflow Flag |
.equ OCF1A = 1 ; Output Compare Flag 1A |
.equ OCF1B = 2 ; Output Compare Flag 1B |
.equ ICF1 = 5 ; Input Capture Flag 1 |
; TCCR1A - Timer/Counter1 Control Register A |
.equ WGM10 = 0 ; Waveform Generation Mode |
.equ WGM11 = 1 ; Waveform Generation Mode |
.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0 |
.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1 |
.equ COM1A0 = 6 ; Compare Output Mode 1A, bit 0 |
.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1 |
; TCCR1B - Timer/Counter1 Control Register B |
.equ CS10 = 0 ; Prescaler source of Timer/Counter 1 |
.equ CS11 = 1 ; Prescaler source of Timer/Counter 1 |
.equ CS12 = 2 ; Prescaler source of Timer/Counter 1 |
.equ WGM12 = 3 ; Waveform Generation Mode |
.equ WGM13 = 4 ; Waveform Generation Mode |
.equ ICES1 = 6 ; Input Capture 1 Edge Select |
.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler |
; TCCR1C - Timer/Counter 1 Control Register C |
.equ FOC1B = 6 ; Force Output Compare 1B |
.equ FOC1A = 7 ; Force Output Compare 1A |
; ***** TIMER_COUNTER_2 ************** |
; TIMSK2 - Timer/Counter2 Interrupt Mask register |
.equ TOIE2 = 0 ; Timer/Counter2 Overflow Interrupt Enable |
.equ OCIE2A = 1 ; Timer/Counter2 Output Compare Match Interrupt Enable |
; TIFR2 - Timer/Counter2 Interrupt Flag Register |
.equ TOV2 = 0 ; Timer/Counter2 Overflow Flag |
.equ OCF2A = 1 ; Timer/Counter2 Output Compare Flag 2 |
; TCCR2A - Timer/Counter2 Control Register |
.equ CS20 = 0 ; Clock Select bit 0 |
.equ CS21 = 1 ; Clock Select bit 1 |
.equ CS22 = 2 ; Clock Select bit 2 |
.equ WGM21 = 3 ; Waveform Generation Mode |
.equ COM2A0 = 4 ; Compare Output Mode bit 0 |
.equ COM2A1 = 5 ; Compare Output Mode bit 1 |
.equ WGM20 = 6 ; Waveform Generation Mode |
.equ FOC2A = 7 ; Force Output Compare A |
; TCNT2 - Timer/Counter2 |
.equ TCNT2_0 = 0 ; Timer/Counter 2 bit 0 |
.equ TCNT2_1 = 1 ; Timer/Counter 2 bit 1 |
.equ TCNT2_2 = 2 ; Timer/Counter 2 bit 2 |
.equ TCNT2_3 = 3 ; Timer/Counter 2 bit 3 |
.equ TCNT2_4 = 4 ; Timer/Counter 2 bit 4 |
.equ TCNT2_5 = 5 ; Timer/Counter 2 bit 5 |
.equ TCNT2_6 = 6 ; Timer/Counter 2 bit 6 |
.equ TCNT2_7 = 7 ; Timer/Counter 2 bit 7 |
; OCR2A - Timer/Counter2 Output Compare Register |
.equ OCR2A0 = 0 ; Timer/Counter2 Output Compare Register Bit 0 |
.equ OCR2A1 = 1 ; Timer/Counter2 Output Compare Register Bit 1 |
.equ OCR2A2 = 2 ; Timer/Counter2 Output Compare Register Bit 2 |
.equ OCR2A3 = 3 ; Timer/Counter2 Output Compare Register Bit 3 |
.equ OCR2A4 = 4 ; Timer/Counter2 Output Compare Register Bit 4 |
.equ OCR2A5 = 5 ; Timer/Counter2 Output Compare Register Bit 5 |
.equ OCR2A6 = 6 ; Timer/Counter2 Output Compare Register Bit 6 |
.equ OCR2A7 = 7 ; Timer/Counter2 Output Compare Register Bit 7 |
; GTCCR - General Timer/Counter Control Register |
.equ PSR2 = 1 ; Prescaler Reset Timer/Counter2 |
; ASSR - Asynchronous Status Register |
.equ TCR2UB = 0 ; TCR2UB: Timer/Counter Control Register2 Update Busy |
.equ OCR2UB = 1 ; Output Compare Register2 Update Busy |
.equ TCN2UB = 2 ; TCN2UB: Timer/Counter2 Update Busy |
.equ AS2 = 3 ; AS2: Asynchronous Timer/Counter2 |
.equ EXCLK = 4 ; Enable External Clock Interrupt |
; ***** WATCHDOG ********************* |
; WDTCR - Watchdog Timer Control Register |
.equ WDTCSR = WDTCR ; For compatibility |
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 |
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 |
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 |
.equ WDE = 3 ; Watch Dog Enable |
.equ WDCE = 4 ; Watchdog Change Enable |
.equ WDTOE = WDCE ; For compatibility |
; ***** BOOT_LOAD ******************** |
; SPMCSR - Store Program Memory Control Register |
.equ SPMCR = SPMCSR ; For compatibility |
.equ SPMEN = 0 ; Store Program Memory Enable |
.equ PGERS = 1 ; Page Erase |
.equ PGWRT = 2 ; Page Write |
.equ BLBSET = 3 ; Boot Lock Bit Set |
.equ RWWSRE = 4 ; Read While Write section read enable |
.equ ASRE = RWWSRE ; For compatibility |
.equ RWWSB = 6 ; Read While Write Section Busy |
.equ ASB = RWWSB ; For compatibility |
.equ SPMIE = 7 ; SPM Interrupt Enable |
; ***** LOCKSBITS ******************************************************** |
.equ LB1 = 0 ; Lock bit |
.equ LB2 = 1 ; Lock bit |
.equ BLB01 = 2 ; Boot Lock bit |
.equ BLB02 = 3 ; Boot Lock bit |
.equ BLB11 = 4 ; Boot lock bit |
.equ BLB12 = 5 ; Boot lock bit |
; ***** FUSES ************************************************************ |
; LOW fuse bits |
.equ CKSEL0 = 0 ; Select Clock Source |
.equ CKSEL1 = 1 ; Select Clock Source |
.equ CKSEL2 = 2 ; Select Clock Source |
.equ CKSEL3 = 3 ; Select Clock Source |
.equ SUT0 = 4 ; Select start-up time |
.equ SUT1 = 5 ; Select start-up time |
.equ CKOUT = 6 ; Oscillator options |
.equ CLKDIV8 = 7 ; Divide clock by 8 |
; HIGH fuse bits |
.equ BOOTRST = 0 ; Select Reset Vector |
.equ BOOTSZ0 = 1 ; Select Boot Size |
.equ BOOTSZ1 = 2 ; Select Boot Size |
.equ EESAVE = 3 ; EEPROM memory is preserved through chip erase |
.equ WDTON = 4 ; Watchdog timer always on |
.equ SPIEN = 5 ; Enable Serial programming and Data Downloading |
.equ JTAGEN = 6 ; Enable JTAG |
.equ OCDEN = 7 ; Enable OCD |
; EXTENDED fuse bits |
.equ RSTDISBL = 0 ; External Reset Disable |
.equ BODLEVEL0 = 1 ; Brown-out Detector trigger level |
.equ BODLEVEL1 = 2 ; Brown-out Detector trigger level |
; ***** CPU REGISTER DEFINITIONS ***************************************** |
.def XH = r27 |
.def XL = r26 |
.def YH = r29 |
.def YL = r28 |
.def ZH = r31 |
.def ZL = r30 |
; ***** DATA MEMORY DECLARATIONS ***************************************** |
.equ FLASHEND = 0x7fff ; Note: Word address |
.equ IOEND = 0x00ff |
.equ SRAM_START = 0x0100 |
.equ SRAM_SIZE = 4096 |
.equ RAMEND = 0x10ff |
.equ XRAMEND = 0x0000 |
.equ E2END = 0x07ff |
.equ EEPROMEND = 0x07ff |
.equ EEADRBITS = 11 |
#pragma AVRPART MEMORY PROG_FLASH 65536 |
#pragma AVRPART MEMORY EEPROM 2048 |
#pragma AVRPART MEMORY INT_SRAM SIZE 4096 |
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x100 |
; ***** BOOTLOADER DECLARATIONS ****************************************** |
.equ NRWW_START_ADDR = 0x7000 |
.equ NRWW_STOP_ADDR = 0x7fff |
.equ RWW_START_ADDR = 0x0 |
.equ RWW_STOP_ADDR = 0x6fff |
.equ PAGESIZE = 128 |
.equ FIRSTBOOTSTART = 0x7e00 |
.equ SECONDBOOTSTART = 0x7c00 |
.equ THIRDBOOTSTART = 0x7800 |
.equ FOURTHBOOTSTART = 0x7000 |
.equ SMALLBOOTSTART = FIRSTBOOTSTART |
.equ LARGEBOOTSTART = FOURTHBOOTSTART |
; ***** INTERRUPT VECTORS ************************************************ |
.equ INT0addr = 0x0002 ; External Interrupt Request 0 |
.equ PCI0addr = 0x0004 ; Pin Change Interrupt Request 0 |
.equ PCI1addr = 0x0006 ; Pin Change Interrupt Request 1 |
.equ OC2addr = 0x0008 ; Timer/Counter2 Compare Match |
.equ OVF2addr = 0x000a ; Timer/Counter2 Overflow |
.equ ICP1addr = 0x000c ; Timer/Counter1 Capture Event |
.equ OC1Aaddr = 0x000e ; Timer/Counter1 Compare Match A |
.equ OC1Baddr = 0x0010 ; Timer/Counter Compare Match B |
.equ OVF1addr = 0x0012 ; Timer/Counter1 Overflow |
.equ OC0addr = 0x0014 ; Timer/Counter0 Compare Match |
.equ OVF0addr = 0x0016 ; Timer/Counter0 Overflow |
.equ SPIaddr = 0x0018 ; SPI Serial Transfer Complete |
.equ URXC0addr = 0x001a ; USART0, Rx Complete |
.equ URXCaddr = 0x001a ; For compatibility |
.equ UDRE0addr = 0x001c ; USART0 Data register Empty |
.equ UDREaddr = 0x001c ; For compatibility |
.equ UTXC0addr = 0x001e ; USART0, Tx Complete |
.equ UTXCaddr = 0x001e ; For compatibility |
.equ USI_STARTaddr = 0x0020 ; USI Start Condition |
.equ USI_OVFaddr = 0x0022 ; USI Overflow |
.equ ACIaddr = 0x0024 ; Analog Comparator |
.equ ADCCaddr = 0x0026 ; ADC Conversion Complete |
.equ ERDYaddr = 0x0028 ; EEPROM Ready |
.equ SPMRaddr = 0x002a ; Store Program Memory Read |
.equ LCDSFaddr = 0x002c ; LCD Start of Frame |
.equ INT_VECTORS_SIZE = 46 ; size in words |
#endif /* _M649DEF_INC_ */ |
; ***** END OF FILE ****************************************************** |
/contrib/toolchain/avra/includes/m64def.inc |
---|
0,0 → 1,1178 |
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** |
;***** Created: 2005-01-11 10:31 ******* Source: ATmega64.xml ************ |
;************************************************************************* |
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y |
;* |
;* Number : AVR000 |
;* File Name : "m64def.inc" |
;* Title : Register/Bit Definitions for the ATmega64 |
;* Date : 2005-01-11 |
;* Version : 2.14 |
;* Support E-mail : avr@atmel.com |
;* Target MCU : ATmega64 |
;* |
;* DESCRIPTION |
;* When including this file in the assembly program file, all I/O register |
;* names and I/O register bit names appearing in the data book can be used. |
;* In addition, the six registers forming the three data pointers X, Y and |
;* Z have been assigned names XL - ZH. Highest RAM address for Internal |
;* SRAM is also defined |
;* |
;* The Register names are represented by their hexadecimal address. |
;* |
;* The Register Bit names are represented by their bit number (0-7). |
;* |
;* Please observe the difference in using the bit names with instructions |
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" |
;* (skip if bit in register set/cleared). The following example illustrates |
;* this: |
;* |
;* in r16,PORTB ;read PORTB latch |
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) |
;* out PORTB,r16 ;output to PORTB |
;* |
;* in r16,TIFR ;read the Timer Interrupt Flag Register |
;* sbrc r16,TOV0 ;test the overflow flag (use bit#) |
;* rjmp TOV0_is_set ;jump if set |
;* ... ;otherwise do something else |
;************************************************************************* |
#ifndef _M64DEF_INC_ |
#define _M64DEF_INC_ |
#pragma partinc 0 |
; ***** SPECIFY DEVICE *************************************************** |
.device ATmega64 |
#pragma AVRPART ADMIN PART_NAME ATmega64 |
.equ SIGNATURE_000 = 0x1e |
.equ SIGNATURE_001 = 0x96 |
.equ SIGNATURE_002 = 0x02 |
#pragma AVRPART CORE CORE_VERSION V2E |
; ***** I/O REGISTER DEFINITIONS ***************************************** |
; NOTE: |
; Definitions marked "MEMORY MAPPED"are extended I/O ports |
; and cannot be used with IN/OUT instructions |
.equ UCSR1C = 0x9d ; MEMORY MAPPED |
.equ UDR1 = 0x9c ; MEMORY MAPPED |
.equ UCSR1A = 0x9b ; MEMORY MAPPED |
.equ UCSR1B = 0x9a ; MEMORY MAPPED |
.equ UBRR1L = 0x99 ; MEMORY MAPPED |
.equ UBRR1H = 0x98 ; MEMORY MAPPED |
.equ UCSR0C = 0x95 ; MEMORY MAPPED |
.equ UBRR0H = 0x90 ; MEMORY MAPPED |
.equ ADCSRB = 0x8e ; MEMORY MAPPED |
.equ TCCR3C = 0x8c ; MEMORY MAPPED |
.equ TCCR3A = 0x8b ; MEMORY MAPPED |
.equ TCCR3B = 0x8a ; MEMORY MAPPED |
.equ TCNT3H = 0x89 ; MEMORY MAPPED |
.equ TCNT3L = 0x88 ; MEMORY MAPPED |
.equ OCR3AH = 0x87 ; MEMORY MAPPED |
.equ OCR3AL = 0x86 ; MEMORY MAPPED |
.equ OCR3BH = 0x85 ; MEMORY MAPPED |
.equ OCR3BL = 0x84 ; MEMORY MAPPED |
.equ OCR3CH = 0x83 ; MEMORY MAPPED |
.equ OCR3CL = 0x82 ; MEMORY MAPPED |
.equ ICR3H = 0x81 ; MEMORY MAPPED |
.equ ICR3L = 0x80 ; MEMORY MAPPED |
.equ ETIMSK = 0x7d ; MEMORY MAPPED |
.equ ETIFR = 0x7c ; MEMORY MAPPED |
.equ TCCR1C = 0x7a ; MEMORY MAPPED |
.equ OCR1CH = 0x79 ; MEMORY MAPPED |
.equ OCR1CL = 0x78 ; MEMORY MAPPED |
.equ TWCR = 0x74 ; MEMORY MAPPED |
.equ TWDR = 0x73 ; MEMORY MAPPED |
.equ TWAR = 0x72 ; MEMORY MAPPED |
.equ TWSR = 0x71 ; MEMORY MAPPED |
.equ TWBR = 0x70 ; MEMORY MAPPED |
.equ OSCCAL = 0x6f ; MEMORY MAPPED |
.equ XMCRA = 0x6d ; MEMORY MAPPED |
.equ XMCRB = 0x6c ; MEMORY MAPPED |
.equ EICRA = 0x6a ; MEMORY MAPPED |
.equ SPMCSR = 0x68 ; MEMORY MAPPED |
.equ PORTG = 0x65 ; MEMORY MAPPED |
.equ DDRG = 0x64 ; MEMORY MAPPED |
.equ PING = 0x63 ; MEMORY MAPPED |
.equ PORTF = 0x62 ; MEMORY MAPPED |
.equ DDRF = 0x61 ; MEMORY MAPPED |
.equ SREG = 0x3f |
.equ SPH = 0x3e |
.equ SPL = 0x3d |
.equ XDIV = 0x3c |
.equ EICRB = 0x3a |
.equ EIMSK = 0x39 |
.equ EIFR = 0x38 |
.equ TIMSK = 0x37 |
.equ TIFR = 0x36 |
.equ MCUCR = 0x35 |
.equ MCUCSR = 0x34 |
.equ TCCR0 = 0x33 |
.equ TCNT0 = 0x32 |
.equ OCR0 = 0x31 |
.equ ASSR = 0x30 |
.equ TCCR1A = 0x2f |
.equ TCCR1B = 0x2e |
.equ TCNT1H = 0x2d |
.equ TCNT1L = 0x2c |
.equ OCR1AH = 0x2b |
.equ OCR1AL = 0x2a |
.equ OCR1BH = 0x29 |
.equ OCR1BL = 0x28 |
.equ ICR1H = 0x27 |
.equ ICR1L = 0x26 |
.equ TCCR2 = 0x25 |
.equ TCNT2 = 0x24 |
.equ OCR2 = 0x23 |
.equ OCDR = 0x22 |
.equ WDTCR = 0x21 |
.equ SFIOR = 0x20 |
.equ EEARH = 0x1f |
.equ EEARL = 0x1e |
.equ EEDR = 0x1d |
.equ EECR = 0x1c |
.equ PORTA = 0x1b |
.equ DDRA = 0x1a |
.equ PINA = 0x19 |
.equ PORTB = 0x18 |
.equ DDRB = 0x17 |
.equ PINB = 0x16 |
.equ PORTC = 0x15 |
.equ DDRC = 0x14 |
.equ PINC = 0x13 |
.equ PORTD = 0x12 |
.equ DDRD = 0x11 |
.equ PIND = 0x10 |
.equ SPDR = 0x0f |
.equ SPSR = 0x0e |
.equ SPCR = 0x0d |
.equ UDR0 = 0x0c |
.equ UCSR0A = 0x0b |
.equ UCSR0B = 0x0a |
.equ UBRR0L = 0x09 |
.equ ACSR = 0x08 |
.equ ADMUX = 0x07 |
.equ ADCSRA = 0x06 |
.equ ADCH = 0x05 |
.equ ADCL = 0x04 |
.equ PORTE = 0x03 |
.equ DDRE = 0x02 |
.equ PINE = 0x01 |
.equ PINF = 0x00 |
; ***** BIT DEFINITIONS ************************************************** |
; ***** ANALOG_COMPARATOR ************ |
; SFIOR - Special Function IO Register |
.equ ACME = 3 ; Analog Comparator Multiplexer Enable |
; ACSR - Analog Comparator Control And Status Register |
.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 |
.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 |
.equ ACIC = 2 ; Analog Comparator Input Capture Enable |
.equ ACIE = 3 ; Analog Comparator Interrupt Enable |
.equ ACI = 4 ; Analog Comparator Interrupt Flag |
.equ ACO = 5 ; Analog Compare Output |
.equ ACBG = 6 ; Analog Comparator Bandgap Select |
.equ ACD = 7 ; Analog Comparator Disable |
; ***** AD_CONVERTER ***************** |
; ADMUX - The ADC multiplexer Selection Register |
.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits |
.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits |
.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits |
.equ MUX3 = 3 ; Analog Channel and Gain Selection Bits |
.equ MUX4 = 4 ; Analog Channel and Gain Selection Bits |
.equ ADLAR = 5 ; Left Adjust Result |
.equ REFS0 = 6 ; Reference Selection Bit 0 |
.equ REFS1 = 7 ; Reference Selection Bit 1 |
; ADCSRA - The ADC Control and Status register A |
.equ ADCSR = ADCSRA ; For compatibility |
.equ ADPS0 = 0 ; ADC Prescaler Select Bits |
.equ ADPS1 = 1 ; ADC Prescaler Select Bits |
.equ ADPS2 = 2 ; ADC Prescaler Select Bits |
.equ ADIE = 3 ; ADC Interrupt Enable |
.equ ADIF = 4 ; ADC Interrupt Flag |
.equ ADATE = 5 ; ADC Auto Trigger Enable |
.equ ADFR = ADATE ; For compatibility |
.equ ADSC = 6 ; ADC Start Conversion |
.equ ADEN = 7 ; ADC Enable |
; ADCH - ADC Data Register High Byte |
.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0 |
.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1 |
.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2 |
.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3 |
.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4 |
.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5 |
.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6 |
.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7 |
; ADCL - ADC Data Register Low Byte |
.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0 |
.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1 |
.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2 |
.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3 |
.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4 |
.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5 |
.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6 |
.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7 |
; ADCSRB - The ADC Control and Status register B |
.equ ADTS0 = 0 ; ADC Auto Trigger Source bit 0 |
.equ ADTS1 = 1 ; ADC Auto Trigger Source bit 1 |
.equ ADTS2 = 2 ; ADC Auto Trigger Source bit 2 |
; ***** SPI ************************** |
; SPDR - SPI Data Register |
.equ SPDR0 = 0 ; SPI Data Register bit 0 |
.equ SPDR1 = 1 ; SPI Data Register bit 1 |
.equ SPDR2 = 2 ; SPI Data Register bit 2 |
.equ SPDR3 = 3 ; SPI Data Register bit 3 |
.equ SPDR4 = 4 ; SPI Data Register bit 4 |
.equ SPDR5 = 5 ; SPI Data Register bit 5 |
.equ SPDR6 = 6 ; SPI Data Register bit 6 |
.equ SPDR7 = 7 ; SPI Data Register bit 7 |
; SPSR - SPI Status Register |
.equ SPI2X = 0 ; Double SPI Speed Bit |
.equ WCOL = 6 ; Write Collision Flag |
.equ SPIF = 7 ; SPI Interrupt Flag |
; SPCR - SPI Control Register |
.equ SPR0 = 0 ; SPI Clock Rate Select 0 |
.equ SPR1 = 1 ; SPI Clock Rate Select 1 |
.equ CPHA = 2 ; Clock Phase |
.equ CPOL = 3 ; Clock polarity |
.equ MSTR = 4 ; Master/Slave Select |
.equ DORD = 5 ; Data Order |
.equ SPE = 6 ; SPI Enable |
.equ SPIE = 7 ; SPI Interrupt Enable |
; ***** TWI ************************** |
; TWBR - TWI Bit Rate register |
.equ I2BR = TWBR ; For compatibility |
.equ TWBR0 = 0 ; |
.equ TWBR1 = 1 ; |
.equ TWBR2 = 2 ; |
.equ TWBR3 = 3 ; |
.equ TWBR4 = 4 ; |
.equ TWBR5 = 5 ; |
.equ TWBR6 = 6 ; |
.equ TWBR7 = 7 ; |
; TWCR - TWI Control Register |
.equ I2CR = TWCR ; For compatibility |
.equ TWIE = 0 ; TWI Interrupt Enable |
.equ I2IE = TWIE ; For compatibility |
.equ TWEN = 2 ; TWI Enable Bit |
.equ I2EN = TWEN ; For compatibility |
.equ ENI2C = TWEN ; For compatibility |
.equ TWWC = 3 ; TWI Write Collition Flag |
.equ I2WC = TWWC ; For compatibility |
.equ TWSTO = 4 ; TWI Stop Condition Bit |
.equ I2STO = TWSTO ; For compatibility |
.equ TWSTA = 5 ; TWI Start Condition Bit |
.equ I2STA = TWSTA ; For compatibility |
.equ TWEA = 6 ; TWI Enable Acknowledge Bit |
.equ I2EA = TWEA ; For compatibility |
.equ TWINT = 7 ; TWI Interrupt Flag |
.equ I2INT = TWINT ; For compatibility |
; TWSR - TWI Status Register |
.equ I2SR = TWSR ; For compatibility |
.equ TWPS0 = 0 ; TWI Prescaler |
.equ TWS0 = TWPS0 ; For compatibility |
.equ I2GCE = TWPS0 ; For compatibility |
.equ TWPS1 = 1 ; TWI Prescaler |
.equ TWS1 = TWPS1 ; For compatibility |
.equ TWS3 = 3 ; TWI Status |
.equ I2S3 = TWS3 ; For compatibility |
.equ TWS4 = 4 ; TWI Status |
.equ I2S4 = TWS4 ; For compatibility |
.equ TWS5 = 5 ; TWI Status |
.equ I2S5 = TWS5 ; For compatibility |
.equ TWS6 = 6 ; TWI Status |
.equ I2S6 = TWS6 ; For compatibility |
.equ TWS7 = 7 ; TWI Status |
.equ I2S7 = TWS7 ; For compatibility |
; TWDR - TWI Data register |
.equ I2DR = TWDR ; For compatibility |
.equ TWD0 = 0 ; TWI Data Register Bit 0 |
.equ TWD1 = 1 ; TWI Data Register Bit 1 |
.equ TWD2 = 2 ; TWI Data Register Bit 2 |
.equ TWD3 = 3 ; TWI Data Register Bit 3 |
.equ TWD4 = 4 ; TWI Data Register Bit 4 |
.equ TWD5 = 5 ; TWI Data Register Bit 5 |
.equ TWD6 = 6 ; TWI Data Register Bit 6 |
.equ TWD7 = 7 ; TWI Data Register Bit 7 |
; TWAR - TWI (Slave) Address register |
.equ I2AR = TWAR ; For compatibility |
.equ TWGCE = 0 ; TWI General Call Recognition Enable Bit |
.equ TWA0 = 1 ; TWI (Slave) Address register Bit 0 |
.equ TWA1 = 2 ; TWI (Slave) Address register Bit 1 |
.equ TWA2 = 3 ; TWI (Slave) Address register Bit 2 |
.equ TWA3 = 4 ; TWI (Slave) Address register Bit 3 |
.equ TWA4 = 5 ; TWI (Slave) Address register Bit 4 |
.equ TWA5 = 6 ; TWI (Slave) Address register Bit 5 |
.equ TWA6 = 7 ; TWI (Slave) Address register Bit 6 |
; ***** USART0 *********************** |
; UDR0 - USART I/O Data Register |
.equ UDR00 = 0 ; USART I/O Data Register bit 0 |
.equ UDR01 = 1 ; USART I/O Data Register bit 1 |
.equ UDR02 = 2 ; USART I/O Data Register bit 2 |
.equ UDR03 = 3 ; USART I/O Data Register bit 3 |
.equ UDR04 = 4 ; USART I/O Data Register bit 4 |
.equ UDR05 = 5 ; USART I/O Data Register bit 5 |
.equ UDR06 = 6 ; USART I/O Data Register bit 6 |
.equ UDR07 = 7 ; USART I/O Data Register bit 7 |
; UCSR0A - USART Control and Status Register A |
.equ MPCM0 = 0 ; Multi-processor Communication Mode |
.equ U2X0 = 1 ; Double the USART transmission speed |
.equ UPE0 = 2 ; Parity Error |
.equ DOR0 = 3 ; Data overRun |
.equ FE0 = 4 ; Framing Error |
.equ UDRE0 = 5 ; USART Data Register Empty |
.equ TXC0 = 6 ; USART Transmitt Complete |
.equ RXC0 = 7 ; USART Receive Complete |
; UCSR0B - USART Control and Status Register B |
.equ TXB80 = 0 ; Transmit Data Bit 8 |
.equ RXB80 = 1 ; Receive Data Bit 8 |
.equ UCSZ02 = 2 ; Character Size |
.equ UCSZ2 = UCSZ02 ; For compatibility |
.equ TXEN0 = 3 ; Transmitter Enable |
.equ RXEN0 = 4 ; Receiver Enable |
.equ UDRIE0 = 5 ; USART Data register Empty Interrupt Enable |
.equ TXCIE0 = 6 ; TX Complete Interrupt Enable |
.equ RXCIE0 = 7 ; RX Complete Interrupt Enable |
; UCSR0C - USART Control and Status Register C |
.equ UCPOL0 = 0 ; Clock Polarity |
.equ UCSZ00 = 1 ; Character Size |
.equ UCSZ01 = 2 ; Character Size |
.equ USBS0 = 3 ; Stop Bit Select |
.equ UPM00 = 4 ; Parity Mode Bit 0 |
.equ UPM01 = 5 ; Parity Mode Bit 1 |
.equ UMSEL0 = 6 ; USART Mode Select |
; ***** USART1 *********************** |
; UDR1 - USART I/O Data Register |
.equ UDR10 = 0 ; USART I/O Data Register bit 0 |
.equ UDR11 = 1 ; USART I/O Data Register bit 1 |
.equ UDR12 = 2 ; USART I/O Data Register bit 2 |
.equ UDR13 = 3 ; USART I/O Data Register bit 3 |
.equ UDR14 = 4 ; USART I/O Data Register bit 4 |
.equ UDR15 = 5 ; USART I/O Data Register bit 5 |
.equ UDR16 = 6 ; USART I/O Data Register bit 6 |
.equ UDR17 = 7 ; USART I/O Data Register bit 7 |
; UCSR1A - USART Control and Status Register A |
.equ MPCM1 = 0 ; Multi-processor Communication Mode |
.equ U2X1 = 1 ; Double the USART transmission speed |
.equ UPE1 = 2 ; Parity Error |
.equ DOR1 = 3 ; Data overRun |
.equ FE1 = 4 ; Framing Error |
.equ UDRE1 = 5 ; USART Data Register Empty |
.equ TXC1 = 6 ; USART Transmitt Complete |
.equ RXC1 = 7 ; USART Receive Complete |
; UCSR1B - USART Control and Status Register B |
.equ TXB81 = 0 ; Transmit Data Bit 8 |
.equ RXB81 = 1 ; Receive Data Bit 8 |
.equ UCSZ12 = 2 ; Character Size |
.equ TXEN1 = 3 ; Transmitter Enable |
.equ RXEN1 = 4 ; Receiver Enable |
.equ UDRIE1 = 5 ; USART Data register Empty Interrupt Enable |
.equ TXCIE1 = 6 ; TX Complete Interrupt Enable |
.equ RXCIE1 = 7 ; RX Complete Interrupt Enable |
; UCSR1C - USART Control and Status Register C |
.equ UCPOL1 = 0 ; Clock Polarity |
.equ UCSZ10 = 1 ; Character Size |
.equ UCSZ11 = 2 ; Character Size |
.equ USBS1 = 3 ; Stop Bit Select |
.equ UPM10 = 4 ; Parity Mode Bit 0 |
.equ UPM11 = 5 ; Parity Mode Bit 1 |
.equ UMSEL1 = 6 ; USART Mode Select |
; ***** CPU ************************** |
; SREG - Status Register |
.equ SREG_C = 0 ; Carry Flag |
.equ SREG_Z = 1 ; Zero Flag |
.equ SREG_N = 2 ; Negative Flag |
.equ SREG_V = 3 ; Two's Complement Overflow Flag |
.equ SREG_S = 4 ; Sign Bit |
.equ SREG_H = 5 ; Half Carry Flag |
.equ SREG_T = 6 ; Bit Copy Storage |
.equ SREG_I = 7 ; Global Interrupt Enable |
; MCUCR - MCU Control Register |
.equ IVCE = 0 ; Interrupt Vector Change Enable |
.equ IVSEL = 1 ; Interrupt Vector Select |
.equ SM2 = 2 ; Sleep Mode Select |
.equ SM0 = 3 ; Sleep Mode Select |
.equ SM1 = 4 ; Sleep Mode Select |
.equ SE = 5 ; Sleep Enable |
.equ SRW10 = 6 ; External SRAM Wait State Select |
.equ SRE = 7 ; External SRAM Enable |
; XMCRA - External Memory Control Register A |
.equ SRW11 = 1 ; Wait state select bit upper page |
.equ SRW00 = 2 ; Wait state select bit lower page |
.equ SRW01 = 3 ; Wait state select bit lower page |
.equ SRL0 = 4 ; Wait state page limit |
.equ SRL1 = 5 ; Wait state page limit |
.equ SRL2 = 6 ; Wait state page limit |
; XMCRB - External Memory Control Register B |
.equ XMM0 = 0 ; External Memory High Mask |
.equ XMM1 = 1 ; External Memory High Mask |
.equ XMM2 = 2 ; External Memory High Mask |
.equ XMBK = 7 ; External Memory Bus Keeper Enable |
; OSCCAL - Oscillator Calibration Value |
.equ CAL0 = 0 ; Oscillator Calibration Value |
.equ CAL1 = 1 ; Oscillator Calibration Value |
.equ CAL2 = 2 ; Oscillator Calibration Value |
.equ CAL3 = 3 ; Oscillator Calibration Value |
.equ CAL4 = 4 ; Oscillator Calibration Value |
.equ CAL5 = 5 ; Oscillator Calibration Value |
.equ CAL6 = 6 ; Oscillator Calibration Value |
.equ CAL7 = 7 ; Oscillator Calibration Value |
; XDIV - XTAL Divide Control Register |
.equ XDIV0 = 0 ; XTAl Divide Select Bit 0 |
.equ XDIV1 = 1 ; XTAl Divide Select Bit 1 |
.equ XDIV2 = 2 ; XTAl Divide Select Bit 2 |
.equ XDIV3 = 3 ; XTAl Divide Select Bit 3 |
.equ XDIV4 = 4 ; XTAl Divide Select Bit 4 |
.equ XDIV5 = 5 ; XTAl Divide Select Bit 5 |
.equ XDIV6 = 6 ; XTAl Divide Select Bit 6 |
.equ XDIVEN = 7 ; XTAL Divide Enable |
; MCUCSR - MCU Control And Status Register |
.equ PORF = 0 ; Power-on reset flag |
.equ EXTRF = 1 ; External Reset Flag |
.equ BORF = 2 ; Brown-out Reset Flag |
.equ WDRF = 3 ; Watchdog Reset Flag |
.equ JTRF = 4 ; JTAG Reset Flag |
.equ JTD = 7 ; JTAG Interface Disable |
; ***** BOOT_LOAD ******************** |
; SPMCSR - Store Program Memory Control Register |
.equ SPMCR = SPMCSR ; For compatibility |
.equ SPMEN = 0 ; Store Program Memory Enable |
.equ PGERS = 1 ; Page Erase |
.equ PGWRT = 2 ; Page Write |
.equ BLBSET = 3 ; Boot Lock Bit Set |
.equ RWWSRE = 4 ; Read While Write section read enable |
.equ ASRE = RWWSRE ; For compatibility |
.equ RWWSB = 6 ; Read While Write Section Busy |
.equ ASB = RWWSB ; For compatibility |
.equ SPMIE = 7 ; SPM Interrupt Enable |
; ***** JTAG ************************* |
; OCDR - On-Chip Debug Related Register in I/O Memory |
.equ OCDR0 = 0 ; On-Chip Debug Register Bit 0 |
.equ OCDR1 = 1 ; On-Chip Debug Register Bit 1 |
.equ OCDR2 = 2 ; On-Chip Debug Register Bit 2 |
.equ OCDR3 = 3 ; On-Chip Debug Register Bit 3 |
.equ OCDR4 = 4 ; On-Chip Debug Register Bit 4 |
.equ OCDR5 = 5 ; On-Chip Debug Register Bit 5 |
.equ OCDR6 = 6 ; On-Chip Debug Register Bit 6 |
.equ OCDR7 = 7 ; On-Chip Debug Register Bit 7 |
.equ IDRD = OCDR7 ; For compatibility |
; MCUCSR - MCU Control And Status Register |
;.equ JTRF = 4 ; JTAG Reset Flag |
;.equ JTD = 7 ; JTAG Interface Disable |
; ***** MISC ************************* |
; SFIOR - Special Function IO Register |
.equ PSR321 = 0 ; Prescaler Reset Timer/Counter3, Timer/Counter2, and Timer/Counter1 |
.equ PSR1 = PSR321 ; For compatibility |
.equ PSR2 = PSR321 ; For compatibility |
.equ PSR3 = PSR321 ; For compatibility |
.equ PSR0 = 1 ; Prescaler Reset Timer/Counter0 |
.equ PUD = 2 ; Pull Up Disable |
;.equ ACME = 3 ; Analog Comparator Multiplexer Enable |
.equ TSM = 7 ; Timer/Counter Synchronization Mode |
; ***** EXTERNAL_INTERRUPT *********** |
; EICRA - External Interrupt Control Register A |
.equ ISC00 = 0 ; External Interrupt Sense Control Bit |
.equ ISC01 = 1 ; External Interrupt Sense Control Bit |
.equ ISC10 = 2 ; External Interrupt Sense Control Bit |
.equ ISC11 = 3 ; External Interrupt Sense Control Bit |
.equ ISC20 = 4 ; External Interrupt Sense Control Bit |
.equ ISC21 = 5 ; External Interrupt Sense Control Bit |
.equ ISC30 = 6 ; External Interrupt Sense Control Bit |
.equ ISC31 = 7 ; External Interrupt Sense Control Bit |
; EICRB - External Interrupt Control Register B |
.equ ISC40 = 0 ; External Interrupt 7-4 Sense Control Bit |
.equ ISC41 = 1 ; External Interrupt 7-4 Sense Control Bit |
.equ ISC50 = 2 ; External Interrupt 7-4 Sense Control Bit |
.equ ISC51 = 3 ; External Interrupt 7-4 Sense Control Bit |
.equ ISC60 = 4 ; External Interrupt 7-4 Sense Control Bit |
.equ ISC61 = 5 ; External Interrupt 7-4 Sense Control Bit |
.equ ISC70 = 6 ; External Interrupt 7-4 Sense Control Bit |
.equ ISC71 = 7 ; External Interrupt 7-4 Sense Control Bit |
; EIMSK - External Interrupt Mask Register |
.equ GICR = EIMSK ; For compatibility |
.equ GIMSK = EIMSK ; For compatibility |
.equ INT0 = 0 ; External Interrupt Request 0 Enable |
.equ INT1 = 1 ; External Interrupt Request 1 Enable |
.equ INT2 = 2 ; External Interrupt Request 2 Enable |
.equ INT3 = 3 ; External Interrupt Request 3 Enable |
.equ INT4 = 4 ; External Interrupt Request 4 Enable |
.equ INT5 = 5 ; External Interrupt Request 5 Enable |
.equ INT6 = 6 ; External Interrupt Request 6 Enable |
.equ INT7 = 7 ; External Interrupt Request 7 Enable |
; EIFR - External Interrupt Flag Register |
.equ GIFR = EIFR ; For compatibility |
.equ INTF0 = 0 ; External Interrupt Flag 0 |
.equ INTF1 = 1 ; External Interrupt Flag 1 |
.equ INTF2 = 2 ; External Interrupt Flag 2 |
.equ INTF3 = 3 ; External Interrupt Flag 3 |
.equ INTF4 = 4 ; External Interrupt Flag 4 |
.equ INTF5 = 5 ; External Interrupt Flag 5 |
.equ INTF6 = 6 ; External Interrupt Flag 6 |
.equ INTF7 = 7 ; External Interrupt Flag 7 |
; ***** EEPROM *********************** |
; EEDR - EEPROM Data Register |
.equ EEDR0 = 0 ; EEPROM Data Register bit 0 |
.equ EEDR1 = 1 ; EEPROM Data Register bit 1 |
.equ EEDR2 = 2 ; EEPROM Data Register bit 2 |
.equ EEDR3 = 3 ; EEPROM Data Register bit 3 |
.equ EEDR4 = 4 ; EEPROM Data Register bit 4 |
.equ EEDR5 = 5 ; EEPROM Data Register bit 5 |
.equ EEDR6 = 6 ; EEPROM Data Register bit 6 |
.equ EEDR7 = 7 ; EEPROM Data Register bit 7 |
; EECR - EEPROM Control Register |
.equ EERE = 0 ; EEPROM Read Enable |
.equ EEWE = 1 ; EEPROM Write Enable |
.equ EEMWE = 2 ; EEPROM Master Write Enable |
.equ EERIE = 3 ; EEPROM Ready Interrupt Enable |
; ***** PORTA ************************ |
; PORTA - Port A Data Register |
.equ PORTA0 = 0 ; Port A Data Register bit 0 |
.equ PA0 = 0 ; For compatibility |
.equ PORTA1 = 1 ; Port A Data Register bit 1 |
.equ PA1 = 1 ; For compatibility |
.equ PORTA2 = 2 ; Port A Data Register bit 2 |
.equ PA2 = 2 ; For compatibility |
.equ PORTA3 = 3 ; Port A Data Register bit 3 |
.equ PA3 = 3 ; For compatibility |
.equ PORTA4 = 4 ; Port A Data Register bit 4 |
.equ PA4 = 4 ; For compatibility |
.equ PORTA5 = 5 ; Port A Data Register bit 5 |
.equ PA5 = 5 ; For compatibility |
.equ PORTA6 = 6 ; Port A Data Register bit 6 |
.equ PA6 = 6 ; For compatibility |
.equ PORTA7 = 7 ; Port A Data Register bit 7 |
.equ PA7 = 7 ; For compatibility |
; DDRA - Port A Data Direction Register |
.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0 |
.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1 |
.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2 |
.equ DDA3 = 3 ; Data Direction Register, Port A, bit 3 |
.equ DDA4 = 4 ; Data Direction Register, Port A, bit 4 |
.equ DDA5 = 5 ; Data Direction Register, Port A, bit 5 |
.equ DDA6 = 6 ; Data Direction Register, Port A, bit 6 |
.equ DDA7 = 7 ; Data Direction Register, Port A, bit 7 |
; PINA - Port A Input Pins |
.equ PINA0 = 0 ; Input Pins, Port A bit 0 |
.equ PINA1 = 1 ; Input Pins, Port A bit 1 |
.equ PINA2 = 2 ; Input Pins, Port A bit 2 |
.equ PINA3 = 3 ; Input Pins, Port A bit 3 |
.equ PINA4 = 4 ; Input Pins, Port A bit 4 |
.equ PINA5 = 5 ; Input Pins, Port A bit 5 |
.equ PINA6 = 6 ; Input Pins, Port A bit 6 |
.equ PINA7 = 7 ; Input Pins, Port A bit 7 |
; ***** PORTB ************************ |
; PORTB - Port B Data Register |
.equ PORTB0 = 0 ; Port B Data Register bit 0 |
.equ PB0 = 0 ; For compatibility |
.equ PORTB1 = 1 ; Port B Data Register bit 1 |
.equ PB1 = 1 ; For compatibility |
.equ PORTB2 = 2 ; Port B Data Register bit 2 |
.equ PB2 = 2 ; For compatibility |
.equ PORTB3 = 3 ; Port B Data Register bit 3 |
.equ PB3 = 3 ; For compatibility |
.equ PORTB4 = 4 ; Port B Data Register bit 4 |
.equ PB4 = 4 ; For compatibility |
.equ PORTB5 = 5 ; Port B Data Register bit 5 |
.equ PB5 = 5 ; For compatibility |
.equ PORTB6 = 6 ; Port B Data Register bit 6 |
.equ PB6 = 6 ; For compatibility |
.equ PORTB7 = 7 ; Port B Data Register bit 7 |
.equ PB7 = 7 ; For compatibility |
; DDRB - Port B Data Direction Register |
.equ DDB0 = 0 ; Port B Data Direction Register bit 0 |
.equ DDB1 = 1 ; Port B Data Direction Register bit 1 |
.equ DDB2 = 2 ; Port B Data Direction Register bit 2 |
.equ DDB3 = 3 ; Port B Data Direction Register bit 3 |
.equ DDB4 = 4 ; Port B Data Direction Register bit 4 |
.equ DDB5 = 5 ; Port B Data Direction Register bit 5 |
.equ DDB6 = 6 ; Port B Data Direction Register bit 6 |
.equ DDB7 = 7 ; Port B Data Direction Register bit 7 |
; PINB - Port B Input Pins |
.equ PINB0 = 0 ; Port B Input Pins bit 0 |
.equ PINB1 = 1 ; Port B Input Pins bit 1 |
.equ PINB2 = 2 ; Port B Input Pins bit 2 |
.equ PINB3 = 3 ; Port B Input Pins bit 3 |
.equ PINB4 = 4 ; Port B Input Pins bit 4 |
.equ PINB5 = 5 ; Port B Input Pins bit 5 |
.equ PINB6 = 6 ; Port B Input Pins bit 6 |
.equ PINB7 = 7 ; Port B Input Pins bit 7 |
; ***** PORTC ************************ |
; PORTC - Port C Data Register |
.equ PORTC0 = 0 ; Port C Data Register bit 0 |
.equ PC0 = 0 ; For compatibility |
.equ PORTC1 = 1 ; Port C Data Register bit 1 |
.equ PC1 = 1 ; For compatibility |
.equ PORTC2 = 2 ; Port C Data Register bit 2 |
.equ PC2 = 2 ; For compatibility |
.equ PORTC3 = 3 ; Port C Data Register bit 3 |
.equ PC3 = 3 ; For compatibility |
.equ PORTC4 = 4 ; Port C Data Register bit 4 |
.equ PC4 = 4 ; For compatibility |
.equ PORTC5 = 5 ; Port C Data Register bit 5 |
.equ PC5 = 5 ; For compatibility |
.equ PORTC6 = 6 ; Port C Data Register bit 6 |
.equ PC6 = 6 ; For compatibility |
.equ PORTC7 = 7 ; Port C Data Register bit 7 |
.equ PC7 = 7 ; For compatibility |
; DDRC - Port C Data Direction Register |
.equ DDC0 = 0 ; Port C Data Direction Register bit 0 |
.equ DDC1 = 1 ; Port C Data Direction Register bit 1 |
.equ DDC2 = 2 ; Port C Data Direction Register bit 2 |
.equ DDC3 = 3 ; Port C Data Direction Register bit 3 |
.equ DDC4 = 4 ; Port C Data Direction Register bit 4 |
.equ DDC5 = 5 ; Port C Data Direction Register bit 5 |
.equ DDC6 = 6 ; Port C Data Direction Register bit 6 |
.equ DDC7 = 7 ; Port C Data Direction Register bit 7 |
; PINC - Port C Input Pins |
.equ PINC0 = 0 ; Port C Input Pins bit 0 |
.equ PINC1 = 1 ; Port C Input Pins bit 1 |
.equ PINC2 = 2 ; Port C Input Pins bit 2 |
.equ PINC3 = 3 ; Port C Input Pins bit 3 |
.equ PINC4 = 4 ; Port C Input Pins bit 4 |
.equ PINC5 = 5 ; Port C Input Pins bit 5 |
.equ PINC6 = 6 ; Port C Input Pins bit 6 |
.equ PINC7 = 7 ; Port C Input Pins bit 7 |
; ***** PORTD ************************ |
; PORTD - Port D Data Register |
.equ PORTD0 = 0 ; Port D Data Register bit 0 |
.equ PD0 = 0 ; For compatibility |
.equ PORTD1 = 1 ; Port D Data Register bit 1 |
.equ PD1 = 1 ; For compatibility |
.equ PORTD2 = 2 ; Port D Data Register bit 2 |
.equ PD2 = 2 ; For compatibility |
.equ PORTD3 = 3 ; Port D Data Register bit 3 |
.equ PD3 = 3 ; For compatibility |
.equ PORTD4 = 4 ; Port D Data Register bit 4 |
.equ PD4 = 4 ; For compatibility |
.equ PORTD5 = 5 ; Port D Data Register bit 5 |
.equ PD5 = 5 ; For compatibility |
.equ PORTD6 = 6 ; Port D Data Register bit 6 |
.equ PD6 = 6 ; For compatibility |
.equ PORTD7 = 7 ; Port D Data Register bit 7 |
.equ PD7 = 7 ; For compatibility |
; DDRD - Port D Data Direction Register |
.equ DDD0 = 0 ; Port D Data Direction Register bit 0 |
.equ DDD1 = 1 ; Port D Data Direction Register bit 1 |
.equ DDD2 = 2 ; Port D Data Direction Register bit 2 |
.equ DDD3 = 3 ; Port D Data Direction Register bit 3 |
.equ DDD4 = 4 ; Port D Data Direction Register bit 4 |
.equ DDD5 = 5 ; Port D Data Direction Register bit 5 |
.equ DDD6 = 6 ; Port D Data Direction Register bit 6 |
.equ DDD7 = 7 ; Port D Data Direction Register bit 7 |
; PIND - Port D Input Pins |
.equ PIND0 = 0 ; Port D Input Pins bit 0 |
.equ PIND1 = 1 ; Port D Input Pins bit 1 |
.equ PIND2 = 2 ; Port D Input Pins bit 2 |
.equ PIND3 = 3 ; Port D Input Pins bit 3 |
.equ PIND4 = 4 ; Port D Input Pins bit 4 |
.equ PIND5 = 5 ; Port D Input Pins bit 5 |
.equ PIND6 = 6 ; Port D Input Pins bit 6 |
.equ PIND7 = 7 ; Port D Input Pins bit 7 |
; ***** PORTE ************************ |
; PORTE - Data Register, Port E |
.equ PORTE0 = 0 ; |
.equ PE0 = 0 ; For compatibility |
.equ PORTE1 = 1 ; |
.equ PE1 = 1 ; For compatibility |
.equ PORTE2 = 2 ; |
.equ PE2 = 2 ; For compatibility |
.equ PORTE3 = 3 ; |
.equ PE3 = 3 ; For compatibility |
.equ PORTE4 = 4 ; |
.equ PE4 = 4 ; For compatibility |
.equ PORTE5 = 5 ; |
.equ PE5 = 5 ; For compatibility |
.equ PORTE6 = 6 ; |
.equ PE6 = 6 ; For compatibility |
.equ PORTE7 = 7 ; |
.equ PE7 = 7 ; For compatibility |
; DDRE - Data Direction Register, Port E |
.equ DDE0 = 0 ; |
.equ DDE1 = 1 ; |
.equ DDE2 = 2 ; |
.equ DDE3 = 3 ; |
.equ DDE4 = 4 ; |
.equ DDE5 = 5 ; |
.equ DDE6 = 6 ; |
.equ DDE7 = 7 ; |
; PINE - Input Pins, Port E |
.equ PINE0 = 0 ; |
.equ PINE1 = 1 ; |
.equ PINE2 = 2 ; |
.equ PINE3 = 3 ; |
.equ PINE4 = 4 ; |
.equ PINE5 = 5 ; |
.equ PINE6 = 6 ; |
.equ PINE7 = 7 ; |
; ***** PORTF ************************ |
; PORTF - Data Register, Port F |
.equ PORTF0 = 0 ; |
.equ PF0 = 0 ; For compatibility |
.equ PORTF1 = 1 ; |
.equ PF1 = 1 ; For compatibility |
.equ PORTF2 = 2 ; |
.equ PF2 = 2 ; For compatibility |
.equ PORTF3 = 3 ; |
.equ PF3 = 3 ; For compatibility |
.equ PORTF4 = 4 ; |
.equ PF4 = 4 ; For compatibility |
.equ PORTF5 = 5 ; |
.equ PF5 = 5 ; For compatibility |
.equ PORTF6 = 6 ; |
.equ PF6 = 6 ; For compatibility |
.equ PORTF7 = 7 ; |
.equ PF7 = 7 ; For compatibility |
; DDRF - Data Direction Register, Port F |
.equ DDF0 = 0 ; |
.equ DDF1 = 1 ; |
.equ DDF2 = 2 ; |
.equ DDF3 = 3 ; |
.equ DDF4 = 4 ; |
.equ DDF5 = 5 ; |
.equ DDF6 = 6 ; |
.equ DDF7 = 7 ; |
; PINF - Input Pins, Port F |
.equ PINF0 = 0 ; |
.equ PINF1 = 1 ; |
.equ PINF2 = 2 ; |
.equ PINF3 = 3 ; |
.equ PINF4 = 4 ; |
.equ PINF5 = 5 ; |
.equ PINF6 = 6 ; |
.equ PINF7 = 7 ; |
; ***** PORTG ************************ |
; PORTG - Data Register, Port G |
.equ PORTG0 = 0 ; |
.equ PG0 = 0 ; For compatibility |
.equ PORTG1 = 1 ; |
.equ PG1 = 1 ; For compatibility |
.equ PORTG2 = 2 ; |
.equ PG2 = 2 ; For compatibility |
.equ PORTG3 = 3 ; |
.equ PG3 = 3 ; For compatibility |
.equ PORTG4 = 4 ; |
.equ PG4 = 4 ; For compatibility |
; DDRG - Data Direction Register, Port G |
.equ DDG0 = 0 ; |
.equ DDG1 = 1 ; |
.equ DDG2 = 2 ; |
.equ DDG3 = 3 ; |
.equ DDG4 = 4 ; |
; PING - Input Pins, Port G |
.equ PING0 = 0 ; |
.equ PING1 = 1 ; |
.equ PING2 = 2 ; |
.equ PING3 = 3 ; |
.equ PING4 = 4 ; |
; ***** TIMER_COUNTER_0 ************** |
; TCCR0 - Timer/Counter Control Register |
.equ CS00 = 0 ; Clock Select 0 |
.equ CS01 = 1 ; Clock Select 1 |
.equ CS02 = 2 ; Clock Select 2 |
.equ WGM01 = 3 ; Waveform Generation Mode 1 |
.equ CTC0 = WGM01 ; For compatibility |
.equ COM00 = 4 ; Compare match Output Mode 0 |
.equ COM01 = 5 ; Compare Match Output Mode 1 |
.equ WGM00 = 6 ; Waveform Generation Mode 0 |
.equ PWM0 = WGM00 ; For compatibility |
.equ FOC0 = 7 ; Force Output Compare |
; TCNT0 - Timer/Counter Register |
.equ TCNT0_0 = 0 ; |
.equ TCNT0_1 = 1 ; |
.equ TCNT0_2 = 2 ; |
.equ TCNT0_3 = 3 ; |
.equ TCNT0_4 = 4 ; |
.equ TCNT0_5 = 5 ; |
.equ TCNT0_6 = 6 ; |
.equ TCNT0_7 = 7 ; |
; OCR0 - Output Compare Register |
.equ OCR0_0 = 0 ; |
.equ OCR0_1 = 1 ; |
.equ OCR0_2 = 2 ; |
.equ OCR0_3 = 3 ; |
.equ OCR0_4 = 4 ; |
.equ OCR0_5 = 5 ; |
.equ OCR0_6 = 6 ; |
.equ OCR0_7 = 7 ; |
; ASSR - Asynchronus Status Register |
.equ TCR0UB = 0 ; Timer/Counter Control Register 0 Update Busy |
.equ OCR0UB = 1 ; Output Compare register 0 Busy |
.equ TCN0UB = 2 ; Timer/Counter0 Update Busy |
.equ AS0 = 3 ; Asynchronus Timer/Counter 0 |
; TIMSK - Timer/Counter Interrupt Mask Register |
.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable |
.equ OCIE0 = 1 ; Timer/Counter0 Output Compare Match Interrupt register |
; TIFR - Timer/Counter Interrupt Flag register |
.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag |
.equ OCF0 = 1 ; Output Compare Flag 0 |
; SFIOR - Special Function IO Register |
;.equ PSR0 = 1 ; Prescaler Reset Timer/Counter0 |
;.equ TSM = 7 ; Timer/Counter Synchronization Mode |
; ***** TIMER_COUNTER_1 ************** |
; TIMSK - Timer/Counter Interrupt Mask Register |
.equ TOIE1 = 2 ; Timer/Counter1 Overflow Interrupt Enable |
.equ OCIE1B = 3 ; Timer/Counter1 Output CompareB Match Interrupt Enable |
.equ OCIE1A = 4 ; Timer/Counter1 Output CompareA Match Interrupt Enable |
.equ TICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable |
; ETIMSK - Extended Timer/Counter Interrupt Mask Register |
.equ OCIE1C = 0 ; Timer/Counter 1, Output Compare Match C Interrupt Enable |
; TIFR - Timer/Counter Interrupt Flag register |
.equ TOV1 = 2 ; Timer/Counter1 Overflow Flag |
.equ OCF1B = 3 ; Output Compare Flag 1B |
.equ OCF1A = 4 ; Output Compare Flag 1A |
.equ ICF1 = 5 ; Input Capture Flag 1 |
; ETIFR - Extended Timer/Counter Interrupt Flag register |
.equ OCF1C = 0 ; Timer/Counter 1, Output Compare C Match Flag |
; SFIOR - Special Function IO Register |
;.equ PSR321 = 0 ; Prescaler Reset, T/C3, T/C2, T/C1 |
;.equ TSM = 7 ; Timer/Counter Synchronization Mode |
; TCCR1A - Timer/Counter1 Control Register A |
.equ WGM10 = 0 ; Waveform Generation Mode Bit 0 |
.equ PWM10 = WGM10 ; For compatibility |
.equ WGM11 = 1 ; Waveform Generation Mode Bit 1 |
.equ PWM11 = WGM11 ; For compatibility |
.equ COM1C0 = 2 ; Compare Output Mode 1C, bit 0 |
.equ COM1C1 = 3 ; Compare Output Mode 1C, bit 1 |
.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0 |
.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1 |
.equ COM1A0 = 6 ; Compare Ouput Mode 1A, bit 0 |
.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1 |
; TCCR1B - Timer/Counter1 Control Register B |
.equ CS10 = 0 ; Clock Select bit 0 |
.equ CS11 = 1 ; Clock Select 1 bit 1 |
.equ CS12 = 2 ; Clock Select1 bit 2 |
.equ WGM12 = 3 ; Waveform Generation Mode |
.equ CTC10 = WGM12 ; For compatibility |
.equ WGM13 = 4 ; Waveform Generation Mode |
.equ CTC11 = WGM13 ; For compatibility |
.equ ICES1 = 6 ; Input Capture 1 Edge Select |
.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler |
; TCCR1C - Timer/Counter1 Control Register C |
.equ FOC1C = 5 ; Force Output Compare for channel C |
.equ FOC1B = 6 ; Force Output Compare for channel B |
.equ FOC1A = 7 ; Force Output Compare for channel A |
; ***** TIMER_COUNTER_2 ************** |
; TCCR2 - Timer/Counter Control Register |
.equ CS20 = 0 ; Clock Select |
.equ CS21 = 1 ; Clock Select |
.equ CS22 = 2 ; Clock Select |
.equ WGM21 = 3 ; Waveform Generation Mode |
.equ CTC2 = WGM21 ; For compatibility |
.equ COM20 = 4 ; Compare Match Output Mode |
.equ COM21 = 5 ; Compare Match Output Mode |
.equ WGM20 = 6 ; Wafeform Generation Mode |
.equ PWM2 = WGM20 ; For compatibility |
.equ FOC2 = 7 ; Force Output Compare |
; TCNT2 - Timer/Counter Register |
.equ TCNT2_0 = 0 ; Timer/Counter Register Bit 0 |
.equ TCNT2_1 = 1 ; Timer/Counter Register Bit 1 |
.equ TCNT2_2 = 2 ; Timer/Counter Register Bit 2 |
.equ TCNT2_3 = 3 ; Timer/Counter Register Bit 3 |
.equ TCNT2_4 = 4 ; Timer/Counter Register Bit 4 |
.equ TCNT2_5 = 5 ; Timer/Counter Register Bit 5 |
.equ TCNT2_6 = 6 ; Timer/Counter Register Bit 6 |
.equ TCNT2_7 = 7 ; Timer/Counter Register Bit 7 |
; OCR2 - Output Compare Register |
.equ OCR2_0 = 0 ; Output Compare Register Bit 0 |
.equ OCR2_1 = 1 ; Output Compare Register Bit 1 |
.equ OCR2_2 = 2 ; Output Compare Register Bit 2 |
.equ OCR2_3 = 3 ; Output Compare Register Bit 3 |
.equ OCR2_4 = 4 ; Output Compare Register Bit 4 |
.equ OCR2_5 = 5 ; Output Compare Register Bit 5 |
.equ OCR2_6 = 6 ; Output Compare Register Bit 6 |
.equ OCR2_7 = 7 ; Output Compare Register Bit 7 |
; TIMSK - |
.equ TOIE2 = 6 ; |
.equ OCIE2 = 7 ; |
; TIFR - Timer/Counter Interrupt Flag Register |
.equ TOV2 = 6 ; Timer/Counter2 Overflow Flag |
.equ OCF2 = 7 ; Output Compare Flag 2 |
; ***** TIMER_COUNTER_3 ************** |
; ETIMSK - Extended Timer/Counter Interrupt Mask Register |
.equ OCIE3C = 1 ; Timer/Counter3, Output Compare Match Interrupt Enable |
.equ TOIE3 = 2 ; Timer/Counter3 Overflow Interrupt Enable |
.equ OCIE3B = 3 ; Timer/Counter3 Output CompareB Match Interrupt Enable |
.equ OCIE3A = 4 ; Timer/Counter3 Output CompareA Match Interrupt Enable |
.equ TICIE3 = 5 ; Timer/Counter3 Input Capture Interrupt Enable |
; ETIFR - Extended Timer/Counter Interrupt Flag register |
.equ OCF3C = 1 ; Timer/Counter3 Output Compare C Match Flag |
.equ TOV3 = 2 ; Timer/Counter3 Overflow Flag |
.equ OCF3B = 3 ; Output Compare Flag 1B |
.equ OCF3A = 4 ; Output Compare Flag 1A |
.equ ICF3 = 5 ; Input Capture Flag 1 |
; SFIOR - Special Function IO Register |
;.equ PSR321 = 0 ; Prescaler Reset, T/C3, T/C2, T/C1 |
;.equ PSR1 = PSR321 ; For compatibility |
;.equ PSR2 = PSR321 ; For compatibility |
;.equ TSM = 7 ; Timer/Counter Synchronization Mode |
; TCCR3A - Timer/Counter3 Control Register A |
.equ WGM30 = 0 ; Waveform Generation Mode Bit 0 |
.equ PWM30 = WGM30 ; For compatibility |
.equ WGM31 = 1 ; Waveform Generation Mode Bit 1 |
.equ PWM31 = WGM31 ; For compatibility |
.equ COM3C0 = 2 ; Compare Output Mode 3C, bit 0 |
.equ COM3C1 = 3 ; Compare Output Mode 3C, bit 1 |
.equ COM3B0 = 4 ; Compare Output Mode 3B, bit 0 |
.equ COM3B1 = 5 ; Compare Output Mode 3B, bit 1 |
.equ COM3A0 = 6 ; Comparet Ouput Mode 3A, bit 0 |
.equ COM3A1 = 7 ; Compare Output Mode 3A, bit 1 |
; TCCR3B - Timer/Counter3 Control Register B |
.equ CS30 = 0 ; Clock Select 3 bit 0 |
.equ CS31 = 1 ; Clock Select 3 bit 1 |
.equ CS32 = 2 ; Clock Select3 bit 2 |
.equ WGM32 = 3 ; Waveform Generation Mode |
.equ CTC30 = WGM32 ; For compatibility |
.equ WGM33 = 4 ; Waveform Generation Mode |
.equ CTC31 = WGM33 ; For compatibility |
.equ ICES3 = 6 ; Input Capture 3 Edge Select |
.equ ICNC3 = 7 ; Input Capture 3 Noise Canceler |
; TCCR3C - Timer/Counter3 Control Register C |
.equ FOC3C = 5 ; Force Output Compare for channel C |
.equ FOC3B = 6 ; Force Output Compare for channel B |
.equ FOC3A = 7 ; Force Output Compare for channel A |
; ***** WATCHDOG ********************* |
; WDTCR - Watchdog Timer Control Register |
.equ WDTCSR = WDTCR ; For compatibility |
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 |
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 |
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 |
.equ WDE = 3 ; Watch Dog Enable |
.equ WDCE = 4 ; Watchdog Change Enable |
.equ WDTOE = WDCE ; For compatibility |
; ***** LOCKSBITS ******************************************************** |
.equ LB1 = 0 ; Lock bit |
.equ LB2 = 1 ; Lock bit |
.equ BLB01 = 2 ; Boot Lock bit |
.equ BLB02 = 3 ; Boot Lock bit |
.equ BLB11 = 4 ; Boot lock bit |
.equ BLB12 = 5 ; Boot lock bit |
; ***** FUSES ************************************************************ |
; LOW fuse bits |
.equ CKSEL0 = 0 ; Select Clock Source |
.equ CKSEL1 = 1 ; Select Clock Source |
.equ CKSEL2 = 2 ; Select Clock Source |
.equ CKSEL3 = 3 ; Select Clock Source |
.equ SUT0 = 4 ; Select start-up time |
.equ SUT1 = 5 ; Select start-up time |
.equ BODEN = 6 ; Brown out detector enable |
.equ BODLEVEL = 7 ; Brown out detector trigger level |
; HIGH fuse bits |
.equ BOOTRST = 0 ; Select Reset Vector |
.equ BOOTSZ0 = 1 ; Select Boot Size |
.equ BOOTSZ1 = 2 ; Select Boot Size |
.equ EESAVE = 3 ; EEPROM memory is preserved through chip erase |
.equ CKOPT = 4 ; Oscillator Options |
.equ SPIEN = 5 ; Enable Serial programming and Data Downloading |
.equ JTAGEN = 6 ; Enable JTAG |
.equ OCDEN = 7 ; Enable OCD |
; EXTENDED fuse bits |
.equ WDTON = 0 ; Watchdog timer always on |
.equ CompMode = 1 ; Compabillity mode |
; ***** CPU REGISTER DEFINITIONS ***************************************** |
.def XH = r27 |
.def XL = r26 |
.def YH = r29 |
.def YL = r28 |
.def ZH = r31 |
.def ZL = r30 |
; ***** DATA MEMORY DECLARATIONS ***************************************** |
.equ FLASHEND = 0x7fff ; Note: Word address |
.equ IOEND = 0x00ff |
.equ SRAM_START = 0x0100 |
.equ SRAM_SIZE = 4096 |
.equ RAMEND = 0x10ff |
.equ XRAMEND = 0xffff |
.equ E2END = 0x07ff |
.equ EEPROMEND = 0x07ff |
.equ EEADRBITS = 11 |
#pragma AVRPART MEMORY PROG_FLASH 65536 |
#pragma AVRPART MEMORY EEPROM 2048 |
#pragma AVRPART MEMORY INT_SRAM SIZE 4096 |
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x100 |
; ***** BOOTLOADER DECLARATIONS ****************************************** |
.equ NRWW_START_ADDR = 0x7000 |
.equ NRWW_STOP_ADDR = 0x7fff |
.equ RWW_START_ADDR = 0x0 |
.equ RWW_STOP_ADDR = 0x6fff |
.equ PAGESIZE = 128 |
.equ FIRSTBOOTSTART = 0x7e00 |
.equ SECONDBOOTSTART = 0x7c00 |
.equ THIRDBOOTSTART = 0x7800 |
.equ FOURTHBOOTSTART = 0x7000 |
.equ SMALLBOOTSTART = FIRSTBOOTSTART |
.equ LARGEBOOTSTART = FOURTHBOOTSTART |
; ***** INTERRUPT VECTORS ************************************************ |
.equ INT0addr = 0x0002 ; External Interrupt Request 0 |
.equ INT1addr = 0x0004 ; External Interrupt Request 1 |
.equ INT2addr = 0x0006 ; External Interrupt Request 2 |
.equ INT3addr = 0x0008 ; External Interrupt Request 3 |
.equ INT4addr = 0x000a ; External Interrupt Request 4 |
.equ INT5addr = 0x000c ; External Interrupt Request 5 |
.equ INT6addr = 0x000e ; External Interrupt Request 6 |
.equ INT7addr = 0x0010 ; External Interrupt Request 7 |
.equ OC2addr = 0x0012 ; Timer/Counter2 Compare Match |
.equ OVF2addr = 0x0014 ; Timer/Counter2 Overflow |
.equ ICP1addr = 0x0016 ; Timer/Counter1 Capture Event |
.equ OC1Aaddr = 0x0018 ; Timer/Counter1 Compare Match A |
.equ OC1Baddr = 0x001a ; Timer/Counter Compare Match B |
.equ OVF1addr = 0x001c ; Timer/Counter1 Overflow |
.equ OC0addr = 0x001e ; Timer/Counter0 Compare Match |
.equ OVF0addr = 0x0020 ; Timer/Counter0 Overflow |
.equ SPIaddr = 0x0022 ; SPI Serial Transfer Complete |
.equ URXC0addr = 0x0024 ; USART0, Rx Complete |
.equ UDRE0addr = 0x0026 ; USART0 Data Register Empty |
.equ UTXC0addr = 0x0028 ; USART0, Tx Complete |
.equ ADCCaddr = 0x002a ; ADC Conversion Complete |
.equ ERDYaddr = 0x002c ; EEPROM Ready |
.equ ACIaddr = 0x002e ; Analog Comparator |
.equ OC1Caddr = 0x0030 ; Timer/Counter1 Compare Match C |
.equ ICP3addr = 0x0032 ; Timer/Counter3 Capture Event |
.equ OC3Aaddr = 0x0034 ; Timer/Counter3 Compare Match A |
.equ OC3Baddr = 0x0036 ; Timer/Counter3 Compare Match B |
.equ OC3Caddr = 0x0038 ; Timer/Counter3 Compare Match C |
.equ OVF3addr = 0x003a ; Timer/Counter3 Overflow |
.equ URXC1addr = 0x003c ; USART1, Rx Complete |
.equ UDRE1addr = 0x003e ; USART1, Data Register Empty |
.equ UTXC1addr = 0x0040 ; USART1, Tx Complete |
.equ TWIaddr = 0x0042 ; 2-wire Serial Interface |
.equ SPMRaddr = 0x0044 ; Store Program Memory Read |
.equ INT_VECTORS_SIZE = 70 ; size in words |
#endif /* _M64DEF_INC_ */ |
; ***** END OF FILE ****************************************************** |
/contrib/toolchain/avra/includes/m8515def.inc |
---|
0,0 → 1,683 |
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** |
;***** Created: 2005-01-11 10:31 ******* Source: ATmega8515.xml ********** |
;************************************************************************* |
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y |
;* |
;* Number : AVR000 |
;* File Name : "m8515def.inc" |
;* Title : Register/Bit Definitions for the ATmega8515 |
;* Date : 2005-01-11 |
;* Version : 2.14 |
;* Support E-mail : avr@atmel.com |
;* Target MCU : ATmega8515 |
;* |
;* DESCRIPTION |
;* When including this file in the assembly program file, all I/O register |
;* names and I/O register bit names appearing in the data book can be used. |
;* In addition, the six registers forming the three data pointers X, Y and |
;* Z have been assigned names XL - ZH. Highest RAM address for Internal |
;* SRAM is also defined |
;* |
;* The Register names are represented by their hexadecimal address. |
;* |
;* The Register Bit names are represented by their bit number (0-7). |
;* |
;* Please observe the difference in using the bit names with instructions |
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" |
;* (skip if bit in register set/cleared). The following example illustrates |
;* this: |
;* |
;* in r16,PORTB ;read PORTB latch |
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) |
;* out PORTB,r16 ;output to PORTB |
;* |
;* in r16,TIFR ;read the Timer Interrupt Flag Register |
;* sbrc r16,TOV0 ;test the overflow flag (use bit#) |
;* rjmp TOV0_is_set ;jump if set |
;* ... ;otherwise do something else |
;************************************************************************* |
#ifndef _M8515DEF_INC_ |
#define _M8515DEF_INC_ |
#pragma partinc 0 |
; ***** SPECIFY DEVICE *************************************************** |
.device ATmega8515 |
#pragma AVRPART ADMIN PART_NAME ATmega8515 |
.equ SIGNATURE_000 = 0x1e |
.equ SIGNATURE_001 = 0x93 |
.equ SIGNATURE_002 = 0x06 |
#pragma AVRPART CORE CORE_VERSION V2E |
; ***** I/O REGISTER DEFINITIONS ***************************************** |
; NOTE: |
; Definitions marked "MEMORY MAPPED"are extended I/O ports |
; and cannot be used with IN/OUT instructions |
.equ SREG = 0x3f |
.equ SPH = 0x3e |
.equ SPL = 0x3d |
.equ GICR = 0x3b |
.equ GIFR = 0x3a |
.equ TIMSK = 0x39 |
.equ TIFR = 0x38 |
.equ SPMCR = 0x37 |
.equ EMCUCR = 0x36 |
.equ MCUCR = 0x35 |
.equ MCUCSR = 0x34 |
.equ TCCR0 = 0x33 |
.equ TCNT0 = 0x32 |
.equ OCR0 = 0x31 |
.equ SFIOR = 0x30 |
.equ TCCR1A = 0x2f |
.equ TCCR1B = 0x2e |
.equ TCNT1H = 0x2d |
.equ TCNT1L = 0x2c |
.equ OCR1AH = 0x2b |
.equ OCR1AL = 0x2a |
.equ OCR1BH = 0x29 |
.equ OCR1BL = 0x28 |
.equ ICR1H = 0x25 |
.equ ICR1L = 0x24 |
.equ WDTCR = 0x21 |
.equ UBRRH = 0x20 |
.equ UCSRC = 0x20 |
.equ EEARH = 0x1f |
.equ EEARL = 0x1e |
.equ EEDR = 0x1d |
.equ EECR = 0x1c |
.equ PORTA = 0x1b |
.equ DDRA = 0x1a |
.equ PINA = 0x19 |
.equ PORTB = 0x18 |
.equ DDRB = 0x17 |
.equ PINB = 0x16 |
.equ PORTC = 0x15 |
.equ DDRC = 0x14 |
.equ PINC = 0x13 |
.equ PORTD = 0x12 |
.equ DDRD = 0x11 |
.equ PIND = 0x10 |
.equ SPDR = 0x0f |
.equ SPSR = 0x0e |
.equ SPCR = 0x0d |
.equ UDR = 0x0c |
.equ UCSRA = 0x0b |
.equ UCSRB = 0x0a |
.equ UBRRL = 0x09 |
.equ ACSR = 0x08 |
.equ PORTE = 0x07 |
.equ DDRE = 0x06 |
.equ PINE = 0x05 |
.equ OSCCAL = 0x04 |
; ***** BIT DEFINITIONS ************************************************** |
; ***** ANALOG_COMPARATOR ************ |
; ACSR - Analog Comparator Control And Status Register |
.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 |
.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 |
.equ ACIC = 2 ; Analog Comparator Input Capture Enable |
.equ ACIE = 3 ; Analog Comparator Interrupt Enable |
.equ ACI = 4 ; Analog Comparator Interrupt Flag |
.equ ACO = 5 ; Analog Compare Output |
.equ ACBG = 6 ; Analog Comparator Bandgap Select |
.equ AINBG = ACBG ; For compatibility |
.equ ACD = 7 ; Analog Comparator Disable |
; ***** USART ************************ |
; UDR - USART I/O Data Register |
.equ UDR0 = 0 ; USART I/O Data Register bit 0 |
.equ UDR1 = 1 ; USART I/O Data Register bit 1 |
.equ UDR2 = 2 ; USART I/O Data Register bit 2 |
.equ UDR3 = 3 ; USART I/O Data Register bit 3 |
.equ UDR4 = 4 ; USART I/O Data Register bit 4 |
.equ UDR5 = 5 ; USART I/O Data Register bit 5 |
.equ UDR6 = 6 ; USART I/O Data Register bit 6 |
.equ UDR7 = 7 ; USART I/O Data Register bit 7 |
; UCSRA - USART Control and Status Register A |
.equ MPCM = 0 ; Multi-processor Communication Mode |
.equ U2X = 1 ; Double the USART transmission speed |
.equ UPE = 2 ; Parity Error |
.equ PE = UPE ; For compatibility |
.equ DOR = 3 ; Data overRun |
.equ FE = 4 ; Framing Error |
.equ UDRE = 5 ; USART Data Register Empty |
.equ TXC = 6 ; USART Transmitt Complete |
.equ RXC = 7 ; USART Receive Complete |
; UCSRB - USART Control and Status Register B |
.equ TXB8 = 0 ; Transmit Data Bit 8 |
.equ RXB8 = 1 ; Receive Data Bit 8 |
.equ UCSZ2 = 2 ; Character Size Bit 2 |
.equ CHR9 = UCSZ2 ; For compatibility |
.equ TXEN = 3 ; Transmitter Enable |
.equ RXEN = 4 ; Receiver Enable |
.equ UDRIE = 5 ; USART Data register Empty Interrupt Enable |
.equ TXCIE = 6 ; TX Complete Interrupt Enable |
.equ RXCIE = 7 ; RX Complete Interrupt Enable |
; UCSRC - USART Control and Status Register C |
.equ UCPOL = 0 ; Clock Polarity |
.equ UCSZ0 = 1 ; Character Size Bit 0 |
.equ UCSZ1 = 2 ; Character Size Bit 1 |
.equ USBS = 3 ; Stop Bit Select |
.equ UPM0 = 4 ; Parity Mode Bit 0 |
.equ UPM1 = 5 ; Parity Mode Bit 1 |
.equ UMSEL = 6 ; USART Mode Select |
.equ URSEL = 7 ; Register Select |
; UBRRH - USART Baud Rate Register High Byte |
.equ UBRR8 = 0 ; USART Baud Rate Register bit 8 |
.equ UBRR9 = 1 ; USART Baud Rate Register bit 9 |
.equ UBRR10 = 2 ; USART Baud Rate Register bit 10 |
.equ UBRR11 = 3 ; USART Baud Rate Register bit 11 |
;.equ URSEL = 7 ; Register Select |
; ***** SPI ************************** |
; SPDR - SPI Data Register |
.equ SPDR0 = 0 ; SPI Data Register bit 0 |
.equ SPDR1 = 1 ; SPI Data Register bit 1 |
.equ SPDR2 = 2 ; SPI Data Register bit 2 |
.equ SPDR3 = 3 ; SPI Data Register bit 3 |
.equ SPDR4 = 4 ; SPI Data Register bit 4 |
.equ SPDR5 = 5 ; SPI Data Register bit 5 |
.equ SPDR6 = 6 ; SPI Data Register bit 6 |
.equ SPDR7 = 7 ; SPI Data Register bit 7 |
; SPSR - SPI Status Register |
.equ SPI2X = 0 ; Double SPI Speed Bit |
.equ WCOL = 6 ; Write Collision Flag |
.equ SPIF = 7 ; SPI Interrupt Flag |
; SPCR - SPI Control Register |
.equ SPR0 = 0 ; SPI Clock Rate Select 0 |
.equ SPR1 = 1 ; SPI Clock Rate Select 1 |
.equ CPHA = 2 ; Clock Phase |
.equ CPOL = 3 ; Clock polarity |
.equ MSTR = 4 ; Master/Slave Select |
.equ DORD = 5 ; Data Order |
.equ SPE = 6 ; SPI Enable |
.equ SPIE = 7 ; SPI Interrupt Enable |
; ***** CPU ************************** |
; SREG - Status Register |
.equ SREG_C = 0 ; Carry Flag |
.equ SREG_Z = 1 ; Zero Flag |
.equ SREG_N = 2 ; Negative Flag |
.equ SREG_V = 3 ; Two's Complement Overflow Flag |
.equ SREG_S = 4 ; Sign Bit |
.equ SREG_H = 5 ; Half Carry Flag |
.equ SREG_T = 6 ; Bit Copy Storage |
.equ SREG_I = 7 ; Global Interrupt Enable |
; EMCUCR - Extended MCU Control Register |
.equ ISC2 = 0 ; Interrupt Sense Control 2 |
.equ SRW11 = 1 ; Wait State Select Bits for Upper Sector, bit 1 |
.equ SRW00 = 2 ; Wait State Select Bits for Lower Sector, bit 0 |
.equ SRW01 = 3 ; Wait State Select Bits for Lower Sector, bit 1 |
.equ SRL0 = 4 ; Wait State Selector Limit bit 0 |
.equ SRL1 = 5 ; Wait State Selector Limit bit 1 |
.equ SRL2 = 6 ; Wait State Selector Limit bit 2 |
.equ SM0 = 7 ; Sleep Mode Select Bit 0 |
; MCUCR - MCU Control Register |
.equ ISC00 = 0 ; Interrupt Sense Control 0 Bit 0 |
.equ ISC01 = 1 ; Interrupt Sense Control 0 Bit 1 |
.equ ISC10 = 2 ; Interrupt Sense Control 1 Bit 0 |
.equ ISC11 = 3 ; Interrupt Sense Control 1 Bit 1 |
.equ SM1 = 4 ; Sleep Mode Select Bit 1 |
.equ SE = 5 ; Sleep Enable |
.equ SRW10 = 6 ; Wait State Select Bits for Upper Sector, bit 0 |
.equ SRE = 7 ; External SRAM/XMEM Enable |
; MCUCSR - MCU Control And Status Register |
.equ MCUSR = MCUCSR ; For compatibility |
.equ PORF = 0 ; Power-on reset flag |
.equ EXTRF = 1 ; External Reset Flag |
.equ BORF = 2 ; Brown-out Reset Flag |
.equ WDRF = 3 ; Watchdog Reset Flag |
.equ SM2 = 5 ; Sleep Mode Select Bit 2 |
; OSCCAL - Oscillator Calibration Value |
.equ CAL0 = 0 ; Oscillator Calibration Value Bit0 |
.equ CAL1 = 1 ; Oscillator Calibration Value Bit1 |
.equ CAL2 = 2 ; Oscillator Calibration Value Bit2 |
.equ CAL3 = 3 ; Oscillator Calibration Value Bit3 |
.equ CAL4 = 4 ; Oscillator Calibration Value Bit4 |
.equ CAL5 = 5 ; Oscillator Calibration Value Bit5 |
.equ CAL6 = 6 ; Oscillator Calibration Value Bit6 |
.equ CAL7 = 7 ; Oscillator Calibration Value Bit7 |
; SPMCR - Store Program Memory Control Register |
.equ SPMEN = 0 ; Store Program Memory Enable |
.equ PGERS = 1 ; Page Erase |
.equ PGWRT = 2 ; Page Write |
.equ BLBSET = 3 ; Boot Lock Bit Set |
.equ RWWSRE = 4 ; Read-While-Write Section Read Enable |
.equ ASRE = RWWSRE ; For compatibility |
.equ RWWSB = 6 ; Read-While-Write Section Busy |
.equ ASB = RWWSB ; For compatibility |
.equ SPMIE = 7 ; SPM Interrupt Enable |
; SFIOR - Special Function IO Register |
.equ PSR10 = 0 ; Prescaler Reset Timer / Counter 1 and Timer / Counter 0 |
.equ PUD = 2 ; Pull-up Disable |
.equ XMM0 = 3 ; External Memory High Mask Bit 0 |
.equ XMM1 = 4 ; External Memory High Mask Bit 1 |
.equ XMM2 = 5 ; External Memory High Mask Bit 2 |
.equ XMBK = 6 ; External Memory Bus Keeper Enable |
; ***** EXTERNAL_INTERRUPT *********** |
; GICR - General Interrupt Control Register |
.equ GIMSK = GICR ; For compatibility |
.equ IVCE = 0 ; Interrupt Vector Change Enable |
.equ IVSEL = 1 ; Interrupt Vector Select |
.equ INT2 = 5 ; External Interrupt Request 2 Enable |
.equ INT0 = 6 ; External Interrupt Request 0 Enable |
.equ INT1 = 7 ; External Interrupt Request 1 Enable |
; GIFR - General Interrupt Flag Register |
.equ INTF2 = 5 ; External Interrupt Flag 2 |
.equ INTF0 = 6 ; External Interrupt Flag 0 |
.equ INTF1 = 7 ; External Interrupt Flag 1 |
; ***** WATCHDOG ********************* |
; WDTCR - Watchdog Timer Control Register |
.equ WDTCSR = WDTCR ; For compatibility |
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 |
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 |
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 |
.equ WDE = 3 ; Watch Dog Enable |
.equ WDCE = 4 ; Watchdog Change Enable |
.equ WDTOE = WDCE ; For compatibility |
; ***** TIMER_COUNTER_0 ************** |
; TCCR0 - Timer/Counter 0 Control Register |
.equ CS00 = 0 ; Clock Select 1 |
.equ CS01 = 1 ; Clock Select 1 |
.equ CS02 = 2 ; Clock Select 2 |
.equ WGM01 = 3 ; Waveform Generation Mode 1 |
.equ CTC0 = WGM01 ; For compatibility |
.equ COM00 = 4 ; Compare match Output Mode 0 |
.equ COM01 = 5 ; Compare Match Output Mode 1 |
.equ WGM00 = 6 ; Waveform Generation Mode 0 |
.equ PWM0 = WGM00 ; For compatibility |
.equ FOC0 = 7 ; Force Output Compare |
; TCNT0 - Timer/Counter 0 Register |
.equ TCNT0_0 = 0 ; |
.equ TCNT0_1 = 1 ; |
.equ TCNT0_2 = 2 ; |
.equ TCNT0_3 = 3 ; |
.equ TCNT0_4 = 4 ; |
.equ TCNT0_5 = 5 ; |
.equ TCNT0_6 = 6 ; |
.equ TCNT0_7 = 7 ; |
; OCR0 - Timer/Counter 0 Output Compare Register |
.equ OCR0_0 = 0 ; |
.equ OCR0_1 = 1 ; |
.equ OCR0_2 = 2 ; |
.equ OCR0_3 = 3 ; |
.equ OCR0_4 = 4 ; |
.equ OCR0_5 = 5 ; |
.equ OCR0_6 = 6 ; |
.equ OCR0_7 = 7 ; |
; TIMSK - Timer/Counter Interrupt Mask Register |
.equ OCIE0 = 0 ; Timer/Counter0 Output Compare Match Interrupt register |
.equ TOIE0 = 1 ; Timer/Counter0 Overflow Interrupt Enable |
; TIFR - Timer/Counter Interrupt Flag register |
.equ OCF0 = 0 ; Output Compare Flag 0 |
.equ TOV0 = 1 ; Timer/Counter0 Overflow Flag |
; ***** TIMER_COUNTER_1 ************** |
; TIMSK - Timer/Counter Interrupt Mask Register |
.equ TICIE1 = 3 ; Timer/Counter1 Input Capture Interrupt Enable |
.equ OCIE1B = 5 ; Timer/Counter1 Output CompareB Match Interrupt Enable |
.equ OCIE1A = 6 ; Timer/Counter1 Output CompareA Match Interrupt Enable |
.equ TOIE1 = 7 ; Timer/Counter1 Overflow Interrupt Enable |
; TIFR - Timer/Counter Interrupt Flag register |
.equ ICF1 = 3 ; Input Capture Flag 1 |
.equ OCF1B = 5 ; Output Compare Flag 1B |
.equ OCF1A = 6 ; Output Compare Flag 1A |
.equ TOV1 = 7 ; Timer/Counter1 Overflow Flag |
; TCCR1A - Timer/Counter1 Control Register A |
.equ WGM10 = 0 ; Pulse Width Modulator Select Bit 0 |
.equ PWM10 = WGM10 ; For compatibility |
.equ WGM11 = 1 ; Pulse Width Modulator Select Bit 1 |
.equ PWM11 = WGM11 ; For compatibility |
.equ FOC1B = 2 ; Force Output Compare for Channel B |
.equ FOC1A = 3 ; Force Output Compare for Channel A |
.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0 |
.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1 |
.equ COM1A0 = 6 ; Compare Ouput Mode 1A, bit 0 |
.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1 |
; TCCR1B - Timer/Counter1 Control Register B |
.equ CS10 = 0 ; Clock Select1 bit 0 |
.equ CS11 = 1 ; Clock Select1 bit 1 |
.equ CS12 = 2 ; Clock Select1 bit 2 |
.equ WGM12 = 3 ; Pulse Width Modulator Select Bit 2 |
.equ CTC10 = WGM12 ; For compatibility |
.equ WGM13 = 4 ; Pulse Width Modulator Select Bit 3 |
.equ CTC11 = WGM13 ; For compatibility |
.equ ICES1 = 6 ; Input Capture 1 Edge Select |
.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler |
; ***** PORTA ************************ |
; PORTA - Port A Data Register |
.equ PORTA0 = 0 ; Port A Data Register bit 0 |
.equ PA0 = 0 ; For compatibility |
.equ PORTA1 = 1 ; Port A Data Register bit 1 |
.equ PA1 = 1 ; For compatibility |
.equ PORTA2 = 2 ; Port A Data Register bit 2 |
.equ PA2 = 2 ; For compatibility |
.equ PORTA3 = 3 ; Port A Data Register bit 3 |
.equ PA3 = 3 ; For compatibility |
.equ PORTA4 = 4 ; Port A Data Register bit 4 |
.equ PA4 = 4 ; For compatibility |
.equ PORTA5 = 5 ; Port A Data Register bit 5 |
.equ PA5 = 5 ; For compatibility |
.equ PORTA6 = 6 ; Port A Data Register bit 6 |
.equ PA6 = 6 ; For compatibility |
.equ PORTA7 = 7 ; Port A Data Register bit 7 |
.equ PA7 = 7 ; For compatibility |
; DDRA - Port A Data Direction Register |
.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0 |
.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1 |
.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2 |
.equ DDA3 = 3 ; Data Direction Register, Port A, bit 3 |
.equ DDA4 = 4 ; Data Direction Register, Port A, bit 4 |
.equ DDA5 = 5 ; Data Direction Register, Port A, bit 5 |
.equ DDA6 = 6 ; Data Direction Register, Port A, bit 6 |
.equ DDA7 = 7 ; Data Direction Register, Port A, bit 7 |
; PINA - Port A Input Pins |
.equ PINA0 = 0 ; Input Pins, Port A bit 0 |
.equ PINA1 = 1 ; Input Pins, Port A bit 1 |
.equ PINA2 = 2 ; Input Pins, Port A bit 2 |
.equ PINA3 = 3 ; Input Pins, Port A bit 3 |
.equ PINA4 = 4 ; Input Pins, Port A bit 4 |
.equ PINA5 = 5 ; Input Pins, Port A bit 5 |
.equ PINA6 = 6 ; Input Pins, Port A bit 6 |
.equ PINA7 = 7 ; Input Pins, Port A bit 7 |
; ***** PORTB ************************ |
; PORTB - Port B Data Register |
.equ PORTB0 = 0 ; Port B Data Register bit 0 |
.equ PB0 = 0 ; For compatibility |
.equ PORTB1 = 1 ; Port B Data Register bit 1 |
.equ PB1 = 1 ; For compatibility |
.equ PORTB2 = 2 ; Port B Data Register bit 2 |
.equ PB2 = 2 ; For compatibility |
.equ PORTB3 = 3 ; Port B Data Register bit 3 |
.equ PB3 = 3 ; For compatibility |
.equ PORTB4 = 4 ; Port B Data Register bit 4 |
.equ PB4 = 4 ; For compatibility |
.equ PORTB5 = 5 ; Port B Data Register bit 5 |
.equ PB5 = 5 ; For compatibility |
.equ PORTB6 = 6 ; Port B Data Register bit 6 |
.equ PB6 = 6 ; For compatibility |
.equ PORTB7 = 7 ; Port B Data Register bit 7 |
.equ PB7 = 7 ; For compatibility |
; DDRB - Port B Data Direction Register |
.equ DDB0 = 0 ; Port B Data Direction Register bit 0 |
.equ DDB1 = 1 ; Port B Data Direction Register bit 1 |
.equ DDB2 = 2 ; Port B Data Direction Register bit 2 |
.equ DDB3 = 3 ; Port B Data Direction Register bit 3 |
.equ DDB4 = 4 ; Port B Data Direction Register bit 4 |
.equ DDB5 = 5 ; Port B Data Direction Register bit 5 |
.equ DDB6 = 6 ; Port B Data Direction Register bit 6 |
.equ DDB7 = 7 ; Port B Data Direction Register bit 7 |
; PINB - Port B Input Pins |
.equ PINB0 = 0 ; Port B Input Pins bit 0 |
.equ PINB1 = 1 ; Port B Input Pins bit 1 |
.equ PINB2 = 2 ; Port B Input Pins bit 2 |
.equ PINB3 = 3 ; Port B Input Pins bit 3 |
.equ PINB4 = 4 ; Port B Input Pins bit 4 |
.equ PINB5 = 5 ; Port B Input Pins bit 5 |
.equ PINB6 = 6 ; Port B Input Pins bit 6 |
.equ PINB7 = 7 ; Port B Input Pins bit 7 |
; ***** PORTC ************************ |
; PORTC - Port C Data Register |
.equ PORTC0 = 0 ; Port C Data Register bit 0 |
.equ PC0 = 0 ; For compatibility |
.equ PORTC1 = 1 ; Port C Data Register bit 1 |
.equ PC1 = 1 ; For compatibility |
.equ PORTC2 = 2 ; Port C Data Register bit 2 |
.equ PC2 = 2 ; For compatibility |
.equ PORTC3 = 3 ; Port C Data Register bit 3 |
.equ PC3 = 3 ; For compatibility |
.equ PORTC4 = 4 ; Port C Data Register bit 4 |
.equ PC4 = 4 ; For compatibility |
.equ PORTC5 = 5 ; Port C Data Register bit 5 |
.equ PC5 = 5 ; For compatibility |
.equ PORTC6 = 6 ; Port C Data Register bit 6 |
.equ PC6 = 6 ; For compatibility |
.equ PORTC7 = 7 ; Port C Data Register bit 7 |
.equ PC7 = 7 ; For compatibility |
; DDRC - Port C Data Direction Register |
.equ DDC0 = 0 ; Port C Data Direction Register bit 0 |
.equ DDC1 = 1 ; Port C Data Direction Register bit 1 |
.equ DDC2 = 2 ; Port C Data Direction Register bit 2 |
.equ DDC3 = 3 ; Port C Data Direction Register bit 3 |
.equ DDC4 = 4 ; Port C Data Direction Register bit 4 |
.equ DDC5 = 5 ; Port C Data Direction Register bit 5 |
.equ DDC6 = 6 ; Port C Data Direction Register bit 6 |
.equ DDC7 = 7 ; Port C Data Direction Register bit 7 |
; PINC - Port C Input Pins |
.equ PINC0 = 0 ; Port C Input Pins bit 0 |
.equ PINC1 = 1 ; Port C Input Pins bit 1 |
.equ PINC2 = 2 ; Port C Input Pins bit 2 |
.equ PINC3 = 3 ; Port C Input Pins bit 3 |
.equ PINC4 = 4 ; Port C Input Pins bit 4 |
.equ PINC5 = 5 ; Port C Input Pins bit 5 |
.equ PINC6 = 6 ; Port C Input Pins bit 6 |
.equ PINC7 = 7 ; Port C Input Pins bit 7 |
; ***** PORTD ************************ |
; PORTD - Port D Data Register |
.equ PORTD0 = 0 ; Port D Data Register bit 0 |
.equ PD0 = 0 ; For compatibility |
.equ PORTD1 = 1 ; Port D Data Register bit 1 |
.equ PD1 = 1 ; For compatibility |
.equ PORTD2 = 2 ; Port D Data Register bit 2 |
.equ PD2 = 2 ; For compatibility |
.equ PORTD3 = 3 ; Port D Data Register bit 3 |
.equ PD3 = 3 ; For compatibility |
.equ PORTD4 = 4 ; Port D Data Register bit 4 |
.equ PD4 = 4 ; For compatibility |
.equ PORTD5 = 5 ; Port D Data Register bit 5 |
.equ PD5 = 5 ; For compatibility |
.equ PORTD6 = 6 ; Port D Data Register bit 6 |
.equ PD6 = 6 ; For compatibility |
.equ PORTD7 = 7 ; Port D Data Register bit 7 |
.equ PD7 = 7 ; For compatibility |
; DDRD - Port D Data Direction Register |
.equ DDD0 = 0 ; Port D Data Direction Register bit 0 |
.equ DDD1 = 1 ; Port D Data Direction Register bit 1 |
.equ DDD2 = 2 ; Port D Data Direction Register bit 2 |
.equ DDD3 = 3 ; Port D Data Direction Register bit 3 |
.equ DDD4 = 4 ; Port D Data Direction Register bit 4 |
.equ DDD5 = 5 ; Port D Data Direction Register bit 5 |
.equ DDD6 = 6 ; Port D Data Direction Register bit 6 |
.equ DDD7 = 7 ; Port D Data Direction Register bit 7 |
; PIND - Port D Input Pins |
.equ PIND0 = 0 ; Port D Input Pins bit 0 |
.equ PIND1 = 1 ; Port D Input Pins bit 1 |
.equ PIND2 = 2 ; Port D Input Pins bit 2 |
.equ PIND3 = 3 ; Port D Input Pins bit 3 |
.equ PIND4 = 4 ; Port D Input Pins bit 4 |
.equ PIND5 = 5 ; Port D Input Pins bit 5 |
.equ PIND6 = 6 ; Port D Input Pins bit 6 |
.equ PIND7 = 7 ; Port D Input Pins bit 7 |
; ***** PORTE ************************ |
; PORTE - Port E Data Register |
.equ PORTE0 = 0 ; |
.equ PE0 = 0 ; For compatibility |
.equ PORTE1 = 1 ; |
.equ PE1 = 1 ; For compatibility |
.equ PORTE2 = 2 ; |
.equ PE2 = 2 ; For compatibility |
; DDRE - Port E Data Direction Register |
.equ DDE0 = 0 ; |
.equ DDE1 = 1 ; |
.equ DDE2 = 2 ; |
; PINE - Port E Input Pins |
.equ PINE0 = 0 ; |
.equ PINE1 = 1 ; |
.equ PINE2 = 2 ; |
; ***** EEPROM *********************** |
; EEDR - EEPROM Data Register |
.equ EEDR0 = 0 ; EEPROM Data Register bit 0 |
.equ EEDR1 = 1 ; EEPROM Data Register bit 1 |
.equ EEDR2 = 2 ; EEPROM Data Register bit 2 |
.equ EEDR3 = 3 ; EEPROM Data Register bit 3 |
.equ EEDR4 = 4 ; EEPROM Data Register bit 4 |
.equ EEDR5 = 5 ; EEPROM Data Register bit 5 |
.equ EEDR6 = 6 ; EEPROM Data Register bit 6 |
.equ EEDR7 = 7 ; EEPROM Data Register bit 7 |
; EECR - EEPROM Control Register |
.equ EERE = 0 ; EEPROM Read Enable |
.equ EEWE = 1 ; EEPROM Write Enable |
.equ EEMWE = 2 ; EEPROM Master Write Enable |
.equ EEWEE = EEMWE ; For compatibility |
.equ EERIE = 3 ; EEPROM Ready Interrupt Enable |
; ***** LOCKSBITS ******************************************************** |
.equ LB1 = 0 ; Lock bit |
.equ LB2 = 1 ; Lock bit |
.equ BLB01 = 2 ; Boot Lock bit |
.equ BLB02 = 3 ; Boot Lock bit |
.equ BLB11 = 4 ; Boot lock bit |
.equ BLB12 = 5 ; Boot lock bit |
; ***** FUSES ************************************************************ |
; LOW fuse bits |
.equ CKSEL0 = 0 ; Select Clock Source |
.equ CKSEL1 = 1 ; Select Clock Source |
.equ CKSEL2 = 2 ; Select Clock Source |
.equ CKSEL3 = 3 ; Select Clock Source |
.equ SUT0 = 4 ; Select start-up time |
.equ SUT1 = 5 ; Select start-up time |
.equ BODEN = 6 ; Brown out detector enable |
.equ BODLEVEL = 7 ; Brown out detector trigger level |
; HIGH fuse bits |
.equ BOOTRST = 0 ; Select Reset Vector |
.equ BOOTSZ0 = 1 ; Select Boot Size |
.equ BOOTSZ1 = 2 ; Select Boot Size |
.equ EESAVE = 3 ; EEPROM memory is preserved through chip erase |
.equ CKOPT = 4 ; Oscillator Options |
.equ SPIEN = 5 ; Enable Serial programming and Data Downloading |
.equ WDTON = 6 ; Watchdog timer always on |
.equ S8515C = 7 ; AT90S4414/8515 compabillity mode |
; ***** CPU REGISTER DEFINITIONS ***************************************** |
.def XH = r27 |
.def XL = r26 |
.def YH = r29 |
.def YL = r28 |
.def ZH = r31 |
.def ZL = r30 |
; ***** DATA MEMORY DECLARATIONS ***************************************** |
.equ FLASHEND = 0x0fff ; Note: Word address |
.equ IOEND = 0x003f |
.equ SRAM_START = 0x0060 |
.equ SRAM_SIZE = 512 |
.equ RAMEND = 0x025f |
.equ XRAMEND = 0xffff |
.equ E2END = 0x01ff |
.equ EEPROMEND = 0x01ff |
.equ EEADRBITS = 9 |
#pragma AVRPART MEMORY PROG_FLASH 8192 |
#pragma AVRPART MEMORY EEPROM 512 |
#pragma AVRPART MEMORY INT_SRAM SIZE 512 |
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60 |
; ***** BOOTLOADER DECLARATIONS ****************************************** |
.equ NRWW_START_ADDR = 0xc00 |
.equ NRWW_STOP_ADDR = 0xfff |
.equ RWW_START_ADDR = 0x0 |
.equ RWW_STOP_ADDR = 0xbff |
.equ PAGESIZE = 32 |
.equ FIRSTBOOTSTART = 0xf80 |
.equ SECONDBOOTSTART = 0xf00 |
.equ THIRDBOOTSTART = 0xe00 |
.equ FOURTHBOOTSTART = 0xc00 |
.equ SMALLBOOTSTART = FIRSTBOOTSTART |
.equ LARGEBOOTSTART = FOURTHBOOTSTART |
; ***** INTERRUPT VECTORS ************************************************ |
.equ INT0addr = 0x0001 ; External Interrupt Request 0 |
.equ INT1addr = 0x0002 ; External Interrupt Request 1 |
.equ ICP1addr = 0x0003 ; Timer/Counter1 Capture Event |
.equ OC1Aaddr = 0x0004 ; Timer/Counter1 Compare Match A |
.equ OC1Baddr = 0x0005 ; Timer/Counter1 Compare MatchB |
.equ OVF1addr = 0x0006 ; Timer/Counter1 Overflow |
.equ OVF0addr = 0x0007 ; Timer/Counter0 Overflow |
.equ SPIaddr = 0x0008 ; Serial Transfer Complete |
.equ URXCaddr = 0x0009 ; UART, Rx Complete |
.equ UDREaddr = 0x000a ; UART Data Register Empty |
.equ UTXCaddr = 0x000b ; UART, Tx Complete |
.equ ACIaddr = 0x000c ; Analog Comparator |
.equ INT2addr = 0x000d ; External Interrupt Request 2 |
.equ OC0addr = 0x000e ; Timer 0 Compare Match |
.equ ERDYaddr = 0x000f ; EEPROM Ready |
.equ SPMRaddr = 0x0010 ; Store Program Memory Ready |
.equ INT_VECTORS_SIZE = 17 ; size in words |
#pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED break |
#endif /* _M8515DEF_INC_ */ |
; ***** END OF FILE ****************************************************** |
/contrib/toolchain/avra/includes/m8535def.inc |
---|
0,0 → 1,841 |
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** |
;***** Created: 2005-01-11 10:31 ******* Source: ATmega8535.xml ********** |
;************************************************************************* |
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y |
;* |
;* Number : AVR000 |
;* File Name : "m8535def.inc" |
;* Title : Register/Bit Definitions for the ATmega8535 |
;* Date : 2005-01-11 |
;* Version : 2.14 |
;* Support E-mail : avr@atmel.com |
;* Target MCU : ATmega8535 |
;* |
;* DESCRIPTION |
;* When including this file in the assembly program file, all I/O register |
;* names and I/O register bit names appearing in the data book can be used. |
;* In addition, the six registers forming the three data pointers X, Y and |
;* Z have been assigned names XL - ZH. Highest RAM address for Internal |
;* SRAM is also defined |
;* |
;* The Register names are represented by their hexadecimal address. |
;* |
;* The Register Bit names are represented by their bit number (0-7). |
;* |
;* Please observe the difference in using the bit names with instructions |
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" |
;* (skip if bit in register set/cleared). The following example illustrates |
;* this: |
;* |
;* in r16,PORTB ;read PORTB latch |
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) |
;* out PORTB,r16 ;output to PORTB |
;* |
;* in r16,TIFR ;read the Timer Interrupt Flag Register |
;* sbrc r16,TOV0 ;test the overflow flag (use bit#) |
;* rjmp TOV0_is_set ;jump if set |
;* ... ;otherwise do something else |
;************************************************************************* |
#ifndef _M8535DEF_INC_ |
#define _M8535DEF_INC_ |
#pragma partinc 0 |
; ***** SPECIFY DEVICE *************************************************** |
.device ATmega8535 |
#pragma AVRPART ADMIN PART_NAME ATmega8535 |
.equ SIGNATURE_000 = 0x1e |
.equ SIGNATURE_001 = 0x93 |
.equ SIGNATURE_002 = 0x08 |
#pragma AVRPART CORE CORE_VERSION V2E |
; ***** I/O REGISTER DEFINITIONS ***************************************** |
; NOTE: |
; Definitions marked "MEMORY MAPPED"are extended I/O ports |
; and cannot be used with IN/OUT instructions |
.equ SREG = 0x3f |
.equ SPH = 0x3e |
.equ SPL = 0x3d |
.equ OCR0 = 0x3c |
.equ GICR = 0x3b |
.equ GIFR = 0x3a |
.equ TIMSK = 0x39 |
.equ TIFR = 0x38 |
.equ SPMCR = 0x37 |
.equ TWCR = 0x36 |
.equ MCUCR = 0x35 |
.equ MCUCSR = 0x34 |
.equ TCCR0 = 0x33 |
.equ TCNT0 = 0x32 |
.equ OSCCAL = 0x31 |
.equ SFIOR = 0x30 |
.equ TCCR1A = 0x2f |
.equ TCCR1B = 0x2e |
.equ TCNT1H = 0x2d |
.equ TCNT1L = 0x2c |
.equ OCR1AH = 0x2b |
.equ OCR1AL = 0x2a |
.equ OCR1BH = 0x29 |
.equ OCR1BL = 0x28 |
.equ ICR1H = 0x27 |
.equ ICR1L = 0x26 |
.equ TCCR2 = 0x25 |
.equ TCNT2 = 0x24 |
.equ OCR2 = 0x23 |
.equ ASSR = 0x22 |
.equ WDTCR = 0x21 |
.equ UBRRH = 0x20 |
.equ UCSRC = 0x20 |
.equ EEARH = 0x1f |
.equ EEARL = 0x1e |
.equ EEDR = 0x1d |
.equ EECR = 0x1c |
.equ PORTA = 0x1b |
.equ DDRA = 0x1a |
.equ PINA = 0x19 |
.equ PORTB = 0x18 |
.equ DDRB = 0x17 |
.equ PINB = 0x16 |
.equ PORTC = 0x15 |
.equ DDRC = 0x14 |
.equ PINC = 0x13 |
.equ PORTD = 0x12 |
.equ DDRD = 0x11 |
.equ PIND = 0x10 |
.equ SPDR = 0x0f |
.equ SPSR = 0x0e |
.equ SPCR = 0x0d |
.equ UDR = 0x0c |
.equ UCSRA = 0x0b |
.equ UCSRB = 0x0a |
.equ UBRRL = 0x09 |
.equ ACSR = 0x08 |
.equ ADMUX = 0x07 |
.equ ADCSRA = 0x06 |
.equ ADCH = 0x05 |
.equ ADCL = 0x04 |
.equ TWDR = 0x03 |
.equ TWAR = 0x02 |
.equ TWSR = 0x01 |
.equ TWBR = 0x00 |
; ***** BIT DEFINITIONS ************************************************** |
; ***** AD_CONVERTER ***************** |
; ADMUX - The ADC multiplexer Selection Register |
.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits |
.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits |
.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits |
.equ MUX3 = 3 ; Analog Channel and Gain Selection Bits |
.equ MUX4 = 4 ; Analog Channel and Gain Selection Bits |
.equ ADLAR = 5 ; Left Adjust Result |
.equ REFS0 = 6 ; Reference Selection Bit 0 |
.equ REFS1 = 7 ; Reference Selection Bit 1 |
; ADCSRA - The ADC Control and Status register |
.equ ADPS0 = 0 ; ADC Prescaler Select Bits |
.equ ADPS1 = 1 ; ADC Prescaler Select Bits |
.equ ADPS2 = 2 ; ADC Prescaler Select Bits |
.equ ADIE = 3 ; ADC Interrupt Enable |
.equ ADIF = 4 ; ADC Interrupt Flag |
.equ ADATE = 5 ; When this bit is written to one,the Timer/Counter2 prescaler will be reset.The bit will be cleared by hardware after the operation is performed.Writing a zero to this bit will have no effect.This bit will always be read as zero if Timer/Counter2 is clocked by the internal CPU clock.If this bit is written when Timer/Counter2 is operating in asynchronous mode,the bit will remain one until the prescaler has been reset. |
.equ ADFR = ADATE ; For compatibility |
.equ ADSC = 6 ; ADC Start Conversion |
.equ ADEN = 7 ; ADC Enable |
; ADCH - ADC Data Register High Byte |
.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0 |
.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1 |
.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2 |
.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3 |
.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4 |
.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5 |
.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6 |
.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7 |
; ADCL - ADC Data Register Low Byte |
.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0 |
.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1 |
.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2 |
.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3 |
.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4 |
.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5 |
.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6 |
.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7 |
; ***** ANALOG_COMPARATOR ************ |
; ACSR - Analog Comparator Control And Status Register |
.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 |
.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 |
.equ ACIC = 2 ; Analog Comparator Input Capture Enable |
.equ ACIE = 3 ; Analog Comparator Interrupt Enable |
.equ ACI = 4 ; Analog Comparator Interrupt Flag |
.equ ACO = 5 ; Analog Compare Output |
.equ ACBG = 6 ; Analog Comparator Bandgap Select |
.equ AINBG = ACBG ; For compatibility |
.equ ACD = 7 ; Analog Comparator Disable |
; ***** TWI ************************** |
; TWBR - TWI Bit Rate register |
.equ I2BR = TWBR ; For compatibility |
.equ TWBR0 = 0 ; |
.equ TWBR1 = 1 ; |
.equ TWBR2 = 2 ; |
.equ TWBR3 = 3 ; |
.equ TWBR4 = 4 ; |
.equ TWBR5 = 5 ; |
.equ TWBR6 = 6 ; |
.equ TWBR7 = 7 ; |
; TWCR - TWI Control Register |
.equ I2CR = TWCR ; For compatibility |
.equ TWIE = 0 ; TWI Interrupt Enable |
.equ I2IE = TWIE ; For compatibility |
.equ TWEN = 2 ; TWI Enable Bit |
.equ I2EN = TWEN ; For compatibility |
.equ ENI2C = TWEN ; For compatibility |
.equ TWWC = 3 ; TWI Write Collition Flag |
.equ I2WC = TWWC ; For compatibility |
.equ TWSTO = 4 ; TWI Stop Condition Bit |
.equ I2STO = TWSTO ; For compatibility |
.equ TWSTA = 5 ; TWI Start Condition Bit |
.equ I2STA = TWSTA ; For compatibility |
.equ TWEA = 6 ; TWI Enable Acknowledge Bit |
.equ I2EA = TWEA ; For compatibility |
.equ TWINT = 7 ; TWI Interrupt Flag |
.equ I2INT = TWINT ; For compatibility |
; TWSR - TWI Status Register |
.equ I2SR = TWSR ; For compatibility |
.equ TWPS0 = 0 ; TWI Prescaler |
.equ TWS0 = TWPS0 ; For compatibility |
.equ I2GCE = TWPS0 ; For compatibility |
.equ TWPS1 = 1 ; TWI Prescaler |
.equ TWS1 = TWPS1 ; For compatibility |
.equ TWS3 = 3 ; TWI Status |
.equ I2S3 = TWS3 ; For compatibility |
.equ TWS4 = 4 ; TWI Status |
.equ I2S4 = TWS4 ; For compatibility |
.equ TWS5 = 5 ; TWI Status |
.equ I2S5 = TWS5 ; For compatibility |
.equ TWS6 = 6 ; TWI Status |
.equ I2S6 = TWS6 ; For compatibility |
.equ TWS7 = 7 ; TWI Status |
.equ I2S7 = TWS7 ; For compatibility |
; TWDR - TWI Data register |
.equ I2DR = TWDR ; For compatibility |
.equ TWD0 = 0 ; TWI Data Register Bit 0 |
.equ TWD1 = 1 ; TWI Data Register Bit 1 |
.equ TWD2 = 2 ; TWI Data Register Bit 2 |
.equ TWD3 = 3 ; TWI Data Register Bit 3 |
.equ TWD4 = 4 ; TWI Data Register Bit 4 |
.equ TWD5 = 5 ; TWI Data Register Bit 5 |
.equ TWD6 = 6 ; TWI Data Register Bit 6 |
.equ TWD7 = 7 ; TWI Data Register Bit 7 |
; TWAR - TWI (Slave) Address register |
.equ I2AR = TWAR ; For compatibility |
.equ TWGCE = 0 ; TWI General Call Recognition Enable Bit |
.equ TWA0 = 1 ; TWI (Slave) Address register Bit 0 |
.equ TWA1 = 2 ; TWI (Slave) Address register Bit 1 |
.equ TWA2 = 3 ; TWI (Slave) Address register Bit 2 |
.equ TWA3 = 4 ; TWI (Slave) Address register Bit 3 |
.equ TWA4 = 5 ; TWI (Slave) Address register Bit 4 |
.equ TWA5 = 6 ; TWI (Slave) Address register Bit 5 |
.equ TWA6 = 7 ; TWI (Slave) Address register Bit 6 |
; ***** USART ************************ |
; UDR - USART I/O Data Register |
.equ UDR0 = 0 ; USART I/O Data Register bit 0 |
.equ UDR1 = 1 ; USART I/O Data Register bit 1 |
.equ UDR2 = 2 ; USART I/O Data Register bit 2 |
.equ UDR3 = 3 ; USART I/O Data Register bit 3 |
.equ UDR4 = 4 ; USART I/O Data Register bit 4 |
.equ UDR5 = 5 ; USART I/O Data Register bit 5 |
.equ UDR6 = 6 ; USART I/O Data Register bit 6 |
.equ UDR7 = 7 ; USART I/O Data Register bit 7 |
; UCSRA - USART Control and Status Register A |
.equ MPCM = 0 ; Multi-processor Communication Mode |
.equ U2X = 1 ; Double the USART transmission speed |
.equ UPE = 2 ; Parity Error |
.equ PE = UPE ; For compatibility |
.equ DOR = 3 ; Data overRun |
.equ FE = 4 ; Framing Error |
.equ UDRE = 5 ; USART Data Register Empty |
.equ TXC = 6 ; USART Transmitt Complete |
.equ RXC = 7 ; USART Receive Complete |
; UCSRB - USART Control and Status Register B |
.equ TXB8 = 0 ; Transmit Data Bit 8 |
.equ RXB8 = 1 ; Receive Data Bit 8 |
.equ UCSZ2 = 2 ; Character Size Bit 2 |
.equ CHR9 = UCSZ2 ; For compatibility |
.equ TXEN = 3 ; Transmitter Enable |
.equ RXEN = 4 ; Receiver Enable |
.equ UDRIE = 5 ; USART Data register Empty Interrupt Enable |
.equ TXCIE = 6 ; TX Complete Interrupt Enable |
.equ RXCIE = 7 ; RX Complete Interrupt Enable |
; UCSRC - USART Control and Status Register C |
.equ UCPOL = 0 ; Clock Polarity |
.equ UCSZ0 = 1 ; Character Size Bit 0 |
.equ UCSZ1 = 2 ; Character Size Bit 1 |
.equ USBS = 3 ; Stop Bit Select |
.equ UPM0 = 4 ; Parity Mode Bit 0 |
.equ UPM1 = 5 ; Parity Mode Bit 1 |
.equ UMSEL = 6 ; USART Mode Select |
.equ URSEL = 7 ; Register Select |
; UBRRH - USART Baud Rate Register High Byte |
.equ UBRR8 = 0 ; USART Baud Rate Register bit 8 |
.equ UBRR9 = 1 ; USART Baud Rate Register bit 9 |
.equ UBRR10 = 2 ; USART Baud Rate Register bit 10 |
.equ UBRR11 = 3 ; USART Baud Rate Register bit 11 |
;.equ URSEL = 7 ; Register Select |
; ***** PORTA ************************ |
; PORTA - Port A Data Register |
.equ PORTA0 = 0 ; Port A Data Register bit 0 |
.equ PA0 = 0 ; For compatibility |
.equ PORTA1 = 1 ; Port A Data Register bit 1 |
.equ PA1 = 1 ; For compatibility |
.equ PORTA2 = 2 ; Port A Data Register bit 2 |
.equ PA2 = 2 ; For compatibility |
.equ PORTA3 = 3 ; Port A Data Register bit 3 |
.equ PA3 = 3 ; For compatibility |
.equ PORTA4 = 4 ; Port A Data Register bit 4 |
.equ PA4 = 4 ; For compatibility |
.equ PORTA5 = 5 ; Port A Data Register bit 5 |
.equ PA5 = 5 ; For compatibility |
.equ PORTA6 = 6 ; Port A Data Register bit 6 |
.equ PA6 = 6 ; For compatibility |
.equ PORTA7 = 7 ; Port A Data Register bit 7 |
.equ PA7 = 7 ; For compatibility |
; DDRA - Port A Data Direction Register |
.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0 |
.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1 |
.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2 |
.equ DDA3 = 3 ; Data Direction Register, Port A, bit 3 |
.equ DDA4 = 4 ; Data Direction Register, Port A, bit 4 |
.equ DDA5 = 5 ; Data Direction Register, Port A, bit 5 |
.equ DDA6 = 6 ; Data Direction Register, Port A, bit 6 |
.equ DDA7 = 7 ; Data Direction Register, Port A, bit 7 |
; PINA - Port A Input Pins |
.equ PINA0 = 0 ; Input Pins, Port A bit 0 |
.equ PINA1 = 1 ; Input Pins, Port A bit 1 |
.equ PINA2 = 2 ; Input Pins, Port A bit 2 |
.equ PINA3 = 3 ; Input Pins, Port A bit 3 |
.equ PINA4 = 4 ; Input Pins, Port A bit 4 |
.equ PINA5 = 5 ; Input Pins, Port A bit 5 |
.equ PINA6 = 6 ; Input Pins, Port A bit 6 |
.equ PINA7 = 7 ; Input Pins, Port A bit 7 |
; ***** PORTB ************************ |
; PORTB - Port B Data Register |
.equ PORTB0 = 0 ; Port B Data Register bit 0 |
.equ PB0 = 0 ; For compatibility |
.equ PORTB1 = 1 ; Port B Data Register bit 1 |
.equ PB1 = 1 ; For compatibility |
.equ PORTB2 = 2 ; Port B Data Register bit 2 |
.equ PB2 = 2 ; For compatibility |
.equ PORTB3 = 3 ; Port B Data Register bit 3 |
.equ PB3 = 3 ; For compatibility |
.equ PORTB4 = 4 ; Port B Data Register bit 4 |
.equ PB4 = 4 ; For compatibility |
.equ PORTB5 = 5 ; Port B Data Register bit 5 |
.equ PB5 = 5 ; For compatibility |
.equ PORTB6 = 6 ; Port B Data Register bit 6 |
.equ PB6 = 6 ; For compatibility |
.equ PORTB7 = 7 ; Port B Data Register bit 7 |
.equ PB7 = 7 ; For compatibility |
; DDRB - Port B Data Direction Register |
.equ DDB0 = 0 ; Port B Data Direction Register bit 0 |
.equ DDB1 = 1 ; Port B Data Direction Register bit 1 |
.equ DDB2 = 2 ; Port B Data Direction Register bit 2 |
.equ DDB3 = 3 ; Port B Data Direction Register bit 3 |
.equ DDB4 = 4 ; Port B Data Direction Register bit 4 |
.equ DDB5 = 5 ; Port B Data Direction Register bit 5 |
.equ DDB6 = 6 ; Port B Data Direction Register bit 6 |
.equ DDB7 = 7 ; Port B Data Direction Register bit 7 |
; PINB - Port B Input Pins |
.equ PINB0 = 0 ; Port B Input Pins bit 0 |
.equ PINB1 = 1 ; Port B Input Pins bit 1 |
.equ PINB2 = 2 ; Port B Input Pins bit 2 |
.equ PINB3 = 3 ; Port B Input Pins bit 3 |
.equ PINB4 = 4 ; Port B Input Pins bit 4 |
.equ PINB5 = 5 ; Port B Input Pins bit 5 |
.equ PINB6 = 6 ; Port B Input Pins bit 6 |
.equ PINB7 = 7 ; Port B Input Pins bit 7 |
; ***** PORTC ************************ |
; PORTC - Port C Data Register |
.equ PORTC0 = 0 ; Port C Data Register bit 0 |
.equ PC0 = 0 ; For compatibility |
.equ PORTC1 = 1 ; Port C Data Register bit 1 |
.equ PC1 = 1 ; For compatibility |
.equ PORTC2 = 2 ; Port C Data Register bit 2 |
.equ PC2 = 2 ; For compatibility |
.equ PORTC3 = 3 ; Port C Data Register bit 3 |
.equ PC3 = 3 ; For compatibility |
.equ PORTC4 = 4 ; Port C Data Register bit 4 |
.equ PC4 = 4 ; For compatibility |
.equ PORTC5 = 5 ; Port C Data Register bit 5 |
.equ PC5 = 5 ; For compatibility |
.equ PORTC6 = 6 ; Port C Data Register bit 6 |
.equ PC6 = 6 ; For compatibility |
.equ PORTC7 = 7 ; Port C Data Register bit 7 |
.equ PC7 = 7 ; For compatibility |
; DDRC - Port C Data Direction Register |
.equ DDC0 = 0 ; Port C Data Direction Register bit 0 |
.equ DDC1 = 1 ; Port C Data Direction Register bit 1 |
.equ DDC2 = 2 ; Port C Data Direction Register bit 2 |
.equ DDC3 = 3 ; Port C Data Direction Register bit 3 |
.equ DDC4 = 4 ; Port C Data Direction Register bit 4 |
.equ DDC5 = 5 ; Port C Data Direction Register bit 5 |
.equ DDC6 = 6 ; Port C Data Direction Register bit 6 |
.equ DDC7 = 7 ; Port C Data Direction Register bit 7 |
; PINC - Port C Input Pins |
.equ PINC0 = 0 ; Port C Input Pins bit 0 |
.equ PINC1 = 1 ; Port C Input Pins bit 1 |
.equ PINC2 = 2 ; Port C Input Pins bit 2 |
.equ PINC3 = 3 ; Port C Input Pins bit 3 |
.equ PINC4 = 4 ; Port C Input Pins bit 4 |
.equ PINC5 = 5 ; Port C Input Pins bit 5 |
.equ PINC6 = 6 ; Port C Input Pins bit 6 |
.equ PINC7 = 7 ; Port C Input Pins bit 7 |
; ***** PORTD ************************ |
; PORTD - Port D Data Register |
.equ PORTD0 = 0 ; Port D Data Register bit 0 |
.equ PD0 = 0 ; For compatibility |
.equ PORTD1 = 1 ; Port D Data Register bit 1 |
.equ PD1 = 1 ; For compatibility |
.equ PORTD2 = 2 ; Port D Data Register bit 2 |
.equ PD2 = 2 ; For compatibility |
.equ PORTD3 = 3 ; Port D Data Register bit 3 |
.equ PD3 = 3 ; For compatibility |
.equ PORTD4 = 4 ; Port D Data Register bit 4 |
.equ PD4 = 4 ; For compatibility |
.equ PORTD5 = 5 ; Port D Data Register bit 5 |
.equ PD5 = 5 ; For compatibility |
.equ PORTD6 = 6 ; Port D Data Register bit 6 |
.equ PD6 = 6 ; For compatibility |
.equ PORTD7 = 7 ; Port D Data Register bit 7 |
.equ PD7 = 7 ; For compatibility |
; DDRD - Port D Data Direction Register |
.equ DDD0 = 0 ; Port D Data Direction Register bit 0 |
.equ DDD1 = 1 ; Port D Data Direction Register bit 1 |
.equ DDD2 = 2 ; Port D Data Direction Register bit 2 |
.equ DDD3 = 3 ; Port D Data Direction Register bit 3 |
.equ DDD4 = 4 ; Port D Data Direction Register bit 4 |
.equ DDD5 = 5 ; Port D Data Direction Register bit 5 |
.equ DDD6 = 6 ; Port D Data Direction Register bit 6 |
.equ DDD7 = 7 ; Port D Data Direction Register bit 7 |
; PIND - Port D Input Pins |
.equ PIND0 = 0 ; Port D Input Pins bit 0 |
.equ PIND1 = 1 ; Port D Input Pins bit 1 |
.equ PIND2 = 2 ; Port D Input Pins bit 2 |
.equ PIND3 = 3 ; Port D Input Pins bit 3 |
.equ PIND4 = 4 ; Port D Input Pins bit 4 |
.equ PIND5 = 5 ; Port D Input Pins bit 5 |
.equ PIND6 = 6 ; Port D Input Pins bit 6 |
.equ PIND7 = 7 ; Port D Input Pins bit 7 |
; ***** SPI ************************** |
; SPDR - SPI Data Register |
.equ SPDR0 = 0 ; SPI Data Register bit 0 |
.equ SPDR1 = 1 ; SPI Data Register bit 1 |
.equ SPDR2 = 2 ; SPI Data Register bit 2 |
.equ SPDR3 = 3 ; SPI Data Register bit 3 |
.equ SPDR4 = 4 ; SPI Data Register bit 4 |
.equ SPDR5 = 5 ; SPI Data Register bit 5 |
.equ SPDR6 = 6 ; SPI Data Register bit 6 |
.equ SPDR7 = 7 ; SPI Data Register bit 7 |
; SPSR - SPI Status Register |
.equ SPI2X = 0 ; Double SPI Speed Bit |
.equ WCOL = 6 ; Write Collision Flag |
.equ SPIF = 7 ; SPI Interrupt Flag |
; SPCR - SPI Control Register |
.equ SPR0 = 0 ; SPI Clock Rate Select 0 |
.equ SPR1 = 1 ; SPI Clock Rate Select 1 |
.equ CPHA = 2 ; Clock Phase |
.equ CPOL = 3 ; Clock polarity |
.equ MSTR = 4 ; Master/Slave Select |
.equ DORD = 5 ; Data Order |
.equ SPE = 6 ; SPI Enable |
.equ SPIE = 7 ; SPI Interrupt Enable |
; ***** EEPROM *********************** |
; EEDR - EEPROM Data Register |
.equ EEDR0 = 0 ; EEPROM Data Register bit 0 |
.equ EEDR1 = 1 ; EEPROM Data Register bit 1 |
.equ EEDR2 = 2 ; EEPROM Data Register bit 2 |
.equ EEDR3 = 3 ; EEPROM Data Register bit 3 |
.equ EEDR4 = 4 ; EEPROM Data Register bit 4 |
.equ EEDR5 = 5 ; EEPROM Data Register bit 5 |
.equ EEDR6 = 6 ; EEPROM Data Register bit 6 |
.equ EEDR7 = 7 ; EEPROM Data Register bit 7 |
; EECR - EEPROM Control Register |
.equ EERE = 0 ; EEPROM Read Enable |
.equ EEWE = 1 ; EEPROM Write Enable |
.equ EEMWE = 2 ; EEPROM Master Write Enable |
.equ EEWEE = EEMWE ; For compatibility |
.equ EERIE = 3 ; EEPROM Ready Interrupt Enable |
; ***** TIMER_COUNTER_0 ************** |
; TCCR0 - Timer/Counter Control Register |
.equ CS00 = 0 ; Clock Select 1 |
.equ CS01 = 1 ; Clock Select 1 |
.equ CS02 = 2 ; Clock Select 2 |
.equ WGM01 = 3 ; Waveform Generation Mode 1 |
.equ CTC0 = WGM01 ; For compatibility |
.equ COM00 = 4 ; Compare match Output Mode 0 |
.equ COM01 = 5 ; Compare Match Output Mode 1 |
.equ WGM00 = 6 ; Waveform Generation Mode 0 |
.equ PWM0 = WGM00 ; For compatibility |
.equ FOC0 = 7 ; Force Output Compare |
; TCNT0 - Timer/Counter Register |
.equ TCNT0_0 = 0 ; |
.equ TCNT0_1 = 1 ; |
.equ TCNT0_2 = 2 ; |
.equ TCNT0_3 = 3 ; |
.equ TCNT0_4 = 4 ; |
.equ TCNT0_5 = 5 ; |
.equ TCNT0_6 = 6 ; |
.equ TCNT0_7 = 7 ; |
; OCR0 - Output Compare Register |
.equ OCR0_0 = 0 ; |
.equ OCR0_1 = 1 ; |
.equ OCR0_2 = 2 ; |
.equ OCR0_3 = 3 ; |
.equ OCR0_4 = 4 ; |
.equ OCR0_5 = 5 ; |
.equ OCR0_6 = 6 ; |
.equ OCR0_7 = 7 ; |
; TIMSK - Timer/Counter Interrupt Mask Register |
.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable |
.equ OCIE0 = 1 ; Timer/Counter0 Output Compare Match Interrupt register |
; TIFR - Timer/Counter Interrupt Flag register |
.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag |
.equ OCF0 = 1 ; Output Compare Flag 0 |
; SFIOR - Special Function IO Register |
.equ PSR10 = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0 |
; ***** TIMER_COUNTER_1 ************** |
; TIMSK - Timer/Counter Interrupt Mask Register |
.equ TOIE1 = 2 ; Timer/Counter1 Overflow Interrupt Enable |
.equ OCIE1B = 3 ; Timer/Counter1 Output CompareB Match Interrupt Enable |
.equ OCIE1A = 4 ; Timer/Counter1 Output CompareA Match Interrupt Enable |
.equ TICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable |
; TIFR - Timer/Counter Interrupt Flag register |
.equ TOV1 = 2 ; Timer/Counter1 Overflow Flag |
.equ OCF1B = 3 ; Output Compare Flag 1B |
.equ OCF1A = 4 ; Output Compare Flag 1A |
.equ ICF1 = 5 ; Input Capture Flag 1 |
; TCCR1A - Timer/Counter1 Control Register A |
.equ WGM10 = 0 ; Waveform Generation Mode |
.equ PWM10 = WGM10 ; For compatibility |
.equ WGM11 = 1 ; Waveform Generation Mode |
.equ PWM11 = WGM11 ; For compatibility |
.equ FOC1B = 2 ; Force Output Compare 1B |
.equ FOC1A = 3 ; Force Output Compare 1A |
.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0 |
.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1 |
.equ COM1A0 = 6 ; Comparet Ouput Mode 1A, bit 0 |
.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1 |
; TCCR1B - Timer/Counter1 Control Register B |
.equ CS10 = 0 ; Prescaler source of Timer/Counter 1 |
.equ CS11 = 1 ; Prescaler source of Timer/Counter 1 |
.equ CS12 = 2 ; Prescaler source of Timer/Counter 1 |
.equ WGM12 = 3 ; Waveform Generation Mode |
.equ CTC10 = WGM12 ; For compatibility |
.equ CTC1 = WGM12 ; For compatibility |
.equ WGM13 = 4 ; Waveform Generation Mode |
.equ CTC11 = WGM13 ; For compatibility |
.equ ICES1 = 6 ; Input Capture 1 Edge Select |
.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler |
; ***** TIMER_COUNTER_2 ************** |
; TIMSK - Timer/Counter Interrupt Mask register |
.equ TOIE2 = 6 ; Timer/Counter2 Overflow Interrupt Enable |
.equ OCIE2 = 7 ; Timer/Counter2 Output Compare Match Interrupt Enable |
; TIFR - Timer/Counter Interrupt Flag Register |
.equ TOV2 = 6 ; Timer/Counter2 Overflow Flag |
.equ OCF2 = 7 ; Output Compare Flag 2 |
; TCCR2 - Timer/Counter2 Control Register |
.equ CS20 = 0 ; Clock Select bit 0 |
.equ CS21 = 1 ; Clock Select bit 1 |
.equ CS22 = 2 ; Clock Select bit 2 |
.equ WGM21 = 3 ; Waveform Generation Mode |
.equ CTC2 = WGM21 ; For compatibility |
.equ COM20 = 4 ; Compare Output Mode bit 0 |
.equ COM21 = 5 ; Compare Output Mode bit 1 |
.equ WGM20 = 6 ; Waveform Genration Mode |
.equ PWM2 = WGM20 ; For compatibility |
.equ FOC2 = 7 ; Force Output Compare |
; TCNT2 - Timer/Counter2 |
.equ TCNT2_0 = 0 ; Timer/Counter 2 bit 0 |
.equ TCNT2_1 = 1 ; Timer/Counter 2 bit 1 |
.equ TCNT2_2 = 2 ; Timer/Counter 2 bit 2 |
.equ TCNT2_3 = 3 ; Timer/Counter 2 bit 3 |
.equ TCNT2_4 = 4 ; Timer/Counter 2 bit 4 |
.equ TCNT2_5 = 5 ; Timer/Counter 2 bit 5 |
.equ TCNT2_6 = 6 ; Timer/Counter 2 bit 6 |
.equ TCNT2_7 = 7 ; Timer/Counter 2 bit 7 |
; OCR2 - Timer/Counter2 Output Compare Register |
.equ OCR2_0 = 0 ; Timer/Counter2 Output Compare Register Bit 0 |
.equ OCR2_1 = 1 ; Timer/Counter2 Output Compare Register Bit 1 |
.equ OCR2_2 = 2 ; Timer/Counter2 Output Compare Register Bit 2 |
.equ OCR2_3 = 3 ; Timer/Counter2 Output Compare Register Bit 3 |
.equ OCR2_4 = 4 ; Timer/Counter2 Output Compare Register Bit 4 |
.equ OCR2_5 = 5 ; Timer/Counter2 Output Compare Register Bit 5 |
.equ OCR2_6 = 6 ; Timer/Counter2 Output Compare Register Bit 6 |
.equ OCR2_7 = 7 ; Timer/Counter2 Output Compare Register Bit 7 |
; ASSR - Asynchronous Status Register |
.equ TCR2UB = 0 ; Timer/counter Control Register2 Update Busy |
.equ OCR2UB = 1 ; Output Compare Register2 Update Busy |
.equ TCN2UB = 2 ; Timer/Counter2 Update Busy |
.equ AS2 = 3 ; Asynchronous Timer/counter2 |
; SFIOR - Special Function IO Register |
.equ PSR2 = 1 ; Prescaler Reset Timer/Counter2 |
; ***** EXTERNAL_INTERRUPT *********** |
; GICR - General Interrupt Control Register |
.equ GIMSK = GICR ; For compatibility |
.equ IVCE = 0 ; Interrupt Vector Change Enable |
.equ IVSEL = 1 ; Interrupt Vector Select |
.equ INT2 = 5 ; External Interrupt Request 2 Enable |
.equ INT0 = 6 ; External Interrupt Request 0 Enable |
.equ INT1 = 7 ; External Interrupt Request 1 Enable |
; GIFR - General Interrupt Flag Register |
.equ INTF2 = 5 ; External Interrupt Flag 2 |
.equ INTF0 = 6 ; External Interrupt Flag 0 |
.equ INTF1 = 7 ; External Interrupt Flag 1 |
; MCUCR - General Interrupt Control Register |
.equ ISC00 = 0 ; Interrupt Sense Control 0 Bit 0 |
.equ ISC01 = 1 ; Interrupt Sense Control 0 Bit 1 |
.equ ISC10 = 2 ; Interrupt Sense Control 1 Bit 0 |
.equ ISC11 = 3 ; Interrupt Sense Control 1 Bit 1 |
; MCUCSR - MCU Control And Status Register |
.equ ISC2 = 6 ; Interrupt Sense Control 2 |
; ***** WATCHDOG ********************* |
; WDTCR - Watchdog Timer Control Register |
.equ WDTCSR = WDTCR ; For compatibility |
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 |
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 |
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 |
.equ WDE = 3 ; Watch Dog Enable |
.equ WDCE = 4 ; Watchdog Change Enable |
.equ WDTOE = WDCE ; For compatibility |
; ***** CPU ************************** |
; SREG - Status Register |
.equ SREG_C = 0 ; Carry Flag |
.equ SREG_Z = 1 ; Zero Flag |
.equ SREG_N = 2 ; Negative Flag |
.equ SREG_V = 3 ; Two's Complement Overflow Flag |
.equ SREG_S = 4 ; Sign Bit |
.equ SREG_H = 5 ; Half Carry Flag |
.equ SREG_T = 6 ; Bit Copy Storage |
.equ SREG_I = 7 ; Global Interrupt Enable |
; MCUCR - MCU Control Register |
;.equ ISC00 = 0 ; Interrupt Sense Control 0 Bit 0 |
;.equ ISC01 = 1 ; Interrupt Sense Control 0 Bit 1 |
;.equ ISC10 = 2 ; Interrupt Sense Control 1 Bit 0 |
;.equ ISC11 = 3 ; Interrupt Sense Control 1 Bit 1 |
.equ SM0 = 4 ; Sleep Mode Select |
.equ SM1 = 5 ; Sleep Mode Select |
.equ SE = 6 ; Sleep Enable |
.equ SM2 = 7 ; Sleep Mode Select |
; MCUCSR - MCU Control And Status Register |
.equ MCUSR = MCUCSR ; For compatibility |
.equ PORF = 0 ; Power-on reset flag |
.equ EXTRF = 1 ; External Reset Flag |
.equ BORF = 2 ; Brown-out Reset Flag |
.equ WDRF = 3 ; Watchdog Reset Flag |
; OSCCAL - Oscillator Calibration Value |
.equ CAL0 = 0 ; Oscillator Calibration Value Bit0 |
.equ CAL1 = 1 ; Oscillator Calibration Value Bit1 |
.equ CAL2 = 2 ; Oscillator Calibration Value Bit2 |
.equ CAL3 = 3 ; Oscillator Calibration Value Bit3 |
.equ CAL4 = 4 ; Oscillator Calibration Value Bit4 |
.equ CAL5 = 5 ; Oscillator Calibration Value Bit5 |
.equ CAL6 = 6 ; Oscillator Calibration Value Bit6 |
.equ CAL7 = 7 ; Oscillator Calibration Value Bit7 |
; SFIOR - Special Function IO Register |
.equ PUD = 2 ; Pull-up Disable |
.equ ACME = 3 ; Anlog Comparator Multiplexer Enable |
.equ ADHSM = 4 ; ADC High Speed Mode |
.equ ADTS0 = 5 ; ADC High Speed Mode |
.equ ADTS1 = 6 ; ADC Auto Trigger Source |
.equ ADTS2 = 7 ; ADC Auto Trigger Source |
; SPMCR - |
.equ SPMEN = 0 ; Store Program Memory Enable |
.equ PGERS = 1 ; Page Erase |
.equ PGWRT = 2 ; Page Write |
.equ BLBSET = 3 ; Boot Lock Bit Set |
.equ RWWSRE = 4 ; Read-While-Write Section Read Enable |
.equ RWWSB = 6 ; Read-While-Write Section Busy |
.equ SPMIE = 7 ; SPM Interrupt Enable |
; ***** LOCKSBITS ******************************************************** |
.equ LB1 = 0 ; Lock bit |
.equ LB2 = 1 ; Lock bit |
.equ BLB01 = 2 ; Boot Lock bit |
.equ BLB02 = 3 ; Boot Lock bit |
.equ BLB11 = 4 ; Boot lock bit |
.equ BLB12 = 5 ; Boot lock bit |
; ***** FUSES ************************************************************ |
; LOW fuse bits |
.equ CKSEL0 = 0 ; Select Clock Source |
.equ CKSEL1 = 1 ; Select Clock Source |
.equ CKSEL2 = 2 ; Select Clock Source |
.equ CKSEL3 = 3 ; Select Clock Source |
.equ SUT0 = 4 ; Select start-up time |
.equ SUT1 = 5 ; Select start-up time |
.equ BODEN = 6 ; Brown out detector enable |
.equ BODLEVEL = 7 ; Brown out detector trigger level |
; HIGH fuse bits |
.equ BOOTRST = 0 ; Select Reset Vector |
.equ BOOTSZ0 = 1 ; Select Boot Size |
.equ BOOTSZ1 = 2 ; Select Boot Size |
.equ EESAVE = 3 ; EEPROM memory is preserved through chip erase |
.equ CKOPT = 4 ; Oscillator Options |
.equ SPIEN = 5 ; Enable Serial programming and Data Downloading |
.equ WDTON = 6 ; Watchdog timer always on |
.equ S8535C = 7 ; AT90S4434/8535 compabillity mode |
; ***** CPU REGISTER DEFINITIONS ***************************************** |
.def XH = r27 |
.def XL = r26 |
.def YH = r29 |
.def YL = r28 |
.def ZH = r31 |
.def ZL = r30 |
; ***** DATA MEMORY DECLARATIONS ***************************************** |
.equ FLASHEND = 0x0fff ; Note: Word address |
.equ IOEND = 0x003f |
.equ SRAM_START = 0x0060 |
.equ SRAM_SIZE = 512 |
.equ RAMEND = 0x025f |
.equ XRAMEND = 0x0000 |
.equ E2END = 0x01ff |
.equ EEPROMEND = 0x01ff |
.equ EEADRBITS = 9 |
#pragma AVRPART MEMORY PROG_FLASH 8192 |
#pragma AVRPART MEMORY EEPROM 512 |
#pragma AVRPART MEMORY INT_SRAM SIZE 512 |
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60 |
; ***** BOOTLOADER DECLARATIONS ****************************************** |
.equ NRWW_START_ADDR = 0xc00 |
.equ NRWW_STOP_ADDR = 0xfff |
.equ RWW_START_ADDR = 0x0 |
.equ RWW_STOP_ADDR = 0xbff |
.equ PAGESIZE = 32 |
.equ FIRSTBOOTSTART = 0xf80 |
.equ SECONDBOOTSTART = 0xf00 |
.equ THIRDBOOTSTART = 0xe00 |
.equ FOURTHBOOTSTART = 0xc00 |
.equ SMALLBOOTSTART = FIRSTBOOTSTART |
.equ LARGEBOOTSTART = FOURTHBOOTSTART |
; ***** INTERRUPT VECTORS ************************************************ |
.equ INT0addr = 0x0001 ; External Interrupt 0 |
.equ INT1addr = 0x0002 ; External Interrupt 1 |
.equ OC2addr = 0x0003 ; Timer/Counter2 Compare Match |
.equ OVF2addr = 0x0004 ; Timer/Counter2 Overflow |
.equ ICP1addr = 0x0005 ; Timer/Counter1 Capture Event |
.equ OC1Aaddr = 0x0006 ; Timer/Counter1 Compare Match A |
.equ OC1Baddr = 0x0007 ; Timer/Counter1 Compare Match B |
.equ OVF1addr = 0x0008 ; Timer/Counter1 Overflow |
.equ OVF0addr = 0x0009 ; Timer/Counter0 Overflow |
.equ SPIaddr = 0x000a ; SPI Serial Transfer Complete |
.equ URXCaddr = 0x000b ; USART, RX Complete |
.equ UDREaddr = 0x000c ; USART Data Register Empty |
.equ UTXCaddr = 0x000d ; USART, TX Complete |
.equ ADCCaddr = 0x000e ; ADC Conversion Complete |
.equ ERDYaddr = 0x000f ; EEPROM Ready |
.equ ACIaddr = 0x0010 ; Analog Comparator |
.equ TWIaddr = 0x0011 ; Two-wire Serial Interface |
.equ INT2addr = 0x0012 ; External Interrupt Request 2 |
.equ OC0addr = 0x0013 ; TimerCounter0 Compare Match |
.equ SPMRaddr = 0x0014 ; Store Program Memory Read |
.equ INT_VECTORS_SIZE = 21 ; size in words |
#pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED break |
#endif /* _M8535DEF_INC_ */ |
; ***** END OF FILE ****************************************************** |
/contrib/toolchain/avra/includes/m88def.inc |
---|
0,0 → 1,958 |
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** |
;***** Created: 2005-01-11 10:31 ******* Source: ATmega88.xml ************ |
;************************************************************************* |
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y |
;* |
;* Number : AVR000 |
;* File Name : "m88def.inc" |
;* Title : Register/Bit Definitions for the ATmega88 |
;* Date : 2005-01-11 |
;* Version : 2.14 |
;* Support E-mail : avr@atmel.com |
;* Target MCU : ATmega88 |
;* |
;* DESCRIPTION |
;* When including this file in the assembly program file, all I/O register |
;* names and I/O register bit names appearing in the data book can be used. |
;* In addition, the six registers forming the three data pointers X, Y and |
;* Z have been assigned names XL - ZH. Highest RAM address for Internal |
;* SRAM is also defined |
;* |
;* The Register names are represented by their hexadecimal address. |
;* |
;* The Register Bit names are represented by their bit number (0-7). |
;* |
;* Please observe the difference in using the bit names with instructions |
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" |
;* (skip if bit in register set/cleared). The following example illustrates |
;* this: |
;* |
;* in r16,PORTB ;read PORTB latch |
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) |
;* out PORTB,r16 ;output to PORTB |
;* |
;* in r16,TIFR ;read the Timer Interrupt Flag Register |
;* sbrc r16,TOV0 ;test the overflow flag (use bit#) |
;* rjmp TOV0_is_set ;jump if set |
;* ... ;otherwise do something else |
;************************************************************************* |
#ifndef _M88DEF_INC_ |
#define _M88DEF_INC_ |
#pragma partinc 0 |
; ***** SPECIFY DEVICE *************************************************** |
.device ATmega88 |
#pragma AVRPART ADMIN PART_NAME ATmega88 |
.equ SIGNATURE_000 = 0x1e |
.equ SIGNATURE_001 = 0x93 |
.equ SIGNATURE_002 = 0x0a |
#pragma AVRPART CORE CORE_VERSION V2E |
; ***** I/O REGISTER DEFINITIONS ***************************************** |
; NOTE: |
; Definitions marked "MEMORY MAPPED"are extended I/O ports |
; and cannot be used with IN/OUT instructions |
.equ UDR0 = 0xc6 ; MEMORY MAPPED |
.equ UBRR0H = 0xc5 ; MEMORY MAPPED |
.equ UBRR0L = 0xc4 ; MEMORY MAPPED |
.equ UCSR0C = 0xc2 ; MEMORY MAPPED |
.equ UCSR0B = 0xc1 ; MEMORY MAPPED |
.equ UCSR0A = 0xc0 ; MEMORY MAPPED |
.equ TWAMR = 0xbd ; MEMORY MAPPED |
.equ TWCR = 0xbc ; MEMORY MAPPED |
.equ TWDR = 0xbb ; MEMORY MAPPED |
.equ TWAR = 0xba ; MEMORY MAPPED |
.equ TWSR = 0xb9 ; MEMORY MAPPED |
.equ TWBR = 0xb8 ; MEMORY MAPPED |
.equ ASSR = 0xb6 ; MEMORY MAPPED |
.equ OCR2B = 0xb4 ; MEMORY MAPPED |
.equ OCR2A = 0xb3 ; MEMORY MAPPED |
.equ TCNT2 = 0xb2 ; MEMORY MAPPED |
.equ TCCR2B = 0xb1 ; MEMORY MAPPED |
.equ TCCR2A = 0xb0 ; MEMORY MAPPED |
.equ OCR1BH = 0x8b ; MEMORY MAPPED |
.equ OCR1BL = 0x8a ; MEMORY MAPPED |
.equ OCR1AH = 0x89 ; MEMORY MAPPED |
.equ OCR1AL = 0x88 ; MEMORY MAPPED |
.equ ICR1H = 0x87 ; MEMORY MAPPED |
.equ ICR1L = 0x86 ; MEMORY MAPPED |
.equ TCNT1H = 0x85 ; MEMORY MAPPED |
.equ TCNT1L = 0x84 ; MEMORY MAPPED |
.equ TCCR1C = 0x82 ; MEMORY MAPPED |
.equ TCCR1B = 0x81 ; MEMORY MAPPED |
.equ TCCR1A = 0x80 ; MEMORY MAPPED |
.equ DIDR1 = 0x7f ; MEMORY MAPPED |
.equ DIDR0 = 0x7e ; MEMORY MAPPED |
.equ ADMUX = 0x7c ; MEMORY MAPPED |
.equ ADCSRB = 0x7b ; MEMORY MAPPED |
.equ ADCSRA = 0x7a ; MEMORY MAPPED |
.equ ADCH = 0x79 ; MEMORY MAPPED |
.equ ADCL = 0x78 ; MEMORY MAPPED |
.equ TIMSK2 = 0x70 ; MEMORY MAPPED |
.equ TIMSK1 = 0x6f ; MEMORY MAPPED |
.equ TIMSK0 = 0x6e ; MEMORY MAPPED |
.equ PCMSK2 = 0x6d ; MEMORY MAPPED |
.equ PCMSK1 = 0x6c ; MEMORY MAPPED |
.equ PCMSK0 = 0x6b ; MEMORY MAPPED |
.equ EICRA = 0x69 ; MEMORY MAPPED |
.equ PCICR = 0x68 ; MEMORY MAPPED |
.equ OSCCAL = 0x66 ; MEMORY MAPPED |
.equ PRR = 0x64 ; MEMORY MAPPED |
.equ CLKPR = 0x61 ; MEMORY MAPPED |
.equ WDTCSR = 0x60 ; MEMORY MAPPED |
.equ SREG = 0x3f |
.equ SPH = 0x3e |
.equ SPL = 0x3d |
.equ SPMCSR = 0x37 |
.equ MCUCR = 0x35 |
.equ MCUSR = 0x34 |
.equ SMCR = 0x33 |
.equ ACSR = 0x30 |
.equ SPDR = 0x2e |
.equ SPSR = 0x2d |
.equ SPCR = 0x2c |
.equ GPIOR2 = 0x2b |
.equ GPIOR1 = 0x2a |
.equ OCR0B = 0x28 |
.equ OCR0A = 0x27 |
.equ TCNT0 = 0x26 |
.equ TCCR0B = 0x25 |
.equ TCCR0A = 0x24 |
.equ GTCCR = 0x23 |
.equ EEARH = 0x22 |
.equ EEARL = 0x21 |
.equ EEDR = 0x20 |
.equ EECR = 0x1f |
.equ GPIOR0 = 0x1e |
.equ EIMSK = 0x1d |
.equ EIFR = 0x1c |
.equ PCIFR = 0x1b |
.equ TIFR2 = 0x17 |
.equ TIFR1 = 0x16 |
.equ TIFR0 = 0x15 |
.equ PORTD = 0x0b |
.equ DDRD = 0x0a |
.equ PIND = 0x09 |
.equ PORTC = 0x08 |
.equ DDRC = 0x07 |
.equ PINC = 0x06 |
.equ PORTB = 0x05 |
.equ DDRB = 0x04 |
.equ PINB = 0x03 |
; ***** BIT DEFINITIONS ************************************************** |
; ***** USART0 *********************** |
; UDR0 - USART I/O Data Register |
.equ UDR0_0 = 0 ; USART I/O Data Register bit 0 |
.equ UDR0_1 = 1 ; USART I/O Data Register bit 1 |
.equ UDR0_2 = 2 ; USART I/O Data Register bit 2 |
.equ UDR0_3 = 3 ; USART I/O Data Register bit 3 |
.equ UDR0_4 = 4 ; USART I/O Data Register bit 4 |
.equ UDR0_5 = 5 ; USART I/O Data Register bit 5 |
.equ UDR0_6 = 6 ; USART I/O Data Register bit 6 |
.equ UDR0_7 = 7 ; USART I/O Data Register bit 7 |
; UCSR0A - USART Control and Status Register A |
.equ MPCM0 = 0 ; Multi-processor Communication Mode |
.equ U2X0 = 1 ; Double the USART transmission speed |
.equ UPE0 = 2 ; Parity Error |
.equ DOR0 = 3 ; Data overRun |
.equ FE0 = 4 ; Framing Error |
.equ UDRE0 = 5 ; USART Data Register Empty |
.equ TXC0 = 6 ; USART Transmitt Complete |
.equ RXC0 = 7 ; USART Receive Complete |
; UCSR0B - USART Control and Status Register B |
.equ TXB80 = 0 ; Transmit Data Bit 8 |
.equ RXB80 = 1 ; Receive Data Bit 8 |
.equ UCSZ02 = 2 ; Character Size |
.equ TXEN0 = 3 ; Transmitter Enable |
.equ RXEN0 = 4 ; Receiver Enable |
.equ UDRIE0 = 5 ; USART Data register Empty Interrupt Enable |
.equ TXCIE0 = 6 ; TX Complete Interrupt Enable |
.equ RXCIE0 = 7 ; RX Complete Interrupt Enable |
; UCSR0C - USART Control and Status Register C |
.equ UCPOL0 = 0 ; Clock Polarity |
.equ UCSZ00 = 1 ; Character Size |
.equ UCPHA0 = UCSZ00 ; For compatibility |
.equ UCSZ01 = 2 ; Character Size |
.equ UDORD0 = UCSZ01 ; For compatibility |
.equ USBS0 = 3 ; Stop Bit Select |
.equ UPM00 = 4 ; Parity Mode Bit 0 |
.equ UPM01 = 5 ; Parity Mode Bit 1 |
.equ UMSEL00 = 6 ; USART Mode Select |
.equ UMSEL0 = UMSEL00 ; For compatibility |
.equ UMSEL01 = 7 ; USART Mode Select |
.equ UMSEL1 = UMSEL01 ; For compatibility |
; ***** TWI ************************** |
; TWAMR - TWI (Slave) Address Mask Register |
.equ TWAM0 = 1 ; |
.equ TWAMR0 = TWAM0 ; For compatibility |
.equ TWAM1 = 2 ; |
.equ TWAMR1 = TWAM1 ; For compatibility |
.equ TWAM2 = 3 ; |
.equ TWAMR2 = TWAM2 ; For compatibility |
.equ TWAM3 = 4 ; |
.equ TWAMR3 = TWAM3 ; For compatibility |
.equ TWAM4 = 5 ; |
.equ TWAMR4 = TWAM4 ; For compatibility |
.equ TWAM5 = 6 ; |
.equ TWAMR5 = TWAM5 ; For compatibility |
.equ TWAM6 = 7 ; |
.equ TWAMR6 = TWAM6 ; For compatibility |
; TWBR - TWI Bit Rate register |
.equ TWBR0 = 0 ; |
.equ TWBR1 = 1 ; |
.equ TWBR2 = 2 ; |
.equ TWBR3 = 3 ; |
.equ TWBR4 = 4 ; |
.equ TWBR5 = 5 ; |
.equ TWBR6 = 6 ; |
.equ TWBR7 = 7 ; |
; TWCR - TWI Control Register |
.equ TWIE = 0 ; TWI Interrupt Enable |
.equ TWEN = 2 ; TWI Enable Bit |
.equ TWWC = 3 ; TWI Write Collition Flag |
.equ TWSTO = 4 ; TWI Stop Condition Bit |
.equ TWSTA = 5 ; TWI Start Condition Bit |
.equ TWEA = 6 ; TWI Enable Acknowledge Bit |
.equ TWINT = 7 ; TWI Interrupt Flag |
; TWSR - TWI Status Register |
.equ TWPS0 = 0 ; TWI Prescaler |
.equ TWPS1 = 1 ; TWI Prescaler |
.equ TWS3 = 3 ; TWI Status |
.equ TWS4 = 4 ; TWI Status |
.equ TWS5 = 5 ; TWI Status |
.equ TWS6 = 6 ; TWI Status |
.equ TWS7 = 7 ; TWI Status |
; TWDR - TWI Data register |
.equ TWD0 = 0 ; TWI Data Register Bit 0 |
.equ TWD1 = 1 ; TWI Data Register Bit 1 |
.equ TWD2 = 2 ; TWI Data Register Bit 2 |
.equ TWD3 = 3 ; TWI Data Register Bit 3 |
.equ TWD4 = 4 ; TWI Data Register Bit 4 |
.equ TWD5 = 5 ; TWI Data Register Bit 5 |
.equ TWD6 = 6 ; TWI Data Register Bit 6 |
.equ TWD7 = 7 ; TWI Data Register Bit 7 |
; TWAR - TWI (Slave) Address register |
.equ TWGCE = 0 ; TWI General Call Recognition Enable Bit |
.equ TWA0 = 1 ; TWI (Slave) Address register Bit 0 |
.equ TWA1 = 2 ; TWI (Slave) Address register Bit 1 |
.equ TWA2 = 3 ; TWI (Slave) Address register Bit 2 |
.equ TWA3 = 4 ; TWI (Slave) Address register Bit 3 |
.equ TWA4 = 5 ; TWI (Slave) Address register Bit 4 |
.equ TWA5 = 6 ; TWI (Slave) Address register Bit 5 |
.equ TWA6 = 7 ; TWI (Slave) Address register Bit 6 |
; ***** TIMER_COUNTER_1 ************** |
; TIMSK1 - Timer/Counter Interrupt Mask Register |
.equ TOIE1 = 0 ; Timer/Counter1 Overflow Interrupt Enable |
.equ OCIE1A = 1 ; Timer/Counter1 Output CompareA Match Interrupt Enable |
.equ OCIE1B = 2 ; Timer/Counter1 Output CompareB Match Interrupt Enable |
.equ ICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable |
; TIFR1 - Timer/Counter Interrupt Flag register |
.equ TOV1 = 0 ; Timer/Counter1 Overflow Flag |
.equ OCF1A = 1 ; Output Compare Flag 1A |
.equ OCF1B = 2 ; Output Compare Flag 1B |
.equ ICF1 = 5 ; Input Capture Flag 1 |
; TCCR1A - Timer/Counter1 Control Register A |
.equ WGM10 = 0 ; Waveform Generation Mode |
.equ WGM11 = 1 ; Waveform Generation Mode |
.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0 |
.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1 |
.equ COM1A0 = 6 ; Comparet Ouput Mode 1A, bit 0 |
.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1 |
; TCCR1B - Timer/Counter1 Control Register B |
.equ CS10 = 0 ; Prescaler source of Timer/Counter 1 |
.equ CS11 = 1 ; Prescaler source of Timer/Counter 1 |
.equ CS12 = 2 ; Prescaler source of Timer/Counter 1 |
.equ WGM12 = 3 ; Waveform Generation Mode |
.equ WGM13 = 4 ; Waveform Generation Mode |
.equ ICES1 = 6 ; Input Capture 1 Edge Select |
.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler |
; TCCR1C - Timer/Counter1 Control Register C |
.equ FOC1B = 6 ; |
.equ FOC1A = 7 ; |
; GTCCR - General Timer/Counter Control Register |
.equ PSRSYNC = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0 |
.equ TSM = 7 ; Timer/Counter Synchronization Mode |
; ***** TIMER_COUNTER_2 ************** |
; TIMSK2 - Timer/Counter Interrupt Mask register |
.equ TOIE2 = 0 ; Timer/Counter2 Overflow Interrupt Enable |
.equ TOIE2A = TOIE2 ; For compatibility |
.equ OCIE2A = 1 ; Timer/Counter2 Output Compare Match A Interrupt Enable |
.equ OCIE2B = 2 ; Timer/Counter2 Output Compare Match B Interrupt Enable |
; TIFR2 - Timer/Counter Interrupt Flag Register |
.equ TOV2 = 0 ; Timer/Counter2 Overflow Flag |
.equ OCF2A = 1 ; Output Compare Flag 2A |
.equ OCF2B = 2 ; Output Compare Flag 2B |
; TCCR2A - Timer/Counter2 Control Register A |
.equ WGM20 = 0 ; Waveform Genration Mode |
.equ WGM21 = 1 ; Waveform Genration Mode |
.equ COM2B0 = 4 ; Compare Output Mode bit 0 |
.equ COM2B1 = 5 ; Compare Output Mode bit 1 |
.equ COM2A0 = 6 ; Compare Output Mode bit 1 |
.equ COM2A1 = 7 ; Compare Output Mode bit 1 |
; TCCR2B - Timer/Counter2 Control Register B |
.equ CS20 = 0 ; Clock Select bit 0 |
.equ CS21 = 1 ; Clock Select bit 1 |
.equ CS22 = 2 ; Clock Select bit 2 |
.equ WGM22 = 3 ; Waveform Generation Mode |
.equ FOC2B = 6 ; Force Output Compare B |
.equ FOC2A = 7 ; Force Output Compare A |
; TCNT2 - Timer/Counter2 |
.equ TCNT2_0 = 0 ; Timer/Counter 2 bit 0 |
.equ TCNT2_1 = 1 ; Timer/Counter 2 bit 1 |
.equ TCNT2_2 = 2 ; Timer/Counter 2 bit 2 |
.equ TCNT2_3 = 3 ; Timer/Counter 2 bit 3 |
.equ TCNT2_4 = 4 ; Timer/Counter 2 bit 4 |
.equ TCNT2_5 = 5 ; Timer/Counter 2 bit 5 |
.equ TCNT2_6 = 6 ; Timer/Counter 2 bit 6 |
.equ TCNT2_7 = 7 ; Timer/Counter 2 bit 7 |
; OCR2A - Timer/Counter2 Output Compare Register A |
.equ OCR2_0 = 0 ; Timer/Counter2 Output Compare Register Bit 0 |
.equ OCR2_1 = 1 ; Timer/Counter2 Output Compare Register Bit 1 |
.equ OCR2_2 = 2 ; Timer/Counter2 Output Compare Register Bit 2 |
.equ OCR2_3 = 3 ; Timer/Counter2 Output Compare Register Bit 3 |
.equ OCR2_4 = 4 ; Timer/Counter2 Output Compare Register Bit 4 |
.equ OCR2_5 = 5 ; Timer/Counter2 Output Compare Register Bit 5 |
.equ OCR2_6 = 6 ; Timer/Counter2 Output Compare Register Bit 6 |
.equ OCR2_7 = 7 ; Timer/Counter2 Output Compare Register Bit 7 |
; OCR2B - Timer/Counter2 Output Compare Register B |
;.equ OCR2_0 = 0 ; Timer/Counter2 Output Compare Register Bit 0 |
;.equ OCR2_1 = 1 ; Timer/Counter2 Output Compare Register Bit 1 |
;.equ OCR2_2 = 2 ; Timer/Counter2 Output Compare Register Bit 2 |
;.equ OCR2_3 = 3 ; Timer/Counter2 Output Compare Register Bit 3 |
;.equ OCR2_4 = 4 ; Timer/Counter2 Output Compare Register Bit 4 |
;.equ OCR2_5 = 5 ; Timer/Counter2 Output Compare Register Bit 5 |
;.equ OCR2_6 = 6 ; Timer/Counter2 Output Compare Register Bit 6 |
;.equ OCR2_7 = 7 ; Timer/Counter2 Output Compare Register Bit 7 |
; ASSR - Asynchronous Status Register |
.equ TCR2BUB = 0 ; Timer/Counter Control Register2 Update Busy |
.equ TCR2AUB = 1 ; Timer/Counter Control Register2 Update Busy |
.equ OCR2BUB = 2 ; Output Compare Register 2 Update Busy |
.equ OCR2AUB = 3 ; Output Compare Register2 Update Busy |
.equ TCN2UB = 4 ; Timer/Counter2 Update Busy |
.equ AS2 = 5 ; Asynchronous Timer/Counter2 |
.equ EXCLK = 6 ; Enable External Clock Input |
; GTCCR - General Timer Counter Control register |
.equ PSRASY = 1 ; Prescaler Reset Timer/Counter2 |
.equ PSR2 = PSRASY ; For compatibility |
;.equ TSM = 7 ; Timer/Counter Synchronization Mode |
; ***** AD_CONVERTER ***************** |
; ADMUX - The ADC multiplexer Selection Register |
.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits |
.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits |
.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits |
.equ MUX3 = 3 ; Analog Channel and Gain Selection Bits |
.equ ADLAR = 5 ; Left Adjust Result |
.equ REFS0 = 6 ; Reference Selection Bit 0 |
.equ REFS1 = 7 ; Reference Selection Bit 1 |
; ADCSRA - The ADC Control and Status register A |
.equ ADPS0 = 0 ; ADC Prescaler Select Bits |
.equ ADPS1 = 1 ; ADC Prescaler Select Bits |
.equ ADPS2 = 2 ; ADC Prescaler Select Bits |
.equ ADIE = 3 ; ADC Interrupt Enable |
.equ ADIF = 4 ; ADC Interrupt Flag |
.equ ADATE = 5 ; ADC Auto Trigger Enable |
.equ ADSC = 6 ; ADC Start Conversion |
.equ ADEN = 7 ; ADC Enable |
; ADCSRB - The ADC Control and Status register B |
.equ ADTS0 = 0 ; ADC Auto Trigger Source bit 0 |
.equ ADTS1 = 1 ; ADC Auto Trigger Source bit 1 |
.equ ADTS2 = 2 ; ADC Auto Trigger Source bit 2 |
.equ ACME = 6 ; |
; ADCH - ADC Data Register High Byte |
.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0 |
.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1 |
.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2 |
.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3 |
.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4 |
.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5 |
.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6 |
.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7 |
; ADCL - ADC Data Register Low Byte |
.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0 |
.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1 |
.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2 |
.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3 |
.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4 |
.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5 |
.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6 |
.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7 |
; DIDR0 - Digital Input Disable Register |
.equ ADC0D = 0 ; |
.equ ADC1D = 1 ; |
.equ ADC2D = 2 ; |
.equ ADC3D = 3 ; |
.equ ADC4D = 4 ; |
.equ ADC5D = 5 ; |
; ***** ANALOG_COMPARATOR ************ |
; ACSR - Analog Comparator Control And Status Register |
.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 |
.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 |
.equ ACIC = 2 ; |
.equ ACIE = 3 ; Analog Comparator Interrupt Enable |
.equ ACI = 4 ; Analog Comparator Interrupt Flag |
.equ ACO = 5 ; Analog Compare Output |
.equ ACBG = 6 ; Analog Comparator Bandgap Select |
.equ ACD = 7 ; Analog Comparator Disable |
; DIDR1 - Digital Input Disable Register 1 |
.equ AIN0D = 0 ; AIN0 Digital Input Disable |
.equ AIN1D = 1 ; AIN1 Digital Input Disable |
; ***** PORTB ************************ |
; PORTB - Port B Data Register |
.equ PORTB0 = 0 ; Port B Data Register bit 0 |
.equ PB0 = 0 ; For compatibility |
.equ PORTB1 = 1 ; Port B Data Register bit 1 |
.equ PB1 = 1 ; For compatibility |
.equ PORTB2 = 2 ; Port B Data Register bit 2 |
.equ PB2 = 2 ; For compatibility |
.equ PORTB3 = 3 ; Port B Data Register bit 3 |
.equ PB3 = 3 ; For compatibility |
.equ PORTB4 = 4 ; Port B Data Register bit 4 |
.equ PB4 = 4 ; For compatibility |
.equ PORTB5 = 5 ; Port B Data Register bit 5 |
.equ PB5 = 5 ; For compatibility |
.equ PORTB6 = 6 ; Port B Data Register bit 6 |
.equ PB6 = 6 ; For compatibility |
.equ PORTB7 = 7 ; Port B Data Register bit 7 |
.equ PB7 = 7 ; For compatibility |
; DDRB - Port B Data Direction Register |
.equ DDB0 = 0 ; Port B Data Direction Register bit 0 |
.equ DDB1 = 1 ; Port B Data Direction Register bit 1 |
.equ DDB2 = 2 ; Port B Data Direction Register bit 2 |
.equ DDB3 = 3 ; Port B Data Direction Register bit 3 |
.equ DDB4 = 4 ; Port B Data Direction Register bit 4 |
.equ DDB5 = 5 ; Port B Data Direction Register bit 5 |
.equ DDB6 = 6 ; Port B Data Direction Register bit 6 |
.equ DDB7 = 7 ; Port B Data Direction Register bit 7 |
; PINB - Port B Input Pins |
.equ PINB0 = 0 ; Port B Input Pins bit 0 |
.equ PINB1 = 1 ; Port B Input Pins bit 1 |
.equ PINB2 = 2 ; Port B Input Pins bit 2 |
.equ PINB3 = 3 ; Port B Input Pins bit 3 |
.equ PINB4 = 4 ; Port B Input Pins bit 4 |
.equ PINB5 = 5 ; Port B Input Pins bit 5 |
.equ PINB6 = 6 ; Port B Input Pins bit 6 |
.equ PINB7 = 7 ; Port B Input Pins bit 7 |
; ***** PORTC ************************ |
; PORTC - Port C Data Register |
.equ PORTC0 = 0 ; Port C Data Register bit 0 |
.equ PC0 = 0 ; For compatibility |
.equ PORTC1 = 1 ; Port C Data Register bit 1 |
.equ PC1 = 1 ; For compatibility |
.equ PORTC2 = 2 ; Port C Data Register bit 2 |
.equ PC2 = 2 ; For compatibility |
.equ PORTC3 = 3 ; Port C Data Register bit 3 |
.equ PC3 = 3 ; For compatibility |
.equ PORTC4 = 4 ; Port C Data Register bit 4 |
.equ PC4 = 4 ; For compatibility |
.equ PORTC5 = 5 ; Port C Data Register bit 5 |
.equ PC5 = 5 ; For compatibility |
.equ PORTC6 = 6 ; Port C Data Register bit 6 |
.equ PC6 = 6 ; For compatibility |
; DDRC - Port C Data Direction Register |
.equ DDC0 = 0 ; Port C Data Direction Register bit 0 |
.equ DDC1 = 1 ; Port C Data Direction Register bit 1 |
.equ DDC2 = 2 ; Port C Data Direction Register bit 2 |
.equ DDC3 = 3 ; Port C Data Direction Register bit 3 |
.equ DDC4 = 4 ; Port C Data Direction Register bit 4 |
.equ DDC5 = 5 ; Port C Data Direction Register bit 5 |
.equ DDC6 = 6 ; Port C Data Direction Register bit 6 |
; PINC - Port C Input Pins |
.equ PINC0 = 0 ; Port C Input Pins bit 0 |
.equ PINC1 = 1 ; Port C Input Pins bit 1 |
.equ PINC2 = 2 ; Port C Input Pins bit 2 |
.equ PINC3 = 3 ; Port C Input Pins bit 3 |
.equ PINC4 = 4 ; Port C Input Pins bit 4 |
.equ PINC5 = 5 ; Port C Input Pins bit 5 |
.equ PINC6 = 6 ; Port C Input Pins bit 6 |
; ***** PORTD ************************ |
; PORTD - Port D Data Register |
.equ PORTD0 = 0 ; Port D Data Register bit 0 |
.equ PD0 = 0 ; For compatibility |
.equ PORTD1 = 1 ; Port D Data Register bit 1 |
.equ PD1 = 1 ; For compatibility |
.equ PORTD2 = 2 ; Port D Data Register bit 2 |
.equ PD2 = 2 ; For compatibility |
.equ PORTD3 = 3 ; Port D Data Register bit 3 |
.equ PD3 = 3 ; For compatibility |
.equ PORTD4 = 4 ; Port D Data Register bit 4 |
.equ PD4 = 4 ; For compatibility |
.equ PORTD5 = 5 ; Port D Data Register bit 5 |
.equ PD5 = 5 ; For compatibility |
.equ PORTD6 = 6 ; Port D Data Register bit 6 |
.equ PD6 = 6 ; For compatibility |
.equ PORTD7 = 7 ; Port D Data Register bit 7 |
.equ PD7 = 7 ; For compatibility |
; DDRD - Port D Data Direction Register |
.equ DDD0 = 0 ; Port D Data Direction Register bit 0 |
.equ DDD1 = 1 ; Port D Data Direction Register bit 1 |
.equ DDD2 = 2 ; Port D Data Direction Register bit 2 |
.equ DDD3 = 3 ; Port D Data Direction Register bit 3 |
.equ DDD4 = 4 ; Port D Data Direction Register bit 4 |
.equ DDD5 = 5 ; Port D Data Direction Register bit 5 |
.equ DDD6 = 6 ; Port D Data Direction Register bit 6 |
.equ DDD7 = 7 ; Port D Data Direction Register bit 7 |
; PIND - Port D Input Pins |
.equ PIND0 = 0 ; Port D Input Pins bit 0 |
.equ PIND1 = 1 ; Port D Input Pins bit 1 |
.equ PIND2 = 2 ; Port D Input Pins bit 2 |
.equ PIND3 = 3 ; Port D Input Pins bit 3 |
.equ PIND4 = 4 ; Port D Input Pins bit 4 |
.equ PIND5 = 5 ; Port D Input Pins bit 5 |
.equ PIND6 = 6 ; Port D Input Pins bit 6 |
.equ PIND7 = 7 ; Port D Input Pins bit 7 |
; ***** TIMER_COUNTER_0 ************** |
; TIMSK0 - Timer/Counter0 Interrupt Mask Register |
.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable |
.equ OCIE0A = 1 ; Timer/Counter0 Output Compare Match A Interrupt Enable |
.equ OCIE0B = 2 ; Timer/Counter0 Output Compare Match B Interrupt Enable |
; TIFR0 - Timer/Counter0 Interrupt Flag register |
.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag |
.equ OCF0A = 1 ; Timer/Counter0 Output Compare Flag 0A |
.equ OCF0B = 2 ; Timer/Counter0 Output Compare Flag 0B |
; TCCR0A - Timer/Counter Control Register A |
.equ WGM00 = 0 ; Waveform Generation Mode |
.equ WGM01 = 1 ; Waveform Generation Mode |
.equ COM0B0 = 4 ; Compare Output Mode, Fast PWm |
.equ COM0B1 = 5 ; Compare Output Mode, Fast PWm |
.equ COM0A0 = 6 ; Compare Output Mode, Phase Correct PWM Mode |
.equ COM0A1 = 7 ; Compare Output Mode, Phase Correct PWM Mode |
; TCCR0B - Timer/Counter Control Register B |
.equ CS00 = 0 ; Clock Select |
.equ CS01 = 1 ; Clock Select |
.equ CS02 = 2 ; Clock Select |
.equ WGM02 = 3 ; |
.equ FOC0B = 6 ; Force Output Compare B |
.equ FOC0A = 7 ; Force Output Compare A |
; TCNT0 - Timer/Counter0 |
.equ TCNT0_0 = 0 ; |
.equ TCNT0_1 = 1 ; |
.equ TCNT0_2 = 2 ; |
.equ TCNT0_3 = 3 ; |
.equ TCNT0_4 = 4 ; |
.equ TCNT0_5 = 5 ; |
.equ TCNT0_6 = 6 ; |
.equ TCNT0_7 = 7 ; |
; OCR0A - Timer/Counter0 Output Compare Register |
.equ OCROA_0 = 0 ; |
.equ OCROA_1 = 1 ; |
.equ OCROA_2 = 2 ; |
.equ OCROA_3 = 3 ; |
.equ OCROA_4 = 4 ; |
.equ OCROA_5 = 5 ; |
.equ OCROA_6 = 6 ; |
.equ OCROA_7 = 7 ; |
; OCR0B - Timer/Counter0 Output Compare Register |
.equ OCR0B_0 = 0 ; |
.equ OCR0B_1 = 1 ; |
.equ OCR0B_2 = 2 ; |
.equ OCR0B_3 = 3 ; |
.equ OCR0B_4 = 4 ; |
.equ OCR0B_5 = 5 ; |
.equ OCR0B_6 = 6 ; |
.equ OCR0B_7 = 7 ; |
; GTCCR - General Timer/Counter Control Register |
;.equ PSRSYNC = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0 |
.equ PSR10 = PSRSYNC ; For compatibility |
;.equ TSM = 7 ; Timer/Counter Synchronization Mode |
; ***** EXTERNAL_INTERRUPT *********** |
; EICRA - External Interrupt Control Register |
.equ ISC00 = 0 ; External Interrupt Sense Control 0 Bit 0 |
.equ ISC01 = 1 ; External Interrupt Sense Control 0 Bit 1 |
.equ ISC10 = 2 ; External Interrupt Sense Control 1 Bit 0 |
.equ ISC11 = 3 ; External Interrupt Sense Control 1 Bit 1 |
; EIMSK - External Interrupt Mask Register |
.equ INT0 = 0 ; External Interrupt Request 0 Enable |
.equ INT1 = 1 ; External Interrupt Request 1 Enable |
; EIFR - External Interrupt Flag Register |
.equ INTF0 = 0 ; External Interrupt Flag 0 |
.equ INTF1 = 1 ; External Interrupt Flag 1 |
; PCMSK2 - Pin Change Mask Register 2 |
.equ PCINT16 = 0 ; Pin Change Enable Mask 16 |
.equ PCINT17 = 1 ; Pin Change Enable Mask 17 |
.equ PCINT18 = 2 ; Pin Change Enable Mask 18 |
.equ PCINT19 = 3 ; Pin Change Enable Mask 19 |
.equ PCINT20 = 4 ; Pin Change Enable Mask 20 |
.equ PCINT21 = 5 ; Pin Change Enable Mask 21 |
.equ PCINT22 = 6 ; Pin Change Enable Mask 22 |
.equ PCINT23 = 7 ; Pin Change Enable Mask 23 |
; PCMSK1 - Pin Change Mask Register 1 |
.equ PCINT8 = 0 ; Pin Change Enable Mask 8 |
.equ PCINT9 = 1 ; Pin Change Enable Mask 9 |
.equ PCINT10 = 2 ; Pin Change Enable Mask 10 |
.equ PCINT11 = 3 ; Pin Change Enable Mask 11 |
.equ PCINT12 = 4 ; Pin Change Enable Mask 12 |
.equ PCINT13 = 5 ; Pin Change Enable Mask 13 |
.equ PCINT14 = 6 ; Pin Change Enable Mask 14 |
; PCMSK0 - Pin Change Mask Register 0 |
.equ PCINT0 = 0 ; Pin Change Enable Mask 0 |
.equ PCINT1 = 1 ; Pin Change Enable Mask 1 |
.equ PCINT2 = 2 ; Pin Change Enable Mask 2 |
.equ PCINT3 = 3 ; Pin Change Enable Mask 3 |
.equ PCINT4 = 4 ; Pin Change Enable Mask 4 |
.equ PCINT5 = 5 ; Pin Change Enable Mask 5 |
.equ PCINT6 = 6 ; Pin Change Enable Mask 6 |
.equ PCINT7 = 7 ; Pin Change Enable Mask 7 |
; PCIFR - Pin Change Interrupt Flag Register |
.equ PCIF0 = 0 ; Pin Change Interrupt Flag 0 |
.equ PCIF1 = 1 ; Pin Change Interrupt Flag 1 |
.equ PCIF2 = 2 ; Pin Change Interrupt Flag 2 |
; ***** SPI ************************** |
; SPDR - SPI Data Register |
.equ SPDR0 = 0 ; SPI Data Register bit 0 |
.equ SPDR1 = 1 ; SPI Data Register bit 1 |
.equ SPDR2 = 2 ; SPI Data Register bit 2 |
.equ SPDR3 = 3 ; SPI Data Register bit 3 |
.equ SPDR4 = 4 ; SPI Data Register bit 4 |
.equ SPDR5 = 5 ; SPI Data Register bit 5 |
.equ SPDR6 = 6 ; SPI Data Register bit 6 |
.equ SPDR7 = 7 ; SPI Data Register bit 7 |
; SPSR - SPI Status Register |
.equ SPI2X = 0 ; Double SPI Speed Bit |
.equ WCOL = 6 ; Write Collision Flag |
.equ SPIF = 7 ; SPI Interrupt Flag |
; SPCR - SPI Control Register |
.equ SPR0 = 0 ; SPI Clock Rate Select 0 |
.equ SPR1 = 1 ; SPI Clock Rate Select 1 |
.equ CPHA = 2 ; Clock Phase |
.equ CPOL = 3 ; Clock polarity |
.equ MSTR = 4 ; Master/Slave Select |
.equ DORD = 5 ; Data Order |
.equ SPE = 6 ; SPI Enable |
.equ SPIE = 7 ; SPI Interrupt Enable |
; ***** CPU ************************** |
; SREG - Status Register |
.equ SREG_C = 0 ; Carry Flag |
.equ SREG_Z = 1 ; Zero Flag |
.equ SREG_N = 2 ; Negative Flag |
.equ SREG_V = 3 ; Two's Complement Overflow Flag |
.equ SREG_S = 4 ; Sign Bit |
.equ SREG_H = 5 ; Half Carry Flag |
.equ SREG_T = 6 ; Bit Copy Storage |
.equ SREG_I = 7 ; Global Interrupt Enable |
; OSCCAL - Oscillator Calibration Value |
.equ CAL0 = 0 ; Oscillator Calibration Value Bit0 |
.equ CAL1 = 1 ; Oscillator Calibration Value Bit1 |
.equ CAL2 = 2 ; Oscillator Calibration Value Bit2 |
.equ CAL3 = 3 ; Oscillator Calibration Value Bit3 |
.equ CAL4 = 4 ; Oscillator Calibration Value Bit4 |
.equ CAL5 = 5 ; Oscillator Calibration Value Bit5 |
.equ CAL6 = 6 ; Oscillator Calibration Value Bit6 |
.equ CAL7 = 7 ; Oscillator Calibration Value Bit7 |
; CLKPR - Clock Prescale Register |
.equ CLKPS0 = 0 ; Clock Prescaler Select Bit 0 |
.equ CLKPS1 = 1 ; Clock Prescaler Select Bit 1 |
.equ CLKPS2 = 2 ; Clock Prescaler Select Bit 2 |
.equ CLKPS3 = 3 ; Clock Prescaler Select Bit 3 |
.equ CLKPCE = 7 ; Clock Prescaler Change Enable |
; SPMCSR - Store Program Memory Control Register |
.equ SELFPRGEN = 0 ; Self Programming Enable |
.equ PGERS = 1 ; Page Erase |
.equ PGWRT = 2 ; Page Write |
.equ BLBSET = 3 ; Boot Lock Bit Set |
.equ RWWSRE = 4 ; Read-While-Write section read enable |
.equ RWWSB = 6 ; Read-While-Write Section Busy |
.equ SPMIE = 7 ; SPM Interrupt Enable |
; MCUCR - MCU Control Register |
.equ IVCE = 0 ; |
.equ IVSEL = 1 ; |
.equ PUD = 4 ; |
; MCUSR - MCU Status Register |
.equ PORF = 0 ; Power-on reset flag |
.equ EXTRF = 1 ; External Reset Flag |
.equ EXTREF = EXTRF ; For compatibility |
.equ BORF = 2 ; Brown-out Reset Flag |
.equ WDRF = 3 ; Watchdog Reset Flag |
; SMCR - |
.equ SE = 0 ; |
.equ SM0 = 1 ; |
.equ SM1 = 2 ; |
.equ SM2 = 3 ; |
; GPIOR2 - General Purpose I/O Register 2 |
.equ GPIOR20 = 0 ; |
.equ GPIOR21 = 1 ; |
.equ GPIOR22 = 2 ; |
.equ GPIOR23 = 3 ; |
.equ GPIOR24 = 4 ; |
.equ GPIOR25 = 5 ; |
.equ GPIOR26 = 6 ; |
.equ GPIOR27 = 7 ; |
; GPIOR1 - General Purpose I/O Register 1 |
.equ GPIOR10 = 0 ; |
.equ GPIOR11 = 1 ; |
.equ GPIOR12 = 2 ; |
.equ GPIOR13 = 3 ; |
.equ GPIOR14 = 4 ; |
.equ GPIOR15 = 5 ; |
.equ GPIOR16 = 6 ; |
.equ GPIOR17 = 7 ; |
; GPIOR0 - General Purpose I/O Register 0 |
.equ GPIOR00 = 0 ; |
.equ GPIOR01 = 1 ; |
.equ GPIOR02 = 2 ; |
.equ GPIOR03 = 3 ; |
.equ GPIOR04 = 4 ; |
.equ GPIOR05 = 5 ; |
.equ GPIOR06 = 6 ; |
.equ GPIOR07 = 7 ; |
; PRR - Power Reduction Register |
.equ PRADC = 0 ; Power Reduction ADC |
.equ PRUSART0 = 1 ; Power Reduction USART |
.equ PRSPI = 2 ; Power Reduction Serial Peripheral Interface |
.equ PRTIM1 = 3 ; Power Reduction Timer/Counter1 |
.equ PRTIM0 = 5 ; Power Reduction Timer/Counter0 |
.equ PRTIM2 = 6 ; Power Reduction Timer/Counter2 |
.equ PRTWI = 7 ; Power Reduction TWI |
; PCICR - |
.equ PCIE0 = 0 ; |
.equ PCIE1 = 1 ; |
.equ PCIE2 = 2 ; |
; ***** WATCHDOG ********************* |
; WDTCSR - Watchdog Timer Control Register |
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 |
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 |
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 |
.equ WDE = 3 ; Watch Dog Enable |
.equ WDCE = 4 ; Watchdog Change Enable |
.equ WDP3 = 5 ; Watchdog Timer Prescaler Bit 3 |
.equ WDIE = 6 ; Watchdog Timeout Interrupt Enable |
.equ WDIF = 7 ; Watchdog Timeout Interrupt Flag |
; ***** EEPROM *********************** |
; EEARL - EEPROM Address Register Low Byte |
.equ EEAR0 = 0 ; EEPROM Read/Write Access Bit 0 |
.equ EEAR1 = 1 ; EEPROM Read/Write Access Bit 1 |
.equ EEAR2 = 2 ; EEPROM Read/Write Access Bit 2 |
.equ EEAR3 = 3 ; EEPROM Read/Write Access Bit 3 |
.equ EEAR4 = 4 ; EEPROM Read/Write Access Bit 4 |
.equ EEAR5 = 5 ; EEPROM Read/Write Access Bit 5 |
.equ EEAR6 = 6 ; EEPROM Read/Write Access Bit 6 |
.equ EEAR7 = 7 ; EEPROM Read/Write Access Bit 7 |
; EEARH - EEPROM Address Register High Byte |
.equ EEAR8 = 0 ; EEPROM Read/Write Access Bit 0 |
; EEDR - EEPROM Data Register |
.equ EEDR0 = 0 ; EEPROM Data Register bit 0 |
.equ EEDR1 = 1 ; EEPROM Data Register bit 1 |
.equ EEDR2 = 2 ; EEPROM Data Register bit 2 |
.equ EEDR3 = 3 ; EEPROM Data Register bit 3 |
.equ EEDR4 = 4 ; EEPROM Data Register bit 4 |
.equ EEDR5 = 5 ; EEPROM Data Register bit 5 |
.equ EEDR6 = 6 ; EEPROM Data Register bit 6 |
.equ EEDR7 = 7 ; EEPROM Data Register bit 7 |
; EECR - EEPROM Control Register |
.equ EERE = 0 ; EEPROM Read Enable |
.equ EEPE = 1 ; EEPROM Write Enable |
.equ EEMPE = 2 ; EEPROM Master Write Enable |
.equ EERIE = 3 ; EEPROM Ready Interrupt Enable |
.equ EEPM0 = 4 ; EEPROM Programming Mode Bit 0 |
.equ EEPM1 = 5 ; EEPROM Programming Mode Bit 1 |
; ***** LOCKSBITS ******************************************************** |
.equ LB1 = 0 ; Lock bit |
.equ LB2 = 1 ; Lock bit |
.equ BLB01 = 2 ; Boot Lock bit |
.equ BLB02 = 3 ; Boot Lock bit |
.equ BLB11 = 4 ; Boot lock bit |
.equ BLB12 = 5 ; Boot lock bit |
; ***** FUSES ************************************************************ |
; LOW fuse bits |
.equ CKSEL0 = 0 ; Select Clock Source |
.equ CKSEL1 = 1 ; Select Clock Source |
.equ CKSEL2 = 2 ; Select Clock Source |
.equ CKSEL3 = 3 ; Select Clock Source |
.equ SUT0 = 4 ; Select start-up time |
.equ SUT1 = 5 ; Select start-up time |
.equ CKOUT = 6 ; Clock output |
.equ CKDIV8 = 7 ; Divide clock by 8 |
; HIGH fuse bits |
.equ BODLEVEL0 = 0 ; Brown-out Detector trigger level |
.equ BODLEVEL1 = 1 ; Brown-out Detector trigger level |
.equ BODLEVEL2 = 2 ; Brown-out Detector trigger level |
.equ EESAVE = 3 ; EEPROM memory is preserved through chip erase |
.equ WDTON = 4 ; Watchdog Timer Always On |
.equ SPIEN = 5 ; Enable Serial programming and Data Downloading |
.equ DWEN = 6 ; debugWIRE Enable |
.equ RSTDISBL = 7 ; External reset disable |
; EXTENDED fuse bits |
.equ BOOTRST = 0 ; Select reset vector |
.equ BOOTSZ0 = 1 ; Select boot size |
.equ BOOTSZ1 = 2 ; Select boot size |
; ***** CPU REGISTER DEFINITIONS ***************************************** |
.def XH = r27 |
.def XL = r26 |
.def YH = r29 |
.def YL = r28 |
.def ZH = r31 |
.def ZL = r30 |
; ***** DATA MEMORY DECLARATIONS ***************************************** |
.equ FLASHEND = 0x0fff ; Note: Word address |
.equ IOEND = 0x00ff |
.equ SRAM_START = 0x0100 |
.equ SRAM_SIZE = 1024 |
.equ RAMEND = 0x04ff |
.equ XRAMEND = 0x0000 |
.equ E2END = 0x01ff |
.equ EEPROMEND = 0x01ff |
.equ EEADRBITS = 9 |
#pragma AVRPART MEMORY PROG_FLASH 8192 |
#pragma AVRPART MEMORY EEPROM 512 |
#pragma AVRPART MEMORY INT_SRAM SIZE 1024 |
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x100 |
; ***** BOOTLOADER DECLARATIONS ****************************************** |
.equ NRWW_START_ADDR = 0xc00 |
.equ NRWW_STOP_ADDR = 0xfff |
.equ RWW_START_ADDR = 0x0 |
.equ RWW_STOP_ADDR = 0xbff |
.equ PAGESIZE = 32 |
.equ FIRSTBOOTSTART = 0xf80 |
.equ SECONDBOOTSTART = 0xf00 |
.equ THIRDBOOTSTART = 0xe00 |
.equ FOURTHBOOTSTART = 0xc00 |
.equ SMALLBOOTSTART = FIRSTBOOTSTART |
.equ LARGEBOOTSTART = FOURTHBOOTSTART |
; ***** INTERRUPT VECTORS ************************************************ |
.equ INT0addr = 0x0001 ; External Interrupt Request 0 |
.equ INT1addr = 0x0002 ; External Interrupt Request 1 |
.equ PCI0addr = 0x0003 ; Pin Change Interrupt Request 0 |
.equ PCI1addr = 0x0004 ; Pin Change Interrupt Request 0 |
.equ PCI2addr = 0x0005 ; Pin Change Interrupt Request 1 |
.equ WDTaddr = 0x0006 ; Watchdog Time-out Interrupt |
.equ OC2Aaddr = 0x0007 ; Timer/Counter2 Compare Match A |
.equ OC2Baddr = 0x0008 ; Timer/Counter2 Compare Match A |
.equ OVF2addr = 0x0009 ; Timer/Counter2 Overflow |
.equ ICP1addr = 0x000a ; Timer/Counter1 Capture Event |
.equ OC1Aaddr = 0x000b ; Timer/Counter1 Compare Match A |
.equ OC1Baddr = 0x000c ; Timer/Counter1 Compare Match B |
.equ OVF1addr = 0x000d ; Timer/Counter1 Overflow |
.equ OC0Aaddr = 0x000e ; TimerCounter0 Compare Match A |
.equ OC0Baddr = 0x001f ; TimerCounter0 Compare Match B |
.equ OVF0addr = 0x0010 ; Timer/Couner0 Overflow |
.equ SPIaddr = 0x0011 ; SPI Serial Transfer Complete |
.equ URXCaddr = 0x0012 ; USART Rx Complete |
.equ UDREaddr = 0x0013 ; USART, Data Register Empty |
.equ UTXCaddr = 0x0014 ; USART Tx Complete |
.equ ADCCaddr = 0x0015 ; ADC Conversion Complete |
.equ ERDYaddr = 0x0016 ; EEPROM Ready |
.equ ACIaddr = 0x0017 ; Analog Comparator |
.equ TWIaddr = 0x0018 ; Two-wire Serial Interface |
.equ SPMRaddr = 0x0019 ; Store Program Memory Read |
.equ INT_VECTORS_SIZE = 26 ; size in words |
#endif /* _M88DEF_INC_ */ |
; ***** END OF FILE ****************************************************** |
/contrib/toolchain/avra/includes/m8def.inc |
---|
0,0 → 1,738 |
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** |
;***** Created: 2005-01-11 10:31 ******* Source: ATmega8.xml ************* |
;************************************************************************* |
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y |
;* |
;* Number : AVR000 |
;* File Name : "m8def.inc" |
;* Title : Register/Bit Definitions for the ATmega8 |
;* Date : 2005-01-11 |
;* Version : 2.14 |
;* Support E-mail : avr@atmel.com |
;* Target MCU : ATmega8 |
;* |
;* DESCRIPTION |
;* When including this file in the assembly program file, all I/O register |
;* names and I/O register bit names appearing in the data book can be used. |
;* In addition, the six registers forming the three data pointers X, Y and |
;* Z have been assigned names XL - ZH. Highest RAM address for Internal |
;* SRAM is also defined |
;* |
;* The Register names are represented by their hexadecimal address. |
;* |
;* The Register Bit names are represented by their bit number (0-7). |
;* |
;* Please observe the difference in using the bit names with instructions |
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" |
;* (skip if bit in register set/cleared). The following example illustrates |
;* this: |
;* |
;* in r16,PORTB ;read PORTB latch |
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) |
;* out PORTB,r16 ;output to PORTB |
;* |
;* in r16,TIFR ;read the Timer Interrupt Flag Register |
;* sbrc r16,TOV0 ;test the overflow flag (use bit#) |
;* rjmp TOV0_is_set ;jump if set |
;* ... ;otherwise do something else |
;************************************************************************* |
#ifndef _M8DEF_INC_ |
#define _M8DEF_INC_ |
#pragma partinc 0 |
; ***** SPECIFY DEVICE *************************************************** |
.device ATmega8 |
#pragma AVRPART ADMIN PART_NAME ATmega8 |
.equ SIGNATURE_000 = 0x1e |
.equ SIGNATURE_001 = 0x93 |
.equ SIGNATURE_002 = 0x07 |
#pragma AVRPART CORE CORE_VERSION V2E |
; ***** I/O REGISTER DEFINITIONS ***************************************** |
; NOTE: |
; Definitions marked "MEMORY MAPPED"are extended I/O ports |
; and cannot be used with IN/OUT instructions |
.equ SREG = 0x3f |
.equ SPH = 0x3e |
.equ SPL = 0x3d |
.equ GICR = 0x3b |
.equ GIFR = 0x3a |
.equ TIMSK = 0x39 |
.equ TIFR = 0x38 |
.equ SPMCR = 0x37 |
.equ TWCR = 0x36 |
.equ MCUCR = 0x35 |
.equ MCUCSR = 0x34 |
.equ TCCR0 = 0x33 |
.equ TCNT0 = 0x32 |
.equ OSCCAL = 0x31 |
.equ SFIOR = 0x30 |
.equ TCCR1A = 0x2f |
.equ TCCR1B = 0x2e |
.equ TCNT1H = 0x2d |
.equ TCNT1L = 0x2c |
.equ OCR1AH = 0x2b |
.equ OCR1AL = 0x2a |
.equ OCR1BH = 0x29 |
.equ OCR1BL = 0x28 |
.equ ICR1H = 0x27 |
.equ ICR1L = 0x26 |
.equ TCCR2 = 0x25 |
.equ TCNT2 = 0x24 |
.equ OCR2 = 0x23 |
.equ ASSR = 0x22 |
.equ WDTCR = 0x21 |
.equ UBRRH = 0x20 |
.equ UCSRC = 0x20 |
.equ EEARH = 0x1f |
.equ EEARL = 0x1e |
.equ EEDR = 0x1d |
.equ EECR = 0x1c |
.equ PORTB = 0x18 |
.equ DDRB = 0x17 |
.equ PINB = 0x16 |
.equ PORTC = 0x15 |
.equ DDRC = 0x14 |
.equ PINC = 0x13 |
.equ PORTD = 0x12 |
.equ DDRD = 0x11 |
.equ PIND = 0x10 |
.equ SPDR = 0x0f |
.equ SPSR = 0x0e |
.equ SPCR = 0x0d |
.equ UDR = 0x0c |
.equ UCSRA = 0x0b |
.equ UCSRB = 0x0a |
.equ UBRRL = 0x09 |
.equ ACSR = 0x08 |
.equ ADMUX = 0x07 |
.equ ADCSRA = 0x06 |
.equ ADCH = 0x05 |
.equ ADCL = 0x04 |
.equ TWDR = 0x03 |
.equ TWAR = 0x02 |
.equ TWSR = 0x01 |
.equ TWBR = 0x00 |
; ***** BIT DEFINITIONS ************************************************** |
; ***** ANALOG_COMPARATOR ************ |
; SFIOR - Special Function IO Register |
.equ ACME = 3 ; Analog Comparator Multiplexer Enable |
; ACSR - Analog Comparator Control And Status Register |
.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 |
.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 |
.equ ACIC = 2 ; Analog Comparator Input Capture Enable |
.equ ACIE = 3 ; Analog Comparator Interrupt Enable |
.equ ACI = 4 ; Analog Comparator Interrupt Flag |
.equ ACO = 5 ; Analog Compare Output |
.equ ACBG = 6 ; Analog Comparator Bandgap Select |
.equ ACD = 7 ; Analog Comparator Disable |
; ***** SPI ************************** |
; SPDR - SPI Data Register |
.equ SPDR0 = 0 ; SPI Data Register bit 0 |
.equ SPDR1 = 1 ; SPI Data Register bit 1 |
.equ SPDR2 = 2 ; SPI Data Register bit 2 |
.equ SPDR3 = 3 ; SPI Data Register bit 3 |
.equ SPDR4 = 4 ; SPI Data Register bit 4 |
.equ SPDR5 = 5 ; SPI Data Register bit 5 |
.equ SPDR6 = 6 ; SPI Data Register bit 6 |
.equ SPDR7 = 7 ; SPI Data Register bit 7 |
; SPSR - SPI Status Register |
.equ SPI2X = 0 ; Double SPI Speed Bit |
.equ WCOL = 6 ; Write Collision Flag |
.equ SPIF = 7 ; SPI Interrupt Flag |
; SPCR - SPI Control Register |
.equ SPR0 = 0 ; SPI Clock Rate Select 0 |
.equ SPR1 = 1 ; SPI Clock Rate Select 1 |
.equ CPHA = 2 ; Clock Phase |
.equ CPOL = 3 ; Clock polarity |
.equ MSTR = 4 ; Master/Slave Select |
.equ DORD = 5 ; Data Order |
.equ SPE = 6 ; SPI Enable |
.equ SPIE = 7 ; SPI Interrupt Enable |
; ***** EXTERNAL_INTERRUPT *********** |
; GICR - General Interrupt Control Register |
.equ GIMSK = GICR ; For compatibility |
.equ IVCE = 0 ; Interrupt Vector Change Enable |
.equ IVSEL = 1 ; Interrupt Vector Select |
.equ INT0 = 6 ; External Interrupt Request 0 Enable |
.equ INT1 = 7 ; External Interrupt Request 1 Enable |
; GIFR - General Interrupt Flag Register |
.equ INTF0 = 6 ; External Interrupt Flag 0 |
.equ INTF1 = 7 ; External Interrupt Flag 1 |
; MCUCR - MCU Control Register |
.equ ISC00 = 0 ; Interrupt Sense Control 0 Bit 0 |
.equ ISC01 = 1 ; Interrupt Sense Control 0 Bit 1 |
.equ ISC10 = 2 ; Interrupt Sense Control 1 Bit 0 |
.equ ISC11 = 3 ; Interrupt Sense Control 1 Bit 1 |
; ***** TIMER_COUNTER_0 ************** |
; TIMSK - Timer/Counter Interrupt Mask Register |
.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable |
; TIFR - Timer/Counter Interrupt Flag register |
.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag |
; TCCR0 - Timer/Counter0 Control Register |
.equ CS00 = 0 ; Clock Select0 bit 0 |
.equ CS01 = 1 ; Clock Select0 bit 1 |
.equ CS02 = 2 ; Clock Select0 bit 2 |
; TCNT0 - Timer Counter 0 |
.equ TCNT00 = 0 ; Timer Counter 0 bit 0 |
.equ TCNT01 = 1 ; Timer Counter 0 bit 1 |
.equ TCNT02 = 2 ; Timer Counter 0 bit 2 |
.equ TCNT03 = 3 ; Timer Counter 0 bit 3 |
.equ TCNT04 = 4 ; Timer Counter 0 bit 4 |
.equ TCNT05 = 5 ; Timer Counter 0 bit 5 |
.equ TCNT06 = 6 ; Timer Counter 0 bit 6 |
.equ TCNT07 = 7 ; Timer Counter 0 bit 7 |
; ***** TIMER_COUNTER_1 ************** |
; TIMSK - Timer/Counter Interrupt Mask Register |
.equ TOIE1 = 2 ; Timer/Counter1 Overflow Interrupt Enable |
.equ OCIE1B = 3 ; Timer/Counter1 Output CompareB Match Interrupt Enable |
.equ OCIE1A = 4 ; Timer/Counter1 Output CompareA Match Interrupt Enable |
.equ TICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable |
; TIFR - Timer/Counter Interrupt Flag register |
.equ TOV1 = 2 ; Timer/Counter1 Overflow Flag |
.equ OCF1B = 3 ; Output Compare Flag 1B |
.equ OCF1A = 4 ; Output Compare Flag 1A |
.equ ICF1 = 5 ; Input Capture Flag 1 |
; TCCR1A - Timer/Counter1 Control Register A |
.equ WGM10 = 0 ; Waveform Generation Mode |
.equ PWM10 = WGM10 ; For compatibility |
.equ WGM11 = 1 ; Waveform Generation Mode |
.equ PWM11 = WGM11 ; For compatibility |
.equ FOC1B = 2 ; Force Output Compare 1B |
.equ FOC1A = 3 ; Force Output Compare 1A |
.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0 |
.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1 |
.equ COM1A0 = 6 ; Comparet Ouput Mode 1A, bit 0 |
.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1 |
; TCCR1B - Timer/Counter1 Control Register B |
.equ CS10 = 0 ; Prescaler source of Timer/Counter 1 |
.equ CS11 = 1 ; Prescaler source of Timer/Counter 1 |
.equ CS12 = 2 ; Prescaler source of Timer/Counter 1 |
.equ WGM12 = 3 ; Waveform Generation Mode |
.equ CTC10 = WGM12 ; For compatibility |
.equ CTC1 = WGM12 ; For compatibility |
.equ WGM13 = 4 ; Waveform Generation Mode |
.equ CTC11 = WGM13 ; For compatibility |
.equ ICES1 = 6 ; Input Capture 1 Edge Select |
.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler |
; ***** TIMER_COUNTER_2 ************** |
; TIMSK - Timer/Counter Interrupt Mask register |
.equ TOIE2 = 6 ; Timer/Counter2 Overflow Interrupt Enable |
.equ OCIE2 = 7 ; Timer/Counter2 Output Compare Match Interrupt Enable |
; TIFR - Timer/Counter Interrupt Flag Register |
.equ TOV2 = 6 ; Timer/Counter2 Overflow Flag |
.equ OCF2 = 7 ; Output Compare Flag 2 |
; TCCR2 - Timer/Counter2 Control Register |
.equ CS20 = 0 ; Clock Select bit 0 |
.equ CS21 = 1 ; Clock Select bit 1 |
.equ CS22 = 2 ; Clock Select bit 2 |
.equ WGM21 = 3 ; Waveform Generation Mode |
.equ CTC2 = WGM21 ; For compatibility |
.equ COM20 = 4 ; Compare Output Mode bit 0 |
.equ COM21 = 5 ; Compare Output Mode bit 1 |
.equ WGM20 = 6 ; Waveform Genration Mode |
.equ PWM2 = WGM20 ; For compatibility |
.equ FOC2 = 7 ; Force Output Compare |
; TCNT2 - Timer/Counter2 |
.equ TCNT2_0 = 0 ; Timer/Counter 2 bit 0 |
.equ TCNT2_1 = 1 ; Timer/Counter 2 bit 1 |
.equ TCNT2_2 = 2 ; Timer/Counter 2 bit 2 |
.equ TCNT2_3 = 3 ; Timer/Counter 2 bit 3 |
.equ TCNT2_4 = 4 ; Timer/Counter 2 bit 4 |
.equ TCNT2_5 = 5 ; Timer/Counter 2 bit 5 |
.equ TCNT2_6 = 6 ; Timer/Counter 2 bit 6 |
.equ TCNT2_7 = 7 ; Timer/Counter 2 bit 7 |
; OCR2 - Timer/Counter2 Output Compare Register |
.equ OCR2_0 = 0 ; Timer/Counter2 Output Compare Register Bit 0 |
.equ OCR2_1 = 1 ; Timer/Counter2 Output Compare Register Bit 1 |
.equ OCR2_2 = 2 ; Timer/Counter2 Output Compare Register Bit 2 |
.equ OCR2_3 = 3 ; Timer/Counter2 Output Compare Register Bit 3 |
.equ OCR2_4 = 4 ; Timer/Counter2 Output Compare Register Bit 4 |
.equ OCR2_5 = 5 ; Timer/Counter2 Output Compare Register Bit 5 |
.equ OCR2_6 = 6 ; Timer/Counter2 Output Compare Register Bit 6 |
.equ OCR2_7 = 7 ; Timer/Counter2 Output Compare Register Bit 7 |
; ASSR - Asynchronous Status Register |
.equ TCR2UB = 0 ; Timer/counter Control Register2 Update Busy |
.equ OCR2UB = 1 ; Output Compare Register2 Update Busy |
.equ TCN2UB = 2 ; Timer/Counter2 Update Busy |
.equ AS2 = 3 ; Asynchronous Timer/counter2 |
; SFIOR - Special Function IO Register |
.equ PSR2 = 1 ; Prescaler Reset Timer/Counter2 |
; ***** USART ************************ |
; UDR - USART I/O Data Register |
.equ UDR0 = 0 ; USART I/O Data Register bit 0 |
.equ UDR1 = 1 ; USART I/O Data Register bit 1 |
.equ UDR2 = 2 ; USART I/O Data Register bit 2 |
.equ UDR3 = 3 ; USART I/O Data Register bit 3 |
.equ UDR4 = 4 ; USART I/O Data Register bit 4 |
.equ UDR5 = 5 ; USART I/O Data Register bit 5 |
.equ UDR6 = 6 ; USART I/O Data Register bit 6 |
.equ UDR7 = 7 ; USART I/O Data Register bit 7 |
; UCSRA - USART Control and Status Register A |
.equ USR = UCSRA ; For compatibility |
.equ MPCM = 0 ; Multi-processor Communication Mode |
.equ U2X = 1 ; Double the USART transmission speed |
.equ UPE = 2 ; Parity Error |
.equ PE = UPE ; For compatibility |
.equ DOR = 3 ; Data overRun |
.equ FE = 4 ; Framing Error |
.equ UDRE = 5 ; USART Data Register Empty |
.equ TXC = 6 ; USART Transmitt Complete |
.equ RXC = 7 ; USART Receive Complete |
; UCSRB - USART Control and Status Register B |
.equ UCR = UCSRB ; For compatibility |
.equ TXB8 = 0 ; Transmit Data Bit 8 |
.equ RXB8 = 1 ; Receive Data Bit 8 |
.equ UCSZ2 = 2 ; Character Size |
.equ CHR9 = UCSZ2 ; For compatibility |
.equ TXEN = 3 ; Transmitter Enable |
.equ RXEN = 4 ; Receiver Enable |
.equ UDRIE = 5 ; USART Data register Empty Interrupt Enable |
.equ TXCIE = 6 ; TX Complete Interrupt Enable |
.equ RXCIE = 7 ; RX Complete Interrupt Enable |
; UCSRC - USART Control and Status Register C |
.equ UCPOL = 0 ; Clock Polarity |
.equ UCSZ0 = 1 ; Character Size |
.equ UCSZ1 = 2 ; Character Size |
.equ USBS = 3 ; Stop Bit Select |
.equ UPM0 = 4 ; Parity Mode Bit 0 |
.equ UPM1 = 5 ; Parity Mode Bit 1 |
.equ UMSEL = 6 ; USART Mode Select |
.equ URSEL = 7 ; Register Select |
.equ UBRRHI = UBRRH ; For compatibility |
; ***** TWI ************************** |
; TWBR - TWI Bit Rate register |
.equ I2BR = TWBR ; For compatibility |
.equ TWBR0 = 0 ; |
.equ TWBR1 = 1 ; |
.equ TWBR2 = 2 ; |
.equ TWBR3 = 3 ; |
.equ TWBR4 = 4 ; |
.equ TWBR5 = 5 ; |
.equ TWBR6 = 6 ; |
.equ TWBR7 = 7 ; |
; TWCR - TWI Control Register |
.equ I2CR = TWCR ; For compatibility |
.equ TWIE = 0 ; TWI Interrupt Enable |
.equ I2IE = TWIE ; For compatibility |
.equ TWEN = 2 ; TWI Enable Bit |
.equ I2EN = TWEN ; For compatibility |
.equ ENI2C = TWEN ; For compatibility |
.equ TWWC = 3 ; TWI Write Collition Flag |
.equ I2WC = TWWC ; For compatibility |
.equ TWSTO = 4 ; TWI Stop Condition Bit |
.equ I2STO = TWSTO ; For compatibility |
.equ TWSTA = 5 ; TWI Start Condition Bit |
.equ I2STA = TWSTA ; For compatibility |
.equ TWEA = 6 ; TWI Enable Acknowledge Bit |
.equ I2EA = TWEA ; For compatibility |
.equ TWINT = 7 ; TWI Interrupt Flag |
.equ I2INT = TWINT ; For compatibility |
; TWSR - TWI Status Register |
.equ I2SR = TWSR ; For compatibility |
.equ TWPS0 = 0 ; TWI Prescaler |
.equ TWS0 = TWPS0 ; For compatibility |
.equ I2GCE = TWPS0 ; For compatibility |
.equ TWPS1 = 1 ; TWI Prescaler |
.equ TWS1 = TWPS1 ; For compatibility |
.equ TWS3 = 3 ; TWI Status |
.equ I2S3 = TWS3 ; For compatibility |
.equ TWS4 = 4 ; TWI Status |
.equ I2S4 = TWS4 ; For compatibility |
.equ TWS5 = 5 ; TWI Status |
.equ I2S5 = TWS5 ; For compatibility |
.equ TWS6 = 6 ; TWI Status |
.equ I2S6 = TWS6 ; For compatibility |
.equ TWS7 = 7 ; TWI Status |
.equ I2S7 = TWS7 ; For compatibility |
; TWDR - TWI Data register |
.equ I2DR = TWDR ; For compatibility |
.equ TWD0 = 0 ; TWI Data Register Bit 0 |
.equ TWD1 = 1 ; TWI Data Register Bit 1 |
.equ TWD2 = 2 ; TWI Data Register Bit 2 |
.equ TWD3 = 3 ; TWI Data Register Bit 3 |
.equ TWD4 = 4 ; TWI Data Register Bit 4 |
.equ TWD5 = 5 ; TWI Data Register Bit 5 |
.equ TWD6 = 6 ; TWI Data Register Bit 6 |
.equ TWD7 = 7 ; TWI Data Register Bit 7 |
; TWAR - TWI (Slave) Address register |
.equ I2AR = TWAR ; For compatibility |
.equ TWGCE = 0 ; TWI General Call Recognition Enable Bit |
.equ TWA0 = 1 ; TWI (Slave) Address register Bit 0 |
.equ TWA1 = 2 ; TWI (Slave) Address register Bit 1 |
.equ TWA2 = 3 ; TWI (Slave) Address register Bit 2 |
.equ TWA3 = 4 ; TWI (Slave) Address register Bit 3 |
.equ TWA4 = 5 ; TWI (Slave) Address register Bit 4 |
.equ TWA5 = 6 ; TWI (Slave) Address register Bit 5 |
.equ TWA6 = 7 ; TWI (Slave) Address register Bit 6 |
; ***** WATCHDOG ********************* |
; WDTCR - Watchdog Timer Control Register |
.equ WDTCSR = WDTCR ; For compatibility |
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 |
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 |
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 |
.equ WDE = 3 ; Watch Dog Enable |
.equ WDCE = 4 ; Watchdog Change Enable |
.equ WDTOE = WDCE ; For compatibility |
; ***** PORTB ************************ |
; PORTB - Port B Data Register |
.equ PORTB0 = 0 ; Port B Data Register bit 0 |
.equ PB0 = 0 ; For compatibility |
.equ PORTB1 = 1 ; Port B Data Register bit 1 |
.equ PB1 = 1 ; For compatibility |
.equ PORTB2 = 2 ; Port B Data Register bit 2 |
.equ PB2 = 2 ; For compatibility |
.equ PORTB3 = 3 ; Port B Data Register bit 3 |
.equ PB3 = 3 ; For compatibility |
.equ PORTB4 = 4 ; Port B Data Register bit 4 |
.equ PB4 = 4 ; For compatibility |
.equ PORTB5 = 5 ; Port B Data Register bit 5 |
.equ PB5 = 5 ; For compatibility |
.equ PORTB6 = 6 ; Port B Data Register bit 6 |
.equ PB6 = 6 ; For compatibility |
.equ PORTB7 = 7 ; Port B Data Register bit 7 |
.equ PB7 = 7 ; For compatibility |
; DDRB - Port B Data Direction Register |
.equ DDB0 = 0 ; Port B Data Direction Register bit 0 |
.equ DDB1 = 1 ; Port B Data Direction Register bit 1 |
.equ DDB2 = 2 ; Port B Data Direction Register bit 2 |
.equ DDB3 = 3 ; Port B Data Direction Register bit 3 |
.equ DDB4 = 4 ; Port B Data Direction Register bit 4 |
.equ DDB5 = 5 ; Port B Data Direction Register bit 5 |
.equ DDB6 = 6 ; Port B Data Direction Register bit 6 |
.equ DDB7 = 7 ; Port B Data Direction Register bit 7 |
; PINB - Port B Input Pins |
.equ PINB0 = 0 ; Port B Input Pins bit 0 |
.equ PINB1 = 1 ; Port B Input Pins bit 1 |
.equ PINB2 = 2 ; Port B Input Pins bit 2 |
.equ PINB3 = 3 ; Port B Input Pins bit 3 |
.equ PINB4 = 4 ; Port B Input Pins bit 4 |
.equ PINB5 = 5 ; Port B Input Pins bit 5 |
.equ PINB6 = 6 ; Port B Input Pins bit 6 |
.equ PINB7 = 7 ; Port B Input Pins bit 7 |
; ***** PORTC ************************ |
; PORTC - Port C Data Register |
.equ PORTC0 = 0 ; Port C Data Register bit 0 |
.equ PC0 = 0 ; For compatibility |
.equ PORTC1 = 1 ; Port C Data Register bit 1 |
.equ PC1 = 1 ; For compatibility |
.equ PORTC2 = 2 ; Port C Data Register bit 2 |
.equ PC2 = 2 ; For compatibility |
.equ PORTC3 = 3 ; Port C Data Register bit 3 |
.equ PC3 = 3 ; For compatibility |
.equ PORTC4 = 4 ; Port C Data Register bit 4 |
.equ PC4 = 4 ; For compatibility |
.equ PORTC5 = 5 ; Port C Data Register bit 5 |
.equ PC5 = 5 ; For compatibility |
.equ PORTC6 = 6 ; Port C Data Register bit 6 |
.equ PC6 = 6 ; For compatibility |
; DDRC - Port C Data Direction Register |
.equ DDC0 = 0 ; Port C Data Direction Register bit 0 |
.equ DDC1 = 1 ; Port C Data Direction Register bit 1 |
.equ DDC2 = 2 ; Port C Data Direction Register bit 2 |
.equ DDC3 = 3 ; Port C Data Direction Register bit 3 |
.equ DDC4 = 4 ; Port C Data Direction Register bit 4 |
.equ DDC5 = 5 ; Port C Data Direction Register bit 5 |
.equ DDC6 = 6 ; Port C Data Direction Register bit 6 |
; PINC - Port C Input Pins |
.equ PINC0 = 0 ; Port C Input Pins bit 0 |
.equ PINC1 = 1 ; Port C Input Pins bit 1 |
.equ PINC2 = 2 ; Port C Input Pins bit 2 |
.equ PINC3 = 3 ; Port C Input Pins bit 3 |
.equ PINC4 = 4 ; Port C Input Pins bit 4 |
.equ PINC5 = 5 ; Port C Input Pins bit 5 |
.equ PINC6 = 6 ; Port C Input Pins bit 6 |
; ***** PORTD ************************ |
; PORTD - Port D Data Register |
.equ PORTD0 = 0 ; Port D Data Register bit 0 |
.equ PD0 = 0 ; For compatibility |
.equ PORTD1 = 1 ; Port D Data Register bit 1 |
.equ PD1 = 1 ; For compatibility |
.equ PORTD2 = 2 ; Port D Data Register bit 2 |
.equ PD2 = 2 ; For compatibility |
.equ PORTD3 = 3 ; Port D Data Register bit 3 |
.equ PD3 = 3 ; For compatibility |
.equ PORTD4 = 4 ; Port D Data Register bit 4 |
.equ PD4 = 4 ; For compatibility |
.equ PORTD5 = 5 ; Port D Data Register bit 5 |
.equ PD5 = 5 ; For compatibility |
.equ PORTD6 = 6 ; Port D Data Register bit 6 |
.equ PD6 = 6 ; For compatibility |
.equ PORTD7 = 7 ; Port D Data Register bit 7 |
.equ PD7 = 7 ; For compatibility |
; DDRD - Port D Data Direction Register |
.equ DDD0 = 0 ; Port D Data Direction Register bit 0 |
.equ DDD1 = 1 ; Port D Data Direction Register bit 1 |
.equ DDD2 = 2 ; Port D Data Direction Register bit 2 |
.equ DDD3 = 3 ; Port D Data Direction Register bit 3 |
.equ DDD4 = 4 ; Port D Data Direction Register bit 4 |
.equ DDD5 = 5 ; Port D Data Direction Register bit 5 |
.equ DDD6 = 6 ; Port D Data Direction Register bit 6 |
.equ DDD7 = 7 ; Port D Data Direction Register bit 7 |
; PIND - Port D Input Pins |
.equ PIND0 = 0 ; Port D Input Pins bit 0 |
.equ PIND1 = 1 ; Port D Input Pins bit 1 |
.equ PIND2 = 2 ; Port D Input Pins bit 2 |
.equ PIND3 = 3 ; Port D Input Pins bit 3 |
.equ PIND4 = 4 ; Port D Input Pins bit 4 |
.equ PIND5 = 5 ; Port D Input Pins bit 5 |
.equ PIND6 = 6 ; Port D Input Pins bit 6 |
.equ PIND7 = 7 ; Port D Input Pins bit 7 |
; ***** EEPROM *********************** |
; EEDR - EEPROM Data Register |
.equ EEDR0 = 0 ; EEPROM Data Register bit 0 |
.equ EEDR1 = 1 ; EEPROM Data Register bit 1 |
.equ EEDR2 = 2 ; EEPROM Data Register bit 2 |
.equ EEDR3 = 3 ; EEPROM Data Register bit 3 |
.equ EEDR4 = 4 ; EEPROM Data Register bit 4 |
.equ EEDR5 = 5 ; EEPROM Data Register bit 5 |
.equ EEDR6 = 6 ; EEPROM Data Register bit 6 |
.equ EEDR7 = 7 ; EEPROM Data Register bit 7 |
; EECR - EEPROM Control Register |
.equ EERE = 0 ; EEPROM Read Enable |
.equ EEWE = 1 ; EEPROM Write Enable |
.equ EEMWE = 2 ; EEPROM Master Write Enable |
.equ EEWEE = EEMWE ; For compatibility |
.equ EERIE = 3 ; EEPROM Ready Interrupt Enable |
; ***** CPU ************************** |
; SREG - Status Register |
.equ SREG_C = 0 ; Carry Flag |
.equ SREG_Z = 1 ; Zero Flag |
.equ SREG_N = 2 ; Negative Flag |
.equ SREG_V = 3 ; Two's Complement Overflow Flag |
.equ SREG_S = 4 ; Sign Bit |
.equ SREG_H = 5 ; Half Carry Flag |
.equ SREG_T = 6 ; Bit Copy Storage |
.equ SREG_I = 7 ; Global Interrupt Enable |
; MCUCR - MCU Control Register |
;.equ ISC00 = 0 ; Interrupt Sense Control 0 Bit 0 |
;.equ ISC01 = 1 ; Interrupt Sense Control 0 Bit 1 |
;.equ ISC10 = 2 ; Interrupt Sense Control 1 Bit 0 |
;.equ ISC11 = 3 ; Interrupt Sense Control 1 Bit 1 |
.equ SM0 = 4 ; Sleep Mode Select |
.equ SM1 = 5 ; Sleep Mode Select |
.equ SM2 = 6 ; Sleep Mode Select |
.equ SE = 7 ; Sleep Enable |
; MCUCSR - MCU Control And Status Register |
.equ MCUSR = MCUCSR ; For compatibility |
.equ PORF = 0 ; Power-on reset flag |
.equ EXTRF = 1 ; External Reset Flag |
.equ BORF = 2 ; Brown-out Reset Flag |
.equ WDRF = 3 ; Watchdog Reset Flag |
; OSCCAL - Oscillator Calibration Value |
.equ CAL0 = 0 ; Oscillator Calibration Value Bit0 |
.equ CAL1 = 1 ; Oscillator Calibration Value Bit1 |
.equ CAL2 = 2 ; Oscillator Calibration Value Bit2 |
.equ CAL3 = 3 ; Oscillator Calibration Value Bit3 |
.equ CAL4 = 4 ; Oscillator Calibration Value Bit4 |
.equ CAL5 = 5 ; Oscillator Calibration Value Bit5 |
.equ CAL6 = 6 ; Oscillator Calibration Value Bit6 |
.equ CAL7 = 7 ; Oscillator Calibration Value Bit7 |
; SPMCR - Store Program Memory Control Register |
.equ SPMEN = 0 ; Store Program Memory Enable |
.equ PGERS = 1 ; Page Erase |
.equ PGWRT = 2 ; Page Write |
.equ BLBSET = 3 ; Boot Lock Bit Set |
.equ RWWSRE = 4 ; Read-While-Write Section Read Enable |
.equ RWWSB = 6 ; Read-While-Write Section Busy |
.equ SPMIE = 7 ; SPM Interrupt Enable |
; SFIOR - Special Function IO Register |
.equ PSR10 = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0 |
.equ PUD = 2 ; Pull-up Disable |
.equ ADHSM = 4 ; ADC High Speed Mode |
; ***** AD_CONVERTER ***************** |
; ADMUX - The ADC multiplexer Selection Register |
.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits |
.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits |
.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits |
.equ MUX3 = 3 ; Analog Channel and Gain Selection Bits |
.equ ADLAR = 5 ; Left Adjust Result |
.equ REFS0 = 6 ; Reference Selection Bit 0 |
.equ REFS1 = 7 ; Reference Selection Bit 1 |
; ADCSRA - The ADC Control and Status register |
.equ ADCSR = ADCSRA ; For compatibility |
.equ ADPS0 = 0 ; ADC Prescaler Select Bits |
.equ ADPS1 = 1 ; ADC Prescaler Select Bits |
.equ ADPS2 = 2 ; ADC Prescaler Select Bits |
.equ ADIE = 3 ; ADC Interrupt Enable |
.equ ADIF = 4 ; ADC Interrupt Flag |
.equ ADFR = 5 ; ADC Free Running Select |
.equ ADSC = 6 ; ADC Start Conversion |
.equ ADEN = 7 ; ADC Enable |
; ***** LOCKSBITS ******************************************************** |
.equ LB1 = 0 ; Lock bit |
.equ LB2 = 1 ; Lock bit |
.equ BLB01 = 2 ; Boot Lock bit |
.equ BLB02 = 3 ; Boot Lock bit |
.equ BLB11 = 4 ; Boot lock bit |
.equ BLB12 = 5 ; Boot lock bit |
; ***** FUSES ************************************************************ |
; LOW fuse bits |
.equ CKSEL0 = 0 ; Select Clock Source |
.equ CKSEL1 = 1 ; Select Clock Source |
.equ CKSEL2 = 2 ; Select Clock Source |
.equ CKSEL3 = 3 ; Select Clock Source |
.equ SUT0 = 4 ; Select start-up time |
.equ SUT1 = 5 ; Select start-up time |
.equ BODEN = 6 ; Brown out detector enable |
.equ BODLEVEL = 7 ; Brown out detector trigger level |
; HIGH fuse bits |
.equ BOOTRST = 0 ; Select Reset Vector |
.equ BOOTSZ0 = 1 ; Select Boot Size |
.equ BOOTSZ1 = 2 ; Select Boot Size |
.equ EESAVE = 3 ; EEPROM memory is preserved through chip erase |
.equ CKOPT = 4 ; Oscillator Options |
.equ SPIEN = 5 ; Enable Serial programming and Data Downloading |
.equ WTDON = 6 ; Enable watchdog |
.equ RSTDISBL = 7 ; Disable reset |
; ***** CPU REGISTER DEFINITIONS ***************************************** |
.def XH = r27 |
.def XL = r26 |
.def YH = r29 |
.def YL = r28 |
.def ZH = r31 |
.def ZL = r30 |
; ***** DATA MEMORY DECLARATIONS ***************************************** |
.equ FLASHEND = 0x0fff ; Note: Word address |
.equ IOEND = 0x003f |
.equ SRAM_START = 0x0060 |
.equ SRAM_SIZE = 1024 |
.equ RAMEND = 0x045f |
.equ XRAMEND = 0x0000 |
.equ E2END = 0x01ff |
.equ EEPROMEND = 0x01ff |
.equ EEADRBITS = 9 |
#pragma AVRPART MEMORY PROG_FLASH 8192 |
#pragma AVRPART MEMORY EEPROM 512 |
#pragma AVRPART MEMORY INT_SRAM SIZE 1024 |
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60 |
; ***** BOOTLOADER DECLARATIONS ****************************************** |
.equ NRWW_START_ADDR = 0xc00 |
.equ NRWW_STOP_ADDR = 0xfff |
.equ RWW_START_ADDR = 0x0 |
.equ RWW_STOP_ADDR = 0xbff |
.equ PAGESIZE = 32 |
.equ FIRSTBOOTSTART = 0xf80 |
.equ SECONDBOOTSTART = 0xf00 |
.equ THIRDBOOTSTART = 0xe00 |
.equ FOURTHBOOTSTART = 0xc00 |
.equ SMALLBOOTSTART = FIRSTBOOTSTART |
.equ LARGEBOOTSTART = FOURTHBOOTSTART |
; ***** INTERRUPT VECTORS ************************************************ |
.equ INT0addr = 0x0001 ; External Interrupt Request 0 |
.equ INT1addr = 0x0002 ; External Interrupt Request 1 |
.equ OC2addr = 0x0003 ; Timer/Counter2 Compare Match |
.equ OVF2addr = 0x0004 ; Timer/Counter2 Overflow |
.equ ICP1addr = 0x0005 ; Timer/Counter1 Capture Event |
.equ OC1Aaddr = 0x0006 ; Timer/Counter1 Compare Match A |
.equ OC1Baddr = 0x0007 ; Timer/Counter1 Compare Match B |
.equ OVF1addr = 0x0008 ; Timer/Counter1 Overflow |
.equ OVF0addr = 0x0009 ; Timer/Counter0 Overflow |
.equ SPIaddr = 0x000a ; Serial Transfer Complete |
.equ URXCaddr = 0x000b ; USART, Rx Complete |
.equ UDREaddr = 0x000c ; USART Data Register Empty |
.equ UTXCaddr = 0x000d ; USART, Tx Complete |
.equ ADCCaddr = 0x000e ; ADC Conversion Complete |
.equ ERDYaddr = 0x000f ; EEPROM Ready |
.equ ACIaddr = 0x0010 ; Analog Comparator |
.equ TWIaddr = 0x0011 ; 2-wire Serial Interface |
.equ SPMRaddr = 0x0012 ; Store Program Memory Ready |
.equ INT_VECTORS_SIZE = 19 ; size in words |
#pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED break |
#endif /* _M8DEF_INC_ */ |
; ***** END OF FILE ****************************************************** |
/contrib/toolchain/avra/includes/pwm2def.inc |
---|
0,0 → 1,1245 |
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** |
;***** Created: 2005-01-11 10:30 ******* Source: AT90PWM2.xml ************ |
;************************************************************************* |
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y |
;* |
;* Number : AVR000 |
;* File Name : "pwm2def.inc" |
;* Title : Register/Bit Definitions for the AT90PWM2 |
;* Date : 2005-01-11 |
;* Version : 2.14 |
;* Support E-mail : avr@atmel.com |
;* Target MCU : AT90PWM2 |
;* |
;* DESCRIPTION |
;* When including this file in the assembly program file, all I/O register |
;* names and I/O register bit names appearing in the data book can be used. |
;* In addition, the six registers forming the three data pointers X, Y and |
;* Z have been assigned names XL - ZH. Highest RAM address for Internal |
;* SRAM is also defined |
;* |
;* The Register names are represented by their hexadecimal address. |
;* |
;* The Register Bit names are represented by their bit number (0-7). |
;* |
;* Please observe the difference in using the bit names with instructions |
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" |
;* (skip if bit in register set/cleared). The following example illustrates |
;* this: |
;* |
;* in r16,PORTB ;read PORTB latch |
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) |
;* out PORTB,r16 ;output to PORTB |
;* |
;* in r16,TIFR ;read the Timer Interrupt Flag Register |
;* sbrc r16,TOV0 ;test the overflow flag (use bit#) |
;* rjmp TOV0_is_set ;jump if set |
;* ... ;otherwise do something else |
;************************************************************************* |
#ifndef _PWM2DEF_INC_ |
#define _PWM2DEF_INC_ |
#pragma partinc 0 |
; ***** SPECIFY DEVICE *************************************************** |
.device AT90PWM2 |
#pragma AVRPART ADMIN PART_NAME AT90PWM2 |
.equ SIGNATURE_000 = 0x1e |
.equ SIGNATURE_001 = 0x93 |
.equ SIGNATURE_002 = 0x81 |
#pragma AVRPART CORE CORE_VERSION V2E |
; ***** I/O REGISTER DEFINITIONS ***************************************** |
; NOTE: |
; Definitions marked "MEMORY MAPPED"are extended I/O ports |
; and cannot be used with IN/OUT instructions |
.equ PICR2H = 0xff ; MEMORY MAPPED |
.equ PICR2L = 0xfe ; MEMORY MAPPED |
.equ PFRC2B = 0xfd ; MEMORY MAPPED |
.equ PFRC2A = 0xfc ; MEMORY MAPPED |
.equ PCTL2 = 0xfb ; MEMORY MAPPED |
.equ PCNF2 = 0xfa ; MEMORY MAPPED |
.equ OCR2RBH = 0xf9 ; MEMORY MAPPED |
.equ OCR2RBL = 0xf8 ; MEMORY MAPPED |
.equ OCR2SBH = 0xf7 ; MEMORY MAPPED |
.equ OCR2SBL = 0xf6 ; MEMORY MAPPED |
.equ OCR2RAH = 0xf5 ; MEMORY MAPPED |
.equ OCR2RAL = 0xf4 ; MEMORY MAPPED |
.equ OCR2SAH = 0xf3 ; MEMORY MAPPED |
.equ OCR2SAL = 0xf2 ; MEMORY MAPPED |
.equ POM2 = 0xf1 ; MEMORY MAPPED |
.equ PSOC2 = 0xf0 ; MEMORY MAPPED |
.equ PICR1H = 0xef ; MEMORY MAPPED |
.equ PICR1L = 0xee ; MEMORY MAPPED |
.equ PFRC1B = 0xed ; MEMORY MAPPED |
.equ PFRC1A = 0xec ; MEMORY MAPPED |
.equ PCTL1 = 0xeb ; MEMORY MAPPED |
.equ PCNF1 = 0xea ; MEMORY MAPPED |
.equ OCR1RBH = 0xe9 ; MEMORY MAPPED |
.equ OCR1RBL = 0xe8 ; MEMORY MAPPED |
.equ OCR1SBH = 0xe7 ; MEMORY MAPPED |
.equ OCR1SBL = 0xe6 ; MEMORY MAPPED |
.equ OCR1RAH = 0xe5 ; MEMORY MAPPED |
.equ OCR1RAL = 0xe4 ; MEMORY MAPPED |
.equ OCR1SAH = 0xe3 ; MEMORY MAPPED |
.equ OCR1SAL = 0xe2 ; MEMORY MAPPED |
.equ PSOC1 = 0xe0 ; MEMORY MAPPED |
.equ PICR0H = 0xdf ; MEMORY MAPPED |
.equ PICR0L = 0xde ; MEMORY MAPPED |
.equ PFRC0B = 0xdd ; MEMORY MAPPED |
.equ PFRC0A = 0xdc ; MEMORY MAPPED |
.equ PCTL0 = 0xdb ; MEMORY MAPPED |
.equ PCNF0 = 0xda ; MEMORY MAPPED |
.equ OCR0RBH = 0xd9 ; MEMORY MAPPED |
.equ OCR0RBL = 0xd8 ; MEMORY MAPPED |
.equ OCR0SBH = 0xd7 ; MEMORY MAPPED |
.equ OCR0SBL = 0xd6 ; MEMORY MAPPED |
.equ OCR0RAH = 0xd5 ; MEMORY MAPPED |
.equ OCR0RAL = 0xd4 ; MEMORY MAPPED |
.equ OCR0SAH = 0xd3 ; MEMORY MAPPED |
.equ OCR0SAL = 0xd2 ; MEMORY MAPPED |
.equ PSOC0 = 0xd0 ; MEMORY MAPPED |
.equ EUDR = 0xce ; MEMORY MAPPED |
.equ MUBRRH = 0xcd ; MEMORY MAPPED |
.equ MUBRRL = 0xcc ; MEMORY MAPPED |
.equ EUCSRC = 0xca ; MEMORY MAPPED |
.equ EUCSRB = 0xc9 ; MEMORY MAPPED |
.equ EUCSRA = 0xc8 ; MEMORY MAPPED |
.equ UDR = 0xc6 ; MEMORY MAPPED |
.equ UBRRH = 0xc5 ; MEMORY MAPPED |
.equ UBRRL = 0xc4 ; MEMORY MAPPED |
.equ UCSRC = 0xc2 ; MEMORY MAPPED |
.equ UCSRB = 0xc1 ; MEMORY MAPPED |
.equ UCSRA = 0xc0 ; MEMORY MAPPED |
.equ AC2CON = 0xaf ; MEMORY MAPPED |
.equ AC1CON = 0xae ; MEMORY MAPPED |
.equ AC0CON = 0xad ; MEMORY MAPPED |
.equ DACH = 0xac ; MEMORY MAPPED |
.equ DACL = 0xab ; MEMORY MAPPED |
.equ DACON = 0xaa ; MEMORY MAPPED |
.equ PIM2 = 0xa5 ; MEMORY MAPPED |
.equ PIFR2 = 0xa4 ; MEMORY MAPPED |
.equ PIM1 = 0xa3 ; MEMORY MAPPED |
.equ PIFR1 = 0xa2 ; MEMORY MAPPED |
.equ PIM0 = 0xa1 ; MEMORY MAPPED |
.equ PIFR0 = 0xa0 ; MEMORY MAPPED |
.equ OCR1BH = 0x8b ; MEMORY MAPPED |
.equ OCR1BL = 0x8a ; MEMORY MAPPED |
.equ OCR1AH = 0x89 ; MEMORY MAPPED |
.equ OCR1AL = 0x88 ; MEMORY MAPPED |
.equ ICR1H = 0x87 ; MEMORY MAPPED |
.equ ICR1L = 0x86 ; MEMORY MAPPED |
.equ TCNT1H = 0x85 ; MEMORY MAPPED |
.equ TCNT1L = 0x84 ; MEMORY MAPPED |
.equ TCCR1C = 0x82 ; MEMORY MAPPED |
.equ TCCR1B = 0x81 ; MEMORY MAPPED |
.equ TCCR1A = 0x80 ; MEMORY MAPPED |
.equ DIDR1 = 0x7f ; MEMORY MAPPED |
.equ DIDR0 = 0x7e ; MEMORY MAPPED |
.equ ADMUX = 0x7c ; MEMORY MAPPED |
.equ ADCSRB = 0x7b ; MEMORY MAPPED |
.equ ADCSRA = 0x7a ; MEMORY MAPPED |
.equ ADCH = 0x79 ; MEMORY MAPPED |
.equ ADCL = 0x78 ; MEMORY MAPPED |
.equ AMP1CSR = 0x77 ; MEMORY MAPPED |
.equ AMP0CSR = 0x76 ; MEMORY MAPPED |
.equ TIMSK1 = 0x6f ; MEMORY MAPPED |
.equ TIMSK0 = 0x6e ; MEMORY MAPPED |
.equ EICRA = 0x69 ; MEMORY MAPPED |
.equ OSCCAL = 0x66 ; MEMORY MAPPED |
.equ PRR = 0x64 ; MEMORY MAPPED |
.equ CLKPR = 0x61 ; MEMORY MAPPED |
.equ WDTCSR = 0x60 ; MEMORY MAPPED |
.equ SREG = 0x3f |
.equ SPH = 0x3e |
.equ SPL = 0x3d |
.equ SPMCSR = 0x37 |
.equ MCUCR = 0x35 |
.equ MCUSR = 0x34 |
.equ SMCR = 0x33 |
.equ ACSR = 0x30 |
.equ SPDR = 0x2e |
.equ SPSR = 0x2d |
.equ SPCR = 0x2c |
.equ PLLCSR = 0x29 |
.equ OCR0B = 0x28 |
.equ OCR0A = 0x27 |
.equ TCNT0 = 0x26 |
.equ TCCR0B = 0x25 |
.equ TCCR0A = 0x24 |
.equ GTCCR = 0x23 |
.equ EEARH = 0x22 |
.equ EEARL = 0x21 |
.equ EEDR = 0x20 |
.equ EECR = 0x1f |
.equ GPIOR0 = 0x1e |
.equ EIMSK = 0x1d |
.equ EIFR = 0x1c |
.equ GPIOR3 = 0x1b |
.equ GPIOR2 = 0x1a |
.equ GPIOR1 = 0x19 |
.equ TIFR1 = 0x16 |
.equ TIFR0 = 0x15 |
.equ PORTE = 0x0e |
.equ DDRE = 0x0d |
.equ PINE = 0x0c |
.equ PORTD = 0x0b |
.equ DDRD = 0x0a |
.equ PIND = 0x09 |
.equ PORTC = 0x08 |
.equ DDRC = 0x07 |
.equ PINC = 0x06 |
.equ PORTB = 0x05 |
.equ DDRB = 0x04 |
.equ PINB = 0x03 |
; ***** BIT DEFINITIONS ************************************************** |
; ***** PORTB ************************ |
; PORTB - Port B Data Register |
.equ PORTB0 = 0 ; Port B Data Register bit 0 |
.equ PB0 = 0 ; For compatibility |
.equ PORTB1 = 1 ; Port B Data Register bit 1 |
.equ PB1 = 1 ; For compatibility |
.equ PORTB2 = 2 ; Port B Data Register bit 2 |
.equ PB2 = 2 ; For compatibility |
.equ PORTB3 = 3 ; Port B Data Register bit 3 |
.equ PB3 = 3 ; For compatibility |
.equ PORTB4 = 4 ; Port B Data Register bit 4 |
.equ PB4 = 4 ; For compatibility |
.equ PORTB5 = 5 ; Port B Data Register bit 5 |
.equ PB5 = 5 ; For compatibility |
.equ PORTB6 = 6 ; Port B Data Register bit 6 |
.equ PB6 = 6 ; For compatibility |
.equ PORTB7 = 7 ; Port B Data Register bit 7 |
.equ PB7 = 7 ; For compatibility |
; DDRB - Port B Data Direction Register |
.equ DDB0 = 0 ; Port B Data Direction Register bit 0 |
.equ DDB1 = 1 ; Port B Data Direction Register bit 1 |
.equ DDB2 = 2 ; Port B Data Direction Register bit 2 |
.equ DDB3 = 3 ; Port B Data Direction Register bit 3 |
.equ DDB4 = 4 ; Port B Data Direction Register bit 4 |
.equ DDB5 = 5 ; Port B Data Direction Register bit 5 |
.equ DDB6 = 6 ; Port B Data Direction Register bit 6 |
.equ DDB7 = 7 ; Port B Data Direction Register bit 7 |
; PINB - Port B Input Pins |
.equ PINB0 = 0 ; Port B Input Pins bit 0 |
.equ PINB1 = 1 ; Port B Input Pins bit 1 |
.equ PINB2 = 2 ; Port B Input Pins bit 2 |
.equ PINB3 = 3 ; Port B Input Pins bit 3 |
.equ PINB4 = 4 ; Port B Input Pins bit 4 |
.equ PINB5 = 5 ; Port B Input Pins bit 5 |
.equ PINB6 = 6 ; Port B Input Pins bit 6 |
.equ PINB7 = 7 ; Port B Input Pins bit 7 |
; ***** PORTD ************************ |
; PORTD - Port D Data Register |
.equ PORTD0 = 0 ; Port D Data Register bit 0 |
.equ PD0 = 0 ; For compatibility |
.equ PORTD1 = 1 ; Port D Data Register bit 1 |
.equ PD1 = 1 ; For compatibility |
.equ PORTD2 = 2 ; Port D Data Register bit 2 |
.equ PD2 = 2 ; For compatibility |
.equ PORTD3 = 3 ; Port D Data Register bit 3 |
.equ PD3 = 3 ; For compatibility |
.equ PORTD4 = 4 ; Port D Data Register bit 4 |
.equ PD4 = 4 ; For compatibility |
.equ PORTD5 = 5 ; Port D Data Register bit 5 |
.equ PD5 = 5 ; For compatibility |
.equ PORTD6 = 6 ; Port D Data Register bit 6 |
.equ PD6 = 6 ; For compatibility |
.equ PORTD7 = 7 ; Port D Data Register bit 7 |
.equ PD7 = 7 ; For compatibility |
; DDRD - Port D Data Direction Register |
.equ DDD0 = 0 ; Port D Data Direction Register bit 0 |
.equ DDD1 = 1 ; Port D Data Direction Register bit 1 |
.equ DDD2 = 2 ; Port D Data Direction Register bit 2 |
.equ DDD3 = 3 ; Port D Data Direction Register bit 3 |
.equ DDD4 = 4 ; Port D Data Direction Register bit 4 |
.equ DDD5 = 5 ; Port D Data Direction Register bit 5 |
.equ DDD6 = 6 ; Port D Data Direction Register bit 6 |
.equ DDD7 = 7 ; Port D Data Direction Register bit 7 |
; PIND - Port D Input Pins |
.equ PIND0 = 0 ; Port D Input Pins bit 0 |
.equ PIND1 = 1 ; Port D Input Pins bit 1 |
.equ PIND2 = 2 ; Port D Input Pins bit 2 |
.equ PIND3 = 3 ; Port D Input Pins bit 3 |
.equ PIND4 = 4 ; Port D Input Pins bit 4 |
.equ PIND5 = 5 ; Port D Input Pins bit 5 |
.equ PIND6 = 6 ; Port D Input Pins bit 6 |
.equ PIND7 = 7 ; Port D Input Pins bit 7 |
; ***** BOOT_LOAD ******************** |
; SPMCSR - Store Program Memory Control Register |
.equ SPMCR = SPMCSR ; For compatibility |
.equ SPMEN = 0 ; Store Program Memory Enable |
.equ PGERS = 1 ; Page Erase |
.equ PGWRT = 2 ; Page Write |
.equ BLBSET = 3 ; Boot Lock Bit Set |
.equ RWWSRE = 4 ; Read While Write section read enable |
.equ ASRE = RWWSRE ; For compatibility |
.equ RWWSB = 6 ; Read While Write Section Busy |
.equ ASB = RWWSB ; For compatibility |
.equ SPMIE = 7 ; SPM Interrupt Enable |
; ***** EEPROM *********************** |
; EEDR - EEPROM Data Register |
.equ EEDR0 = 0 ; EEPROM Data Register bit 0 |
.equ EEDR1 = 1 ; EEPROM Data Register bit 1 |
.equ EEDR2 = 2 ; EEPROM Data Register bit 2 |
.equ EEDR3 = 3 ; EEPROM Data Register bit 3 |
.equ EEDR4 = 4 ; EEPROM Data Register bit 4 |
.equ EEDR5 = 5 ; EEPROM Data Register bit 5 |
.equ EEDR6 = 6 ; EEPROM Data Register bit 6 |
.equ EEDR7 = 7 ; EEPROM Data Register bit 7 |
; EECR - EEPROM Control Register |
.equ EERE = 0 ; EEPROM Read Enable |
.equ EEWE = 1 ; EEPROM Write Enable |
.equ EEMWE = 2 ; EEPROM Master Write Enable |
.equ EERIE = 3 ; EEPROM Ready Interrupt Enable |
; ***** PSC0 ************************* |
; PICR0H - PSC 0 Input Capture Register High |
.equ PICR0_8 = 0 ; |
.equ PICR0_9 = 1 ; |
.equ PICR0_10 = 2 ; |
.equ PICR0_11 = 3 ; |
; PICR0L - PSC 0 Input Capture Register Low |
.equ PICR0_0 = 0 ; |
.equ PICR0_1 = 1 ; |
.equ PICR0_2 = 2 ; |
.equ PICR0_3 = 3 ; |
.equ PICR0_4 = 4 ; |
.equ PICR0_5 = 5 ; |
.equ PICR0_6 = 6 ; |
.equ PICR0_7 = 7 ; |
; PFRC0B - PSC 0 Input B Control |
.equ PRFM0B0 = 0 ; PSC 0 Retrigger and Fault Mode for Part B |
.equ PRFM0B1 = 1 ; PSC 0 Retrigger and Fault Mode for Part B |
.equ PRFM0B2 = 2 ; PSC 0 Retrigger and Fault Mode for Part B |
.equ PRFM0B3 = 3 ; PSC 0 Retrigger and Fault Mode for Part B |
.equ PFLTE0B = 4 ; PSC 0 Filter Enable on Input Part B |
.equ PELEV0B = 5 ; PSC 0 Edge Level Selector on Input Part B |
.equ PISEL0B = 6 ; PSC 0 Input Select for Part B |
.equ PCAE0B = 7 ; PSC 0 Capture Enable Input Part B |
; PFRC0A - PSC 0 Input A Control |
.equ PRFM0A0 = 0 ; PSC 0 Retrigger and Fault Mode for Part A |
.equ PRFM0A1 = 1 ; PSC 0 Retrigger and Fault Mode for Part A |
.equ PRFM0A2 = 2 ; PSC 0 Retrigger and Fault Mode for Part A |
.equ PRFM0A3 = 3 ; PSC 0 Retrigger and Fault Mode for Part A |
.equ PFLTE0A = 4 ; PSC 0 Filter Enable on Input Part A |
.equ PELEV0A = 5 ; PSC 0 Edge Level Selector on Input Part A |
.equ PISEL0A = 6 ; PSC 0 Input Select for Part A |
.equ PCAE0A = 7 ; PSC 0 Capture Enable Input Part A |
; PCTL0 - PSC 0 Control Register |
.equ PRUN0 = 0 ; PSC 0 Run |
.equ PCCYC0 = 1 ; PSC0 Complete Cycle |
.equ PARUN0 = 2 ; PSC0 Auto Run |
.equ PAOC0A = 3 ; PSC 0 Asynchronous Output Control A |
.equ PAOC0B = 4 ; PSC 0 Asynchronous Output Control B |
.equ PBFM0 = 5 ; PSC 0 Balance Flank Width Modulation |
.equ PPRE00 = 6 ; PSC 0 Prescaler Select 0 |
.equ PPRE01 = 7 ; PSC 0 Prescaler Select 1 |
; PCNF0 - PSC 0 Configuration Register |
.equ PCLKSEL0 = 1 ; PSC 0 Input Clock Select |
.equ POP0 = 2 ; PSC 0 Output Polarity |
.equ PMODE00 = 3 ; PSC 0 Mode |
.equ PMODE01 = 4 ; PSC 0 Mode |
.equ PLOCK0 = 5 ; PSC 0 Lock |
.equ PALOCK0 = 6 ; PSC 0 Autolock |
.equ PFIFTY0 = 7 ; PSC 0 Fifty |
; OCR0RBH - Output Compare RB Register High |
.equ OCR0RB_8 = 0 ; |
.equ OCR0RB_9 = 1 ; |
.equ OCR0RB_00 = 2 ; |
.equ OCR0RB_01 = 3 ; |
.equ OCR0RB_02 = 4 ; |
.equ OCR0RB_03 = 5 ; |
.equ OCR0RB_04 = 6 ; |
.equ OCR0RB_05 = 7 ; |
; OCR0RBL - Output Compare RB Register Low |
.equ OCR0RB_0 = 0 ; |
.equ OCR0RB_1 = 1 ; |
.equ OCR0RB_2 = 2 ; |
.equ OCR0RB_3 = 3 ; |
.equ OCR0RB_4 = 4 ; |
.equ OCR0RB_5 = 5 ; |
.equ OCR0RB_6 = 6 ; |
.equ OCR0RB_7 = 7 ; |
; OCR0SBH - Output Compare SB Register High |
.equ OCR0SB_8 = 0 ; |
.equ OCR0SB_9 = 1 ; |
.equ OCR0SB_00 = 2 ; |
.equ OCR0SB_01 = 3 ; |
; OCR0SBL - Output Compare SB Register Low |
.equ OCR0SB_0 = 0 ; |
.equ OCR0SB_1 = 1 ; |
.equ OCR0SB_2 = 2 ; |
.equ OCR0SB_3 = 3 ; |
.equ OCR0SB_4 = 4 ; |
.equ OCR0SB_5 = 5 ; |
.equ OCR0SB_6 = 6 ; |
.equ OCR0SB_7 = 7 ; |
; OCR0RAH - Output Compare RA Register High |
.equ OCR0RA_8 = 0 ; |
.equ OCR0RA_9 = 1 ; |
.equ OCR0RA_00 = 2 ; |
.equ OCR0RA_01 = 3 ; |
; OCR0RAL - Output Compare RA Register Low |
.equ OCR0RA_0 = 0 ; |
.equ OCR0RA_1 = 1 ; |
.equ OCR0RA_2 = 2 ; |
.equ OCR0RA_3 = 3 ; |
.equ OCR0RA_4 = 4 ; |
.equ OCR0RA_5 = 5 ; |
.equ OCR0RA_6 = 6 ; |
.equ OCR0RA_7 = 7 ; |
; OCR0SAH - Output Compare SA Register High |
.equ OCR0SA_8 = 0 ; |
.equ OCR0SA_9 = 1 ; |
.equ OCR0SA_00 = 2 ; |
.equ OCR0SA_01 = 3 ; |
; OCR0SAL - Output Compare SA Register Low |
.equ OCR0SA_0 = 0 ; |
.equ OCR0SA_1 = 1 ; |
.equ OCR0SA_2 = 2 ; |
.equ OCR0SA_3 = 3 ; |
.equ OCR0SA_4 = 4 ; |
.equ OCR0SA_5 = 5 ; |
.equ OCR0SA_6 = 6 ; |
.equ OCR0SA_7 = 7 ; |
; PSOC0 - PSC0 Synchro and Output Configuration |
.equ POEN0A = 0 ; PSCOUT00 Output Enable |
.equ POEN0B = 2 ; PSCOUT01 Output Enable |
.equ PSYNC00 = 4 ; Synchronization Out for ADC Selection |
.equ PSYNC01 = 5 ; Synchronization Out for ADC Selection |
; PIM0 - PSC0 Interrupt Mask Register |
.equ PEOPE0 = 0 ; End of Cycle Interrupt Enable |
.equ PEVE0A = 3 ; External Event A Interrupt Enable |
.equ PEVE0B = 4 ; External Event B Interrupt Enable |
.equ PSEIE0 = 5 ; PSC 0 Synchro Error Interrupt Enable |
; PIFR0 - PSC0 Interrupt Flag Register |
.equ PEOP0 = 0 ; End of PSC0 Interrupt |
.equ PRN00 = 1 ; Ramp Number |
.equ PRN01 = 2 ; Ramp Number |
.equ PEV0A = 3 ; External Event A Interrupt |
.equ PEV0B = 4 ; External Event B Interrupt |
.equ PSEI0 = 5 ; PSC 0 Synchro Error Interrupt |
; ***** PSC2 ************************* |
; PICR2H - PSC 2 Input Capture Register High |
.equ PICR2_8 = 0 ; |
.equ PICR2_9 = 1 ; |
.equ PICR2_10 = 2 ; |
.equ PICR2_11 = 3 ; |
; PICR2L - PSC 2 Input Capture Register Low |
.equ PICR2_0 = 0 ; |
.equ PICR2_1 = 1 ; |
.equ PICR2_2 = 2 ; |
.equ PICR2_3 = 3 ; |
.equ PICR2_4 = 4 ; |
.equ PICR2_5 = 5 ; |
.equ PICR2_6 = 6 ; |
.equ PICR2_7 = 7 ; |
; PFRC2B - PSC 2 Input B Control |
.equ PRFM2B0 = 0 ; PSC 2 Retrigger and Fault Mode for Part B |
.equ PRFM2B1 = 1 ; PSC 2 Retrigger and Fault Mode for Part B |
.equ PRFM2B2 = 2 ; PSC 2 Retrigger and Fault Mode for Part B |
.equ PRFM2B3 = 3 ; PSC 2 Retrigger and Fault Mode for Part B |
.equ PFLTE2B = 4 ; PSC 2 Filter Enable on Input Part B |
.equ PELEV2B = 5 ; PSC 2 Edge Level Selector on Input Part B |
.equ PISEL2B = 6 ; PSC 2 Input Select for Part B |
.equ PCAE2B = 7 ; PSC 2 Capture Enable Input Part B |
; PFRC2A - PSC 2 Input B Control |
.equ PRFM2A0 = 0 ; PSC 2 Retrigger and Fault Mode for Part A |
.equ PRFM2A1 = 1 ; PSC 2 Retrigger and Fault Mode for Part A |
.equ PRFM2A2 = 2 ; PSC 2 Retrigger and Fault Mode for Part A |
.equ PRFM2A3 = 3 ; PSC 2 Retrigger and Fault Mode for Part A |
.equ PFLTE2A = 4 ; PSC 2 Filter Enable on Input Part A |
.equ PELEV2A = 5 ; PSC 2 Edge Level Selector on Input Part A |
.equ PISEL2A = 6 ; PSC 2 Input Select for Part A |
.equ PCAE2A = 7 ; PSC 2 Capture Enable Input Part A |
; PCTL2 - PSC 2 Control Register |
.equ PRUN2 = 0 ; PSC 2 Run |
.equ PCCYC2 = 1 ; PSC2 Complete Cycle |
.equ PARUN2 = 2 ; PSC2 Auto Run |
.equ PAOC2A = 3 ; PSC 2 Asynchronous Output Control A |
.equ PAOC2B = 4 ; PSC 2 Asynchronous Output Control B |
.equ PBFM2 = 5 ; Balance Flank Width Modulation |
.equ PPRE20 = 6 ; PSC 2 Prescaler Select 0 |
.equ PPRE21 = 7 ; PSC 2 Prescaler Select 1 |
; PCNF2 - PSC 2 Configuration Register |
.equ POME2 = 0 ; PSC 2 Output Matrix Enable |
.equ PCLKSEL2 = 1 ; PSC 2 Input Clock Select |
.equ POP2 = 2 ; PSC 2 Output Polarity |
.equ PMODE20 = 3 ; PSC 2 Mode |
.equ PMODE21 = 4 ; PSC 2 Mode |
.equ PLOCK2 = 5 ; PSC 2 Lock |
.equ PALOCK2 = 6 ; PSC 2 Autolock |
.equ PFIFTY2 = 7 ; PSC 2 Fifty |
; OCR2RBH - Output Compare RB Register High |
.equ OCR2RB_8 = 0 ; |
.equ OCR2RB_9 = 1 ; |
.equ OCR2RB_10 = 2 ; |
.equ OCR2RB_11 = 3 ; |
.equ OCR2RB_12 = 4 ; |
.equ OCR2RB_13 = 5 ; |
.equ OCR2RB_14 = 6 ; |
.equ OCR2RB_15 = 7 ; |
; OCR2RBL - Output Compare RB Register Low |
.equ OCR2RB_0 = 0 ; |
.equ OCR2RB_1 = 1 ; |
.equ OCR2RB_2 = 2 ; |
.equ OCR2RB_3 = 3 ; |
.equ OCR2RB_4 = 4 ; |
.equ OCR2RB_5 = 5 ; |
.equ OCR2RB_6 = 6 ; |
.equ OCR2RB_7 = 7 ; |
; OCR2SBH - Output Compare SB Register High |
.equ OCR2SB_8 = 0 ; |
.equ OCR2SB_9 = 1 ; |
.equ OCR2SB_10 = 2 ; |
.equ OCR2SB_11 = 3 ; |
; OCR2SBL - Output Compare SB Register Low |
.equ OCR2SB_0 = 0 ; |
.equ OCR2SB_1 = 1 ; |
.equ OCR2SB_2 = 2 ; |
.equ OCR2SB_3 = 3 ; |
.equ OCR2SB_4 = 4 ; |
.equ OCR2SB_5 = 5 ; |
.equ OCR2SB_6 = 6 ; |
.equ OCR2SB_7 = 7 ; |
; OCR2RAH - Output Compare RA Register High |
.equ OCR2RA_8 = 0 ; |
.equ OCR2RA_9 = 1 ; |
.equ OCR2RA_10 = 2 ; |
.equ OCR2RA_11 = 3 ; |
; OCR2RAL - Output Compare RA Register Low |
.equ OCR2RA_0 = 0 ; |
.equ OCR2RA_1 = 1 ; |
.equ OCR2RA_2 = 2 ; |
.equ OCR2RA_3 = 3 ; |
.equ OCR2RA_4 = 4 ; |
.equ OCR2RA_5 = 5 ; |
.equ OCR2RA_6 = 6 ; |
.equ OCR2RA_7 = 7 ; |
; OCR2SAH - Output Compare SA Register High |
.equ OCR2SA_8 = 0 ; |
.equ OCR2SA_9 = 1 ; |
.equ OCR2SA_10 = 2 ; |
.equ OCR2SA_11 = 3 ; |
; OCR2SAL - Output Compare SA Register Low |
.equ OCR2SA_0 = 0 ; |
.equ OCR2SA_1 = 1 ; |
.equ OCR2SA_2 = 2 ; |
.equ OCR2SA_3 = 3 ; |
.equ OCR2SA_4 = 4 ; |
.equ OCR2SA_5 = 5 ; |
.equ OCR2SA_6 = 6 ; |
.equ OCR2SA_7 = 7 ; |
; POM2 - PSC 2 Output Matrix |
.equ POMV2A0 = 0 ; Output Matrix Output A Ramp 0 |
.equ POMV2A1 = 1 ; Output Matrix Output A Ramp 1 |
.equ POMV2A2 = 2 ; Output Matrix Output A Ramp 2 |
.equ POMV2A3 = 3 ; Output Matrix Output A Ramp 3 |
.equ POMV2B0 = 4 ; Output Matrix Output B Ramp 0 |
.equ POMV2B1 = 5 ; Output Matrix Output B Ramp 2 |
.equ POMV2B2 = 6 ; Output Matrix Output B Ramp 2 |
.equ POMV2B3 = 7 ; Output Matrix Output B Ramp 3 |
; PSOC2 - PSC2 Synchro and Output Configuration |
.equ POEN2A = 0 ; PSCOUT20 Output Enable |
.equ POEN2C = 1 ; PSCOUT22 Output Enable |
.equ POEN2B = 2 ; PSCOUT21 Output Enable |
.equ POEN2D = 3 ; PSCOUT23 Output Enable |
.equ PSYNC2_0 = 4 ; Synchronization Out for ADC Selection |
.equ PSYNC2_1 = 5 ; Synchronization Out for ADC Selection |
.equ POS22 = 6 ; PSC 2 Output 22 Select |
.equ POS23 = 7 ; PSC 2 Output 23 Select |
; PIM2 - PSC2 Interrupt Mask Register |
.equ PEOPE2 = 0 ; End of Cycle Interrupt Enable |
.equ PEVE2A = 3 ; External Event A Interrupt Enable |
.equ PEVE2B = 4 ; External Event B Interrupt Enable |
.equ PSEIE2 = 5 ; PSC 2 Synchro Error Interrupt Enable |
; PIFR2 - PSC2 Interrupt Flag Register |
.equ PEOP2 = 0 ; End of PSC2 Interrupt |
.equ PRN20 = 1 ; Ramp Number |
.equ PRN21 = 2 ; Ramp Number |
.equ PEV2A = 3 ; External Event A Interrupt |
.equ PEV2B = 4 ; External Event B Interrupt |
.equ PSEI2 = 5 ; PSC 2 Synchro Error Interrupt |
; ***** EUSART *********************** |
; EUDR - EUSART I/O Data Register |
.equ EUDR0 = 0 ; EUSART I/O Data Register bit 0 |
.equ EUDR1 = 1 ; EUSART I/O Data Register bit 1 |
.equ EUDR2 = 2 ; EUSART I/O Data Register bit 2 |
.equ EUDR3 = 3 ; EUSART I/O Data Register bit 3 |
.equ EUDR4 = 4 ; EUSART I/O Data Register bit 4 |
.equ EUDR5 = 5 ; EUSART I/O Data Register bit 5 |
.equ EUDR6 = 6 ; EUSART I/O Data Register bit 6 |
.equ EUDR7 = 7 ; EUSART I/O Data Register bit 7 |
; EUCSRA - EUSART Control and Status Register A |
.equ URxS0 = 0 ; EUSART Control and Status Register A Bit 0 |
.equ URxS1 = 1 ; EUSART Control and Status Register A Bit 1 |
.equ URxS2 = 2 ; EUSART Control and Status Register A Bit 2 |
.equ URxS3 = 3 ; EUSART Control and Status Register A Bit 3 |
.equ UTxS0 = 4 ; EUSART Control and Status Register A Bit 4 |
.equ UTxS1 = 5 ; EUSART Control and Status Register A Bit 5 |
.equ UTxS2 = 6 ; EUSART Control and Status Register A Bit 6 |
.equ UTxS3 = 7 ; EUSART Control and Status Register A Bit 7 |
; EUCSRB - EUSART Control Register B |
.equ BODR = 0 ; Order Bit |
.equ EMCH = 1 ; Manchester Mode Bit |
.equ EUSBS = 3 ; EUSBS Enable Bit |
.equ EUSART = 4 ; EUSART Enable Bit |
; EUCSRC - EUSART Status Register C |
.equ STP0 = 0 ; Stop Bit 0 |
.equ STP1 = 1 ; Stop Bit 1 |
.equ F1617 = 2 ; F1617 Bit |
.equ FEM = 3 ; Frame Error Manchester Bit |
; MUBRRH - Manchester Receiver Baud Rate Register High Byte |
.equ MUBRR8 = 0 ; Manchester Receiver Baud Rate Register Bit 8 |
.equ MUBRR9 = 1 ; Manchester Receiver Baud Rate Register Bit 9 |
.equ MUBRR10 = 2 ; Manchester Receiver Baud Rate Register Bit 10 |
.equ MUBRR11 = 3 ; Manchester Receiver Baud Rate Register Bit 11 |
.equ MUBRR12 = 4 ; Manchester Receiver Baud Rate Register Bit 12 |
.equ MUBRR13 = 5 ; Manchester Receiver Baud Rate Register Bit 13 |
.equ MUBRR14 = 6 ; Manchester Receiver Baud Rate Register Bit 14 |
.equ MUBRR15 = 7 ; Manchester Receiver Baud Rate Register Bit 15 |
; MUBRRL - Manchester Receiver Baud Rate Register Low Byte |
.equ MUBRR0 = 0 ; Manchester Receiver Baud Rate Register Bit 0 |
.equ MUBRR1 = 1 ; Manchester Receiver Baud Rate Register Bit 1 |
.equ MUBRR2 = 2 ; Manchester Receiver Baud Rate Register Bit 2 |
.equ MUBRR3 = 3 ; Manchester Receiver Baud Rate Register Bit 3 |
.equ MUBRR4 = 4 ; Manchester Receiver Baud Rate Register Bit 4 |
.equ MUBRR5 = 5 ; Manchester Receiver Baud Rate Register Bit 5 |
.equ MUBRR6 = 6 ; Manchester Receiver Baud Rate Register Bit 6 |
.equ MUBRR7 = 7 ; Manchester Receiver Baud Rate Register Bit 7 |
; ***** ANALOG_COMPARATOR ************ |
; AC0CON - Analog Comparator 0 Control Register |
.equ AC0M0 = 0 ; Analog Comparator 0 Multiplexer Register |
.equ AC0M1 = 1 ; Analog Comparator 0 Multiplexer Regsiter |
.equ AC0M2 = 2 ; Analog Comparator 0 Multiplexer Register |
.equ AC0IS0 = 4 ; Analog Comparator 0 Interrupt Select Bit |
.equ AC0IS1 = 5 ; Analog Comparator 0 Interrupt Select Bit |
.equ AC0IE = 6 ; Analog Comparator 0 Interrupt Enable Bit |
.equ AC0EN = 7 ; Analog Comparator 0 Enable Bit |
; AC1CON - Analog Comparator 1 Control Register |
.equ AC1M0 = 0 ; Analog Comparator 1 Multiplexer Register |
.equ AC1M1 = 1 ; Analog Comparator 1 Multiplexer Regsiter |
.equ AC1M2 = 2 ; Analog Comparator 1 Multiplexer Register |
.equ AC1ICE = 3 ; Analog Comparator 1 Interrupt Capture Enable Bit |
.equ AC1IS0 = 4 ; Analog Comparator 1 Interrupt Select Bit |
.equ AC1IS1 = 5 ; Analog Comparator 1 Interrupt Select Bit |
.equ AC1IE = 6 ; Analog Comparator 1 Interrupt Enable Bit |
.equ AC1EN = 7 ; Analog Comparator 1 Enable Bit |
; AC2CON - Analog Comparator 2 Control Register |
.equ AC2M0 = 0 ; Analog Comparator 2 Multiplexer Register |
.equ AC2M1 = 1 ; Analog Comparator 2 Multiplexer Regsiter |
.equ AC2M2 = 2 ; Analog Comparator 2 Multiplexer Register |
.equ AC2SADE = 3 ; Analog Comparator 2 Start A/D Conversion Enable Bit |
.equ AC2IS0 = 4 ; Analog Comparator 2 Interrupt Select Bit |
.equ AC2IS1 = 5 ; Analog Comparator 2 Interrupt Select Bit |
.equ AC2IE = 6 ; Analog Comparator 2 Interrupt Enable Bit |
.equ AC2EN = 7 ; Analog Comparator 2 Enable Bit |
; ***** DA_CONVERTER ***************** |
; DACH - DAC Data Register High Byte |
.equ DACH0 = 0 ; DAC Data Register High Byte Bit 0 |
.equ DACH1 = 1 ; DAC Data Register High Byte Bit 1 |
.equ DACH2 = 2 ; DAC Data Register High Byte Bit 2 |
.equ DACH3 = 3 ; DAC Data Register High Byte Bit 3 |
.equ DACH4 = 4 ; DAC Data Register High Byte Bit 4 |
.equ DACH5 = 5 ; DAC Data Register High Byte Bit 5 |
.equ DACH6 = 6 ; DAC Data Register High Byte Bit 6 |
.equ DACH7 = 7 ; DAC Data Register High Byte Bit 7 |
; DACL - DAC Data Register Low Byte |
.equ DACL1 = 1 ; DAC Data Register Low Byte Bit 1 |
.equ DACL2 = 2 ; DAC Data Register Low Byte Bit 2 |
.equ DACL3 = 3 ; DAC Data Register Low Byte Bit 3 |
.equ DACL4 = 4 ; DAC Data Register Low Byte Bit 4 |
.equ DACL5 = 5 ; DAC Data Register Low Byte Bit 5 |
.equ DACL6 = 6 ; DAC Data Register Low Byte Bit 6 |
.equ DACL7 = 7 ; DAC Data Register Low Byte Bit 7 |
; DACON - DAC Control Register |
.equ DAEN = 0 ; DAC Enable Bit |
.equ DAOE = 1 ; DAC Output Enable Bit |
.equ DALA = 2 ; DAC Left Adjust |
.equ DATS0 = 4 ; DAC Trigger Selection Bit 0 |
.equ DATS1 = 5 ; DAC Trigger Selection Bit 1 |
.equ DATS2 = 6 ; DAC Trigger Selection Bit 2 |
.equ DAATE = 7 ; DAC Auto Trigger Enable Bit |
; ***** CPU ************************** |
; SREG - Status Register |
.equ SREG_C = 0 ; Carry Flag |
.equ SREG_Z = 1 ; Zero Flag |
.equ SREG_N = 2 ; Negative Flag |
.equ SREG_V = 3 ; Two's Complement Overflow Flag |
.equ SREG_S = 4 |
.equ SREG_H = 5 ; Half Carry Flag |
.equ SREG_T = 6 ; Bit Copy Storage |
.equ SREG_I = 7 ; Global Interrupt Enable |
; MCUCR - MCU Control Register |
.equ IVCE = 0 ; Interrupt Vector Change Enable |
.equ IVSEL = 1 ; Interrupt Vector Select |
.equ PUD = 4 ; Pull-up disable |
.equ SPIPS = 7 ; SPI Pin Select |
; MCUSR - MCU Status Register |
.equ PORF = 0 ; Power-on reset flag |
.equ EXTRF = 1 ; External Reset Flag |
.equ BORF = 2 ; Brown-out Reset Flag |
.equ WDRF = 3 ; Watchdog Reset Flag |
; OSCCAL - Oscillator Calibration Value |
.equ CAL0 = 0 ; Oscillator Calibration Value Bit0 |
.equ CAL1 = 1 ; Oscillator Calibration Value Bit1 |
.equ CAL2 = 2 ; Oscillator Calibration Value Bit2 |
.equ CAL3 = 3 ; Oscillator Calibration Value Bit3 |
.equ CAL4 = 4 ; Oscillator Calibration Value Bit4 |
.equ CAL5 = 5 ; Oscillator Calibration Value Bit5 |
.equ CAL6 = 6 ; Oscillator Calibration Value Bit6 |
; CLKPR - |
.equ CLKPS0 = 0 ; |
.equ CLKPS1 = 1 ; |
.equ CLKPS2 = 2 ; |
.equ CLKPS3 = 3 ; |
.equ CPKPCE = 7 ; |
; SMCR - Sleep Mode Control Register |
.equ SE = 0 ; Sleep Enable |
.equ SM0 = 1 ; Sleep Mode Select bit 0 |
.equ SM1 = 2 ; Sleep Mode Select bit 1 |
.equ SM2 = 3 ; Sleep Mode Select bit 2 |
; GPIOR3 - General Purpose IO Register 3 |
.equ GPIOR30 = 0 ; General Purpose IO Register 3 bit 0 |
.equ GPIOR31 = 1 ; General Purpose IO Register 3 bit 1 |
.equ GPIOR32 = 2 ; General Purpose IO Register 3 bit 2 |
.equ GPIOR33 = 3 ; General Purpose IO Register 3 bit 3 |
.equ GPIOR34 = 4 ; General Purpose IO Register 3 bit 4 |
.equ GPIOR35 = 5 ; General Purpose IO Register 3 bit 5 |
.equ GPIOR36 = 6 ; General Purpose IO Register 3 bit 6 |
.equ GPIOR37 = 7 ; General Purpose IO Register 3 bit 7 |
; GPIOR2 - General Purpose IO Register 2 |
.equ GPIOR20 = 0 ; General Purpose IO Register 2 bit 0 |
.equ GPIOR21 = 1 ; General Purpose IO Register 2 bit 1 |
.equ GPIOR22 = 2 ; General Purpose IO Register 2 bit 2 |
.equ GPIOR23 = 3 ; General Purpose IO Register 2 bit 3 |
.equ GPIOR24 = 4 ; General Purpose IO Register 2 bit 4 |
.equ GPIOR25 = 5 ; General Purpose IO Register 2 bit 5 |
.equ GPIOR26 = 6 ; General Purpose IO Register 2 bit 6 |
.equ GPIOR27 = 7 ; General Purpose IO Register 2 bit 7 |
; GPIOR1 - General Purpose IO Register 1 |
.equ GPIOR10 = 0 ; General Purpose IO Register 1 bit 0 |
.equ GPIOR11 = 1 ; General Purpose IO Register 1 bit 1 |
.equ GPIOR12 = 2 ; General Purpose IO Register 1 bit 2 |
.equ GPIOR13 = 3 ; General Purpose IO Register 1 bit 3 |
.equ GPIOR14 = 4 ; General Purpose IO Register 1 bit 4 |
.equ GPIOR15 = 5 ; General Purpose IO Register 1 bit 5 |
.equ GPIOR16 = 6 ; General Purpose IO Register 1 bit 6 |
.equ GPIOR17 = 7 ; General Purpose IO Register 1 bit 7 |
; GPIOR0 - General Purpose IO Register 0 |
.equ GPIOR00 = 0 ; General Purpose IO Register 0 bit 0 |
.equ GPIOR01 = 1 ; General Purpose IO Register 0 bit 1 |
.equ GPIOR02 = 2 ; General Purpose IO Register 0 bit 2 |
.equ GPIOR03 = 3 ; General Purpose IO Register 0 bit 3 |
.equ GPIOR04 = 4 ; General Purpose IO Register 0 bit 4 |
.equ GPIOR05 = 5 ; General Purpose IO Register 0 bit 5 |
.equ GPIOR06 = 6 ; General Purpose IO Register 0 bit 6 |
.equ GPIOR07 = 7 ; General Purpose IO Register 0 bit 7 |
; PLLCSR - PLL Control And Status Register |
.equ PLOCK = 0 ; PLL Lock Detector |
.equ PLLE = 1 ; PLL Enable |
.equ PCKE = 2 ; PCK Enable |
; ***** PORTE ************************ |
; PORTE - Port E Data Register |
.equ PORTE0 = 0 ; |
.equ PE0 = 0 ; For compatibility |
.equ PORTE1 = 1 ; |
.equ PE1 = 1 ; For compatibility |
.equ PORTE2 = 2 ; |
.equ PE2 = 2 ; For compatibility |
; DDRE - Port E Data Direction Register |
.equ DDE0 = 0 ; |
.equ DDE1 = 1 ; |
.equ DDE2 = 2 ; |
; PINE - Port E Input Pins |
.equ PINE0 = 0 ; |
.equ PINE1 = 1 ; |
.equ PINE2 = 2 ; |
; ***** TIMER_COUNTER_0 ************** |
; TIMSK0 - Timer/Counter0 Interrupt Mask Register |
.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable |
.equ OCIE0A = 1 ; Timer/Counter0 Output Compare Match A Interrupt Enable |
.equ OCIE0B = 2 ; Timer/Counter0 Output Compare Match B Interrupt Enable |
; TIFR0 - Timer/Counter0 Interrupt Flag register |
.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag |
.equ OCF0A = 1 ; Timer/Counter0 Output Compare Flag 0A |
.equ OCF0B = 2 ; Timer/Counter0 Output Compare Flag 0B |
; TCCR0A - Timer/Counter Control Register A |
.equ WGM00 = 0 ; Waveform Generation Mode |
.equ WGM01 = 1 ; Waveform Generation Mode |
.equ COM0B0 = 4 ; Compare Output Mode, Fast PWm |
.equ COM0B1 = 5 ; Compare Output Mode, Fast PWm |
.equ COM0A0 = 6 ; Compare Output Mode, Phase Correct PWM Mode |
.equ COM0A1 = 7 ; Compare Output Mode, Phase Correct PWM Mode |
; TCCR0B - Timer/Counter Control Register B |
.equ CS00 = 0 ; Clock Select |
.equ CS01 = 1 ; Clock Select |
.equ CS02 = 2 ; Clock Select |
.equ WGM02 = 3 ; |
.equ FOC0B = 6 ; Force Output Compare B |
.equ FOC0A = 7 ; Force Output Compare A |
; TCNT0 - Timer/Counter0 |
.equ TCNT0_0 = 0 ; |
.equ TCNT0_1 = 1 ; |
.equ TCNT0_2 = 2 ; |
.equ TCNT0_3 = 3 ; |
.equ TCNT0_4 = 4 ; |
.equ TCNT0_5 = 5 ; |
.equ TCNT0_6 = 6 ; |
.equ TCNT0_7 = 7 ; |
; OCR0A - Timer/Counter0 Output Compare Register |
.equ OCR0_0 = 0 ; |
.equ OCR0_1 = 1 ; |
.equ OCR0_2 = 2 ; |
.equ OCR0_3 = 3 ; |
.equ OCR0_4 = 4 ; |
.equ OCR0_5 = 5 ; |
.equ OCR0_6 = 6 ; |
.equ OCR0_7 = 7 ; |
; OCR0B - Timer/Counter0 Output Compare Register |
;.equ OCR0_0 = 0 ; |
;.equ OCR0_1 = 1 ; |
;.equ OCR0_2 = 2 ; |
;.equ OCR0_3 = 3 ; |
;.equ OCR0_4 = 4 ; |
;.equ OCR0_5 = 5 ; |
;.equ OCR0_6 = 6 ; |
;.equ OCR0_7 = 7 ; |
; GTCCR - General Timer/Counter Control Register |
.equ PSR10 = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0 |
.equ ICPSEL1 = 6 ; Timer1 Input Capture Selection Bit |
.equ TSM = 7 ; Timer/Counter Synchronization Mode |
; ***** TIMER_COUNTER_1 ************** |
; TIMSK1 - Timer/Counter Interrupt Mask Register |
.equ TOIE1 = 0 ; Timer/Counter1 Overflow Interrupt Enable |
.equ OCIE1A = 1 ; Timer/Counter1 Output CompareA Match Interrupt Enable |
.equ OCIE1B = 2 ; Timer/Counter1 Output CompareB Match Interrupt Enable |
.equ ICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable |
; TIFR1 - Timer/Counter Interrupt Flag register |
.equ TOV1 = 0 ; Timer/Counter1 Overflow Flag |
.equ OCF1A = 1 ; Output Compare Flag 1A |
.equ OCF1B = 2 ; Output Compare Flag 1B |
.equ ICF1 = 5 ; Input Capture Flag 1 |
; TCCR1A - Timer/Counter1 Control Register A |
.equ WGM10 = 0 ; Waveform Generation Mode |
.equ WGM11 = 1 ; Waveform Generation Mode |
.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0 |
.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1 |
.equ COM1A0 = 6 ; Comparet Ouput Mode 1A, bit 0 |
.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1 |
; TCCR1B - Timer/Counter1 Control Register B |
.equ CS10 = 0 ; Prescaler source of Timer/Counter 1 |
.equ CS11 = 1 ; Prescaler source of Timer/Counter 1 |
.equ CS12 = 2 ; Prescaler source of Timer/Counter 1 |
.equ WGM12 = 3 ; Waveform Generation Mode |
.equ WGM13 = 4 ; Waveform Generation Mode |
.equ ICES1 = 6 ; Input Capture 1 Edge Select |
.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler |
; TCCR1C - Timer/Counter1 Control Register C |
.equ FOC1B = 6 ; |
.equ FOC1A = 7 ; |
; GTCCR - General Timer/Counter Control Register |
.equ PSRSYNC = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0 |
;.equ TSM = 7 ; Timer/Counter Synchronization Mode |
; ***** AD_CONVERTER ***************** |
; ADMUX - The ADC multiplexer Selection Register |
.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits |
.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits |
.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits |
.equ MUX3 = 3 ; Analog Channel and Gain Selection Bits |
.equ ADLAR = 5 ; Left Adjust Result |
.equ REFS0 = 6 ; Reference Selection Bit 0 |
.equ REFS1 = 7 ; Reference Selection Bit 1 |
; ADCSRA - The ADC Control and Status register |
.equ ADPS0 = 0 ; ADC Prescaler Select Bits |
.equ ADPS1 = 1 ; ADC Prescaler Select Bits |
.equ ADPS2 = 2 ; ADC Prescaler Select Bits |
.equ ADIE = 3 ; ADC Interrupt Enable |
.equ ADIF = 4 ; ADC Interrupt Flag |
.equ ADATE = 5 ; ADC Auto Trigger Enable |
.equ ADSC = 6 ; ADC Start Conversion |
.equ ADEN = 7 ; ADC Enable |
; ADCH - ADC Data Register High Byte |
.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0 |
.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1 |
.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2 |
.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3 |
.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4 |
.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5 |
.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6 |
.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7 |
; ADCL - ADC Data Register Low Byte |
.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0 |
.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1 |
.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2 |
.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3 |
.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4 |
.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5 |
.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6 |
.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7 |
; ADCSRB - ADC Control and Status Register B |
.equ ADTS0 = 0 ; ADC Auto Trigger Source 0 |
.equ ADTS1 = 1 ; ADC Auto Trigger Source 1 |
.equ ADTS2 = 2 ; ADC Auto Trigger Source 2 |
.equ ADASCR = 3 ; |
.equ ADAP = 4 ; |
; DIDR0 - Digital Input Disable Register 0 |
.equ ADC0D = 0 ; ADC0 Digital input Disable |
.equ ADC1D = 1 ; ADC1 Digital input Disable |
.equ ADC2D = 2 ; ADC2 Digital input Disable |
.equ ADC3D = 3 ; ADC3 Digital input Disable |
.equ ADC4D = 4 ; ADC4 Digital input Disable |
.equ ADC5D = 5 ; ADC5 Digital input Disable |
.equ ADC6D = 6 ; ADC6 Digital input Disable |
.equ ADC7D = 7 ; ADC7 Digital input Disable |
; DIDR1 - |
.equ ADC8D = 0 ; |
.equ ADC9D = 1 ; |
.equ ADC10D = 2 ; |
.equ AMP0ND = 3 ; |
.equ AMP0PD = 4 ; |
.equ ACMP0D = 5 ; |
; ***** USART ************************ |
; UDR - USART I/O Data Register |
.equ UDR0 = 0 ; USART I/O Data Register bit 0 |
.equ UDR1 = 1 ; USART I/O Data Register bit 1 |
.equ UDR2 = 2 ; USART I/O Data Register bit 2 |
.equ UDR3 = 3 ; USART I/O Data Register bit 3 |
.equ UDR4 = 4 ; USART I/O Data Register bit 4 |
.equ UDR5 = 5 ; USART I/O Data Register bit 5 |
.equ UDR6 = 6 ; USART I/O Data Register bit 6 |
.equ UDR7 = 7 ; USART I/O Data Register bit 7 |
; UCSRA - USART Control and Status register A |
.equ MPCM = 0 ; Multi-processor Communication Mode |
.equ U2X = 1 ; Double USART Transmission Bit |
.equ UPE = 2 ; USART Parity Error |
.equ DOR = 3 ; Data Overrun |
.equ FE = 4 ; Framing Error |
.equ UDRE = 5 ; USART Data Register Empty |
.equ TXC = 6 ; USART Transmitt Complete |
.equ RXC = 7 ; USART Receive Complete |
; UCSRB - USART Control an Status register B |
.equ TXB8 = 0 ; Transmit Data Bit 8 |
.equ RXB8 = 1 ; Receive Data Bit 8 |
.equ UCSZ2 = 2 ; Character Size |
.equ TXEN = 3 ; Transmitter Enable |
.equ RXEN = 4 ; Receiver Enable |
.equ UDRIE = 5 ; USART Data Register Empty Interrupt Enable |
.equ TXCIE = 6 ; TX Complete Interrupt Enable |
.equ RXCIE = 7 ; RX Complete Interrupt Enable |
; UCSRC - USART Control an Status register C |
.equ UCPOL = 0 ; Clock Polarity |
.equ UCSZ0 = 1 ; Character Size Bit 0 |
.equ UCSZ1 = 2 ; Character Size Bit 1 |
.equ USBS = 3 ; Stop Bit Select |
.equ UPM0 = 4 ; Parity Mode Bit 0 |
.equ UPM1 = 5 ; Parity Mode Bit 1 |
.equ UMSEL0 = 6 ; USART Mode Select |
; UBRRH - USART Baud Rate Register High Byte |
.equ UBRR8 = 0 ; USART Baud Rate Register Bit 8 |
.equ UBRR9 = 1 ; USART Baud Rate Register Bit 9 |
.equ UBRR10 = 2 ; USART Baud Rate Register Bit 10 |
.equ UBRR11 = 3 ; USART Baud Rate Register Bit 11 |
; UBRRL - USART Baud Rate Register Low Byte |
.equ UBRR0 = 0 ; USART Baud Rate Register bit 0 |
.equ UBRR1 = 1 ; USART Baud Rate Register bit 1 |
.equ UBRR2 = 2 ; USART Baud Rate Register bit 2 |
.equ UBRR3 = 3 ; USART Baud Rate Register bit 3 |
.equ UBRR4 = 4 ; USART Baud Rate Register bit 4 |
.equ UBRR5 = 5 ; USART Baud Rate Register bit 5 |
.equ UBRR6 = 6 ; USART Baud Rate Register bit 6 |
.equ UBRR7 = 7 ; USART Baud Rate Register bit 7 |
; ***** SPI ************************** |
; SPDR - SPI Data Register |
.equ SPDR0 = 0 ; SPI Data Register bit 0 |
.equ SPDR1 = 1 ; SPI Data Register bit 1 |
.equ SPDR2 = 2 ; SPI Data Register bit 2 |
.equ SPDR3 = 3 ; SPI Data Register bit 3 |
.equ SPDR4 = 4 ; SPI Data Register bit 4 |
.equ SPDR5 = 5 ; SPI Data Register bit 5 |
.equ SPDR6 = 6 ; SPI Data Register bit 6 |
.equ SPDR7 = 7 ; SPI Data Register bit 7 |
; SPSR - SPI Status Register |
.equ SPI2X = 0 ; Double SPI Speed Bit |
.equ WCOL = 6 ; Write Collision Flag |
.equ SPIF = 7 ; SPI Interrupt Flag |
; SPCR - SPI Control Register |
.equ SPR0 = 0 ; SPI Clock Rate Select 0 |
.equ SPR1 = 1 ; SPI Clock Rate Select 1 |
.equ CPHA = 2 ; Clock Phase |
.equ CPOL = 3 ; Clock polarity |
.equ MSTR = 4 ; Master/Slave Select |
.equ DORD = 5 ; Data Order |
.equ SPE = 6 ; SPI Enable |
.equ SPIE = 7 ; SPI Interrupt Enable |
; ***** WATCHDOG ********************* |
; WDTCSR - Watchdog Timer Control Register |
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 |
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 |
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 |
.equ WDE = 3 ; Watch Dog Enable |
.equ WDCE = 4 ; Watchdog Change Enable |
.equ WDP3 = 5 ; Watchdog Timer Prescaler Bit 3 |
.equ WDIE = 6 ; Watchdog Timeout Interrupt Enable |
.equ WDIF = 7 ; Watchdog Timeout Interrupt Flag |
; ***** EXTERNAL_INTERRUPT *********** |
; EICRA - External Interrupt Control Register A |
.equ ISC00 = 0 ; External Interrupt Sense Control Bit |
.equ ISC01 = 1 ; External Interrupt Sense Control Bit |
.equ ISC10 = 2 ; External Interrupt Sense Control Bit |
.equ ISC11 = 3 ; External Interrupt Sense Control Bit |
.equ ISC20 = 4 ; External Interrupt Sense Control Bit |
.equ ISC21 = 5 ; External Interrupt Sense Control Bit |
; EIMSK - External Interrupt Mask Register |
.equ INT0 = 0 ; External Interrupt Request 0 Enable |
.equ INT1 = 1 ; External Interrupt Request 1 Enable |
.equ INT2 = 2 ; External Interrupt Request 2 Enable |
; EIFR - External Interrupt Flag Register |
.equ INTF0 = 0 ; External Interrupt Flag 0 |
.equ INTF1 = 1 ; External Interrupt Flag 1 |
.equ INTF2 = 2 ; External Interrupt Flag 2 |
; ***** LOCKSBITS ******************************************************** |
.equ LB1 = 0 ; Lock bit |
.equ LB2 = 1 ; Lock bit |
.equ BLB01 = 2 ; Boot Lock bit |
.equ BLB02 = 3 ; Boot Lock bit |
.equ BLB11 = 4 ; Boot lock bit |
.equ BLB12 = 5 ; Boot lock bit |
; ***** FUSES ************************************************************ |
; LOW fuse bits |
.equ CKSEL0 = 0 ; Select Clock Source |
.equ CKSEL1 = 1 ; Select Clock Source |
.equ CKSEL2 = 2 ; Select Clock Source |
.equ CKSEL3 = 3 ; Select Clock Source |
.equ SUT0 = 4 ; Select start-up time |
.equ SUT1 = 5 ; Select start-up time |
.equ CKOUT = 6 ; Oscillator output option |
.equ CLKDIV8 = 7 ; Divide clock by 8 |
; HIGH fuse bits |
.equ BOOTRST = 0 ; Select Reset Vector |
.equ BOOTSZ0 = 1 ; Select Boot Size |
.equ BOOTSZ1 = 2 ; Select Boot Size |
.equ EESAVE = 3 ; EEPROM memory is preserved through chip erase |
.equ WDTON = 4 ; Watchdog timer always on |
.equ SPIEN = 5 ; Enable Serial programming and Data Downloading |
.equ JTAGEN = 6 ; Enable JTAG |
.equ OCDEN = 7 ; Enable OCD |
; EXTENDED fuse bits |
.equ TA0SEL = 0 ; (Reserved to factory tests) |
.equ BODLEVEL0 = 1 ; Brown-out Detector trigger level |
.equ BODLEVEL1 = 2 ; Brown-out Detector trigger level |
.equ BODLEVEL2 = 3 ; Brown out detector trigger level |
; ***** CPU REGISTER DEFINITIONS ***************************************** |
.def XH = r27 |
.def XL = r26 |
.def YH = r29 |
.def YL = r28 |
.def ZH = r31 |
.def ZL = r30 |
; ***** DATA MEMORY DECLARATIONS ***************************************** |
.equ FLASHEND = 0x0fff ; Note: Word address |
.equ IOEND = 0x00ff |
.equ SRAM_START = 0x0100 |
.equ SRAM_SIZE = 512 |
.equ RAMEND = 0x02ff |
.equ XRAMEND = 0x0000 |
.equ E2END = 0x01ff |
.equ EEPROMEND = 0x01ff |
.equ EEADRBITS = 9 |
#pragma AVRPART MEMORY PROG_FLASH 8192 |
#pragma AVRPART MEMORY EEPROM 512 |
#pragma AVRPART MEMORY INT_SRAM SIZE 512 |
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x100 |
; ***** BOOTLOADER DECLARATIONS ****************************************** |
.equ NRWW_START_ADDR = 0xc00 |
.equ NRWW_STOP_ADDR = 0xfff |
.equ RWW_START_ADDR = 0x0 |
.equ RWW_STOP_ADDR = 0xbff |
.equ PAGESIZE = 32 |
.equ FIRSTBOOTSTART = 0xf80 |
.equ SECONDBOOTSTART = 0xf00 |
.equ THIRDBOOTSTART = 0xe00 |
.equ FOURTHBOOTSTART = 0xc00 |
.equ SMALLBOOTSTART = FIRSTBOOTSTART |
.equ LARGEBOOTSTART = FOURTHBOOTSTART |
; ***** INTERRUPT VECTORS ************************************************ |
.equ PSC2_CAPTaddr = 0x0001 ; PSC2 Capture Event |
.equ PSC2_ECaddr = 0x0002 ; PSC2 End Cycle |
.equ PSC1_CAPTaddr = 0x0003 ; PSC1 Capture Event |
.equ PSC1_ECaddr = 0x0004 ; PSC1 End Cycle |
.equ PSC0_CAPTaddr = 0x0005 ; PSC0 Capture Event |
.equ PSC0_ECaddr = 0x0006 ; PSC0 End Cycle |
.equ ACI0addr = 0x0007 ; Analog Comparator 0 |
.equ ACI1addr = 0x0008 ; Analog Comparator 1 |
.equ ACI2addr = 0x0009 ; Analog Comparator 2 |
.equ INT0addr = 0x000a ; External Interrupt Request 0 |
.equ ICP1addr = 0x000b ; Timer/Counter1 Capture Event |
.equ OC1Aaddr = 0x000c ; Timer/Counter1 Compare Match A |
.equ OC1Baddr = 0x000d ; Timer/Counter Compare Match B |
.equ OVF1addr = 0x000f ; Timer/Counter1 Overflow |
.equ OC0Aaddr = 0x0010 ; Timer/Counter0 Compare Match A |
.equ OVF0addr = 0x0011 ; Timer/Counter0 Overflow |
.equ ADCCaddr = 0x0012 ; ADC Conversion Complete |
.equ INT1addr = 0x0013 ; External Interrupt Request 1 |
.equ SPIaddr = 0x0014 ; SPI Serial Transfer Complete |
.equ URXCaddr = 0x0015 ; USART, Rx Complete |
.equ UDREaddr = 0x0016 ; USART Data Register Empty |
.equ UTXCaddr = 0x0017 ; USART, Tx Complete |
.equ INT2addr = 0x0018 ; External Interrupt Request 2 |
.equ WDTaddr = 0x0019 ; Watchdog Timeout Interrupt |
.equ ERDYaddr = 0x001a ; EEPROM Ready |
.equ OC0Baddr = 0x001b ; Timer Counter 0 Compare Match B |
.equ INT3addr = 0x001c ; External Interrupt Request 3 |
.equ SPMRaddr = 0x001f ; Store Program Memory Read |
.equ INT_VECTORS_SIZE = 29 ; size in words |
#endif /* _PWM2DEF_INC_ */ |
; ***** END OF FILE ****************************************************** |
/contrib/toolchain/avra/includes/pwm3def.inc |
---|
0,0 → 1,1434 |
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** |
;***** Created: 2005-01-11 10:30 ******* Source: AT90PWM3.xml ************ |
;************************************************************************* |
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y |
;* |
;* Number : AVR000 |
;* File Name : "pwm3def.inc" |
;* Title : Register/Bit Definitions for the AT90PWM3 |
;* Date : 2005-01-11 |
;* Version : 2.14 |
;* Support E-mail : avr@atmel.com |
;* Target MCU : AT90PWM3 |
;* |
;* DESCRIPTION |
;* When including this file in the assembly program file, all I/O register |
;* names and I/O register bit names appearing in the data book can be used. |
;* In addition, the six registers forming the three data pointers X, Y and |
;* Z have been assigned names XL - ZH. Highest RAM address for Internal |
;* SRAM is also defined |
;* |
;* The Register names are represented by their hexadecimal address. |
;* |
;* The Register Bit names are represented by their bit number (0-7). |
;* |
;* Please observe the difference in using the bit names with instructions |
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" |
;* (skip if bit in register set/cleared). The following example illustrates |
;* this: |
;* |
;* in r16,PORTB ;read PORTB latch |
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) |
;* out PORTB,r16 ;output to PORTB |
;* |
;* in r16,TIFR ;read the Timer Interrupt Flag Register |
;* sbrc r16,TOV0 ;test the overflow flag (use bit#) |
;* rjmp TOV0_is_set ;jump if set |
;* ... ;otherwise do something else |
;************************************************************************* |
#ifndef _PWM3DEF_INC_ |
#define _PWM3DEF_INC_ |
#pragma partinc 0 |
; ***** SPECIFY DEVICE *************************************************** |
.device AT90PWM3 |
#pragma AVRPART ADMIN PART_NAME AT90PWM3 |
.equ SIGNATURE_000 = 0x1e |
.equ SIGNATURE_001 = 0x93 |
.equ SIGNATURE_002 = 0x81 |
#pragma AVRPART CORE CORE_VERSION V2E |
; ***** I/O REGISTER DEFINITIONS ***************************************** |
; NOTE: |
; Definitions marked "MEMORY MAPPED"are extended I/O ports |
; and cannot be used with IN/OUT instructions |
.equ PICR2H = 0xff ; MEMORY MAPPED |
.equ PICR2L = 0xfe ; MEMORY MAPPED |
.equ PFRC2B = 0xfd ; MEMORY MAPPED |
.equ PFRC2A = 0xfc ; MEMORY MAPPED |
.equ PCTL2 = 0xfb ; MEMORY MAPPED |
.equ PCNF2 = 0xfa ; MEMORY MAPPED |
.equ OCR2RBH = 0xf9 ; MEMORY MAPPED |
.equ OCR2RBL = 0xf8 ; MEMORY MAPPED |
.equ OCR2SBH = 0xf7 ; MEMORY MAPPED |
.equ OCR2SBL = 0xf6 ; MEMORY MAPPED |
.equ OCR2RAH = 0xf5 ; MEMORY MAPPED |
.equ OCR2RAL = 0xf4 ; MEMORY MAPPED |
.equ OCR2SAH = 0xf3 ; MEMORY MAPPED |
.equ OCR2SAL = 0xf2 ; MEMORY MAPPED |
.equ POM2 = 0xf1 ; MEMORY MAPPED |
.equ PSOC2 = 0xf0 ; MEMORY MAPPED |
.equ PICR1H = 0xef ; MEMORY MAPPED |
.equ PICR1L = 0xee ; MEMORY MAPPED |
.equ PFRC1B = 0xed ; MEMORY MAPPED |
.equ PFRC1A = 0xec ; MEMORY MAPPED |
.equ PCTL1 = 0xeb ; MEMORY MAPPED |
.equ PCNF1 = 0xea ; MEMORY MAPPED |
.equ OCR1RBH = 0xe9 ; MEMORY MAPPED |
.equ OCR1RBL = 0xe8 ; MEMORY MAPPED |
.equ OCR1SBH = 0xe7 ; MEMORY MAPPED |
.equ OCR1SBL = 0xe6 ; MEMORY MAPPED |
.equ OCR1RAH = 0xe5 ; MEMORY MAPPED |
.equ OCR1RAL = 0xe4 ; MEMORY MAPPED |
.equ OCR1SAH = 0xe3 ; MEMORY MAPPED |
.equ OCR1SAL = 0xe2 ; MEMORY MAPPED |
.equ PSOC1 = 0xe0 ; MEMORY MAPPED |
.equ PICR0H = 0xdf ; MEMORY MAPPED |
.equ PICR0L = 0xde ; MEMORY MAPPED |
.equ PFRC0B = 0xdd ; MEMORY MAPPED |
.equ PFRC0A = 0xdc ; MEMORY MAPPED |
.equ PCTL0 = 0xdb ; MEMORY MAPPED |
.equ PCNF0 = 0xda ; MEMORY MAPPED |
.equ OCR0RBH = 0xd9 ; MEMORY MAPPED |
.equ OCR0RBL = 0xd8 ; MEMORY MAPPED |
.equ OCR0SBH = 0xd7 ; MEMORY MAPPED |
.equ OCR0SBL = 0xd6 ; MEMORY MAPPED |
.equ OCR0RAH = 0xd5 ; MEMORY MAPPED |
.equ OCR0RAL = 0xd4 ; MEMORY MAPPED |
.equ OCR0SAH = 0xd3 ; MEMORY MAPPED |
.equ OCR0SAL = 0xd2 ; MEMORY MAPPED |
.equ PSOC0 = 0xd0 ; MEMORY MAPPED |
.equ EUDR = 0xce ; MEMORY MAPPED |
.equ MUBRRH = 0xcd ; MEMORY MAPPED |
.equ MUBRRL = 0xcc ; MEMORY MAPPED |
.equ EUCSRC = 0xca ; MEMORY MAPPED |
.equ EUCSRB = 0xc9 ; MEMORY MAPPED |
.equ EUCSRA = 0xc8 ; MEMORY MAPPED |
.equ UDR = 0xc6 ; MEMORY MAPPED |
.equ UBRRH = 0xc5 ; MEMORY MAPPED |
.equ UBRRL = 0xc4 ; MEMORY MAPPED |
.equ UCSRC = 0xc2 ; MEMORY MAPPED |
.equ UCSRB = 0xc1 ; MEMORY MAPPED |
.equ UCSRA = 0xc0 ; MEMORY MAPPED |
.equ AC2CON = 0xaf ; MEMORY MAPPED |
.equ AC1CON = 0xae ; MEMORY MAPPED |
.equ AC0CON = 0xad ; MEMORY MAPPED |
.equ DACH = 0xac ; MEMORY MAPPED |
.equ DACL = 0xab ; MEMORY MAPPED |
.equ DACON = 0xaa ; MEMORY MAPPED |
.equ PIM2 = 0xa5 ; MEMORY MAPPED |
.equ PIFR2 = 0xa4 ; MEMORY MAPPED |
.equ PIM1 = 0xa3 ; MEMORY MAPPED |
.equ PIFR1 = 0xa2 ; MEMORY MAPPED |
.equ PIM0 = 0xa1 ; MEMORY MAPPED |
.equ PIFR0 = 0xa0 ; MEMORY MAPPED |
.equ OCR1BH = 0x8b ; MEMORY MAPPED |
.equ OCR1BL = 0x8a ; MEMORY MAPPED |
.equ OCR1AH = 0x89 ; MEMORY MAPPED |
.equ OCR1AL = 0x88 ; MEMORY MAPPED |
.equ ICR1H = 0x87 ; MEMORY MAPPED |
.equ ICR1L = 0x86 ; MEMORY MAPPED |
.equ TCNT1H = 0x85 ; MEMORY MAPPED |
.equ TCNT1L = 0x84 ; MEMORY MAPPED |
.equ TCCR1C = 0x82 ; MEMORY MAPPED |
.equ TCCR1B = 0x81 ; MEMORY MAPPED |
.equ TCCR1A = 0x80 ; MEMORY MAPPED |
.equ DIDR1 = 0x7f ; MEMORY MAPPED |
.equ DIDR0 = 0x7e ; MEMORY MAPPED |
.equ ADMUX = 0x7c ; MEMORY MAPPED |
.equ ADCSRB = 0x7b ; MEMORY MAPPED |
.equ ADCSRA = 0x7a ; MEMORY MAPPED |
.equ ADCH = 0x79 ; MEMORY MAPPED |
.equ ADCL = 0x78 ; MEMORY MAPPED |
.equ AMP1CSR = 0x77 ; MEMORY MAPPED |
.equ AMP0CSR = 0x76 ; MEMORY MAPPED |
.equ TIMSK1 = 0x6f ; MEMORY MAPPED |
.equ TIMSK0 = 0x6e ; MEMORY MAPPED |
.equ EICRA = 0x69 ; MEMORY MAPPED |
.equ OSCCAL = 0x66 ; MEMORY MAPPED |
.equ PRR = 0x64 ; MEMORY MAPPED |
.equ CLKPR = 0x61 ; MEMORY MAPPED |
.equ WDTCSR = 0x60 ; MEMORY MAPPED |
.equ SREG = 0x3f |
.equ SPH = 0x3e |
.equ SPL = 0x3d |
.equ SPMCSR = 0x37 |
.equ MCUCR = 0x35 |
.equ MCUSR = 0x34 |
.equ SMCR = 0x33 |
.equ ACSR = 0x30 |
.equ SPDR = 0x2e |
.equ SPSR = 0x2d |
.equ SPCR = 0x2c |
.equ PLLCSR = 0x29 |
.equ OCR0B = 0x28 |
.equ OCR0A = 0x27 |
.equ TCNT0 = 0x26 |
.equ TCCR0B = 0x25 |
.equ TCCR0A = 0x24 |
.equ GTCCR = 0x23 |
.equ EEARH = 0x22 |
.equ EEARL = 0x21 |
.equ EEDR = 0x20 |
.equ EECR = 0x1f |
.equ GPIOR0 = 0x1e |
.equ EIMSK = 0x1d |
.equ EIFR = 0x1c |
.equ GPIOR3 = 0x1b |
.equ GPIOR2 = 0x1a |
.equ GPIOR1 = 0x19 |
.equ TIFR1 = 0x16 |
.equ TIFR0 = 0x15 |
.equ PORTE = 0x0e |
.equ DDRE = 0x0d |
.equ PINE = 0x0c |
.equ PORTD = 0x0b |
.equ DDRD = 0x0a |
.equ PIND = 0x09 |
.equ PORTC = 0x08 |
.equ DDRC = 0x07 |
.equ PINC = 0x06 |
.equ PORTB = 0x05 |
.equ DDRB = 0x04 |
.equ PINB = 0x03 |
; ***** BIT DEFINITIONS ************************************************** |
; ***** PORTB ************************ |
; PORTB - Port B Data Register |
.equ PORTB0 = 0 ; Port B Data Register bit 0 |
.equ PB0 = 0 ; For compatibility |
.equ PORTB1 = 1 ; Port B Data Register bit 1 |
.equ PB1 = 1 ; For compatibility |
.equ PORTB2 = 2 ; Port B Data Register bit 2 |
.equ PB2 = 2 ; For compatibility |
.equ PORTB3 = 3 ; Port B Data Register bit 3 |
.equ PB3 = 3 ; For compatibility |
.equ PORTB4 = 4 ; Port B Data Register bit 4 |
.equ PB4 = 4 ; For compatibility |
.equ PORTB5 = 5 ; Port B Data Register bit 5 |
.equ PB5 = 5 ; For compatibility |
.equ PORTB6 = 6 ; Port B Data Register bit 6 |
.equ PB6 = 6 ; For compatibility |
.equ PORTB7 = 7 ; Port B Data Register bit 7 |
.equ PB7 = 7 ; For compatibility |
; DDRB - Port B Data Direction Register |
.equ DDB0 = 0 ; Port B Data Direction Register bit 0 |
.equ DDB1 = 1 ; Port B Data Direction Register bit 1 |
.equ DDB2 = 2 ; Port B Data Direction Register bit 2 |
.equ DDB3 = 3 ; Port B Data Direction Register bit 3 |
.equ DDB4 = 4 ; Port B Data Direction Register bit 4 |
.equ DDB5 = 5 ; Port B Data Direction Register bit 5 |
.equ DDB6 = 6 ; Port B Data Direction Register bit 6 |
.equ DDB7 = 7 ; Port B Data Direction Register bit 7 |
; PINB - Port B Input Pins |
.equ PINB0 = 0 ; Port B Input Pins bit 0 |
.equ PINB1 = 1 ; Port B Input Pins bit 1 |
.equ PINB2 = 2 ; Port B Input Pins bit 2 |
.equ PINB3 = 3 ; Port B Input Pins bit 3 |
.equ PINB4 = 4 ; Port B Input Pins bit 4 |
.equ PINB5 = 5 ; Port B Input Pins bit 5 |
.equ PINB6 = 6 ; Port B Input Pins bit 6 |
.equ PINB7 = 7 ; Port B Input Pins bit 7 |
; ***** PORTC ************************ |
; PORTC - Port C Data Register |
.equ PORTC0 = 0 ; Port C Data Register bit 0 |
.equ PC0 = 0 ; For compatibility |
.equ PORTC1 = 1 ; Port C Data Register bit 1 |
.equ PC1 = 1 ; For compatibility |
.equ PORTC2 = 2 ; Port C Data Register bit 2 |
.equ PC2 = 2 ; For compatibility |
.equ PORTC3 = 3 ; Port C Data Register bit 3 |
.equ PC3 = 3 ; For compatibility |
.equ PORTC4 = 4 ; Port C Data Register bit 4 |
.equ PC4 = 4 ; For compatibility |
.equ PORTC5 = 5 ; Port C Data Register bit 5 |
.equ PC5 = 5 ; For compatibility |
.equ PORTC6 = 6 ; Port C Data Register bit 6 |
.equ PC6 = 6 ; For compatibility |
.equ PORTC7 = 7 ; Port C Data Register bit 7 |
.equ PC7 = 7 ; For compatibility |
; DDRC - Port C Data Direction Register |
.equ DDC0 = 0 ; Port C Data Direction Register bit 0 |
.equ DDC1 = 1 ; Port C Data Direction Register bit 1 |
.equ DDC2 = 2 ; Port C Data Direction Register bit 2 |
.equ DDC3 = 3 ; Port C Data Direction Register bit 3 |
.equ DDC4 = 4 ; Port C Data Direction Register bit 4 |
.equ DDC5 = 5 ; Port C Data Direction Register bit 5 |
.equ DDC6 = 6 ; Port C Data Direction Register bit 6 |
.equ DDC7 = 7 ; Port C Data Direction Register bit 7 |
; PINC - Port C Input Pins |
.equ PINC0 = 0 ; Port C Input Pins bit 0 |
.equ PINC1 = 1 ; Port C Input Pins bit 1 |
.equ PINC2 = 2 ; Port C Input Pins bit 2 |
.equ PINC3 = 3 ; Port C Input Pins bit 3 |
.equ PINC4 = 4 ; Port C Input Pins bit 4 |
.equ PINC5 = 5 ; Port C Input Pins bit 5 |
.equ PINC6 = 6 ; Port C Input Pins bit 6 |
.equ PINC7 = 7 ; Port C Input Pins bit 7 |
; ***** PORTD ************************ |
; PORTD - Port D Data Register |
.equ PORTD0 = 0 ; Port D Data Register bit 0 |
.equ PD0 = 0 ; For compatibility |
.equ PORTD1 = 1 ; Port D Data Register bit 1 |
.equ PD1 = 1 ; For compatibility |
.equ PORTD2 = 2 ; Port D Data Register bit 2 |
.equ PD2 = 2 ; For compatibility |
.equ PORTD3 = 3 ; Port D Data Register bit 3 |
.equ PD3 = 3 ; For compatibility |
.equ PORTD4 = 4 ; Port D Data Register bit 4 |
.equ PD4 = 4 ; For compatibility |
.equ PORTD5 = 5 ; Port D Data Register bit 5 |
.equ PD5 = 5 ; For compatibility |
.equ PORTD6 = 6 ; Port D Data Register bit 6 |
.equ PD6 = 6 ; For compatibility |
.equ PORTD7 = 7 ; Port D Data Register bit 7 |
.equ PD7 = 7 ; For compatibility |
; DDRD - Port D Data Direction Register |
.equ DDD0 = 0 ; Port D Data Direction Register bit 0 |
.equ DDD1 = 1 ; Port D Data Direction Register bit 1 |
.equ DDD2 = 2 ; Port D Data Direction Register bit 2 |
.equ DDD3 = 3 ; Port D Data Direction Register bit 3 |
.equ DDD4 = 4 ; Port D Data Direction Register bit 4 |
.equ DDD5 = 5 ; Port D Data Direction Register bit 5 |
.equ DDD6 = 6 ; Port D Data Direction Register bit 6 |
.equ DDD7 = 7 ; Port D Data Direction Register bit 7 |
; PIND - Port D Input Pins |
.equ PIND0 = 0 ; Port D Input Pins bit 0 |
.equ PIND1 = 1 ; Port D Input Pins bit 1 |
.equ PIND2 = 2 ; Port D Input Pins bit 2 |
.equ PIND3 = 3 ; Port D Input Pins bit 3 |
.equ PIND4 = 4 ; Port D Input Pins bit 4 |
.equ PIND5 = 5 ; Port D Input Pins bit 5 |
.equ PIND6 = 6 ; Port D Input Pins bit 6 |
.equ PIND7 = 7 ; Port D Input Pins bit 7 |
; ***** BOOT_LOAD ******************** |
; SPMCSR - Store Program Memory Control Register |
.equ SPMCR = SPMCSR ; For compatibility |
.equ SPMEN = 0 ; Store Program Memory Enable |
.equ PGERS = 1 ; Page Erase |
.equ PGWRT = 2 ; Page Write |
.equ BLBSET = 3 ; Boot Lock Bit Set |
.equ RWWSRE = 4 ; Read While Write section read enable |
.equ ASRE = RWWSRE ; For compatibility |
.equ RWWSB = 6 ; Read While Write Section Busy |
.equ ASB = RWWSB ; For compatibility |
.equ SPMIE = 7 ; SPM Interrupt Enable |
; ***** EEPROM *********************** |
; EEDR - EEPROM Data Register |
.equ EEDR0 = 0 ; EEPROM Data Register bit 0 |
.equ EEDR1 = 1 ; EEPROM Data Register bit 1 |
.equ EEDR2 = 2 ; EEPROM Data Register bit 2 |
.equ EEDR3 = 3 ; EEPROM Data Register bit 3 |
.equ EEDR4 = 4 ; EEPROM Data Register bit 4 |
.equ EEDR5 = 5 ; EEPROM Data Register bit 5 |
.equ EEDR6 = 6 ; EEPROM Data Register bit 6 |
.equ EEDR7 = 7 ; EEPROM Data Register bit 7 |
; EECR - EEPROM Control Register |
.equ EERE = 0 ; EEPROM Read Enable |
.equ EEWE = 1 ; EEPROM Write Enable |
.equ EEMWE = 2 ; EEPROM Master Write Enable |
.equ EERIE = 3 ; EEPROM Ready Interrupt Enable |
; ***** PSC0 ************************* |
; PICR0H - PSC 0 Input Capture Register High |
.equ PICR0_8 = 0 ; |
.equ PICR0_9 = 1 ; |
.equ PICR0_10 = 2 ; |
.equ PICR0_11 = 3 ; |
; PICR0L - PSC 0 Input Capture Register Low |
.equ PICR0_0 = 0 ; |
.equ PICR0_1 = 1 ; |
.equ PICR0_2 = 2 ; |
.equ PICR0_3 = 3 ; |
.equ PICR0_4 = 4 ; |
.equ PICR0_5 = 5 ; |
.equ PICR0_6 = 6 ; |
.equ PICR0_7 = 7 ; |
; PFRC0B - PSC 0 Input B Control |
.equ PRFM0B0 = 0 ; PSC 0 Retrigger and Fault Mode for Part B |
.equ PRFM0B1 = 1 ; PSC 0 Retrigger and Fault Mode for Part B |
.equ PRFM0B2 = 2 ; PSC 0 Retrigger and Fault Mode for Part B |
.equ PRFM0B3 = 3 ; PSC 0 Retrigger and Fault Mode for Part B |
.equ PFLTE0B = 4 ; PSC 0 Filter Enable on Input Part B |
.equ PELEV0B = 5 ; PSC 0 Edge Level Selector on Input Part B |
.equ PISEL0B = 6 ; PSC 0 Input Select for Part B |
.equ PCAE0B = 7 ; PSC 0 Capture Enable Input Part B |
; PFRC0A - PSC 0 Input A Control |
.equ PRFM0A0 = 0 ; PSC 0 Retrigger and Fault Mode for Part A |
.equ PRFM0A1 = 1 ; PSC 0 Retrigger and Fault Mode for Part A |
.equ PRFM0A2 = 2 ; PSC 0 Retrigger and Fault Mode for Part A |
.equ PRFM0A3 = 3 ; PSC 0 Retrigger and Fault Mode for Part A |
.equ PFLTE0A = 4 ; PSC 0 Filter Enable on Input Part A |
.equ PELEV0A = 5 ; PSC 0 Edge Level Selector on Input Part A |
.equ PISEL0A = 6 ; PSC 0 Input Select for Part A |
.equ PCAE0A = 7 ; PSC 0 Capture Enable Input Part A |
; PCTL0 - PSC 0 Control Register |
.equ PRUN0 = 0 ; PSC 0 Run |
.equ PCCYC0 = 1 ; PSC0 Complete Cycle |
.equ PARUN0 = 2 ; PSC0 Auto Run |
.equ PAOC0A = 3 ; PSC 0 Asynchronous Output Control A |
.equ PAOC0B = 4 ; PSC 0 Asynchronous Output Control B |
.equ PBFM0 = 5 ; PSC 0 Balance Flank Width Modulation |
.equ PPRE00 = 6 ; PSC 0 Prescaler Select 0 |
.equ PPRE01 = 7 ; PSC 0 Prescaler Select 1 |
; PCNF0 - PSC 0 Configuration Register |
.equ PCLKSEL0 = 1 ; PSC 0 Input Clock Select |
.equ POP0 = 2 ; PSC 0 Output Polarity |
.equ PMODE00 = 3 ; PSC 0 Mode |
.equ PMODE01 = 4 ; PSC 0 Mode |
.equ PLOCK0 = 5 ; PSC 0 Lock |
.equ PALOCK0 = 6 ; PSC 0 Autolock |
.equ PFIFTY0 = 7 ; PSC 0 Fifty |
; OCR0RBH - Output Compare RB Register High |
.equ OCR0RB_8 = 0 ; |
.equ OCR0RB_9 = 1 ; |
.equ OCR0RB_00 = 2 ; |
.equ OCR0RB_01 = 3 ; |
.equ OCR0RB_02 = 4 ; |
.equ OCR0RB_03 = 5 ; |
.equ OCR0RB_04 = 6 ; |
.equ OCR0RB_05 = 7 ; |
; OCR0RBL - Output Compare RB Register Low |
.equ OCR0RB_0 = 0 ; |
.equ OCR0RB_1 = 1 ; |
.equ OCR0RB_2 = 2 ; |
.equ OCR0RB_3 = 3 ; |
.equ OCR0RB_4 = 4 ; |
.equ OCR0RB_5 = 5 ; |
.equ OCR0RB_6 = 6 ; |
.equ OCR0RB_7 = 7 ; |
; OCR0SBH - Output Compare SB Register High |
.equ OCR0SB_8 = 0 ; |
.equ OCR0SB_9 = 1 ; |
.equ OCR0SB_00 = 2 ; |
.equ OCR0SB_01 = 3 ; |
; OCR0SBL - Output Compare SB Register Low |
.equ OCR0SB_0 = 0 ; |
.equ OCR0SB_1 = 1 ; |
.equ OCR0SB_2 = 2 ; |
.equ OCR0SB_3 = 3 ; |
.equ OCR0SB_4 = 4 ; |
.equ OCR0SB_5 = 5 ; |
.equ OCR0SB_6 = 6 ; |
.equ OCR0SB_7 = 7 ; |
; OCR0RAH - Output Compare RA Register High |
.equ OCR0RA_8 = 0 ; |
.equ OCR0RA_9 = 1 ; |
.equ OCR0RA_00 = 2 ; |
.equ OCR0RA_01 = 3 ; |
; OCR0RAL - Output Compare RA Register Low |
.equ OCR0RA_0 = 0 ; |
.equ OCR0RA_1 = 1 ; |
.equ OCR0RA_2 = 2 ; |
.equ OCR0RA_3 = 3 ; |
.equ OCR0RA_4 = 4 ; |
.equ OCR0RA_5 = 5 ; |
.equ OCR0RA_6 = 6 ; |
.equ OCR0RA_7 = 7 ; |
; OCR0SAH - Output Compare SA Register High |
.equ OCR0SA_8 = 0 ; |
.equ OCR0SA_9 = 1 ; |
.equ OCR0SA_00 = 2 ; |
.equ OCR0SA_01 = 3 ; |
; OCR0SAL - Output Compare SA Register Low |
.equ OCR0SA_0 = 0 ; |
.equ OCR0SA_1 = 1 ; |
.equ OCR0SA_2 = 2 ; |
.equ OCR0SA_3 = 3 ; |
.equ OCR0SA_4 = 4 ; |
.equ OCR0SA_5 = 5 ; |
.equ OCR0SA_6 = 6 ; |
.equ OCR0SA_7 = 7 ; |
; PSOC0 - PSC0 Synchro and Output Configuration |
.equ POEN0A = 0 ; PSCOUT00 Output Enable |
.equ POEN0B = 2 ; PSCOUT01 Output Enable |
.equ PSYNC00 = 4 ; Synchronization Out for ADC Selection |
.equ PSYNC01 = 5 ; Synchronization Out for ADC Selection |
; PIM0 - PSC0 Interrupt Mask Register |
.equ PEOPE0 = 0 ; End of Cycle Interrupt Enable |
.equ PEVE0A = 3 ; External Event A Interrupt Enable |
.equ PEVE0B = 4 ; External Event B Interrupt Enable |
.equ PSEIE0 = 5 ; PSC 0 Synchro Error Interrupt Enable |
; PIFR0 - PSC0 Interrupt Flag Register |
.equ PEOP0 = 0 ; End of PSC0 Interrupt |
.equ PRN00 = 1 ; Ramp Number |
.equ PRN01 = 2 ; Ramp Number |
.equ PEV0A = 3 ; External Event A Interrupt |
.equ PEV0B = 4 ; External Event B Interrupt |
.equ PSEI0 = 5 ; PSC 0 Synchro Error Interrupt |
; ***** PSC1 ************************* |
; PICR1H - PSC 1 Input Capture Register High |
.equ PICR1_8 = 0 ; |
.equ PICR1_9 = 1 ; |
.equ PICR1_10 = 2 ; |
.equ PICR1_11 = 3 ; |
; PICR1L - PSC 1 Input Capture Register Low |
.equ PICR1_0 = 0 ; |
.equ PICR1_1 = 1 ; |
.equ PICR1_2 = 2 ; |
.equ PICR1_3 = 3 ; |
.equ PICR1_4 = 4 ; |
.equ PICR1_5 = 5 ; |
.equ PICR1_6 = 6 ; |
.equ PICR1_7 = 7 ; |
; PFRC1B - PSC 1 Input B Control |
.equ PRFM1B0 = 0 ; PSC 1 Retrigger and Fault Mode for Part B |
.equ PRFM1B1 = 1 ; PSC 1 Retrigger and Fault Mode for Part B |
.equ PRFM1B2 = 2 ; PSC 1 Retrigger and Fault Mode for Part B |
.equ PRFM1B3 = 3 ; PSC 1 Retrigger and Fault Mode for Part B |
.equ PFLTE1B = 4 ; PSC 1 Filter Enable on Input Part B |
.equ PELEV1B = 5 ; PSC 1 Edge Level Selector on Input Part B |
.equ PISEL1B = 6 ; PSC 1 Input Select for Part B |
.equ PCAE1B = 7 ; PSC 1 Capture Enable Input Part B |
; PFRC1A - PSC 1 Input B Control |
.equ PRFM1A0 = 0 ; PSC 1 Retrigger and Fault Mode for Part A |
.equ PRFM1A1 = 1 ; PSC 1 Retrigger and Fault Mode for Part A |
.equ PRFM1A2 = 2 ; PSC 1 Retrigger and Fault Mode for Part A |
.equ PRFM1A3 = 3 ; PSC 1 Retrigger and Fault Mode for Part A |
.equ PFLTE1A = 4 ; PSC 1 Filter Enable on Input Part A |
.equ PELEV1A = 5 ; PSC 1 Edge Level Selector on Input Part A |
.equ PISEL1A = 6 ; PSC 1 Input Select for Part A |
.equ PCAE1A = 7 ; PSC 1 Capture Enable Input Part A |
; PCTL1 - PSC 1 Control Register |
.equ PRUN1 = 0 ; PSC 1 Run |
.equ PCCYC1 = 1 ; PSC1 Complete Cycle |
.equ PARUN1 = 2 ; PSC1 Auto Run |
.equ PAOC1A = 3 ; PSC 1 Asynchronous Output Control A |
.equ PAOC1B = 4 ; PSC 1 Asynchronous Output Control B |
.equ PBFM1 = 5 ; Balance Flank Width Modulation |
.equ PPRE10 = 6 ; PSC 1 Prescaler Select 0 |
.equ PPRE11 = 7 ; PSC 1 Prescaler Select 1 |
; PCNF1 - PSC 1 Configuration Register |
.equ PCLKSEL1 = 1 ; PSC 1 Input Clock Select |
.equ POP1 = 2 ; PSC 1 Output Polarity |
.equ PMODE10 = 3 ; PSC 1 Mode |
.equ PMODE11 = 4 ; PSC 1 Mode |
.equ PLOCK1 = 5 ; PSC 1 Lock |
.equ PALOCK1 = 6 ; PSC 1 Autolock |
.equ PFIFTY1 = 7 ; PSC 1 Fifty |
; OCR1RBH - Output Compare RB Register High |
.equ OCR1RB_8 = 0 ; |
.equ OCR1RB_9 = 1 ; |
.equ OCR1RB_10 = 2 ; |
.equ OCR1RB_11 = 3 ; |
.equ OCR1RB_12 = 4 ; |
.equ OCR1RB_13 = 5 ; |
.equ OCR1RB_14 = 6 ; |
.equ OCR1RB_15 = 7 ; |
; OCR1RBL - Output Compare RB Register Low |
.equ OCR1RB_0 = 0 ; |
.equ OCR1RB_1 = 1 ; |
.equ OCR1RB_2 = 2 ; |
.equ OCR1RB_3 = 3 ; |
.equ OCR1RB_4 = 4 ; |
.equ OCR1RB_5 = 5 ; |
.equ OCR1RB_6 = 6 ; |
.equ OCR1RB_7 = 7 ; |
; OCR1SBH - Output Compare SB Register High |
.equ OCR1SB_8 = 0 ; |
.equ OCR1SB_9 = 1 ; |
.equ OCR1SB_10 = 2 ; |
.equ OCR1SB_11 = 3 ; |
; OCR1SBL - Output Compare SB Register Low |
.equ OCR1SB_0 = 0 ; |
.equ OCR1SB_1 = 1 ; |
.equ OCR1SB_2 = 2 ; |
.equ OCR1SB_3 = 3 ; |
.equ OCR1SB_4 = 4 ; |
.equ OCR1SB_5 = 5 ; |
.equ OCR1SB_6 = 6 ; |
.equ OCR1SB_7 = 7 ; |
; OCR1RAH - Output Compare RA Register High |
.equ OCR1RA_8 = 0 ; |
.equ OCR1RA_9 = 1 ; |
.equ OCR1RA_10 = 2 ; |
.equ OCR1RA_11 = 3 ; |
; OCR1RAL - Output Compare RA Register Low |
.equ OCR1RA_0 = 0 ; |
.equ OCR1RA_1 = 1 ; |
.equ OCR1RA_2 = 2 ; |
.equ OCR1RA_3 = 3 ; |
.equ OCR1RA_4 = 4 ; |
.equ OCR1RA_5 = 5 ; |
.equ OCR1RA_6 = 6 ; |
.equ OCR1RA_7 = 7 ; |
; OCR1SAH - Output Compare SA Register High |
.equ OCR1SA_8 = 0 ; |
.equ OCR1SA_9 = 1 ; |
.equ OCR1SA_10 = 2 ; |
.equ OCR1SA_11 = 3 ; |
; OCR1SAL - Output Compare SA Register Low |
.equ OCR1SA_0 = 0 ; |
.equ OCR1SA_1 = 1 ; |
.equ OCR1SA_2 = 2 ; |
.equ OCR1SA_3 = 3 ; |
.equ OCR1SA_4 = 4 ; |
.equ OCR1SA_5 = 5 ; |
.equ OCR1SA_6 = 6 ; |
.equ OCR1SA_7 = 7 ; |
; PSOC1 - PSC1 Synchro and Output Configuration |
.equ POEN1A = 0 ; PSCOUT10 Output Enable |
.equ POEN1B = 2 ; PSCOUT11 Output Enable |
.equ PSYNC1_0 = 4 ; Synchronization Out for ADC Selection |
.equ PSYNC1_1 = 5 ; Synchronization Out for ADC Selection |
; PIM1 - PSC1 Interrupt Mask Register |
.equ PEOPE1 = 0 ; End of Cycle Interrupt Enable |
.equ PEVE1A = 3 ; External Event A Interrupt Enable |
.equ PEVE1B = 4 ; External Event B Interrupt Enable |
.equ PSEIE1 = 5 ; PSC 1 Synchro Error Interrupt Enable |
; PIFR1 - PSC1 Interrupt Flag Register |
.equ PEOP1 = 0 ; End of PSC1 Interrupt |
.equ PRN10 = 1 ; Ramp Number |
.equ PRN11 = 2 ; Ramp Number |
.equ PEV1A = 3 ; External Event A Interrupt |
.equ PEV1B = 4 ; External Event B Interrupt |
.equ PSEI1 = 5 ; PSC 1 Synchro Error Interrupt |
; ***** PSC2 ************************* |
; PICR2H - PSC 2 Input Capture Register High |
.equ PICR2_8 = 0 ; |
.equ PICR2_9 = 1 ; |
.equ PICR2_10 = 2 ; |
.equ PICR2_11 = 3 ; |
; PICR2L - PSC 2 Input Capture Register Low |
.equ PICR2_0 = 0 ; |
.equ PICR2_1 = 1 ; |
.equ PICR2_2 = 2 ; |
.equ PICR2_3 = 3 ; |
.equ PICR2_4 = 4 ; |
.equ PICR2_5 = 5 ; |
.equ PICR2_6 = 6 ; |
.equ PICR2_7 = 7 ; |
; PFRC2B - PSC 2 Input B Control |
.equ PRFM2B0 = 0 ; PSC 2 Retrigger and Fault Mode for Part B |
.equ PRFM2B1 = 1 ; PSC 2 Retrigger and Fault Mode for Part B |
.equ PRFM2B2 = 2 ; PSC 2 Retrigger and Fault Mode for Part B |
.equ PRFM2B3 = 3 ; PSC 2 Retrigger and Fault Mode for Part B |
.equ PFLTE2B = 4 ; PSC 2 Filter Enable on Input Part B |
.equ PELEV2B = 5 ; PSC 2 Edge Level Selector on Input Part B |
.equ PISEL2B = 6 ; PSC 2 Input Select for Part B |
.equ PCAE2B = 7 ; PSC 2 Capture Enable Input Part B |
; PFRC2A - PSC 2 Input B Control |
.equ PRFM2A0 = 0 ; PSC 2 Retrigger and Fault Mode for Part A |
.equ PRFM2A1 = 1 ; PSC 2 Retrigger and Fault Mode for Part A |
.equ PRFM2A2 = 2 ; PSC 2 Retrigger and Fault Mode for Part A |
.equ PRFM2A3 = 3 ; PSC 2 Retrigger and Fault Mode for Part A |
.equ PFLTE2A = 4 ; PSC 2 Filter Enable on Input Part A |
.equ PELEV2A = 5 ; PSC 2 Edge Level Selector on Input Part A |
.equ PISEL2A = 6 ; PSC 2 Input Select for Part A |
.equ PCAE2A = 7 ; PSC 2 Capture Enable Input Part A |
; PCTL2 - PSC 2 Control Register |
.equ PRUN2 = 0 ; PSC 2 Run |
.equ PCCYC2 = 1 ; PSC2 Complete Cycle |
.equ PARUN2 = 2 ; PSC2 Auto Run |
.equ PAOC2A = 3 ; PSC 2 Asynchronous Output Control A |
.equ PAOC2B = 4 ; PSC 2 Asynchronous Output Control B |
.equ PBFM2 = 5 ; Balance Flank Width Modulation |
.equ PPRE20 = 6 ; PSC 2 Prescaler Select 0 |
.equ PPRE21 = 7 ; PSC 2 Prescaler Select 1 |
; PCNF2 - PSC 2 Configuration Register |
.equ POME2 = 0 ; PSC 2 Output Matrix Enable |
.equ PCLKSEL2 = 1 ; PSC 2 Input Clock Select |
.equ POP2 = 2 ; PSC 2 Output Polarity |
.equ PMODE20 = 3 ; PSC 2 Mode |
.equ PMODE21 = 4 ; PSC 2 Mode |
.equ PLOCK2 = 5 ; PSC 2 Lock |
.equ PALOCK2 = 6 ; PSC 2 Autolock |
.equ PFIFTY2 = 7 ; PSC 2 Fifty |
; OCR2RBH - Output Compare RB Register High |
.equ OCR2RB_8 = 0 ; |
.equ OCR2RB_9 = 1 ; |
.equ OCR2RB_10 = 2 ; |
.equ OCR2RB_11 = 3 ; |
.equ OCR2RB_12 = 4 ; |
.equ OCR2RB_13 = 5 ; |
.equ OCR2RB_14 = 6 ; |
.equ OCR2RB_15 = 7 ; |
; OCR2RBL - Output Compare RB Register Low |
.equ OCR2RB_0 = 0 ; |
.equ OCR2RB_1 = 1 ; |
.equ OCR2RB_2 = 2 ; |
.equ OCR2RB_3 = 3 ; |
.equ OCR2RB_4 = 4 ; |
.equ OCR2RB_5 = 5 ; |
.equ OCR2RB_6 = 6 ; |
.equ OCR2RB_7 = 7 ; |
; OCR2SBH - Output Compare SB Register High |
.equ OCR2SB_8 = 0 ; |
.equ OCR2SB_9 = 1 ; |
.equ OCR2SB_10 = 2 ; |
.equ OCR2SB_11 = 3 ; |
; OCR2SBL - Output Compare SB Register Low |
.equ OCR2SB_0 = 0 ; |
.equ OCR2SB_1 = 1 ; |
.equ OCR2SB_2 = 2 ; |
.equ OCR2SB_3 = 3 ; |
.equ OCR2SB_4 = 4 ; |
.equ OCR2SB_5 = 5 ; |
.equ OCR2SB_6 = 6 ; |
.equ OCR2SB_7 = 7 ; |
; OCR2RAH - Output Compare RA Register High |
.equ OCR2RA_8 = 0 ; |
.equ OCR2RA_9 = 1 ; |
.equ OCR2RA_10 = 2 ; |
.equ OCR2RA_11 = 3 ; |
; OCR2RAL - Output Compare RA Register Low |
.equ OCR2RA_0 = 0 ; |
.equ OCR2RA_1 = 1 ; |
.equ OCR2RA_2 = 2 ; |
.equ OCR2RA_3 = 3 ; |
.equ OCR2RA_4 = 4 ; |
.equ OCR2RA_5 = 5 ; |
.equ OCR2RA_6 = 6 ; |
.equ OCR2RA_7 = 7 ; |
; OCR2SAH - Output Compare SA Register High |
.equ OCR2SA_8 = 0 ; |
.equ OCR2SA_9 = 1 ; |
.equ OCR2SA_10 = 2 ; |
.equ OCR2SA_11 = 3 ; |
; OCR2SAL - Output Compare SA Register Low |
.equ OCR2SA_0 = 0 ; |
.equ OCR2SA_1 = 1 ; |
.equ OCR2SA_2 = 2 ; |
.equ OCR2SA_3 = 3 ; |
.equ OCR2SA_4 = 4 ; |
.equ OCR2SA_5 = 5 ; |
.equ OCR2SA_6 = 6 ; |
.equ OCR2SA_7 = 7 ; |
; POM2 - PSC 2 Output Matrix |
.equ POMV2A0 = 0 ; Output Matrix Output A Ramp 0 |
.equ POMV2A1 = 1 ; Output Matrix Output A Ramp 1 |
.equ POMV2A2 = 2 ; Output Matrix Output A Ramp 2 |
.equ POMV2A3 = 3 ; Output Matrix Output A Ramp 3 |
.equ POMV2B0 = 4 ; Output Matrix Output B Ramp 0 |
.equ POMV2B1 = 5 ; Output Matrix Output B Ramp 2 |
.equ POMV2B2 = 6 ; Output Matrix Output B Ramp 2 |
.equ POMV2B3 = 7 ; Output Matrix Output B Ramp 3 |
; PSOC2 - PSC2 Synchro and Output Configuration |
.equ POEN2A = 0 ; PSCOUT20 Output Enable |
.equ POEN2C = 1 ; PSCOUT22 Output Enable |
.equ POEN2B = 2 ; PSCOUT21 Output Enable |
.equ POEN2D = 3 ; PSCOUT23 Output Enable |
.equ PSYNC2_0 = 4 ; Synchronization Out for ADC Selection |
.equ PSYNC2_1 = 5 ; Synchronization Out for ADC Selection |
.equ POS22 = 6 ; PSC 2 Output 22 Select |
.equ POS23 = 7 ; PSC 2 Output 23 Select |
; PIM2 - PSC2 Interrupt Mask Register |
.equ PEOPE2 = 0 ; End of Cycle Interrupt Enable |
.equ PEVE2A = 3 ; External Event A Interrupt Enable |
.equ PEVE2B = 4 ; External Event B Interrupt Enable |
.equ PSEIE2 = 5 ; PSC 2 Synchro Error Interrupt Enable |
; PIFR2 - PSC2 Interrupt Flag Register |
.equ PEOP2 = 0 ; End of PSC2 Interrupt |
.equ PRN20 = 1 ; Ramp Number |
.equ PRN21 = 2 ; Ramp Number |
.equ PEV2A = 3 ; External Event A Interrupt |
.equ PEV2B = 4 ; External Event B Interrupt |
.equ PSEI2 = 5 ; PSC 2 Synchro Error Interrupt |
; ***** EUSART *********************** |
; EUDR - EUSART I/O Data Register |
.equ EUDR0 = 0 ; EUSART I/O Data Register bit 0 |
.equ EUDR1 = 1 ; EUSART I/O Data Register bit 1 |
.equ EUDR2 = 2 ; EUSART I/O Data Register bit 2 |
.equ EUDR3 = 3 ; EUSART I/O Data Register bit 3 |
.equ EUDR4 = 4 ; EUSART I/O Data Register bit 4 |
.equ EUDR5 = 5 ; EUSART I/O Data Register bit 5 |
.equ EUDR6 = 6 ; EUSART I/O Data Register bit 6 |
.equ EUDR7 = 7 ; EUSART I/O Data Register bit 7 |
; EUCSRA - EUSART Control and Status Register A |
.equ URxS0 = 0 ; EUSART Control and Status Register A Bit 0 |
.equ URxS1 = 1 ; EUSART Control and Status Register A Bit 1 |
.equ URxS2 = 2 ; EUSART Control and Status Register A Bit 2 |
.equ URxS3 = 3 ; EUSART Control and Status Register A Bit 3 |
.equ UTxS0 = 4 ; EUSART Control and Status Register A Bit 4 |
.equ UTxS1 = 5 ; EUSART Control and Status Register A Bit 5 |
.equ UTxS2 = 6 ; EUSART Control and Status Register A Bit 6 |
.equ UTxS3 = 7 ; EUSART Control and Status Register A Bit 7 |
; EUCSRB - EUSART Control Register B |
.equ BODR = 0 ; Order Bit |
.equ EMCH = 1 ; Manchester Mode Bit |
.equ EUSBS = 3 ; EUSBS Enable Bit |
.equ EUSART = 4 ; EUSART Enable Bit |
; EUCSRC - EUSART Status Register C |
.equ STP0 = 0 ; Stop Bit 0 |
.equ STP1 = 1 ; Stop Bit 1 |
.equ F1617 = 2 ; F1617 Bit |
.equ FEM = 3 ; Frame Error Manchester Bit |
; MUBRRH - Manchester Receiver Baud Rate Register High Byte |
.equ MUBRR8 = 0 ; Manchester Receiver Baud Rate Register Bit 8 |
.equ MUBRR9 = 1 ; Manchester Receiver Baud Rate Register Bit 9 |
.equ MUBRR10 = 2 ; Manchester Receiver Baud Rate Register Bit 10 |
.equ MUBRR11 = 3 ; Manchester Receiver Baud Rate Register Bit 11 |
.equ MUBRR12 = 4 ; Manchester Receiver Baud Rate Register Bit 12 |
.equ MUBRR13 = 5 ; Manchester Receiver Baud Rate Register Bit 13 |
.equ MUBRR14 = 6 ; Manchester Receiver Baud Rate Register Bit 14 |
.equ MUBRR15 = 7 ; Manchester Receiver Baud Rate Register Bit 15 |
; MUBRRL - Manchester Receiver Baud Rate Register Low Byte |
.equ MUBRR0 = 0 ; Manchester Receiver Baud Rate Register Bit 0 |
.equ MUBRR1 = 1 ; Manchester Receiver Baud Rate Register Bit 1 |
.equ MUBRR2 = 2 ; Manchester Receiver Baud Rate Register Bit 2 |
.equ MUBRR3 = 3 ; Manchester Receiver Baud Rate Register Bit 3 |
.equ MUBRR4 = 4 ; Manchester Receiver Baud Rate Register Bit 4 |
.equ MUBRR5 = 5 ; Manchester Receiver Baud Rate Register Bit 5 |
.equ MUBRR6 = 6 ; Manchester Receiver Baud Rate Register Bit 6 |
.equ MUBRR7 = 7 ; Manchester Receiver Baud Rate Register Bit 7 |
; ***** ANALOG_COMPARATOR ************ |
; AC0CON - Analog Comparator 0 Control Register |
.equ AC0M0 = 0 ; Analog Comparator 0 Multiplexer Register |
.equ AC0M1 = 1 ; Analog Comparator 0 Multiplexer Regsiter |
.equ AC0M2 = 2 ; Analog Comparator 0 Multiplexer Register |
.equ AC0IS0 = 4 ; Analog Comparator 0 Interrupt Select Bit |
.equ AC0IS1 = 5 ; Analog Comparator 0 Interrupt Select Bit |
.equ AC0IE = 6 ; Analog Comparator 0 Interrupt Enable Bit |
.equ AC0EN = 7 ; Analog Comparator 0 Enable Bit |
; AC1CON - Analog Comparator 1 Control Register |
.equ AC1M0 = 0 ; Analog Comparator 1 Multiplexer Register |
.equ AC1M1 = 1 ; Analog Comparator 1 Multiplexer Regsiter |
.equ AC1M2 = 2 ; Analog Comparator 1 Multiplexer Register |
.equ AC1ICE = 3 ; Analog Comparator 1 Interrupt Capture Enable Bit |
.equ AC1IS0 = 4 ; Analog Comparator 1 Interrupt Select Bit |
.equ AC1IS1 = 5 ; Analog Comparator 1 Interrupt Select Bit |
.equ AC1IE = 6 ; Analog Comparator 1 Interrupt Enable Bit |
.equ AC1EN = 7 ; Analog Comparator 1 Enable Bit |
; AC2CON - Analog Comparator 2 Control Register |
.equ AC2M0 = 0 ; Analog Comparator 2 Multiplexer Register |
.equ AC2M1 = 1 ; Analog Comparator 2 Multiplexer Regsiter |
.equ AC2M2 = 2 ; Analog Comparator 2 Multiplexer Register |
.equ AC2SADE = 3 ; Analog Comparator 2 Start A/D Conversion Enable Bit |
.equ AC2IS0 = 4 ; Analog Comparator 2 Interrupt Select Bit |
.equ AC2IS1 = 5 ; Analog Comparator 2 Interrupt Select Bit |
.equ AC2IE = 6 ; Analog Comparator 2 Interrupt Enable Bit |
.equ AC2EN = 7 ; Analog Comparator 2 Enable Bit |
; ***** DA_CONVERTER ***************** |
; DACH - DAC Data Register High Byte |
.equ DACH0 = 0 ; DAC Data Register High Byte Bit 0 |
.equ DACH1 = 1 ; DAC Data Register High Byte Bit 1 |
.equ DACH2 = 2 ; DAC Data Register High Byte Bit 2 |
.equ DACH3 = 3 ; DAC Data Register High Byte Bit 3 |
.equ DACH4 = 4 ; DAC Data Register High Byte Bit 4 |
.equ DACH5 = 5 ; DAC Data Register High Byte Bit 5 |
.equ DACH6 = 6 ; DAC Data Register High Byte Bit 6 |
.equ DACH7 = 7 ; DAC Data Register High Byte Bit 7 |
; DACL - DAC Data Register Low Byte |
.equ DACL1 = 1 ; DAC Data Register Low Byte Bit 1 |
.equ DACL2 = 2 ; DAC Data Register Low Byte Bit 2 |
.equ DACL3 = 3 ; DAC Data Register Low Byte Bit 3 |
.equ DACL4 = 4 ; DAC Data Register Low Byte Bit 4 |
.equ DACL5 = 5 ; DAC Data Register Low Byte Bit 5 |
.equ DACL6 = 6 ; DAC Data Register Low Byte Bit 6 |
.equ DACL7 = 7 ; DAC Data Register Low Byte Bit 7 |
; DACON - DAC Control Register |
.equ DAEN = 0 ; DAC Enable Bit |
.equ DAOE = 1 ; DAC Output Enable Bit |
.equ DALA = 2 ; DAC Left Adjust |
.equ DATS0 = 4 ; DAC Trigger Selection Bit 0 |
.equ DATS1 = 5 ; DAC Trigger Selection Bit 1 |
.equ DATS2 = 6 ; DAC Trigger Selection Bit 2 |
.equ DAATE = 7 ; DAC Auto Trigger Enable Bit |
; ***** CPU ************************** |
; SREG - Status Register |
.equ SREG_C = 0 ; Carry Flag |
.equ SREG_Z = 1 ; Zero Flag |
.equ SREG_N = 2 ; Negative Flag |
.equ SREG_V = 3 ; Two's Complement Overflow Flag |
.equ SREG_S = 4 |
.equ SREG_H = 5 ; Half Carry Flag |
.equ SREG_T = 6 ; Bit Copy Storage |
.equ SREG_I = 7 ; Global Interrupt Enable |
; MCUCR - MCU Control Register |
.equ IVCE = 0 ; Interrupt Vector Change Enable |
.equ IVSEL = 1 ; Interrupt Vector Select |
.equ PUD = 4 ; Pull-up disable |
.equ SPIPS = 7 ; SPI Pin Select |
; MCUSR - MCU Status Register |
.equ PORF = 0 ; Power-on reset flag |
.equ EXTRF = 1 ; External Reset Flag |
.equ BORF = 2 ; Brown-out Reset Flag |
.equ WDRF = 3 ; Watchdog Reset Flag |
; OSCCAL - Oscillator Calibration Value |
.equ CAL0 = 0 ; Oscillator Calibration Value Bit0 |
.equ CAL1 = 1 ; Oscillator Calibration Value Bit1 |
.equ CAL2 = 2 ; Oscillator Calibration Value Bit2 |
.equ CAL3 = 3 ; Oscillator Calibration Value Bit3 |
.equ CAL4 = 4 ; Oscillator Calibration Value Bit4 |
.equ CAL5 = 5 ; Oscillator Calibration Value Bit5 |
.equ CAL6 = 6 ; Oscillator Calibration Value Bit6 |
; CLKPR - |
.equ CLKPS0 = 0 ; |
.equ CLKPS1 = 1 ; |
.equ CLKPS2 = 2 ; |
.equ CLKPS3 = 3 ; |
.equ CPKPCE = 7 ; |
; SMCR - Sleep Mode Control Register |
.equ SE = 0 ; Sleep Enable |
.equ SM0 = 1 ; Sleep Mode Select bit 0 |
.equ SM1 = 2 ; Sleep Mode Select bit 1 |
.equ SM2 = 3 ; Sleep Mode Select bit 2 |
; GPIOR3 - General Purpose IO Register 3 |
.equ GPIOR30 = 0 ; General Purpose IO Register 3 bit 0 |
.equ GPIOR31 = 1 ; General Purpose IO Register 3 bit 1 |
.equ GPIOR32 = 2 ; General Purpose IO Register 3 bit 2 |
.equ GPIOR33 = 3 ; General Purpose IO Register 3 bit 3 |
.equ GPIOR34 = 4 ; General Purpose IO Register 3 bit 4 |
.equ GPIOR35 = 5 ; General Purpose IO Register 3 bit 5 |
.equ GPIOR36 = 6 ; General Purpose IO Register 3 bit 6 |
.equ GPIOR37 = 7 ; General Purpose IO Register 3 bit 7 |
; GPIOR2 - General Purpose IO Register 2 |
.equ GPIOR20 = 0 ; General Purpose IO Register 2 bit 0 |
.equ GPIOR21 = 1 ; General Purpose IO Register 2 bit 1 |
.equ GPIOR22 = 2 ; General Purpose IO Register 2 bit 2 |
.equ GPIOR23 = 3 ; General Purpose IO Register 2 bit 3 |
.equ GPIOR24 = 4 ; General Purpose IO Register 2 bit 4 |
.equ GPIOR25 = 5 ; General Purpose IO Register 2 bit 5 |
.equ GPIOR26 = 6 ; General Purpose IO Register 2 bit 6 |
.equ GPIOR27 = 7 ; General Purpose IO Register 2 bit 7 |
; GPIOR1 - General Purpose IO Register 1 |
.equ GPIOR10 = 0 ; General Purpose IO Register 1 bit 0 |
.equ GPIOR11 = 1 ; General Purpose IO Register 1 bit 1 |
.equ GPIOR12 = 2 ; General Purpose IO Register 1 bit 2 |
.equ GPIOR13 = 3 ; General Purpose IO Register 1 bit 3 |
.equ GPIOR14 = 4 ; General Purpose IO Register 1 bit 4 |
.equ GPIOR15 = 5 ; General Purpose IO Register 1 bit 5 |
.equ GPIOR16 = 6 ; General Purpose IO Register 1 bit 6 |
.equ GPIOR17 = 7 ; General Purpose IO Register 1 bit 7 |
; GPIOR0 - General Purpose IO Register 0 |
.equ GPIOR00 = 0 ; General Purpose IO Register 0 bit 0 |
.equ GPIOR01 = 1 ; General Purpose IO Register 0 bit 1 |
.equ GPIOR02 = 2 ; General Purpose IO Register 0 bit 2 |
.equ GPIOR03 = 3 ; General Purpose IO Register 0 bit 3 |
.equ GPIOR04 = 4 ; General Purpose IO Register 0 bit 4 |
.equ GPIOR05 = 5 ; General Purpose IO Register 0 bit 5 |
.equ GPIOR06 = 6 ; General Purpose IO Register 0 bit 6 |
.equ GPIOR07 = 7 ; General Purpose IO Register 0 bit 7 |
; PLLCSR - PLL Control And Status Register |
.equ PLOCK = 0 ; PLL Lock Detector |
.equ PLLE = 1 ; PLL Enable |
.equ PCKE = 2 ; PCK Enable |
; ***** PORTE ************************ |
; PORTE - Port E Data Register |
.equ PORTE0 = 0 ; |
.equ PE0 = 0 ; For compatibility |
.equ PORTE1 = 1 ; |
.equ PE1 = 1 ; For compatibility |
.equ PORTE2 = 2 ; |
.equ PE2 = 2 ; For compatibility |
; DDRE - Port E Data Direction Register |
.equ DDE0 = 0 ; |
.equ DDE1 = 1 ; |
.equ DDE2 = 2 ; |
; PINE - Port E Input Pins |
.equ PINE0 = 0 ; |
.equ PINE1 = 1 ; |
.equ PINE2 = 2 ; |
; ***** TIMER_COUNTER_0 ************** |
; TIMSK0 - Timer/Counter0 Interrupt Mask Register |
.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable |
.equ OCIE0A = 1 ; Timer/Counter0 Output Compare Match A Interrupt Enable |
.equ OCIE0B = 2 ; Timer/Counter0 Output Compare Match B Interrupt Enable |
; TIFR0 - Timer/Counter0 Interrupt Flag register |
.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag |
.equ OCF0A = 1 ; Timer/Counter0 Output Compare Flag 0A |
.equ OCF0B = 2 ; Timer/Counter0 Output Compare Flag 0B |
; TCCR0A - Timer/Counter Control Register A |
.equ WGM00 = 0 ; Waveform Generation Mode |
.equ WGM01 = 1 ; Waveform Generation Mode |
.equ COM0B0 = 4 ; Compare Output Mode, Fast PWm |
.equ COM0B1 = 5 ; Compare Output Mode, Fast PWm |
.equ COM0A0 = 6 ; Compare Output Mode, Phase Correct PWM Mode |
.equ COM0A1 = 7 ; Compare Output Mode, Phase Correct PWM Mode |
; TCCR0B - Timer/Counter Control Register B |
.equ CS00 = 0 ; Clock Select |
.equ CS01 = 1 ; Clock Select |
.equ CS02 = 2 ; Clock Select |
.equ WGM02 = 3 ; |
.equ FOC0B = 6 ; Force Output Compare B |
.equ FOC0A = 7 ; Force Output Compare A |
; TCNT0 - Timer/Counter0 |
.equ TCNT0_0 = 0 ; |
.equ TCNT0_1 = 1 ; |
.equ TCNT0_2 = 2 ; |
.equ TCNT0_3 = 3 ; |
.equ TCNT0_4 = 4 ; |
.equ TCNT0_5 = 5 ; |
.equ TCNT0_6 = 6 ; |
.equ TCNT0_7 = 7 ; |
; OCR0A - Timer/Counter0 Output Compare Register |
.equ OCR0_0 = 0 ; |
.equ OCR0_1 = 1 ; |
.equ OCR0_2 = 2 ; |
.equ OCR0_3 = 3 ; |
.equ OCR0_4 = 4 ; |
.equ OCR0_5 = 5 ; |
.equ OCR0_6 = 6 ; |
.equ OCR0_7 = 7 ; |
; OCR0B - Timer/Counter0 Output Compare Register |
;.equ OCR0_0 = 0 ; |
;.equ OCR0_1 = 1 ; |
;.equ OCR0_2 = 2 ; |
;.equ OCR0_3 = 3 ; |
;.equ OCR0_4 = 4 ; |
;.equ OCR0_5 = 5 ; |
;.equ OCR0_6 = 6 ; |
;.equ OCR0_7 = 7 ; |
; GTCCR - General Timer/Counter Control Register |
.equ PSR10 = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0 |
.equ ICPSEL1 = 6 ; Timer1 Input Capture Selection Bit |
.equ TSM = 7 ; Timer/Counter Synchronization Mode |
; ***** TIMER_COUNTER_1 ************** |
; TIMSK1 - Timer/Counter Interrupt Mask Register |
.equ TOIE1 = 0 ; Timer/Counter1 Overflow Interrupt Enable |
.equ OCIE1A = 1 ; Timer/Counter1 Output CompareA Match Interrupt Enable |
.equ OCIE1B = 2 ; Timer/Counter1 Output CompareB Match Interrupt Enable |
.equ ICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable |
; TIFR1 - Timer/Counter Interrupt Flag register |
.equ TOV1 = 0 ; Timer/Counter1 Overflow Flag |
.equ OCF1A = 1 ; Output Compare Flag 1A |
.equ OCF1B = 2 ; Output Compare Flag 1B |
.equ ICF1 = 5 ; Input Capture Flag 1 |
; TCCR1A - Timer/Counter1 Control Register A |
.equ WGM10 = 0 ; Waveform Generation Mode |
.equ WGM11 = 1 ; Waveform Generation Mode |
.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0 |
.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1 |
.equ COM1A0 = 6 ; Comparet Ouput Mode 1A, bit 0 |
.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1 |
; TCCR1B - Timer/Counter1 Control Register B |
.equ CS10 = 0 ; Prescaler source of Timer/Counter 1 |
.equ CS11 = 1 ; Prescaler source of Timer/Counter 1 |
.equ CS12 = 2 ; Prescaler source of Timer/Counter 1 |
.equ WGM12 = 3 ; Waveform Generation Mode |
.equ WGM13 = 4 ; Waveform Generation Mode |
.equ ICES1 = 6 ; Input Capture 1 Edge Select |
.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler |
; TCCR1C - Timer/Counter1 Control Register C |
.equ FOC1B = 6 ; |
.equ FOC1A = 7 ; |
; GTCCR - General Timer/Counter Control Register |
.equ PSRSYNC = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0 |
;.equ TSM = 7 ; Timer/Counter Synchronization Mode |
; ***** AD_CONVERTER ***************** |
; ADMUX - The ADC multiplexer Selection Register |
.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits |
.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits |
.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits |
.equ MUX3 = 3 ; Analog Channel and Gain Selection Bits |
.equ ADLAR = 5 ; Left Adjust Result |
.equ REFS0 = 6 ; Reference Selection Bit 0 |
.equ REFS1 = 7 ; Reference Selection Bit 1 |
; ADCSRA - The ADC Control and Status register |
.equ ADPS0 = 0 ; ADC Prescaler Select Bits |
.equ ADPS1 = 1 ; ADC Prescaler Select Bits |
.equ ADPS2 = 2 ; ADC Prescaler Select Bits |
.equ ADIE = 3 ; ADC Interrupt Enable |
.equ ADIF = 4 ; ADC Interrupt Flag |
.equ ADATE = 5 ; ADC Auto Trigger Enable |
.equ ADSC = 6 ; ADC Start Conversion |
.equ ADEN = 7 ; ADC Enable |
; ADCH - ADC Data Register High Byte |
.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0 |
.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1 |
.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2 |
.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3 |
.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4 |
.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5 |
.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6 |
.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7 |
; ADCL - ADC Data Register Low Byte |
.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0 |
.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1 |
.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2 |
.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3 |
.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4 |
.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5 |
.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6 |
.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7 |
; ADCSRB - ADC Control and Status Register B |
.equ ADTS0 = 0 ; ADC Auto Trigger Source 0 |
.equ ADTS1 = 1 ; ADC Auto Trigger Source 1 |
.equ ADTS2 = 2 ; ADC Auto Trigger Source 2 |
.equ ADASCR = 3 ; |
.equ ADAP = 4 ; |
; DIDR0 - Digital Input Disable Register 0 |
.equ ADC0D = 0 ; ADC0 Digital input Disable |
.equ ADC1D = 1 ; ADC1 Digital input Disable |
.equ ADC2D = 2 ; ADC2 Digital input Disable |
.equ ADC3D = 3 ; ADC3 Digital input Disable |
.equ ADC4D = 4 ; ADC4 Digital input Disable |
.equ ADC5D = 5 ; ADC5 Digital input Disable |
.equ ADC6D = 6 ; ADC6 Digital input Disable |
.equ ADC7D = 7 ; ADC7 Digital input Disable |
; DIDR1 - |
.equ ADC8D = 0 ; |
.equ ADC9D = 1 ; |
.equ ADC10D = 2 ; |
.equ AMP0ND = 3 ; |
.equ AMP0PD = 4 ; |
.equ ACMP0D = 5 ; |
; ***** USART ************************ |
; UDR - USART I/O Data Register |
.equ UDR0 = 0 ; USART I/O Data Register bit 0 |
.equ UDR1 = 1 ; USART I/O Data Register bit 1 |
.equ UDR2 = 2 ; USART I/O Data Register bit 2 |
.equ UDR3 = 3 ; USART I/O Data Register bit 3 |
.equ UDR4 = 4 ; USART I/O Data Register bit 4 |
.equ UDR5 = 5 ; USART I/O Data Register bit 5 |
.equ UDR6 = 6 ; USART I/O Data Register bit 6 |
.equ UDR7 = 7 ; USART I/O Data Register bit 7 |
; UCSRA - USART Control and Status register A |
.equ MPCM = 0 ; Multi-processor Communication Mode |
.equ U2X = 1 ; Double USART Transmission Bit |
.equ UPE = 2 ; USART Parity Error |
.equ DOR = 3 ; Data Overrun |
.equ FE = 4 ; Framing Error |
.equ UDRE = 5 ; USART Data Register Empty |
.equ TXC = 6 ; USART Transmitt Complete |
.equ RXC = 7 ; USART Receive Complete |
; UCSRB - USART Control an Status register B |
.equ TXB8 = 0 ; Transmit Data Bit 8 |
.equ RXB8 = 1 ; Receive Data Bit 8 |
.equ UCSZ2 = 2 ; Character Size |
.equ TXEN = 3 ; Transmitter Enable |
.equ RXEN = 4 ; Receiver Enable |
.equ UDRIE = 5 ; USART Data Register Empty Interrupt Enable |
.equ TXCIE = 6 ; TX Complete Interrupt Enable |
.equ RXCIE = 7 ; RX Complete Interrupt Enable |
; UCSRC - USART Control an Status register C |
.equ UCPOL = 0 ; Clock Polarity |
.equ UCSZ0 = 1 ; Character Size Bit 0 |
.equ UCSZ1 = 2 ; Character Size Bit 1 |
.equ USBS = 3 ; Stop Bit Select |
.equ UPM0 = 4 ; Parity Mode Bit 0 |
.equ UPM1 = 5 ; Parity Mode Bit 1 |
.equ UMSEL0 = 6 ; USART Mode Select |
; UBRRH - USART Baud Rate Register High Byte |
.equ UBRR8 = 0 ; USART Baud Rate Register Bit 8 |
.equ UBRR9 = 1 ; USART Baud Rate Register Bit 9 |
.equ UBRR10 = 2 ; USART Baud Rate Register Bit 10 |
.equ UBRR11 = 3 ; USART Baud Rate Register Bit 11 |
; UBRRL - USART Baud Rate Register Low Byte |
.equ UBRR0 = 0 ; USART Baud Rate Register bit 0 |
.equ UBRR1 = 1 ; USART Baud Rate Register bit 1 |
.equ UBRR2 = 2 ; USART Baud Rate Register bit 2 |
.equ UBRR3 = 3 ; USART Baud Rate Register bit 3 |
.equ UBRR4 = 4 ; USART Baud Rate Register bit 4 |
.equ UBRR5 = 5 ; USART Baud Rate Register bit 5 |
.equ UBRR6 = 6 ; USART Baud Rate Register bit 6 |
.equ UBRR7 = 7 ; USART Baud Rate Register bit 7 |
; ***** SPI ************************** |
; SPDR - SPI Data Register |
.equ SPDR0 = 0 ; SPI Data Register bit 0 |
.equ SPDR1 = 1 ; SPI Data Register bit 1 |
.equ SPDR2 = 2 ; SPI Data Register bit 2 |
.equ SPDR3 = 3 ; SPI Data Register bit 3 |
.equ SPDR4 = 4 ; SPI Data Register bit 4 |
.equ SPDR5 = 5 ; SPI Data Register bit 5 |
.equ SPDR6 = 6 ; SPI Data Register bit 6 |
.equ SPDR7 = 7 ; SPI Data Register bit 7 |
; SPSR - SPI Status Register |
.equ SPI2X = 0 ; Double SPI Speed Bit |
.equ WCOL = 6 ; Write Collision Flag |
.equ SPIF = 7 ; SPI Interrupt Flag |
; SPCR - SPI Control Register |
.equ SPR0 = 0 ; SPI Clock Rate Select 0 |
.equ SPR1 = 1 ; SPI Clock Rate Select 1 |
.equ CPHA = 2 ; Clock Phase |
.equ CPOL = 3 ; Clock polarity |
.equ MSTR = 4 ; Master/Slave Select |
.equ DORD = 5 ; Data Order |
.equ SPE = 6 ; SPI Enable |
.equ SPIE = 7 ; SPI Interrupt Enable |
; ***** WATCHDOG ********************* |
; WDTCSR - Watchdog Timer Control Register |
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 |
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 |
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 |
.equ WDE = 3 ; Watch Dog Enable |
.equ WDCE = 4 ; Watchdog Change Enable |
.equ WDP3 = 5 ; Watchdog Timer Prescaler Bit 3 |
.equ WDIE = 6 ; Watchdog Timeout Interrupt Enable |
.equ WDIF = 7 ; Watchdog Timeout Interrupt Flag |
; ***** EXTERNAL_INTERRUPT *********** |
; EICRA - External Interrupt Control Register A |
.equ ISC00 = 0 ; External Interrupt Sense Control Bit |
.equ ISC01 = 1 ; External Interrupt Sense Control Bit |
.equ ISC10 = 2 ; External Interrupt Sense Control Bit |
.equ ISC11 = 3 ; External Interrupt Sense Control Bit |
.equ ISC20 = 4 ; External Interrupt Sense Control Bit |
.equ ISC21 = 5 ; External Interrupt Sense Control Bit |
.equ ISC30 = 6 ; External Interrupt Sense Control Bit |
.equ ISC31 = 7 ; External Interrupt Sense Control Bit |
; EIMSK - External Interrupt Mask Register |
.equ INT0 = 0 ; External Interrupt Request 0 Enable |
.equ INT1 = 1 ; External Interrupt Request 1 Enable |
.equ INT2 = 2 ; External Interrupt Request 2 Enable |
.equ INT3 = 3 ; External Interrupt Request 3 Enable |
; EIFR - External Interrupt Flag Register |
.equ INTF0 = 0 ; External Interrupt Flag 0 |
.equ INTF1 = 1 ; External Interrupt Flag 1 |
.equ INTF2 = 2 ; External Interrupt Flag 2 |
.equ INTF3 = 3 ; External Interrupt Flag 3 |
; ***** LOCKSBITS ******************************************************** |
.equ LB1 = 0 ; Lock bit |
.equ LB2 = 1 ; Lock bit |
.equ BLB01 = 2 ; Boot Lock bit |
.equ BLB02 = 3 ; Boot Lock bit |
.equ BLB11 = 4 ; Boot lock bit |
.equ BLB12 = 5 ; Boot lock bit |
; ***** FUSES ************************************************************ |
; LOW fuse bits |
.equ CKSEL0 = 0 ; Select Clock Source |
.equ CKSEL1 = 1 ; Select Clock Source |
.equ CKSEL2 = 2 ; Select Clock Source |
.equ CKSEL3 = 3 ; Select Clock Source |
.equ SUT0 = 4 ; Select start-up time |
.equ SUT1 = 5 ; Select start-up time |
.equ CKOUT = 6 ; Oscillator output option |
.equ CLKDIV8 = 7 ; Divide clock by 8 |
; HIGH fuse bits |
.equ BOOTRST = 0 ; Select Reset Vector |
.equ BOOTSZ0 = 1 ; Select Boot Size |
.equ BOOTSZ1 = 2 ; Select Boot Size |
.equ EESAVE = 3 ; EEPROM memory is preserved through chip erase |
.equ WDTON = 4 ; Watchdog timer always on |
.equ SPIEN = 5 ; Enable Serial programming and Data Downloading |
.equ JTAGEN = 6 ; Enable JTAG |
.equ OCDEN = 7 ; Enable OCD |
; EXTENDED fuse bits |
.equ TA0SEL = 0 ; (Reserved to factory tests) |
.equ BODLEVEL0 = 1 ; Brown-out Detector trigger level |
.equ BODLEVEL1 = 2 ; Brown-out Detector trigger level |
.equ BODLEVEL2 = 3 ; Brown out detector trigger level |
; ***** CPU REGISTER DEFINITIONS ***************************************** |
.def XH = r27 |
.def XL = r26 |
.def YH = r29 |
.def YL = r28 |
.def ZH = r31 |
.def ZL = r30 |
; ***** DATA MEMORY DECLARATIONS ***************************************** |
.equ FLASHEND = 0x0fff ; Note: Word address |
.equ IOEND = 0x00ff |
.equ SRAM_START = 0x0100 |
.equ SRAM_SIZE = 512 |
.equ RAMEND = 0x02ff |
.equ XRAMEND = 0x0000 |
.equ E2END = 0x01ff |
.equ EEPROMEND = 0x01ff |
.equ EEADRBITS = 9 |
#pragma AVRPART MEMORY PROG_FLASH 8192 |
#pragma AVRPART MEMORY EEPROM 512 |
#pragma AVRPART MEMORY INT_SRAM SIZE 512 |
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x100 |
; ***** BOOTLOADER DECLARATIONS ****************************************** |
.equ NRWW_START_ADDR = 0xc00 |
.equ NRWW_STOP_ADDR = 0xfff |
.equ RWW_START_ADDR = 0x0 |
.equ RWW_STOP_ADDR = 0xbff |
.equ PAGESIZE = 32 |
.equ FIRSTBOOTSTART = 0xf80 |
.equ SECONDBOOTSTART = 0xf00 |
.equ THIRDBOOTSTART = 0xe00 |
.equ FOURTHBOOTSTART = 0xc00 |
.equ SMALLBOOTSTART = FIRSTBOOTSTART |
.equ LARGEBOOTSTART = FOURTHBOOTSTART |
; ***** INTERRUPT VECTORS ************************************************ |
.equ PSC2_CAPTaddr = 0x0001 ; PSC2 Capture Event |
.equ PSC2_ECaddr = 0x0002 ; PSC2 End Cycle |
.equ PSC1_CAPTaddr = 0x0003 ; PSC1 Capture Event |
.equ PSC1_ECaddr = 0x0004 ; PSC1 End Cycle |
.equ PSC0_CAPTaddr = 0x0005 ; PSC0 Capture Event |
.equ PSC0_ECaddr = 0x0006 ; PSC0 End Cycle |
.equ ACI0addr = 0x0007 ; Analog Comparator 0 |
.equ ACI1addr = 0x0008 ; Analog Comparator 1 |
.equ ACI2addr = 0x0009 ; Analog Comparator 2 |
.equ INT0addr = 0x000a ; External Interrupt Request 0 |
.equ ICP1addr = 0x000b ; Timer/Counter1 Capture Event |
.equ OC1Aaddr = 0x000c ; Timer/Counter1 Compare Match A |
.equ OC1Baddr = 0x000d ; Timer/Counter Compare Match B |
.equ OVF1addr = 0x000f ; Timer/Counter1 Overflow |
.equ OC0Aaddr = 0x0010 ; Timer/Counter0 Compare Match A |
.equ OVF0addr = 0x0011 ; Timer/Counter0 Overflow |
.equ ADCCaddr = 0x0012 ; ADC Conversion Complete |
.equ INT1addr = 0x0013 ; External Interrupt Request 1 |
.equ SPIaddr = 0x0014 ; SPI Serial Transfer Complete |
.equ URXCaddr = 0x0015 ; USART, Rx Complete |
.equ UDREaddr = 0x0016 ; USART Data Register Empty |
.equ UTXCaddr = 0x0017 ; USART, Tx Complete |
.equ INT2addr = 0x0018 ; External Interrupt Request 2 |
.equ WDTaddr = 0x0019 ; Watchdog Timeout Interrupt |
.equ ERDYaddr = 0x001a ; EEPROM Ready |
.equ OC0Baddr = 0x001b ; Timer Counter 0 Compare Match B |
.equ INT3addr = 0x001c ; External Interrupt Request 3 |
.equ SPMRaddr = 0x001f ; Store Program Memory Read |
.equ INT_VECTORS_SIZE = 29 ; size in words |
#endif /* _PWM3DEF_INC_ */ |
; ***** END OF FILE ****************************************************** |
/contrib/toolchain/avra/includes/tn11def.inc |
---|
0,0 → 1,233 |
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** |
;***** Created: 2005-01-11 10:31 ******* Source: ATtiny11.xml ************ |
;************************************************************************* |
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y |
;* |
;* Number : AVR000 |
;* File Name : "tn11def.inc" |
;* Title : Register/Bit Definitions for the ATtiny11 |
;* Date : 2005-01-11 |
;* Version : 2.14 |
;* Support E-mail : avr@atmel.com |
;* Target MCU : ATtiny11 |
;* |
;* DESCRIPTION |
;* When including this file in the assembly program file, all I/O register |
;* names and I/O register bit names appearing in the data book can be used. |
;* In addition, the six registers forming the three data pointers X, Y and |
;* Z have been assigned names XL - ZH. Highest RAM address for Internal |
;* SRAM is also defined |
;* |
;* The Register names are represented by their hexadecimal address. |
;* |
;* The Register Bit names are represented by their bit number (0-7). |
;* |
;* Please observe the difference in using the bit names with instructions |
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" |
;* (skip if bit in register set/cleared). The following example illustrates |
;* this: |
;* |
;* in r16,PORTB ;read PORTB latch |
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) |
;* out PORTB,r16 ;output to PORTB |
;* |
;* in r16,TIFR ;read the Timer Interrupt Flag Register |
;* sbrc r16,TOV0 ;test the overflow flag (use bit#) |
;* rjmp TOV0_is_set ;jump if set |
;* ... ;otherwise do something else |
;************************************************************************* |
#ifndef _TN11DEF_INC_ |
#define _TN11DEF_INC_ |
#pragma partinc 0 |
; ***** SPECIFY DEVICE *************************************************** |
.device ATtiny11 |
#pragma AVRPART ADMIN PART_NAME ATtiny11 |
.equ SIGNATURE_000 = 0x1e |
.equ SIGNATURE_001 = 0x90 |
.equ SIGNATURE_002 = 0x04 |
#pragma AVRPART CORE CORE_VERSION V0E |
; ***** I/O REGISTER DEFINITIONS ***************************************** |
; NOTE: |
; Definitions marked "MEMORY MAPPED"are extended I/O ports |
; and cannot be used with IN/OUT instructions |
.equ SREG = 0x3f |
.equ GIMSK = 0x3b |
.equ GIFR = 0x3a |
.equ TIMSK = 0x39 |
.equ TIFR = 0x38 |
.equ MCUCR = 0x35 |
.equ MCUSR = 0x34 |
.equ TCCR0 = 0x33 |
.equ TCNT0 = 0x32 |
.equ WDTCR = 0x21 |
.equ PORTB = 0x18 |
.equ DDRB = 0x17 |
.equ PINB = 0x16 |
.equ ACSR = 0x08 |
; ***** BIT DEFINITIONS ************************************************** |
; ***** ANALOG_COMPARATOR ************ |
; ACSR - Analog Comparator Control And Status Register |
.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 |
.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 |
.equ ACIE = 3 ; Analog Comparator Interrupt Enable |
.equ ACI = 4 ; Analog Comparator Interrupt Flag |
.equ ACO = 5 ; Analog Comparator Output |
.equ ACD = 7 ; Analog Comparator Disable |
; ***** EXTERNAL_INTERRUPT *********** |
; GIMSK - General Interrupt Mask Register |
.equ PCIE = 5 ; Pin Change Interrupt Enable |
.equ INT0 = 6 ; External Interrupt Request 0 Enable |
; GIFR - General Interrupt Flag register |
.equ PCIF = 5 ; Pin Change Interrupt Flag |
.equ INTF0 = 6 ; External Interrupt Flag 0 |
; ***** PORTB ************************ |
; PORTB - Data Register, Port B |
.equ PORTB0 = 0 ; |
.equ PB0 = 0 ; For compatibility |
.equ PORTB1 = 1 ; |
.equ PB1 = 1 ; For compatibility |
.equ PORTB2 = 2 ; |
.equ PB2 = 2 ; For compatibility |
.equ PORTB3 = 3 ; |
.equ PB3 = 3 ; For compatibility |
.equ PORTB4 = 4 ; |
.equ PB4 = 4 ; For compatibility |
; DDRB - Data Direction Register, Port B |
.equ DDB0 = 0 ; |
.equ DDB1 = 1 ; |
.equ DDB2 = 2 ; |
.equ DDB3 = 3 ; |
.equ DDB4 = 4 ; |
; PINB - Input Pins, Port B |
.equ PINB0 = 0 ; |
.equ PINB1 = 1 ; |
.equ PINB2 = 2 ; |
.equ PINB3 = 3 ; |
.equ PINB4 = 4 ; |
.equ PINB5 = 5 ; |
; ***** TIMER_COUNTER_0 ************** |
; TIMSK - Timer/Counter Interrupt Mask Register |
.equ TOIE0 = 1 ; Timer/Counter0 Overflow Interrupt Enable |
; TIFR - Timer/Counter Interrupt Flag register |
.equ TOV0 = 1 ; Timer/Counter0 Overflow Flag |
; TCCR0 - Timer/Counter0 Control Register |
.equ CS00 = 0 ; Clock Select0 bit 0 |
.equ CS01 = 1 ; Clock Select0 bit 1 |
.equ CS02 = 2 ; Clock Select0 bit 2 |
; TCNT0 - Timer Counter 0 |
.equ TCNT00 = 0 ; Timer Counter 0 bit 0 |
.equ TCNT01 = 1 ; Timer Counter 0 bit 1 |
.equ TCNT02 = 2 ; Timer Counter 0 bit 2 |
.equ TCNT03 = 3 ; Timer Counter 0 bit 3 |
.equ TCNT04 = 4 ; Timer Counter 0 bit 4 |
.equ TCNT05 = 5 ; Timer Counter 0 bit 5 |
.equ TCNT06 = 6 ; Timer Counter 0 bit 6 |
.equ TCNT07 = 7 ; Timer Counter 0 bit 7 |
; ***** WATCHDOG ********************* |
; WDTCR - Watchdog Timer Control Register |
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 |
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 |
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 |
.equ WDE = 3 ; Watch Dog Enable |
.equ WDTOE = 4 ; RW |
.equ WDDE = WDTOE ; For compatibility |
; ***** CPU ************************** |
; SREG - Status Register |
.equ SREG_C = 0 ; Carry Flag |
.equ SREG_Z = 1 ; Zero Flag |
.equ SREG_N = 2 ; Negative Flag |
.equ SREG_V = 3 ; Two's Complement Overflow Flag |
.equ SREG_S = 4 ; Sign Bit |
.equ SREG_H = 5 ; Half Carry Flag |
.equ SREG_T = 6 ; Bit Copy Storage |
.equ SREG_I = 7 ; Global Interrupt Enable |
; MCUCR - MCU Control Register |
.equ ISC00 = 0 ; Interrupt Sense Control 0 bit 0 |
.equ ISC01 = 1 ; Interrupt Sense Control 0 bit 1 |
.equ SM = 4 ; Sleep Mode |
.equ SE = 5 ; Sleep Enable |
; MCUSR - MCU Status register |
.equ PORF = 0 ; Power-On Reset Flag |
.equ EXTRF = 1 ; External Reset Flag |
; ***** LOCKSBITS ******************************************************** |
.equ LB1 = 0 ; Lockbit |
.equ LB2 = 1 ; Lockbit |
; ***** FUSES ************************************************************ |
; LOW fuse bits |
; ***** CPU REGISTER DEFINITIONS ***************************************** |
.def XH = r27 |
.def XL = r26 |
.def YH = r29 |
.def YL = r28 |
.def ZH = r31 |
.def ZL = r30 |
; ***** DATA MEMORY DECLARATIONS ***************************************** |
.equ FLASHEND = 0x01ff ; Note: Word address |
.equ IOEND = 0x003f |
.equ SRAM_SIZE = 0 |
.equ RAMEND = 0x0000 |
.equ XRAMEND = 0x0000 |
.equ E2END = 0x0000 |
.equ EEPROMEND = 0x0000 |
.equ EEADRBITS = 4294967295 |
#pragma AVRPART MEMORY PROG_FLASH 1024 |
#pragma AVRPART MEMORY EEPROM 0 |
#pragma AVRPART MEMORY INT_SRAM SIZE 0 |
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x0 |
; ***** INTERRUPT VECTORS ************************************************ |
.equ INT0addr = 0x0001 ; External Interrupt 0 |
.equ PCI0addr = 0x0002 ; External Interrupt Request 0 |
.equ OVF0addr = 0x0003 ; Timer/Counter0 Overflow |
.equ ACIaddr = 0x0004 ; Analog Comparator |
.equ INT_VECTORS_SIZE = 5 ; size in words |
#pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED break |
#endif /* _TN11DEF_INC_ */ |
; ***** END OF FILE ****************************************************** |
/contrib/toolchain/avra/includes/tn12def.inc |
---|
0,0 → 1,279 |
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** |
;***** Created: 2005-01-11 10:31 ******* Source: ATtiny12.xml ************ |
;************************************************************************* |
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y |
;* |
;* Number : AVR000 |
;* File Name : "tn12def.inc" |
;* Title : Register/Bit Definitions for the ATtiny12 |
;* Date : 2005-01-11 |
;* Version : 2.14 |
;* Support E-mail : avr@atmel.com |
;* Target MCU : ATtiny12 |
;* |
;* DESCRIPTION |
;* When including this file in the assembly program file, all I/O register |
;* names and I/O register bit names appearing in the data book can be used. |
;* In addition, the six registers forming the three data pointers X, Y and |
;* Z have been assigned names XL - ZH. Highest RAM address for Internal |
;* SRAM is also defined |
;* |
;* The Register names are represented by their hexadecimal address. |
;* |
;* The Register Bit names are represented by their bit number (0-7). |
;* |
;* Please observe the difference in using the bit names with instructions |
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" |
;* (skip if bit in register set/cleared). The following example illustrates |
;* this: |
;* |
;* in r16,PORTB ;read PORTB latch |
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) |
;* out PORTB,r16 ;output to PORTB |
;* |
;* in r16,TIFR ;read the Timer Interrupt Flag Register |
;* sbrc r16,TOV0 ;test the overflow flag (use bit#) |
;* rjmp TOV0_is_set ;jump if set |
;* ... ;otherwise do something else |
;************************************************************************* |
#ifndef _TN12DEF_INC_ |
#define _TN12DEF_INC_ |
#pragma partinc 0 |
; ***** SPECIFY DEVICE *************************************************** |
.device ATtiny12 |
#pragma AVRPART ADMIN PART_NAME ATtiny12 |
.equ SIGNATURE_000 = 0x1e |
.equ SIGNATURE_001 = 0x90 |
.equ SIGNATURE_002 = 0x05 |
#pragma AVRPART CORE CORE_VERSION V0E |
; ***** I/O REGISTER DEFINITIONS ***************************************** |
; NOTE: |
; Definitions marked "MEMORY MAPPED"are extended I/O ports |
; and cannot be used with IN/OUT instructions |
.equ SREG = 0x3f |
.equ GIMSK = 0x3b |
.equ GIFR = 0x3a |
.equ TIMSK = 0x39 |
.equ TIFR = 0x38 |
.equ MCUCR = 0x35 |
.equ MCUSR = 0x34 |
.equ TCCR0 = 0x33 |
.equ TCNT0 = 0x32 |
.equ OSCCAL = 0x31 |
.equ WDTCR = 0x21 |
.equ EEAR = 0x1e |
.equ EEDR = 0x1d |
.equ EECR = 0x1c |
.equ PORTB = 0x18 |
.equ DDRB = 0x17 |
.equ PINB = 0x16 |
.equ ACSR = 0x08 |
; ***** BIT DEFINITIONS ************************************************** |
; ***** ANALOG_COMPARATOR ************ |
; ACSR - Analog Comparator Control And Status Register |
.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 |
.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 |
.equ ACIE = 3 ; Analog Comparator Interrupt Enable |
.equ ACI = 4 ; Analog Comparator Interrupt Flag |
.equ ACO = 5 ; Analog Comparator Output |
.equ AINBG = 6 ; Analog Comparator Bandgap Select |
.equ ACD = 7 ; Analog Comparator Disable |
; ***** CPU ************************** |
; SREG - Status Register |
.equ SREG_C = 0 ; Carry Flag |
.equ SREG_Z = 1 ; Zero Flag |
.equ SREG_N = 2 ; Negative Flag |
.equ SREG_V = 3 ; Two's Complement Overflow Flag |
.equ SREG_S = 4 ; Sign Bit |
.equ SREG_H = 5 ; Half Carry Flag |
.equ SREG_T = 6 ; Bit Copy Storage |
.equ SREG_I = 7 ; Global Interrupt Enable |
; MCUCR - MCU Control Register |
.equ ISC00 = 0 ; Interrupt Sense Control 0 bit 0 |
.equ ISC01 = 1 ; Interrupt Sense Control 0 bit 1 |
.equ SM = 4 ; Sleep Mode |
.equ SE = 5 ; Sleep Enable |
.equ PUD = 6 ; Pull-up Disable |
; MCUSR - MCU Status register |
.equ PORF = 0 ; Power-On Reset Flag |
.equ EXTRF = 1 ; External Reset Flag |
.equ BORF = 2 ; Brown-out Reset Flag |
.equ WDRF = 3 ; Watchdog Reset Flag |
; OSCCAL - Status Register |
.equ CAL0 = 0 ; Oscillator Calibration Value Bit 0 |
.equ CAL1 = 1 ; Oscillator Calibration Value Bit 1 |
.equ CAL2 = 2 ; Oscillator Calibration Value Bit 2 |
.equ CAL3 = 3 ; Oscillator Calibration Value Bit 3 |
.equ CAL4 = 4 |
.equ CAL5 = 5 ; Oscillator Calibration Value Bit 5 |
.equ CAL6 = 6 ; Oscillator Calibration Value Bit 6 |
.equ CAL7 = 7 ; Oscillator Calibration Value Bit 7 |
; ***** EXTERNAL_INTERRUPT *********** |
; GIMSK - General Interrupt Mask Register |
.equ PCIE = 5 ; Pin Change Interrupt Enable |
.equ INT0 = 6 ; External Interrupt Request 0 Enable |
; GIFR - General Interrupt Flag register |
.equ PCIF = 5 ; Pin Change Interrupt Flag |
.equ INTF0 = 6 ; External Interrupt Flag 0 |
; ***** EEPROM *********************** |
; EEAR - EEPROM Read/Write Access |
.equ EEAR0 = 0 ; EEPROM Read/Write Access bit 0 |
.equ EEAR1 = 1 ; EEPROM Read/Write Access bit 1 |
.equ EEAR2 = 2 ; EEPROM Read/Write Access bit 2 |
.equ EEAR3 = 3 ; EEPROM Read/Write Access bit 3 |
.equ EEAR4 = 4 ; EEPROM Read/Write Access bit 4 |
.equ EEAR5 = 5 ; EEPROM Read/Write Access bit 5 |
; EEDR - EEPROM Data Register |
.equ EEDR0 = 0 ; EEPROM Data Register bit 0 |
.equ EEDR1 = 1 ; EEPROM Data Register bit 1 |
.equ EEDR2 = 2 ; EEPROM Data Register bit 2 |
.equ EEDR3 = 3 ; EEPROM Data Register bit 3 |
.equ EEDR4 = 4 ; EEPROM Data Register bit 4 |
.equ EEDR5 = 5 ; EEPROM Data Register bit 5 |
.equ EEDR6 = 6 ; EEPROM Data Register bit 6 |
.equ EEDR7 = 7 ; EEPROM Data Register bit 7 |
; EECR - EEPROM Control Register |
.equ EERE = 0 ; EEPROM Read Enable |
.equ EEWE = 1 ; EEPROM Write Enable |
.equ EEMWE = 2 ; EEPROM Master Write Enable |
.equ EERIE = 3 ; EEProm Ready Interrupt Enable |
; ***** PORTB ************************ |
; PORTB - Data Register, Port B |
.equ PORTB0 = 0 ; |
.equ PB0 = 0 ; For compatibility |
.equ PORTB1 = 1 ; |
.equ PB1 = 1 ; For compatibility |
.equ PORTB2 = 2 ; |
.equ PB2 = 2 ; For compatibility |
.equ PORTB3 = 3 ; |
.equ PB3 = 3 ; For compatibility |
.equ PORTB4 = 4 ; |
.equ PB4 = 4 ; For compatibility |
; DDRB - Data Direction Register, Port B |
.equ DDB0 = 0 ; |
.equ DDB1 = 1 ; |
.equ DDB2 = 2 ; |
.equ DDB3 = 3 ; |
.equ DDB4 = 4 ; |
.equ DDB5 = 5 ; |
; PINB - Input Pins, Port B |
.equ PINB0 = 0 ; |
.equ PINB1 = 1 ; |
.equ PINB2 = 2 ; |
.equ PINB3 = 3 ; |
.equ PINB4 = 4 ; |
.equ PINB5 = 5 ; |
; ***** TIMER_COUNTER_0 ************** |
; TIMSK - Timer/Counter Interrupt Mask Register |
.equ TOIE0 = 1 ; Timer/Counter0 Overflow Interrupt Enable |
; TIFR - Timer/Counter Interrupt Flag register |
.equ TOV0 = 1 ; Timer/Counter0 Overflow Flag |
; TCCR0 - Timer/Counter0 Control Register |
.equ CS00 = 0 ; Clock Select0 bit 0 |
.equ CS01 = 1 ; Clock Select0 bit 1 |
.equ CS02 = 2 ; Clock Select0 bit 2 |
; TCNT0 - Timer Counter 0 |
.equ TCNT00 = 0 ; Timer Counter 0 bit 0 |
.equ TCNT01 = 1 ; Timer Counter 0 bit 1 |
.equ TCNT02 = 2 ; Timer Counter 0 bit 2 |
.equ TCNT03 = 3 ; Timer Counter 0 bit 3 |
.equ TCNT04 = 4 ; Timer Counter 0 bit 4 |
.equ TCNT05 = 5 ; Timer Counter 0 bit 5 |
.equ TCNT06 = 6 ; Timer Counter 0 bit 6 |
.equ TCNT07 = 7 ; Timer Counter 0 bit 7 |
; ***** WATCHDOG ********************* |
; WDTCR - Watchdog Timer Control Register |
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 |
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 |
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 |
.equ WDE = 3 ; Watch Dog Enable |
.equ WDTOE = 4 ; RW |
.equ WDDE = WDTOE ; For compatibility |
; ***** LOCKSBITS ******************************************************** |
.equ LB1 = 0 ; Lockbit |
.equ LB2 = 1 ; Lockbit |
; ***** FUSES ************************************************************ |
; LOW fuse bits |
; ***** CPU REGISTER DEFINITIONS ***************************************** |
.def XH = r27 |
.def XL = r26 |
.def YH = r29 |
.def YL = r28 |
.def ZH = r31 |
.def ZL = r30 |
; ***** DATA MEMORY DECLARATIONS ***************************************** |
.equ FLASHEND = 0x01ff ; Note: Word address |
.equ IOEND = 0x003f |
.equ SRAM_SIZE = 0 |
.equ RAMEND = 0x0000 |
.equ XRAMEND = 0x0000 |
.equ E2END = 0x003f |
.equ EEPROMEND = 0x003f |
.equ EEADRBITS = 6 |
#pragma AVRPART MEMORY PROG_FLASH 1024 |
#pragma AVRPART MEMORY EEPROM 64 |
#pragma AVRPART MEMORY INT_SRAM SIZE 0 |
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x0 |
; ***** INTERRUPT VECTORS ************************************************ |
.equ INT0addr = 0x0001 ; External Interrupt 0 |
.equ PCI0addr = 0x0002 ; External Interrupt Request 0 |
.equ OVF0addr = 0x0003 ; Timer/Counter0 Overflow |
.equ ERDYaddr = 0x0004 ; EEPROM Ready |
.equ ACIaddr = 0x0005 ; Analog Comparator |
.equ INT_VECTORS_SIZE = 6 ; size in words |
#pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED break |
#endif /* _TN12DEF_INC_ */ |
; ***** END OF FILE ****************************************************** |
/contrib/toolchain/avra/includes/tn13def.inc |
---|
0,0 → 1,468 |
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** |
;***** Created: 2005-01-11 10:31 ******* Source: ATtiny13.xml ************ |
;************************************************************************* |
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y |
;* |
;* Number : AVR000 |
;* File Name : "tn13def.inc" |
;* Title : Register/Bit Definitions for the ATtiny13 |
;* Date : 2005-01-11 |
;* Version : 2.14 |
;* Support E-mail : avr@atmel.com |
;* Target MCU : ATtiny13 |
;* |
;* DESCRIPTION |
;* When including this file in the assembly program file, all I/O register |
;* names and I/O register bit names appearing in the data book can be used. |
;* In addition, the six registers forming the three data pointers X, Y and |
;* Z have been assigned names XL - ZH. Highest RAM address for Internal |
;* SRAM is also defined |
;* |
;* The Register names are represented by their hexadecimal address. |
;* |
;* The Register Bit names are represented by their bit number (0-7). |
;* |
;* Please observe the difference in using the bit names with instructions |
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" |
;* (skip if bit in register set/cleared). The following example illustrates |
;* this: |
;* |
;* in r16,PORTB ;read PORTB latch |
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) |
;* out PORTB,r16 ;output to PORTB |
;* |
;* in r16,TIFR ;read the Timer Interrupt Flag Register |
;* sbrc r16,TOV0 ;test the overflow flag (use bit#) |
;* rjmp TOV0_is_set ;jump if set |
;* ... ;otherwise do something else |
;************************************************************************* |
#ifndef _TN13DEF_INC_ |
#define _TN13DEF_INC_ |
#pragma partinc 0 |
; ***** SPECIFY DEVICE *************************************************** |
.device ATtiny13 |
#pragma AVRPART ADMIN PART_NAME ATtiny13 |
.equ SIGNATURE_000 = 0x1e |
.equ SIGNATURE_001 = 0x90 |
.equ SIGNATURE_002 = 0x07 |
#pragma AVRPART CORE CORE_VERSION V2 |
#pragma AVRPART CORE NEW_INSTRUCTIONS lpm rd,z+ |
; ***** I/O REGISTER DEFINITIONS ***************************************** |
; NOTE: |
; Definitions marked "MEMORY MAPPED"are extended I/O ports |
; and cannot be used with IN/OUT instructions |
.equ SREG = 0x3f |
.equ SPL = 0x3d |
.equ GIMSK = 0x3b |
.equ GIFR = 0x3a |
.equ TIMSK0 = 0x39 |
.equ TIFR0 = 0x38 |
.equ SPMCSR = 0x37 |
.equ OCR0A = 0x36 |
.equ MCUCR = 0x35 |
.equ MCUSR = 0x34 |
.equ TCCR0B = 0x33 |
.equ TCNT0 = 0x32 |
.equ OSCCAL = 0x31 |
.equ TCCR0A = 0x2f |
.equ DWDR = 0x2e |
.equ OCR0B = 0x29 |
.equ GTCCR = 0x28 |
.equ CLKPR = 0x26 |
.equ WDTCR = 0x21 |
.equ EEAR = 0x1e |
.equ EEDR = 0x1d |
.equ EECR = 0x1c |
.equ PORTB = 0x18 |
.equ DDRB = 0x17 |
.equ PINB = 0x16 |
.equ PCMSK = 0x15 |
.equ DIDR0 = 0x14 |
.equ ACSR = 0x08 |
.equ ADMUX = 0x07 |
.equ ADCSRA = 0x06 |
.equ ADCH = 0x05 |
.equ ADCL = 0x04 |
.equ ADCSRB = 0x03 |
; ***** BIT DEFINITIONS ************************************************** |
; ***** AD_CONVERTER ***************** |
; ADMUX - The ADC multiplexer Selection Register |
.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits |
.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits |
.equ ADLAR = 5 ; Left Adjust Result |
.equ REFS0 = 6 ; Reference Selection Bit 0 |
; ADCSRA - The ADC Control and Status register |
.equ ADPS0 = 0 ; ADC Prescaler Select Bits |
.equ ADPS1 = 1 ; ADC Prescaler Select Bits |
.equ ADPS2 = 2 ; ADC Prescaler Select Bits |
.equ ADIE = 3 ; ADC Interrupt Enable |
.equ ADIF = 4 ; ADC Interrupt Flag |
.equ ADATE = 5 ; ADC Auto Trigger Enable |
.equ ADSC = 6 ; ADC Start Conversion |
.equ ADEN = 7 ; ADC Enable |
; ADCH - ADC Data Register High Byte |
.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0 |
.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1 |
.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2 |
.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3 |
.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4 |
.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5 |
.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6 |
.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7 |
; ADCL - ADC Data Register Low Byte |
.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0 |
.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1 |
.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2 |
.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3 |
.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4 |
.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5 |
.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6 |
.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7 |
; ADCSRB - ADC Control and Status Register B |
.equ ADTS0 = 0 ; ADC Auto Trigger Source 0 |
.equ ADTS1 = 1 ; ADC Auto Trigger Source 1 |
.equ ADTS2 = 2 ; ADC Auto Trigger Source 2 |
; DIDR0 - Digital Input Disable Register 0 |
.equ ADC1D = 2 ; ADC2 Digital input Disable |
.equ ADC3D = 3 ; ADC3 Digital input Disable |
.equ ADC2D = 4 ; ADC2 Digital input Disable |
.equ ADC0D = 5 ; ADC0 Digital input Disable |
; ***** ANALOG_COMPARATOR ************ |
; ADCSRB - ADC Control and Status Register B |
.equ ACME = 6 ; Analog Comparator Multiplexer Enable |
; ACSR - Analog Comparator Control And Status Register |
.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 |
.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 |
.equ ACIE = 3 ; Analog Comparator Interrupt Enable |
.equ ACI = 4 ; Analog Comparator Interrupt Flag |
.equ ACO = 5 ; Analog Compare Output |
.equ ACBG = 6 ; Analog Comparator Bandgap Select |
.equ AINBG = ACBG ; For compatibility |
.equ ACD = 7 ; Analog Comparator Disable |
; DIDR0 - |
.equ AIN0D = 0 ; AIN0 Digital Input Disable |
.equ AIN1D = 1 ; AIN1 Digital Input Disable |
; ***** EEPROM *********************** |
; EEAR - EEPROM Read/Write Access |
.equ EEARL = EEAR ; For compatibility |
.equ EEAR0 = 0 ; EEPROM Read/Write Access bit 0 |
.equ EEAR1 = 1 ; EEPROM Read/Write Access bit 1 |
.equ EEAR2 = 2 ; EEPROM Read/Write Access bit 2 |
.equ EEAR3 = 3 ; EEPROM Read/Write Access bit 3 |
.equ EEAR4 = 4 ; EEPROM Read/Write Access bit 4 |
.equ EEAR5 = 5 ; EEPROM Read/Write Access bit 5 |
; EEDR - EEPROM Data Register |
.equ EEDR0 = 0 ; EEPROM Data Register bit 0 |
.equ EEDR1 = 1 ; EEPROM Data Register bit 1 |
.equ EEDR2 = 2 ; EEPROM Data Register bit 2 |
.equ EEDR3 = 3 ; EEPROM Data Register bit 3 |
.equ EEDR4 = 4 ; EEPROM Data Register bit 4 |
.equ EEDR5 = 5 ; EEPROM Data Register bit 5 |
.equ EEDR6 = 6 ; EEPROM Data Register bit 6 |
.equ EEDR7 = 7 ; EEPROM Data Register bit 7 |
; EECR - EEPROM Control Register |
.equ EERE = 0 ; EEPROM Read Enable |
.equ EEWE = 1 ; EEPROM Write Enable |
.equ EEPE = EEWE ; For compatibility |
.equ EEMWE = 2 ; EEPROM Master Write Enable |
.equ EEMPE = EEMWE ; For compatibility |
.equ EERIE = 3 ; EEProm Ready Interrupt Enable |
.equ EEPM0 = 4 ; |
.equ EEPM1 = 5 ; |
; ***** CPU ************************** |
; SREG - Status Register |
.equ SREG_C = 0 ; Carry Flag |
.equ SREG_Z = 1 ; Zero Flag |
.equ SREG_N = 2 ; Negative Flag |
.equ SREG_V = 3 ; Two's Complement Overflow Flag |
.equ SREG_S = 4 ; Sign Bit |
.equ SREG_H = 5 ; Half Carry Flag |
.equ SREG_T = 6 ; Bit Copy Storage |
.equ SREG_I = 7 ; Global Interrupt Enable |
; SPL - Stack Pointer Low Byte |
.equ SP0 = 0 ; Stack Pointer Bit 0 |
.equ SP1 = 1 ; Stack Pointer Bit 1 |
.equ SP2 = 2 ; Stack Pointer Bit 2 |
.equ SP3 = 3 ; Stack Pointer Bit 3 |
.equ SP4 = 4 |
.equ SP5 = 5 ; Stack Pointer Bit 5 |
.equ SP6 = 6 ; Stack Pointer Bit 6 |
.equ SP7 = 7 ; Stack Pointer Bit 7 |
; MCUCR - MCU Control Register |
.equ ISC00 = 0 ; Interrupt Sense Control 0 bit 0 |
.equ ISC01 = 1 ; Interrupt Sense Control 0 bit 1 |
.equ SM0 = 3 ; Sleep Mode Select Bit 0 |
.equ SM1 = 4 ; Sleep Mode Select Bit 1 |
.equ SE = 5 ; Sleep Enable |
.equ PUD = 6 ; Pull-up Disable |
; MCUSR - MCU Status register |
.equ PORF = 0 ; Power-On Reset Flag |
.equ EXTRF = 1 ; External Reset Flag |
.equ BORF = 2 ; Brown-out Reset Flag |
.equ WDRF = 3 ; Watchdog Reset Flag |
; OSCCAL - Oscillator Calibration Register |
.equ CAL0 = 0 ; Oscillatro Calibration Value Bit 0 |
.equ CAL1 = 1 ; Oscillatro Calibration Value Bit 1 |
.equ CAL2 = 2 ; Oscillatro Calibration Value Bit 2 |
.equ CAL3 = 3 ; Oscillatro Calibration Value Bit 3 |
.equ CAL4 = 4 ; Oscillatro Calibration Value Bit 4 |
.equ CAL5 = 5 ; Oscillatro Calibration Value Bit 5 |
.equ CAL6 = 6 ; Oscillatro Calibration Value Bit 6 |
; CLKPR - Clock Prescale Register |
.equ CLKPS0 = 0 ; Clock Prescaler Select Bit 0 |
.equ CLKPS1 = 1 ; Clock Prescaler Select Bit 1 |
.equ CLKPS2 = 2 ; Clock Prescaler Select Bit 2 |
.equ CLKPS3 = 3 ; Clock Prescaler Select Bit 3 |
.equ CLKPCE = 7 ; Clock Prescaler Change Enable |
; DWDR - Debug Wire Data Register |
.equ DWDR0 = 0 ; Debug Wire Data Register Bit 0 |
.equ DWDR1 = 1 ; Debug Wire Data Register Bit 1 |
.equ DWDR2 = 2 ; Debug Wire Data Register Bit 2 |
.equ DWDR3 = 3 ; Debug Wire Data Register Bit 3 |
.equ DWDR4 = 4 ; Debug Wire Data Register Bit 4 |
.equ DWDR5 = 5 ; Debug Wire Data Register Bit 5 |
.equ DWDR6 = 6 ; Debug Wire Data Register Bit 6 |
.equ DWDR7 = 7 ; Debug Wire Data Register Bit 7 |
; SPMCSR - Store Program Memory Control and Status Register |
.equ SPMEN = 0 ; Store program Memory Enable |
.equ PGERS = 1 ; Page Erase |
.equ PGWRT = 2 ; Page Write |
.equ RFLB = 3 ; Read Fuse and Lock Bits |
.equ CTPB = 4 ; Clear Temporary Page Buffer |
; ***** PORTB ************************ |
; PORTB - Data Register, Port B |
.equ PORTB0 = 0 ; |
.equ PB0 = 0 ; For compatibility |
.equ PORTB1 = 1 ; |
.equ PB1 = 1 ; For compatibility |
.equ PORTB2 = 2 ; |
.equ PB2 = 2 ; For compatibility |
.equ PORTB3 = 3 ; |
.equ PB3 = 3 ; For compatibility |
.equ PORTB4 = 4 ; |
.equ PB4 = 4 ; For compatibility |
.equ PORTB5 = 5 ; |
.equ PB5 = 5 ; For compatibility |
; DDRB - Data Direction Register, Port B |
.equ DDB0 = 0 ; |
.equ DDB1 = 1 ; |
.equ DDB2 = 2 ; |
.equ DDB3 = 3 ; |
.equ DDB4 = 4 ; |
.equ DDB5 = 5 ; |
; PINB - Input Pins, Port B |
.equ PINB0 = 0 ; |
.equ PINB1 = 1 ; |
.equ PINB2 = 2 ; |
.equ PINB3 = 3 ; |
.equ PINB4 = 4 ; |
.equ PINB5 = 5 ; |
; ***** EXTERNAL_INTERRUPT *********** |
; MCUCR - MCU Control Register |
;.equ ISC00 = 0 ; Interrupt Sense Control 0 Bit 0 |
;.equ ISC01 = 1 ; Interrupt Sense Control 0 Bit 1 |
; GIMSK - General Interrupt Mask Register |
.equ GICR = GIMSK ; For compatibility |
.equ PCIE = 5 ; Pin Change Interrupt Enable |
.equ INT0 = 6 ; External Interrupt Request 0 Enable |
; GIFR - General Interrupt Flag register |
.equ PCIF = 5 ; Pin Change Interrupt Flag |
.equ INTF0 = 6 ; External Interrupt Flag 0 |
; PCMSK - Pin Change Enable Mask |
.equ PCINT0 = 0 ; Pin Change Enable Mask Bit 0 |
.equ PCINT1 = 1 ; Pin Change Enable Mask Bit 1 |
.equ PCINT2 = 2 ; Pin Change Enable Mask Bit 2 |
.equ PCINT3 = 3 ; Pin Change Enable Mask Bit 3 |
.equ PCINT4 = 4 ; Pin Change Enable Mask Bit 4 |
.equ PCINT5 = 5 ; Pin Change Enable Mask Bit 5 |
; ***** TIMER_COUNTER_0 ************** |
; TIMSK0 - Timer/Counter0 Interrupt Mask Register |
.equ TOIE0 = 1 ; Timer/Counter0 Overflow Interrupt Enable |
.equ OCIE0A = 2 ; Timer/Counter0 Output Compare Match A Interrupt Enable |
.equ OCIE0B = 3 ; Timer/Counter0 Output Compare Match B Interrupt Enable |
; TIFR0 - Timer/Counter0 Interrupt Flag register |
.equ TOV0 = 1 ; Timer/Counter0 Overflow Flag |
.equ OCF0A = 2 ; Timer/Counter0 Output Compare Flag 0A |
.equ OCF0B = 3 ; Timer/Counter0 Output Compare Flag 0B |
; OCR0A - Timer/Counter0 Output Compare Register |
.equ OCR0_0 = 0 ; |
.equ OCR0_1 = 1 ; |
.equ OCR0_2 = 2 ; |
.equ OCR0_3 = 3 ; |
.equ OCR0_4 = 4 ; |
.equ OCR0_5 = 5 ; |
.equ OCR0_6 = 6 ; |
.equ OCR0_7 = 7 ; |
; TCCR0A - Timer/Counter Control Register A |
.equ WGM00 = 0 ; Waveform Generation Mode |
.equ WGM01 = 1 ; Waveform Generation Mode |
.equ COM0B0 = 4 ; Compare Match Output B Mode |
.equ COM0B1 = 5 ; Compare Match Output B Mode |
.equ COM0A0 = 6 ; Compare Match Output A Mode |
.equ COM0A1 = 7 ; Compare Match Output A Mode |
; TCNT0 - Timer/Counter0 |
.equ TCNT0_0 = 0 ; |
.equ TCNT0_1 = 1 ; |
.equ TCNT0_2 = 2 ; |
.equ TCNT0_3 = 3 ; |
.equ TCNT0_4 = 4 ; |
.equ TCNT0_5 = 5 ; |
.equ TCNT0_6 = 6 ; |
.equ TCNT0_7 = 7 ; |
; TCCR0B - Timer/Counter Control Register B |
.equ CS00 = 0 ; Clock Select |
.equ CS01 = 1 ; Clock Select |
.equ CS02 = 2 ; Clock Select |
.equ WGM02 = 3 ; Waveform Generation Mode |
.equ FOC0B = 6 ; Force Output Compare B |
.equ FOC0A = 7 ; Force Output Compare A |
; OCR0B - Timer/Counter0 Output Compare Register |
;.equ OCR0_0 = 0 ; |
;.equ OCR0_1 = 1 ; |
;.equ OCR0_2 = 2 ; |
;.equ OCR0_3 = 3 ; |
;.equ OCR0_4 = 4 ; |
;.equ OCR0_5 = 5 ; |
;.equ OCR0_6 = 6 ; |
;.equ OCR0_7 = 7 ; |
; GTCCR - General Timer Conuter Register |
.equ PSR10 = 0 ; Prescaler Reset Timer/Counter0 |
.equ TSM = 7 ; Timer/Counter Synchronization Mode |
; ***** WATCHDOG ********************* |
; WDTCR - Watchdog Timer Control Register |
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 |
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 |
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 |
.equ WDE = 3 ; Watch Dog Enable |
.equ WDCE = 4 ; Watchdog Change Enable |
.equ WDP3 = 5 ; Watchdog Timer Prescaler Bit 3 |
.equ WDTIE = 6 ; Watchdog Timeout Interrupt Enable |
.equ WDTIF = 7 ; Watchdog Timeout Interrupt Flag |
; ***** LOCKSBITS ******************************************************** |
.equ LB1 = 0 ; Lockbit |
.equ LB2 = 1 ; Lockbit |
; ***** FUSES ************************************************************ |
; LOW fuse bits |
.equ CKSEL0 = 0 ; Select Clock Source |
.equ CKSEL1 = 1 ; Select Clock Source |
.equ SUT0 = 2 ; Select start-up time |
.equ SUT1 = 3 ; Select start-up time |
.equ CKDIV8 = 4 ; Start up with system clock divided by 8 |
.equ WDTON = 5 ; Watch dog timer always on |
.equ EESAVE = 6 ; Keep EEprom contents during chip erase |
.equ SPIEN = 7 ; SPI programming enable |
; HIGH fuse bits |
.equ RSTDISBL = 0 ; Disable external reset |
.equ BODLEVEL0 = 1 ; Enable BOD and select level |
.equ BODLEVEL1 = 2 ; Enable BOD and select level |
.equ DWEN = 3 ; DebugWire Enable |
.equ SELFPRGEN = 4 ; Self Programming Enable |
; ***** CPU REGISTER DEFINITIONS ***************************************** |
.def XH = r27 |
.def XL = r26 |
.def YH = r29 |
.def YL = r28 |
.def ZH = r31 |
.def ZL = r30 |
; ***** DATA MEMORY DECLARATIONS ***************************************** |
.equ FLASHEND = 0x01ff ; Note: Word address |
.equ IOEND = 0x003f |
.equ SRAM_START = 0x0060 |
.equ SRAM_SIZE = 64 |
.equ RAMEND = 0x009f |
.equ XRAMEND = 0x0000 |
.equ E2END = 0x003f |
.equ EEPROMEND = 0x003f |
.equ EEADRBITS = 6 |
#pragma AVRPART MEMORY PROG_FLASH 1024 |
#pragma AVRPART MEMORY EEPROM 64 |
#pragma AVRPART MEMORY INT_SRAM SIZE 64 |
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60 |
; ***** BOOTLOADER DECLARATIONS ****************************************** |
.equ PAGESIZE = 16 |
; ***** INTERRUPT VECTORS ************************************************ |
.equ INT0addr = 0x0001 ; External Interrupt 0 |
.equ PCI0addr = 0x0002 ; External Interrupt Request 0 |
.equ OVF0addr = 0x0003 ; Timer/Counter0 Overflow |
.equ ERDYaddr = 0x0004 ; EEPROM Ready |
.equ ACIaddr = 0x0005 ; Analog Comparator |
.equ OC0Aaddr = 0x0006 ; Timer/Counter Compare Match A |
.equ OC0Baddr = 0x0007 ; Timer/Counter Compare Match B |
.equ WDTaddr = 0x0008 ; Watchdog Time-out |
.equ ADCCaddr = 0x0009 ; ADC Conversion Complete |
.equ INT_VECTORS_SIZE = 10 ; size in words |
#endif /* _TN13DEF_INC_ */ |
; ***** END OF FILE ****************************************************** |
/contrib/toolchain/avra/includes/tn15def.inc |
---|
0,0 → 1,388 |
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** |
;***** Created: 2005-01-11 10:31 ******* Source: ATtiny15.xml ************ |
;************************************************************************* |
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y |
;* |
;* Number : AVR000 |
;* File Name : "tn15def.inc" |
;* Title : Register/Bit Definitions for the ATtiny15 |
;* Date : 2005-01-11 |
;* Version : 2.14 |
;* Support E-mail : avr@atmel.com |
;* Target MCU : ATtiny15 |
;* |
;* DESCRIPTION |
;* When including this file in the assembly program file, all I/O register |
;* names and I/O register bit names appearing in the data book can be used. |
;* In addition, the six registers forming the three data pointers X, Y and |
;* Z have been assigned names XL - ZH. Highest RAM address for Internal |
;* SRAM is also defined |
;* |
;* The Register names are represented by their hexadecimal address. |
;* |
;* The Register Bit names are represented by their bit number (0-7). |
;* |
;* Please observe the difference in using the bit names with instructions |
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" |
;* (skip if bit in register set/cleared). The following example illustrates |
;* this: |
;* |
;* in r16,PORTB ;read PORTB latch |
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) |
;* out PORTB,r16 ;output to PORTB |
;* |
;* in r16,TIFR ;read the Timer Interrupt Flag Register |
;* sbrc r16,TOV0 ;test the overflow flag (use bit#) |
;* rjmp TOV0_is_set ;jump if set |
;* ... ;otherwise do something else |
;************************************************************************* |
#ifndef _TN15DEF_INC_ |
#define _TN15DEF_INC_ |
#pragma partinc 0 |
; ***** SPECIFY DEVICE *************************************************** |
.device ATtiny15 |
#pragma AVRPART ADMIN PART_NAME ATtiny15 |
.equ SIGNATURE_000 = 0x1e |
.equ SIGNATURE_001 = 0x90 |
.equ SIGNATURE_002 = 0x06 |
#pragma AVRPART CORE CORE_VERSION V0E |
; ***** I/O REGISTER DEFINITIONS ***************************************** |
; NOTE: |
; Definitions marked "MEMORY MAPPED"are extended I/O ports |
; and cannot be used with IN/OUT instructions |
.equ SREG = 0x3f |
.equ GIMSK = 0x3b |
.equ GIFR = 0x3a |
.equ TIMSK = 0x39 |
.equ TIFR = 0x38 |
.equ MCUCR = 0x35 |
.equ MCUSR = 0x34 |
.equ TCCR0 = 0x33 |
.equ TCNT0 = 0x32 |
.equ OSCCAL = 0x31 |
.equ TCCR1 = 0x30 |
.equ TCNT1 = 0x2f |
.equ OCR1A = 0x2e |
.equ OCR1B = 0x2d |
.equ SFIOR = 0x2c |
.equ WDTCR = 0x21 |
.equ EEAR = 0x1e |
.equ EEDR = 0x1d |
.equ EECR = 0x1c |
.equ PORTB = 0x18 |
.equ DDRB = 0x17 |
.equ PINB = 0x16 |
.equ ACSR = 0x08 |
.equ ADMUX = 0x07 |
.equ ADCSR = 0x06 |
.equ ADCH = 0x05 |
.equ ADCL = 0x04 |
; ***** BIT DEFINITIONS ************************************************** |
; ***** AD_CONVERTER ***************** |
; ADMUX - The ADC multiplexer Selection Register |
.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits |
.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits |
.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits |
.equ ADLAR = 5 ; Left Adjust Result |
.equ REFS0 = 6 ; Reference Selection Bit 0 |
.equ REFS1 = 7 ; Reference Selection Bit 1 |
; ADCSR - The ADC Control and Status register |
.equ ADPS0 = 0 ; ADC Prescaler Select Bits |
.equ ADPS1 = 1 ; ADC Prescaler Select Bits |
.equ ADPS2 = 2 ; ADC Prescaler Select Bits |
.equ ADIE = 3 ; ADC Interrupt Enable |
.equ ADIF = 4 ; ADC Interrupt Flag |
.equ ADFR = 5 ; ADC Free Running Select |
.equ ADSC = 6 ; ADC Start Conversion |
.equ ADEN = 7 ; ADC Enable |
; ADCH - ADC Data Register High Byte |
.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0 |
.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1 |
.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2 |
.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3 |
.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4 |
.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5 |
.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6 |
.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7 |
; ADCL - ADC Data Register Low Byte |
.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0 |
.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1 |
.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2 |
.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3 |
.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4 |
.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5 |
.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6 |
.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7 |
; ***** ANALOG_COMPARATOR ************ |
; ACSR - Analog Comparator Control And Status Register |
.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 |
.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 |
.equ ACIE = 3 ; Analog Comparator Interrupt Enable |
.equ ACI = 4 ; Analog Comparator Interrupt Flag |
.equ ACO = 5 ; Analog Compare Output |
.equ ACBG = 6 ; Analog Comparator Bandgap Select |
.equ AINBG6 = ACBG ; For compatibility |
.equ ACD = 7 ; Analog Comparator Disable |
; ***** EEPROM *********************** |
; EEAR - EEPROM Read/Write Access |
.equ EEAR0 = 0 ; EEPROM Read/Write Access bit 0 |
.equ EEAR1 = 1 ; EEPROM Read/Write Access bit 1 |
.equ EEAR2 = 2 ; EEPROM Read/Write Access bit 2 |
.equ EEAR3 = 3 ; EEPROM Read/Write Access bit 3 |
.equ EEAR4 = 4 ; EEPROM Read/Write Access bit 4 |
.equ EEAR5 = 5 ; EEPROM Read/Write Access bit 5 |
; EEDR - EEPROM Data Register |
.equ EEDR0 = 0 ; EEPROM Data Register bit 0 |
.equ EEDR1 = 1 ; EEPROM Data Register bit 1 |
.equ EEDR2 = 2 ; EEPROM Data Register bit 2 |
.equ EEDR3 = 3 ; EEPROM Data Register bit 3 |
.equ EEDR4 = 4 ; EEPROM Data Register bit 4 |
.equ EEDR5 = 5 ; EEPROM Data Register bit 5 |
.equ EEDR6 = 6 ; EEPROM Data Register bit 6 |
.equ EEDR7 = 7 ; EEPROM Data Register bit 7 |
; EECR - EEPROM Control Register |
.equ EERE = 0 ; EEPROM Read Enable |
.equ EEWE = 1 ; EEPROM Write Enable |
.equ EEMWE = 2 ; EEPROM Master Write Enable |
.equ EERIE = 3 ; EEProm Ready Interrupt Enable |
; ***** PORTB ************************ |
; PORTB - Data Register, Port B |
.equ PORTB0 = 0 ; |
.equ PB0 = 0 ; For compatibility |
.equ PORTB1 = 1 ; |
.equ PB1 = 1 ; For compatibility |
.equ PORTB2 = 2 ; |
.equ PB2 = 2 ; For compatibility |
.equ PORTB3 = 3 ; |
.equ PB3 = 3 ; For compatibility |
.equ PORTB4 = 4 ; |
.equ PB4 = 4 ; For compatibility |
; DDRB - Data Direction Register, Port B |
.equ DDB0 = 0 ; |
.equ DDB1 = 1 ; |
.equ DDB2 = 2 ; |
.equ DDB3 = 3 ; |
.equ DDB4 = 4 ; |
.equ DDB5 = 5 ; |
; PINB - Input Pins, Port B |
.equ PINB0 = 0 ; |
.equ PINB1 = 1 ; |
.equ PINB2 = 2 ; |
.equ PINB3 = 3 ; |
.equ PINB4 = 4 ; |
.equ PINB5 = 5 ; |
; ***** TIMER_COUNTER_0 ************** |
; TIMSK - Timer/Counter Interrupt Mask Register |
.equ TOIE0 = 1 ; Timer/Counter0 Overflow Interrupt Enable |
; TIFR - Timer/Counter Interrupt Flag register |
.equ TOV0 = 1 ; Timer/Counter0 Overflow Flag |
; TCCR0 - Timer/Counter0 Control Register |
.equ CS00 = 0 ; Clock Select0 bit 0 |
.equ CS01 = 1 ; Clock Select0 bit 1 |
.equ CS02 = 2 ; Clock Select0 bit 2 |
; TCNT0 - Timer Counter 0 |
.equ TCNT00 = 0 ; Timer Counter 0 bit 0 |
.equ TCNT01 = 1 ; Timer Counter 0 bit 1 |
.equ TCNT02 = 2 ; Timer Counter 0 bit 2 |
.equ TCNT03 = 3 ; Timer Counter 0 bit 3 |
.equ TCNT04 = 4 ; Timer Counter 0 bit 4 |
.equ TCNT05 = 5 ; Timer Counter 0 bit 5 |
.equ TCNT06 = 6 ; Timer Counter 0 bit 6 |
.equ TCNT07 = 7 ; Timer Counter 0 bit 7 |
; ***** WATCHDOG ********************* |
; WDTCR - Watchdog Timer Control Register |
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 |
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 |
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 |
.equ WDE = 3 ; Watch Dog Enable |
.equ WDTOE = 4 ; RW |
.equ WDDE = WDTOE ; For compatibility |
; ***** CPU ************************** |
; SREG - Status Register |
.equ SREG_C = 0 ; Carry Flag |
.equ SREG_Z = 1 ; Zero Flag |
.equ SREG_N = 2 ; Negative Flag |
.equ SREG_V = 3 ; Two's Complement Overflow Flag |
.equ SREG_S = 4 ; Sign Bit |
.equ SREG_H = 5 ; Half Carry Flag |
.equ SREG_T = 6 ; Bit Copy Storage |
.equ SREG_I = 7 ; Global Interrupt Enable |
; MCUCR - MCU Control Register |
.equ ISC00 = 0 ; Interrupt Sense Control 0 bit 0 |
.equ ISC01 = 1 ; Interrupt Sense Control 0 bit 1 |
.equ SM0 = 3 ; Sleep Mode Select Bit 0 |
.equ SM1 = 4 ; Sleep Mode Select Bit 1 |
.equ SE = 5 ; Sleep Enable |
.equ PUD = 6 ; Pull-up Disable |
; MCUSR - MCU Status register |
.equ PORF = 0 ; Power-On Reset Flag |
.equ EXTRF = 1 ; External Reset Flag |
.equ BORF = 2 ; Brown-out Reset Flag |
.equ WDRF = 3 ; Watchdog Reset Flag |
; OSCCAL - Status Register |
.equ CAL0 = 0 ; Oscillator Calibration Value Bit 0 |
.equ CAL1 = 1 ; Oscillator Calibration Value Bit 1 |
.equ CAL2 = 2 ; Oscillator Calibration Value Bit 2 |
.equ CAL3 = 3 ; Oscillator Calibration Value Bit 3 |
.equ CAL4 = 4 |
.equ CAL5 = 5 ; Oscillator Calibration Value Bit 5 |
.equ CAL6 = 6 ; Oscillator Calibration Value Bit 6 |
.equ CAL7 = 7 ; Oscillator Calibration Value Bit 7 |
; ***** EXTERNAL_INTERRUPT *********** |
; GIMSK - General Interrupt Mask Register |
.equ PCIE = 5 ; Pin Change Interrupt Enable |
.equ INT0 = 6 ; External Interrupt Request 0 Enable |
; GIFR - General Interrupt Flag register |
.equ PCIF = 5 ; Pin Change Interrupt Flag |
.equ INTF0 = 6 ; External Interrupt Flag 0 |
; ***** TIMER_COUNTER_1 ************** |
; TCCR1 - Timer/Counter Control Register |
.equ CS10 = 0 ; Clock Select Bits |
.equ CS11 = 1 ; Clock Select Bits |
.equ CS12 = 2 ; Clock Select Bits |
.equ CS13 = 3 ; Clock Select Bits |
.equ COM1A0 = 4 ; Compare Output Mode, Bit 1 |
.equ COM1A1 = 5 ; Compare Output Mode, Bit 0 |
.equ PWM1 = 6 ; Pulse Width Modulator Enable |
.equ CTC1 = 7 ; Clear Timer/Counter on Compare Match |
; TCNT1 - Timer/Counter Register |
.equ TCNT1_0 = 0 ; Timer/Counter Register Bit 0 |
.equ TCNT1_1 = 1 ; Timer/Counter Register Bit 1 |
.equ TCNT1_2 = 2 ; Timer/Counter Register Bit 2 |
.equ TCNT1_3 = 3 ; Timer/Counter Register Bit 3 |
.equ TCNT1_4 = 4 ; Timer/Counter Register Bit 4 |
.equ TCNT1_5 = 5 ; Timer/Counter Register Bit 5 |
.equ TCNT1_6 = 6 ; Timer/Counter Register Bit 6 |
.equ TCNT1_7 = 7 ; Timer/Counter Register Bit 7 |
; OCR1A - Output Compare Register |
.equ OCR1A0 = 0 ; Output Compare Register A Bit 0 |
.equ OCR1A1 = 1 ; Output Compare Register A Bit 1 |
.equ OCR1A2 = 2 ; Output Compare Register A Bit 2 |
.equ OCR1A3 = 3 ; Output Compare Register A Bit 3 |
.equ OCR1A4 = 4 ; Output Compare Register A Bit 4 |
.equ OCR1A5 = 5 ; Output Compare Register A Bit 5 |
.equ OCR1A6 = 6 ; Output Compare Register A Bit 6 |
.equ OCR1A7 = 7 ; Output Compare Register A Bit 7 |
; OCR1B - Output Compare Register |
.equ OCR1B0 = 0 ; Output Compare Register B Bit 0 |
.equ OCR1B1 = 1 ; Output Compare Register B Bit 1 |
.equ OCR1B2 = 2 ; Output Compare Register B Bit 2 |
.equ OCR1B3 = 3 ; Output Compare Register B Bit 3 |
.equ OCR1B4 = 4 ; Output Compare Register B Bit 4 |
.equ OCR1B5 = 5 ; Output Compare Register B Bit 5 |
.equ OCR1B6 = 6 ; Output Compare Register B Bit 6 |
.equ OCR1B7 = 7 ; Output Compare Register B Bit 7 |
; TIMSK - Timer/Counter Interrupt Mask Register |
.equ TOIE1 = 2 ; Timer/Counter1 Overflow Interrupt Enable |
.equ OCIE1A = 6 ; OCIE1A: Timer/Counter1 Output Compare Interrupt Enable |
; TIFR - Timer/Counter Interrupt Flag Register |
.equ TOV1 = 2 ; Timer/Counter1 Overflow Flag |
.equ OCF1A = 6 ; Timer/Counter1 Output Compare Flag 1A |
; SFIOR - Special Function IO Register |
.equ PSR0 = 0 ; Prescaler Reset Timer/Counter0 |
.equ PSR1 = 1 ; Prescaler Reset Timer/Counter1 |
.equ FOC1A = 2 ; Force Output Compare 1A |
; ***** LOCKSBITS ******************************************************** |
.equ LB1 = 0 ; Lockbit |
.equ LB2 = 1 ; Lockbit |
; ***** FUSES ************************************************************ |
; LOW fuse bits |
; ***** CPU REGISTER DEFINITIONS ***************************************** |
.def XH = r27 |
.def XL = r26 |
.def YH = r29 |
.def YL = r28 |
.def ZH = r31 |
.def ZL = r30 |
; ***** DATA MEMORY DECLARATIONS ***************************************** |
.equ FLASHEND = 0x01ff ; Note: Word address |
.equ IOEND = 0x003f |
.equ SRAM_SIZE = 0 |
.equ RAMEND = 0x0000 |
.equ XRAMEND = 0x0000 |
.equ E2END = 0x003f |
.equ EEPROMEND = 0x003f |
.equ EEADRBITS = 6 |
#pragma AVRPART MEMORY PROG_FLASH 1024 |
#pragma AVRPART MEMORY EEPROM 64 |
#pragma AVRPART MEMORY INT_SRAM SIZE 0 |
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x0 |
; ***** INTERRUPT VECTORS ************************************************ |
.equ INT0addr = 0x0001 ; External Interrupt 0 |
.equ PCI0addr = 0x0002 ; External Interrupt Request 0 |
.equ OC1addr = 0x0003 ; Timer/Counter1 Compare Match |
.equ OVF1addr = 0x0004 ; Timer/Counter1 Overflow |
.equ OVF0addr = 0x0005 ; Timer/Counter0 Overflow |
.equ ERDYaddr = 0x0006 ; EEPROM Ready |
.equ ACIaddr = 0x0007 ; Analog Comparator |
.equ ADCCaddr = 0x0008 ; ADC Conversion Ready |
.equ INT_VECTORS_SIZE = 9 ; size in words |
#pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED break |
#endif /* _TN15DEF_INC_ */ |
; ***** END OF FILE ****************************************************** |
/contrib/toolchain/avra/includes/tn22def.inc |
---|
0,0 → 1,251 |
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** |
;***** Created: 2005-01-11 10:31 ******* Source: ATtiny22.xml ************ |
;************************************************************************* |
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y |
;* |
;* Number : AVR000 |
;* File Name : "tn22def.inc" |
;* Title : Register/Bit Definitions for the ATtiny22 |
;* Date : 2005-01-11 |
;* Version : 2.14 |
;* Support E-mail : avr@atmel.com |
;* Target MCU : ATtiny22 |
;* |
;* DESCRIPTION |
;* When including this file in the assembly program file, all I/O register |
;* names and I/O register bit names appearing in the data book can be used. |
;* In addition, the six registers forming the three data pointers X, Y and |
;* Z have been assigned names XL - ZH. Highest RAM address for Internal |
;* SRAM is also defined |
;* |
;* The Register names are represented by their hexadecimal address. |
;* |
;* The Register Bit names are represented by their bit number (0-7). |
;* |
;* Please observe the difference in using the bit names with instructions |
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" |
;* (skip if bit in register set/cleared). The following example illustrates |
;* this: |
;* |
;* in r16,PORTB ;read PORTB latch |
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) |
;* out PORTB,r16 ;output to PORTB |
;* |
;* in r16,TIFR ;read the Timer Interrupt Flag Register |
;* sbrc r16,TOV0 ;test the overflow flag (use bit#) |
;* rjmp TOV0_is_set ;jump if set |
;* ... ;otherwise do something else |
;************************************************************************* |
#ifndef _TN22DEF_INC_ |
#define _TN22DEF_INC_ |
#pragma partinc 0 |
; ***** SPECIFY DEVICE *************************************************** |
.device ATtiny22 |
#pragma AVRPART ADMIN PART_NAME ATtiny22 |
.equ SIGNATURE_000 = 0x1e |
.equ SIGNATURE_001 = 0x91 |
.equ SIGNATURE_002 = 0x06 |
#pragma AVRPART CORE CORE_VERSION V1 |
; ***** I/O REGISTER DEFINITIONS ***************************************** |
; NOTE: |
; Definitions marked "MEMORY MAPPED"are extended I/O ports |
; and cannot be used with IN/OUT instructions |
.equ SREG = 0x3f |
.equ SPL = 0x3d |
.equ GIMSK = 0x3b |
.equ GIFR = 0x3a |
.equ TIMSK = 0x39 |
.equ TIFR = 0x38 |
.equ MCUCR = 0x35 |
.equ MCUSR = 0x34 |
.equ TCCR0 = 0x33 |
.equ TCNT0 = 0x32 |
.equ WDTCR = 0x21 |
.equ EEAR = 0x1e |
.equ EEDR = 0x1d |
.equ EECR = 0x1c |
.equ PORTB = 0x18 |
.equ DDRB = 0x17 |
.equ PINB = 0x16 |
; ***** BIT DEFINITIONS ************************************************** |
; ***** CPU ************************** |
; SREG - Status Register |
.equ SREG_C = 0 ; Carry Flag |
.equ SREG_Z = 1 ; Zero Flag |
.equ SREG_N = 2 ; Negative Flag |
.equ SREG_V = 3 ; Two's Complement Overflow Flag |
.equ SREG_S = 4 ; Sign Bit |
.equ SREG_H = 5 ; Half Carry Flag |
.equ SREG_T = 6 ; Bit Copy Storage |
.equ SREG_I = 7 ; Global Interrupt Enable |
; SPL - Stack Pointer Low |
.equ SP0 = 0 ; Stack pointer bit 0 |
.equ SP1 = 1 ; Stack pointer bit 1 |
.equ SP2 = 2 ; Stack pointer bit 2 |
.equ SP3 = 3 ; Stack pointer bit 3 |
.equ SP4 = 4 |
.equ SP5 = 5 ; Stack pointer bit 5 |
.equ SP6 = 6 ; Stack pointer bit 6 |
.equ SP7 = 7 ; Stack pointer bit 7 |
; MCUCR - MCU Control Register |
.equ ISC00 = 0 ; Interrupt Sense Control 0 bit 0 |
.equ ISC01 = 1 ; Interrupt Sense Control 0 bit 1 |
.equ SM = 4 ; Sleep Mode |
.equ SE = 5 ; Sleep Enable |
; MCUSR - MCU Status register |
.equ PORF = 0 ; Power-On Reset Flag |
.equ EXTRF = 1 ; External Reset Flag |
; ***** TIMER_COUNTER_0 ************** |
; TIMSK - Timer/Counter Interrupt Mask Register |
.equ TOIE0 = 1 ; Timer/Counter0 Overflow Interrupt Enable |
; TIFR - Timer/Counter Interrupt Flag register |
.equ TOV0 = 1 ; Timer/Counter0 Overflow Flag |
; TCCR0 - Timer/Counter0 Control Register |
.equ CS00 = 0 ; Clock Select0 bit 0 |
.equ CS01 = 1 ; Clock Select0 bit 1 |
.equ CS02 = 2 ; Clock Select0 bit 2 |
; TCNT0 - Timer Counter 0 |
.equ TCNT00 = 0 ; Timer Counter 0 bit 0 |
.equ TCNT01 = 1 ; Timer Counter 0 bit 1 |
.equ TCNT02 = 2 ; Timer Counter 0 bit 2 |
.equ TCNT03 = 3 ; Timer Counter 0 bit 3 |
.equ TCNT04 = 4 ; Timer Counter 0 bit 4 |
.equ TCNT05 = 5 ; Timer Counter 0 bit 5 |
.equ TCNT06 = 6 ; Timer Counter 0 bit 6 |
.equ TCNT07 = 7 ; Timer Counter 0 bit 7 |
; ***** EEPROM *********************** |
; EEAR - EEPROM Read/Write Access |
.equ EEAR0 = 0 ; EEPROM Read/Write Access bit 0 |
.equ EEAR1 = 1 ; EEPROM Read/Write Access bit 1 |
.equ EEAR2 = 2 ; EEPROM Read/Write Access bit 2 |
.equ EEAR3 = 3 ; EEPROM Read/Write Access bit 3 |
.equ EEAR4 = 4 ; EEPROM Read/Write Access bit 4 |
.equ EEAR5 = 5 ; EEPROM Read/Write Access bit 5 |
.equ EEAR6 = 6 ; EEPROM Read/Write Access bit 6 |
.equ EEAR7 = 7 ; EEPROM Read/Write Access bit 7 |
; EEDR - EEPROM Data Register |
.equ EEDR0 = 0 ; EEPROM Data Register bit 0 |
.equ EEDR1 = 1 ; EEPROM Data Register bit 1 |
.equ EEDR2 = 2 ; EEPROM Data Register bit 2 |
.equ EEDR3 = 3 ; EEPROM Data Register bit 3 |
.equ EEDR4 = 4 ; EEPROM Data Register bit 4 |
.equ EEDR5 = 5 ; EEPROM Data Register bit 5 |
.equ EEDR6 = 6 ; EEPROM Data Register bit 6 |
.equ EEDR7 = 7 ; EEPROM Data Register bit 7 |
; EECR - EEPROM Control Register |
.equ EERE = 0 ; EEPROM Read Enable |
.equ EEWE = 1 ; EEPROM Write Enable |
.equ EEMWE = 2 ; EEPROM Master Write Enable |
; ***** WATCHDOG ********************* |
; WDTCR - Watchdog Timer Control Register |
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 |
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 |
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 |
.equ WDE = 3 ; Watch Dog Enable |
.equ WDTOE = 4 ; RW |
.equ WDDE = WDTOE ; For compatibility |
; ***** PORTB ************************ |
; PORTB - Data Register, Port B |
.equ PORTB0 = 0 ; |
.equ PB0 = 0 ; For compatibility |
.equ PORTB1 = 1 ; |
.equ PB1 = 1 ; For compatibility |
.equ PORTB2 = 2 ; |
.equ PB2 = 2 ; For compatibility |
.equ PORTB3 = 3 ; |
.equ PB3 = 3 ; For compatibility |
.equ PORTB4 = 4 ; |
.equ PB4 = 4 ; For compatibility |
; DDRB - Data Direction Register, Port B |
.equ DDB0 = 0 ; |
.equ DDB1 = 1 ; |
.equ DDB2 = 2 ; |
.equ DDB3 = 3 ; |
.equ DDB4 = 4 ; |
; PINB - Input Pins, Port B |
.equ PINB0 = 0 ; |
.equ PINB1 = 1 ; |
.equ PINB2 = 2 ; |
.equ PINB3 = 3 ; |
.equ PINB4 = 4 ; |
; ***** LOCKSBITS ******************************************************** |
.equ LB1 = 0 ; Lockbit |
.equ LB2 = 1 ; Lockbit |
; ***** FUSES ************************************************************ |
; LOW fuse bits |
; ***** CPU REGISTER DEFINITIONS ***************************************** |
.def XH = r27 |
.def XL = r26 |
.def YH = r29 |
.def YL = r28 |
.def ZH = r31 |
.def ZL = r30 |
; ***** DATA MEMORY DECLARATIONS ***************************************** |
.equ FLASHEND = 0x03ff ; Note: Word address |
.equ IOEND = 0x003f |
.equ SRAM_START = 0x0060 |
.equ SRAM_SIZE = 128 |
.equ RAMEND = 0x00df |
.equ XRAMEND = 0x0000 |
.equ E2END = 0x007f |
.equ EEPROMEND = 0x007f |
.equ EEADRBITS = 7 |
#pragma AVRPART MEMORY PROG_FLASH 2048 |
#pragma AVRPART MEMORY EEPROM 128 |
#pragma AVRPART MEMORY INT_SRAM SIZE 128 |
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60 |
; ***** INTERRUPT VECTORS ************************************************ |
.equ INT0addr = 0x0001 ; External Interrupt 0 |
.equ OVF0addr = 0x0002 ; Timer/Counter0 Overflow |
.equ INT_VECTORS_SIZE = 3 ; size in words |
#pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED break |
#endif /* _TN22DEF_INC_ */ |
; ***** END OF FILE ****************************************************** |
/contrib/toolchain/avra/includes/tn2313def.inc |
---|
0,0 → 1,660 |
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** |
;***** Created: 2005-01-11 10:31 ******* Source: ATtiny2313.xml ********** |
;************************************************************************* |
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y |
;* |
;* Number : AVR000 |
;* File Name : "tn2313def.inc" |
;* Title : Register/Bit Definitions for the ATtiny2313 |
;* Date : 2005-01-11 |
;* Version : 2.14 |
;* Support E-mail : avr@atmel.com |
;* Target MCU : ATtiny2313 |
;* |
;* DESCRIPTION |
;* When including this file in the assembly program file, all I/O register |
;* names and I/O register bit names appearing in the data book can be used. |
;* In addition, the six registers forming the three data pointers X, Y and |
;* Z have been assigned names XL - ZH. Highest RAM address for Internal |
;* SRAM is also defined |
;* |
;* The Register names are represented by their hexadecimal address. |
;* |
;* The Register Bit names are represented by their bit number (0-7). |
;* |
;* Please observe the difference in using the bit names with instructions |
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" |
;* (skip if bit in register set/cleared). The following example illustrates |
;* this: |
;* |
;* in r16,PORTB ;read PORTB latch |
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) |
;* out PORTB,r16 ;output to PORTB |
;* |
;* in r16,TIFR ;read the Timer Interrupt Flag Register |
;* sbrc r16,TOV0 ;test the overflow flag (use bit#) |
;* rjmp TOV0_is_set ;jump if set |
;* ... ;otherwise do something else |
;************************************************************************* |
#ifndef _TN2313DEF_INC_ |
#define _TN2313DEF_INC_ |
#pragma partinc 0 |
; ***** SPECIFY DEVICE *************************************************** |
.device ATtiny2313 |
#pragma AVRPART ADMIN PART_NAME ATtiny2313 |
.equ SIGNATURE_000 = 0x1e |
.equ SIGNATURE_001 = 0x91 |
.equ SIGNATURE_002 = 0x0a |
#pragma AVRPART CORE CORE_VERSION V2 |
#pragma AVRPART CORE NEW_INSTRUCTIONS lpm rd,z+ |
; ***** I/O REGISTER DEFINITIONS ***************************************** |
; NOTE: |
; Definitions marked "MEMORY MAPPED"are extended I/O ports |
; and cannot be used with IN/OUT instructions |
.equ SREG = 0x3f |
.equ SPL = 0x3d |
.equ OCR0B = 0x3c |
.equ GIMSK = 0x3b |
.equ EIFR = 0x3a |
.equ TIMSK = 0x39 |
.equ TIFR = 0x38 |
.equ SPMCSR = 0x37 |
.equ OCR0A = 0x36 |
.equ MCUCR = 0x35 |
.equ MCUSR = 0x34 |
.equ TCCR0B = 0x33 |
.equ TCNT0 = 0x32 |
.equ OSCCAL = 0x31 |
.equ TCCR0A = 0x30 |
.equ TCCR1A = 0x2f |
.equ TCCR1B = 0x2e |
.equ TCNT1H = 0x2d |
.equ TCNT1L = 0x2c |
.equ OCR1AH = 0x2b |
.equ OCR1AL = 0x2a |
.equ OCR1BH = 0x29 |
.equ OCR1BL = 0x28 |
.equ CLKPR = 0x26 |
.equ ICR1H = 0x25 |
.equ ICR1L = 0x24 |
.equ GTCCR = 0x23 |
.equ TCCR1C = 0x22 |
.equ WDTCR = 0x21 |
.equ PCMSK = 0x20 |
.equ EEAR = 0x1e |
.equ EEDR = 0x1d |
.equ EECR = 0x1c |
.equ PORTA = 0x1b |
.equ DDRA = 0x1a |
.equ PINA = 0x19 |
.equ PORTB = 0x18 |
.equ DDRB = 0x17 |
.equ PINB = 0x16 |
.equ GPIOR2 = 0x15 |
.equ GPIOR1 = 0x14 |
.equ GPIOR0 = 0x13 |
.equ PORTD = 0x12 |
.equ DDRD = 0x11 |
.equ PIND = 0x10 |
.equ USIDR = 0x0f |
.equ USISR = 0x0e |
.equ USICR = 0x0d |
.equ UDR = 0x0c |
.equ UCSRA = 0x0b |
.equ UCSRB = 0x0a |
.equ UBRRL = 0x09 |
.equ ACSR = 0x08 |
.equ UCSRC = 0x03 |
.equ UBRRH = 0x02 |
.equ DIDR = 0x01 |
; ***** BIT DEFINITIONS ************************************************** |
; ***** PORTB ************************ |
; PORTB - Port B Data Register |
.equ PORTB0 = 0 ; Port B Data Register bit 0 |
.equ PB0 = 0 ; For compatibility |
.equ PORTB1 = 1 ; Port B Data Register bit 1 |
.equ PB1 = 1 ; For compatibility |
.equ PORTB2 = 2 ; Port B Data Register bit 2 |
.equ PB2 = 2 ; For compatibility |
.equ PORTB3 = 3 ; Port B Data Register bit 3 |
.equ PB3 = 3 ; For compatibility |
.equ PORTB4 = 4 ; Port B Data Register bit 4 |
.equ PB4 = 4 ; For compatibility |
.equ PORTB5 = 5 ; Port B Data Register bit 5 |
.equ PB5 = 5 ; For compatibility |
.equ PORTB6 = 6 ; Port B Data Register bit 6 |
.equ PB6 = 6 ; For compatibility |
.equ PORTB7 = 7 ; Port B Data Register bit 7 |
.equ PB7 = 7 ; For compatibility |
; DDRB - Port B Data Direction Register |
.equ DDB0 = 0 ; Port B Data Direction Register bit 0 |
.equ DDB1 = 1 ; Port B Data Direction Register bit 1 |
.equ DDB2 = 2 ; Port B Data Direction Register bit 2 |
.equ DDB3 = 3 ; Port B Data Direction Register bit 3 |
.equ DDB4 = 4 ; Port B Data Direction Register bit 4 |
.equ DDB5 = 5 ; Port B Data Direction Register bit 5 |
.equ DDB6 = 6 ; Port B Data Direction Register bit 6 |
.equ DDB7 = 7 ; Port B Data Direction Register bit 7 |
; PINB - Port B Input Pins |
.equ PINB0 = 0 ; Port B Input Pins bit 0 |
.equ PINB1 = 1 ; Port B Input Pins bit 1 |
.equ PINB2 = 2 ; Port B Input Pins bit 2 |
.equ PINB3 = 3 ; Port B Input Pins bit 3 |
.equ PINB4 = 4 ; Port B Input Pins bit 4 |
.equ PINB5 = 5 ; Port B Input Pins bit 5 |
.equ PINB6 = 6 ; Port B Input Pins bit 6 |
.equ PINB7 = 7 ; Port B Input Pins bit 7 |
; ***** TIMER_COUNTER_0 ************** |
; TIMSK - Timer/Counter Interrupt Mask Register |
.equ OCIE0A = 0 ; Timer/Counter0 Output Compare Match A Interrupt Enable |
.equ TOIE0 = 1 ; Timer/Counter0 Overflow Interrupt Enable |
.equ OCIE0B = 2 ; Timer/Counter0 Output Compare Match B Interrupt Enable |
; TIFR - Timer/Counter Interrupt Flag register |
.equ OCF0A = 0 ; Timer/Counter0 Output Compare Flag 0A |
.equ TOV0 = 1 ; Timer/Counter0 Overflow Flag |
.equ OCF0B = 2 ; Timer/Counter0 Output Compare Flag 0B |
; OCR0B - Timer/Counter0 Output Compare Register |
.equ OCR0_0 = 0 ; |
.equ OCR0_1 = 1 ; |
.equ OCR0_2 = 2 ; |
.equ OCR0_3 = 3 ; |
.equ OCR0_4 = 4 ; |
.equ OCR0_5 = 5 ; |
.equ OCR0_6 = 6 ; |
.equ OCR0_7 = 7 ; |
; OCR0A - Timer/Counter0 Output Compare Register |
;.equ OCR0_0 = 0 ; |
;.equ OCR0_1 = 1 ; |
;.equ OCR0_2 = 2 ; |
;.equ OCR0_3 = 3 ; |
;.equ OCR0_4 = 4 ; |
;.equ OCR0_5 = 5 ; |
;.equ OCR0_6 = 6 ; |
;.equ OCR0_7 = 7 ; |
; TCCR0A - Timer/Counter Control Register A |
.equ WGM00 = 0 ; Waveform Generation Mode |
.equ WGM01 = 1 ; Waveform Generation Mode |
.equ COM0B0 = 4 ; Compare Match Output B Mode |
.equ COM0B1 = 5 ; Compare Match Output B Mode |
.equ COM0A0 = 6 ; Compare Match Output A Mode |
.equ COM0A1 = 7 ; Compare Match Output A Mode |
; TCNT0 - Timer/Counter0 |
.equ TCNT0_0 = 0 ; |
.equ TCNT0_1 = 1 ; |
.equ TCNT0_2 = 2 ; |
.equ TCNT0_3 = 3 ; |
.equ TCNT0_4 = 4 ; |
.equ TCNT0_5 = 5 ; |
.equ TCNT0_6 = 6 ; |
.equ TCNT0_7 = 7 ; |
; TCCR0B - Timer/Counter Control Register B |
.equ TCCR0 = TCCR0B ; For compatibility |
.equ CS00 = 0 ; Clock Select |
.equ CS01 = 1 ; Clock Select |
.equ CS02 = 2 ; Clock Select |
.equ WGM02 = 3 ; |
.equ FOC0B = 6 ; Force Output Compare B |
.equ FOC0A = 7 ; Force Output Compare B |
; ***** TIMER_COUNTER_1 ************** |
; TIMSK - Timer/Counter Interrupt Mask Register |
.equ ICIE1 = 3 ; Timer/Counter1 Input Capture Interrupt Enable |
.equ TICIE = ICIE1 ; For compatibility |
.equ OCIE1B = 5 ; Timer/Counter1 Output CompareB Match Interrupt Enable |
.equ OCIE1A = 6 ; Timer/Counter1 Output CompareA Match Interrupt Enable |
.equ TOIE1 = 7 ; Timer/Counter1 Overflow Interrupt Enable |
; TIFR - Timer/Counter Interrupt Flag register |
.equ ICF1 = 3 ; Input Capture Flag 1 |
.equ OCF1B = 5 ; Output Compare Flag 1B |
.equ OCF1A = 6 ; Output Compare Flag 1A |
.equ TOV1 = 7 ; Timer/Counter1 Overflow Flag |
; TCCR1A - Timer/Counter1 Control Register A |
.equ WGM10 = 0 ; Pulse Width Modulator Select Bit 0 |
.equ PWM10 = WGM10 ; For compatibility |
.equ WGM11 = 1 ; Pulse Width Modulator Select Bit 1 |
.equ PWM11 = WGM11 ; For compatibility |
.equ COM1B0 = 4 ; Comparet Ouput Mode 1B, bit 0 |
.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1 |
.equ COM1A0 = 6 ; Comparet Ouput Mode 1A, bit 0 |
.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1 |
; TCCR1B - Timer/Counter1 Control Register B |
.equ CS10 = 0 ; Clock Select bit 0 |
.equ CS11 = 1 ; Clock Select 1 bit 1 |
.equ CS12 = 2 ; Clock Select1 bit 2 |
.equ WGM12 = 3 ; Waveform Generation Mode Bit 2 |
.equ CTC1 = WGM12 ; For compatibility |
.equ WGM13 = 4 ; Waveform Generation Mode Bit 3 |
.equ ICES1 = 6 ; Input Capture 1 Edge Select |
.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler |
; TCCR1C - Timer/Counter1 Control Register C |
.equ FOC1B = 6 ; Force Output Compare for Channel B |
.equ FOC1A = 7 ; Force Output Compare for Channel A |
; ***** WATCHDOG ********************* |
; WDTCR - Watchdog Timer Control Register |
.equ WDTCSR = WDTCR ; For compatibility |
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 |
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 |
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 |
.equ WDE = 3 ; Watch Dog Enable |
.equ WDCE = 4 ; Watchdog Change Enable |
.equ WDTOE = WDCE ; For compatibility |
.equ WDP3 = 5 ; Watchdog Timer Prescaler Bit 3 |
.equ WDIE = 6 ; Watchdog Timeout Interrupt Enable |
.equ WDIF = 7 ; Watchdog Timeout Interrupt Flag |
; ***** EXTERNAL_INTERRUPT *********** |
; GIMSK - General Interrupt Mask Register |
.equ PCIE = 5 ; |
.equ INT0 = 6 ; External Interrupt Request 0 Enable |
.equ INT1 = 7 ; External Interrupt Request 1 Enable |
; EIFR - Extended Interrupt Flag Register |
.equ GIFR = EIFR ; For compatibility |
.equ PCIF = 5 ; |
.equ INTF0 = 6 ; External Interrupt Flag 0 |
.equ INTF1 = 7 ; External Interrupt Flag 1 |
; ***** USART ************************ |
; UDR - USART I/O Data Register |
.equ UDR0 = 0 ; USART I/O Data Register bit 0 |
.equ UDR1 = 1 ; USART I/O Data Register bit 1 |
.equ UDR2 = 2 ; USART I/O Data Register bit 2 |
.equ UDR3 = 3 ; USART I/O Data Register bit 3 |
.equ UDR4 = 4 ; USART I/O Data Register bit 4 |
.equ UDR5 = 5 ; USART I/O Data Register bit 5 |
.equ UDR6 = 6 ; USART I/O Data Register bit 6 |
.equ UDR7 = 7 ; USART I/O Data Register bit 7 |
; UCSRA - USART Control and Status Register A |
.equ USR = UCSRA ; For compatibility |
.equ MPCM = 0 ; Multi-processor Communication Mode |
.equ U2X = 1 ; Double the USART Transmission Speed |
.equ UPE = 2 ; USART Parity Error |
.equ PE = UPE ; For compatibility |
.equ DOR = 3 ; Data overRun |
.equ FE = 4 ; Framing Error |
.equ UDRE = 5 ; USART Data Register Empty |
.equ TXC = 6 ; USART Transmitt Complete |
.equ RXC = 7 ; USART Receive Complete |
; UCSRB - USART Control and Status Register B |
.equ UCR = UCSRB ; For compatibility |
.equ TXB8 = 0 ; Transmit Data Bit 8 |
.equ RXB8 = 1 ; Receive Data Bit 8 |
.equ UCSZ2 = 2 ; Character Size |
.equ CHR9 = UCSZ2 ; For compatibility |
.equ TXEN = 3 ; Transmitter Enable |
.equ RXEN = 4 ; Receiver Enable |
.equ UDRIE = 5 ; USART Data register Empty Interrupt Enable |
.equ TXCIE = 6 ; TX Complete Interrupt Enable |
.equ RXCIE = 7 ; RX Complete Interrupt Enable |
; UCSRC - USART Control and Status Register C |
.equ UCPOL = 0 ; Clock Polarity |
.equ UCSZ0 = 1 ; Character Size Bit 0 |
.equ UCSZ1 = 2 ; Character Size Bit 1 |
.equ USBS = 3 ; Stop Bit Select |
.equ UPM0 = 4 ; Parity Mode Bit 0 |
.equ UPM1 = 5 ; Parity Mode Bit 1 |
.equ UMSEL = 6 ; USART Mode Select |
.equ UBRR = UBRRL ; For compatibility |
; ***** ANALOG_COMPARATOR ************ |
; ACSR - Analog Comparator Control And Status Register |
.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 |
.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 |
.equ ACIC = 2 ; |
.equ ACIE = 3 ; Analog Comparator Interrupt Enable |
.equ ACI = 4 ; Analog Comparator Interrupt Flag |
.equ ACO = 5 ; Analog Compare Output |
.equ ACBG = 6 ; Analog Comparator Bandgap Select |
.equ ACD = 7 ; Analog Comparator Disable |
; DIDR - Digital Input Disable Register 1 |
.equ AIN0D = 0 ; AIN0 Digital Input Disable |
.equ AIN1D = 1 ; AIN1 Digital Input Disable |
; ***** PORTD ************************ |
; PORTD - Data Register, Port D |
.equ PORTD0 = 0 ; |
.equ PD0 = 0 ; For compatibility |
.equ PORTD1 = 1 ; |
.equ PD1 = 1 ; For compatibility |
.equ PORTD2 = 2 ; |
.equ PD2 = 2 ; For compatibility |
.equ PORTD3 = 3 ; |
.equ PD3 = 3 ; For compatibility |
.equ PORTD4 = 4 ; |
.equ PD4 = 4 ; For compatibility |
.equ PORTD5 = 5 ; |
.equ PD5 = 5 ; For compatibility |
.equ PORTD6 = 6 ; |
.equ PD6 = 6 ; For compatibility |
; DDRD |
.equ DDD0 = 0 ; |
.equ DDD1 = 1 ; |
.equ DDD2 = 2 ; |
.equ DDD3 = 3 ; |
.equ DDD4 = 4 ; |
.equ DDD5 = 5 ; |
.equ DDD6 = 6 ; |
; PIND - Input Pins, Port D |
.equ PIND0 = 0 ; |
.equ PIND1 = 1 ; |
.equ PIND2 = 2 ; |
.equ PIND3 = 3 ; |
.equ PIND4 = 4 ; |
.equ PIND5 = 5 ; |
.equ PIND6 = 6 ; |
; ***** EEPROM *********************** |
; EEAR - EEPROM Read/Write Access |
.equ EEARL = EEAR ; For compatibility |
.equ EEAR0 = 0 ; EEPROM Read/Write Access bit 0 |
.equ EEAR1 = 1 ; EEPROM Read/Write Access bit 1 |
.equ EEAR2 = 2 ; EEPROM Read/Write Access bit 2 |
.equ EEAR3 = 3 ; EEPROM Read/Write Access bit 3 |
.equ EEAR4 = 4 ; EEPROM Read/Write Access bit 4 |
.equ EEAR5 = 5 ; EEPROM Read/Write Access bit 5 |
.equ EEAR6 = 6 ; EEPROM Read/Write Access bit 6 |
; EEDR - EEPROM Data Register |
.equ EEDR0 = 0 ; EEPROM Data Register bit 0 |
.equ EEDR1 = 1 ; EEPROM Data Register bit 1 |
.equ EEDR2 = 2 ; EEPROM Data Register bit 2 |
.equ EEDR3 = 3 ; EEPROM Data Register bit 3 |
.equ EEDR4 = 4 ; EEPROM Data Register bit 4 |
.equ EEDR5 = 5 ; EEPROM Data Register bit 5 |
.equ EEDR6 = 6 ; EEPROM Data Register bit 6 |
.equ EEDR7 = 7 ; EEPROM Data Register bit 7 |
; EECR - EEPROM Control Register |
.equ EERE = 0 ; EEPROM Read Enable |
.equ EEPE = 1 ; EEPROM Write Enable |
.equ EEWE = EEPE ; For compatibility |
.equ EEMPE = 2 ; EEPROM Master Write Enable |
.equ EEMWE = EEMPE ; For compatibility |
.equ EERIE = 3 ; EEProm Ready Interrupt Enable |
.equ EEPM0 = 4 ; |
.equ EEPM1 = 5 ; |
; ***** PORTA ************************ |
; PORTA - Port A Data Register |
.equ PORTA0 = 0 ; Port A Data Register bit 0 |
.equ PA0 = 0 ; For compatibility |
.equ PORTA1 = 1 ; Port A Data Register bit 1 |
.equ PA1 = 1 ; For compatibility |
.equ PORTA2 = 2 ; Port A Data Register bit 2 |
.equ PA2 = 2 ; For compatibility |
; DDRA - Port A Data Direction Register |
.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0 |
.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1 |
.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2 |
; PINA - Port A Input Pins |
.equ PINA0 = 0 ; Input Pins, Port A bit 0 |
.equ PINA1 = 1 ; Input Pins, Port A bit 1 |
.equ PINA2 = 2 ; Input Pins, Port A bit 2 |
; ***** CPU ************************** |
; SREG - Status Register |
.equ SREG_C = 0 ; Carry Flag |
.equ SREG_Z = 1 ; Zero Flag |
.equ SREG_N = 2 ; Negative Flag |
.equ SREG_V = 3 ; Two's Complement Overflow Flag |
.equ SREG_S = 4 ; Sign Bit |
.equ SREG_H = 5 ; Half Carry Flag |
.equ SREG_T = 6 ; Bit Copy Storage |
.equ SREG_I = 7 ; Global Interrupt Enable |
; SPMCSR - Store Program Memory Control and Status register |
.equ SPMEN = 0 ; Store Program Memory Enable |
.equ PGERS = 1 ; Page Erase |
.equ PGWRT = 2 ; Page Write |
.equ RFLB = 3 ; Read Fuse and Lock Bits |
.equ CTPB = 4 |
; MCUCR - MCU Control Register |
.equ ISC00 = 0 ; Interrupt Sense Control 0 bit 0 |
.equ ISC01 = 1 ; Interrupt Sense Control 0 bit 1 |
.equ ISC10 = 2 ; Interrupt Sense Control 1 bit 0 |
.equ ISC11 = 3 ; Interrupt Sense Control 1 bit 1 |
.equ SM0 = 4 ; Sleep Mode Select Bit 0 |
.equ SM = SM0 ; For compatibility |
.equ SE = 5 ; Sleep Enable |
.equ SM1 = 6 ; Sleep Mode Select Bit 1 |
.equ PUD = 7 ; Pull-up Disable |
; CLKPR - Clock Prescale Register |
.equ CLKPS0 = 0 ; Clock Prescaler Select Bit 0 |
.equ CLKPS1 = 1 ; Clock Prescaler Select Bit 1 |
.equ CLKPS2 = 2 ; Clock Prescaler Select Bit 2 |
.equ CLKPS3 = 3 ; Clock Prescaler Select Bit 3 |
.equ CLKPCE = 7 ; Clock Prescaler Change Enable |
; MCUSR - MCU Status register |
.equ PORF = 0 ; Power-On Reset Flag |
.equ EXTRF = 1 ; External Reset Flag |
.equ BORF = 2 ; Brown-out Reset Flag |
.equ WDRF = 3 ; Watchdog Reset Flag |
; OSCCAL - Oscillator Calibration Register |
.equ CAL0 = 0 ; Oscillatro Calibration Value Bit 0 |
.equ CAL1 = 1 ; Oscillatro Calibration Value Bit 1 |
.equ CAL2 = 2 ; Oscillatro Calibration Value Bit 2 |
.equ CAL3 = 3 ; Oscillatro Calibration Value Bit 3 |
.equ CAL4 = 4 ; Oscillatro Calibration Value Bit 4 |
.equ CAL5 = 5 ; Oscillatro Calibration Value Bit 5 |
.equ CAL6 = 6 ; Oscillatro Calibration Value Bit 6 |
; GTCCR - General Timer Counter Control Register |
.equ SFIOR = GTCCR ; For compatibility |
.equ PSR10 = 0 ; |
; PCMSK - Pin-Change Mask register |
.equ PCINT0 = 0 ; Pin-Change Interrupt 0 |
.equ PCINT1 = 1 ; Pin-Change Interrupt 1 |
.equ PCINT2 = 2 ; Pin-Change Interrupt 2 |
.equ PCINT3 = 3 ; Pin-Change Interrupt 3 |
.equ PCINT4 = 4 ; Pin-Change Interrupt 4 |
.equ PCINT5 = 5 ; Pin-Change Interrupt 5 |
.equ PCINT6 = 6 ; Pin-Change Interrupt 6 |
.equ PCINT7 = 7 ; Pin-Change Interrupt 7 |
; GPIOR2 - General Purpose I/O Register 2 |
.equ GPIOR20 = 0 ; General Purpose I/O Register 2 bit 0 |
.equ GPIOR21 = 1 ; General Purpose I/O Register 2 bit 1 |
.equ GPIOR22 = 2 ; General Purpose I/O Register 2 bit 2 |
.equ GPIOR23 = 3 ; General Purpose I/O Register 2 bit 3 |
.equ GPIOR24 = 4 ; General Purpose I/O Register 2 bit 4 |
.equ GPIOR25 = 5 ; General Purpose I/O Register 2 bit 5 |
.equ GPIOR26 = 6 ; General Purpose I/O Register 2 bit 6 |
.equ GPIOR27 = 7 ; General Purpose I/O Register 2 bit 7 |
; GPIOR1 - General Purpose I/O Register 1 |
.equ GPIOR10 = 0 ; General Purpose I/O Register 1 bit 0 |
.equ GPIOR11 = 1 ; General Purpose I/O Register 1 bit 1 |
.equ GPIOR12 = 2 ; General Purpose I/O Register 1 bit 2 |
.equ GPIOR13 = 3 ; General Purpose I/O Register 1 bit 3 |
.equ GPIOR14 = 4 ; General Purpose I/O Register 1 bit 4 |
.equ GPIOR15 = 5 ; General Purpose I/O Register 1 bit 5 |
.equ GPIOR16 = 6 ; General Purpose I/O Register 1 bit 6 |
.equ GPIOR17 = 7 ; General Purpose I/O Register 1 bit 7 |
; GPIOR0 - General Purpose I/O Register 0 |
.equ GPIOR00 = 0 ; General Purpose I/O Register 0 bit 0 |
.equ GPIOR01 = 1 ; General Purpose I/O Register 0 bit 1 |
.equ GPIOR02 = 2 ; General Purpose I/O Register 0 bit 2 |
.equ GPIOR03 = 3 ; General Purpose I/O Register 0 bit 3 |
.equ GPIOR04 = 4 ; General Purpose I/O Register 0 bit 4 |
.equ GPIOR05 = 5 ; General Purpose I/O Register 0 bit 5 |
.equ GPIOR06 = 6 ; General Purpose I/O Register 0 bit 6 |
.equ GPIOR07 = 7 ; General Purpose I/O Register 0 bit 7 |
; ***** USI ************************** |
; USIDR - USI Data Register |
.equ USIDR0 = 0 ; USI Data Register bit 0 |
.equ USIDR1 = 1 ; USI Data Register bit 1 |
.equ USIDR2 = 2 ; USI Data Register bit 2 |
.equ USIDR3 = 3 ; USI Data Register bit 3 |
.equ USIDR4 = 4 ; USI Data Register bit 4 |
.equ USIDR5 = 5 ; USI Data Register bit 5 |
.equ USIDR6 = 6 ; USI Data Register bit 6 |
.equ USIDR7 = 7 ; USI Data Register bit 7 |
; USISR - USI Status Register |
.equ USICNT0 = 0 ; USI Counter Value Bit 0 |
.equ USICNT1 = 1 ; USI Counter Value Bit 1 |
.equ USICNT2 = 2 ; USI Counter Value Bit 2 |
.equ USICNT3 = 3 ; USI Counter Value Bit 3 |
.equ USIDC = 4 ; Data Output Collision |
.equ USIPF = 5 ; Stop Condition Flag |
.equ USIOIF = 6 ; Counter Overflow Interrupt Flag |
.equ USISIF = 7 ; Start Condition Interrupt Flag |
; USICR - USI Control Register |
.equ USITC = 0 ; Toggle Clock Port Pin |
.equ USICLK = 1 ; Clock Strobe |
.equ USICS0 = 2 ; USI Clock Source Select Bit 0 |
.equ USICS1 = 3 ; USI Clock Source Select Bit 1 |
.equ USIWM0 = 4 ; USI Wire Mode Bit 0 |
.equ USIWM1 = 5 ; USI Wire Mode Bit 1 |
.equ USIOIE = 6 ; Counter Overflow Interrupt Enable |
.equ USISIE = 7 ; Start Condition Interrupt Enable |
; ***** LOCKSBITS ******************************************************** |
.equ LB1 = 0 ; Lockbit |
.equ LB2 = 1 ; Lockbit |
; ***** FUSES ************************************************************ |
; LOW fuse bits |
.equ CKSEL0 = 0 ; Select Clock Source |
.equ CKSEL1 = 1 ; Select Clock Source |
.equ CKSEL2 = 2 ; Select Clock Source |
.equ CKSEL3 = 3 ; Select Clock Source |
.equ SUT0 = 4 ; Select start-up time |
.equ SUT1 = 5 ; Select start-up time |
.equ CKOUT = 6 ; Clock output |
.equ CKDIV8 = 7 ; Divide clock by 8 |
; HIGH fuse bits |
.equ BODLEVEL0 = 0 ; Brown-out Detector trigger level |
.equ BODLEVEL1 = 1 ; Brown-out Detector trigger level |
.equ BODLEVEL2 = 2 ; Brown-out Detector trigger level |
.equ EESAVE = 3 ; EEPROM memory is preserved through chip erase |
.equ WDTON = 4 ; Watchdog Timer Always On |
.equ SPIEN = 5 ; Enable Serial programming and Data Downloading |
.equ DWEN = 6 ; debugWIRE Enable |
.equ RSTDISBL = 7 ; External reset disable |
; EXTENDED fuse bits |
.equ SELFPRGEN = 0 ; Self Programming Enable |
; ***** CPU REGISTER DEFINITIONS ***************************************** |
.def XH = r27 |
.def XL = r26 |
.def YH = r29 |
.def YL = r28 |
.def ZH = r31 |
.def ZL = r30 |
; ***** DATA MEMORY DECLARATIONS ***************************************** |
.equ FLASHEND = 0x03ff ; Note: Word address |
.equ IOEND = 0x003f |
.equ SRAM_START = 0x0060 |
.equ SRAM_SIZE = 128 |
.equ RAMEND = 0x00df |
.equ XRAMEND = 0x0000 |
.equ E2END = 0x007f |
.equ EEPROMEND = 0x007f |
.equ EEADRBITS = 7 |
#pragma AVRPART MEMORY PROG_FLASH 2048 |
#pragma AVRPART MEMORY EEPROM 128 |
#pragma AVRPART MEMORY INT_SRAM SIZE 128 |
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60 |
; ***** BOOTLOADER DECLARATIONS ****************************************** |
.equ NRWW_START_ADDR = 0x0 |
.equ NRWW_STOP_ADDR = 0x3ff |
.equ RWW_START_ADDR = 0x0 |
.equ RWW_STOP_ADDR = 0x0 |
.equ PAGESIZE = 16 |
; ***** INTERRUPT VECTORS ************************************************ |
.equ INT0addr = 0x0001 ; External Interrupt Request 0 |
.equ INT1addr = 0x0002 ; External Interrupt Request 1 |
.equ ICP1addr = 0x0003 ; Timer/Counter1 Capture Event |
.equ OC1Aaddr = 0x0004 ; Timer/Counter1 Compare Match A |
.equ OC1addr = 0x0004 ; For compatibility |
.equ OVF1addr = 0x0005 ; Timer/Counter1 Overflow |
.equ OVF0addr = 0x0006 ; Timer/Counter0 Overflow |
.equ URXCaddr = 0x0007 ; USART, Rx Complete |
.equ URXC0addr = 0x0007 ; For compatibility |
.equ UDREaddr = 0x0008 ; USART Data Register Empty |
.equ UDRE0addr = 0x0008 ; For compatibility |
.equ UTXCaddr = 0x0009 ; USART, Tx Complete |
.equ UTXC0addr = 0x0009 ; For compatibility |
.equ ACIaddr = 0x000a ; Analog Comparator |
.equ PCIaddr = 0x000b ; |
.equ OC1Baddr = 0x000c ; |
.equ OC0Aaddr = 0x000d ; |
.equ OC0Baddr = 0x000e ; |
.equ USI_STARTaddr = 0x000f ; USI Start Condition |
.equ USI_OVFaddr = 0x0010 ; USI Overflow |
.equ ERDYaddr = 0x0011 ; |
.equ WDTaddr = 0x0012 ; Watchdog Timer Overflow |
.equ INT_VECTORS_SIZE = 19 ; size in words |
#endif /* _TN2313DEF_INC_ */ |
; ***** END OF FILE ****************************************************** |
/contrib/toolchain/avra/includes/tn26def.inc |
---|
0,0 → 1,542 |
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** |
;***** Created: 2005-01-11 10:31 ******* Source: ATtiny26.xml ************ |
;************************************************************************* |
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y |
;* |
;* Number : AVR000 |
;* File Name : "tn26def.inc" |
;* Title : Register/Bit Definitions for the ATtiny26 |
;* Date : 2005-01-11 |
;* Version : 2.14 |
;* Support E-mail : avr@atmel.com |
;* Target MCU : ATtiny26 |
;* |
;* DESCRIPTION |
;* When including this file in the assembly program file, all I/O register |
;* names and I/O register bit names appearing in the data book can be used. |
;* In addition, the six registers forming the three data pointers X, Y and |
;* Z have been assigned names XL - ZH. Highest RAM address for Internal |
;* SRAM is also defined |
;* |
;* The Register names are represented by their hexadecimal address. |
;* |
;* The Register Bit names are represented by their bit number (0-7). |
;* |
;* Please observe the difference in using the bit names with instructions |
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" |
;* (skip if bit in register set/cleared). The following example illustrates |
;* this: |
;* |
;* in r16,PORTB ;read PORTB latch |
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) |
;* out PORTB,r16 ;output to PORTB |
;* |
;* in r16,TIFR ;read the Timer Interrupt Flag Register |
;* sbrc r16,TOV0 ;test the overflow flag (use bit#) |
;* rjmp TOV0_is_set ;jump if set |
;* ... ;otherwise do something else |
;************************************************************************* |
#ifndef _TN26DEF_INC_ |
#define _TN26DEF_INC_ |
#pragma partinc 0 |
; ***** SPECIFY DEVICE *************************************************** |
.device ATtiny26 |
#pragma AVRPART ADMIN PART_NAME ATtiny26 |
.equ SIGNATURE_000 = 0x1e |
.equ SIGNATURE_001 = 0x91 |
.equ SIGNATURE_002 = 0x09 |
#pragma AVRPART CORE CORE_VERSION V1 |
#pragma AVRPART CORE NEW_INSTRUCTIONS lpm rd,z |
; ***** I/O REGISTER DEFINITIONS ***************************************** |
; NOTE: |
; Definitions marked "MEMORY MAPPED"are extended I/O ports |
; and cannot be used with IN/OUT instructions |
.equ SREG = 0x3f |
.equ SP = 0x3d |
.equ GIMSK = 0x3b |
.equ GIFR = 0x3a |
.equ TIMSK = 0x39 |
.equ TIFR = 0x38 |
.equ MCUCR = 0x35 |
.equ MCUSR = 0x34 |
.equ TCCR0 = 0x33 |
.equ TCNT0 = 0x32 |
.equ OSCCAL = 0x31 |
.equ TCCR1A = 0x30 |
.equ TCCR1B = 0x2f |
.equ TCNT1 = 0x2e |
.equ OCR1A = 0x2d |
.equ OCR1B = 0x2c |
.equ OCR1C = 0x2b |
.equ PLLCSR = 0x29 |
.equ WDTCR = 0x21 |
.equ EEAR = 0x1e |
.equ EEDR = 0x1d |
.equ EECR = 0x1c |
.equ PORTA = 0x1b |
.equ DDRA = 0x1a |
.equ PINA = 0x19 |
.equ PORTB = 0x18 |
.equ DDRB = 0x17 |
.equ PINB = 0x16 |
.equ USIDR = 0x0f |
.equ USISR = 0x0e |
.equ USICR = 0x0d |
.equ ACSR = 0x08 |
.equ ADMUX = 0x07 |
.equ ADCSRA = 0x06 |
.equ ADCH = 0x05 |
.equ ADCL = 0x04 |
; ***** BIT DEFINITIONS ************************************************** |
; ***** AD_CONVERTER ***************** |
; ADMUX - The ADC multiplexer Selection Register |
.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits |
.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits |
.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits |
.equ MUX3 = 3 ; Analog Channel and Gain Selection Bits |
.equ MUX4 = 4 ; Analog Channel and Gain Selection Bits |
.equ ADLAR = 5 ; Left Adjust Result |
.equ REFS0 = 6 ; Reference Selection Bit 0 |
.equ REFS1 = 7 ; Reference Selection Bit 1 |
; ADCSRA - The ADC Control and Status register |
.equ ADCSR = ADCSRA ; For compatibility |
.equ ADPS0 = 0 ; ADC Prescaler Select Bits |
.equ ADPS1 = 1 ; ADC Prescaler Select Bits |
.equ ADPS2 = 2 ; ADC Prescaler Select Bits |
.equ ADIE = 3 ; ADC Interrupt Enable |
.equ ADIF = 4 ; ADC Interrupt Flag |
.equ ADFR = 5 ; ADC Free Running Select |
.equ ADSC = 6 ; ADC Start Conversion |
.equ ADEN = 7 ; ADC Enable |
; ADCH - ADC Data Register High Byte |
.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0 |
.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1 |
.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2 |
.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3 |
.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4 |
.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5 |
.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6 |
.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7 |
; ADCL - ADC Data Register Low Byte |
.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0 |
.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1 |
.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2 |
.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3 |
.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4 |
.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5 |
.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6 |
.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7 |
; ***** ANALOG_COMPARATOR ************ |
; ACSR - Analog Comparator Control And Status Register |
.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 |
.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 |
.equ ACME = 2 ; Analog Comparator Multiplexer Enable |
.equ ACIE = 3 ; Analog Comparator Interrupt Enable |
.equ ACI = 4 ; Analog Comparator Interrupt Flag |
.equ ACO = 5 ; Analog Compare Output |
.equ ACBG = 6 ; Analog Comparator Bandgap Select |
.equ ACD = 7 ; Analog Comparator Disable |
; ***** USI ************************** |
; USIDR - USI Data Register |
.equ USIDR0 = 0 ; USI Data Register bit 0 |
.equ USIDR1 = 1 ; USI Data Register bit 1 |
.equ USIDR2 = 2 ; USI Data Register bit 2 |
.equ USIDR3 = 3 ; USI Data Register bit 3 |
.equ USIDR4 = 4 ; USI Data Register bit 4 |
.equ USIDR5 = 5 ; USI Data Register bit 5 |
.equ USIDR6 = 6 ; USI Data Register bit 6 |
.equ USIDR7 = 7 ; USI Data Register bit 7 |
; USISR - USI Status Register |
.equ USICNT0 = 0 ; USI Counter Value Bit 0 |
.equ USICNT1 = 1 ; USI Counter Value Bit 1 |
.equ USICNT2 = 2 ; USI Counter Value Bit 2 |
.equ USICNT3 = 3 ; USI Counter Value Bit 3 |
.equ USIDC = 4 ; Data Output Collision |
.equ USIPF = 5 ; Stop Condition Flag |
.equ USIOIF = 6 ; Counter Overflow Interrupt Flag |
.equ USISIF = 7 ; Start Condition Interrupt Flag |
; USICR - USI Control Register |
.equ USITC = 0 ; Toggle Clock Port Pin |
.equ USICLK = 1 ; Clock Strobe |
.equ USICS0 = 2 ; USI Clock Source Select Bit 0 |
.equ USICS1 = 3 ; USI Clock Source Select Bit 1 |
.equ USIWM0 = 4 ; USI Wire Mode Bit 0 |
.equ USIWM1 = 5 ; USI Wire Mode Bit 1 |
.equ USIOIE = 6 ; Counter Overflow Interrupt Enable |
.equ USISIE = 7 ; Start Condition Interrupt Enable |
; ***** PORTA ************************ |
; PORTA - Port A Data Register |
.equ PORTA0 = 0 ; Port A Data Register bit 0 |
.equ PA0 = 0 ; For compatibility |
.equ PORTA1 = 1 ; Port A Data Register bit 1 |
.equ PA1 = 1 ; For compatibility |
.equ PORTA2 = 2 ; Port A Data Register bit 2 |
.equ PA2 = 2 ; For compatibility |
.equ PORTA3 = 3 ; Port A Data Register bit 3 |
.equ PA3 = 3 ; For compatibility |
.equ PORTA4 = 4 ; Port A Data Register bit 4 |
.equ PA4 = 4 ; For compatibility |
.equ PORTA5 = 5 ; Port A Data Register bit 5 |
.equ PA5 = 5 ; For compatibility |
.equ PORTA6 = 6 ; Port A Data Register bit 6 |
.equ PA6 = 6 ; For compatibility |
.equ PORTA7 = 7 ; Port A Data Register bit 7 |
.equ PA7 = 7 ; For compatibility |
; DDRA - Port A Data Direction Register |
.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0 |
.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1 |
.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2 |
.equ DDA3 = 3 ; Data Direction Register, Port A, bit 3 |
.equ DDA4 = 4 ; Data Direction Register, Port A, bit 4 |
.equ DDA5 = 5 ; Data Direction Register, Port A, bit 5 |
.equ DDA6 = 6 ; Data Direction Register, Port A, bit 6 |
.equ DDA7 = 7 ; Data Direction Register, Port A, bit 7 |
; PINA - Port A Input Pins |
.equ PINA0 = 0 ; Input Pins, Port A bit 0 |
.equ PINA1 = 1 ; Input Pins, Port A bit 1 |
.equ PINA2 = 2 ; Input Pins, Port A bit 2 |
.equ PINA3 = 3 ; Input Pins, Port A bit 3 |
.equ PINA4 = 4 ; Input Pins, Port A bit 4 |
.equ PINA5 = 5 ; Input Pins, Port A bit 5 |
.equ PINA6 = 6 ; Input Pins, Port A bit 6 |
.equ PINA7 = 7 ; Input Pins, Port A bit 7 |
; ***** PORTB ************************ |
; PORTB - Port B Data Register |
.equ PORTB0 = 0 ; Port B Data Register bit 0 |
.equ PB0 = 0 ; For compatibility |
.equ PORTB1 = 1 ; Port B Data Register bit 1 |
.equ PB1 = 1 ; For compatibility |
.equ PORTB2 = 2 ; Port B Data Register bit 2 |
.equ PB2 = 2 ; For compatibility |
.equ PORTB3 = 3 ; Port B Data Register bit 3 |
.equ PB3 = 3 ; For compatibility |
.equ PORTB4 = 4 ; Port B Data Register bit 4 |
.equ PB4 = 4 ; For compatibility |
.equ PORTB5 = 5 ; Port B Data Register bit 5 |
.equ PB5 = 5 ; For compatibility |
.equ PORTB6 = 6 ; Port B Data Register bit 6 |
.equ PB6 = 6 ; For compatibility |
.equ PORTB7 = 7 ; Port B Data Register bit 7 |
.equ PB7 = 7 ; For compatibility |
; DDRB - Port B Data Direction Register |
.equ DDB0 = 0 ; Port B Data Direction Register bit 0 |
.equ DDB1 = 1 ; Port B Data Direction Register bit 1 |
.equ DDB2 = 2 ; Port B Data Direction Register bit 2 |
.equ DDB3 = 3 ; Port B Data Direction Register bit 3 |
.equ DDB4 = 4 ; Port B Data Direction Register bit 4 |
.equ DDB5 = 5 ; Port B Data Direction Register bit 5 |
.equ DDB6 = 6 ; Port B Data Direction Register bit 6 |
.equ DDB7 = 7 ; Port B Data Direction Register bit 7 |
; PINB - Port B Input Pins |
.equ PINB0 = 0 ; Port B Input Pins bit 0 |
.equ PINB1 = 1 ; Port B Input Pins bit 1 |
.equ PINB2 = 2 ; Port B Input Pins bit 2 |
.equ PINB3 = 3 ; Port B Input Pins bit 3 |
.equ PINB4 = 4 ; Port B Input Pins bit 4 |
.equ PINB5 = 5 ; Port B Input Pins bit 5 |
.equ PINB6 = 6 ; Port B Input Pins bit 6 |
.equ PINB7 = 7 ; Port B Input Pins bit 7 |
; ***** EEPROM *********************** |
; EEAR - EEPROM Read/Write Access |
.equ EEAR0 = 0 ; EEPROM Read/Write Access bit 0 |
.equ EEAR1 = 1 ; EEPROM Read/Write Access bit 1 |
.equ EEAR2 = 2 ; EEPROM Read/Write Access bit 2 |
.equ EEAR3 = 3 ; EEPROM Read/Write Access bit 3 |
.equ EEAR4 = 4 ; EEPROM Read/Write Access bit 4 |
.equ EEAR5 = 5 ; EEPROM Read/Write Access bit 5 |
.equ EEAR6 = 6 ; EEPROM Read/Write Access bit 6 |
; EEDR - EEPROM Data Register |
.equ EEDR0 = 0 ; EEPROM Data Register bit 0 |
.equ EEDR1 = 1 ; EEPROM Data Register bit 1 |
.equ EEDR2 = 2 ; EEPROM Data Register bit 2 |
.equ EEDR3 = 3 ; EEPROM Data Register bit 3 |
.equ EEDR4 = 4 ; EEPROM Data Register bit 4 |
.equ EEDR5 = 5 ; EEPROM Data Register bit 5 |
.equ EEDR6 = 6 ; EEPROM Data Register bit 6 |
.equ EEDR7 = 7 ; EEPROM Data Register bit 7 |
; EECR - EEPROM Control Register |
.equ EERE = 0 ; EEPROM Read Enable |
.equ EEWE = 1 ; EEPROM Write Enable |
.equ EEMWE = 2 ; EEPROM Master Write Enable |
.equ EERIE = 3 ; EEProm Ready Interrupt Enable |
; ***** WATCHDOG ********************* |
; WDTCR - Watchdog Timer Control Register |
.equ WDTCSR = WDTCR ; For compatibility |
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 |
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 |
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 |
.equ WDE = 3 ; Watch Dog Enable |
.equ WDCE = 4 ; Watchdog Change Enable |
.equ WDTOE = WDCE ; For compatibility |
; ***** CPU ************************** |
; SREG - Status Register |
.equ SREG_C = 0 ; Carry Flag |
.equ SREG_Z = 1 ; Zero Flag |
.equ SREG_N = 2 ; Negative Flag |
.equ SREG_V = 3 ; Two's Complement Overflow Flag |
.equ SREG_S = 4 ; Sign Bit |
.equ SREG_H = 5 ; Half Carry Flag |
.equ SREG_T = 6 ; Bit Copy Storage |
.equ SREG_I = 7 ; Global Interrupt Enable |
; SP - Stack Pointer |
.equ SP0 = 0 ; Stack Pointer Bit 0 |
.equ SP1 = 1 ; Stack Pointer Bit 1 |
.equ SP2 = 2 ; Stack Pointer Bit 2 |
.equ SP3 = 3 ; Stack Pointer Bit 3 |
.equ SP4 = 4 |
.equ SP5 = 5 ; Stack Pointer Bit 5 |
.equ SP6 = 6 ; Stack Pointer Bit 6 |
.equ SP7 = 7 ; Stack Pointer Bit 7 |
; MCUCR - MCU Control Register |
.equ ISC00 = 0 ; Interrupt Sense Control 0 bit 0 |
.equ ISC01 = 1 ; Interrupt Sense Control 0 bit 1 |
.equ SM0 = 3 ; Sleep Mode Select Bit 0 |
.equ SM1 = 4 ; Sleep Mode Select Bit 1 |
.equ SE = 5 ; Sleep Enable |
.equ PUD = 6 ; Pull-up Disable |
; MCUSR - MCU Status register |
.equ PORF = 0 ; Power-On Reset Flag |
.equ EXTRF = 1 ; External Reset Flag |
.equ BORF = 2 ; Brown-out Reset Flag |
.equ WDRF = 3 ; Watchdog Reset Flag |
; OSCCAL - Status Register |
.equ CAL0 = 0 ; Oscillator Calibration Value Bit 0 |
.equ OSCCAL0 = CAL0 ; For compatibility |
.equ CAL1 = 1 ; Oscillator Calibration Value Bit 1 |
.equ OSCCAL1 = CAL1 ; For compatibility |
.equ CAL2 = 2 ; Oscillator Calibration Value Bit 2 |
.equ OSCCAL2 = CAL2 ; For compatibility |
.equ CAL3 = 3 ; Oscillator Calibration Value Bit 3 |
.equ OSCCAL3 = CAL3 ; For compatibility |
.equ CAL4 = 4 |
.equ OSCCAL4 = CAL4 ; For compatibility |
.equ CAL5 = 5 ; Oscillator Calibration Value Bit 5 |
.equ CAL6 = 6 ; Oscillator Calibration Value Bit 6 |
.equ CAL7 = 7 ; Oscillator Calibration Value Bit 7 |
; ***** TIMER_COUNTER_0 ************** |
; TIMSK - Timer/Counter Interrupt Mask Register |
.equ TOIE0 = 1 ; Timer/Counter0 Overflow Interrupt Enable |
; TIFR - Timer/Counter Interrupt Flag register |
.equ TOV0 = 1 ; Timer/Counter0 Overflow Flag |
; TCCR0 - Timer/Counter0 Control Register |
.equ CS00 = 0 ; Clock Select0 bit 0 |
.equ CS01 = 1 ; Clock Select0 bit 1 |
.equ CS02 = 2 ; Clock Select0 bit 2 |
.equ PSR0 = 3 ; Prescaler Reset Timer/Counter0 |
; TCNT0 - Timer Counter 0 |
.equ TCNT00 = 0 ; Timer Counter 0 bit 0 |
.equ TCNT01 = 1 ; Timer Counter 0 bit 1 |
.equ TCNT02 = 2 ; Timer Counter 0 bit 2 |
.equ TCNT03 = 3 ; Timer Counter 0 bit 3 |
.equ TCNT04 = 4 ; Timer Counter 0 bit 4 |
.equ TCNT05 = 5 ; Timer Counter 0 bit 5 |
.equ TCNT06 = 6 ; Timer Counter 0 bit 6 |
.equ TCNT07 = 7 ; Timer Counter 0 bit 7 |
; ***** TIMER_COUNTER_1 ************** |
; TCCR1A - Timer/Counter Control Register A |
.equ PWM1B = 0 ; Pulse Width Modulator B Enable |
.equ PWM1A = 1 ; Pulse Width Modulator A Enable |
.equ FOC1B = 2 ; Force Output Compare Match 1B |
.equ FOC1A = 3 ; Force Output Compare Match 1A |
.equ COM1B0 = 4 ; Comparator B Output Mode Bit 0 |
.equ COM1B1 = 5 ; Comparator B Output Mode Bit 1 |
.equ COM1A0 = 6 ; Comparator A Output Mode Bit 0 |
.equ COM1A1 = 7 ; Comparator A Output Mode Bit 1 |
; TCCR1B - Timer/Counter Control Register B |
.equ CS10 = 0 ; Clock Select Bits |
.equ CS11 = 1 ; Clock Select Bits |
.equ CS12 = 2 ; Clock Select Bits |
.equ CS13 = 3 ; Clock Select Bits |
.equ PSR1 = 6 ; Prescaler Reset Timer/Counter1 |
.equ CTC1 = 7 ; Clear Timer/Counter on Compare Match |
; TCNT1 - Timer/Counter Register |
.equ TCNT1_0 = 0 ; Timer/Counter Register Bit 0 |
.equ TCNT1_1 = 1 ; Timer/Counter Register Bit 1 |
.equ TCNT1_2 = 2 ; Timer/Counter Register Bit 2 |
.equ TCNT1_3 = 3 ; Timer/Counter Register Bit 3 |
.equ TCNT1_4 = 4 ; Timer/Counter Register Bit 4 |
.equ TCNT1_5 = 5 ; Timer/Counter Register Bit 5 |
.equ TCNT1_6 = 6 ; Timer/Counter Register Bit 6 |
.equ TCNT1_7 = 7 ; Timer/Counter Register Bit 7 |
; OCR1A - Output Compare Register |
.equ OCR1A0 = 0 ; Output Compare Register A Bit 0 |
.equ OCR1A1 = 1 ; Output Compare Register A Bit 1 |
.equ OCR1A2 = 2 ; Output Compare Register A Bit 2 |
.equ OCR1A3 = 3 ; Output Compare Register A Bit 3 |
.equ OCR1A4 = 4 ; Output Compare Register A Bit 4 |
.equ OCR1A5 = 5 ; Output Compare Register A Bit 5 |
.equ OCR1A6 = 6 ; Output Compare Register A Bit 6 |
.equ OCR1A7 = 7 ; Output Compare Register A Bit 7 |
; OCR1B - Output Compare Register |
.equ OCR1B0 = 0 ; Output Compare Register B Bit 0 |
.equ OCR1B1 = 1 ; Output Compare Register B Bit 1 |
.equ OCR1B2 = 2 ; Output Compare Register B Bit 2 |
.equ OCR1B3 = 3 ; Output Compare Register B Bit 3 |
.equ OCR1B4 = 4 ; Output Compare Register B Bit 4 |
.equ OCR1B5 = 5 ; Output Compare Register B Bit 5 |
.equ OCR1B6 = 6 ; Output Compare Register B Bit 6 |
.equ OCR1B7 = 7 ; Output Compare Register B Bit 7 |
; OCR1C - Output Compare Register |
.equ OCR1C0 = 0 ; Output Compare Register C Bit 0 |
.equ OCR1C1 = 1 ; Output Compare Register C Bit 1 |
.equ OCR1C2 = 2 ; Output Compare Register C Bit 2 |
.equ OCR1C3 = 3 ; Output Compare Register C Bit 3 |
.equ OCR1C4 = 4 ; Output Compare Register C Bit 4 |
.equ OCR1C5 = 5 ; Output Compare Register C Bit 5 |
.equ OCR1C6 = 6 ; Output Compare Register C Bit 6 |
.equ OCR1C7 = 7 ; Output Compare Register C Bit 7 |
; TIMSK - Timer/Counter Interrupt Mask Register |
;.equ TOIE0 = 1 ; Timer/Counter1 Overflow Interrupt Enable |
.equ TOIE1 = 2 ; Timer/Counter1 Overflow Interrupt Enable |
.equ OCIE1B = 5 ; Timer/Counter1 Output Compare Interrupt Enable |
.equ OCIE1A = 6 ; Timer/Counter1 Output Compare Interrupt Enable |
; TIFR - Timer/Counter Interrupt Flag Register |
.equ TOV1 = 2 ; Timer/Counter1 Overflow Flag |
.equ OCF1B = 5 ; Timer/Counter1 Output Compare Flag 1B |
.equ OCF1A = 6 ; Timer/Counter1 Output Compare Flag 1A |
; PLLCSR - PLL Control and Status Register |
.equ PLOCK = 0 ; PLL Lock Detector |
.equ PLLE = 1 ; PLL Enable |
.equ PCKE = 2 ; PCK Enable |
; ***** EXTERNAL_INTERRUPT *********** |
; GIMSK - General Interrupt Mask Register |
.equ PCIE0 = 4 ; Pin Change Interrupt Enable 0 |
.equ PCIE1 = 5 ; Pin Change Interrupt Enable 1 |
.equ INT0 = 6 ; External Interrupt Request 0 Enable |
; GIFR - General Interrupt Flag register |
.equ PCIF = 5 ; Pin Change Interrupt Flag |
.equ INTF0 = 6 ; External Interrupt Flag 0 |
; ***** LOCKSBITS ******************************************************** |
.equ LB1 = 0 ; Lockbit |
.equ LB2 = 1 ; Lockbit |
; ***** FUSES ************************************************************ |
; LOW fuse bits |
.equ CKSEL0 = 0 ; Select Clock Source |
.equ CKSEL1 = 1 ; Select Clock Source |
.equ CKSEL2 = 2 ; Select Clock Source |
.equ CKSEL3 = 3 ; Select Clock Source |
.equ SUT0 = 4 ; Select start-up time |
.equ SUT1 = 5 ; Select start-up time |
.equ CKOPT = 6 ; Oscillator options |
.equ PLLCK = 7 ; Use PLL for internal clock |
; HIGH fuse bits |
.equ BODEN = 0 ; Brown out detector enable |
.equ BODLEVEL = 1 ; Brown out detector trigger level |
.equ EESAVE = 2 ; EEPROM memory is preserved through the Chip Erase |
.equ SPIEN = 3 ; Enable Serial Program and Data Downloading |
.equ RSTDISBL = 4 ; Select if PB/ is I/O pin or RESET pin |
; ***** CPU REGISTER DEFINITIONS ***************************************** |
.def XH = r27 |
.def XL = r26 |
.def YH = r29 |
.def YL = r28 |
.def ZH = r31 |
.def ZL = r30 |
; ***** DATA MEMORY DECLARATIONS ***************************************** |
.equ FLASHEND = 0x03ff ; Note: Word address |
.equ IOEND = 0x003f |
.equ SRAM_START = 0x0060 |
.equ SRAM_SIZE = 128 |
.equ RAMEND = 0x00df |
.equ XRAMEND = 0x0000 |
.equ E2END = 0x007f |
.equ EEPROMEND = 0x007f |
.equ EEADRBITS = 7 |
#pragma AVRPART MEMORY PROG_FLASH 2048 |
#pragma AVRPART MEMORY EEPROM 128 |
#pragma AVRPART MEMORY INT_SRAM SIZE 128 |
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60 |
; ***** INTERRUPT VECTORS ************************************************ |
.equ INT0addr = 0x0001 ; External Interrupt 0 |
.equ PCI0addr = 0x0002 ; External Interrupt Request 0 |
.equ OC1Aaddr = 0x0003 ; Timer/Counter1 Compare Match 1A |
.equ OC1Baddr = 0x0004 ; Timer/Counter1 Compare Match 1B |
.equ OVF1addr = 0x0005 ; Timer/Counter1 Overflow |
.equ OVF0addr = 0x0006 ; Timer/Counter0 Overflow |
.equ USI_STARTaddr = 0x0007 ; USI Start |
.equ USI_OVFaddr = 0x0008 ; USI Overflow |
.equ ERDYaddr = 0x0009 ; EEPROM Ready |
.equ ACIaddr = 0x000a ; Analog Comparator |
.equ ADCCaddr = 0x000b ; ADC Conversion Complete |
.equ INT_VECTORS_SIZE = 12 ; size in words |
#pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED break |
#endif /* _TN26DEF_INC_ */ |
; ***** END OF FILE ****************************************************** |
/contrib/toolchain/avra/includes/tn28def.inc |
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0,0 → 1,188 |
;*************************************************************************** |
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y |
;* |
;* Number :AVR000 |
;* File Name :"tn28def.inc" |
;* Title :Register/Bit Definitions for the ATtiny28 |
;* Date :99.01.28 |
;* Version :1.30 |
;* Support E-mail :avr@atmel.com |
;* Target MCU :ATtiny28 |
;* |
;* DESCRIPTION |
;* When including this file in the assembly program file, all I/O register |
;* names and I/O register bit names appearing in the data book can be used. |
;* In addition, the two registers forming the data pointers Z have been |
;* assigned names ZL - ZH. |
;* |
;* |
;* The Register names are represented by their hexadecimal address. |
;* |
;* The Register Bit names are represented by their bit number (0-7). |
;* |
;* Please observe the difference in using the bit names with instructions |
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" |
;* (skip if bit in register set/cleared). The following example illustrates |
;* this: |
;* |
;* in r16,PORTB ;read PORTB latch |
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) |
;* out PORTB,r16 ;output to PORTB |
;* |
;* in r16,TIFR ;read the Timer Interrupt Flag Register |
;* sbrc r16,TOV0 ;test the overflow flag (use bit#) |
;* rjmp TOV0_is_set ;jump if set |
;* ... ;otherwise do something else |
;*************************************************************************** |
;***** Specify Device |
.device ATtiny28 |
;***** I/O Register Definitions |
.equ SREG =$3f |
.equ PORTA =$1b |
.equ PACR =$1a |
.equ PINA =$19 |
.equ PINB =$16 |
.equ PORTD =$12 |
.equ DDRD =$11 |
.equ PIND =$10 |
.equ ACSR =$08 |
.equ MCUCS =$07 |
.equ ICR =$06 |
.equ IFR =$05 |
.equ TCCR0 =$04 |
.equ TCNT0 =$03 |
.equ MODCR =$02 |
.equ WDTCR =$01 |
.equ OSCCAL =$00 |
;***** Bit Definitions |
.equ PA3 =3 |
.equ PA2 =2 |
.equ PA1 =1 |
.equ PA0 =0 |
.equ DDA3 =3 |
.equ PA2HC =2 |
.equ DDA1 =1 |
.equ DDA0 =0 |
.equ PINA3 =3 |
.equ PINA1 =1 |
.equ PINA0 =0 |
.equ PINB7 =7 |
.equ PINB6 =6 |
.equ PINB5 =5 |
.equ PINB4 =4 |
.equ PINB3 =3 |
.equ PINB2 =2 |
.equ PINB1 =1 |
.equ PINB0 =0 |
.equ PD7 =7 |
.equ PD6 =6 |
.equ PD5 =5 |
.equ PD4 =4 |
.equ PD3 =3 |
.equ PD2 =2 |
.equ PD1 =1 |
.equ PD0 =0 |
.equ DDD7 =7 |
.equ DDD6 =6 |
.equ DDD5 =5 |
.equ DDD4 =4 |
.equ DDD3 =3 |
.equ DDD2 =2 |
.equ DDD1 =1 |
.equ DDD0 =0 |
.equ PIND7 =7 |
.equ PIND6 =6 |
.equ PIND5 =5 |
.equ PIND4 =4 |
.equ PIND3 =3 |
.equ PIND2 =2 |
.equ PIND1 =1 |
.equ PIND0 =0 |
.equ ACD =7 |
.equ ACO =5 |
.equ ACI =4 |
.equ ACIE =3 |
.equ ACIS1 =1 |
.equ ACIS0 =0 |
.equ PLUPB =7 |
.equ SE =5 |
.equ SM =4 |
.equ WDRF =3 |
.equ EXTRF =1 |
.equ PORF =0 |
.equ INT1 =7 |
.equ INT0 =6 |
.equ LLIE =5 |
.equ TOIE0 =4 |
.equ ISC11 =3 |
.equ ISC10 =2 |
.equ ISC01 =1 |
.equ ISC00 =0 |
.equ INTF1 =7 |
.equ INTF0 =6 |
.equ TOV0 =4 |
.equ FOV0 =7 |
.equ OOM01 =4 |
.equ OOM00 =3 |
.equ CS02 =2 |
.equ CS01 =1 |
.equ CS00 =0 |
.equ WDTOE =4 |
.equ WDE =3 |
.equ WDP2 =2 |
.equ WDP1 =1 |
.equ WDP0 =0 |
.equ ONTIM4 =7 |
.equ ONTIM3 =6 |
.equ ONTIM2 =5 |
.equ ONTIM1 =4 |
.equ ONTIM0 =3 |
.equ MCONF2 =2 |
.equ MCONF1 =1 |
.equ MCONF0 =0 |
.equ CAL7 =7 |
.equ CAL6 =6 |
.equ CAL5 =5 |
.equ CAL4 =4 |
.equ CAL3 =3 |
.equ CAL2 =2 |
.equ CAL1 =1 |
.equ CAL0 =0 |
.def ZL =r30 |
.def ZH =r31 |
.equ FLASHEND = 0x07FF |
.equ RAMEND = 0x03FF |
.equ INT0addr =$001 ;External Interrupt0 Vector Address |
.equ INT1addr =$002 ;External Interrupt1 Vector Address |
.equ LLINTaddr=$003 ;Low level Interrupt Vector Address |
.equ OVF0addr =$004 ;Overflow0 Interrupt Vector Address |
.equ ACIaddr =$005 ;Analog Comparator Interrupt Vector Address |
#pragma AVRPART ADMIN PART_NAME ATtiny28 |
#pragma AVRPART CORE CORE_VERSION V0E |
#pragma AVRPART MEMORY PROG_FLASH 2048 |
#pragma AVRPART MEMORY EEPROM 0 |
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60 |
#pragma AVRPART MEMORY INT_SRAM SIZE 0 |
/contrib/toolchain/avra/includes/tn45def.inc |
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0,0 → 1,682 |
;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** |
;***** Created: 2005-01-11 10:31 ******* Source: ATtiny45.xml ************ |
;************************************************************************* |
;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y |
;* |
;* Number : AVR000 |
;* File Name : "tn45def.inc" |
;* Title : Register/Bit Definitions for the ATtiny45 |
;* Date : 2005-01-11 |
;* Version : 2.14 |
;* Support E-mail : avr@atmel.com |
;* Target MCU : ATtiny45 |
;* |
;* DESCRIPTION |
;* When including this file in the assembly program file, all I/O register |
;* names and I/O register bit names appearing in the data book can be used. |
;* In addition, the six registers forming the three data pointers X, Y and |
;* Z have been assigned names XL - ZH. Highest RAM address for Internal |
;* SRAM is also defined |
;* |
;* The Register names are represented by their hexadecimal address. |
;* |
;* The Register Bit names are represented by their bit number (0-7). |
;* |
;* Please observe the difference in using the bit names with instructions |
;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" |
;* (skip if bit in register set/cleared). The following example illustrates |
;* this: |
;* |
;* in r16,PORTB ;read PORTB latch |
;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#) |
;* out PORTB,r16 ;output to PORTB |
;* |
;* in r16,TIFR ;read the Timer Interrupt Flag Register |
;* sbrc r16,TOV0 ;test the overflow flag (use bit#) |
;* rjmp TOV0_is_set ;jump if set |
;* ... ;otherwise do something else |
;************************************************************************* |
#ifndef _TN45DEF_INC_ |
#define _TN45DEF_INC_ |
#pragma partinc 0 |
; ***** SPECIFY DEVICE *************************************************** |
.device ATtiny45 |
#pragma AVRPART ADMIN PART_NAME ATtiny45 |
.equ SIGNATURE_000 = 0x1e |
.equ SIGNATURE_001 = 0x92 |
.equ SIGNATURE_002 = 0x06 |
#pragma AVRPART CORE CORE_VERSION V2 |
#pragma AVRPART CORE NEW_INSTRUCTIONS lpm rd,z+ |
; ***** I/O REGISTER DEFINITIONS ***************************************** |
; NOTE: |
; Definitions marked "MEMORY MAPPED"are extended I/O ports |
; and cannot be used with IN/OUT instructions |
.equ SREG = 0x3f |
.equ SPH = 0x3e |
.equ SPL = 0x3d |
.equ GIMSK = 0x3b |
.equ GIFR = 0x3a |
.equ TIMSK = 0x39 |
.equ TIFR = 0x38 |
.equ SPMCSR = 0x37 |
.equ MCUCR = 0x35 |
.equ MCUSR = 0x34 |
.equ TCCR0B = 0x33 |
.equ TCNT0 = 0x32 |
.equ OSCCAL = 0x31 |
.equ TCCR1 = 0x30 |
.equ TCNT1 = 0x2f |
.equ OCR1A = 0x2e |
.equ OCR1C = 0x2d |
.equ GTCCR = 0x2c |
.equ OCR1B = 0x2b |
.equ TCCR0A = 0x2a |
.equ OCR0A = 0x29 |
.equ OCR0B = 0x28 |
.equ PLLCSR = 0x27 |
.equ CLKPR = 0x26 |
.equ DTVALA = 0x25 |
.equ DTVALB = 0x24 |
.equ DTPS = 0x23 |
.equ DWDR = 0x22 |
.equ WDTCR = 0x21 |
.equ PRR = 0x20 |
.equ EEARH = 0x1f |
.equ EEARL = 0x1e |
.equ EEDR = 0x1d |
.equ EECR = 0x1c |
.equ PORTB = 0x18 |
.equ DDRB = 0x17 |
.equ PINB = 0x16 |
.equ PCMSK = 0x15 |
.equ DIDR0 = 0x14 |
.equ GPIOR2 = 0x13 |
.equ GPIOR1 = 0x12 |
.equ GPIOR0 = 0x11 |
.equ USIBR = 0x10 |
.equ USIDR = 0x0f |
.equ USISR = 0x0e |
.equ USICR = 0x0d |
.equ ACSR = 0x08 |
.equ ADMUX = 0x07 |
.equ ADCSRA = 0x06 |
.equ ADCH = 0x05 |
.equ ADCL = 0x04 |
.equ ADCSRB = 0x03 |
; ***** BIT DEFINITIONS ************************************************** |
; ***** PORTB ************************ |
; PORTB - Data Register, Port B |
.equ PORTB0 = 0 ; |
.equ PB0 = 0 ; For compatibility |
.equ PORTB1 = 1 ; |
.equ PB1 = 1 ; For compatibility |
.equ PORTB2 = 2 ; |
.equ PB2 = 2 ; For compatibility |
.equ PORTB3 = 3 ; |
.equ PB3 = 3 ; For compatibility |
.equ PORTB4 = 4 ; |
.equ PB4 = 4 ; For compatibility |
.equ PORTB5 = 5 ; |
.equ PB5 = 5 ; For compatibility |
; DDRB - Data Direction Register, Port B |
.equ DDB0 = 0 ; |
.equ DDB1 = 1 ; |
.equ DDB2 = 2 ; |
.equ DDB3 = 3 ; |
.equ DDB4 = 4 ; |
.equ DDB5 = 5 ; |
; PINB - Input Pins, Port B |
.equ PINB0 = 0 ; |
.equ PINB1 = 1 ; |
.equ PINB2 = 2 ; |
.equ PINB3 = 3 ; |
.equ PINB4 = 4 ; |
.equ PINB5 = 5 ; |
; ***** ANALOG_COMPARATOR ************ |
; ADCSRB - ADC Control and Status Register B |
.equ ACME = 6 ; Analog Comparator Multiplexer Enable |
; ACSR - Analog Comparator Control And Status Register |
.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0 |
.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1 |
.equ ACIE = 3 ; Analog Comparator Interrupt Enable |
.equ ACI = 4 ; Analog Comparator Interrupt Flag |
.equ ACO = 5 ; Analog Compare Output |
.equ ACBG = 6 ; Analog Comparator Bandgap Select |
.equ AINBG = ACBG ; For compatibility |
.equ ACD = 7 ; Analog Comparator Disable |
; DIDR0 - |
.equ AIN0D = 0 ; AIN0 Digital Input Disable |
.equ AIN1D = 1 ; AIN1 Digital Input Disable |
; ***** AD_CONVERTER ***************** |
; ADMUX - The ADC multiplexer Selection Register |
.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits |
.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits |
.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits |
.equ MUX3 = 3 ; Analog Channel and Gain Selection Bits |
.equ REFS2 = 4 ; Reference Selection Bit 2 |
.equ ADLAR = 5 ; Left Adjust Result |
.equ REFS0 = 6 ; Reference Selection Bit 0 |
.equ REFS1 = 7 ; Reference Selection Bit 1 |
; ADCSRA - The ADC Control and Status register |
.equ ADPS0 = 0 ; ADC Prescaler Select Bits |
.equ ADPS1 = 1 ; ADC Prescaler Select Bits |
.equ ADPS2 = 2 ; ADC Prescaler Select Bits |
.equ ADIE = 3 ; ADC Interrupt Enable |
.equ ADIF = 4 ; ADC Interrupt Flag |
.equ ADATE = 5 ; ADC Auto Trigger Enable |
.equ ADSC = 6 ; ADC Start Conversion |
.equ ADEN = 7 ; ADC Enable |
; ADCH - ADC Data Register High Byte |
.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0 |
.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1 |
.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2 |
.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3 |
.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4 |
.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5 |
.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6 |
.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7 |
; ADCL - ADC Data Register Low Byte |
.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0 |
.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1 |
.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2 |
.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3 |
.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4 |
.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5 |
.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6 |
.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7 |
; ADCSRB - ADC Control and Status Register B |
.equ ADTS0 = 0 ; ADC Auto Trigger Source 0 |
.equ ADTS1 = 1 ; ADC Auto Trigger Source 1 |
.equ ADTS2 = 2 ; ADC Auto Trigger Source 2 |
.equ IPR = 5 ; Input Polarity Mode |
.equ BIN = 7 ; Bipolar Input Mode |
; DIDR0 - Digital Input Disable Register 0 |
.equ ADC1D = 2 ; ADC1 Digital input Disable |
.equ ADC3D = 3 ; ADC3 Digital input Disable |
.equ ADC2D = 4 ; ADC2 Digital input Disable |
.equ ADC0D = 5 ; ADC0 Digital input Disable |
; ***** USI ************************** |
; USIBR - USI Buffer Register |
.equ USIBR0 = 0 ; USI Buffer Register bit 0 |
.equ USIBR1 = 1 ; USI Buffer Register bit 1 |
.equ USIBR2 = 2 ; USI Buffer Register bit 2 |
.equ USIBR3 = 3 ; USI Buffer Register bit 3 |
.equ USIBR4 = 4 ; USI Buffer Register bit 4 |
.equ USIBR5 = 5 ; USI Buffer Register bit 5 |
.equ USIBR6 = 6 ; USI Buffer Register bit 6 |
.equ USIBR7 = 7 ; USI Buffer Register bit 7 |
; USIDR - USI Data Register |
.equ USIDR0 = 0 ; USI Data Register bit 0 |
.equ USIDR1 = 1 ; USI Data Register bit 1 |
.equ USIDR2 = 2 ; USI Data Register bit 2 |
.equ USIDR3 = 3 ; USI Data Register bit 3 |
.equ USIDR4 = 4 ; USI Data Register bit 4 |
.equ USIDR5 = 5 ; USI Data Register bit 5 |
.equ USIDR6 = 6 ; USI Data Register bit 6 |
.equ USIDR7 = 7 ; USI Data Register bit 7 |
; USISR - USI Status Register |
.equ USICNT0 = 0 ; USI Counter Value Bit 0 |
.equ USICNT1 = 1 ; USI Counter Value Bit 1 |
.equ USICNT2 = 2 ; USI Counter Value Bit 2 |
.equ USICNT3 = 3 ; USI Counter Value Bit 3 |
.equ USIDC = 4 ; Data Output Collision |
.equ USIPF = 5 ; Stop Condition Flag |
.equ USIOIF = 6 ; Counter Overflow Interrupt Flag |
.equ USISIF = 7 ; Start Condition Interrupt Flag |
; USICR - USI Control Register |
.equ USITC = 0 ; Toggle Clock Port Pin |
.equ USICLK = 1 ; Clock Strobe |
.equ USICS0 = 2 ; USI Clock Source Select Bit 0 |
.equ USICS1 = 3 ; USI Clock Source Select Bit 1 |
.equ USIWM0 = 4 ; USI Wire Mode Bit 0 |
.equ USIWM1 = 5 ; USI Wire Mode Bit 1 |
.equ USIOIE = 6 ; Counter Overflow Interrupt Enable |
.equ USISIE = 7 ; Start Condition Interrupt Enable |
; ***** EXTERNAL_INTERRUPT *********** |
; MCUCR - MCU Control Register |
.equ ISC00 = 0 ; Interrupt Sense Control 0 Bit 0 |
.equ ISC01 = 1 ; Interrupt Sense Control 0 Bit 1 |
; GIMSK - General Interrupt Mask Register |
.equ GICR = GIMSK ; For compatibility |
.equ PCIE = 5 ; Pin Change Interrupt Enable |
.equ INT0 = 6 ; External Interrupt Request 0 Enable |
; GIFR - General Interrupt Flag register |
.equ PCIF = 5 ; Pin Change Interrupt Flag |
.equ INTF0 = 6 ; External Interrupt Flag 0 |
; PCMSK - Pin Change Enable Mask |
.equ PCINT0 = 0 ; Pin Change Enable Mask Bit 0 |
.equ PCINT1 = 1 ; Pin Change Enable Mask Bit 1 |
.equ PCINT2 = 2 ; Pin Change Enable Mask Bit 2 |
.equ PCINT3 = 3 ; Pin Change Enable Mask Bit 3 |
.equ PCINT4 = 4 ; Pin Change Enable Mask Bit 4 |
.equ PCINT5 = 5 ; Pin Change Enable Mask Bit 5 |
; ***** EEPROM *********************** |
; EEARL - EEPROM Address Register Low Byte |
.equ EEAR0 = 0 ; EEPROM Read/Write Access Bit 0 |
.equ EEAR1 = 1 ; EEPROM Read/Write Access Bit 1 |
.equ EEAR2 = 2 ; EEPROM Read/Write Access Bit 2 |
.equ EEAR3 = 3 ; EEPROM Read/Write Access Bit 3 |
.equ EEAR4 = 4 ; EEPROM Read/Write Access Bit 4 |
.equ EEAR5 = 5 ; EEPROM Read/Write Access Bit 5 |
.equ EEAR6 = 6 ; EEPROM Read/Write Access Bit 6 |
.equ EEAR7 = 7 ; EEPROM Read/Write Access Bit 7 |
; EEARH - EEPROM Address Register High Byte |
.equ EEAR8 = 0 ; EEPROM Read/Write Access Bit 0 |
; EEDR - EEPROM Data Register |
.equ EEDR0 = 0 ; EEPROM Data Register bit 0 |
.equ EEDR1 = 1 ; EEPROM Data Register bit 1 |
.equ EEDR2 = 2 ; EEPROM Data Register bit 2 |
.equ EEDR3 = 3 ; EEPROM Data Register bit 3 |
.equ EEDR4 = 4 ; EEPROM Data Register bit 4 |
.equ EEDR5 = 5 ; EEPROM Data Register bit 5 |
.equ EEDR6 = 6 ; EEPROM Data Register bit 6 |
.equ EEDR7 = 7 ; EEPROM Data Register bit 7 |
; EECR - EEPROM Control Register |
.equ EERE = 0 ; EEPROM Read Enable |
.equ EEPE = 1 ; EEPROM Write Enable |
.equ EEMPE = 2 ; EEPROM Master Write Enable |
.equ EERIE = 3 ; EEPROM Ready Interrupt Enable |
.equ EEPM0 = 4 ; EEPROM Programming Mode Bit 0 |
.equ EEPM1 = 5 ; EEPROM Programming Mode Bit 1 |
; ***** WATCHDOG ********************* |
; WDTCR - Watchdog Timer Control Register |
.equ WDTCSR = WDTCR ; For compatibility |
.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0 |
.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1 |
.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2 |
.equ WDE = 3 ; Watch Dog Enable |
.equ WDCE = 4 ; Watchdog Change Enable |
.equ WDTOE = WDCE ; For compatibility |
.equ WDP3 = 5 ; Watchdog Timer Prescaler Bit 3 |
.equ WDIE = 6 ; Watchdog Timeout Interrupt Enable |
.equ WDIF = 7 ; Watchdog Timeout Interrupt Flag |
; ***** TIMER_COUNTER_0 ************** |
; TIMSK - Timer/Counter Interrupt Mask Register |
.equ TOIE0 = 1 ; Timer/Counter0 Overflow Interrupt Enable |
.equ OCIE0B = 3 ; Timer/Counter0 Output Compare Match B Interrupt Enable |
.equ OCIE0A = 4 ; Timer/Counter0 Output Compare Match A Interrupt Enable |
; TIFR - Timer/Counter0 Interrupt Flag register |
.equ TOV0 = 1 ; Timer/Counter0 Overflow Flag |
.equ OCF0B = 3 ; Timer/Counter0 Output Compare Flag 0B |
.equ OCF0A = 4 ; Timer/Counter0 Output Compare Flag 0A |
; TCCR0A - Timer/Counter Control Register A |
.equ WGM00 = 0 ; Waveform Generation Mode |
.equ WGM01 = 1 ; Waveform Generation Mode |
.equ COM0B0 = 4 ; Compare Output Mode, Fast PWm |
.equ COM0B1 = 5 ; Compare Output Mode, Fast PWm |
.equ COM0A0 = 6 ; Compare Output Mode, Phase Correct PWM Mode |
.equ COM0A1 = 7 ; Compare Output Mode, Phase Correct PWM Mode |
; TCCR0B - Timer/Counter Control Register B |
.equ CS00 = 0 ; Clock Select |
.equ CS01 = 1 ; Clock Select |
.equ CS02 = 2 ; Clock Select |
.equ WGM02 = 3 ; |
.equ FOC0B = 6 ; Force Output Compare B |
.equ FOC0A = 7 ; Force Output Compare A |
; TCNT0 - Timer/Counter0 |
.equ TCNT0_0 = 0 ; |
.equ TCNT0_1 = 1 ; |
.equ TCNT0_2 = 2 ; |
.equ TCNT0_3 = 3 ; |
.equ TCNT0_4 = 4 ; |
.equ TCNT0_5 = 5 ; |
.equ TCNT0_6 = 6 ; |
.equ TCNT0_7 = 7 ; |
; OCR0A - Timer/Counter0 Output Compare Register |
.equ OCR0_0 = 0 ; |
.equ OCR0_1 = 1 ; |
.equ OCR0_2 = 2 ; |
.equ OCR0_3 = 3 ; |
.equ OCR0_4 = 4 ; |
.equ OCR0_5 = 5 ; |
.equ OCR0_6 = 6 ; |
.equ OCR0_7 = 7 ; |
; OCR0B - Timer/Counter0 Output Compare Register |
;.equ OCR0_0 = 0 ; |
;.equ OCR0_1 = 1 ; |
;.equ OCR0_2 = 2 ; |
;.equ OCR0_3 = 3 ; |
;.equ OCR0_4 = 4 ; |
;.equ OCR0_5 = 5 ; |
;.equ OCR0_6 = 6 ; |
;.equ OCR0_7 = 7 ; |
; GTCCR - General Timer/Counter Control Register |
.equ PSR0 = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0 |
.equ TSM = 7 ; Timer/Counter Synchronization Mode |
; ***** TIMER_COUNTER_1 ************** |
; TCCR1 - Timer/Counter Control Register |
.equ CS10 = 0 ; Clock Select Bits |
.equ CS11 = 1 ; Clock Select Bits |
.equ CS12 = 2 ; Clock Select Bits |
.equ CS13 = 3 ; Clock Select Bits |
.equ COM1A0 = 4 ; Compare Output Mode, Bit 1 |
.equ COM1A1 = 5 ; Compare Output Mode, Bit 0 |
.equ PWM1A = 6 ; Pulse Width Modulator Enable |
.equ CTC1 = 7 ; Clear Timer/Counter on Compare Match |
; TCNT1 - Timer/Counter Register |
.equ TCNT1_0 = 0 ; Timer/Counter Register Bit 0 |
.equ TCNT1_1 = 1 ; Timer/Counter Register Bit 1 |
.equ TCNT1_2 = 2 ; Timer/Counter Register Bit 2 |
.equ TCNT1_3 = 3 ; Timer/Counter Register Bit 3 |
.equ TCNT1_4 = 4 ; Timer/Counter Register Bit 4 |
.equ TCNT1_5 = 5 ; Timer/Counter Register Bit 5 |
.equ TCNT1_6 = 6 ; Timer/Counter Register Bit 6 |
.equ TCNT1_7 = 7 ; Timer/Counter Register Bit 7 |
; OCR1A - Output Compare Register |
.equ OCR1A0 = 0 ; Output Compare Register A Bit 0 |
.equ OCR1A1 = 1 ; Output Compare Register A Bit 1 |
.equ OCR1A2 = 2 ; Output Compare Register A Bit 2 |
.equ OCR1A3 = 3 ; Output Compare Register A Bit 3 |
.equ OCR1A4 = 4 ; Output Compare Register A Bit 4 |
.equ OCR1A5 = 5 ; Output Compare Register A Bit 5 |
.equ OCR1A6 = 6 ; Output Compare Register A Bit 6 |
.equ OCR1A7 = 7 ; Output Compare Register A Bit 7 |
; OCR1B - Output Compare Register |
.equ OCR1B0 = 0 ; Output Compare Register B Bit 0 |
.equ OCR1B1 = 1 ; Output Compare Register B Bit 1 |
.equ OCR1B2 = 2 ; Output Compare Register B Bit 2 |
.equ OCR1B3 = 3 ; Output Compare Register B Bit 3 |
.equ OCR1B4 = 4 ; Output Compare Register B Bit 4 |
.equ OCR1B5 = 5 ; Output Compare Register B Bit 5 |
.equ OCR1B6 = 6 ; Output Compare Register B Bit 6 |
.equ OCR1B7 = 7 ; Output Compare Register B Bit 7 |
; OCR1C - Output compare register |
.equ OCR1C0 = 0 ; |
.equ OCR1C1 = 1 ; |
.equ OCR1C2 = 2 ; |
.equ OCR1C3 = 3 ; |
.equ OCR1C4 = 4 ; |
.equ OCR1C5 = 5 ; |
.equ OCR1C6 = 6 ; |
.equ OCR1C7 = 7 ; |
; TIMSK - Timer/Counter Interrupt Mask Register |
.equ TOIE1 = 2 ; Timer/Counter1 Overflow Interrupt Enable |
.equ OCIE1B = 5 ; OCIE1A: Timer/Counter1 Output Compare B Interrupt Enable |
.equ OCE1A = 6 ; OCIE1A: Timer/Counter1 Output Compare Interrupt Enable |
; TIFR - Timer/Counter Interrupt Flag Register |
.equ TOV1 = 2 ; Timer/Counter1 Overflow Flag |
.equ OCF1B = 5 ; Timer/Counter1 Output Compare Flag 1B |
.equ OCF1A = 6 ; Timer/Counter1 Output Compare Flag 1A |
; GTCCR - Timer counter control register |
.equ PSR1 = 1 ; Prescaler Reset Timer/Counter1 |
.equ FOC1A = 2 ; Force Output Compare 1A |
.equ FOC1B = 3 ; Force Output Compare Match 1B |
.equ COM1B0 = 4 ; Comparator B Output Mode |
.equ COM1B1 = 5 ; Comparator B Output Mode |
.equ PWM1B = 6 ; Pulse Width Modulator B Enable |
; DTPS - Dead time prescaler register |
.equ DTPS0 = 0 ; |
.equ DTPS1 = 1 ; |
; DTVALA - Dead time value register |
.equ DTVL0 = 0 ; |
.equ DTVL1 = 1 ; |
.equ DTVL2 = 2 ; |
.equ DTVL3 = 3 ; |
.equ DTVH0 = 4 ; |
.equ DTVH1 = 5 ; |
.equ DTVH2 = 6 ; |
.equ DTVH3 = 7 ; |
; DTVALB - Dead time value B |
;.equ DTVL0 = 0 ; |
;.equ DTVL1 = 1 ; |
;.equ DTVL2 = 2 ; |
;.equ DTVL3 = 3 ; |
;.equ DTVH0 = 4 ; |
;.equ DTVH1 = 5 ; |
;.equ DTVH2 = 6 ; |
;.equ DTVH3 = 7 ; |
; ***** CPU ************************** |
; SREG - Status Register |
.equ SREG_C = 0 ; Carry Flag |
.equ SREG_Z = 1 ; Zero Flag |
.equ SREG_N = 2 ; Negative Flag |
.equ SREG_V = 3 ; Two's Complement Overflow Flag |
.equ SREG_S = 4 ; Sign Bit |
.equ SREG_H = 5 ; Half Carry Flag |
.equ SREG_T = 6 ; Bit Copy Storage |
.equ SREG_I = 7 ; Global Interrupt Enable |
; MCUCR - MCU Control Register |
;.equ ISC00 = 0 ; Interrupt Sense Control 0 bit 0 |
;.equ ISC01 = 1 ; Interrupt Sense Control 0 bit 1 |
.equ SM0 = 3 ; Sleep Mode Select Bit 0 |
.equ SM1 = 4 ; Sleep Mode Select Bit 1 |
.equ SE = 5 ; Sleep Enable |
.equ PUD = 6 ; Pull-up Disable |
; MCUSR - MCU Status register |
.equ PORF = 0 ; Power-On Reset Flag |
.equ EXTRF = 1 ; External Reset Flag |
.equ BORF = 2 ; Brown-out Reset Flag |
.equ WDRF = 3 ; Watchdog Reset Flag |
; PRR - Power Reduction Register |
.equ PRADC = 0 ; Power Reduction ADC |
.equ PRUSI = 1 ; Power Reduction USI |
.equ PRTIM0 = 2 ; Power Reduction Timer/Counter0 |
.equ PRTIM1 = 3 ; Power Reduction Timer/Counter1 |
; OSCCAL - Oscillator Calibration Register |
.equ CAL0 = 0 ; Oscillatro Calibration Value Bit 0 |
.equ CAL1 = 1 ; Oscillatro Calibration Value Bit 1 |
.equ CAL2 = 2 ; Oscillatro Calibration Value Bit 2 |
.equ CAL3 = 3 ; Oscillatro Calibration Value Bit 3 |
.equ CAL4 = 4 ; Oscillatro Calibration Value Bit 4 |
.equ CAL5 = 5 ; Oscillatro Calibration Value Bit 5 |
.equ CAL6 = 6 ; Oscillatro Calibration Value Bit 6 |
; PLLCSR - PLL Control and status register |
.equ PLOCK = 0 ; PLL Lock detector |
.equ PLLE = 1 ; PLL Enable |
.equ PCKE = 2 ; PCK Enable |
.equ LSM = 7 ; Low speed mode |
; CLKPR - Clock Prescale Register |
.equ CLKPS0 = 0 ; Clock Prescaler Select Bit 0 |
.equ CLKPS1 = 1 ; Clock Prescaler Select Bit 1 |
.equ CLKPS2 = 2 ; Clock Prescaler Select Bit 2 |
.equ CLKPS3 = 3 ; Clock Prescaler Select Bit 3 |
.equ CLKPCE = 7 ; Clock Prescaler Change Enable |
; DWDR - debugWire data register |
.equ DWDR0 = 0 ; |
.equ DWDR1 = 1 ; |
.equ DWDR2 = 2 ; |
.equ DWDR3 = 3 ; |
.equ DWDR4 = 4 ; |
.equ DWDR5 = 5 ; |
.equ DWDR6 = 6 ; |
.equ DWDR7 = 7 ; |
; GPIOR2 - General Purpose IO register 2 |
.equ GPIOR20 = 0 ; |
.equ GPIOR21 = 1 ; |
.equ GPIOR22 = 2 ; |
.equ GPIOR23 = 3 ; |
.equ GPIOR24 = 4 ; |
.equ GPIOR25 = 5 ; |
.equ GPIOR26 = 6 ; |
.equ GPIOR27 = 7 ; |
; GPIOR1 - General Purpose register 1 |
.equ GPIOR10 = 0 ; |
.equ GPIOR11 = 1 ; |
.equ GPIOR12 = 2 ; |
.equ GPIOR13 = 3 ; |
.equ GPIOR14 = 4 ; |
.equ GPIOR15 = 5 ; |
.equ GPIOR16 = 6 ; |
.equ GPIOR17 = 7 ; |
; GPIOR0 - General purpose register 0 |
.equ GPIOR00 = 0 ; |
.equ GPIOR01 = 1 ; |
.equ GPIOR02 = 2 ; |
.equ GPIOR03 = 3 ; |
.equ GPIOR04 = 4 ; |
.equ GPIOR05 = 5 ; |
.equ GPIOR06 = 6 ; |
.equ GPIOR07 = 7 ; |
; ***** BOOT_LOAD ******************** |
; SPMCSR - Store Program Memory Control Register |
.equ SPMEN = 0 ; Store Program Memory Enable |
.equ PGERS = 1 ; Page Erase |
.equ PGWRT = 2 ; Page Write |
.equ RFLB = 3 ; Read fuse and lock bits |
.equ CTPB = 4 ; Clear temporary page buffer |
; ***** LOCKSBITS ******************************************************** |
.equ LB1 = 0 ; Lockbit |
.equ LB2 = 1 ; Lockbit |
; ***** FUSES ************************************************************ |
; LOW fuse bits |
.equ CKSEL0 = 0 ; Select Clock source |
.equ CKSEL1 = 1 ; Select Clock source |
.equ CKSEL2 = 2 ; Select Clock source |
.equ CKSEL3 = 3 ; Select Clock source |
.equ SUT0 = 4 ; Select start-up time |
.equ SUT1 = 5 ; Select start-up time |
.equ CKOUT = 6 ; Clock Output Enable |
.equ CKDIV8 = 7 ; Divide clock by 8 |
; HIGH fuse bits |
.equ BODLEVEL0 = 0 ; Brown-out Detector trigger level |
.equ BODLEVEL1 = 1 ; Brown-out Detector trigger level |
.equ BODLEVEL2 = 2 ; Brown-out Detector trigger level |
.equ EESAVE = 3 ; EEPROM memory is preserved through the Chip Erase |
.equ WDTON = 4 ; Watchdog Timer always on |
.equ SPIEN = 5 ; Enable Serial Program and Data Downloading |
.equ DWEN = 6 ; DebugWIRE Enable |
.equ RSTDISBL = 7 ; External Reset disable |
; EXTENDED fuse bits |
.equ SELFPRGEN = 0 ; Self-Programming Enable |
; ***** CPU REGISTER DEFINITIONS ***************************************** |
.def XH = r27 |
.def XL = r26 |
.def YH = r29 |
.def YL = r28 |
.def ZH = r31 |
.def ZL = r30 |
; ***** DATA MEMORY DECLARATIONS ***************************************** |
.equ FLASHEND = 0x07ff ; Note: Word address |
.equ IOEND = 0x003f |
.equ SRAM_START = 0x0060 |
.equ SRAM_SIZE = 256 |
.equ RAMEND = 0x015f |
.equ XRAMEND = 0x0000 |
.equ E2END = 0x00ff |
.equ EEPROMEND = 0x00ff |
.equ EEADRBITS = 8 |
#pragma AVRPART MEMORY PROG_FLASH 4096 |
#pragma AVRPART MEMORY EEPROM 256 |
#pragma AVRPART MEMORY INT_SRAM SIZE 256 |
#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60 |
; ***** BOOTLOADER DECLARATIONS ****************************************** |
.equ NRWW_START_ADDR = 0x0 |
.equ NRWW_STOP_ADDR = 0x7ff |
.equ RWW_START_ADDR = 0x0 |
.equ RWW_STOP_ADDR = 0x0 |
.equ PAGESIZE = 32 |
; ***** INTERRUPT VECTORS ************************************************ |
.equ INT0addr = 0x0001 ; External Interrupt 0 |
.equ PCI0addr = 0x0002 ; Pin change Interrupt Request 0 |
.equ OC1Aaddr = 0x0003 ; Timer/Counter1 Compare Match 1A |
.equ OVF1addr = 0x0004 ; Timer/Counter1 Overflow |
.equ OVF0addr = 0x0005 ; Timer/Counter0 Overflow |
.equ ERDYaddr = 0x0006 ; EEPROM Ready |
.equ ACIaddr = 0x0007 ; Analog comparator |
.equ ADCCaddr = 0x0008 ; ADC Conversion ready |
.equ OC1Baddr = 0x0009 ; Timer/Counter1 Compare Match B |
.equ OC0Aaddr = 0x000a ; Timer/Counter0 Compare Match A |
.equ OC0Baddr = 0x000b ; Timer/Counter0 Compare Match B |
.equ WDTaddr = 0x000c ; Watchdog Time-out |
.equ USI_STARTaddr = 0x000d ; USI START |
.equ USI_OVFaddr = 0x000e ; USI Overflow |
.equ INT_VECTORS_SIZE = 15 ; size in words |
#endif /* _TN45DEF_INC_ */ |
; ***** END OF FILE ****************************************************** |
/contrib/toolchain/avra/src/Makefile |
---|
0,0 → 1,40 |
SDK_DIR:= $(abspath ../../../sdk) |
LDFLAGS = -static -S -nostdlib -T $(SDK_DIR)/sources/newlib/app.lds --image-base 0 |
CFLAGS = -c -fno-ident -Wall -O3 -fomit-frame-pointer -U__WIN32__ -U_Win32 -U_WIN32 -U__MINGW32__ -UWIN32 |
INCLUDES= -I $(SDK_DIR)/sources/newlib/libc/include |
LIBPATH:= -L $(SDK_DIR)/lib -L /home/autobuild/tools/win32/mingw32/lib |
CC = kos32-gcc $(CFLAGS) $(INCLUDES) |
LD = kos32-ld |
SOURCES = avra.c device.c parser.c expr.c mnemonic.c directiv.c macro.c file.c map.c coff.c |
OBJECTS = $(SOURCES:.c=.o) |
OBJ_ALL = $(OBJECTS) args.o stdextra.o |
#******************************************************************** |
default: avra |
avra: $(OBJ_ALL) |
$(LD) $(OBJ_ALL) $(LDFLAGS) $(LIBPATH) -o avra -lgcc -lc.dll -lapp |
objcopy avra -O binary |
args.o: args.c misc.h args.h |
avra.o: avra.c misc.h args.h avra.h device.h |
device.o: device.c misc.h avra.h device.h |
directiv.o: directiv.c misc.h args.h avra.h device.h |
expr.o: expr.c misc.h avra.h |
file.o: file.c misc.h avra.h |
macro.o: macro.c misc.h args.h avra.h |
mnemonic.o: mnemonic.c misc.h avra.h device.h |
parser.o: parser.c misc.h avra.h |
stdextra.o: stdextra.c misc.h |
coff.o: coff.c coff.h |
clean: |
rm -f avra *.o *.p *~ |
/contrib/toolchain/avra/src/args.c |
---|
0,0 → 1,222 |
/*********************************************************************** |
* |
* avra - Assembler for the Atmel AVR microcontroller series |
* |
* Copyright (C) 1998-2004 Jon Anders Haugum, Tobias Weber |
* |
* This program is free software; you can redistribute it and/or modify |
* it under the terms of the GNU General Public License as published by |
* the Free Software Foundation; either version 2 of the License, or |
* (at your option) any later version. |
* |
* This program is distributed in the hope that it will be useful, |
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
* GNU General Public License for more details. |
* |
* You should have received a copy of the GNU General Public License |
* along with this program; see the file COPYING. If not, write to |
* the Free Software Foundation, Inc., 59 Temple Place - Suite 330, |
* Boston, MA 02111-1307, USA. |
* |
* |
* Authors of avra can be reached at: |
* email: jonah@omegav.ntnu.no, tobiw@suprafluid.com |
* www: http://sourceforge.net/projects/avra |
*/ |
#include <stdio.h> |
#include <stdlib.h> |
#include <string.h> |
#include "misc.h" |
#include "args.h" |
struct args *alloc_args(int arg_count) |
{ |
struct args *args; |
args = malloc(sizeof(struct args)); |
if(args) { |
args->arg = malloc(sizeof(struct arg) * arg_count); |
if(args->arg) { |
args->count = arg_count; |
args->first_data = NULL; |
return(args); |
} |
free(args); |
} |
printf("Error: Unable to allocate memory\n"); |
return(NULL); |
} |
int read_args(struct args *args, int argc, char *argv[]) |
{ |
int i, j, k, ok, i_old; |
struct data_list **last_data; |
/*** init ***/ |
ok = True; |
args->first_data = NULL; |
/*** end of init ***/ |
last_data = &args->first_data; |
for(i = 1; (i < argc) && ok; i++) { |
if(argv[i][0] == '-') { |
last_data = &args->first_data; |
if(argv[i][1] == 0) { |
printf("Error: Unknown option: -\n"); |
ok = False; |
} else |
if(argv[i][1] == '-') { |
j = 0; |
while((j != args->count) && strcmp(&argv[i][2], args->arg[j].longarg)) { |
j++; |
} |
if(j == args->count) { |
printf("Error: Unknown option: %s\n", argv[i]); |
ok = False; |
} else { |
switch(args->arg[j].type) { |
case ARGTYPE_STRING: |
case ARGTYPE_STRING_MULTISINGLE: |
/* if argument is a string parameter we will do this: */ |
if((i + 1) == argc) { |
printf("Error: No argument supplied with option: %s\n", argv[i]); |
ok = False; |
} else |
if(args->arg[j].type != ARGTYPE_STRING_MULTISINGLE) |
args->arg[j].data = argv[++i]; |
else |
ok = add_arg((struct data_list **)&args->arg[j].data, argv[++i]); |
break; |
case ARGTYPE_BOOLEAN: |
args->arg[j].data = (char *)True; |
break; |
case ARGTYPE_STRING_MULTI: |
last_data = (struct data_list **)&args->arg[j].data; |
break; |
} |
} |
} else { |
for(k = 1, i_old = i; (argv[i][k] != '\0') && ok && (i == i_old); k++) { |
j = 0; |
while((j != args->count) && (argv[i][k] != args->arg[j].letter)) |
j++; |
if(j == args->count) { |
printf("Error: Unknown option: -%c\n", argv[i][k]); |
ok = False; |
} else { |
switch(args->arg[j].type) { |
case ARGTYPE_STRING: |
case ARGTYPE_STRING_MULTISINGLE: |
if(argv[i][k + 1] != '\0') { |
printf("Error: Option -%c must be followed by it's argument\n", argv[i][k]); |
ok = False; |
} else { |
if((i + 1) == argc) { |
printf("Error: No argument supplied with option: -%c\n", argv[i][k]); |
ok = False; |
} else |
if(args->arg[j].type != ARGTYPE_STRING_MULTISINGLE) |
args->arg[j].data = argv[++i]; |
else |
ok = add_arg((struct data_list **)&args->arg[j].data, argv[++i]); |
} |
break; |
case ARGTYPE_BOOLEAN: |
args->arg[j].data = (char *)True; |
break; |
case ARGTYPE_STRING_MULTI: |
last_data = (struct data_list **)&args->arg[j].data; |
break; |
/* Parameters that have only one char attached */ |
case ARGTYPE_CHAR_ATTACHED: |
if((i + 1) == argc) { |
printf("Error: missing arguments: asm file"); |
ok = False; |
} else { |
switch(argv[i][++k]) { |
case 'O': |
args->arg[j].data = (char *)AVRSTUDIO; |
break; |
case 'G': |
args->arg[j].data = (char *)GENERIC; |
break; |
case 'I': |
args->arg[j].data = (char *)INTEL; |
break; |
case 'M': |
args->arg[j].data = (char *)MOTOROLA; |
break; |
default: |
printf("Error: wrong file type '%c'",argv[i][2]); |
ok = False; |
} |
} |
} |
} |
} |
} |
} else |
ok = add_arg(last_data, argv[i]); |
} |
return(ok); |
} |
int add_arg(struct data_list **last_data, char *argv) |
{ |
struct data_list *data; |
while(*last_data) |
last_data = &((*last_data)->next); |
data = malloc(sizeof(struct data_list)); |
if(data) { |
data->next = NULL; |
data->data = argv; |
*last_data = data; |
last_data = &data->next; |
} else { |
printf("Error: Unable to allocate memory\n"); |
return(False); |
} |
return(True); |
} |
void free_args(struct args *args) |
{ |
int i; |
struct data_list *data, *temp; |
for(data = args->first_data; data;) { |
temp = data; |
data = data->next; |
free(temp); |
} |
for(i = 0; i != args->count; i++) |
if((args->arg[i].type == ARGTYPE_STRING_MULTI) |
|| (args->arg[i].type == ARGTYPE_STRING_MULTISINGLE)) |
for(data = args->arg[i].data; data;) { |
temp = data; |
data = data->next; |
free(temp); |
} |
free(args); |
} |
void define_arg(struct args *args, int index, int type, char letter, char *longarg, void *def_value) |
{ |
args->arg[index].type = type; |
args->arg[index].letter = letter; |
args->arg[index].longarg = longarg; |
args->arg[index].data = def_value; |
} |
/* end of args.c */ |
/contrib/toolchain/avra/src/args.h |
---|
0,0 → 1,67 |
/*********************************************************************** |
* |
* avra - Assembler for the Atmel AVR microcontroller series |
* |
* Copyright (C) 1998-2006 Jon Anders Haugum, Tobias Weber |
* |
* This program is free software; you can redistribute it and/or modify |
* it under the terms of the GNU General Public License as published by |
* the Free Software Foundation; either version 2 of the License, or |
* (at your option) any later version. |
* |
* This program is distributed in the hope that it will be useful, |
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
* GNU General Public License for more details. |
* |
* You should have received a copy of the GNU General Public License |
* along with this program; see the file COPYING. If not, write to |
* the Free Software Foundation, Inc., 59 Temple Place - Suite 330, |
* Boston, MA 02111-1307, USA. |
* |
* |
* Authors of avra can be reached at: |
* email: jonah@omegav.ntnu.no, tobiw@suprafluid.com |
* www: http://sourceforge.net/projects/avra |
*/ |
#ifndef _args_h_ |
#define _args_h_ |
enum { |
ARGTYPE_BOOLEAN = 0, /* boolean Value (0 = False) */ |
ARGTYPE_STRING, /* Stringpointer in Data */ |
ARGTYPE_STRING_MULTI, /* List of strings in Data */ |
ARGTYPE_STRING_MULTISINGLE, /* List of strings in Data. requires an option for each element */ |
ARGTYPE_CHAR_ATTACHED |
}; |
#define GET_ARG(args, argnum) (args->arg[argnum].data) |
#define SET_ARG(args, argnum, value) (args->arg[argnum].data = (void *)value) |
struct args { |
struct arg *arg; |
int count; |
struct data_list *first_data; |
}; |
struct arg { |
int type; |
char letter; |
char *longarg; |
void *data; |
}; |
struct data_list { |
struct data_list *next; |
void *data; |
}; |
struct args *alloc_args(int arg_count); |
int read_args(struct args *args, int argc, char *argv[]); |
int add_arg(struct data_list **last_data, char *argv); |
void free_args(struct args *args); |
void define_arg(struct args *args, int index, int type, char letter, char *longarg, void *def_value); |
#endif /* end of args.h */ |
/contrib/toolchain/avra/src/avra.c |
---|
0,0 → 1,802 |
/*********************************************************************** |
* |
* avra - Assembler for the Atmel AVR microcontroller series |
* |
* Copyright (C) 1998-2006 Jon Anders Haugum, Tobias Weber |
* |
* This program is free software; you can redistribute it and/or modify |
* it under the terms of the GNU General Public License as published by |
* the Free Software Foundation; either version 2 of the License, or |
* (at your option) any later version. |
* |
* This program is distributed in the hope that it will be useful, |
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
* GNU General Public License for more details. |
* |
* You should have received a copy of the GNU General Public License |
* along with this program; see the file COPYING. If not, write to |
* the Free Software Foundation, Inc., 59 Temple Place - Suite 330, |
* Boston, MA 02111-1307, USA. |
* |
* |
* Authors of avra can be reached at: |
* email: jonah@omegav.ntnu.no, tobiw@suprafluid.com |
* www: http://sourceforge.net/projects/avra |
*/ |
#include <stdio.h> |
#include <stdlib.h> |
#include <stdarg.h> |
#include <string.h> |
#include "misc.h" |
#include "args.h" |
#include "avra.h" |
#include "device.h" |
#define debug 0 |
const char *title = |
"AVRA: advanced AVR macro assembler Version %i.%i.%i Build %i (%s)\n" |
"Copyright (C) 1998-2010. Check out README file for more info\n" |
"\n" |
" AVRA is an open source assembler for Atmel AVR microcontroller family\n" |
" It can be used as a replacement of 'AVRASM32.EXE' the original assembler\n" |
" shipped with AVR Studio. We do not guarantee full compatibility for avra.\n" |
"\n" |
" AVRA comes with NO WARRANTY, to the extent permitted by law.\n" |
" You may redistribute copies of avra under the terms\n" |
" of the GNU General Public License.\n" |
" For more information about these matters, see the files named COPYING.\n" |
"\n"; |
const char *usage = |
"usage: avra [-f][O|M|I|G] output file type\n" |
" [-o <filename>] output file name\n" |
" [-l <filename>] generate list file\n" |
" [-m <mapfile>] generate map file\n" |
"[--define <symbol>[=<value>]] [--includedir <dir>] [--listmac]\n" |
" [--max_errors <number>] [--devices] [--version]\n" |
" [-h] [--help] general help\n" |
" " |
" <file to assemble>\n" |
"\n" |
" --listfile -l : Create list file\n" |
" --mapfile -m : Create map file\n" |
" --define -D : Define symbol.\n" |
" --includepath -I : Additional include paths.\n" |
" --listmac : List macro expansion in listfile.\n" |
" --max_errors : Maximum number of errors before exit\n" |
" (default: 10)\n" |
" --devices : List out supported devices.\n" |
" --version : Version information.\n" |
" --help, -h : This help text.\n" |
"\n" |
"Just replace the AVRASM32.EXE with AVRA.EXE in your\n" |
"AVRStudio directories to avra's binary.\n"; |
int main(int argc, char *argv[]) |
{ |
int show_usage = False; |
struct prog_info *pi=NULL; |
struct args *args; |
unsigned char c; |
#if debug == 1 |
int i; |
for(i = 0; i < argc; i++) { |
printf(argv[i]); |
printf("\n"); |
} |
#endif |
printf(title, VER_MAJOR, VER_MINOR, VER_RELEASE, VER_BUILD, VER_DATE); |
args = alloc_args(ARG_COUNT); |
if(args) { |
define_arg(args, ARG_DEFINE, ARGTYPE_STRING_MULTISINGLE, 'D', "define", NULL); |
define_arg(args, ARG_INCLUDEPATH, ARGTYPE_STRING_MULTISINGLE, 'I', "includepath", NULL); |
define_arg(args, ARG_LISTMAC, ARGTYPE_BOOLEAN, 0, "listmac", "1"); |
define_arg(args, ARG_MAX_ERRORS, ARGTYPE_STRING, 0, "max_errors", "10"); |
define_arg(args, ARG_COFF, ARGTYPE_BOOLEAN, 0, "coff", NULL); |
define_arg(args, ARG_DEVICES, ARGTYPE_BOOLEAN, 0, "devices", NULL); |
define_arg(args, ARG_VER, ARGTYPE_BOOLEAN, 0, "version", NULL); |
define_arg(args, ARG_HELP, ARGTYPE_BOOLEAN, 'h', "help", NULL); |
define_arg(args, ARG_WRAP, ARGTYPE_BOOLEAN, 'w', "wrap", NULL); // Not implemented ? B.A. |
define_arg(args, ARG_WARNINGS, ARGTYPE_STRING_MULTISINGLE, 'W', "warn", NULL); |
define_arg(args, ARG_FILEFORMAT, ARGTYPE_CHAR_ATTACHED, 'f', "filetype", "0"); // Not implemented ? B.A. |
define_arg(args, ARG_LISTFILE, ARGTYPE_STRING, 'l', "listfile", NULL); |
define_arg(args, ARG_OUTFILE, ARGTYPE_STRING, 'o', "outfile", NULL); // Not implemented ? B.A. |
define_arg(args, ARG_MAPFILE, ARGTYPE_STRING, 'm', "mapfile", NULL); |
define_arg(args, ARG_DEBUGFILE, ARGTYPE_STRING, 'd', "debugfile", NULL); // Not implemented ? B.A. |
define_arg(args, ARG_EEPFILE, ARGTYPE_STRING, 'e', "eepfile", NULL); // Not implemented ? B.A. |
c = read_args(args, argc, argv); |
if(c != 0) { |
if(!GET_ARG(args, ARG_HELP) && (argc != 1)) { |
if(!GET_ARG(args, ARG_VER)) { |
if(!GET_ARG(args, ARG_DEVICES)) { |
pi = get_pi(args); |
if(pi) { |
get_rootpath(pi, args); /* get assembly root path */ |
if (assemble(pi) != 0) { /* the main assembly call */ |
exit(EXIT_FAILURE); |
} |
free_pi(pi); /* free all allocated memory */ |
} |
} |
else { |
list_devices(); /* list all supported devices */ |
} |
} |
} |
else |
show_usage = True; |
} |
free_args(args); |
} |
else { |
show_usage = True; |
printf("\n"); |
} |
if(show_usage) { |
printf("%s", usage); |
} |
exit(EXIT_SUCCESS); |
return (0); /* compiler warning, JEG 4-23-03 */ |
} |
void get_rootpath(struct prog_info *pi, struct args *args) |
{ |
int i; |
int j; |
char c; |
struct data_list *data; |
data = args->first_data; |
if(!data) |
return; |
while(data->next) data = ((data)->next); |
if (data != NULL) { |
i = strlen((char *)data->data); |
if (i > 0) { |
pi->root_path = malloc(i + 1); |
strcpy(pi->root_path,(char *)data->data); |
j = 0; |
do { |
c = pi->root_path[i]; |
if(c == '\\' || c == '/') { |
j = i + 1; |
break; |
} |
} while(i-- > 0); |
pi->root_path[j] = '\0'; |
return; |
} |
} |
pi->root_path = ""; |
} |
int assemble(struct prog_info *pi) { |
unsigned char c; |
if(pi->args->first_data) { |
printf("Pass 1...\n"); |
if(load_arg_defines(pi)==False) |
return -1; |
if(predef_dev(pi)==False) /* B.A.: Now with error check */ |
return -1; |
/*** FIRST PASS ***/ |
def_orglist(pi); /* B.A. : Store first active segment and seg_addr (Default : Code, Adr=0) */ |
c = parse_file(pi, (char *)pi->args->first_data->data); |
fix_orglist(pi); /* B.A. : Update last active segment */ |
test_orglist(pi); /* B.A.: Test for overlapping memory segments and out of chip space */ |
if(c != False) { |
#if debug == 1 |
printf("error_count = %i\n", pi->error_count); |
#endif |
/* B.A.: This part is obsolete. Now check is done in test_orglist() */ |
/* before we go to the 2nd pass, make sure used space is ok */ |
/* if(pi->eseg_count > pi->device->eeprom_size) { |
print_msg(pi, MSGTYPE_ERROR, |
"EEPROM space exceeded by %i bytes!", pi->eseg_count-pi->device->eeprom_size); |
return -1; |
} |
if(pi->cseg_count > pi->device->flash_size) { |
print_msg(pi, MSGTYPE_ERROR, |
"FLASH space exceeded by %i bytes!", pi->cseg_count-pi->device->flash_size); |
return -1; |
} */ |
/* if there are no furter errors, we can continue with 2nd pass */ |
if(pi->error_count == 0) { |
prepare_second_pass(pi); |
if(load_arg_defines(pi)==False) |
return -1; |
if(predef_dev(pi)==False) /* B.A.: Now with error check */ |
return -1; |
c = open_out_files(pi, pi->args->first_data->data); |
if(c != 0) { |
printf("Pass 2...\n"); |
parse_file(pi, (char *)pi->args->first_data->data); |
printf("done\n\n"); |
print_orglist(pi); /* B.A.: List used memory segments */ |
if(GET_ARG(pi->args, ARG_COFF) && (pi->error_count == 0)) { |
write_coff_file(pi); |
} |
write_map_file(pi); |
if(pi->error_count) { /* if there were errors */ |
printf("\nAssembly aborted with %d errors and %d warnings.\n", pi->error_count, pi->warning_count); |
unlink_out_files(pi, pi->args->first_data->data); |
} else { /* assembly was succesfull */ |
if(pi->warning_count) |
printf("\nAssembly complete with no errors (%d warnings).\n", pi->warning_count); |
else |
printf("\nAssembly complete with no errors.\n"); |
close_out_files(pi); |
} |
} |
} else { |
unlink_out_files(pi, pi->args->first_data->data); |
} |
} |
} else { |
printf("Error: You need to specify a file to assemble\n"); |
} |
return pi->error_count; |
} |
int load_arg_defines(struct prog_info *pi) |
{ |
int i; |
char *expr; |
char buff[256]; |
struct data_list *define; |
for(define = GET_ARG(pi->args, ARG_DEFINE); define; define = define->next) { |
strcpy(buff, define->data); |
expr = get_next_token( buff, TERM_EQUAL); |
if(expr) { |
// we reach this, when there is actually a value passed.. |
if(!get_expr(pi, expr, &i)) { |
return(False); |
} |
} else { |
// if user didnt specify a value, we default to 1 |
i = 1; |
} |
/* B.A. : New. Forward references allowed. But check, if everything is ok ... */ |
if(pi->pass==PASS_1) { /* Pass 1 */ |
if(test_constant(pi,buff,NULL)!=NULL) { |
fprintf(stderr,"Error: Can't define symbol %s twice\n", buff); |
return(False); |
} |
if(def_const(pi, buff, i)==False) |
return(False); |
} else { /* Pass 2 */ |
int j; |
if(get_constant(pi, buff, &j)==False) { /* Defined in Pass 1 and now missing ? */ |
fprintf(stderr,"Constant %s is missing in pass 2\n",buff); |
return(False); |
} |
if(i != j) { |
fprintf(stderr,"Constant %s changed value from %d in pass1 to %d in pass 2\n",buff,j,i); |
return(False); |
} |
/* OK. Definition is unchanged */ |
} |
} |
return(True); |
} |
/****************************************** |
* prog_info |
******************************************/ |
struct prog_info *get_pi(struct args *args) { |
struct prog_info *pi; |
struct data_list *warnings; |
pi = (struct prog_info *)calloc(1, sizeof(struct prog_info)); |
if(!pi) |
return(NULL); |
memset(pi, 0, sizeof(struct prog_info)); |
pi->args = args; |
pi->device = get_device(pi,NULL); |
if(GET_ARG(args, ARG_LISTFILE) == NULL) { |
pi->list_on = False; |
} else { |
pi->list_on = True; |
} |
if(GET_ARG(args, ARG_MAPFILE) == NULL) { |
pi->map_on = False; |
} else { |
pi->map_on = True; |
} |
for(warnings = GET_ARG(args, ARG_WARNINGS); warnings; warnings = warnings->next) { |
if(!nocase_strcmp(warnings->data, "NoRegDef")) |
pi->NoRegDef = 1; |
} |
pi->segment = SEGMENT_CODE; |
pi->dseg_addr = pi->device->ram_start; |
pi->max_errors = atoi(GET_ARG(args, ARG_MAX_ERRORS)); |
pi->pass=PASS_1; /* B.A. : The pass variable is now stored in the pi struct */ |
pi->time=time(NULL); /* B.A. : Now use a global timestamp */ |
return(pi); |
} |
void free_pi(struct prog_info *pi) { |
free_defs(pi); /* B.A. : Now free in pi included structures first */ |
free_labels(pi); |
free_constants(pi); |
free_variables(pi); |
free_blacklist(pi); |
free_orglist(pi); |
free(pi); |
} |
void prepare_second_pass(struct prog_info *pi) { |
pi->segment = SEGMENT_CODE; |
pi->cseg_addr = 0; |
pi->dseg_addr = pi->device->ram_start; |
pi->eseg_addr = 0; |
//pi->macro_nstlblnr = 0; |
pi->pass=PASS_2; /* B.A. : Change to pass 2. Now stored in pi struct. */ |
free_defs(pi); |
// free_constants(pi); /* B.A. : Now don't kill stored constants. We need them in the second pass now */ |
free_variables(pi); |
} |
void print_msg(struct prog_info *pi, int type, char *fmt, ... ) |
{ |
char *pc; |
if(type == MSGTYPE_OUT_OF_MEM) { |
fprintf(stderr, "Error: Unable to allocate memory!\n"); |
} else { |
if(type != MSGTYPE_APPEND) { /* B.A. Added for .message directive */ |
if((pi->fi != NULL) && (pi->fi->include_file->name != NULL)) { /* B.A.: Skip, if filename or fi is NULL (Bug 1462900) */ |
/* check if adding path name is needed*/ |
pc = strstr(pi->fi->include_file->name, pi->root_path); |
if(pc == NULL) { |
fprintf(stderr, "%s%s(%d) : ", pi->root_path ,pi->fi->include_file->name, pi->fi->line_number); |
} else { |
fprintf(stderr, "%s(%d) : ", pi->fi->include_file->name, pi->fi->line_number); |
} |
} |
} |
switch(type) { |
case MSGTYPE_ERROR: |
pi->error_count++; |
fprintf(stderr, "Error : "); |
break; |
case MSGTYPE_WARNING: |
pi->warning_count++; |
fprintf(stderr, "Warning : "); |
break; |
case MSGTYPE_MESSAGE: |
/* case MSGTYPE_MESSAGE_NO_LF: |
case MSGTYPE_APPEND: */ |
break; |
} |
if(type != MSGTYPE_APPEND) { /* B.A. Added for .message directive */ |
if(pi->macro_call) { |
fprintf(stderr, "[Macro: %s: %d:] ", pi->macro_call->macro->include_file->name, |
pi->macro_call->line_index + pi->macro_call->macro->first_line_number); |
} |
} |
if(fmt != NULL) { |
va_list args; |
+ va_end(args); |
+ } |
+ |
+ if( (type != MSGTYPE_APPEND) && (type != MSGTYPE_MESSAGE_NO_LF) ) /* B.A. Added for .message directive */ |
+ fprintf(stderr, "\n"); |
+ } |
+} |
+ |
+ |
+/* B.A. : New functions to create / search / remove constant, variables, labels */ |
+/* def_const, def_var moved from device.c to this place */ |
+int def_const(struct prog_info *pi, const char *name, int value) |
+{ |
+ struct label *label; |
+ label = malloc(sizeof(struct label)); |
+ if(!label) { |
+ print_msg(pi, MSGTYPE_OUT_OF_MEM, NULL); |
+ return(False); |
+ } |
+ label->next = NULL; |
+ if(pi->last_constant) |
+ pi->last_constant->next = label; |
+ else |
+ pi->first_constant = label; |
+ pi->last_constant = label; |
+ label->name = malloc(strlen(name) + 1); |
+ if(!label->name) { |
+ print_msg(pi, MSGTYPE_OUT_OF_MEM, NULL); |
+ return(False); |
+ } |
+ strcpy(label->name, name); |
+ label->value = value; |
+ return(True); |
+} |
+ |
+int def_var(struct prog_info *pi, char *name, int value) |
+{ |
+ struct label *label; |
+ |
+ for(label = pi->first_variable; label; label = label->next) |
+ if(!nocase_strcmp(label->name, name)) { |
+ label->value = value; |
+ return(True); |
+ } |
+ label = malloc(sizeof(struct label)); |
+ if(!label) { |
+ print_msg(pi, MSGTYPE_OUT_OF_MEM, NULL); |
+ return(False); |
+ } |
+ label->next = NULL; |
+ if(pi->last_variable) |
+ pi->last_variable->next = label; |
+ else |
+ pi->first_variable = label; |
+ pi->last_variable = label; |
+ label->name = malloc(strlen(name) + 1); |
+ if(!label->name) { |
+ print_msg(pi, MSGTYPE_OUT_OF_MEM, NULL); |
+ return(False); |
+ } |
+ strcpy(label->name, name); |
+ label->value = value; |
+ return(True); |
+} |
+ |
+ |
+int def_blacklist(struct prog_info *pi, const char *name) |
+{ |
+ struct label *label; |
+ label = malloc(sizeof(struct label)); |
+ if(!label) { |
+ print_msg(pi, MSGTYPE_OUT_OF_MEM, NULL); |
+ return(False); |
+ } |
+ label->next = NULL; |
+ if(pi->last_blacklist) |
+ pi->last_blacklist->next = label; |
+ else |
+ pi->first_blacklist = label; |
+ pi->last_blacklist = label; |
+ label->name = malloc(strlen(name) + 1); |
+ if(!label->name) { |
+ print_msg(pi, MSGTYPE_OUT_OF_MEM, NULL); |
+ return(False); |
+ } |
+ strcpy(label->name, name); |
+ label->value = 0; |
+ return(True); |
+} |
+ |
+/* B.A.: Store programmed areas for later check */ |
+int def_orglist(struct prog_info *pi) |
+{ |
+ struct orglist *orglist; |
+ if(pi->pass != PASS_1) |
+ return(True); |
+ orglist = malloc(sizeof(struct orglist)); |
+ if(!orglist) { |
+ print_msg(pi, MSGTYPE_OUT_OF_MEM, NULL); |
+ return(False); |
+ } |
+ orglist->next = NULL; |
+ if(pi->last_orglist) |
+ pi->last_orglist->next = orglist; |
+ else |
+ pi->first_orglist = orglist; |
+ pi->last_orglist = orglist; |
+ orglist->segment=pi->segment; |
+ switch(pi->segment) { |
+ case SEGMENT_CODE: |
+ orglist->start = pi->cseg_addr; |
+ break; |
+ case SEGMENT_DATA: |
+ orglist->start = pi->dseg_addr; |
+ break; |
+ case SEGMENT_EEPROM: |
+ orglist->start = pi->eseg_addr; |
+ } |
+ orglist->length=0; |
+ return(True); |
+} |
+ |
+/* B.A.: Fill length entry of last orglist */ |
+int fix_orglist(struct prog_info *pi) |
+{ |
+ if(pi->pass != PASS_1) |
+ return(True); |
+ if((pi->last_orglist == NULL) || (pi->last_orglist->length!=0)) { |
+ fprintf(stderr,"Internal Error: fix_orglist\n"); |
+ return(False); |
+ } |
+ pi->last_orglist->segment=pi->segment; |
+ switch(pi->segment) { |
+ case SEGMENT_CODE: |
+ pi->last_orglist->length = pi->cseg_addr - pi->last_orglist->start; |
+ break; |
+ case SEGMENT_DATA: |
+ pi->last_orglist->length = pi->dseg_addr - pi->last_orglist->start; |
+ break; |
+ case SEGMENT_EEPROM: |
+ pi->last_orglist->length = pi->eseg_addr - pi->last_orglist->start; |
+ } |
+ return(True); |
+} |
+ |
+/* B.A.: Debug output of orglist */ |
+void print_orglist(struct prog_info *pi) |
+{ |
+ struct orglist *orglist=pi->first_orglist; |
+ printf("Used memory blocks:\n"); |
+ while(orglist!=NULL) { |
+ if(orglist->length) { /* Skip blocks with size == 0 */ |
+ switch(orglist->segment) { |
+ case SEGMENT_CODE: |
+ printf(" Code "); break; |
+ case SEGMENT_DATA: |
+ printf(" Data "); break; |
+ case SEGMENT_EEPROM: |
+ printf(" EEPROM"); break; |
+ printf("INVALID SEGMENT DATA !\n"); |
+ } |
+ printf(" : Start = 0x%04X, End = 0x%04X, Length = 0x%04X\n", |
+ orglist->start,orglist->start+orglist->length-1,orglist->length); |
+ } |
+ orglist=orglist->next; |
+ } |
+} |
+ |
+/* B.A.: Test for overlapping segments and device space */ |
+int test_orglist(struct prog_info *pi) |
+{ |
+ struct orglist *orglist2,*orglist=pi->first_orglist; |
+ int error_count=0; |
+ if(pi->device->name==NULL) { |
+ fprintf(stderr,"Warning : No .DEVICE definition found. Cannot make useful address range check !\n"); |
+ pi->warning_count++; |
+ } |
+ while(orglist!=NULL) { |
+ if(orglist->length) { /* Skip blocks with size == 0 */ |
+ // printf("Segment %d, Start = %5d, Length = %5d\n",orglist->segment,orglist->start,orglist->length); |
+ /* Make sure address area is valid */ |
+ switch(orglist->segment) { |
+ case SEGMENT_CODE: |
+ if((orglist->start + orglist->length) > pi->device->flash_size) { |
+ fprintf(stderr,"Code segment exceeds valid address range [0..0x%04X] :", |
+ pi->device->flash_size-1); |
+ fprintf(stderr," Start = 0x%04X, End = 0x%04X, Length = 0x%04X\n", |
+ orglist->start,orglist->start+orglist->length-1,orglist->length); |
+ error_count++; |
+ } |
+ break; |
+ case SEGMENT_DATA: |
+ if(pi->device->ram_size == 0) { |
+ // Error message is generated in .DSEG directive. Skip ... |
+ // fprintf(stderr,"This device has no RAM. Don't use .DSEG \n"); |
+ // error_count++; |
+ break; |
+ } // Fix bug 1742436. Added missing pi->device->ram_start |
+ if(((orglist->start + orglist->length) > (pi->device->ram_size + pi->device->ram_start)) || |
+ (orglist->start < pi->device->ram_start)) { |
+ fprintf(stderr,"Data segment exceeds valid address range [0x%04X..0x%04X] :", |
+ pi->device->ram_start,pi->device->ram_start+pi->device->ram_size-1); |
+ fprintf(stderr," Start = 0x%04X, End = 0x%04X, Length = 0x%04X\n", |
+ orglist->start,orglist->start+orglist->length-1,orglist->length); |
+ error_count++; |
+ } |
+ break; |
+ case SEGMENT_EEPROM: // Fix bug 1742437 : replace ram_size by eeprom_size |
+ if(pi->device->eeprom_size == 0) { |
+ // Error message is generated in .ESEG directive. Skip ... |
+ // fprintf(stderr,"This device has no EEPROM. Don't use .ESEG !\n"); |
+ // error_count++; |
+ break; |
+ } |
+ if((orglist->start + orglist->length) > pi->device->eeprom_size) { |
+ fprintf(stderr,"EEPROM segment exceeds valid address range [0..0x%04X] :", |
+ pi->device->eeprom_size-1); |
+ fprintf(stderr," Start = 0x%04X, End = 0x%04X, Length = 0x%04X\n", |
+ orglist->start,orglist->start+orglist->length-1,orglist->length); |
+ error_count++; |
+ } |
+ break; |
+ } |
+ /* Overlap-test */ |
+ orglist2=orglist->next; |
+ while(orglist2!=NULL) { |
+ if((orglist != orglist2) && (orglist2->length) && (orglist->segment == orglist2->segment)) { |
+ // printf("<> Segment %d, Start = %5d, Length = %5d\n",orglist2->segment,orglist2->start,orglist2->length); |
+ if((orglist->start < (orglist2->start + orglist2->length)) && |
+ (orglist2->start < ( orglist->start + orglist->length))) { |
+ fprintf(stderr,"Error: Overlapping "); |
+ switch(orglist->segment) { |
+ case SEGMENT_CODE: |
+ fprintf(stderr,"Code"); break; |
+ case SEGMENT_DATA: |
+ fprintf(stderr,"Data"); break; |
+ case SEGMENT_EEPROM: |
+ fprintf(stderr,"EEPROM"); break; |
+ } |
+ fprintf(stderr,"-segments :\n"); |
+ fprintf(stderr," Start = 0x%04X, End = 0x%04X, Length = 0x%04X\n", |
+ orglist->start,orglist->start+orglist->length-1,orglist->length); |
+ fprintf(stderr," Start = 0x%04X, End = 0x%04X, Length = 0x%04X\n", |
+ orglist2->start,orglist2->start+orglist2->length-1,orglist2->length); |
+ fprintf(stderr,"Please check your .ORG directives !\n"); |
+ error_count++; |
+ } |
+ } |
+ orglist2=orglist2->next; |
+ } |
+ } |
+ orglist=orglist->next; |
+ } |
+ if(!error_count) |
+ return(True); |
+ pi->error_count+=error_count; |
+ return(False); |
+} |
+ |
+ |
+ |
+/* Get the value of a label. Return FALSE if label was not found */ |
+int get_label(struct prog_info *pi,char *name,int *value) |
+{ |
+ struct label *label=search_symbol(pi,pi->first_label,name,NULL); |
+ if(label==NULL) return False; |
+ if(value!=NULL) *value=label->value; |
+ return True; |
+} |
+ |
+int get_constant(struct prog_info *pi,char *name,int *value) |
+{ |
+ struct label *label=search_symbol(pi,pi->first_constant,name,NULL); |
+ if(label==NULL) return False; |
+ if(value!=NULL) *value=label->value; |
+ return True; |
+} |
+ |
+int get_variable(struct prog_info *pi,char *name,int *value) |
+{ |
+ struct label *label=search_symbol(pi,pi->first_variable,name,NULL); |
+ if(label==NULL) return False; |
+ if(value!=NULL) *value=label->value; |
+ return True; |
+} |
+ |
+/* Test, if label exists. Return NULL -> not defined, else return the pointer to label struct */ |
+/* If message != NULL print error message if symbol is defined */ |
+struct label *test_label(struct prog_info *pi,char *name,char *message) |
+{ |
+ return search_symbol(pi,pi->first_label,name,message); |
+} |
+ |
+struct label *test_constant(struct prog_info *pi,char *name,char *message) |
+{ |
+ return search_symbol(pi,pi->first_constant,name,message); |
+} |
+ |
+struct label *test_variable(struct prog_info *pi,char *name,char *message) |
+{ |
+ return search_symbol(pi,pi->first_variable,name,message); |
+} |
+ |
+struct label *test_blacklist(struct prog_info *pi,char *name,char *message) |
+{ |
+ return search_symbol(pi,pi->first_blacklist,name,message); |
+} |
+ |
+/* Search in label,constant,variable,blacklist - list for a matching entry */ |
+/* Use first = pi->first_label,first_constant,first_variable,first_blacklist to select list */ |
+/* If message != NULL Print error message if symbol is defined */ |
+struct label *search_symbol(struct prog_info *pi,struct label *first,char *name,char *message) |
+{ |
+ struct label *label; |
+ for(label = first; label; label = label->next) |
+ if(!nocase_strcmp(label->name, name)) { |
+ if(message) { |
+ print_msg(pi, MSGTYPE_ERROR, message, name); |
+ } |
+ return(label); |
+ } |
+ return(NULL); |
+} |
+ |
+ |
+void free_defs(struct prog_info *pi) |
+{ |
+ struct def *def, *temp_def; |
+ for(def = pi->first_def; def;) { |
+ temp_def = def; |
+ def = def->next; |
+ free(temp_def->name); |
+ free(temp_def); |
+ } |
+ pi->first_def = NULL; |
+ pi->last_def = NULL; |
+} |
+ |
+void free_labels(struct prog_info *pi) |
+{ |
+ struct label *label, *temp_label; |
+ for(label = pi->first_label; label;) { |
+ temp_label = label; |
+ label = label->next; |
+ free(temp_label->name); |
+ free(temp_label); |
+ } |
+ pi->first_label = NULL; |
+ pi->last_label = NULL; |
+} |
+ |
+void free_constants(struct prog_info *pi) |
+{ |
+ struct label *label, *temp_label; |
+ for(label = pi->first_constant; label;) { |
+ temp_label = label; |
+ label = label->next; |
+ free(temp_label->name); |
+ free(temp_label); |
+ } |
+ pi->first_constant = NULL; |
+ pi->last_constant = NULL; |
+} |
+ |
+void free_blacklist(struct prog_info *pi) |
+{ |
+ struct label *label, *temp_label; |
+ for(label = pi->first_blacklist; label;) { |
+ temp_label = label; |
+ label = label->next; |
+ free(temp_label->name); |
+ free(temp_label); |
+ } |
+ pi->first_blacklist = NULL; |
+ pi->last_blacklist = NULL; |
+} |
+ |
+void free_variables(struct prog_info *pi) |
+{ |
+ struct label *label, *temp_label; |
+ for(label = pi->first_variable; label;) { |
+ temp_label = label; |
+ label = label->next; |
+ free(temp_label->name); |
+ free(temp_label); |
+ } |
+ pi->first_variable = NULL; |
+ pi->last_variable = NULL; |
+} |
+ |
+void free_orglist(struct prog_info *pi) |
+{ |
+ struct orglist *orglist, *temp_orglist; |
+ for(orglist = pi->first_orglist; orglist;) { |
+ temp_orglist = orglist; |
+ orglist = orglist->next; |
+ free(temp_orglist); |
+ } |
+ pi->first_orglist = NULL; |
+ pi->last_orglist = NULL; |
+} |
+ |
+ |
+/* avra.c */ |
+ |
/contrib/toolchain/avra/src/avra.h |
---|
0,0 → 1,370 |
/*********************************************************************** |
* |
* avra - Assembler for the Atmel AVR microcontroller series |
* |
* Copyright (C) 1998-2006 Jon Anders Haugum, Tobias Weber |
* |
* This program is free software; you can redistribute it and/or modify |
* it under the terms of the GNU General Public License as published by |
* the Free Software Foundation; either version 2 of the License, or |
* (at your option) any later version. |
* |
* This program is distributed in the hope that it will be useful, |
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
* GNU General Public License for more details. |
* |
* You should have received a copy of the GNU General Public License |
* along with this program; see the file COPYING. If not, write to |
* the Free Software Foundation, Inc., 59 Temple Place - Suite 330, |
* Boston, MA 02111-1307, USA. |
* |
* |
* Authors of avra can be reached at: |
* email: jonah@omegav.ntnu.no, tobiw@suprafluid.com |
* www: http://sourceforge.net/projects/avra |
*/ |
#ifndef _AVRA_H_ /* avoid multiple inclusion */ |
#define _AVRA_H_ |
#include <stdio.h> |
#include <time.h> |
#ifndef VER_MAJOR |
# define VER_MAJOR 1 |
#endif |
#ifndef VER_MINOR |
# define VER_MINOR 3 |
#endif |
#ifndef VER_RELEASE |
# define VER_RELEASE 0 |
#endif |
#ifndef VER_BUILD |
# define VER_BUILD 1 |
#endif |
#ifndef VER_DATE |
# define VER_DATE "8 May 2010" |
#endif |
#define IS_HOR_SPACE(x) ((x == ' ') || (x == 9)) |
#define IS_LABEL(x) (isalnum(x) || (x == '%') || (x == '_')) |
#define IS_END_OR_COMMENT(x) ((x == ';') || (x == 10) || (x == 13) || (x == '\0') || (x == 12)) |
#define IS_ENDLINE(x) ((x == 10) || (x == 13) || (x == '\0') || (x == 12)) |
#define IS_SEPARATOR(x) ((x == ' ') || (x == ',') || (x == '[') || (x == ']')) |
#define LINEBUFFER_LENGTH 256 |
#define MAX_NESTED_MACROLOOPS 256 |
#define MAX_MACRO_ARGS 10 |
/* warning switches */ |
/* Option enumeration */ |
enum { |
ARG_DEFINE = 0, /* --define, -D */ |
ARG_INCLUDEPATH, /* --includedir, -I */ |
ARG_LISTMAC, /* --listmac */ |
ARG_MAX_ERRORS, /* --max_errors */ |
ARG_COFF, /* --coff */ |
ARG_DEVICES, /* --devices */ |
ARG_VER, /* --version */ |
ARG_HELP, /* --help, -h */ |
ARG_WRAP, /* --wrap */ |
ARG_WARNINGS, /* --warn, -W */ |
ARG_FILEFORMAT, /* --filetype */ |
ARG_LISTFILE, /* --listfile */ |
ARG_OUTFILE, /* --outfile */ |
ARG_MAPFILE, /* --mapfile */ |
ARG_DEBUGFILE, /* --debugfile */ |
ARG_EEPFILE, /* --eepfile */ |
ARG_COUNT |
}; |
enum { |
MSGTYPE_ERROR = 0, |
MSGTYPE_WARNING, |
MSGTYPE_MESSAGE, |
MSGTYPE_OUT_OF_MEM, |
MSGTYPE_MESSAGE_NO_LF, /* B.A. : Like MSGTYPE_MESSAGE, but without /n */ |
MSGTYPE_APPEND /* B.A. : Print Message without any header and without /n. To append messages */ |
/* MSGTYPE_INCLUDE B.A. Removed. Was not in used */ |
}; |
enum { |
PASS_1 = 0, |
PASS_2 |
}; |
enum { |
SEGMENT_CODE = 0, |
SEGMENT_DATA, |
SEGMENT_EEPROM |
}; |
enum { |
TERM_END = 0, |
TERM_SPACE, |
TERM_COMMA, |
TERM_EQUAL, |
TERM_DASH, |
TERM_DOUBLEQUOTE, |
TERM_COLON |
}; |
/* Structures */ |
struct prog_info |
{ |
struct args *args; |
struct device *device; |
struct file_info *fi; |
struct macro_call *macro_call; |
struct macro_line *macro_line; |
FILE *list_file; |
int list_on; |
int map_on; |
char *list_line; |
char *root_path; |
FILE *obj_file; |
struct hex_file_info *hfi; |
struct hex_file_info *eep_hfi; |
int segment; |
int cseg_addr; |
int dseg_addr; |
int eseg_addr; |
int cseg_count; |
int dseg_count; |
int eseg_count; |
int error_count; |
int max_errors; |
int warning_count; |
struct include_file *last_include_file; |
struct include_file *first_include_file; |
struct def *first_def; |
struct def *last_def; |
struct label *first_label; |
struct label *last_label; |
struct label *first_constant; |
struct label *last_constant; |
struct label *first_variable; |
struct label *last_variable; |
struct label *first_blacklist; /* B.A. : List for undefined symbols. Needed to make forward references safe */ |
struct label *last_blacklist; |
struct macro *first_macro; |
struct macro *last_macro; |
struct macro_call *first_macro_call; |
struct macro_call *last_macro_call; |
struct orglist *first_orglist; /* B.A. : List of used memory segments. Needed for overlap-check */ |
struct orglist *last_orglist; |
int conditional_depth; |
time_t time; /* B.A. : Use a global timestamp for listing header and %hour% ... tags */ |
/* coff additions */ |
FILE *coff_file; |
/* Warning additions */ |
int NoRegDef; |
int pass; |
}; |
struct file_info |
{ |
FILE *fp; |
struct include_file *include_file; |
char buff[LINEBUFFER_LENGTH]; |
char scratch[LINEBUFFER_LENGTH]; |
int line_number; |
int exit_file; |
struct label *label; |
}; |
struct hex_file_info |
{ |
FILE *fp; |
int count; |
int linestart_addr; |
int segment; |
unsigned char hex_line[16]; |
}; |
struct include_file |
{ |
struct include_file *next; |
char *name; |
int num; |
}; |
struct def |
{ |
struct def *next; |
char *name; |
int reg; |
}; |
struct label |
{ |
struct label *next; |
char *name; |
int value; |
}; |
struct macro |
{ |
struct macro *next; |
char *name; |
struct include_file *include_file; |
int first_line_number; |
struct macro_line *first_macro_line; |
struct macro_label *first_label; |
}; |
struct macro_label |
{ |
char *label; |
struct macro_label *next; |
int running_number; |
}; |
struct macro_line |
{ |
struct macro_line *next; |
char *line; |
}; |
struct macro_call |
{ |
struct macro_call *next; |
int line_number; |
struct include_file *include_file; |
struct macro_call *prev_on_stack; |
struct macro *macro; |
int line_index; |
int prev_line_index; |
int nest_level; |
struct label *first_label; |
struct label *last_label; |
}; |
struct orglist |
{ |
struct orglist *next; |
int segment; |
int start; |
int length; |
}; |
/* Prototypes */ |
/* avra.c */ |
int assemble(struct prog_info *pi); |
int load_arg_defines(struct prog_info *pi); |
struct prog_info *get_pi(struct args *args); |
void free_pi(struct prog_info *pi); |
void prepare_second_pass(struct prog_info *pi); |
void print_msg(struct prog_info *pi, int type, char *fmt, ... ); |
void get_rootpath(struct prog_info *pi, struct args *args); |
int def_const(struct prog_info *pi, const char *name, int value); |
int def_var(struct prog_info *pi, char *name, int value); |
int def_blacklist(struct prog_info *pi, const char *name); |
int def_orglist(struct prog_info *pi); /* B.A. : Test for overlapping segments */ |
int fix_orglist(struct prog_info *pi); |
void print_orglist(struct prog_info *pi); |
int test_orglist(struct prog_info *pi); |
int get_label(struct prog_info *pi,char *name,int *value); |
int get_constant(struct prog_info *pi,char *name,int *value); |
int get_variable(struct prog_info *pi,char *name,int *value); |
struct label *test_label(struct prog_info *pi,char *name,char *message); |
struct label *test_constant(struct prog_info *pi,char *name,char *message); |
struct label *test_variable(struct prog_info *pi,char *name,char *message); |
struct label *test_blacklist(struct prog_info *pi,char *name,char *message); |
struct label *search_symbol(struct prog_info *pi,struct label *first,char *name,char *message); |
void free_defs(struct prog_info *pi); |
void free_labels(struct prog_info *pi); |
void free_constants(struct prog_info *pi); |
void free_blacklist(struct prog_info *pi); |
void free_variables(struct prog_info *pi); |
void free_orglist(struct prog_info *pi); |
/* parser.c */ |
int parse_file(struct prog_info *pi, char *filename); |
int parse_line(struct prog_info *pi, char *line); |
char *get_next_token(char *scratch, int term); |
char *fgets_new(struct prog_info *pi, char *s, int size, FILE *stream); |
/* expr.c */ |
int get_expr(struct prog_info *pi, char *data, int *value); |
//int get_operator(char *op); |
//int test_operator_at_precedence(int operator, int precedence); |
//int calc(struct prog_info *pi, int left, int operator, int right); |
//int get_function(char *function); |
//int do_function(int function, int value); |
//int log2(int value); |
int get_symbol(struct prog_info *pi, char *label_name, int *data); |
int par_length(char *data); |
/* mnemonic.c */ |
int parse_mnemonic(struct prog_info *pi); |
int get_mnemonic_type(char *mnemonic); |
int get_register(struct prog_info *pi, char *data); |
int get_bitnum(struct prog_info *pi, char *data, int *ret); |
int get_indirect(struct prog_info *pi, char *operand); |
int is_supported(struct prog_info *pi, char *name); |
int count_supported_instructions(int flags); |
/* directiv.c */ |
int parse_directive(struct prog_info *pi); |
int get_directive_type(char *directive); |
char *term_string(struct prog_info *pi, char *string); |
int parse_db(struct prog_info *pi, char *next); |
void write_db(struct prog_info *pi, char byte, char *prev, int count); |
int spool_conditional(struct prog_info *pi, int only_endif); |
int check_conditional(struct prog_info *pi, char *buff, int *current_depth, int *do_next, int only_endif); |
int test_include(const char *filename); |
/* macro.c */ |
int read_macro(struct prog_info *pi, char *name); |
struct macro *get_macro(struct prog_info *pi, char *name); |
struct macro_label *get_macro_label(char *line, struct macro *macro); |
int expand_macro(struct prog_info *pi, struct macro *macro, char *rest_line); |
/* file.c */ |
int open_out_files(struct prog_info *pi, char *filename); |
void close_out_files(struct prog_info *pi); |
struct hex_file_info *open_hex_file(char *filename); |
void close_hex_file(struct hex_file_info *hfi); |
void write_ee_byte(struct prog_info *pi, int address, unsigned char data); |
void write_prog_word(struct prog_info *pi, int address, int data); |
void do_hex_line(struct hex_file_info *hfi); |
FILE *open_obj_file(struct prog_info *pi, char *filename); |
void close_obj_file(struct prog_info *pi, FILE *fp); |
void write_obj_record(struct prog_info *pi, int address, int data); |
void unlink_out_files(struct prog_info *pi, char *filename); |
/* map.c */ |
void write_map_file(struct prog_info *pi); |
char *Space(char *n); |
/* stdextra.c */ |
char *nocase_strcmp(char *s, char *t); |
char *nocase_strncmp(char *s, char *t, int n); |
char *nocase_strstr(char *s, char *t); |
int atox(char *s); |
int atoi_n(char *s, int n); |
int atox_n(char *s, int n); |
char *my_strlwr(char *in); |
char *my_strupr(char *in); |
/* coff.c */ |
FILE *open_coff_file(struct prog_info *pi, char *filename); |
void write_coff_file(struct prog_info *pi); |
void write_coff_eeprom( struct prog_info *pi, int address, unsigned char data); |
void write_coff_program( struct prog_info *pi, int address, unsigned int data); |
void close_coff_file(struct prog_info *pi, FILE *fp); |
int parse_stabs( struct prog_info *pi, char *p ); |
int parse_stabn( struct prog_info *pi, char *p ); |
#endif /* end of avra.h */ |
/contrib/toolchain/avra/src/coff.c |
---|
0,0 → 1,2089 |
/*********************************************************************** |
* |
* avra - Assembler for the Atmel AVR microcontroller series |
* |
* Copyright (C) 1998-2004 Jon Anders Haugum, Tobias Weber |
* |
* coff.c - Common Object File Format (COFF) support |
* |
* This file was developed for the avra assembler in order to produce COFF output files |
* for use with the Atmel AVR Studio. The Lean C Compiler (LCC) debugging stabs |
* output was used as input to the assembler. The information used to develop this file |
* was obtained from various sources on the Internet, most notably, the Free Software Foundation, |
* The "stabs" debug format, ??? Chapter 7: Common Object File Format (COFF), |
* |
* This software has absolutely no warrantee! The money you paid for this will be |
* promptly refunded if not fully satisfied. |
* |
* Beta release 1/20/2000 by Bob Harris |
* |
* This software has not been fully tested and probably has a few software deficiencies. |
* Some software support may be possible by sending a problem description report to |
* rth@mclean.sparta.com |
* |
* Made the recommended change in write_coff_program(). |
* Fixed an obvious typo in SkipPastDigits(). The if() statement was terminated |
* with a semicolon, which terminated the if(); early. JEG 4-01-03 |
*/ |
#include <stdio.h> |
#include <stdlib.h> |
#include <string.h> |
#include <ctype.h> |
#include <time.h> |
#include "misc.h" |
#include "avra.h" |
#include "args.h" |
#include "coff.h" |
#include "device.h" /* device flash and eeprom size */ |
struct FundamentalType { |
char const *pString; |
int Type; |
int Size; |
}; |
struct FundamentalType FundamentalTypes[] = { |
{"null", T_NULL, 0}, |
{"void", T_VOID, 0}, |
{"char", T_CHAR, 1}, |
{"short", T_SHORT, 1}, |
{"int", T_INT, 1}, |
{"long", T_LONG, 2}, |
{"float", T_FLOAT, 4}, |
{"double", T_DOUBLE, 4}, |
{"struct", T_STRUCT, 0}, |
{"union", T_UNION, 0}, |
{"enum", T_ENUM, 0}, |
{"moe", T_MOE, 0}, |
{"unsigned char", T_UCHAR, 1}, |
{"unsigned short", T_USHORT, 1}, |
{"unsigned int", T_UINT, 1}, |
{"unsigned long", T_ULONG, 2}, |
{"long double", T_LNGDBL, 2}, |
{"long long int", T_LONG, 2}, |
{"long int", T_LONG, 2}, |
{"unsigned long long", T_ULONG, 2}, |
{"signed char", T_CHAR, 1}, |
{0, 0} |
}; |
struct coff_info *ci; |
/****************************************************************************************/ |
FILE *open_coff_file(struct prog_info *pi, char *filename){ |
int ok /*, i*/; |
FILE *fp; |
//unsigned long *pu4; |
char*p; |
ci = calloc( 1, sizeof(struct coff_info) ); |
if ( !ci ) |
return( 0 ); |
ok = True; |
/* default values */ |
ci->CurrentFileNumber = 0; |
ci->pRomMemory = 0; |
ci->pEEPRomMemory = 0; |
ci->MaxRomAddress = 0; |
ci->MaxEepromAddress = 0; |
ci->NeedLineNumberFixup = 0; |
ci->GlobalStartAddress = -1; |
ci->GlobalEndAddress = 0; |
/* Linked lists start out at zero */ |
InitializeList( &ci->ListOfSectionHeaders ); |
InitializeList( &ci->ListOfRawData ); |
InitializeList( &ci->ListOfRelocations ); |
InitializeList( &ci->ListOfLineNumbers ); |
InitializeList( &ci->ListOfSymbols ); |
InitializeList( &ci->ListOfGlobals ); |
InitializeList( &ci->ListOfSpecials ); |
InitializeList( &ci->ListOfUndefined ); |
InitializeList( &ci->ListOfStrings ); |
InitializeList( &ci->ListOfTypes ); |
InitializeList( &ci->ListOfSplitLines ); |
/* add two default sections to SectionHeaders */ |
if ( !AllocateListObject( &ci->ListOfSectionHeaders, sizeof(struct external_scnhdr) ) || |
!AllocateListObject( &ci->ListOfSectionHeaders, sizeof(struct external_scnhdr) ) ) { |
fprintf(stderr, "\nOut of memory allocating section headers!"); |
return( 0 ); |
} |
/* add to string table */ |
p = (char *)AllocateListObject( &ci->ListOfStrings, 4 ); |
if ( !p ) { |
fprintf(stderr, "\nOut of memory allocating string table space!"); |
return( 0 ); |
} |
/* Allocate space for binary output into ROM, and EEPROM memory buffers for COFF output */ |
/* ASSUMES ci->device is accurate */ |
if ( (ci->pRomMemory = AllocateListObject( &ci->ListOfRawData, pi->device->flash_size * 2 ) ) != 0) { |
if ( (ci->pEEPRomMemory = AllocateListObject( &ci->ListOfRawData, pi->device->eeprom_size )) != 0) { |
ok = True; /* only true if both buffers are properly allocated */ |
/* now fill them with 0xff's to simulate flash erasure */ |
memset( (void *)ci->pRomMemory, 0xff, pi->device->flash_size * 2 ); |
memset( ( void *)ci->pEEPRomMemory, 0xff, pi->device->eeprom_size ); |
} |
} |
if ( ok != True ) |
return( 0 ); |
fp = fopen(filename,"wb"); |
if ( fp == NULL ) { |
fprintf(stderr,"Error: cannot write coff file\n"); |
return( fp ); |
} |
/* simulate void type .stabs void:t15=r1;*/ |
stab_add_local_type( "void", "15=r1;0;0;" ); |
return( fp ); |
} |
/****************************************************************************************/ |
void write_coff_file(struct prog_info *pi){ |
//FILE *fp; |
//struct label *label; |
char /* File[256],*/*p; |
struct external_scnhdr *pSectionHdr; |
struct syment *pEntry; |
union auxent *pAux; |
unsigned long *plong; |
int NumberOfSymbols, SymbolIndex, LastFileIndex, LastFunctionIndex, LastFunctionAddress; |
LISTNODE *pNode; |
int LinesOffset, SymbolsOffset, StringsOffset, RawOffset; |
struct lineno *pLine; |
/* add two special sections */ |
/* one for .text */ |
if ( ( pEntry = (struct syment*)AllocateTwoListObjects( &ci->ListOfSpecials, sizeof(struct syment) * 2 ) ) == 0 ) { |
fprintf(stderr, "\nOut of memory allocating special headers for .text!"); |
return; |
} |
memset( pEntry->n_name, 0, 8 ); |
strcpy( pEntry->n_name, ".text" ); |
pEntry->n_value = 0; |
pEntry->n_scnum = 1; |
pEntry->n_type = 0; |
pEntry->n_sclass = C_STAT; |
pEntry->n_numaux = 1; |
pEntry++; |
pAux = (union auxent *)pEntry; |
pAux->x_scn.x_scnlen = ci->MaxRomAddress + 2; |
pAux->x_scn.x_nreloc = 0; |
pAux->x_scn.x_nlinno = ci->ListOfLineNumbers.TotalItems; |
/* one for .bss */ |
if ( ( pEntry = (struct syment*)AllocateTwoListObjects( &ci->ListOfSpecials, sizeof(struct syment) * 2 ) ) == 0 ) { |
fprintf(stderr, "\nOut of memory allocating special header for .bss!"); |
return; |
} |
memset( pEntry->n_name, 0, 8 ); |
strcpy( pEntry->n_name, ".bss" ); |
if ( ci->GlobalStartAddress == -1 ) { |
ci->GlobalEndAddress = ci->GlobalStartAddress = 0x60; |
} |
pEntry->n_value = ci->GlobalStartAddress; |
pEntry->n_scnum = 2; |
pEntry->n_type = 0; |
pEntry->n_sclass = C_STAT; |
pEntry->n_numaux = 1; |
pEntry++; |
pAux = (union auxent *)pEntry; |
pAux->x_scn.x_scnlen = 0; /* we don't store any data here */ |
pAux->x_scn.x_nreloc = 0; |
pAux->x_scn.x_nlinno = 0; |
/* one more for .data - eeprom ??? */ |
/* Calculate common offsets into the file */ |
RawOffset = sizeof(struct external_filehdr) + ci->ListOfSectionHeaders.TotalBytes; |
LinesOffset = RawOffset + ci->MaxRomAddress + 2; /* ignore eeprom for now */ |
SymbolsOffset = LinesOffset + ci->ListOfLineNumbers.TotalBytes; |
StringsOffset = SymbolsOffset + ci->ListOfSymbols.TotalBytes + ci->ListOfSpecials.TotalBytes + ci->ListOfGlobals.TotalBytes; |
/* Clean up loose ends in string table */ |
if ( !(plong = (unsigned long *)FindFirstListObject(&ci->ListOfStrings)) ) { |
fprintf(stderr,"\nInternal error in string table!"); |
return; |
} |
*plong = ci->ListOfStrings.TotalBytes; /* Size of string table */ |
/* Clean up loose ends in symbol table */ |
/* symbol table - Filename value - index to next .file or global symbol */ |
/* The value of that symbol equals the symbol table entry index of the next .file symbol or .global */ |
LastFunctionAddress = ci->MaxRomAddress; |
NumberOfSymbols = ci->ListOfSymbols.TotalItems + ci->ListOfSpecials.TotalItems + ci->ListOfGlobals.TotalItems; |
SymbolIndex = LastFileIndex = NumberOfSymbols; |
LastFunctionIndex = 0; /* set to zero on last function */ |
for ( pEntry = (struct syment *)FindLastListObject(&ci->ListOfSymbols); |
pEntry != 0; |
pEntry = (struct syment *)FindNextLastListObject(&ci->ListOfSymbols) ) { |
/* Search for .file entries designated by C_FILE */ |
if ( pEntry->n_sclass == C_FILE ) { |
pEntry->n_value = LastFileIndex; |
LastFileIndex = SymbolIndex; /* save current index */ |
} |
/* Search for Function entries C_EXT */ |
else if ( pEntry->n_sclass == C_EXT ) { |
pEntry++; |
pAux = (union auxent *)pEntry; |
pAux->x_sym.x_misc.x_fsize = LastFunctionAddress - pEntry->n_value; /* function updated size */ |
pAux->x_sym.x_fcnary.x_fcn.x_lnnoptr += LinesOffset; |
LastFunctionAddress = pEntry->n_value; |
pAux->x_sym.x_fcnary.x_fcn.x_endndx = LastFunctionIndex; /* point to next function index */ |
pAux->x_sym.x_tvndx = 0; /* ??? */ |
LastFunctionIndex = SymbolIndex; |
} else if ( (pEntry->n_sclass == C_FCN ) || ( pEntry->n_sclass == C_BLOCK) ) { |
if ( pEntry->n_name[1] == 'b' ) { |
/* .bf and .bb */ |
pEntry++; |
pAux = (union auxent *)pEntry; |
pAux->x_sym.x_fcnary.x_fcn.x_endndx = LastFunctionIndex; |
} |
} |
/* else do nothing */ |
/* update current symbol index */ |
pNode = GetCurrentNode( &ci->ListOfSymbols ); |
SymbolIndex -= ( pNode->Size / sizeof(struct syment) ); |
} |
// File Header |
ci->FileHeader.f_magic = MAGIC_NUMBER_AVR; |
ci->FileHeader.f_nscns = 2; |
// ci->FileHeader.f_timdat = time( (time_t *)&ci->FileHeader.f_timdat); |
ci->FileHeader.f_timdat = pi->time; |
ci->FileHeader.f_symptr = SymbolsOffset; |
ci->FileHeader.f_nsyms = NumberOfSymbols; |
ci->FileHeader.f_opthdr = 0; |
ci->FileHeader.f_flags = 0xff; /*F_RELFLG;*/ /* No relocation information available */ |
/* write it out */ |
if ( fwrite(&ci->FileHeader, 1, sizeof(struct external_filehdr), pi->coff_file ) != sizeof(struct external_filehdr) ) { |
fprintf(stderr,"\nFile error writing header ...(disk full?)"); |
return; |
} |
// Optional Information |
// Section 1 Header |
pSectionHdr = (struct external_scnhdr *)FindFirstListObject(&ci->ListOfSectionHeaders); |
if ( !pSectionHdr ) { |
fprintf(stderr, "\nInternal Coff error - cannot find section header .text!"); |
return; |
} |
memset( &pSectionHdr->s_name[0], 0, sizeof(struct external_scnhdr) ); |
strcpy( &pSectionHdr->s_name[0], ".text"); |
pSectionHdr->s_paddr = 0; |
pSectionHdr->s_vaddr = 0; |
pSectionHdr->s_size = ci->MaxRomAddress + 2; /* remember the last instruction */ |
pSectionHdr->s_scnptr = RawOffset; |
pSectionHdr->s_relptr = 0; |
pSectionHdr->s_lnnoptr = LinesOffset; |
pSectionHdr->s_nreloc = 0; |
pSectionHdr->s_nlnno = ci->ListOfLineNumbers.TotalBytes/sizeof(struct lineno); |
pSectionHdr->s_flags = STYP_TEXT; |
/* write it out */ |
if ( fwrite(&pSectionHdr->s_name[0], 1, sizeof(struct external_scnhdr), pi->coff_file ) != sizeof(struct external_scnhdr) ) { |
fprintf(stderr,"\nFile error writing section header ...(disk full?)"); |
return; |
} |
// Section 2 Header |
pSectionHdr = (struct external_scnhdr *)FindNextListObject(&ci->ListOfSectionHeaders); |
if ( !pSectionHdr ) { |
fprintf(stderr, "\nInternal Coff error - cannot find section header .bss!"); |
return; |
} |
memset( &pSectionHdr->s_name[0], 0, sizeof(struct external_scnhdr) ); |
strcpy( &pSectionHdr->s_name[0], ".bss"); |
/* later expansion */ |
pSectionHdr->s_paddr = ci->GlobalStartAddress; |
pSectionHdr->s_vaddr = ci->GlobalStartAddress; |
pSectionHdr->s_flags = STYP_DATA; /* seems it should be STYP_BSS */ |
/* write it out */ |
if ( fwrite(&pSectionHdr->s_name[0], 1, sizeof(struct external_scnhdr), pi->coff_file ) != sizeof(struct external_scnhdr) ) { |
fprintf(stderr,"\nFile error writing section header ...(disk full?)"); |
return; |
} |
/* Section N Header - .data or eeprom */ |
// Raw Data for Section 1 |
if ( (p = FindFirstListObject(&ci->ListOfRawData) ) == 0 ) { |
fprintf(stderr,"\nInternal error - unable to find binary data!"); |
return; |
} |
/* write it out */ |
if ( fwrite( p, 1, ci->MaxRomAddress + 2, pi->coff_file ) != (size_t)(ci->MaxRomAddress + 2) ) { |
fprintf(stderr,"\nFile error writing raw .text data ...(disk full?)"); |
return; |
} |
// Raw data for section n |
// Relocation Info for section 1 |
// Relocation info for section n |
// Line numbers for section 1 |
for ( pLine = (struct lineno *)FindFirstListObject( &ci->ListOfLineNumbers ); |
pLine != 0; |
pLine = (struct lineno *)FindNextListObject( &ci->ListOfLineNumbers ) ) { |
pNode = GetCurrentNode( &ci->ListOfLineNumbers ); |
/* write it out */ |
if ( fwrite( pLine, 1, pNode->Size, pi->coff_file ) != pNode->Size ) { |
fprintf(stderr,"\nFile error writing line numbers ...(disk full?)"); |
return; |
} |
} |
// Line numbers for section n |
// Symbol table |
for ( pEntry = (struct syment *)FindFirstListObject( &ci->ListOfSymbols ); |
pEntry != 0; |
pEntry = (struct syment *)FindNextListObject( &ci->ListOfSymbols ) ) { |
pNode = GetCurrentNode( &ci->ListOfSymbols ); |
/* write it out */ |
if ( fwrite( pEntry, 1, pNode->Size, pi->coff_file ) != pNode->Size ) { |
fprintf(stderr,"\nFile error writing symbol table ...(disk full?)"); |
return; |
} |
} |
// Symbol table of Globals |
for ( pEntry = (struct syment *)FindFirstListObject( &ci->ListOfGlobals ); |
pEntry != 0; |
pEntry = (struct syment *)FindNextListObject( &ci->ListOfGlobals ) ) { |
pNode = GetCurrentNode( &ci->ListOfGlobals ); |
/* write it out */ |
if ( fwrite( pEntry, 1, pNode->Size, pi->coff_file ) != pNode->Size ) { |
fprintf(stderr,"\nFile error writing global symbols ...(disk full?)"); |
return; |
} |
} |
/* Specials .text, .bss, .data */ |
for ( pEntry = (struct syment *)FindFirstListObject( &ci->ListOfSpecials ); |
pEntry != 0; |
pEntry = (struct syment *)FindNextListObject( &ci->ListOfSpecials ) ) { |
pNode = GetCurrentNode( &ci->ListOfSpecials ); |
/* write it out */ |
if ( fwrite( pEntry, 1, pNode->Size, pi->coff_file ) != pNode->Size ) { |
fprintf(stderr,"\nFile error writing special symbols ...(disk full?)"); |
return; |
} |
} |
// String Table |
for ( p = (char *)FindFirstListObject( &ci->ListOfStrings ); |
p != 0; |
p = (char *)FindNextListObject( &ci->ListOfStrings ) ) { |
pNode = GetCurrentNode( &ci->ListOfStrings ); |
/* write it out */ |
if ( fwrite( p, 1, pNode->Size, pi->coff_file ) != pNode->Size ) { |
fprintf(stderr,"\nFile error writing strings data ...(disk full?)"); |
return; |
} |
} |
return; |
} |
/****************************************************************************************/ |
void write_coff_eeprom( struct prog_info *pi, int address, unsigned char data){ |
if ( !GET_ARG(pi->args, ARG_COFF) ) |
return; |
/* Coff output keeps track of binary data in memory buffers */ |
if ( ci->pEEPRomMemory ) { |
if ( address <= pi->device->eeprom_size ) { |
*(ci->pEEPRomMemory + address) = data; |
if ( address >= ci->MaxEepromAddress ) |
ci->MaxEepromAddress = address; /* keep high water mark */ |
} else { |
pi->error_count++; |
fprintf(stderr, "Error: EEPROM address %d exceeds max range %d", address, pi->device->eeprom_size ); |
} |
} |
} |
/****************************************************************************************/ |
void write_coff_program( struct prog_info *pi, int address, unsigned int data){ |
unsigned char *pByte; |
if ( !GET_ARG(pi->args, ARG_COFF) ) |
return; |
/* Coff output keeps track of binary data in memory buffers, address is in bytes not words */ |
if ( ci->pRomMemory ) { |
/* JEG if ( address <= pi->device->flash_size ) { */ /* JEG 4-23-03 */ |
if ( address <= pi->device->flash_size*2 ) { |
pByte = (unsigned char *)(ci->pRomMemory + address); /* point to low byte in memory */ |
*pByte++ = (data & 0xff); /* low byte */ |
*pByte = ((data >> 8) & 0xff); /* high byte */ |
if ( address >= ci->MaxRomAddress ) |
ci->MaxRomAddress = address; /* keep high water mark */ |
} else { |
pi->error_count++; |
/* JEG fprintf(stderr, "Error: FLASH address %d exceeds max range %d", address, pi->device->flash_size ); */ |
fprintf(stderr, "Error: FLASH address %d exceeds max range %d", address, pi->device->flash_size*2 ); |
} |
} |
} |
/****************************************************************************************/ |
void close_coff_file(struct prog_info *pi, FILE *fp){ |
/* close the output file */ |
fclose( fp ); |
pi->coff_file = 0; |
/* free all the internal memory buffers used by ci */ |
FreeList( &ci->ListOfSectionHeaders ); |
FreeList( &ci->ListOfRawData ); |
FreeList( &ci->ListOfRelocations ); |
FreeList( &ci->ListOfLineNumbers ); |
FreeList( &ci->ListOfSymbols ); |
FreeList( &ci->ListOfGlobals ); |
FreeList( &ci->ListOfUndefined ); |
FreeList( &ci->ListOfStrings ); |
FreeList( &ci->ListOfTypes ); |
FreeList( &ci->ListOfSplitLines ); |
/* now free ci */ |
free( ci ); |
ci = 0; |
} |
/****************************************************************************************/ |
int parse_stabs( struct prog_info *pi, char *p ){ |
int ok = True; |
int TypeCode, n; |
char *pString, *p2, *p3, *p4, *p5, *pType, *pEnd, *pp, *pJoined; |
if ( !GET_ARG(pi->args, ARG_COFF) || ( pi->pass == PASS_1 ) ) |
return(True); |
/* stabs debugging information is in the form: |
.stabs "symbolic info string", HexorDecimalTypecode, parm3, parm4, parm5 |
parm1, parm2, parm3 depend on typecode |
N_LSYM 0x80 local sym: name,,0,type,offset |
N_OPT 0x3c compiler options |
N_SO 0x64 source file name: name,,0,0,address |
N_SOL 0x84 #included file name: name,,0,0,address |
N_FUN 0x24 procedure: name,,0,linenumber,address |
N_GSYM 0x20 global symbol: name,,0,type,0 |
N_LCSYM 0x28 .lcomm symbol: name,,0,type,address |
N_STSYM 0x26 static symbol: name,,0,type,address |
N_RSYM 0x40 register sym: name,,0,type,register |
N_PSYM 0xa0 parameter: name,,0,type,offset |
*/ |
/* Look for multiple commands per line */ |
/* .stabs "linktag:T19=s46next:20=*19,0,16;last:20,16,16;a:21=ar1;0;2;22=ar1;0;3;1,32,96;\\",128,0,0,0 */ |
/* .stabs "b:23=ar1;0;4;24=ar1;0;5;2,128,240;;",128,0,0,0 */ |
/* Look for continuation lines per line */ |
/* Get String information as a token */ |
/* Parse the tokens in the stabn line buffer */ |
pString = get_next_token(p, TERM_DOUBLEQUOTE ); /* zap first doublequote */ |
p2 = get_next_token(pString, TERM_DOUBLEQUOTE ); /* zap last doublequote */ |
p2 = get_next_token(p2, TERM_COMMA ); /* zap comma */ |
p3 = get_next_token(p2, TERM_COMMA ); |
p4 = get_next_token(p3, TERM_COMMA ); |
p5 = get_next_token(p4, TERM_COMMA ); |
pEnd = get_next_token(p5, TERM_END ); /* zap CR LF, make ASCIIZ */ |
if ( !pString || !p2 || !p3 || !p4 || !p5 ) |
return( False ); |
/* Check for split lines */ |
n = strlen( pString ); |
if ( ( pString[n - 1] == '\\' ) && (pString[n - 2] == '\\') ) { |
/* We have a continuation string here */ |
pString[n - 2] = 0; |
n -= 2; |
if ( !(pp = (char *)AllocateListObject( &ci->ListOfSplitLines, n + 1 )) ) { |
fprintf(stderr, "\nOut of memory allocating continuation line!"); |
return( False ); |
} |
strcpy( pp, pString ); /* loose the continuation characters */ |
return(True); |
} |
if ( ci->ListOfSplitLines.TotalItems > 0 ) { |
/* Join lines together and process */ |
if ( !(pJoined = calloc( 1, n + ci->ListOfSplitLines.TotalBytes ) ) ) { |
fprintf(stderr, "\nOut of memory joining continuation lines!"); |
return( False ); |
} |
for ( pp = (char *)FindFirstListObject( &ci->ListOfSplitLines ); |
pp != 0; |
pp = (char *)FindNextListObject( &ci->ListOfSplitLines ) ) { |
strcat( pJoined, pp ); /* connect the lines */ |
} |
strcat( pJoined, pString ); |
FreeList( &ci->ListOfSplitLines ); |
if ( !AddListObject( &ci->ListOfSplitLines, pJoined, n + ci->ListOfSplitLines.TotalBytes ) ) { |
fprintf(stderr, "\nUnable to add joined continuation line"); |
return( False ); |
} |
pString = pJoined; |
} |
if ( *p2 == '0' ) |
TypeCode = atox(p2); /* presume to be hex 0x */ |
else |
TypeCode = atoi(p2); |
switch ( TypeCode ) { |
case N_OPT: /* compiler options */ |
break; /* nothing used here */ |
case N_SO: /* source file name: name,,0,0,address */ |
ok = stab_add_filename( pString, p5 ); |
break; |
case N_GSYM: /* global symbol: name,,0,type,0 */ |
pType = get_next_token(pString, TERM_COLON ); /* separate at colon */ |
ok = stab_add_global( pi, pString, pType ); |
break; |
case N_FUN: /* procedure: name,,0,linenumber,address */ |
ok = stab_add_function( pi, pString, p5 ); |
break; |
case N_LSYM: /* local sym: name,,0,type,offset */ |
/* pString, p2 = TypeCode, p3 = 0, p4 = 0, p5 = offset */ |
pType = get_next_token(pString, TERM_COLON ); /* pType = symbol descriptor (character after the colon) */ |
if ( *pType == 't') |
ok = stab_add_local_type( pString, ++pType ); |
else if (*pType == 'T') |
ok = stab_add_tag_type( pString, ++pType ); |
else |
ok = stab_add_local( pi, pString, pType, p5 ); |
break; |
case N_RSYM: /* Symbol:[P|r]type,0,size,register */ |
pType = get_next_token(pString, TERM_COLON ); /* separate at colon */ |
ok = stab_add_local_register( pi, pString, pType, p5 ); |
break; |
case N_LCSYM: /* .lcomm symbol: name,,0,type,address */ |
ok = True; |
break; /* ignore constants */ |
case N_STSYM: /* static symbol: name,,0,type,address */ |
pType = get_next_token(pString, TERM_COLON ); /* separate at colon */ |
ok = stab_add_static_symbol( pi, pString, pType, p5 ); |
break; |
case N_PSYM: /* parameter: name,,0,type,offset */ |
pType = get_next_token(pString, TERM_COLON ); /* separate at colon */ |
ok = stab_add_parameter_symbol( pi, pString, pType, p5 ); |
break; |
case N_SOL: /* #included file name: name,,0,0,address */ |
ok = True; |
break; /* ignore include files */ |
default: |
ok = False; |
} |
if ( ci->ListOfSplitLines.TotalItems > 0 ) |
FreeList( &ci->ListOfSplitLines ); |
return( ok ); |
} |
/****************************************************************************************/ |
int parse_stabn( struct prog_info *pi, char *p ){ |
int ok = True; |
int TypeCode /* , LineNumber */, Level; |
char *p1, *p2, *p3, *p4, *pLabel, *pFunction, *pEnd; |
/* stabn debugging information is in the form: |
.stabn TypeCode, 0, parm1, parm2 |
parm1 is level |
parm2 is Label-Function |
compiler currently produces the following TypeCodes: |
N_LBRAC 0xc0 left bracket: 0,,0,nesting level,address |
N_RBRAC 0xe0 right bracket: 0,,0,nesting level,address |
N_SLINE 0x44 src line: 0,,0,linenumber,address |
*/ |
if ( !GET_ARG(pi->args, ARG_COFF) || ( pi->pass == PASS_1 ) ) |
return(True); |
/* Parse the tokens in the stabn line buffer */ |
p1 = get_next_token(p, TERM_SPACE ); |
p2 = get_next_token(p1, TERM_COMMA ); |
p3 = get_next_token(p2, TERM_COMMA ); |
p4 = get_next_token(p3, TERM_COMMA ); |
pEnd = get_next_token(p4, TERM_END ); /* zap CR LF, make ASCIIZ */ |
if ( !p1 || !p2 || !p3 || !p4 ) |
return( False ); |
/* first convert TypeCode to binary */ |
if ( *p1 == '0' ) |
TypeCode = atox(p1); /* presume to be hex 0x */ |
else |
TypeCode = atoi(p1); |
Level = atoi(p3); /* line number or level */ |
pLabel = p4; /* Assembly label */ |
pFunction = get_next_token( pLabel, TERM_DASH ); /* Function */ |
switch ( TypeCode ) { |
case N_SLINE: /* src line: 0,,0,linenumber,address */ |
ok = stab_add_lineno( pi, Level, pLabel, pFunction ); |
break; |
case N_LBRAC: /* left bracket: 0,,0,nesting level,address */ |
ok = stab_add_lbracket( pi, Level, pLabel, pFunction ); |
break; |
case N_RBRAC: /* right bracket: 0,,0,nesting level,address */ |
ok = stab_add_rbracket( pi, Level, pLabel, pFunction ); |
break; |
default: |
fprintf(stderr, "\nUnknown .stabn TypeCode = 0x%x", TypeCode ); |
ok = False; |
} |
return( ok ); |
} |
/****************************************************************************************/ |
int stab_add_lineno( struct prog_info *pi, int LineNumber, char *pLabel, char *pFunction ){ |
int Address; |
struct lineno *pln; |
struct syment *pEntry; |
union auxent *pAux; |
/* Allocate LineNumber Table entry and fill it in */ |
pln = (struct lineno *)AllocateListObject(&ci->ListOfLineNumbers, sizeof(struct lineno) ); |
if ( !pln ) { |
fprintf(stderr, "\nOut of memory allocating lineno table for function %s", pFunction ); |
return( False ); |
} |
/* set value field to be address of label in bytes */ |
if ( !get_symbol(pi, pLabel, &Address) ) { |
fprintf(stderr, "\nUnable to locate label %s", pLabel ); |
return( False ); |
} |
pln->l_addr.l_paddr = Address * 2; /* need byte quanities */ |
/* Line number is relative to beginning of function, starts at 1 */ |
if ( ci->FunctionStartLine == 0 ) { |
/* This line number is that same as the function start */ |
ci->FunctionStartLine = LineNumber; |
} |
pln->l_lnno = LineNumber - ci->FunctionStartLine + 1; |
ci->CurrentSourceLine = LineNumber; /* keep track of source line for .eb .ef arrays */ |
if ( ci->NeedLineNumberFixup ) { |
/* need to go into symbol table and fix last NeedLineNumberFixup entries */ |
for ( pEntry = (struct syment *)FindLastListObject(&ci->ListOfSymbols); |
(pEntry != 0) && ( ci->NeedLineNumberFixup != 0); |
pEntry = (struct syment *)FindNextLastListObject(&ci->ListOfSymbols) ) { |
/* Fix up line number entries */ |
if ( (pEntry->n_sclass == C_FCN ) || ( pEntry->n_sclass == C_BLOCK ) || ( pEntry->n_sclass == C_EXT) ) { |
pEntry++; |
pAux = (union auxent *)pEntry; |
pAux->x_sym.x_misc.x_lnsz.x_lnno = LineNumber; |
ci->NeedLineNumberFixup--; |
} |
} |
} |
return(True); |
} |
/****************************************************************************************/ |
int stab_add_lbracket( struct prog_info *pi, int Level, char *pLabel, char *pFunction ){ |
int Address; |
struct syment *pEntry; |
union auxent *pAux; |
//char *p; |
//struct lineno *pln; |
if ( !get_symbol(pi, pLabel, &Address) ) { |
fprintf(stderr, "\nUnable to locate label %s", pLabel ); |
return( False ); |
} |
/* Now create a .bb symbol table entry and aux entry too */ |
pEntry = (struct syment *)AllocateTwoListObjects( &ci->ListOfSymbols, sizeof(struct syment) * 2 ); |
if ( !pEntry ) { |
fprintf(stderr, "\nOut of memory allocating symbol table entry for .bb %s", pLabel ); |
return( False ); |
} |
/* n_name */ |
memset( pEntry->n_name, 0, 8 ); |
strcpy( pEntry->n_name, ".bb" ); |
pEntry->n_value = Address * 2; /* bytes not words */ |
pEntry->n_scnum = 1; /* .text */ |
pEntry->n_type = 0; |
pEntry->n_sclass = C_BLOCK; |
pEntry->n_numaux = 1; |
pEntry++; /* point to aux entry */ |
pAux = (union auxent *)pEntry; |
pAux->x_sym.x_misc.x_lnsz.x_lnno = 0; /* UNKNOWN - post process */ |
pAux->x_sym.x_misc.x_lnsz.x_size = 0; /* UNKNOWN - post process */ |
ci->NeedLineNumberFixup++; /* once for .bb block */ |
return(True); |
} |
/****************************************************************************************/ |
int stab_add_rbracket( struct prog_info *pi, int Level, char *pLabel, char *pFunction ){ |
int Address; |
struct syment *pEntry; |
union auxent *pAux; |
//char *p; |
//struct lineno *pln; |
if ( !get_symbol(pi, pLabel, &Address) ) { |
fprintf(stderr, "\nUnable to locate label %s", pLabel ); |
return( False ); |
} |
/* Now create a .eb symbol table entry */ |
pEntry = (struct syment *)AllocateTwoListObjects( &ci->ListOfSymbols, sizeof(struct syment) * 2 ); |
if ( !pEntry ) { |
fprintf(stderr, "\nOut of memory allocating symbol table entry for .eb %s", pLabel ); |
return( False ); |
} |
/* n_name */ |
memset( pEntry->n_name, 0, 8 ); |
strcpy( pEntry->n_name, ".eb" ); |
pEntry->n_sclass = C_BLOCK; |
pEntry->n_value = Address * 2; /* bytes not words */ |
pEntry->n_scnum = 1; /* .text */ |
pEntry->n_type = 0; |
pEntry->n_numaux = 1; |
pEntry++; /* point to aux entry */ |
pAux = (union auxent *)pEntry; |
pAux->x_sym.x_misc.x_lnsz.x_lnno = ci->CurrentSourceLine; |
/* create an .ef if at level 0 */ |
if ( Level == 0 ) { |
/* Now create a .ef symbol table entry */ |
pEntry = (struct syment *)AllocateTwoListObjects( &ci->ListOfSymbols, sizeof(struct syment) * 2 ); |
if ( !pEntry ) { |
fprintf(stderr, "\nOut of memory allocating symbol table entry for .ef %s", pLabel ); |
return( False ); |
} |
/* n_name */ |
memset( pEntry->n_name, 0, 8 ); |
strcpy( pEntry->n_name, ".ef" ); |
pEntry->n_sclass = C_FCN; |
pEntry->n_value = Address * 2; /* bytes not words */ |
pEntry->n_scnum = 1; /* .text */ |
pEntry->n_type = 0; |
pEntry->n_numaux = 1; |
pEntry++; /* point to aux entry */ |
pAux = (union auxent *)pEntry; |
pAux->x_sym.x_misc.x_lnsz.x_lnno = ci->CurrentSourceLine; |
} |
return(True); |
} |
/****************************************************************************************/ |
int stab_add_filename( char *pName, char *pLabel ){ |
int ok, n; |
struct syment *pEntry; |
union auxent *pAux; |
char *p; |
/* if( pLabel == "Ltext0" ) then beginning of .text, pName = cwd, next pName = file */ |
/* if( pLabel == "Letext" ) then end of .text , pName == NULL */ |
/* we only need the one not ending in Slash */ |
ok = True; |
n = strlen(pName); |
if ( n > 0 ) { |
if ( ( pName[ n - 1] == '\\') || (pName[ n - 1] == '/') ) |
return(True); /* ignore */ |
} else |
return(True); |
/* allocate entry in symbol table list */ |
pEntry = (struct syment *)AllocateTwoListObjects( |
&ci->ListOfSymbols, sizeof(struct syment) * 2 ); /* aux entry too */ |
if ( !pEntry ) { |
fprintf(stderr, "\nOut of memory allocating symbol table entry for global %s", pName ); |
return( False ); |
} |
/* n_name */ |
memset( pEntry->n_name, 0, 8 ); |
strcpy( pEntry->n_name, ".file" ); |
/* n_value is determined after processing done UNKNOWN - post process */ |
/* The value of that symbol equals the symbol table entry index of the next .file symbol or .global */ |
/* post process */ |
pEntry->n_scnum = N_DEBUG; |
pEntry->n_sclass = C_FILE; |
pEntry->n_numaux = 1; |
pEntry++; /* point to aux entry */ |
pAux = (union auxent *)pEntry; |
/* Add Label name to symbol table */ |
if ( n <= FILNMLEN ) { |
/* inline filename */ |
memset( pAux->x_file.x_fname, 0, FILNMLEN ); |
strncpy( pAux->x_file.x_fname, pName, n ); /* might not be zero terminated */ |
} else { |
pAux->x_file.x_n.x_zeroes = 0; /* symbol name is in string table */ |
pAux->x_file.x_n.x_offset = ci->ListOfStrings.TotalBytes; |
/* add to string table */ |
p = (char *)AllocateListObject( &ci->ListOfStrings, n + 1 ); |
if ( !p ) { |
fprintf(stderr, "\nOut of memory allocating string table space!"); |
return( False ); |
} |
strcpy( p, pName ); |
} |
return( ok ); |
} |
/****************************************************************************************/ |
int stab_add_function( struct prog_info *pi, char *pName, char *pLabel ){ |
int n, Address; |
unsigned short CoffType, Type; |
struct syment *pEntry; |
char *pType; |
struct lineno *pln; |
union auxent *pAux; |
int SymbolIndex; |
pType = get_next_token(pName, TERM_COLON ); /* pType = symbol descriptor (character after the colon) */ |
Type = atoi(pType + 1); /* skip past F, predefined variable type */ |
if ( (CoffType = GetCoffType( Type )) == 0 ) { |
fprintf(stderr, "\nUnrecognized return type found for function %s = %d", pName, Type ); |
return(False); |
} |
/* Get Current Symbol Index, Allocate Symbol Table entry and fill it in */ |
SymbolIndex = ci->ListOfSymbols.TotalItems; |
pEntry = (struct syment *)AllocateTwoListObjects( &ci->ListOfSymbols, sizeof(struct syment) * 2 ); |
if ( !pEntry ) { |
fprintf(stderr, "\nOut of memory allocating symbol table entry for function %s", pName ); |
return( False ); |
} |
if ( (n = AddNameToEntry( pName, pEntry )) == 0 ) { |
fprintf(stderr,"\nOut of memory adding local %s to string table", pName ); |
} |
if ( !get_symbol(pi, pLabel, &Address) ) { |
fprintf(stderr, "\nUnable to locate function %s", pName ); |
return( False ); |
} |
pEntry->n_value = Address * 2; /* convert words to bytes */ |
pEntry->n_scnum = 2; /* .bss */ |
if ( (CoffType = GetCoffType( Type )) == 0 ) { |
fprintf(stderr, "\nUnrecognized type found for function %s = %d", pName, Type ); |
return(False); |
} |
pEntry->n_type = (unsigned short)(CoffType | (DT_FCN << 4)); |
pEntry->n_sclass = C_EXT; |
pEntry->n_numaux = 1; |
pEntry++; /* point to aux entry */ |
pAux = (union auxent *)pEntry; |
pAux->x_sym.x_tagndx = SymbolIndex + 1; /* point to the .bf entry index */ |
// wrong! |
// pAux->x_sym.x_misc.x_lnsz.x_lnno = ci->ListOfLineNumbers.TotalBytes; /* Relative Fixup point to where line numbers start */ |
// pAux->x_sym.x_misc.x_lnsz.x_size = 0; /* UNKNOWN till next function called */ |
pAux->x_sym.x_misc.x_fsize = 0; /* unknown till end */ |
pAux->x_sym.x_fcnary.x_fcn.x_lnnoptr = ci->ListOfLineNumbers.TotalBytes; /* relative offset to line number entry */ |
pAux->x_sym.x_fcnary.x_fcn.x_endndx = 0; /* index to next entry */ |
/* Now add function entry into the line number table */ |
/* Allocate Symbol Table entry and fill it in */ |
pln = (struct lineno *)AllocateListObject(&ci->ListOfLineNumbers, sizeof(struct lineno) ); |
if ( !pln ) { |
fprintf(stderr, "\nOut of memory allocating lineno table for function %s", pName ); |
return( False ); |
} |
pln->l_lnno = 0; |
pln->l_addr.l_symndx = SymbolIndex; |
/* Initialize the FunctionStartLine from the beginning of the function */ |
ci->FunctionStartLine = 0; |
/* Allocate Symbol Table entry and fill it in */ |
pEntry = (struct syment *)AllocateTwoListObjects( &ci->ListOfSymbols, sizeof(struct syment) * 2 ); |
if ( !pEntry ) { |
fprintf(stderr, "\nOut of memory allocating symbol table entry .bf for function %s", pName ); |
return( False ); |
} |
memset( pEntry->n_name, 0, 8 ); |
strcpy( pEntry->n_name, ".bf" ); |
pEntry->n_value = Address * 2; /* bytes not words */ |
pEntry->n_scnum = 1; /* .text */ |
pEntry->n_type = 0; |
pEntry->n_sclass = C_FCN; |
pEntry->n_numaux = 1; |
pEntry++; /* point to aux entry */ |
pAux = (union auxent *)pEntry; |
pAux->x_sym.x_misc.x_lnsz.x_lnno = 0; /* UNKNOWN - post process */ |
pAux->x_sym.x_misc.x_lnsz.x_size = 0; /* UNKNOWN - post process */ |
ci->NeedLineNumberFixup++; /* once for function C_EXT symbol */ |
ci->NeedLineNumberFixup++; /* once for .bf block */ |
return( True ); |
} |
/****************************************************************************************/ |
int stab_add_global( struct prog_info *pi, char *pName, char *pType ){ |
int n, Address, IsArray, SymbolIndex; |
unsigned short CoffType, Type; |
struct syment *pEntry; |
char *p; |
STABCOFFMAP *pMap; |
n = strlen( pName ); /* see if it's 8 bytes or less */ |
Type = atoi(pType + 1); /* skip past G, predefined variable type */ |
if ( (CoffType = GetCoffType( Type )) == 0 ) { |
fprintf(stderr, "\nUnrecognized type found for global %s = %d", pName, Type ); |
return(False); |
} |
pMap = (STABCOFFMAP *)GetCurrentListObject( &ci->ListOfTypes ); |
SymbolIndex = ci->ListOfSymbols.TotalItems; |
/* Allocate Symbol Table entry and fill it in, Auxiliary table if its an array */ |
if ( IsTypeArray( CoffType ) == True ) { |
IsArray = True; |
pEntry = (struct syment *)AllocateTwoListObjects( &ci->ListOfGlobals, sizeof(struct syment) * 2 ); |
} else { |
IsArray = False; |
pEntry = (struct syment *)AllocateListObject( &ci->ListOfGlobals, sizeof(struct syment) ); |
} |
if ( (n = AddNameToEntry( pName, pEntry )) == 0 ) { |
fprintf(stderr,"\nOut of memory adding local %s to string table", pName ); |
} |
/* set value field to be address of label in bytes */ |
/* add underscore to lookup label */ |
if ( (p = calloc( 1, n + 2)) == 0 ) { |
fprintf(stderr,"\nOut of memory adding global %s", pName ); |
return(False); |
} |
*p = '_'; |
strcpy( p + 1, pName ); |
if ( !get_symbol(pi, p, &Address) ) { |
fprintf(stderr, "\nUnable to locate global %s", p ); |
free( p ); |
return( False ); |
} |
free( p ); |
pEntry->n_value = Address; /* already in bytes */ |
if ( ci->GlobalStartAddress == -1 ) { |
ci->GlobalStartAddress = Address; |
} |
if ( Address < ci->GlobalStartAddress ) |
ci->GlobalStartAddress = Address; |
if ( Address > ci->GlobalEndAddress ) |
ci->GlobalEndAddress = Address; |
pEntry->n_scnum = 2; /* .bss */ |
pEntry->n_type = CoffType; |
pEntry->n_sclass = C_STAT; |
if ( IsArray == False ) |
pEntry->n_numaux = 0; |
else { |
pEntry->n_numaux = 1; |
pEntry++; |
AddArrayAuxInfo( (union auxent *)pEntry, (unsigned short)SymbolIndex, pMap ); |
} |
return( True ); |
} |
/****************************************************************************************/ |
int stab_add_local( struct prog_info *pi, char *pName, char *pType, char *pOffset ){ |
int n, Offset, IsArray; |
unsigned short CoffType, Type, SymbolIndex; |
struct syment *pEntry; |
STABCOFFMAP *pMap; |
n = strlen( pName ); /* see if it's 8 bytes or less */ |
Type = atoi(pType); /* predefined variable type */ |
Offset = atoi(pOffset); /* offset in stack frame */ |
if ( (CoffType = GetCoffType( Type )) == 0 ) { |
fprintf(stderr, "\nUnrecognized type found for local %s = %d", pName, Type ); |
return(False); |
} |
pMap = (STABCOFFMAP *)GetCurrentListObject( &ci->ListOfTypes ); |
SymbolIndex = ci->ListOfSymbols.TotalItems; |
/* Allocate Symbol Table entry and fill it in, Auxiliary table if its an array */ |
if ( IsTypeArray( CoffType ) == True ) { |
IsArray = True; |
pEntry = (struct syment *)AllocateTwoListObjects( &ci->ListOfGlobals, sizeof(struct syment) * 2 ); |
} else { |
IsArray = False; |
pEntry = (struct syment *)AllocateListObject( &ci->ListOfSymbols, sizeof(struct syment) ); |
} |
if ( (n = AddNameToEntry( pName, pEntry )) == 0 ) { |
fprintf(stderr,"\nOut of memory adding local %s to string table", pName ); |
} |
pEntry->n_type = CoffType; |
pEntry->n_sclass = C_AUTO; |
pEntry->n_scnum = N_ABS; |
pEntry->n_value = Offset + 1; /* Silly avr studio is set in its ways */ |
if ( IsArray == False ) |
pEntry->n_numaux = 0; |
else { |
pEntry->n_numaux = 1; |
pEntry++; |
AddArrayAuxInfo( (union auxent *)pEntry, SymbolIndex, pMap ); |
} |
return( True ); |
} |
/****************************************************************************************/ |
int stab_add_parameter_symbol( struct prog_info *pi, char *pName, char *pType, char *pOffset ){ |
int n, Offset; |
unsigned short CoffType, Type; |
struct syment *pEntry; |
n = strlen( pName ); /* see if it's 8 bytes or less */ |
Type = atoi(pType); /* predefined variable type */ |
Offset = atoi(pOffset); /* offset in stack frame */ |
if ( (CoffType = GetCoffType( Type )) == 0 ) { |
fprintf(stderr, "\nUnrecognized type found for %s = %d", pName, Type ); |
return(False); |
} |
/* Allocate Symbol Table entry and fill it in */ |
pEntry = (struct syment *)AllocateListObject( &ci->ListOfSymbols, sizeof(struct syment) ); |
if ( (n = AddNameToEntry( pName, pEntry )) == 0 ) { |
fprintf(stderr,"\nOut of memory adding local %s to string table", pName ); |
} |
pEntry->n_type = CoffType; |
pEntry->n_sclass = C_ARG; |
pEntry->n_scnum = N_ABS; |
pEntry->n_value = Offset; |
pEntry->n_numaux = 0; |
return( True ); |
} |
/****************************************************************************************/ |
int stab_add_static_symbol( struct prog_info *pi, char *pName, char *pType, char *pLabel ){ |
int n, Address; |
unsigned short CoffType, Type; |
struct syment *pEntry; |
n = strlen( pName ); /* see if it's 8 bytes or less */ |
Type = atoi(pType + 1); /* skip past S, predefined variable type */ |
if ( (CoffType = GetCoffType( Type )) == 0 ) { |
fprintf(stderr, "\nUnrecognized type found for %s = %d", pName, Type ); |
return(False); |
} |
/* Allocate Symbol Table entry and fill it in */ |
pEntry = (struct syment *)AllocateListObject( &ci->ListOfSymbols, sizeof(struct syment) ); |
if ( (n = AddNameToEntry( pName, pEntry )) == 0 ) { |
fprintf(stderr,"\nOut of memory adding local %s to string table", pName ); |
} |
pEntry->n_type = CoffType; |
pEntry->n_sclass = C_STAT; |
pEntry->n_scnum = N_ABS; |
if ( !get_symbol(pi, pLabel, &Address) ) { |
fprintf(stderr, "\nUnable to locate label %s", pLabel ); |
return( False ); |
} |
pEntry->n_value = Address * 2; /* find address of variable in bytes */ |
pEntry->n_numaux = 0; |
return( True ); |
} |
/****************************************************************************************/ |
int stab_add_local_register( struct prog_info *pi, char *pName, char *pType, char *pRegister ){ |
int n, Register, Size; |
unsigned short CoffType, Type; |
struct syment *pEntry; |
n = strlen( pName ); /* see if it's 8 bytes or less */ |
Type = (unsigned short)atoi(pType + 1); /* skip past P, predefined variable type */ |
Register = atoi(pRegister); /* offset in stack frame */ |
if ( (CoffType = GetCoffType( Type )) == 0 ) { |
fprintf(stderr, "\nUnrecognized type found for %s = %d", pName, Type ); |
return(False); |
} |
Size = GetCoffTypeSize( Type ); /* Silly requirement for avr studio */ |
/* Allocate Symbol Table entry and fill it in */ |
pEntry = (struct syment *)AllocateListObject( &ci->ListOfSymbols, sizeof(struct syment) ); |
if ( (n = AddNameToEntry( pName, pEntry )) == 0 ) { |
fprintf(stderr,"\nOut of memory adding local %s to string table", pName ); |
return(False); |
} |
pEntry->n_type = CoffType; |
// if( (*pType == 'r') || (*pType == 'R') ) |
// pEntry->n_sclass = C_REG; |
// else if( (*pType == 'p') || (*pType == 'P') ) |
pEntry->n_sclass = C_REGPARM; /* Silly avr studio only accepts this for registers */ |
// else{ |
// fprintf(stderr,"\nUnknown register type -> %s", pType ); |
// return(False); |
// } |
pEntry->n_scnum = N_ABS; |
pEntry->n_numaux = 0; |
if ( Size == 1 ) |
pEntry->n_value = 0xffffff00 | Register; /* Silly requirement for avr studio */ |
else if ( Size == 2 ) |
pEntry->n_value = 0xffff0000 | ((Register + 1) << 8) | Register; /* Silly requirement for avr studio */ |
else if ( Size == 4 ) |
pEntry->n_value = ((Register + 3) << 24) | ((Register + 3) << 16) | ((Register + 1) << 8) | Register; /* Silly requirement for avr studio */ |
else { |
fprintf(stderr,"\nUnknown register size (%d) and coff type (%d)", Size, CoffType ); |
return(False); |
} |
return( True ); |
} |
/****************************************************************************************/ |
int stab_add_local_type( char *pName, char *pType ){ |
char *p; |
unsigned short StabType; |
/* .stabs "int:t1=r1;-128;127;",128,0,0,0 */ |
/* .stabs ":t20=ar1;0;1;21=ar1;0;1;2",128,0,0,0 */ |
/* pType-----^ */ |
/* Stab Type - convert to Coff type at end (after inline assignments */ |
if ( GetStabType( pType, &StabType, &p ) != True ) { |
fprintf(stderr,"\nInvalid tag type found in structure item -> %s", p); |
return(False); |
} |
return(True); |
} |
/****************************************************************************************/ |
int GetStructUnionTagItem( char *p, char **pEnd, char **pName, unsigned short *pType, unsigned short *pBitOffset, unsigned short *pBitSize) { |
unsigned short StabType; |
/* Structure or Union Tag Item consists of -> name:type,bitoffset,bitsize; */ |
/* name */ |
*pName = p; |
while ( *p && (*p != ':') ) p++; // locate colon |
if ( *p != ':' ) { |
fprintf(stderr,"\nNo colon found in structure item -> %s", *pName); |
return(False); |
} |
*p++ = 0; // Asciiz |
/* Stab Type - convert to Coff type at end (after inline assignments */ |
if ( GetStabType( p, &StabType, &p ) != True ) { |
fprintf(stderr,"\nInvalid tag type found in structure item -> %s", p); |
return(False); |
} |
/* BitSize */ |
if ( *p != ',' ) { |
fprintf(stderr,"\nNo Bit size found in structure item -> %s", p ); |
return(False); |
} |
*pBitOffset = (unsigned short)atoi( ++p ); |
while ( *p && (*p >= '0') && (*p <= '9') ) p++; // locate end of digits |
/* BitOffset */ |
if ( *p != ',' ) { |
fprintf(stderr,"\nNo Bit offset found in structure item -> %s", p ); |
return(False); |
} |
*pBitSize = (unsigned short)atoi( ++p ); |
while ( *p && (*p >= '0') && (*p <= '9') ) p++; // locate end of digits |
/* Now convert stab type to COFF */ |
if ( (*pType = GetCoffType( (unsigned short)StabType)) == 0 ) { |
fprintf(stderr,"\nNo COFF type found for stab type %d", StabType ); |
return( False); |
} |
if ( *++p == ';' ) /* Now eat last semicolon(s) */ |
p++; |
*pEnd = p; |
return( True ); |
} |
/****************************************************************************************/ |
int GetEnumTagItem( char *p, char **pEnd, char **pEnumName, int *pEnumValue ) { |
/* Enum Tag Item consists of -> member1:value,member2:value2,; */ |
*pEnumName = p; |
while ( *p && (*p != ':') ) p++; // locate colon |
if ( *p != ':' ) { |
fprintf(stderr,"\nNo colon found in enum item -> %s", *pEnumName); |
return(False); |
} |
*p++ = 0; // Asciiz |
*pEnumValue = atoi(p); |
while ( *p && (*p >= '0') && (*p <= '9') ) p++; // locate end of digits |
if ( *p != ',' ) { |
fprintf(stderr,"\nNo comma found after enum value -> %s", p ); |
return(False); |
} |
if ( *++p ==';' ) |
p++; /* eat last semicolon */ |
*pEnd = p; |
return( True ); |
} |
/****************************************************************************************/ |
int GetArrayType( char *p, char **pEnd, STABCOFFMAP *pMap, unsigned short *DerivedBits, int ExtraLevels ){ |
int MinIndex, MaxIndex, Result, Size, i; |
char *pMinIndex, *pMaxIndex, *pType; |
unsigned short Type; |
Result = True; |
pMinIndex = pMaxIndex = pType = 0; |
while ( *p && (*p != ';') ) p++; /* find min index */ |
pMinIndex = ++p; |
while ( *p && (*p != ';') ) p++; /* find max index */ |
pMaxIndex = ++p; |
while ( *p && (*p != ';') ) p++; /* find type index */ |
pType = ++p; |
/* bump the pointers to the digits */ |
if ( !isdigit(*pMinIndex) ) |
Result = False; |
if ( !isdigit(*pMaxIndex) ) |
Result = False; |
if ( !isdigit(*pType) ) |
Result = False; |
/* Is syntax ok ? */ |
if ( Result != True ) { |
fprintf(stderr,"\nSyntax error on array parameters %s%s%s", pMinIndex, pMaxIndex, pType ); |
return(False); |
} |
MinIndex = atoi(pMinIndex); |
MaxIndex = atoi(pMaxIndex); |
if ( GetStabType( p, &Type, &p ) != True ) |
return(False); |
if ( !SetupDefinedType( Type, pMap, DerivedBits, ExtraLevels ) ) |
return( False ); |
/* Now update the size based on the indicies */ |
Size = (MaxIndex - MinIndex) + 1; |
pMap->ByteSize *= Size; |
pMap->Line = ci->CurrentSourceLine; |
/* add the dimension information */ |
for ( i = 5; i >= 0; i-- ) { |
if ( pMap->Dimensions[i] != 0 ) { |
i++; |
pMap->Dimensions[i] = Size; |
break; |
} |
} |
*pEnd = p; |
return(True); |
} |
/****************************************************************************************/ |
int GetStabType( char *p, unsigned short *pType, char **pEnd ) { |
STABCOFFMAP *pMap; |
int extra, ok; |
unsigned short derivedbits[6]; |
unsigned short LStabType, RStabType; |
char *pHigh, *pLow; |
LStabType = atoi( p ); |
while ( *p && (*p >= '0') && (*p <= '9') ) p++; // locate end of digits |
*pType = LStabType; |
if ( GetCoffType( LStabType ) != 0 ) { |
*pEnd = p; |
return(True); |
} |
if ( *p != '=' ) { |
fprintf(stderr, "\nSyntax error in type assignment -> %s", p ); |
return(False); |
} |
p++; |
/* Allocate space for new internal type */ |
if ( !(pMap = (STABCOFFMAP *)AllocateListObject(&ci->ListOfTypes, sizeof(STABCOFFMAP)) ) ) { |
fprintf(stderr, "\nOut of memory allocating type info!"); |
return(False); |
} |
pMap->StabType = LStabType; |
/* process items to right of equals */ |
for ( extra = 0; extra < 6; extra++ ) { |
if ( isdigit( *p ) ) { |
/* Finally found base type, try to terminate loop */ |
GetStabType( p, &RStabType, &p ); |
// RStabType = atoi( p ); |
while ( *p && (*p >= '0') && (*p <= '9') ) p++; // locate end of digits |
if ( SetupDefinedType( RStabType, pMap, &derivedbits[0], extra ) != True ) |
return( False ); |
break; |
} else if ( *p == 'a' ) { |
derivedbits[extra] = DT_ARY; |
p++; |
/* Calculate size */ |
/* Since type assignment will be made we need to set extra bits here */ |
extra++; |
/* =ar1;MinIndex;MaxIndex;BaseType */ |
if ( GetArrayType( p, &p, pMap, &derivedbits[0], extra ) != True ) |
return(False); |
break; |
} else if ( *p == 'f' ) { |
derivedbits[extra] = DT_FCN; |
p++; |
} else if ( *p == '*' ) { |
derivedbits[extra] = DT_PTR; |
p++; |
} else if ( *p == 'r' ) { |
// if( LStabType < 15 ) |
// ok = GetInternalType( pString, pMap ); /* internal types not yet installed */ |
// else |
while ( *p && (*p != ';' ) ) p++; |
pLow = p++; |
while ( *p && (*p != ';' ) ) p++; |
pHigh = p++; |
ok = GetSubRangeType( LStabType, pMap, pLow, pHigh ); |
if ( ok != True ) |
return(False); |
while ( *p && (*p != ';' ) ) p++; /* find end of range */ |
p++; |
break; |
} else { |
fprintf(stderr, "\nUnrecognized Type modifier %c!", *p ); |
return(False); |
} |
} |
*pEnd = p; /* Update return pointer */ |
return(True); |
} |
/****************************************************************************************/ |
int stab_add_tag_type( char *pName, char *pString ){ |
int SymbolIndex, StabType, TotalSize, n, EnumValue; |
unsigned short TagType, ItemType, BitOffset, BitSize; |
char *p; |
struct syment* pEntry; |
union auxent *pAux; |
STABCOFFMAP *pMap; |
/* We arrived here due to :T defining either a structure, union or enumeration */ |
/* store the basic type as for internals and emit coff structures for debugging */ |
/* .stabs "stag:T17=s2i:1,0,8;c:2,8,8;;",128,0,0,0 */ |
/* .stabs "2:T18=u2a:2,0,8;b:1,0,8;c:6,0,16;;",128,0,0,0 */ |
/* .stabs "1:T19=eenum1:1,enum2:2,enum3:3,;",128,0,0,0 */ |
/* we don't care about the name */ |
/* check for bogus errors */ |
if ( !pName || !pString ) { |
fprintf(stderr,"\nInvalid .stabs type format - no information!"); |
return(False); |
} |
p = pString; |
/* Stab Type - convert to Coff type at end (after inline assignments */ |
if ( (StabType = (unsigned short)atoi(p)) == 0 ) { |
fprintf(stderr,"\nInvalid .stabs type format - no information! - > %s", p ); |
return(False); |
} |
while ( *p && (*p >= '0') && (*p <= '9') ) p++; // locate end of digits |
if ( *p != '=' ) { |
fprintf(stderr,"\nInvalid .stabs type format - no equals - > %s", p ); |
return(False); |
} |
SymbolIndex = ci->ListOfSymbols.TotalItems; |
if ( ( pEntry = (struct syment*)AllocateTwoListObjects( &ci->ListOfGlobals, sizeof(struct syment) * 2 ) ) == 0 ) { |
fprintf(stderr, "\nOut of memory allocating symbol tag entries"); |
return(False); |
} |
/* Prepare Tag Header */ |
if ( (n = AddNameToEntry( pName, pEntry )) == 0 ) { |
fprintf(stderr,"\nOut of memory adding local %s to string table", pString ); |
return(False); |
} |
if ( !(pMap = (STABCOFFMAP *)AllocateListObject(&ci->ListOfTypes, sizeof(STABCOFFMAP)) ) ) { |
fprintf(stderr, "\nOut of memory allocating type info!"); |
return(False); |
} |
pMap->StabType = StabType; |
pEntry->n_value = 0; |
pEntry->n_scnum = N_DEBUG; |
pEntry->n_numaux = 1; |
if ( *++p == 's' ) { |
TagType = pEntry->n_type = pMap->CoffType = T_STRUCT; |
pEntry->n_sclass = C_STRTAG; |
TotalSize = (unsigned short)atoi(++p); |
} else if ( *p == 'u' ) { |
TagType = pEntry->n_type = pMap->CoffType = T_UNION; |
pEntry->n_sclass = C_UNTAG; |
TotalSize = (unsigned short)atoi(++p); |
} else if ( *p == 'e' ) { |
TagType = pEntry->n_type = pMap->CoffType = T_ENUM; |
pEntry->n_sclass = C_ENTAG; |
TotalSize = FundamentalTypes[T_INT].Size; /* use size of int for enums */ |
} else { |
fprintf(stderr,"\nUnknown tag type -> %s", p ); |
return(False); |
} |
while ( *p && (*p >= '0') && (*p <= '9') ) p++; // locate end of digits |
pEntry++; /* point to aux entry */ |
pAux = (union auxent *)pEntry; |
pAux->x_sym.x_tagndx = SymbolIndex; |
pAux->x_sym.x_misc.x_lnsz.x_size = TotalSize; |
/* update our local knowledge of tag type */ |
pMap->CoffType = TagType; |
pMap->ByteSize = TotalSize; |
pMap->Line = ci->CurrentSourceLine; |
/* Process the items until the end of the line */ |
while ( *pName ) { |
if ( ( pEntry = (struct syment*)AllocateTwoListObjects( &ci->ListOfGlobals, sizeof(struct syment) * 2 ) ) == 0 ) { |
fprintf(stderr, "\nOut of memory allocating symbol tag member entries"); |
return(False); |
} |
if ( TagType == T_STRUCT ) { |
if ( GetStructUnionTagItem( p, &p, &pName, &ItemType, &BitOffset, &BitSize) != True ) { |
return(False); |
} |
pEntry->n_value = BitOffset/8; |
pEntry->n_type = ItemType; |
pEntry->n_sclass = C_MOS; |
} else if ( TagType == T_UNION ) { |
if ( GetStructUnionTagItem( p, &p, &pName, &ItemType, &BitOffset, &BitSize) != True ) { |
return(False); |
} |
pEntry->n_value = BitOffset/8; |
pEntry->n_type = ItemType; |
pEntry->n_sclass = C_MOU; |
} else { /* T_ENUM */ |
if ( GetEnumTagItem( p, &p, &pName, &EnumValue ) != True ) { |
return(False); |
} |
pEntry->n_value = EnumValue; |
pEntry->n_type = TotalSize; |
pEntry->n_sclass = C_MOE; |
} |
/* Prepare Common Tag Header items */ |
if ( (n = AddNameToEntry( pName, pEntry )) == 0 ) { |
fprintf(stderr,"\nOut of memory adding local %s to string table", pString ); |
return(False); |
} |
pEntry->n_scnum = N_ABS; |
pEntry->n_numaux = 1; |
pEntry++; /* point to aux entry */ |
pAux = (union auxent *)pEntry; |
pAux->x_sym.x_tagndx = SymbolIndex; |
pAux->x_sym.x_misc.x_lnsz.x_size = TotalSize; |
pName = p; |
} |
/* End of Structures/Unions/Enumberations */ |
if ( ( pEntry = (struct syment*)AllocateTwoListObjects( &ci->ListOfGlobals, sizeof(struct syment) * 2 ) ) == 0 ) { |
fprintf(stderr, "\nOut of memory allocating special headers for structure!"); |
return(False); |
} |
strcpy( pEntry->n_name, ".eos" ); |
pEntry->n_value = TotalSize; |
pEntry->n_scnum = N_ABS; |
pEntry->n_type = 0; |
pEntry->n_sclass = C_EOS; |
pEntry->n_numaux = 1; |
pEntry++; /* point to aux entry */ |
pAux = (union auxent *)pEntry; |
pAux->x_sym.x_tagndx = SymbolIndex; /* point to the .bf entry index */ |
pAux->x_sym.x_misc.x_lnsz.x_size = TotalSize; |
return(True); |
} |
/****************************************************************************************/ |
int SetupDefinedType( unsigned short Type, STABCOFFMAP *pMap, unsigned short *DerivedBits, int ExtraLevels ){ |
int i, Dlimit, Dstart; |
unsigned short StabType; |
StabType = pMap->StabType; /* save the new type we found earlier */ |
if ( CopyStabCoffMap( Type, pMap ) != True ) { |
fprintf(stderr, "\nCould not find defined type %d", Type ); |
return(False); |
} |
pMap->StabType = StabType; /* save the new type we found earlier */ |
/* Determine existing derived types for base class */ |
for ( i = 0; i < 6; i++ ) { |
if ( (pMap->CoffType & ( 3 << (4 + i + i))) == 0 ) |
break; |
} |
Dstart = i; |
Dlimit = i + ExtraLevels; |
if ( (Dlimit) >= 6 ) { |
fprintf(stderr, "\nStab Type %d has too many derived (%d) types!", pMap->StabType, Dlimit ); |
return(False); |
} |
/* Add the new derived levels */ |
for ( ; i < Dlimit; i++ ) { |
pMap->CoffType |= ( ( DerivedBits[i - Dstart] & 3) << (4 + i + i) ); /* add in the derived bits */ |
} |
return(True); |
} |
/****************************************************************************************/ |
int GetArrayDefinitions( STABCOFFMAP *pMap , char *pMinIndex, char *pMaxIndex, char *pType, unsigned short *DerivedBits, int ExtraLevels ){ |
int MinIndex, MaxIndex, Result, Size, i; |
unsigned short Type; |
Result = True; |
if ( (*pMinIndex != ';') || (*pMaxIndex != ';') || (*pType != ';') ) |
Result = False; |
/* bump the pointers to the digits */ |
pMinIndex++; |
if ( !isdigit(*pMinIndex) ) |
Result = False; |
pMaxIndex++; |
if ( !isdigit(*pMaxIndex) ) |
Result = False; |
pType++; |
if ( !isdigit(*pType) ) |
Result = False; |
/* Is syntax ok ? */ |
if ( Result != True ) { |
fprintf(stderr,"\nSyntax error on array parameters %s%s%s", pMinIndex, pMaxIndex, pType ); |
return(False); |
} |
MinIndex = atoi(pMinIndex); |
MaxIndex = atoi(pMaxIndex); |
Type = (unsigned short)atoi(pType); |
if ( SetupDefinedType( Type, pMap, DerivedBits, ExtraLevels ) != True ) |
return( False ); |
/* Now update the size based on the indicies */ |
Size = (MaxIndex - MinIndex) + 1; |
pMap->ByteSize *= Size; |
pMap->Line = ci->CurrentSourceLine; |
/* add the dimension information */ |
for ( i = 5; i >= 0; i-- ) { |
if ( pMap->Dimensions[i] != 0 ) { |
i++; |
pMap->Dimensions[i] = Size; |
break; |
} |
} |
return(True); |
} |
/****************************************************************************************/ |
int GetInternalType( char *pName, STABCOFFMAP *pMap ){ |
int n, found, i; |
if ( !pName ) { |
return(False); |
} |
found = False; |
n = strlen(pName); |
/* Find out if it is a local type */ |
for (i = 0; FundamentalTypes[i].pString != 0; i++) { |
if ( !strncmp(pName, FundamentalTypes[i].pString, n) ) { |
/* found an internal type */ |
pMap->CoffType = FundamentalTypes[i].Type; |
pMap->ByteSize = FundamentalTypes[i].Size; |
found = True; |
} |
} |
return(found); |
} |
/****************************************************************************************/ |
int GetSubRangeType( unsigned short Type, STABCOFFMAP *pMap , char *pLow, char *pHigh ){ |
int Result, i; |
long High, Low; |
unsigned long Test; |
Result = True; |
if ( (*pLow != ';') || (*pHigh != ';') || (Type <= 0) ) |
Result = False; |
/* Is syntax ok ? */ |
if ( Result != True ) { |
fprintf(stderr,"\nSyntax error on sub range parameters!" ); |
return(False); |
} |
Low = atol(++pLow); |
High = atol(++pHigh); |
/* Special handling of type void */ |
if ( (Low == 0) && (High == 0) ) { |
/* Declare type void */ |
pMap->ByteSize =0; |
pMap->CoffType = T_VOID; |
pMap->Line = ci->CurrentSourceLine; |
return(True); |
} |
if ( (pMap->CoffType = GetCoffType( Type )) != 0 ) { |
pMap->ByteSize = GetCoffTypeSize( Type ); |
} else { |
/* Try to base everything off integer */ |
pMap->ByteSize = FundamentalTypes[T_INT].Size; |
} |
/* Now calculate the byte size */ |
if ( High == 0 ) { |
pMap->ByteSize = (unsigned short)Low; /* floating point */ |
} else { |
if ( Low == 0 ) { |
/* Unsigned */ |
Test = (unsigned long)High; |
} else if ( Low < 0 ) { |
/* signed */ |
Test = (unsigned long)High << 1; |
} else { |
if ( Low <= High ) |
Test = (unsigned long)High; |
else |
Test = (unsigned long)Low; |
} |
if ( pMap->ByteSize == 0 ) { |
fprintf(stderr,"\nType Range Error 1, need previous type %d size!", pMap->CoffType ); |
return(False); |
} |
for ( i = 0; i < sizeof(unsigned long); i++ ) { |
if ( !(Test & (0xff << (i * 8))) ) |
break; |
} |
pMap->ByteSize = i; |
} |
/* Now determine the best fit based on byte size, compare against IAR Compiler */ |
if ( pMap->ByteSize == 1 ) { |
if ( Low < 0 ) |
pMap->CoffType = T_CHAR; |
else |
pMap->CoffType = T_UCHAR; |
} else if ( pMap->ByteSize == 2 ) { |
if ( Low < 0 ) |
pMap->CoffType = T_INT; |
else |
pMap->CoffType = T_UINT; |
} else if ( pMap->ByteSize == 4 ) { |
if ( Low == 0 ) |
pMap->CoffType = T_FLOAT; |
if ( Low < 0 ) |
pMap->CoffType = T_LONG; |
else |
pMap->CoffType = T_ULONG; |
} else { |
fprintf(stderr,"\nGetSubRangeType failure - byte size %d", pMap->ByteSize ); |
return(False); |
} |
return(True); |
} |
/****************************************************************************************/ |
int CopyStabCoffMap( unsigned short StabType, STABCOFFMAP *pMap ){ |
STABCOFFMAP *p; |
for ( p = FindFirstListObject( &ci->ListOfTypes ); p != 0; p = FindNextListObject( &ci->ListOfTypes) ) { |
if ( p->StabType == StabType ) { |
memcpy( pMap, p, sizeof(STABCOFFMAP) ); |
return(True); |
} |
} |
return( False ); /* Nothing found */ |
} |
/****************************************************************************************/ |
unsigned short GetCoffType( unsigned short StabType ){ |
STABCOFFMAP *p; |
for ( p = FindFirstListObject( &ci->ListOfTypes ); p != 0; p = FindNextListObject( &ci->ListOfTypes) ) { |
if ( p->StabType == StabType ) |
return( p->CoffType ); |
} |
return( 0 ); /* Nothing found */ |
} |
/****************************************************************************************/ |
unsigned short GetCoffTypeSize( unsigned short StabType ){ |
STABCOFFMAP *p; |
for ( p = FindFirstListObject( &ci->ListOfTypes ); p != 0; p = FindNextListObject( &ci->ListOfTypes) ) { |
if ( p->StabType == StabType ) |
return( p->ByteSize ); |
} |
return( 0 ); /* Nothing found */ |
} |
/****************************************************************************************/ |
int GetDigitLength( char *p ){ |
int i; |
if ( p == 0 ) |
return(0); |
for ( i = 0; (*p != 0) && ( *p >= '0' ) && ( *p <= '9' ); i++ ); |
return( i ); |
} |
/****************************************************************************************/ |
int GetStringDelimiters( char *pString, char **pTokens, int MaxTokens ){ |
int i; |
char *p; |
p = pString; |
if ( !p ) |
return( 0 ); |
for ( i = 0; i < MaxTokens; i++ ) { |
while ( True ) { |
if ( (*p == ':') || (*p == ';') || (*p == '=') || (*p == ',') || (*p == '"') || (*p == 0 ) ) { |
*(pTokens + i) = p; /* Remember this location */ |
p++; |
if ( *p == 0 ) |
return( i ); |
break; |
} |
p++; |
} |
} |
return( i ); |
} |
/****************************************************************************************/ |
int IsTypeArray( unsigned short CoffType ){ |
int Result; |
Result = False; |
if ( (CoffType & (DT_ARY << 4 )) == (DT_ARY << 4 ) ) |
Result = True; |
if ( (CoffType & (DT_ARY << 6 )) == (DT_ARY << 6 ) ) |
Result = True; |
if ( (CoffType & (DT_ARY << 8 )) == (DT_ARY << 8 ) ) |
Result = True; |
if ( (CoffType & (DT_ARY << 10 )) == (DT_ARY << 10 ) ) |
Result = True; |
if ( (CoffType & (DT_ARY << 12 )) == (DT_ARY << 12 ) ) |
Result = True; |
if ( (CoffType & (DT_ARY << 14 )) == (DT_ARY << 14 ) ) |
Result = True; |
return(Result); |
} |
/****************************************************************************************/ |
void AddArrayAuxInfo( union auxent *pAux, unsigned short SymbolIndex, STABCOFFMAP *pMap ){ |
int i; |
pAux->x_sym.x_tagndx = SymbolIndex; /* point to the .bf entry index */ |
pAux->x_sym.x_misc.x_lnsz.x_lnno = pMap->Line; |
pAux->x_sym.x_misc.x_lnsz.x_size = pMap->ByteSize; |
for ( i = 0; i < 4; i++ ) |
pAux->x_sym.x_fcnary.x_ary.x_dimen[i] = pMap->Dimensions[i]; |
} |
/****************************************************************************************/ |
int AddNameToEntry( char *pName, struct syment *pEntry ) { |
int n; |
char *p; |
n = strlen( pName ); /* see if it's 8 bytes or less */ |
if ( n <= 8 ) { |
strncpy( pEntry->n_name, pName, 8 ); |
} else { |
/* point to current offset in string table */ |
pEntry->n_offset = ci->ListOfStrings.TotalBytes; |
/* Allocate string table entry */ |
if ( (p = (char *)AllocateListObject( &ci->ListOfStrings, n + 1 )) == 0 ) { |
return(0); |
} |
strcpy( p, pName ); |
} |
return(n); /* return size of string */ |
} |
/****************************************************************************************/ |
char *SkipPastDigits( char *p ){ |
if ( !p ) |
return(p); |
/* if ( *p == 0 ); */ /* JEG 5-01-03 */ |
if ( *p == 0 ) |
return(p); /* This line s/b indented JEG */ |
for ( p--; (*p >= '0') && (*p <= '9') && (*p != 0); p-- ); |
return(p); |
} |
/****************************************************************************************/ |
/****************************************************************************************/ |
/****************************************************************************************/ |
/* List management routines */ |
/****************************************************************************************/ |
/****************************************************************************************/ |
/****************************************************************************************/ |
/****************************************************************************************/ |
void InitializeList( LISTNODEHEAD *pHead ){ |
pHead->Node.Next = &pHead->Node; |
pHead->Node.Last = &pHead->Node; |
pHead->TotalBytes = 0; |
pHead->TotalItems = 0; |
pHead->current = &pHead->Node; |
return; |
} |
/****************************************************************************************/ |
void *AllocateTwoListObjects( LISTNODEHEAD *pHead, int size ){ |
void *p; |
if ( (p = AllocateListObject( pHead, size ) ) ) |
pHead->TotalItems++; /* already incremented once in addtolist */ |
return( p ); |
} |
/****************************************************************************************/ |
void *AllocateListObject( LISTNODEHEAD *pHead, int size ){ |
void *pObject; |
LISTNODE *pNode; |
if ( (pObject = calloc( 1, size )) != 0 ) { |
if ( !(pNode = AddListObject( pHead, pObject, size )) ) { |
free( pObject ); |
pObject = 0; |
} |
} |
return( pObject ); |
} |
/****************************************************************************************/ |
LISTNODE *AddListObject(LISTNODEHEAD *pHead, void *pObject, int size ){ |
LISTNODE *pNode; |
if ( (pNode = calloc( 1, sizeof(LISTNODE) )) != 0 ) { |
pNode->pObject = pObject; |
pNode->Size = size; |
pNode->FileNumber = ci->CurrentFileNumber; |
AddNodeToList( pHead, pNode ); |
} |
return( pNode ); |
} |
/****************************************************************************************/ |
LISTNODE *AllocateListNode( void *pObject, int size ){ |
LISTNODE *pNew; |
if ( (pNew = calloc( 1, sizeof( LISTNODE ) ) ) != 0 ) { |
/* Then we initialize the node */ |
pNew->pObject = pObject; |
pNew->Size = size; |
pNew->FileNumber = ci->CurrentFileNumber; |
} |
return(pNew); |
} |
/****************************************************************************************/ |
void AddNodeToList( LISTNODEHEAD *pHead, LISTNODE *pNode ){ |
LISTNODE *p; |
p = &pHead->Node; |
pNode->Next = p->Last->Next; |
p->Last->Next = pNode; |
pNode->Last = p->Last; |
p->Last = pNode; |
/* and update current size of data contained in the list */ |
pHead->TotalBytes += pNode->Size; |
pHead->TotalItems++; |
} |
/****************************************************************************************/ |
void RemoveNodeFromList( LISTNODEHEAD *pHead, LISTNODE *pNode ){ |
pNode->Last->Next = pNode->Next; |
pNode->Next->Last = pNode->Last; |
pHead->TotalBytes -= pNode->Size; |
pHead->TotalItems--; |
} |
/****************************************************************************************/ |
void *FindFirstListObject( LISTNODEHEAD *pHead ){ |
if ( pHead->Node.Next == &pHead->Node ) |
return(0); /* Nothing in list */ |
pHead->current = pHead->Node.Next; |
return( pHead->current->pObject ); |
} |
/****************************************************************************************/ |
void *FindNextListObject( LISTNODEHEAD *pHead ){ |
if ( pHead->current->Next == &pHead->Node ) |
return( 0 ); |
pHead->current = pHead->current->Next; |
return( pHead->current->pObject ); |
} |
/****************************************************************************************/ |
LISTNODE *GetCurrentNode( LISTNODEHEAD *pHead ){ |
return( pHead->current ); |
} |
/****************************************************************************************/ |
void *GetCurrentListObject( LISTNODEHEAD *pHead ){ |
return( pHead->current->pObject ); |
} |
/****************************************************************************************/ |
void *FindLastListObject( LISTNODEHEAD *pHead ){ |
if ( pHead->Node.Last == &pHead->Node ) |
return(0); /* Nothing in list */ |
pHead->current = pHead->Node.Last; |
return( pHead->current->pObject ); |
} |
/****************************************************************************************/ |
void *FindNextLastListObject( LISTNODEHEAD *pHead ){ |
if ( pHead->current->Last == &pHead->Node ) |
return( 0 ); |
pHead->current = pHead->current->Last; |
return( pHead->current->pObject ); |
} |
/****************************************************************************************/ |
void FreeList( LISTNODEHEAD *pHead ){ |
LISTNODE *pNode; |
for ( pNode = pHead->Node.Last; pNode->Next != &pHead->Node; pNode = pHead->Node.Last ) { |
RemoveNodeFromList( pHead, pNode ); |
free( pNode->pObject ); |
free( pNode ); |
} |
pHead->TotalBytes = 0; |
pHead->TotalItems = 0; |
pHead->current = &pHead->Node; |
} |
/****************************************************************************************/ |
/contrib/toolchain/avra/src/coff.h |
---|
0,0 → 1,403 |
// |
// coff.h - Common Object File Format (COFF) support |
// |
// This file was developed for the avra assembler in order to produce COFF output files |
// for use with the Atmel AVR Studio. The Lean C Compiler (LCC) debugging stabs |
// output was used as input to the assembler. |
// |
// This software has absolutely no warrantee! The money you paid for this will be |
// promptly refunded if not fully satisfied. |
// |
// Beta release 1/20/2000 by Bob Harris |
// |
// This software has not been fully tested and probably has a few software deficiencies. |
// Some software support may be possible by sending a problem description report to |
// rth@mclean.sparta.com |
#define MAGIC_NUMBER_AVR 0xa12 |
#define N_GSYM 0x20 /* global symbol: name,,0,type,0 */ |
#define N_FNAME 0x22 /* procedure name (f77 kludge): name,,0 */ |
#define N_FUN 0x24 /* procedure: name,,0,linenumber,address */ |
#define N_STSYM 0x26 /* static symbol: name,,0,type,address */ |
#define N_LCSYM 0x28 /* .lcomm symbol: name,,0,type,address */ |
#define N_MAIN 0x2a /* name of main routine : name,,0,0,0 */ |
#define N_ROSYM 0x2c /* ro_data objects */ |
#define N_OBJ 0x38 /* object file path or name */ |
#define N_OPT 0x3c /* compiler options */ |
#define N_RSYM 0x40 /* register sym: name,,0,type,register */ |
#define N_SLINE 0x44 /* src line: 0,,0,linenumber,address */ |
#define N_FLINE 0x4c /* function start.end */ |
#define N_SSYM 0x60 /* structure elt: name,,0,type,struct_offset */ |
#define N_ENDM 0x62 /* last stab emitted for module */ |
#define N_SO 0x64 /* source file name: name,,0,0,address */ |
#define N_LSYM 0x80 /* local sym: name,,0,type,offset */ |
#define N_BINCL 0x82 /* header file: name,,0,0,0 */ |
#define N_SOL 0x84 /* #included file name: name,,0,0,address */ |
#define N_PSYM 0xa0 /* parameter: name,,0,type,offset */ |
#define N_EINCL 0xa2 /* end of include file */ |
#define N_ENTRY 0xa4 /* alternate entry: name,linenumber,address */ |
#define N_LBRAC 0xc0 /* left bracket: 0,,0,nesting level,address */ |
#define N_EXCL 0xc2 /* excluded include file */ |
#define N_RBRAC 0xe0 /* right bracket: 0,,0,nesting level,address */ |
#define N_BCOMM 0xe2 /* begin common: name,, */ |
#define N_ECOMM 0xe4 /* end common: name,, */ |
#define N_ECOML 0xe8 /* end common (local name): ,,address */ |
#define N_LENG 0xfe /* second stab entry with length information */ |
/* |
* Type of a symbol, in low N bits of the word |
*/ |
#define T_NULL 0 |
#define T_VOID 1 /* function argument (only used by compiler) */ |
#define T_CHAR 2 /* character */ |
#define T_SHORT 3 /* short integer */ |
#define T_INT 4 /* integer */ |
#define T_LONG 5 /* long integer */ |
#define T_FLOAT 6 /* floating point */ |
#define T_DOUBLE 7 /* double word */ |
#define T_STRUCT 8 /* structure */ |
#define T_UNION 9 /* union */ |
#define T_ENUM 10 /* enumeration */ |
#define T_MOE 11 /* member of enumeration*/ |
#define T_UCHAR 12 /* unsigned character */ |
#define T_USHORT 13 /* unsigned short */ |
#define T_UINT 14 /* unsigned integer */ |
#define T_ULONG 15 /* unsigned long */ |
#define T_LNGDBL 16 /* long double */ |
/* |
* derived types, in n_type |
*/ |
#define DT_NON (0) /* no derived type */ |
#define DT_PTR (1) /* pointer */ |
#define DT_FCN (2) /* function */ |
#define DT_ARY (3) /* array */ |
struct external_filehdr { |
unsigned short f_magic; /* magic number */ |
unsigned short f_nscns; /* number of sections */ |
unsigned long f_timdat; /* time & date stamp */ |
unsigned long f_symptr; /* file pointer to symtab */ |
unsigned long f_nsyms; /* number of symtab entries */ |
unsigned short f_opthdr; /* sizeof(optional hdr) */ |
unsigned short f_flags; /* flags */ |
}; |
/* Bits for f_flags: |
* F_RELFLG relocation info stripped from file |
* F_EXEC file is executable (no unresolved external references) |
* F_LNNO line numbers stripped from file |
* F_LSYMS local symbols stripped from file |
* F_AR32WR file has byte ordering of an AR32WR machine (e.g. vax) |
*/ |
#define F_RELFLG (0x0001) |
#define F_EXEC (0x0002) |
#define F_LNNO (0x0004) |
#define F_LSYMS (0x0008) |
/*********************************************************************/ |
struct external_scnhdr { |
char s_name[8]; /* section name */ |
unsigned long s_paddr; /* physical address, aliased s_nlib */ |
unsigned long s_vaddr; /* virtual address */ |
unsigned long s_size; /* section size */ |
unsigned long s_scnptr; /* file ptr to raw data for section */ |
unsigned long s_relptr; /* file ptr to relocation */ |
unsigned long s_lnnoptr; /* file ptr to line numbers */ |
unsigned short s_nreloc; /* number of relocation entries */ |
unsigned short s_nlnno; /* number of line number entries*/ |
unsigned long s_flags; /* flags */ |
}; |
#define SCNHDR struct external_scnhdr |
#define SCNHSZ sizeof(SCNHDR) |
/* |
* names of "special" sections |
*/ |
#define _TEXT ".text" |
#define _DATA ".data" |
#define _BSS ".bss" |
#define _COMMENT ".comment" |
#define _LIB ".lib" |
/* |
* s_flags "type" |
*/ |
#define STYP_TEXT (0x0020) /* section contains text only */ |
#define STYP_DATA (0x0040) /* section contains data only */ |
#define STYP_BSS (0x0080) /* section contains bss only */ |
/*********************************************************************/ |
struct lineno |
{ |
union |
{ |
long l_symndx; /* symtbl index of func name */ |
long l_paddr; /* paddr of line number */ |
} l_addr; |
unsigned short l_lnno; /* line number */ |
}; |
#define LINENO struct lineno |
#define LINESZ 6 |
#define N_UNDEF ((short)0) /* undefined symbol */ |
#define N_ABS ((short)-1) /* value of symbol is absolute */ |
#define N_DEBUG ((short)-2) /* debugging symbol -- value is meaningless */ |
/********************** STORAGE CLASSES **********************/ |
/* This used to be defined as -1, but now n_sclass is unsigned. */ |
#define C_EFCN 0xff /* physical end of function */ |
#define C_NULL 0 |
#define C_AUTO 1 /* automatic variable */ |
#define C_EXT 2 /* external symbol */ |
#define C_STAT 3 /* static */ |
#define C_REG 4 /* register variable */ |
#define C_EXTDEF 5 /* external definition */ |
#define C_LABEL 6 /* label */ |
#define C_ULABEL 7 /* undefined label */ |
#define C_MOS 8 /* member of structure */ |
#define C_ARG 9 /* function argument */ |
#define C_STRTAG 10 /* structure tag */ |
#define C_MOU 11 /* member of union */ |
#define C_UNTAG 12 /* union tag */ |
#define C_TPDEF 13 /* type definition */ |
#define C_USTATIC 14 /* undefined static */ |
#define C_ENTAG 15 /* enumeration tag */ |
#define C_MOE 16 /* member of enumeration */ |
#define C_REGPARM 17 /* register parameter */ |
#define C_FIELD 18 /* bit field */ |
#define C_AUTOARG 19 /* auto argument */ |
#define C_LASTENT 20 /* dummy entry (end of block) */ |
#define C_BLOCK 100 /* ".bb" or ".eb" */ |
#define C_FCN 101 /* ".bf" or ".ef" */ |
#define C_EOS 102 /* end of structure */ |
#define C_FILE 103 /* file name */ |
#define C_LINE 104 /* line # reformatted as symbol table entry */ |
#define C_ALIAS 105 /* duplicate tag */ |
#define C_HIDDEN 106 /* ext symbol in dmert public lib */ |
#define E_SYMNMLEN 8 /* # characters in a symbol name */ |
#define E_FILNMLEN 14 /* # characters in a file name */ |
#define E_DIMNUM 4 /* # array dimensions in auxiliary entry */ |
struct syment |
{ |
union |
{ |
char _n_name[E_SYMNMLEN]; /* symbol name*/ |
struct |
{ |
long _n_zeroes; /* symbol name */ |
long _n_offset; /* location in string table */ |
} _n_n; |
char *_n_nptr[2]; /* allows overlaying */ |
} _n; |
unsigned long n_value; /* value of symbol */ |
short n_scnum; /* section number */ |
unsigned short n_type; /* type and derived */ |
char n_sclass; /* storage class */ |
char n_numaux; /* number of aux entries */ |
}; |
#define n_name _n._n_name |
#define n_zeroes _n._n_n._n_zeroes |
#define n_offset _n._n_n._n_offset |
#define n_nptr _n._n_nptr[1] |
#define SYMNMLEN 8 |
#define SYMESZ 18 /* size of a symbol table entry */ |
union auxent |
{ |
struct |
{ |
long x_tagndx; |
union |
{ |
struct |
{ |
unsigned short x_lnno; |
unsigned short x_size; |
} x_lnsz; |
long x_fsize; |
} x_misc; |
union |
{ |
struct |
{ |
long x_lnnoptr; |
long x_endndx; |
} x_fcn; |
struct |
{ |
unsigned short x_dimen[E_DIMNUM]; |
} x_ary; |
} x_fcnary; |
unsigned short x_tvndx; |
} x_sym; |
union |
{ |
char x_fname[E_FILNMLEN]; |
struct { |
unsigned long x_zeroes; |
unsigned long x_offset; |
} x_n; |
} x_file; |
struct |
{ |
long x_scnlen; |
unsigned short x_nreloc; |
unsigned short x_nlinno; |
} x_scn; |
struct |
{ |
long x_tvfill; |
unsigned short x_tvlen; |
unsigned short x_tvran[2]; |
} x_tv; |
}; |
#define FILNMLEN 14 |
#define DIMNUM 4 |
#define AUXENT union auxent |
#define AUXESZ 18 |
/* Coff additions */ |
typedef struct ListNodeTag{ |
struct ListNodeTag *Next; /* Double Linked List */ |
struct ListNodeTag *Last; /* Double Linked List */ |
void *pObject; /* points to list object */ |
unsigned long Size; |
int FileNumber; /* corresponds to individual file(s) */ |
} LISTNODE; |
//#define LISTNODE struct ListNodeTag; |
typedef struct ListNodeHeadTag { |
LISTNODE Node; |
// struct ListNodeTag *Next; /* Double Linked List */ |
// struct ListNodeTag *Last; /* Double Linked List */ |
int TotalBytes; /* size of allocated object(s) */ |
int TotalItems; /* number of allocated objects */ |
LISTNODE *current; /* pointer for FindFirst/FindNext */ |
} LISTNODEHEAD ; |
typedef struct { |
unsigned short StabType; |
unsigned short CoffType; |
unsigned short ByteSize; |
unsigned short Line; /* used by arrays */ |
unsigned short Dimensions[6]; /* used by arrays */ |
} STABCOFFMAP; |
struct coff_info { |
int CurrentFileNumber; |
int FunctionStartLine; /* used in Line number table */ |
int CurrentSourceLine; |
/* Internal */ |
unsigned char *pRomMemory; /* 16 bit wide words/addresses */ |
unsigned char *pEEPRomMemory; /* 8 bit wide words/addresses */ |
int MaxRomAddress; |
int MaxEepromAddress; |
int NeedLineNumberFixup; |
int GlobalStartAddress; |
int GlobalEndAddress; |
LISTNODEHEAD ListOfSplitLines; |
/* External */ |
struct external_filehdr FileHeader; /* Only one of these per output file */ |
LISTNODEHEAD ListOfSectionHeaders; /* .text, .bss */ |
LISTNODEHEAD ListOfRawData; /* Program, EEPROM */ |
LISTNODEHEAD ListOfRelocations; /* Not used now */ |
LISTNODEHEAD ListOfLineNumbers; |
LISTNODEHEAD ListOfSymbols; |
LISTNODEHEAD ListOfGlobals; |
LISTNODEHEAD ListOfSpecials; |
LISTNODEHEAD ListOfUndefined; |
LISTNODEHEAD ListOfStrings; |
LISTNODEHEAD ListOfTypes; |
}; |
#if 0 /* defined in avra.h */ |
FILE *open_coff_file(struct prog_info *pi, char *filename); |
void write_coff_file(struct prog_info *pi); |
void write_coff_eeprom( struct prog_info *pi, int address, unsigned char data); |
void write_coff_program( struct prog_info *pi, int address, unsigned char data); |
void close_coff_file(struct prog_info *pi, FILE *fp); |
int parse_stabs( struct prog_info *pi, char *p ); |
int parse_stabn( struct prog_info *pi, char *p ); |
#endif |
/**************************************************************/ |
/*********** Internal Routines ********************************/ |
/**************************************************************/ |
int stab_add_lineno( struct prog_info *pi, int LineNumber, char *pLabel, char *pFunction ); |
int stab_add_lbracket( struct prog_info *pi, int Level, char *pLabel, char *pFunction ); |
int stab_add_rbracket( struct prog_info *pi, int Level, char *pLabel, char *pFunction ); |
int stab_add_filename( char *pName, char *pLabel ); |
int stab_add_function( struct prog_info *pi, char *pName, char *pLabel ); |
int stab_add_global( struct prog_info *pi, char *pName, char *pType ); |
int stab_add_local( struct prog_info *pi, char *pName, char *pType, char *pOffset ); |
int stab_add_parameter_symbol( struct prog_info *pi, char *pName, char *pType, char *pOffset ); |
int stab_add_static_symbol( struct prog_info *pi, char *pName, char *pType, char *pLabel ); |
int stab_add_local_register( struct prog_info *pi, char *pName, char *pType, char *pRegister ); |
int stab_add_local_type( char *pString, char *pType ); |
int stab_add_tag_type( char *pName, char *pDesciptor ); |
int GetStabType( char *p, unsigned short *pType, char **pEnd ); |
int AddNameToEntry( char *pName, struct syment *pEntry ); |
int GetArrayType( char *p, char **pEnd, STABCOFFMAP *pMap, unsigned short *DerivedBits, int ExtraLevels ); |
int GetEnumTagItem( char *p, char **pEnd, char **pEnumName, int *pEnumValue ); |
int GetStructUnionTagItem( char *p, char **pEnd, char **pName, unsigned short *pType, unsigned short *pBitOffset, unsigned short *pBitSize); |
int GetStringDelimiters( char *pString, char **pTokens, int MaxTokens ); |
int SetupDefinedType( unsigned short Type, STABCOFFMAP *pMap, unsigned short *DerivedBits, int ExtraLevels ); |
int GetArrayDefinitions( STABCOFFMAP *pMap , char *pMinIndex, char *pMaxIndex, char *pType, unsigned short *DerivedBits, int ExtraLevels ); |
int GetInternalType( char *pName, STABCOFFMAP *pMap ); |
unsigned short GetCoffType( unsigned short StabType ); |
unsigned short GetCoffTypeSize( unsigned short StabType ); |
int CopyStabCoffMap( unsigned short StabType, STABCOFFMAP *pMap ); |
int IsTypeArray( unsigned short CoffType ); |
void AddArrayAuxInfo( union auxent *pAux, unsigned short SymbolIndex, STABCOFFMAP *pMap ); |
int GetSubRangeType( unsigned short Type, STABCOFFMAP *pMap , char *pLow, char *pHigh ); |
char *SkipPastDigits( char *p ); |
int GetDigitLength( char *p ); |
/****************************************************************************************/ |
/* List management routines */ |
/****************************************************************************************/ |
void InitializeList( LISTNODEHEAD *pNode ); |
void *AllocateTwoListObjects( LISTNODEHEAD *pHead, int size ); |
void *AllocateListObject( LISTNODEHEAD *pHead, int size ); |
LISTNODE *AllocateListNode( void *pObject, int size ); |
void AddNodeToList( LISTNODEHEAD *pHead, LISTNODE *pNode ); |
void *FindFirstListObject( LISTNODEHEAD *pHead ); |
void *FindNextListObject( LISTNODEHEAD *pHead ); |
LISTNODE *GetCurrentNode( LISTNODEHEAD *pHead ); |
void *GetCurrentListObject( LISTNODEHEAD *pHead ); |
void *FindLastListObject( LISTNODEHEAD *pHead ); |
void *FindNextLastListObject( LISTNODEHEAD *pHead ); |
void FreeList( LISTNODEHEAD *pHead ); |
LISTNODE *AddListObject(LISTNODEHEAD *pHead, void *pObject, int size ); |
/contrib/toolchain/avra/src/device.c |
---|
0,0 → 1,214 |
/*********************************************************************** |
* |
* avra - Assembler for the Atmel AVR microcontroller series |
* |
* Copyright (C) 1998-2010 Jon Anders Haugum, Tobias Weber, Jerry Jacobs |
* |
* This program is free software; you can redistribute it and/or modify |
* it under the terms of the GNU General Public License as published by |
* the Free Software Foundation; either version 2 of the License, or |
* (at your option) any later version. |
* |
* This program is distributed in the hope that it will be useful, |
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
* GNU General Public License for more details. |
* |
* You should have received a copy of the GNU General Public License |
* along with this program; see the file COPYING. If not, write to |
* the Free Software Foundation, Inc., 59 Temple Place - Suite 330, |
* Boston, MA 02111-1307, USA. |
* |
* |
* Authors of avra can be reached at: |
* email: jonah@omegav.ntnu.no, tobiw@suprafluid.com |
* www: http://sourceforge.net/projects/avra |
* |
*/ |
#include <stdlib.h> |
#include <string.h> |
#include "misc.h" |
#include "avra.h" |
#include "device.h" |
#define DEV_VAR "__DEVICE__" // Device var name |
#define FLASH_VAR "__FLASH_SIZE__" // Flash size var name |
#define EEPROM_VAR "__EEPROM_SIZE__" // EEPROM size var name |
#define RAM_VAR "__RAM_SIZE__" // RAM size var name |
#define DEV_PREFIX "__" // Device name prefix |
#define DEV_SUFFIX "__" // Device name suffix |
#define DEF_DEV_NAME "DEFAULT" // Default device name (without prefix/suffix) |
#define MAX_DEV_NAME 32 // Max device name length |
struct device device_list[] = |
{ |
/* Name, Flash(words),RAM start, RAM size, EEPROM, flags */ |
{ NULL, 4194304, 0x60, 8388608, 65536, 0}, // Total instructions: 137 |
/* ATtiny Series */ |
// ATtiny4 |
// ATtiny5 |
// ATtiny9 |
{ "ATtiny10", 512, 0x00, 0, 0, DF_NO_MUL|DF_NO_JMP|DF_TINY1X|DF_NO_XREG|DF_NO_YREG|DF_NO_LPM_X|DF_NO_ELPM|DF_NO_SPM|DF_NO_ESPM|DF_NO_MOVW|DF_NO_BREAK|DF_NO_EICALL|DF_NO_EIJMP}, |
{ "ATtiny11", 512, 0x00, 0, 0, DF_NO_MUL|DF_NO_JMP|DF_TINY1X|DF_NO_XREG|DF_NO_YREG|DF_NO_LPM_X|DF_NO_ELPM|DF_NO_SPM|DF_NO_ESPM|DF_NO_MOVW|DF_NO_BREAK|DF_NO_EICALL|DF_NO_EIJMP}, |
{ "ATtiny12", 512, 0x00, 0, 64, DF_NO_MUL|DF_NO_JMP|DF_TINY1X|DF_NO_XREG|DF_NO_YREG|DF_NO_LPM_X|DF_NO_ELPM|DF_NO_SPM|DF_NO_ESPM|DF_NO_MOVW|DF_NO_BREAK|DF_NO_EICALL|DF_NO_EIJMP}, |
{ "ATtiny13", 512, 0x60, 64, 64, DF_NO_MUL|DF_NO_JMP|DF_NO_ELPM|DF_NO_ESPM|DF_NO_EICALL|DF_NO_EIJMP}, |
{ "ATtiny13A", 512, 0x60, 64, 64, DF_NO_MUL|DF_NO_JMP|DF_NO_ELPM|DF_NO_ESPM|DF_NO_EICALL|DF_NO_EIJMP}, |
{ "ATtiny15", 512, 0x00, 0, 64, DF_NO_MUL|DF_NO_JMP|DF_TINY1X|DF_NO_XREG|DF_NO_YREG|DF_NO_LPM_X|DF_NO_ELPM|DF_NO_SPM|DF_NO_ESPM|DF_NO_MOVW|DF_NO_BREAK|DF_NO_EICALL|DF_NO_EIJMP}, |
// ATtiny20 |
{ "ATtiny22", 1024, 0x60, 128, 128, DF_NO_MUL|DF_NO_JMP|DF_NO_LPM_X|DF_NO_ELPM|DF_NO_SPM|DF_NO_ESPM|DF_NO_MOVW|DF_NO_BREAK|DF_NO_EICALL|DF_NO_EIJMP}, |
{ "ATtiny24", 1024, 0x60, 128, 128, DF_NO_MUL|DF_NO_JMP|DF_NO_ELPM|DF_NO_ESPM|DF_NO_EICALL|DF_NO_EIJMP}, |
{ "ATtiny24A", 1024, 0x60, 128, 128, DF_NO_MUL|DF_NO_JMP|DF_NO_ELPM|DF_NO_ESPM|DF_NO_EICALL|DF_NO_EIJMP}, |
{ "ATtiny25", 1024, 0x60, 128, 128, DF_NO_MUL|DF_NO_JMP|DF_NO_ELPM|DF_NO_ESPM|DF_NO_EICALL|DF_NO_EIJMP}, |
{ "ATtiny26", 1024, 0x60, 128, 128, DF_NO_MUL|DF_NO_JMP|DF_NO_ELPM|DF_NO_SPM|DF_NO_ESPM|DF_NO_MOVW|DF_NO_BREAK|DF_NO_EICALL|DF_NO_EIJMP}, |
{ "ATtiny28", 1024, 0x00, 0, 0, DF_NO_MUL|DF_NO_JMP|DF_TINY1X|DF_NO_XREG|DF_NO_YREG|DF_NO_LPM_X|DF_NO_ELPM|DF_NO_SPM|DF_NO_ESPM|DF_NO_MOVW|DF_NO_BREAK|DF_NO_EICALL|DF_NO_EIJMP}, |
// ATtiny43U |
{ "ATtiny44", 2048, 0x60, 256, 256, DF_NO_MUL|DF_NO_JMP|DF_NO_ELPM|DF_NO_ESPM|DF_NO_EICALL|DF_NO_EIJMP}, |
{ "ATtiny44A", 2048, 0x60, 256, 256, DF_NO_MUL|DF_NO_JMP|DF_NO_ELPM|DF_NO_ESPM|DF_NO_EICALL|DF_NO_EIJMP}, |
{ "ATtiny45", 2048, 0x60, 256, 256, DF_NO_MUL|DF_NO_JMP|DF_NO_ELPM|DF_NO_ESPM|DF_NO_EICALL|DF_NO_EIJMP}, |
{ "ATtiny84", 4096, 0x60, 512, 512, DF_NO_MUL|DF_NO_JMP|DF_NO_ELPM|DF_NO_ESPM|DF_NO_EICALL|DF_NO_EIJMP}, |
{ "ATtiny85", 4096, 0x60, 512, 512, DF_NO_MUL|DF_NO_JMP|DF_NO_ELPM|DF_NO_ESPM|DF_NO_EICALL|DF_NO_EIJMP}, |
// ATtiny87 |
// ATtiny167 |
// ATtiny261A |
// ATtiny461A |
// ATtiny861A |
{ "ATtiny2313", 1024, 0x60, 128, 128, DF_NO_MUL|DF_NO_JMP|DF_NO_ELPM|DF_NO_ESPM|DF_NO_EICALL|DF_NO_EIJMP}, |
{ "ATtiny2313A", 1024, 0x60, 128, 128, DF_NO_MUL|DF_NO_JMP|DF_NO_ELPM|DF_NO_ESPM|DF_NO_EICALL|DF_NO_EIJMP}, |
{ "ATtiny4313", 2048, 0x60, 256, 256, DF_NO_MUL|DF_NO_JMP|DF_NO_ELPM|DF_NO_ESPM|DF_NO_EICALL|DF_NO_EIJMP}, |
/* AT90 series */ |
{ "AT90S1200", 512, 0x00, 0, 64, DF_NO_MUL|DF_NO_JMP|DF_TINY1X|DF_NO_XREG|DF_NO_YREG|DF_NO_LPM|DF_NO_ELPM|DF_NO_SPM|DF_NO_ESPM|DF_NO_MOVW|DF_NO_BREAK|DF_NO_EICALL|DF_NO_EIJMP}, // 137 - MUL(6) - JMP(2) - TINY(10) |
{ "AT90S2313", 1024, 0x60, 128, 128, DF_NO_MUL|DF_NO_JMP|DF_NO_LPM_X|DF_NO_ELPM|DF_NO_SPM|DF_NO_ESPM|DF_NO_MOVW|DF_NO_BREAK|DF_NO_EICALL|DF_NO_EIJMP}, |
{ "AT90S2323", 1024, 0x60, 128, 128, DF_NO_MUL|DF_NO_JMP|DF_NO_LPM_X|DF_NO_ELPM|DF_NO_SPM|DF_NO_ESPM|DF_NO_MOVW|DF_NO_BREAK|DF_NO_EICALL|DF_NO_EIJMP}, |
{ "AT90S2333", 1024, 0x60, 128, 128, DF_NO_MUL|DF_NO_JMP|DF_NO_LPM_X|DF_NO_ELPM|DF_NO_SPM|DF_NO_ESPM|DF_NO_MOVW|DF_NO_BREAK|DF_NO_EICALL|DF_NO_EIJMP}, |
{ "AT90S2343", 1024, 0x60, 128, 128, DF_NO_MUL|DF_NO_JMP|DF_NO_LPM_X|DF_NO_ELPM|DF_NO_SPM|DF_NO_ESPM|DF_NO_MOVW|DF_NO_BREAK|DF_NO_EICALL|DF_NO_EIJMP}, |
{ "AT90S4414", 2048, 0x60, 256, 256, DF_NO_MUL|DF_NO_JMP|DF_NO_LPM_X|DF_NO_ELPM|DF_NO_SPM|DF_NO_ESPM|DF_NO_MOVW|DF_NO_BREAK|DF_NO_EICALL|DF_NO_EIJMP}, |
{ "AT90S4433", 2048, 0x60, 128, 256, DF_NO_MUL|DF_NO_JMP|DF_NO_LPM_X|DF_NO_ELPM|DF_NO_SPM|DF_NO_ESPM|DF_NO_MOVW|DF_NO_BREAK|DF_NO_EICALL|DF_NO_EIJMP}, |
{ "AT90S4434", 2048, 0x60, 256, 256, DF_NO_MUL|DF_NO_JMP|DF_NO_LPM_X|DF_NO_ELPM|DF_NO_SPM|DF_NO_ESPM|DF_NO_MOVW|DF_NO_BREAK|DF_NO_EICALL|DF_NO_EIJMP}, |
{ "AT90S8515", 4096, 0x60, 512, 512, DF_NO_MUL|DF_NO_JMP|DF_NO_LPM_X|DF_NO_ELPM|DF_NO_SPM|DF_NO_ESPM|DF_NO_MOVW|DF_NO_BREAK|DF_NO_EICALL|DF_NO_EIJMP}, // 137 - MUL(6) - JMP(2) - LPM_X(2) - ELPM(3) - SPM - ESPM - MOVW - BREAK - EICALL - EIJMP = 118 |
{ "AT90C8534", 4096, 0x60, 256, 512, DF_NO_MUL|DF_NO_JMP|DF_NO_LPM_X|DF_NO_ELPM|DF_NO_SPM|DF_NO_ESPM|DF_NO_MOVW|DF_NO_BREAK|DF_NO_EICALL|DF_NO_EIJMP}, |
{ "AT90S8535", 4096, 0x60, 512, 512, DF_NO_MUL|DF_NO_JMP|DF_NO_LPM_X|DF_NO_ELPM|DF_NO_SPM|DF_NO_ESPM|DF_NO_MOVW|DF_NO_BREAK|DF_NO_EICALL|DF_NO_EIJMP}, |
/* AT90USB series*/ |
// AT90USB168 |
// AT90USB1287 |
/* ATmega series */ |
{ "ATmega8", 4096, 0x60, 1024, 512, DF_NO_JMP|DF_NO_EICALL|DF_NO_EIJMP|DF_NO_ELPM|DF_NO_ESPM}, |
{ "ATmega161", 8192, 0x60, 1024, 512, DF_NO_EICALL|DF_NO_EIJMP|DF_NO_ELPM|DF_NO_ESPM}, |
{ "ATmega162", 8192, 0x100, 1024, 512, DF_NO_EICALL|DF_NO_EIJMP|DF_NO_ELPM|DF_NO_ESPM}, |
{ "ATmega163", 8192, 0x60, 1024, 512, DF_NO_EICALL|DF_NO_EIJMP|DF_NO_ELPM|DF_NO_ESPM}, |
{ "ATmega16", 8192, 0x60, 1024, 512, DF_NO_EICALL|DF_NO_EIJMP|DF_NO_ELPM|DF_NO_ESPM}, |
{ "ATmega323", 16384, 0x60, 2048, 1024, DF_NO_EICALL|DF_NO_EIJMP|DF_NO_ELPM|DF_NO_ESPM}, // 137 - EICALL - EIJMP - ELPM(3) - ESPM = 131 (Data sheet says 130 but it's wrong) |
{ "ATmega328P", 16384, 0x100, 2048, 1024, DF_NO_EICALL|DF_NO_EIJMP|DF_NO_ELPM|DF_NO_ESPM}, |
{ "ATmega32", 16384, 0x60, 2048, 1024, DF_NO_EICALL|DF_NO_EIJMP|DF_NO_ELPM|DF_NO_ESPM}, |
{ "ATmega603", 32768, 0x60, 4096, 2048, DF_NO_EICALL|DF_NO_EIJMP|DF_NO_MUL|DF_NO_MOVW|DF_NO_LPM_X|DF_NO_ELPM|DF_NO_SPM|DF_NO_ESPM|DF_NO_BREAK}, |
{ "ATmega103", 65536, 0x60, 4096, 4096, DF_NO_EICALL|DF_NO_EIJMP|DF_NO_MUL|DF_NO_MOVW|DF_NO_LPM_X|DF_NO_ELPM_X|DF_NO_SPM|DF_NO_ESPM|DF_NO_BREAK}, // 137 - EICALL - EIJMP - MUL(6) - MOVW - LPM_X(2) - ELPM_X(2) - SPM - ESPM - BREAK = 121 |
{ "ATmega104", 65536, 0x60, 4096, 4096, DF_NO_EICALL|DF_NO_EIJMP|DF_NO_ESPM}, // Old name for mega128 |
{ "ATmega128", 65536, 0x100, 4096, 4096, DF_NO_EICALL|DF_NO_EIJMP|DF_NO_ESPM}, // 137 - EICALL - EIJMP - ESPM = 134 (Data sheet says 133 but it's wrong) |
{ "ATmega48", 2048, 0x100, 512, 256, DF_NO_EICALL|DF_NO_EIJMP|DF_NO_ELPM|DF_NO_ESPM}, |
{ "ATmega88", 4096, 0x100, 1024, 512, DF_NO_EICALL|DF_NO_EIJMP|DF_NO_ELPM|DF_NO_ESPM}, |
{ "ATmega168", 8192, 0x100, 1024, 512, DF_NO_EICALL|DF_NO_EIJMP|DF_NO_ELPM|DF_NO_ESPM}, |
{ "ATmega8515", 8192, 0x60, 512, 512, DF_NO_EICALL|DF_NO_EIJMP|DF_NO_ELPM|DF_NO_ESPM}, |
/* Other */ |
{ "AT94K", 8192, 0x60, 16384, 0, DF_NO_EICALL|DF_NO_EIJMP|DF_NO_ELPM|DF_NO_SPM|DF_NO_ESPM|DF_NO_BREAK}, // 137 - EICALL - EIJMP - ELPM(3) - SPM - ESPM - BREAK = 129 |
{NULL, 0, 0, 0, 0} |
}; |
static int LastDevice=0; |
/*********************************************/ |
/* Define vars for device in LastDevice */ |
/*********************************************/ |
static void def_dev(struct prog_info *pi) |
{ |
def_var(pi,DEV_VAR,LastDevice); |
def_var(pi,FLASH_VAR,device_list[LastDevice].flash_size); |
def_var(pi,EEPROM_VAR,device_list[LastDevice].eeprom_size); |
def_var(pi,RAM_VAR,device_list[LastDevice].ram_size); |
} |
struct device *get_device(struct prog_info *pi, char *name) |
{ |
int i = 1; |
LastDevice = 0; |
if(name == NULL) { |
def_dev(pi); |
return(&device_list[0]); |
} |
while(device_list[i].name) { |
if(!nocase_strcmp(name, device_list[i].name)) { |
LastDevice=i; |
def_dev(pi); |
return(&device_list[i]); |
} |
i++; |
} |
def_dev(pi); |
return(NULL); |
} |
// Pre-define devices. B.A. : Return value change from void to int |
int predef_dev(struct prog_info *pi) |
{ |
int i; |
char temp[MAX_DEV_NAME+1]; |
def_dev(pi); |
for (i=0;(!i)||(device_list[i].name);i++) { |
strncpy(temp,DEV_PREFIX,MAX_DEV_NAME); |
if (!i) strncat(temp,DEF_DEV_NAME,MAX_DEV_NAME); |
else strncat(temp,device_list[i].name,MAX_DEV_NAME); |
strncat(temp,DEV_SUFFIX,MAX_DEV_NAME); |
/* B.A. : New. Forward references allowed. But check, if everything is ok ... */ |
if(pi->pass==PASS_1) { /* Pass 1 */ |
if(test_constant(pi,temp,NULL)!=NULL) { |
fprintf(stderr,"Error: Can't define symbol %s twice. Please don't use predefined symbols !\n", temp); |
return(False); |
} |
if(def_const(pi, temp, i)==False) |
return(False); |
} else { /* Pass 2 */ |
int j; |
if(get_constant(pi, temp, &j)==False) { /* Defined in Pass 1 and now missing ? */ |
fprintf(stderr,"Constant %s is missing in pass 2\n",temp); |
return(False); |
} |
if(i != j) { |
fprintf(stderr,"Constant %s changed value from %d in pass1 to %d in pass 2\n",temp,j,i); |
return(False); |
} |
/* OK. definition is unchanged */ |
} |
} |
return(True); |
} |
void list_devices() |
{ |
int i = 1; |
printf("Device name | Flash size | RAM start | RAM size | EEPROM size | Supported\n" |
" | (words) | (bytes) | (bytes) | (bytes) | instructions\n" |
"------------+------------+-----------+----------+-------------+--------------\n" |
" (default) | %7d | 0x%04x | %7d | %5d | %3d\n", |
device_list[0].flash_size, |
device_list[0].ram_start, |
device_list[0].ram_size, |
device_list[0].eeprom_size, |
count_supported_instructions(device_list[0].flag)); |
while(device_list[i].name) { |
printf(" %-10s | %7d | 0x%04x | %7d | %5d | %3d\n", |
device_list[i].name, |
device_list[i].flash_size, |
device_list[i].ram_start, |
device_list[i].ram_size, |
device_list[i].eeprom_size, |
count_supported_instructions(device_list[i].flag)); |
i++; |
} |
} |
/* end of device.c */ |
/contrib/toolchain/avra/src/device.h |
---|
0,0 → 1,33 |
/* Device flags */ |
#define DF_NO_MUL 0x00000001 |
#define DF_NO_JMP 0x00000002 // No JMP, CALL |
#define DF_NO_XREG 0x00000004 // No X register |
#define DF_NO_YREG 0x00000008 // No Y register |
#define DF_TINY1X 0x00000010 /* AT90S1200, ATtiny10-12 set: No ADIW, SBIW, |
IJMP, ICALL, LDD, STD, LDS, STS, PUSH, POP */ |
#define DF_NO_LPM 0x00000020 // No LPM instruction |
#define DF_NO_LPM_X 0x00000040 // No LPM Rd,Z or LPM Rd,Z+ instruction |
#define DF_NO_ELPM 0x00000080 // No ELPM instruction |
#define DF_NO_ELPM_X 0x00000100 // No ELPM Rd,Z or LPM Rd,Z+ instruction |
#define DF_NO_SPM 0x00000200 // No SPM instruction |
#define DF_NO_ESPM 0x00000400 // No ESPM instruction |
#define DF_NO_MOVW 0x00000800 // No MOVW instruction |
#define DF_NO_BREAK 0x00001000 // No BREAK instruction |
#define DF_NO_EICALL 0x00002000 // No EICALL instruction |
#define DF_NO_EIJMP 0x00004000 // No EIJMP instruction |
struct device |
{ |
char *name; |
int flash_size; |
int ram_start; |
int ram_size; |
int eeprom_size; |
int flag; |
}; |
/* device.c */ |
struct device *get_device(struct prog_info *pi,char *name); |
int predef_dev(struct prog_info *pi); |
void list_devices(); |
/contrib/toolchain/avra/src/directiv.c |
---|
0,0 → 1,934 |
/*********************************************************************** |
// Modified at line 252 to print out DW value in list file by davidrjburke@hotmail.com 11 Nov 2005 |
* avra - Assembler for the Atmel AVR microcontroller series |
* |
* Copyright (C) 1998-2004 Jon Anders Haugum, Tobias Weber |
* |
* This program is free software; you can redistribute it and/or modify |
* it under the terms of the GNU General Public License as published by |
* the Free Software Foundation; either version 2 of the License, or |
* (at your option) any later version. |
* |
* This program is distributed in the hope that it will be useful, |
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
* GNU General Public License for more details. |
* |
* You should have received a copy of the GNU General Public License |
* along with this program; see the file COPYING. If not, write to |
* the Free Software Foundation, Inc., 59 Temple Place - Suite 330, |
* Boston, MA 02111-1307, USA. |
* |
* |
* Authors of avra can be reached at: |
* email: jonah@omegav.ntnu.no, tobiw@suprafluid.com |
* www: http://sourceforge.net/projects/avra |
*/ |
#include <stdio.h> |
#include <stdlib.h> |
#include <string.h> |
#include <ctype.h> |
#include "misc.h" |
#include "args.h" |
#include "avra.h" |
#include "device.h" |
enum |
{ |
DIRECTIVE_BYTE = 0, |
DIRECTIVE_CSEG, |
DIRECTIVE_CSEGSIZE, |
DIRECTIVE_DB, |
DIRECTIVE_DEF, |
DIRECTIVE_DEVICE, |
DIRECTIVE_DSEG, |
DIRECTIVE_DW, |
DIRECTIVE_ENDM, |
DIRECTIVE_ENDMACRO, |
DIRECTIVE_EQU, |
DIRECTIVE_ESEG, |
DIRECTIVE_EXIT, |
DIRECTIVE_INCLUDE, |
DIRECTIVE_INCLUDEPATH, |
DIRECTIVE_LIST, |
DIRECTIVE_LISTMAC, |
DIRECTIVE_MACRO, |
DIRECTIVE_NOLIST, |
DIRECTIVE_ORG, |
DIRECTIVE_SET, |
DIRECTIVE_DEFINE, |
DIRECTIVE_UNDEF, |
DIRECTIVE_IFDEF, |
DIRECTIVE_IFNDEF, |
DIRECTIVE_IF, |
DIRECTIVE_ELSE, |
DIRECTIVE_ELSEIF, /* B.A. : The Atmel AVR Assembler version 1.71 and later use ELSEIF and not ELIF */ |
DIRECTIVE_ELIF, |
DIRECTIVE_ENDIF, |
DIRECTIVE_MESSAGE, |
DIRECTIVE_WARNING, |
DIRECTIVE_ERROR, |
DIRECTIVE_PRAGMA, |
DIRECTIVE_COUNT |
}; |
char *directive_list[] = |
{ |
"BYTE", |
"CSEG", |
"CSEGSIZE", |
"DB", |
"DEF", |
"DEVICE", |
"DSEG", |
"DW", |
"ENDM", |
"ENDMACRO", |
"EQU", |
"ESEG", |
"EXIT", |
"INCLUDE", |
"INCLUDEPATH", |
"LIST", |
"LISTMAC", |
"MACRO", |
"NOLIST", |
"ORG", |
"SET", |
"DEFINE", |
"UNDEF", |
"IFDEF", |
"IFNDEF", |
"IF", |
"ELSE", |
"ELSEIF", /* B.A. : The Atmel AVR Assembler version 1.71 and later use ELSEIF and not ELIF */ |
"ELIF", |
"ENDIF", |
"MESSAGE", |
"WARNING", |
"ERROR", |
"PRAGMA" |
}; |
int parse_directive(struct prog_info *pi) |
{ |
int directive; |
int ok = True; |
int i; |
char *next, *data; |
struct file_info *fi_bak; |
struct def *def; |
struct data_list *incpath, *dl; |
next = get_next_token(pi->fi->scratch, TERM_SPACE); |
for(i = 0; pi->fi->scratch[i] != '\0'; i++) { |
pi->fi->scratch[i] = toupper(pi->fi->scratch[i]); |
} |
directive = get_directive_type(pi->fi->scratch + 1); |
if(directive == -1) { |
print_msg(pi, MSGTYPE_ERROR, "Unknown directive: %s", pi->fi->scratch); |
return(True); |
} |
switch(directive) { |
case DIRECTIVE_BYTE: |
if(!next) { |
print_msg(pi, MSGTYPE_ERROR, ".BYTE needs a size operand"); |
return(True); |
} |
if(pi->segment != SEGMENT_DATA) |
print_msg(pi, MSGTYPE_ERROR, ".BYTE directive can only be used in data segment (.DSEG)"); |
get_next_token(next, TERM_END); |
if(!get_expr(pi, next, &i)) |
return(False); |
if((pi->pass == PASS_2) && pi->list_line && pi->list_on) { |
fprintf(pi->list_file, "D:%06x %s\n", pi->dseg_addr, pi->list_line); |
pi->list_line = NULL; |
} |
pi->dseg_addr += i; |
if(pi->pass == PASS_1) |
pi->dseg_count += i; |
break; |
case DIRECTIVE_CSEG: |
fix_orglist(pi); |
pi->segment = SEGMENT_CODE; |
def_orglist(pi); |
break; |
case DIRECTIVE_CSEGSIZE: |
break; |
case DIRECTIVE_DB: |
if((pi->pass == PASS_2) && pi->list_line && pi->list_on) { |
fprintf(pi->list_file, " %s\n", pi->list_line); |
pi->list_line = NULL; |
} |
return(parse_db(pi, next)); |
// break; |
/* Directive .def */ |
case DIRECTIVE_DEF: |
if(!next) { |
print_msg(pi, MSGTYPE_ERROR, ".DEF needs an operand"); |
return(True); |
} |
data = get_next_token(next, TERM_EQUAL); |
if(!(data && (tolower(data[0]) == 'r') && isdigit(data[1]))) { |
print_msg(pi, MSGTYPE_ERROR, "%s needs a register (e.g. .def BZZZT = r16)", next); |
return(True); |
} |
i = atoi(&data[1]); |
/* check range of given register */ |
if(i > 31) |
print_msg(pi, MSGTYPE_ERROR, "R%d is not a valid register", i); |
/* check if this reg is already assigned */ |
for(def = pi->first_def; def; def = def->next) { |
if(def->reg == i && pi->pass == PASS_1 && !pi->NoRegDef) { |
print_msg(pi, MSGTYPE_WARNING, "r%d is already assigned to '%s'!", i, def->name); |
return(True); |
} |
} |
/* check if this regname is already defined */ |
for(def = pi->first_def; def; def = def->next) { |
if(!nocase_strcmp(def->name, next)) { |
if(pi->pass == PASS_1 && !pi->NoRegDef) { |
print_msg(pi, MSGTYPE_WARNING, "'%s' is already assigned as r%d but will now be set to r%i!", next, def->reg, i); |
} |
def->reg = i; |
return(True); |
} |
} |
/* B.A.: Check, if symbol is already defined as a label or constant */ |
if(pi->pass == PASS_2) { |
if(get_label(pi,next,NULL)) |
print_msg(pi, MSGTYPE_WARNING, "Name '%s' is used for a register and a label", next); |
if(get_constant(pi,next,NULL)) |
print_msg(pi, MSGTYPE_WARNING, "Name '%s' is used for a register and a constant", next); |
} |
def = malloc(sizeof(struct def)); |
if(!def) { |
print_msg(pi, MSGTYPE_OUT_OF_MEM, NULL); |
return(False); |
} |
def->next = NULL; |
if(pi->last_def) |
pi->last_def->next = def; |
else |
pi->first_def = def; |
pi->last_def = def; |
def->name = malloc(strlen(next) + 1); |
if(!def->name) { |
print_msg(pi, MSGTYPE_OUT_OF_MEM, NULL); |
return(False); |
} |
strcpy(def->name, next); |
def->reg = i; |
break; |
case DIRECTIVE_DEVICE: |
if(pi->pass == PASS_2) |
return(True); |
if(!next) { |
print_msg(pi, MSGTYPE_ERROR, ".DEVICE needs an operand"); |
return(True); |
} |
if(pi->device->name!=NULL) { /* B.A.: Check for multiple device definitions */ |
print_msg(pi, MSGTYPE_ERROR, "More than one .DEVICE definition"); |
} |
if(pi->cseg_count || pi->dseg_count || pi->eseg_count) { /* B.A.: Check if something was already assembled */ |
print_msg(pi, MSGTYPE_ERROR, ".DEVICE definition must be before any code lines"); |
} else { |
if(pi->cseg_addr || pi->eseg_addr || (pi->dseg_addr != pi->device->ram_start)) { /* B.A.: Check if something was already assembled */ |
print_msg(pi, MSGTYPE_ERROR, ".DEVICE definition must be before any .ORG directive"); |
} |
} |
get_next_token(next, TERM_END); |
pi->device = get_device(pi,next); |
if(!pi->device) { |
print_msg(pi, MSGTYPE_ERROR, "Unknown device: %s", next); |
pi->device = get_device(pi,NULL); /* B.A.: Fix segmentation fault if device is unknown */ |
} |
/* Now that we know the device type, we can |
* start memory allocation from the correct offsets. |
*/ |
fix_orglist(pi); |
pi->cseg_addr = 0; |
pi->dseg_addr = pi->device->ram_start; |
pi->eseg_addr = 0; |
def_orglist(pi); |
break; |
case DIRECTIVE_DSEG: |
fix_orglist(pi); |
pi->segment = SEGMENT_DATA; |
def_orglist(pi); |
if(pi->device->ram_size == 0) { |
print_msg(pi, MSGTYPE_ERROR, "Can't use .DSEG directive because device has no RAM"); |
} |
break; |
case DIRECTIVE_DW: |
if(pi->segment == SEGMENT_DATA) { |
print_msg(pi, MSGTYPE_ERROR, "Can't use .DW directive in data segment (.DSEG)"); |
return(True); |
} |
while(next) { |
data = get_next_token(next, TERM_COMMA); |
if(pi->pass == PASS_2) { |
if(!get_expr(pi, next, &i)) |
return(False); |
if((i < -32768) || (i > 65535)) |
print_msg(pi, MSGTYPE_WARNING, "Value %d is out of range (-32768 <= k <= 65535). Will be masked", i); |
} |
if(pi->segment == SEGMENT_EEPROM) { |
if(pi->pass == PASS_2) { |
write_ee_byte(pi, pi->eseg_addr, (unsigned char)i); |
write_ee_byte(pi, pi->eseg_addr + 1, (unsigned char)(i >> 8)); |
} |
pi->eseg_addr += 2; |
if(pi->pass == PASS_1) |
pi->eseg_count += 2; |
} |
// Modified by David Burke to print DW word in list file 4/Nov/2005 |
else { |
if((pi->pass == PASS_2) && pi->hfi) { |
write_prog_word(pi, pi->cseg_addr, i); |
// Actual fiddling |
if((pi->pass == PASS_2) && pi->list_line && pi->list_on) { |
fprintf(pi->list_file, " %s\n", pi->list_line); |
pi->list_line = NULL; |
fprintf(pi->list_file, "C:%06x %04x\n", pi->cseg_addr,i); |
} |
} |
pi->cseg_addr++; |
if(pi->pass == PASS_1) pi->cseg_count++; |
} |
// End of Modification by David Burke |
next = data; |
} |
break; |
case DIRECTIVE_ENDM: |
case DIRECTIVE_ENDMACRO: |
print_msg(pi, MSGTYPE_ERROR, "No .MACRO found before .ENDMACRO"); |
break; |
case DIRECTIVE_EQU: |
if(!next) { |
print_msg(pi, MSGTYPE_ERROR, ".EQU needs an operand"); |
return(True); |
} |
data = get_next_token(next, TERM_EQUAL); |
if(!data) { |
print_msg(pi, MSGTYPE_ERROR, "%s needs an expression (e.g. .EQU BZZZT = 0x2a)", next); |
return(True); |
} |
get_next_token(data, TERM_END); |
if(!get_expr(pi, data, &i)) |
return(False); |
if(test_label(pi,next,"%s have already been defined as a label")!=NULL) |
return(True); |
if(test_variable(pi,next,"%s have already been defined as a .SET variable")!=NULL) |
return(True); |
/* B.A. : New. Forward references allowed. But check, if everything is ok ... */ |
if(pi->pass==PASS_1) { /* Pass 1 */ |
if(test_constant(pi,next,"Can't redefine constant %s, use .SET instead")!=NULL) |
return(True); |
if(def_const(pi, next, i)==False) |
return(False); |
} else { /* Pass 2 */ |
int j; |
if(get_constant(pi, next, &j)==False) { /* Defined in Pass 1 and now missing ? */ |
print_msg(pi, MSGTYPE_ERROR, "Constant %s is missing in pass 2", next); |
return(False); |
} |
if(i != j) { |
print_msg(pi, MSGTYPE_ERROR, "Constant %s changed value from %d in pass1 to %d in pass 2", next,j,i); |
return(False); |
} |
/* OK. Definition is unchanged */ |
} |
if((pi->pass == PASS_2) && pi->list_line && pi->list_on) { |
fprintf(pi->list_file, " %s\n", pi->list_line); |
pi->list_line = NULL; |
} |
break; |
case DIRECTIVE_ESEG: |
fix_orglist(pi); |
pi->segment = SEGMENT_EEPROM; |
def_orglist(pi); |
if(pi->device->eeprom_size == 0) { |
print_msg(pi, MSGTYPE_ERROR, "Can't use .ESEG directive because device has no EEPROM"); |
} |
break; |
case DIRECTIVE_EXIT: |
pi->fi->exit_file = True; |
break; |
/*** .include ***/ |
case DIRECTIVE_INCLUDE: |
if(!next) { |
print_msg(pi, MSGTYPE_ERROR, "Nothing to include"); |
return(True); |
} |
next = term_string(pi, next); |
if((pi->pass == PASS_2) && pi->list_line && pi->list_on) { |
fprintf(pi->list_file, " %s\n", pi->list_line); |
pi->list_line = NULL; |
} |
// Test if include is in local directory |
ok = test_include(next); |
data = NULL; |
if(!ok) |
for(incpath = GET_ARG(pi->args, ARG_INCLUDEPATH); incpath && !ok; incpath = incpath->next) { |
i = strlen(incpath->data); |
if(data) |
free(data); |
data = malloc(i + strlen(next) + 2); |
if(!data) { |
print_msg(pi, MSGTYPE_OUT_OF_MEM, NULL); |
return(False); |
} |
strcpy(data, incpath->data); |
if((data[i - 1] != '\\') && (data[i - 1] != '/')) |
data[i++] = '/'; |
strcpy(&data[i], next); |
//printf("testing: %s\n", data); |
ok = test_include(data); |
} |
if(ok) { |
fi_bak = pi->fi; |
ok = parse_file(pi, data ? data : next); |
pi->fi = fi_bak; |
} |
else |
print_msg(pi, MSGTYPE_ERROR, "Cannot find include file: %s", next); |
if(data) |
free(data); |
break; |
/*** .includepath ***/ |
case DIRECTIVE_INCLUDEPATH: |
if(!next) { |
print_msg(pi, MSGTYPE_ERROR, ".INCLUDEPATH needs an operand"); |
return(True); |
} |
data = get_next_token(next, TERM_SPACE); |
if(data) { |
print_msg(pi, MSGTYPE_ERROR, ".INCLUDEPATH needs an operand!!!"); |
get_next_token(data, TERM_END); |
if(!get_expr(pi, data, &i)) |
return(False); |
} |
next = term_string(pi, next); |
/* get arg list start pointer */ |
incpath = GET_ARG(pi->args, ARG_INCLUDEPATH); |
/* search for last element */ |
if(incpath == NULL) { |
dl = malloc(sizeof(struct data_list)); |
data = malloc(strlen(next)+1); |
if(dl && data) { |
dl->next = NULL; |
strcpy(data, next); |
dl->data = data; |
SET_ARG(pi->args, ARG_INCLUDEPATH, dl); |
} |
else { |
printf("Error: Unable to allocate memory\n"); |
return(False); |
} |
} |
else |
add_arg(&incpath, next); |
break; |
case DIRECTIVE_LIST: |
if(pi->pass == PASS_2) |
if(pi->list_file) |
pi->list_on = True; |
break; |
case DIRECTIVE_LISTMAC: |
if(pi->pass == PASS_2) |
SET_ARG(pi->args, ARG_LISTMAC, True); |
break; |
case DIRECTIVE_MACRO: |
return(read_macro(pi, next)); |
// break; |
case DIRECTIVE_NOLIST: |
if(pi->pass == PASS_2) |
pi->list_on = False; |
break; |
case DIRECTIVE_ORG: |
if(!next) { |
print_msg(pi, MSGTYPE_ERROR, ".ORG needs an operand"); |
return(True); |
} |
get_next_token(next, TERM_END); |
if(!get_expr(pi, next, &i)) |
return(False); |
fix_orglist(pi); /* Update last segment */ |
switch(pi->segment) { |
case SEGMENT_CODE: |
pi->cseg_addr = i; |
break; |
case SEGMENT_DATA: |
pi->dseg_addr = i; |
break; |
case SEGMENT_EEPROM: |
pi->eseg_addr = i; |
} |
def_orglist(pi); /* Create new segment */ |
if(pi->fi->label) |
pi->fi->label->value = i; |
if((pi->pass == PASS_2) && pi->list_line && pi->list_on) { |
fprintf(pi->list_file, " %s\n", pi->list_line); |
pi->list_line = NULL; |
} |
break; |
case DIRECTIVE_SET: |
if(!next) { |
print_msg(pi, MSGTYPE_ERROR, ".SET needs an operand"); |
return(True); |
} |
data = get_next_token(next, TERM_EQUAL); |
if(!data) { |
print_msg(pi, MSGTYPE_ERROR, "%s needs an expression (e.g. .SET BZZZT = 0x2a)", next); |
return(True); |
} |
get_next_token(data, TERM_END); |
if(!get_expr(pi, data, &i)) |
return(False); |
if(test_label(pi,next,"%s have already been defined as a label")!=NULL) |
return(True); |
if(test_constant(pi,next,"%s have already been defined as a .EQU constant")!=NULL) |
return(True); |
return(def_var(pi, next, i)); |
// break; |
case DIRECTIVE_DEFINE: |
if(!next) { |
print_msg(pi, MSGTYPE_ERROR, ".DEFINE needs an operand"); |
return(True); |
} |
data = get_next_token(next, TERM_SPACE); |
if(data) { |
get_next_token(data, TERM_END); |
if(!get_expr(pi, data, &i)) |
return(False); |
} |
else |
i = 1; |
if(test_label(pi,next,"%s have already been defined as a label")!=NULL) |
return(True); |
if(test_variable(pi,next,"%s have already been defined as a .SET variable")!=NULL) |
return(True); |
/* B.A. : New. Forward references allowed. But check, if everything is ok ... */ |
if(pi->pass==PASS_1) { /* Pass 1 */ |
if(test_constant(pi,next,"Can't redefine constant %s, use .SET instead")!=NULL) |
return(True); |
if(def_const(pi, next, i)==False) |
return(False); |
} else { /* Pass 2 */ |
int j; |
if(get_constant(pi, next, &j)==False) { /* Defined in Pass 1 and now missing ? */ |
print_msg(pi, MSGTYPE_ERROR, "Constant %s is missing in pass 2", next); |
return(False); |
} |
if(i != j) { |
print_msg(pi, MSGTYPE_ERROR, "Constant %s changed value from %d in pass1 to %d in pass 2", next,j,i); |
return(False); |
} |
/* OK. Definition is unchanged */ |
} |
if((pi->pass == PASS_2) && pi->list_line && pi->list_on) { |
fprintf(pi->list_file, " %s\n", pi->list_line); |
pi->list_line = NULL; |
} |
break; |
case DIRECTIVE_PRAGMA: |
#if 0 |
may_do_something_with_pragma_someday(); |
#else |
// if ( !flag_no_warnings ) |
print_msg(pi, MSGTYPE_MESSAGE, "PRAGMA directives currently ignored"); |
#endif |
break; |
case DIRECTIVE_UNDEF: // TODO |
break; |
case DIRECTIVE_IFDEF: |
if(!next) |
{ |
print_msg(pi, MSGTYPE_ERROR, ".IFDEF needs an operand"); |
return(True); |
} |
get_next_token(next, TERM_END); |
/* B.A. : Forward referenc is not allowed for ifdef and ifndef */ |
/* Store undefined symbols in blacklist in pass1 and check, if they are still undefined in pass2 */ |
if(get_symbol(pi, next, NULL)) { |
#if 0 |
// If it's not defined in the first pass, but was defined later |
// then it should be considered OK with regards to ifdef..endif and |
// ifndef..endif code sections. Removed this code. |
if(pi->pass==PASS_2) { /* B.A. : 'Still undefined'-test in pass 2 */ |
if(test_blacklist(pi,next,"Forward reference (%s) not allowed in .ifdef directive")!=NULL) |
return(False); |
} |
#else |
pi->conditional_depth++; |
#endif |
} else { |
if(pi->pass==PASS_1) { /* B.A. : Store undefined symbols in pass 1 */ |
if(def_blacklist(pi, next)==False) |
return(False); |
} |
if(!spool_conditional(pi, False)) |
return(False); |
} |
break; |
case DIRECTIVE_IFNDEF: |
if(!next) |
{ |
print_msg(pi, MSGTYPE_ERROR, ".IFNDEF needs an operand"); |
return(True); |
} |
get_next_token(next, TERM_END); |
/* B.A. : Forward referenc is not allowed for ifdef and ifndef */ |
/* Store undefined symbols in blacklist in pass1 and check, if they are still undefined in pass2 */ |
if(get_symbol(pi, next, NULL)) |
{ |
#if 0 |
if(pi->pass==PASS_2) { /* B.A. : 'Still undefined'-test in pass 2 */ |
// If it's not defined in the first pass, but was defined later |
// then it should be considered OK with regards to ifdef..endif and |
// ifndef..endif code sections. Removed this code. |
if(test_blacklist(pi,next,"Forward reference (%s) not allowed in .ifndef directive")!=NULL) |
return(False); |
} |
if(!spool_conditional(pi, False)) |
return(False); |
#else |
pi->conditional_depth++; |
#endif |
} |
else { |
if(pi->pass==PASS_1) { /* B.A. : Store undefined symbols in pass 1 */ |
if(def_blacklist(pi, next)==False) |
return(False); |
} |
pi->conditional_depth++; |
} |
break; |
case DIRECTIVE_IF: |
if(!next) |
{ |
print_msg(pi, MSGTYPE_ERROR, ".IF needs an expression"); |
return(True); |
} |
get_next_token(next, TERM_END); |
if(!get_expr(pi, next, &i)) |
return(False); |
if(i) |
pi->conditional_depth++; |
else |
{ |
if(!spool_conditional(pi, False)) |
return(False); |
} |
break; |
case DIRECTIVE_ELSE: |
case DIRECTIVE_ELIF: |
case DIRECTIVE_ELSEIF: |
if(!spool_conditional(pi, True)) |
return(False); |
break; |
case DIRECTIVE_ENDIF: |
if(pi->conditional_depth == 0) |
print_msg(pi, MSGTYPE_ERROR, "Too many .ENDIF"); |
else |
pi->conditional_depth--; |
break; |
case DIRECTIVE_MESSAGE: |
if(pi->pass == PASS_1) |
return(True); |
if(!next) { |
print_msg(pi, MSGTYPE_ERROR, "No message parameter supplied"); |
return(True); |
} |
/* B.A : Extended .MESSAGE. Now a comma separated list like in .db is possible and not only a string */ |
print_msg(pi, MSGTYPE_MESSAGE_NO_LF, NULL); /* Prints Line Header (filename, linenumber) without trailing /n */ |
while(next) { /* Modified code from parse_db(). Thank you :-) */ |
data = get_next_token(next, TERM_COMMA); |
if(next[0] == '\"') { /* string parsing */ |
next = term_string(pi, next); |
print_msg(pi, MSGTYPE_APPEND,"%s",next); |
while(*next != '\0') { |
next++; |
} |
} else { |
if(!get_expr(pi, next, &i)) { |
print_msg(pi, MSGTYPE_APPEND,"\n"); /* Add newline */ |
return(False); |
} |
print_msg(pi, MSGTYPE_APPEND,"0x%02X",i); |
} |
next = data; |
} |
print_msg(pi, MSGTYPE_APPEND,"\n"); /* Add newline */ |
break; |
case DIRECTIVE_WARNING: |
if(pi->pass == PASS_1) |
return(True); |
if(!next) { |
print_msg(pi, MSGTYPE_ERROR, "No warning string supplied"); |
return(True); |
} |
next = term_string(pi, next); |
print_msg(pi, MSGTYPE_WARNING, next); |
break; |
case DIRECTIVE_ERROR: |
if(!next) { /* B.A : Fix segfault bug if .error without parameter was used */ |
print_msg(pi, MSGTYPE_ERROR, "No error string supplied"); |
return(True); |
} |
next = term_string(pi, next); |
/* B.A. : Don't use this. It may cause segfaults if the 'next' contains printf control sequences %s,%d etc. |
print_msg(pi, MSGTYPE_ERROR, next); |
*/ |
print_msg(pi, MSGTYPE_ERROR,"%s",next); /* B.A. : This is '%s' save :-) */ |
pi->error_count = pi->max_errors; |
if(pi->pass == PASS_1) |
return(True); |
break; |
} |
return(ok); |
} |
int get_directive_type(char *directive) { |
int i; |
for(i = 0; i < DIRECTIVE_COUNT; i++) { |
if(!strcmp(directive, directive_list[i])) return(i); |
} |
return(-1); |
} |
char *term_string(struct prog_info *pi, char *string) { |
int i; |
if(string[0] != '\"') { |
print_msg(pi, MSGTYPE_ERROR, "String must be enclosed in \"-signs"); |
} |
else { |
string++; |
} |
/* skip to the end of the string*/ |
for(i = 0; (string[i] != '\"') && !((string[i] == 10) || (string[i] == 13) || (string[i] == '\0')); i++); |
if((string[i] == 10) || (string[i] == 13) || (string[i] == '\0')) { |
print_msg(pi, MSGTYPE_ERROR, "String is missing a closing \"-sign"); |
} |
string[i] = '\0'; /* and terminate it where the " was */ |
return(string); |
} |
/* Parse data byte directive */ |
int parse_db(struct prog_info *pi, char *next) { |
int i; |
int count; |
char *data; |
char prev = 0; |
/* check if .db is allowed in this segment type */ |
if(pi->segment == SEGMENT_DATA) { |
print_msg(pi, MSGTYPE_ERROR, "Can't use .DB directive in data segment (.DSEG) !"); |
return(True); |
} |
count = 0; |
if(pi->pass == PASS_2 && pi->list_on) { |
if(pi->segment == SEGMENT_EEPROM) |
fprintf(pi->list_file, "E:%06X ", pi->eseg_addr); |
if(pi->segment == SEGMENT_CODE) |
fprintf(pi->list_file, "C:%06X ", pi->cseg_addr); |
} |
/* get each db token */ |
while(next) { |
data = get_next_token(next, TERM_COMMA); |
/* string parsing */ |
if(next[0] == '\"') { |
next = term_string(pi, next); |
while(*next != '\0') { |
count++; |
write_db(pi, *next, &prev, count); |
if(pi->pass == PASS_2 && pi->list_on) |
fprintf(pi->list_file, "%02X", (unsigned char)*next); // B.A.: Patch for chars with bit 7 = 1 (Example: °) |
if((unsigned char)*next > 127 && pi->pass == PASS_2) |
print_msg(pi, MSGTYPE_WARNING, "Found .DB string with characters > code 127. Be careful !"); // B.A.: Print warning for codes > 127 |
next++; |
} |
} |
else { |
if(pi->pass == PASS_2) { |
if(!get_expr(pi, next, &i)) |
return(False); |
if((i < -128) || (i > 255)) |
print_msg(pi, MSGTYPE_WARNING, "Value %d is out of range (-128 <= k <= 255). Will be masked", i); |
if(pi->list_on) fprintf(pi->list_file, "%02X", i); |
} |
count++; |
write_db(pi, (char)i, &prev, count); |
} |
next = data; |
} |
if(pi->segment == SEGMENT_CODE) { |
if((count % 2) == 1) { |
if(pi->pass == PASS_2) { |
if(pi->list_on) fprintf(pi->list_file, "00 ; zero byte added"); |
write_prog_word(pi, pi->cseg_addr, prev & 0xFF); |
print_msg(pi, MSGTYPE_WARNING, "A .DB segment with an odd number of bytes is detected. A zero byte is added."); |
} |
pi->cseg_addr++; |
if(pi->pass == PASS_1) { |
pi->cseg_count++; |
} |
} |
} |
if(pi->pass == PASS_2 && pi->list_on) { |
fprintf(pi->list_file, "\n"); |
pi->list_line = NULL; |
} |
return(True); |
} |
void write_db(struct prog_info *pi, char byte, char *prev, int count) { |
if(pi->segment == SEGMENT_EEPROM) { |
if(pi->pass == PASS_2) { |
write_ee_byte(pi, pi->eseg_addr, byte); |
} |
pi->eseg_addr++; |
if(pi->pass == PASS_1) { |
pi->eseg_count++; |
} |
} |
else { /* pi->segment == SEGMENT_CODE */ |
if((count % 2) == 0) { |
if(pi->pass == PASS_2) { |
write_prog_word(pi, pi->cseg_addr, (byte << 8) | (*prev & 0xff)); |
} |
pi->cseg_addr++; |
if(pi->pass == PASS_1) { |
pi->cseg_count++; |
} |
} |
else { |
*prev = byte; |
} |
} |
} |
int spool_conditional(struct prog_info *pi, int only_endif) { |
int current_depth = 0, do_next; |
if(pi->macro_line) { |
while((pi->macro_line = pi->macro_line->next)) { |
pi->macro_call->line_index++; |
if(check_conditional(pi, pi->macro_line->line, ¤t_depth, &do_next, only_endif)) { |
if(!do_next) |
return(True); |
} |
else |
return(False); |
} |
print_msg(pi, MSGTYPE_ERROR, "Found no closing .ENDIF in macro"); |
} |
else { |
while(fgets_new(pi,pi->fi->buff, LINEBUFFER_LENGTH, pi->fi->fp)) { |
pi->fi->line_number++; |
if(check_conditional(pi, pi->fi->buff, ¤t_depth, &do_next, only_endif)) { |
if(!do_next) |
return(True); |
} |
else |
return(False); |
} |
if(feof(pi->fi->fp)) { |
print_msg(pi, MSGTYPE_ERROR, "Found no closing .ENDIF"); |
return(True); |
} |
else { |
perror(pi->fi->include_file->name); |
return(False); |
} |
} |
return(True); |
} |
int check_conditional(struct prog_info *pi, char *pbuff, int *current_depth, int *do_next, int only_endif) |
{ |
int i = 0; |
char *next; |
char linebuff[LINEBUFFER_LENGTH]; |
strcpy(linebuff, pbuff); /* avoid cutting of the end of .elif line */ |
*do_next = False; |
while(IS_HOR_SPACE(linebuff[i]) && !IS_END_OR_COMMENT(linebuff[i])) i++; |
#if 0 |
if(linebuff[i] == '.') { |
#else |
if((linebuff[i] == '.') || (linebuff[i] == '#')){ |
#endif |
i++; |
if(!nocase_strncmp(&linebuff[i], "if", 2)) |
(*current_depth)++; |
else |
if(!nocase_strncmp(&linebuff[i], "endif", 5)) { |
if(*current_depth == 0) |
return(True); |
(*current_depth)--; |
} else |
if(!only_endif && (*current_depth == 0)) { |
/* B.A. : Add ELSEIF = ELIF */ |
if((!nocase_strncmp(&linebuff[i], "else", 4)) && (nocase_strncmp(&linebuff[i], "elseif", 6))) { |
pi->conditional_depth++; |
return(True); |
} else |
if((!nocase_strncmp(&linebuff[i], "elif", 4)) || (!nocase_strncmp(&linebuff[i], "elseif", 6))) { |
next = get_next_token(&linebuff[i], TERM_SPACE); |
if(!next) { |
print_msg(pi, MSGTYPE_ERROR, ".ELSEIF / .ELIF needs an operand"); |
return(True); |
} |
get_next_token(next, TERM_END); |
if(!get_expr(pi, next, &i)) |
return(False); |
if(i) |
pi->conditional_depth++; |
else { |
if(!spool_conditional(pi, False)) |
return(False); |
} |
return(True); |
} |
} |
} |
*do_next = True; |
return(True); |
} |
int test_include(const char *filename) |
{ |
FILE *fp; |
fp = fopen(filename, "r"); |
if(fp) |
{ |
fclose(fp); |
return(True); |
} |
else |
return(False); |
} |
/* end of directiv.c */ |
/contrib/toolchain/avra/src/expr.c |
---|
0,0 → 1,573 |
/*********************************************************************** |
* |
* avra - Assembler for the Atmel AVR microcontroller series |
* |
* Copyright (C) 1998-2004 Jon Anders Haugum, Tobias Weber |
* |
* This program is free software; you can redistribute it and/or modify |
* it under the terms of the GNU General Public License as published by |
* the Free Software Foundation; either version 2 of the License, or |
* (at your option) any later version. |
* |
* This program is distributed in the hope that it will be useful, |
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
* GNU General Public License for more details. |
* |
* You should have received a copy of the GNU General Public License |
* along with this program; see the file COPYING. If not, write to |
* the Free Software Foundation, Inc., 59 Temple Place - Suite 330, |
* Boston, MA 02111-1307, USA. |
* |
* |
* Authors of avra can be reached at: |
* email: jonah@omegav.ntnu.no, tobiw@suprafluid.com |
* www: http://sourceforge.net/projects/avra |
*/ |
#include <stdio.h> |
#include <stdlib.h> |
#include <string.h> |
#include <ctype.h> |
#include "misc.h" |
#include "avra.h" |
#include "device.h" |
#define IS_UNARY(x) ((x == '!') || (x == '-') || (x == '~')) |
#define IS_OPERATOR(x) ((x == '+') || (x == '-') || (x == '*') || (x == '/') || (x == '%') || (x == '<') || (x == '>') || (x == '=') || (x == '!') || (x == '&') || (x == '^') || (x == '|')) |
#define IS_2ND_OPERATOR(x) ((x == '<') || (x == '>') || (x == '=') || (x == '&') || (x == '|')) |
enum { |
OPERATOR_ERROR = 0, |
OPERATOR_MUL, |
OPERATOR_DIV, |
OPERATOR_MOD, |
OPERATOR_ADD, |
OPERATOR_SUB, |
OPERATOR_SHIFT_LEFT, |
OPERATOR_SHIFT_RIGHT, |
OPERATOR_LESS_THAN, |
OPERATOR_LESS_OR_EQUAL, |
OPERATOR_GREATER_THAN, |
OPERATOR_GREATER_OR_EQUAL, |
OPERATOR_EQUAL, |
OPERATOR_NOT_EQUAL, |
OPERATOR_BITWISE_AND, |
OPERATOR_BITWISE_XOR, |
OPERATOR_BITWISE_OR, |
OPERATOR_LOGICAL_AND, |
OPERATOR_LOGICAL_OR |
}; |
enum { |
FUNCTION_LOW = 0, |
FUNCTION_BYTE1, |
FUNCTION_HIGH, |
FUNCTION_BYTE2, |
FUNCTION_BYTE3, |
FUNCTION_BYTE4, |
FUNCTION_LWRD, |
FUNCTION_HWRD, |
FUNCTION_PAGE, |
FUNCTION_EXP2, |
FUNCTION_LOG2, |
FUNCTION_COUNT |
}; |
struct element |
{ |
struct element *next; |
int data; |
}; |
char *function_list[] = { |
/* |
** allow whitespace between function name |
** and opening brace... |
*/ |
"low", |
"byte1", |
"high", |
"byte2", |
"byte3", |
"byte4", |
"lwrd", |
"hwrd", |
"page", |
"exp2", |
"log2" |
}; |
int log_2(int value) |
{ |
int i = 0; |
while(value >>= 1) |
i++; |
return(i); |
} |
int get_operator(char *op) |
{ |
switch(op[0]) { |
case '*': |
return(OPERATOR_MUL); |
case '/': |
return(OPERATOR_DIV); |
case '%': |
return(OPERATOR_MOD); |
case '+': |
return(OPERATOR_ADD); |
case '-': |
return(OPERATOR_SUB); |
case '<': |
switch(op[1]) { |
case '<': |
return(OPERATOR_SHIFT_LEFT); |
case '=': |
return(OPERATOR_LESS_OR_EQUAL); |
default: |
return(OPERATOR_LESS_THAN); |
} |
case '>': |
switch(op[1]) { |
case '>': |
return(OPERATOR_SHIFT_RIGHT); |
case '=': |
return(OPERATOR_GREATER_OR_EQUAL); |
default: |
return(OPERATOR_GREATER_THAN); |
} |
case '=': |
if(op[1] == '=') |
return(OPERATOR_EQUAL); |
case '!': |
if(op[1] == '=') |
return(OPERATOR_NOT_EQUAL); |
case '&': |
if(op[1] == '&') |
return(OPERATOR_LOGICAL_AND); |
else |
return(OPERATOR_BITWISE_AND); |
case '^': |
return(OPERATOR_BITWISE_XOR); |
case '|': |
if(op[1] == '|') |
return(OPERATOR_LOGICAL_OR); |
else |
return(OPERATOR_BITWISE_OR); |
} |
return(OPERATOR_ERROR); |
} |
int test_operator_at_precedence(int operator, int precedence) |
{ |
switch(precedence) { |
case 13: |
return((operator == OPERATOR_MUL) || (operator == OPERATOR_DIV) |
|| (operator == OPERATOR_MOD)); |
case 12: |
return((operator == OPERATOR_ADD) || (operator == OPERATOR_SUB)); |
case 11: |
return((operator == OPERATOR_SHIFT_LEFT) || (operator == OPERATOR_SHIFT_RIGHT)); |
case 10: |
return((operator == OPERATOR_LESS_THAN) || (operator == OPERATOR_LESS_OR_EQUAL) |
|| (operator == OPERATOR_GREATER_THAN) || (operator == OPERATOR_GREATER_OR_EQUAL)); |
case 9: |
return((operator == OPERATOR_EQUAL) || (operator == OPERATOR_NOT_EQUAL)); |
case 8: |
return(operator == OPERATOR_BITWISE_AND); |
case 7: |
return(operator == OPERATOR_BITWISE_XOR); |
case 6: |
return(operator == OPERATOR_BITWISE_OR); |
case 5: |
return(operator == OPERATOR_LOGICAL_AND); |
default: /* Makes the compiler shut up */ |
case 4: |
return(operator == OPERATOR_LOGICAL_OR); |
} |
} |
int calc(struct prog_info *pi, int left, int operator, int right) // TODO: Sjekk litt resultater |
{ |
switch(operator) { |
case OPERATOR_MUL: |
return(left * right); |
case OPERATOR_DIV: |
if(right == 0) { |
print_msg(pi, MSGTYPE_ERROR, "Division by zero"); |
return(0); |
} |
return(left / right); |
case OPERATOR_MOD: |
if(right == 0) { |
print_msg(pi, MSGTYPE_ERROR, "Division by zero (modulus operator)"); |
return(0); |
} |
return(left % right); |
case OPERATOR_ADD: |
return(left + right); |
case OPERATOR_SUB: |
return(left - right); |
case OPERATOR_SHIFT_LEFT: |
return(left << right); |
case OPERATOR_SHIFT_RIGHT: |
return((unsigned)left >> right); |
case OPERATOR_LESS_THAN: |
return(left < right); |
case OPERATOR_LESS_OR_EQUAL: |
return(left <= right); |
case OPERATOR_GREATER_THAN: |
return(left > right); |
case OPERATOR_GREATER_OR_EQUAL: |
return(left >= right); |
case OPERATOR_EQUAL: |
return(left == right); |
case OPERATOR_NOT_EQUAL: |
return(left != right); |
case OPERATOR_BITWISE_AND: |
return(left & right); |
case OPERATOR_BITWISE_XOR: |
return(left ^ right); |
case OPERATOR_BITWISE_OR: |
return(left | right); |
case OPERATOR_LOGICAL_AND: |
return(left && right); |
default: /* Make the compiler shut up */ |
case OPERATOR_LOGICAL_OR: |
return(left || right); |
} |
} |
/* If found, return the ID of the internal function */ |
int get_function(char *function) |
{ |
int i; |
for(i = 0; i < FUNCTION_COUNT; i++) { |
if(!nocase_strncmp(function, function_list[i], strlen(function_list[i]))) |
{ |
/* |
** some more checks to allow whitespace between function name |
** and opening brace... |
*/ |
char *tmp = function + strlen(function_list[i]); |
while (*tmp <= ' ') |
tmp++; |
if (*tmp != '(') |
continue; |
return(i); |
} |
} |
return(-1); |
} |
unsigned int do_function(int function, int value) |
{ |
switch(function) { |
case FUNCTION_LOW: |
case FUNCTION_BYTE1: |
return(value & 0xFF); |
case FUNCTION_HIGH: |
case FUNCTION_BYTE2: |
return((value >> 8) & 0xff); |
case FUNCTION_BYTE3: |
return((value >> 16) & 0xff); |
case FUNCTION_BYTE4: |
return((value >> 24) & 0xff); |
case FUNCTION_LWRD: |
return(value & 0xffff); |
case FUNCTION_HWRD: |
return((value >> 16) & 0xffff); |
case FUNCTION_PAGE: |
return((value >> 16) & 0xff); |
case FUNCTION_EXP2: |
return(1 << value); |
case FUNCTION_LOG2: |
return(log_2(value)); |
default: |
return(0); |
} |
} |
int get_symbol(struct prog_info *pi, char *label_name, int *data) |
{ |
struct label *label; |
struct macro_call *macro_call; |
if(get_constant(pi,label_name,data)) return(True); |
if(get_variable(pi,label_name,data)) return(True); |
for(macro_call = pi->macro_call; macro_call; macro_call = macro_call->prev_on_stack) { |
for(label = pi->macro_call->first_label; label; label = label->next) |
if(!nocase_strcmp(label->name, label_name)) { |
if(data) |
*data = label->value; |
return(True); |
} |
} |
if(get_label(pi,label_name,data)) return(True); |
return(False); |
} |
int par_length(char *data) |
{ |
int i = 0, b_count = 1; |
for(;;) { |
if(data[i] == ')') { |
b_count--; |
if(!b_count) |
return(i); |
} |
else if(data[i] == '(') |
b_count++; |
else if(data[i] == '\0') |
return(-1); |
i++; |
} |
} |
int get_expr(struct prog_info *pi, char *data, int *value) { |
/* Definition */ |
int ok, end, i, count, first_flag, length, function; |
char unary, *label; |
struct element *element, *first_element = NULL, *temp_element; |
struct element **last_element = &first_element; |
/* Initialisation */ |
first_flag = True; |
ok = True; |
end = False; |
count = 0; |
unary = 0; |
/* the expression parser loop */ |
for(i = 0; ; i++) { |
/* horizontal space is just skipped */ |
if(IS_HOR_SPACE(data[i])); |
/* test for clean or premature end */ |
else if(IS_END_OR_COMMENT(data[i])) { |
if((count % 2) != 1) |
print_msg(pi, MSGTYPE_ERROR, "Missing value in expression"); |
else |
end = True; |
break; |
} |
else if(first_flag && IS_UNARY(data[i])) { |
unary = data[i]; |
first_flag = False; |
} |
else if((count % 2) == 1) { |
if(!IS_OPERATOR(data[i])) { |
print_msg(pi, MSGTYPE_ERROR, "Illegal operator '%c'", data[i]); |
break; |
} |
element = malloc(sizeof(struct element)); |
if(!element) { |
print_msg(pi, MSGTYPE_OUT_OF_MEM, NULL); |
ok = False; |
break; |
} |
element->next = NULL; |
element->data = get_operator(&data[i]); |
if(element->data == OPERATOR_ERROR) { |
if(IS_2ND_OPERATOR(data[i + 1])) |
print_msg(pi, MSGTYPE_ERROR, "Unknown operator %c%c", data[i], data[i + 1]); |
else |
print_msg(pi, MSGTYPE_ERROR, "Unknown operator %c", data[i]); |
break; |
} |
*last_element = element; |
last_element = &element->next; |
if(IS_2ND_OPERATOR(data[i + 1])) |
i++; |
count++; |
first_flag = True; |
unary = 0; |
} |
else { |
element = malloc(sizeof(struct element)); |
if(!element) { |
print_msg(pi, MSGTYPE_OUT_OF_MEM, NULL); |
ok = False; |
break; |
} |
element->next = NULL; |
length = 0; |
if(isdigit(data[i])) { |
if(tolower(data[i + 1]) == 'x') { |
i += 2; |
while(isxdigit(data[i + length])) length++; // TODO: Sjekk overflow |
element->data = atox_n(&data[i], length); |
} |
else if(tolower(data[i + 1]) == 'b') { |
i += 2; |
element->data = 0; |
while((data[i + length] == '1') || (data[i + length] == '0')) { |
element->data <<= 1; |
element->data |= data[i + length++] - '0'; // TODO: Sjekk overflow |
} |
} |
else { |
while(isdigit(data[i + length])) length++; |
element->data = atoi_n(&data[i], length); // TODO: Sjekk overflow |
} |
} |
else if(data[i] == '$') { |
i++; |
while(isxdigit(data[i + length])) length++; |
element->data = atox_n(&data[i], length); // TODO: Sjekk overflow |
} |
else if(data[i] == '\'') { |
i++; |
if(data[i+1] != '\'') { |
print_msg(pi, MSGTYPE_ERROR, "Not a correct character ! Use 'A' !"); |
break; |
} |
element->data = data[i]; |
length = 2; |
} |
else if(data[i] == '(') { |
i++; |
length = par_length(&data[i]); |
if(length == -1) { |
print_msg(pi, MSGTYPE_ERROR, "Missing ')'"); |
break; |
} |
data[i + length++] = '\0'; |
ok = get_expr(pi, &data[i], &element->data); |
if(!ok) |
break; |
} |
/* test for internal function */ |
else if((function = get_function(&data[i])) != -1) { |
while(data[i] != '(') |
i++; |
i++; |
length = par_length(&data[i]); |
if(length == -1) { |
print_msg(pi, MSGTYPE_ERROR, "Missing ')'"); |
break; |
} |
data[i + length++] = '\0'; |
ok = get_expr(pi, &data[i], &element->data); |
if(!ok) |
break; |
element->data = do_function(function, element->data); |
} |
else if(!nocase_strncmp(&data[i], "defined(", 8)) { |
i += 8; |
length = par_length(&data[i]); |
if(length == -1) { |
print_msg(pi, MSGTYPE_ERROR, "Missing ')'"); |
break; |
} |
data[i + length++] = '\0'; |
if(get_symbol(pi, &data[i], NULL)) |
element->data = 1; |
else |
element->data = 0; |
} |
else if(!nocase_strncmp(&data[i], "supported(", 10)) { |
i += 10; |
length = par_length(&data[i]); |
if(length == -1) { |
print_msg(pi, MSGTYPE_ERROR, "Missing ')'"); |
break; |
} |
data[i + length++] = '\0'; |
element->data=is_supported(pi, &data[i]); |
if (element->data<0) { |
if (toupper(data[i])=='X') { |
if (pi->device->flag&DF_NO_XREG) element->data = 0; |
else element->data = 1; |
} |
else if (toupper(data[i])=='Y') { |
if (pi->device->flag&DF_NO_YREG) element->data = 0; |
else element->data = 1; |
} |
else if (toupper(data[i])=='Z') |
element->data = 1; |
else { |
print_msg(pi, MSGTYPE_ERROR, "Unknown mnemonic: %s",&data[i]); |
element->data = 0; |
} |
} |
} |
else { |
while(IS_LABEL(data[i + length])) length++; |
if((length == 2) && !nocase_strncmp(&data[i], "PC", 2)) |
element->data = pi->cseg_addr; |
else { |
label = malloc(length + 1); |
if(!label) { |
print_msg(pi, MSGTYPE_OUT_OF_MEM, NULL); |
ok = False; |
break; |
} |
strncpy(label, &data[i], length); |
label[length] = '\0'; |
if(get_symbol(pi, label, &element->data)) |
free(label); |
else { |
print_msg(pi, MSGTYPE_ERROR, "Found no label/variable/constant named %s", label); |
free(label); |
break; |
} |
} |
} |
/* now the expression has been evaluated */ |
i += length - 1; |
switch(unary) { // TODO: Få den til å takle flere unary på rad. |
case '-': |
element->data = -element->data; |
break; |
case '!': |
element->data = !element->data; |
break; |
case '~': |
element->data = ~element->data; |
} |
*last_element = element; |
last_element = &element->next; |
count++; |
first_flag = False; |
} |
} |
if(end) { |
for(i = 13; (i >= 4) && (count != 1); i--) { |
for(element = first_element; element->next;) { |
if(test_operator_at_precedence(element->next->data, i)) { // TODO: Vurder en hi_i for kjapphet |
element->data = calc(pi, element->data, element->next->data, element->next->next->data); |
temp_element = element->next->next->next; |
free(element->next->next); |
free(element->next); |
count -= 2; |
element->next = temp_element; |
} |
else |
element = element->next->next; |
} |
} |
*value = first_element->data; |
} |
for(element = first_element; element;) { |
temp_element = element; |
element = element->next; |
free(temp_element); |
} |
return(ok); |
} |
/* end of expr.c */ |
/contrib/toolchain/avra/src/file.c |
---|
0,0 → 1,317 |
/*********************************************************************** |
* |
* avra - Assembler for the Atmel AVR microcontroller series |
* |
* Copyright (C) 1998-2004 Jon Anders Haugum, Tobias Weber |
* |
* This program is free software; you can redistribute it and/or modify |
* it under the terms of the GNU General Public License as published by |
* the Free Software Foundation; either version 2 of the License, or |
* (at your option) any later version. |
* |
* This program is distributed in the hope that it will be useful, |
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
* GNU General Public License for more details. |
* |
* You should have received a copy of the GNU General Public License |
* along with this program; see the file COPYING. If not, write to |
* the Free Software Foundation, Inc., 59 Temple Place - Suite 330, |
* Boston, MA 02111-1307, USA. |
* |
* |
* Authors of avra can be reached at: |
* email: jonah@omegav.ntnu.no, tobiw@suprafluid.com |
* www: http://sourceforge.net/projects/avra |
*/ |
#include <stdio.h> |
#include <stdlib.h> |
#include <string.h> |
#include <time.h> |
#include <unistd.h> /* B.A. for unlink function */ |
#include "misc.h" |
#include "avra.h" |
#include "args.h" |
int open_out_files(struct prog_info *pi, char *filename) |
{ |
int length; |
char *buff; |
int ok = True; /* flag for coff results */ |
length = strlen(filename); |
buff = malloc(length + 9); |
if(buff == NULL) { |
print_msg(pi, MSGTYPE_OUT_OF_MEM, NULL); |
return(False); |
} |
strcpy(buff, filename); |
if(length < 4) { |
printf("Error: wrong input file name\n"); |
} |
if(!nocase_strcmp(&buff[length - 4], ".asm")) { |
length -= 4; |
buff[length] = '\0'; |
} |
//printf("pi->cseg_count = %i\n", pi->cseg_count); |
//printf("pi->eseg_count = %i\n", pi->eseg_count); |
/* open files for code output */ |
strcpy(&buff[length], ".hex"); |
if(!(pi->hfi = open_hex_file(buff))) { /* check if open failed */ |
print_msg(pi, MSGTYPE_ERROR, "Could not create output hex file!"); |
ok = False; |
} |
strcpy(&buff[length], ".obj"); |
if(!(pi->obj_file = open_obj_file(pi, buff))) { |
print_msg(pi, MSGTYPE_ERROR, "Could not create object file!"); |
ok = False; |
} |
/* open files for eeprom output */ |
strcpy(&buff[length], ".eep.hex"); |
if(!(pi->eep_hfi = open_hex_file(buff))) { |
print_msg(pi, MSGTYPE_ERROR, "Could not create eeprom hex file!"); |
ok = False; |
} |
/* coff file is always generated */ |
strcpy(&buff[length], ".cof"); |
pi->coff_file = open_coff_file(pi, buff); |
/* open list file */ |
if (pi->list_on) { |
strcpy(buff, GET_ARG(pi->args, ARG_LISTFILE)); |
pi->list_file = fopen(buff, "w"); |
if(pi->list_file == NULL) { |
print_msg(pi, MSGTYPE_ERROR, "Could not create list file!"); |
ok = False; |
} |
/* write list file header */ |
fprintf(pi->list_file, "\nAVRA Ver. %i.%i.%i %s %s\n\n",VER_MAJOR, VER_MINOR, VER_RELEASE, filename, ctime(&pi->time)); |
} |
else { |
pi->list_file = NULL; |
} |
free(buff); |
if(ok) |
return(True); |
else |
close_out_files(pi); |
return(False); |
} |
/* delete all output files */ |
void unlink_out_files(struct prog_info *pi, char *filename) |
{ |
char *buff; |
int length; |
close_out_files(pi); |
length = strlen(filename); |
buff = malloc(length + 9); |
if(buff == NULL) { |
print_msg(pi, MSGTYPE_OUT_OF_MEM, NULL); |
return; |
} |
strcpy(buff, filename); |
if(!nocase_strcmp(&buff[length - 4], ".asm")) { |
length -= 4; |
buff[length] = '\0'; |
} |
#if debug == 1 |
printf("unlinking files"); |
#endif |
strcpy(&buff[length], ".hex"); |
unlink(buff); |
strcpy(&buff[length], ".obj"); |
unlink(buff); |
strcpy(&buff[length], ".eep.hex"); |
unlink(buff); |
strcpy(&buff[length], ".cof"); |
unlink(buff); |
strcpy(&buff[length], ".lst"); |
unlink(buff); |
strcpy(&buff[length], ".map"); |
unlink(buff); |
} |
void close_out_files(struct prog_info *pi) |
{ |
char stmp[2048]; |
if(pi->error_count == 0) { |
sprintf(stmp, |
"Segment usage:\n" |
" Code : %7d words (%d bytes)\n" |
" Data : %7d bytes\n" |
" EEPROM : %7d bytes\n", |
pi->cseg_count, pi->cseg_count * 2, pi->dseg_count, pi->eseg_count); |
printf("%s", stmp); |
} |
if(pi->hfi) |
close_hex_file(pi->hfi); |
if(pi->eep_hfi) |
close_hex_file(pi->eep_hfi); |
if(pi->list_file) { |
fprintf(pi->list_file, "\n\n%s", stmp); |
if(pi->error_count == 0) |
fprintf(pi->list_file, "\nAssembly completed with no errors.\n"); |
fclose(pi->list_file); |
} |
if(pi->obj_file) |
close_obj_file(pi, pi->obj_file); |
if(pi->coff_file) |
close_coff_file(pi, pi->coff_file); |
} |
struct hex_file_info *open_hex_file(char *filename) |
{ |
struct hex_file_info *hfi; |
hfi = calloc(1, sizeof(struct hex_file_info)); |
if(hfi) { |
hfi->segment = -1; |
hfi->fp = fopen(filename, "wb"); |
if(!hfi->fp) { |
close_hex_file(hfi); |
hfi = NULL; |
} |
} |
return(hfi); |
} |
void close_hex_file(struct hex_file_info *hfi) |
{ |
if(hfi->fp) { |
if(hfi->count != 0) |
do_hex_line(hfi); |
fprintf(hfi->fp, ":00000001FF\x0d\x0a"); |
fclose(hfi->fp); |
} |
free(hfi); |
} |
void write_ee_byte(struct prog_info *pi, int address, unsigned char data) |
{ |
if((pi->eep_hfi->count == 16) || ((address != (pi->eep_hfi->linestart_addr + pi->eep_hfi->count)) && (pi->eep_hfi->count != 0))) |
do_hex_line(pi->eep_hfi); |
if(pi->eep_hfi->count == 0) |
pi->eep_hfi->linestart_addr = address; |
pi->eep_hfi->hex_line[pi->eep_hfi->count++] = data; |
if(pi->coff_file) |
write_coff_eeprom(pi, address, data); |
} |
void write_prog_word(struct prog_info *pi, int address, int data) |
{ |
write_obj_record(pi, address, data); |
address *= 2; |
if(pi->hfi->segment != (address >> 16)) { |
if(pi->hfi->count != 0) |
do_hex_line(pi->hfi); |
pi->hfi->segment = address >> 16; |
if(pi->hfi->segment >= 16) // Use 04 record for addresses above 1 meg since 02 can support max 1 meg |
fprintf(pi->hfi->fp, ":02000004%04X%02X\x0d\x0a", pi->hfi->segment & 0xffff, |
(0 - 2 - 4 - ((pi->hfi->segment >> 8) & 0xff) - (pi->hfi->segment & 0xff)) & 0xff); |
else // Use 02 record for addresses below 1 meg since more programmers know about the 02 instead of the 04 |
fprintf(pi->hfi->fp, ":02000002%04X%02X\x0d\x0a", (pi->hfi->segment << 12) & 0xffff, |
(0 - 2 - 2 - ((pi->hfi->segment << 4) & 0xf0)) & 0xff); |
} |
if((pi->hfi->count == 16) || ((address != (pi->hfi->linestart_addr + pi->hfi->count)) && (pi->hfi->count != 0))) |
do_hex_line(pi->hfi); |
if(pi->hfi->count == 0) |
pi->hfi->linestart_addr = address; |
pi->hfi->hex_line[pi->hfi->count++] = data & 0xff; |
pi->hfi->hex_line[pi->hfi->count++] = (data >> 8) & 0xff; |
if(pi->coff_file != 0) |
write_coff_program(pi, address, data); |
} |
void do_hex_line(struct hex_file_info *hfi) |
{ |
int i; |
unsigned char checksum = 0; |
fprintf(hfi->fp, ":%02X%04X00", hfi->count, hfi->linestart_addr & 0xffff); |
checksum -= hfi->count + ((hfi->linestart_addr >> 8) & 0xff) + (hfi->linestart_addr & 0xff); |
for(i = 0; i < hfi->count; i++) { |
fprintf(hfi->fp, "%02X", hfi->hex_line[i]); |
checksum -= hfi->hex_line[i]; |
} |
fprintf(hfi->fp, "%02X\x0d\x0a", checksum); |
hfi->count = 0; |
} |
FILE *open_obj_file(struct prog_info *pi, char *filename) |
{ |
int i; |
FILE *fp; |
struct include_file *include_file; |
fp = fopen(filename, "wb"); |
if(fp) { |
i = pi->cseg_count * 9 + 26; |
fputc((i >> 24) & 0xff, fp); |
fputc((i >> 16) & 0xff, fp); |
fputc((i >> 8) & 0xff, fp); |
fputc(i & 0xff, fp); |
i = 26; |
fputc((i >> 24) & 0xff, fp); |
fputc((i >> 16) & 0xff, fp); |
fputc((i >> 8) & 0xff, fp); |
fputc(i & 0xff, fp); |
fputc(9, fp); |
i = 0; |
for(include_file = pi->first_include_file; include_file; include_file = include_file->next) |
i++; |
fputc(i, fp); |
fprintf(fp, "AVR Object File"); |
fputc('\0', fp); |
} |
return(fp); |
} |
void close_obj_file(struct prog_info *pi, FILE *fp) |
{ |
struct include_file *include_file; |
for(include_file = pi->first_include_file; include_file; include_file = include_file->next) { |
fprintf(fp, "%s", include_file->name); |
fputc('\0', fp); |
} |
fputc('\0', fp); |
fclose(fp); |
} |
void write_obj_record(struct prog_info *pi, int address, int data) |
{ |
fputc((address >> 16) & 0xff, pi->obj_file); |
fputc((address >> 8) & 0xff, pi->obj_file); |
fputc(address & 0xff, pi->obj_file); |
fputc((data >> 8) & 0xff, pi->obj_file); |
fputc(data & 0xff, pi->obj_file); |
fputc(pi->fi->include_file->num & 0xff, pi->obj_file); |
fputc((pi->fi->line_number >> 8) & 0xff, pi->obj_file); |
fputc(pi->fi->line_number & 0xff, pi->obj_file); |
if(pi->macro_call) |
fputc(1, pi->obj_file); |
else |
fputc(0, pi->obj_file); |
} |
/* end of file.c */ |
/contrib/toolchain/avra/src/macro.c |
---|
0,0 → 1,560 |
/*********************************************************************** |
* |
* avra - Assembler for the Atmel AVR microcontroller series |
* |
* Copyright (C) 1998-2004 Jon Anders Haugum, TObias Weber |
* |
* This program is free software; you can redistribute it and/or modify |
* it under the terms of the GNU General Public License as published by |
* the Free Software Foundation; either version 2 of the License, or |
* (at your option) any later version. |
* |
* This program is distributed in the hope that it will be useful, |
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
* GNU General Public License for more details. |
* |
* You should have received a copy of the GNU General Public License |
* along with this program; see the file COPYING. If not, write to |
* the Free Software Foundation, Inc., 59 Temple Place - Suite 330, |
* Boston, MA 02111-1307, USA. |
* |
* |
* Authors of avra can be reached at: |
* email: jonah@omegav.ntnu.no, tobiw@suprafluid.com |
* www: http://sourceforge.net/projects/avra |
*/ |
/* |
* In append_type: added generic register names support |
* Alexey Pavluchenko, 16.Nov.2005 |
*/ |
#include <stdio.h> |
#include <stdlib.h> |
#include <string.h> |
#include <ctype.h> |
#include "misc.h" |
#include "args.h" |
#include "avra.h" |
#include "device.h" |
/* Only Windows LIBC does support itoa, so we add this |
function for other systems here manually. Thank you |
Peter Hettkamp for your work. */ |
#ifndef WIN32 |
char * itoa(int num, char *str, const int number_format) |
{ |
int num1 = num; |
int num_chars = 0; |
int pos; |
while (num1>0) |
{ |
num_chars++; |
num1 /= number_format; |
} |
if (num_chars == 0) num_chars = 1; |
str[num_chars] = 0; |
for (pos = num_chars-1; pos>=0; pos--) |
{ |
int cur_char = num % number_format; |
if (cur_char < 10) /* Insert number */ |
{ |
str[pos] = cur_char + '0'; |
} |
else |
{ |
str[pos] = cur_char-10 + 'A'; |
} |
num /= number_format; |
} |
return(str); |
} |
#endif |
int read_macro(struct prog_info *pi, char *name) |
{ |
int loopok; |
int i; |
int start; |
struct macro *macro; |
struct macro_line *macro_line; |
struct macro_line **last_macro_line = NULL; |
struct macro_label *macro_label; |
if(pi->pass == PASS_1) { |
if(!name) { |
print_msg(pi, MSGTYPE_ERROR, "missing macro name"); |
return(True); |
} |
get_next_token(name, TERM_END); |
for(i = 0; !IS_END_OR_COMMENT(name[i]); i++) { |
if(!IS_LABEL(name[i])) { |
print_msg(pi, MSGTYPE_ERROR, "illegal characters used in macro name '%s'",name); |
return(False); |
} |
} |
macro = calloc(1, sizeof(struct macro)); |
if(!macro) { |
print_msg(pi, MSGTYPE_OUT_OF_MEM, NULL); |
return(False); |
} |
if(pi->last_macro) |
pi->last_macro->next = macro; |
else |
pi->first_macro = macro; |
pi->last_macro = macro; |
macro->name = malloc(strlen(name) + 1); |
if(!macro->name) { |
print_msg(pi, MSGTYPE_OUT_OF_MEM, NULL); |
return(False); |
} |
strcpy(macro->name, name); |
macro->include_file = pi->fi->include_file; |
macro->first_line_number = pi->fi->line_number; |
last_macro_line = ¯o->first_macro_line; |
} |
else { /* pi->pass == PASS_2 */ |
if(pi->list_line && pi->list_on) { |
fprintf(pi->list_file, " %s\n", pi->list_line); |
pi->list_line = NULL; |
} |
// reset macro label running numbers |
get_next_token(name, TERM_END); |
macro = get_macro(pi, name); |
if (!macro) { |
print_msg(pi, MSGTYPE_ERROR, "macro inconsistency in '%s'", name); |
return(True); |
} |
for(macro_label = macro->first_label; macro_label; macro_label = macro_label->next) { |
macro_label->running_number = 0; |
} |
} |
loopok = True; |
while(loopok) { |
if(fgets_new(pi,pi->fi->buff, LINEBUFFER_LENGTH, pi->fi->fp)) { |
pi->fi->line_number++; |
i = 0; |
while(IS_HOR_SPACE(pi->fi->buff[i]) && !IS_END_OR_COMMENT(pi->fi->buff[i])) i++; |
if(pi->fi->buff[i] == '.') { |
i++; |
if(!nocase_strncmp(&pi->fi->buff[i], "endm", 4)) |
loopok = False; |
if(!nocase_strncmp(&pi->fi->buff[i], "endmacro", 8)) |
loopok = False; |
} |
if(pi->pass == PASS_1) { |
if(loopok) { |
i = 0; /* find start of line */ |
while(IS_HOR_SPACE(pi->fi->buff[i]) && !IS_END_OR_COMMENT(pi->fi->buff[i])) { |
i++; |
} |
start = i; |
/* find end of line */ |
while(!IS_END_OR_COMMENT(pi->fi->buff[i]) && (IS_LABEL(pi->fi->buff[i]) || pi->fi->buff[i] == ':')) { |
i++; |
} |
if(pi->fi->buff[i-1] == ':' && (pi->fi->buff[i-2] == '%' |
&& (IS_HOR_SPACE(pi->fi->buff[i]) || IS_END_OR_COMMENT(pi->fi->buff[i])))) { |
if(macro->first_label) { |
for(macro_label = macro->first_label; macro_label->next; macro_label=macro_label->next){} |
macro_label->next = calloc(1,sizeof(struct macro_label)); |
macro_label = macro_label->next; |
} |
else { |
macro_label = calloc(1,sizeof(struct macro_label)); |
macro->first_label = macro_label; |
} |
macro_label->label = malloc(strlen(&pi->fi->buff[start])+1); |
pi->fi->buff[i-1] = '\0'; |
strcpy(macro_label->label, &pi->fi->buff[start]); |
pi->fi->buff[i-1] = ':'; |
macro_label->running_number = 0; |
} |
macro_line = calloc(1, sizeof(struct macro_line)); |
if(!macro_line) { |
print_msg(pi, MSGTYPE_OUT_OF_MEM, NULL); |
return(False); |
} |
*last_macro_line = macro_line; |
last_macro_line = ¯o_line->next; |
macro_line->line = malloc(strlen(pi->fi->buff) + 1); |
if(!macro_line->line) { |
print_msg(pi, MSGTYPE_OUT_OF_MEM, NULL); |
return(False); |
} |
strcpy(macro_line->line, &pi->fi->buff[start]); |
} |
} |
else if(pi->fi->buff && pi->list_file && pi->list_on) { |
if(pi->fi->buff[i] == ';') |
fprintf(pi->list_file, " %s\n", pi->fi->buff); |
else |
fprintf(pi->list_file, " %s\n", pi->fi->buff); |
} |
} |
else { |
if(feof(pi->fi->fp)) { |
print_msg(pi, MSGTYPE_ERROR, "Found no closing .ENDMACRO"); |
return(True); |
} |
else { |
perror(pi->fi->include_file->name); |
return(False); |
} |
} |
} |
return(True); |
} |
struct macro *get_macro(struct prog_info *pi, char *name) |
{ |
struct macro *macro; |
for(macro = pi->first_macro; macro; macro = macro->next) |
if(!nocase_strcmp(macro->name, name)) |
return(macro); |
return(NULL); |
} |
void append_type(struct prog_info *pi, char *name, int c, char *value) |
{ |
int p, l; |
struct def *def; |
p = strlen(name); |
name[p++] = '_'; |
if(c == 0) |
{ |
name[p++] = 'v'; |
name[p] = '\0'; |
return; |
} |
l = strlen(value); |
if ((l==2 || l==3) && (tolower(value[0])=='r') && isdigit(value[1]) && (l==3?isdigit(value[2]):1) && (atoi(&value[1])<32)) |
{ |
itoa((c*8),&name[p],10); |
return; |
} |
for(def = pi->first_def; def; def = def->next) |
if(!nocase_strcmp(def->name, value)) |
{ |
itoa((c*8),&name[p],10); |
return; |
} |
name[p++] = 'i'; |
name[p] = '\0'; |
} |
/********************************************************* |
* This routine replaces the macro call with mnemonics. * |
*********************************************************/ |
int expand_macro(struct prog_info *pi, struct macro *macro, char *rest_line) |
{ |
int ok = True, macro_arg_count = 0, off, a, b = 0, c, i = 0, j = 0; |
char *line = NULL; |
char *temp; |
char *macro_args[MAX_MACRO_ARGS]; |
char tmp[7]; |
char buff[LINEBUFFER_LENGTH]; |
char arg = False; |
char *nmn; //string buffer for 'n'ew 'm'acro 'n'ame |
struct macro_line *old_macro_line; |
struct macro_call *macro_call; |
struct macro_label *macro_label; |
if(rest_line) { |
//we reserve some extra space for extended macro parameters |
line = malloc(strlen(rest_line) + 20); |
if(!line) { |
print_msg(pi, MSGTYPE_OUT_OF_MEM, NULL); |
return(False); |
} |
/* exchange amca word 'src' with YH:YL and 'dst' with ZH:ZL */ |
for(c = 0, a = strlen(rest_line); c < a; c++) { |
switch (tolower(rest_line[c])) { |
case 's': |
if(IS_SEPARATOR(rest_line[c-1]) && (rest_line[c+1] == 'r') && (rest_line[c+2] == 'c') && IS_SEPARATOR(rest_line[c+3])) { |
strcpy(&line[b],"YH:YL"); |
b += 5; |
c += 2; |
} |
else { |
line[b++] = rest_line[c]; |
} |
break; |
case 'd': |
if(IS_SEPARATOR(rest_line[c-1]) && (rest_line[c+1] == 's') && (rest_line[c+2] == 't') && IS_SEPARATOR(rest_line[c+3])) { |
strcpy(&line[b],"ZH:ZL"); |
b += 5; |
c += 2; |
} |
else { |
line[b++] = rest_line[c]; |
} |
break; |
// case ';': |
// break; |
default: |
line[b++] = rest_line[c]; |
} |
} |
strcpy(&line[b],"\n"); /* set CR/LF at the end of the line */ |
/* here we split up the macro arguments into "macro_args" |
* Extended macro code interpreter added by TW 2002 |
*/ |
temp = line; |
/* test for advanced parameters */ |
if( temp[0] == '[' ) { // there must be "[" " then "]", else it is garbage |
if(!strchr(temp, ']')) { |
print_msg(pi, MSGTYPE_ERROR, "found no closing ']'"); |
return(False); |
} |
// Okay now we are within the advanced code interpreter |
temp++; // = &temp[1]; // skip the first bracket |
nmn = malloc(LINEBUFFER_LENGTH); |
if(!nmn) { |
print_msg(pi, MSGTYPE_OUT_OF_MEM, NULL); |
return(False); |
} |
strcpy(nmn,macro->name); // create a new macro name buffer |
c = 1; // byte counter |
arg = True; // loop flag |
while(arg) { |
while(IS_HOR_SPACE(temp[0])) { //skip leading spaces |
temp++; // = &temp[1]; |
} |
off = 0; // pointer offset |
do { |
switch(temp[off]) { //test current character code |
case ':': |
temp[off] = '\0'; |
if(off > 0) { |
c++; |
macro_args[macro_arg_count++] = temp; |
} |
else { |
print_msg(pi, MSGTYPE_ERROR, "missing register before ':'",nmn); |
return(False); |
} |
break; |
case ']': |
arg = False; |
case ',': |
a = off; |
do temp[a--] = '\0'; while( IS_HOR_SPACE(temp[a]) ); |
if(off > 0) { |
macro_args[macro_arg_count++] = temp; |
append_type(pi, nmn, c, temp); |
c = 1; |
} |
else { |
append_type(pi, nmn, 0, temp); |
c = 1; |
} |
break; |
default: |
off++; |
} |
} |
while(temp[off] != '\0'); |
if(arg) temp = &temp[off+1]; |
else break; |
} |
macro = get_macro(pi,nmn); |
if(macro == NULL) { |
print_msg(pi, MSGTYPE_ERROR, "Macro %s is not defined !",nmn); |
return(False); |
} |
free(nmn); |
} |
/* or else, we handle the macro as normal macro */ |
else { |
line = malloc(strlen(rest_line) + 1); |
if(!line) { |
print_msg(pi, MSGTYPE_OUT_OF_MEM, NULL); |
return(False); |
} |
strcpy(line, rest_line); |
temp = line; |
while(temp) { |
macro_args[macro_arg_count++] = temp; |
temp = get_next_token(temp, TERM_COMMA); |
} |
} |
} |
if(pi->pass == PASS_1) { |
macro_call = calloc(1, sizeof(struct macro_call)); |
if(!macro_call) { |
print_msg(pi, MSGTYPE_OUT_OF_MEM, NULL); |
return(False); |
} |
if(pi->last_macro_call) |
pi->last_macro_call->next = macro_call; |
else |
pi->first_macro_call = macro_call; |
pi->last_macro_call = macro_call; |
macro_call->line_number = pi->fi->line_number; |
macro_call->include_file = pi->fi->include_file; |
macro_call->macro = macro; |
macro_call->prev_on_stack = pi->macro_call; |
if(macro_call->prev_on_stack) { |
macro_call->nest_level = macro_call->prev_on_stack->nest_level + 1; |
macro_call->prev_line_index = macro_call->prev_on_stack->line_index; |
} |
} |
else { |
for(macro_call = pi->first_macro_call; macro_call; macro_call = macro_call->next) { |
if((macro_call->include_file->num == pi->fi->include_file->num) && (macro_call->line_number == pi->fi->line_number)) { |
if(pi->macro_call) { |
/* Find correct macro_call when using recursion and nesting */ |
if(macro_call->prev_on_stack == pi->macro_call) |
if((macro_call->nest_level == (pi->macro_call->nest_level + 1)) && (macro_call->prev_line_index == pi->macro_call->line_index)) |
break; |
} |
else break; |
} |
} |
if(pi->list_line && pi->list_on) { |
fprintf(pi->list_file, "C:%06x + %s\n", pi->cseg_addr, pi->list_line); |
pi->list_line = NULL; |
} |
} |
macro_call->line_index = 0; |
pi->macro_call = macro_call; |
old_macro_line = pi->macro_line; |
//printf("\nconvert macro: '%s'\n",macro->name); |
for(pi->macro_line = macro->first_macro_line; pi->macro_line && ok; pi->macro_line = pi->macro_line->next) { |
macro_call->line_index++; |
if(GET_ARG(pi->args, ARG_LISTMAC)) |
pi->list_line = buff; |
else |
pi->list_line = NULL; |
/* here we change jumps/calls within macro that corresponds to macro labels. |
Only in case there is an entry in macro_label list */ |
strcpy(buff,"\0"); |
macro_label = get_macro_label(pi->macro_line->line,macro); |
if(macro_label) { |
/* test if the right macro label has been found */ |
temp = strstr(pi->macro_line->line,macro_label->label); |
c = strlen(macro_label->label); |
if(temp[c] == ':') { /* it is a label definition */ |
macro_label->running_number++; |
strncpy(buff, macro_label->label, c - 1); |
buff[c - 1] = 0; |
i = strlen(buff) + 2; /* we set the process indeafter label */ |
/* add running number to it */ |
strcpy(&buff[c-1],itoa(macro_label->running_number, tmp, 10)); |
strcat(buff, ":\0"); |
} |
else if(IS_HOR_SPACE(temp[c]) || IS_END_OR_COMMENT(temp[c])) { /* it is a jump to a macro defined label */ |
strcpy(buff,pi->macro_line->line); |
temp = strstr(buff, macro_label->label); |
i = temp - buff + strlen(macro_label->label); |
strncpy(temp, macro_label->label, c - 1); |
strcpy(&temp[c-1], itoa(macro_label->running_number, tmp, 10)); |
} |
} |
else { |
i = 0; |
} |
/* here we check every character of current line */ |
for(j = i; pi->macro_line->line[i] != '\0'; i++) { |
/* check for register place holders */ |
if(pi->macro_line->line[i] == '@') { |
i++; |
if(!isdigit(pi->macro_line->line[i])) |
print_msg(pi, MSGTYPE_ERROR, "@ must be followed by a number"); |
else if((pi->macro_line->line[i] - '0') >= macro_arg_count) |
print_msg(pi, MSGTYPE_ERROR, "Missing macro argument (for @%c)", pi->macro_line->line[i]); |
else { |
/* and replace them with given registers */ |
strcat(&buff[j], macro_args[pi->macro_line->line[i] - '0']); |
j += strlen(macro_args[pi->macro_line->line[i] - '0']); |
} |
} |
else if (pi->macro_line->line[i] == ';') { |
strncat(buff, "\n", 1); |
break; |
} |
else { |
strncat(buff, &pi->macro_line->line[i], 1); |
} |
} |
ok = parse_line(pi, buff); |
if(ok) { |
if((pi->pass == PASS_2) && pi->list_line && pi->list_on) |
fprintf(pi->list_file, " %s\n", pi->list_line); |
if(pi->error_count >= pi->max_errors) { |
print_msg(pi, MSGTYPE_MESSAGE, "Maximum error count reached. Exiting..."); |
ok = False; |
break; |
} |
} |
} |
pi->macro_line = old_macro_line; |
pi->macro_call = macro_call->prev_on_stack; |
if(rest_line) |
free(line); |
return(ok); |
} |
struct macro_label *get_macro_label(char *line, struct macro *macro) |
{ |
char *temp ; |
struct macro_label *macro_label; |
for(macro_label = macro->first_label; macro_label; macro_label = macro_label->next) { |
temp = strstr(line,macro_label->label); |
if(temp) { |
return macro_label; |
} |
} |
return NULL; |
} |
/* end of macro.c */ |
/contrib/toolchain/avra/src/map.c |
---|
0,0 → 1,76 |
/*********************************************************************** |
* |
* avra - Assembler for the Atmel AVR microcontroller series |
* |
* Copyright (C) 1998-2004 Jon Anders Haugum, Tobias Weber |
* |
* This program is free software; you can redistribute it and/or modify |
* it under the terms of the GNU General Public License as published by |
* the Free Software Foundation; either version 2 of the License, or |
* (at your option) any later version. |
* |
* This program is distributed in the hope that it will be useful, |
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
* GNU General Public License for more details. |
* |
* You should have received a copy of the GNU General Public License |
* along with this program; see the file COPYING. If not, write to |
* the Free Software Foundation, Inc., 59 Temple Place - Suite 330, |
* Boston, MA 02111-1307, USA. |
* |
* |
* Authors of avra can be reached at: |
* email: jonah@omegav.ntnu.no, tobiw@suprafluid.com |
* www: http://sourceforge.net/projects/avra |
*/ |
#include <stdio.h> |
#include <string.h> |
#include "avra.h" |
#include "args.h" |
char *Space(char *n); |
void write_map_file(struct prog_info *pi) |
{ |
FILE *fp; |
struct label *label; |
char Filename[200]; |
if (!pi->map_on) { |
return; |
} |
strcpy(Filename, GET_ARG(pi->args, ARG_MAPFILE)); |
fp = fopen(Filename,"w"); |
if( fp == NULL ) { |
fprintf(stderr,"Error: cannot create map file\n"); |
return; |
} |
for(label = pi->first_constant; label; label = label->next) |
fprintf(fp,"%s%sC\t%04x\t%d\n",label->name,Space(label->name),label->value,label->value); |
for(label = pi->first_variable; label; label = label->next) |
fprintf(fp,"%s%sV\t%04x\t%d\n",label->name,Space(label->name),label->value,label->value); |
for(label = pi->first_label; label; label = label->next) |
fprintf(fp,"%s%sL\t%04x\t%d\n",label->name,Space(label->name),label->value,label->value); |
fprintf(fp,"\n"); |
fclose(fp); |
return; |
} |
char *Space(char *n) |
{ |
int i; |
i = strlen(n); |
if( i < 1) return "\t\t\t"; |
if( i < 8 ) return "\t\t"; |
return "\t"; |
} |
/* end of map.c */ |
/contrib/toolchain/avra/src/misc.h |
---|
0,0 → 1,19 |
/*********************************************************************** |
* |
* avra - Assembler for the Atmel AVR microcontroller series |
* |
* Copyright (C) 1998-2003 Jon Anders Haugum, Tobias Weber |
* |
* Misc stuff |
*/ |
enum boolean {False = 0, True}; |
enum filetype |
{ |
AVRSTUDIO = 0, |
GENERIC, |
INTEL, |
MOTOROLA |
}; |
/contrib/toolchain/avra/src/mnemonic.c |
---|
0,0 → 1,795 |
/*********************************************************************** |
* |
* avra - Assembler for the Atmel AVR microcontroller series |
* |
* Copyright (C) 1998-2004 Jon Anders Haugum, Tobias Weber |
* |
* This program is free software; you can redistribute it and/or modify |
* it under the terms of the GNU General Public License as published by |
* the Free Software Foundation; either version 2 of the License, or |
* (at your option) any later version. |
* |
* This program is distributed in the hope that it will be useful, |
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
* GNU General Public License for more details. |
* |
* You should have received a copy of the GNU General Public License |
* along with this program; see the file COPYING. If not, write to |
* the Free Software Foundation, Inc., 59 Temple Place - Suite 330, |
* Boston, MA 02111-1307, USA. |
* |
* |
* Authors of avra can be reached at: |
* email: jonah@omegav.ntnu.no, tobiw@suprafluid.com |
* www: http://sourceforge.net/projects/avra |
*/ |
#include <stdio.h> |
#include <stdlib.h> |
#include <string.h> |
#include <ctype.h> |
#include "misc.h" |
#include "avra.h" |
#include "device.h" |
#define MAX_MNEMONIC_LEN 8 // Maximum mnemonic length |
enum { |
MNEMONIC_NOP = 0, // 0000 0000 0000 0000 |
MNEMONIC_SEC, // 1001 0100 0000 1000 |
MNEMONIC_CLC, // 1001 0100 1000 1000 |
MNEMONIC_SEN, // 1001 0100 0010 1000 |
MNEMONIC_CLN, // 1001 0100 1010 1000 |
MNEMONIC_SEZ, // 1001 0100 0001 1000 |
MNEMONIC_CLZ, // 1001 0100 1001 1000 |
MNEMONIC_SEI, // 1001 0100 0111 1000 |
MNEMONIC_CLI, // 1001 0100 1111 1000 |
MNEMONIC_SES, // 1001 0100 0100 1000 |
MNEMONIC_CLS, // 1001 0100 1100 1000 |
MNEMONIC_SEV, // 1001 0100 0011 1000 |
MNEMONIC_CLV, // 1001 0100 1011 1000 |
MNEMONIC_SET, // 1001 0100 0110 1000 |
MNEMONIC_CLT, // 1001 0100 1110 1000 |
MNEMONIC_SEH, // 1001 0100 0101 1000 |
MNEMONIC_CLH, // 1001 0100 1101 1000 |
MNEMONIC_SLEEP, // 1001 0101 1000 1000 |
MNEMONIC_WDR, // 1001 0101 1010 1000 |
MNEMONIC_IJMP, // 1001 0100 0000 1001 |
MNEMONIC_EIJMP, // 1001 0100 0001 1001 |
MNEMONIC_ICALL, // 1001 0101 0000 1001 |
MNEMONIC_EICALL, // 1001 0101 0001 1001 |
MNEMONIC_RET, // 1001 0101 0000 1000 |
MNEMONIC_RETI, // 1001 0101 0001 1000 |
MNEMONIC_SPM, // 1001 0101 1110 1000 |
MNEMONIC_ESPM, // 1001 0101 1111 1000 |
MNEMONIC_BREAK, // 1001 0101 1001 1000 |
MNEMONIC_LPM, // 1001 0101 1100 1000 |
MNEMONIC_ELPM, // 1001 0101 1101 1000 |
MNEMONIC_BSET, // s 1001 0100 0sss 1000 |
MNEMONIC_BCLR, // s 1001 0100 1sss 1000 |
MNEMONIC_SER, // Rd 1110 1111 dddd 1111 |
MNEMONIC_COM, // Rd 1001 010d dddd 0000 |
MNEMONIC_NEG, // Rd 1001 010d dddd 0001 |
MNEMONIC_INC, // Rd 1001 010d dddd 0011 |
MNEMONIC_DEC, // Rd 1001 010d dddd 1010 |
MNEMONIC_LSR, // Rd 1001 010d dddd 0110 |
MNEMONIC_ROR, // Rd 1001 010d dddd 0111 |
MNEMONIC_ASR, // Rd 1001 010d dddd 0101 |
MNEMONIC_SWAP, // Rd 1001 010d dddd 0010 |
MNEMONIC_PUSH, // Rr 1001 001r rrrr 1111 |
MNEMONIC_POP, // Rd 1001 000d dddd 1111 |
MNEMONIC_TST, // Rd 0010 00dd dddd dddd |
MNEMONIC_CLR, // Rd 0010 01dd dddd dddd |
MNEMONIC_LSL, // Rd 0000 11dd dddd dddd |
MNEMONIC_ROL, // Rd 0001 11dd dddd dddd |
MNEMONIC_BREQ, // k 1111 00kk kkkk k001 |
MNEMONIC_BRNE, // k 1111 01kk kkkk k001 |
MNEMONIC_BRCS, // k 1111 00kk kkkk k000 |
MNEMONIC_BRCC, // k 1111 01kk kkkk k000 |
MNEMONIC_BRSH, // k 1111 01kk kkkk k000 |
MNEMONIC_BRLO, // k 1111 00kk kkkk k000 |
MNEMONIC_BRMI, // k 1111 00kk kkkk k010 |
MNEMONIC_BRPL, // k 1111 01kk kkkk k010 |
MNEMONIC_BRGE, // k 1111 01kk kkkk k100 |
MNEMONIC_BRLT, // k 1111 00kk kkkk k100 |
MNEMONIC_BRHS, // k 1111 00kk kkkk k101 |
MNEMONIC_BRHC, // k 1111 01kk kkkk k101 |
MNEMONIC_BRTS, // k 1111 00kk kkkk k110 |
MNEMONIC_BRTC, // k 1111 01kk kkkk k110 |
MNEMONIC_BRVS, // k 1111 00kk kkkk k011 |
MNEMONIC_BRVC, // k 1111 01kk kkkk k011 |
MNEMONIC_BRIE, // k 1111 00kk kkkk k111 |
MNEMONIC_BRID, // k 1111 01kk kkkk k111 |
MNEMONIC_RJMP, // k 1100 kkkk kkkk kkkk |
MNEMONIC_RCALL, // k 1101 kkkk kkkk kkkk |
MNEMONIC_JMP, // k 1001 010k kkkk 110k + 16k |
MNEMONIC_CALL, // k 1001 010k kkkk 111k + 16k |
MNEMONIC_BRBS, // s, k 1111 00kk kkkk ksss |
MNEMONIC_BRBC, // s, k 1111 01kk kkkk ksss |
MNEMONIC_ADD, // Rd, Rr 0000 11rd dddd rrrr |
MNEMONIC_ADC, // Rd, Rr 0001 11rd dddd rrrr |
MNEMONIC_SUB, // Rd, Rr 0001 10rd dddd rrrr |
MNEMONIC_SBC, // Rd, Rr 0000 10rd dddd rrrr |
MNEMONIC_AND, // Rd, Rr 0010 00rd dddd rrrr |
MNEMONIC_OR, // Rd, Rr 0010 10rd dddd rrrr |
MNEMONIC_EOR, // Rd, Rr 0010 01rd dddd rrrr |
MNEMONIC_CP, // Rd, Rr 0001 01rd dddd rrrr |
MNEMONIC_CPC, // Rd, Rr 0000 01rd dddd rrrr |
MNEMONIC_CPSE, // Rd, Rr 0001 00rd dddd rrrr |
MNEMONIC_MOV, // Rd, Rr 0010 11rd dddd rrrr |
MNEMONIC_MUL, // Rd, Rr 1001 11rd dddd rrrr |
MNEMONIC_MOVW, // Rd, Rr 0000 0001 dddd rrrr |
MNEMONIC_MULS, // Rd, Rr 0000 0010 dddd rrrr |
MNEMONIC_MULSU, // Rd, Rr 0000 0011 0ddd 0rrr |
MNEMONIC_FMUL, // Rd, Rr 0000 0011 0ddd 1rrr |
MNEMONIC_FMULS, // Rd, Rr 0000 0011 1ddd 0rrr |
MNEMONIC_FMULSU, // Rd, Rr 0000 0011 1ddd 1rrr |
MNEMONIC_ADIW, // Rd, K 1001 0110 KKdd KKKK |
MNEMONIC_SBIW, // Rd, K 1001 0111 KKdd KKKK |
MNEMONIC_SUBI, // Rd, K 0101 KKKK dddd KKKK |
MNEMONIC_SBCI, // Rd, K 0100 KKKK dddd KKKK |
MNEMONIC_ANDI, // Rd, K 0111 KKKK dddd KKKK |
MNEMONIC_ORI, // Rd, K 0110 KKKK dddd KKKK |
MNEMONIC_SBR, // Rd, K 0110 KKKK dddd KKKK |
MNEMONIC_CPI, // Rd, K 0011 KKKK dddd KKKK |
MNEMONIC_LDI, // Rd, K 1110 KKKK dddd KKKK |
MNEMONIC_CBR, // Rd, K 0111 KKKK dddd KKKK ~K |
MNEMONIC_SBRC, // Rr, b 1111 110r rrrr 0bbb |
MNEMONIC_SBRS, // Rr, b 1111 111r rrrr 0bbb |
MNEMONIC_BST, // Rr, b 1111 101d dddd 0bbb |
MNEMONIC_BLD, // Rd, b 1111 100d dddd 0bbb |
MNEMONIC_IN, // Rd, P 1011 0PPd dddd PPPP |
MNEMONIC_OUT, // P, Rr 1011 1PPr rrrr PPPP |
MNEMONIC_SBIC, // P, b 1001 1001 PPPP Pbbb |
MNEMONIC_SBIS, // P, b 1001 1011 PPPP Pbbb |
MNEMONIC_SBI, // P, b 1001 1010 PPPP Pbbb |
MNEMONIC_CBI, // P, b 1001 1000 PPPP Pbbb |
MNEMONIC_LDS, // Rd, k 1001 000d dddd 0000 + 16k |
MNEMONIC_STS, // k, Rr 1001 001d dddd 0000 + 16k |
MNEMONIC_LD, // Rd, __ dummy |
MNEMONIC_ST, // __, Rr dummy |
MNEMONIC_LDD, // Rd, _+q dummy |
MNEMONIC_STD, // _+q, Rr dummy |
MNEMONIC_COUNT, |
MNEMONIC_LPM_Z, // Rd, Z 1001 000d dddd 0100 |
MNEMONIC_LPM_ZP, // Rd, Z+ 1001 000d dddd 0101 |
MNEMONIC_ELPM_Z, // Rd, Z 1001 000d dddd 0110 |
MNEMONIC_ELPM_ZP, // Rd, Z+ 1001 000d dddd 0111 |
MNEMONIC_LD_X, // Rd, X 1001 000d dddd 1100 |
MNEMONIC_LD_XP, // Rd, X+ 1001 000d dddd 1101 |
MNEMONIC_LD_MX, // Rd, -X 1001 000d dddd 1110 |
MNEMONIC_LD_Y, // Rd, Y 1000 000d dddd 1000 |
MNEMONIC_LD_YP, // Rd, Y+ 1001 000d dddd 1001 |
MNEMONIC_LD_MY, // Rd, -Y 1001 000d dddd 1010 |
MNEMONIC_LD_Z, // Rd, Z 1000 000d dddd 0000 |
MNEMONIC_LD_ZP, // Rd, Z+ 1001 000d dddd 0001 |
MNEMONIC_LD_MZ, // Rd, -Z 1001 000d dddd 0010 |
MNEMONIC_ST_X, // X, Rr 1001 001d dddd 1100 |
MNEMONIC_ST_XP, // X+, Rr 1001 001d dddd 1101 |
MNEMONIC_ST_MX, // -X, Rr 1001 001d dddd 1110 |
MNEMONIC_ST_Y, // Y, Rr 1000 001d dddd 1000 |
MNEMONIC_ST_YP, // Y+, Rr 1001 001d dddd 1001 |
MNEMONIC_ST_MY, // -Y, Rr 1001 001d dddd 1010 |
MNEMONIC_ST_Z, // Z, Rr 1000 001d dddd 0000 |
MNEMONIC_ST_ZP, // Z+, Rr 1001 001d dddd 0001 |
MNEMONIC_ST_MZ, // -Z, Rr 1001 001d dddd 0010 |
MNEMONIC_LDD_Y, // Rd, Y+q 10q0 qq0d dddd 1qqq |
MNEMONIC_LDD_Z, // Rd, Z+q 10q0 qq0d dddd 0qqq |
MNEMONIC_STD_Y, // Y+q, Rr 10q0 qq1r rrrr 1qqq |
MNEMONIC_STD_Z, // Z+q, Rr 10q0 qq1r rrrr 0qqq |
MNEMONIC_END |
}; |
struct instruction { |
char *mnemonic; |
int opcode; |
int flag; /* Device flags meaning the instruction is not |
supported */ |
}; |
struct instruction instruction_list[] = { |
{"nop", 0x0000, 0}, |
{"sec", 0x9408, 0}, |
{"clc", 0x9488, 0}, |
{"sen", 0x9428, 0}, |
{"cln", 0x94a8, 0}, |
{"sez", 0x9418, 0}, |
{"clz", 0x9498, 0}, |
{"sei", 0x9478, 0}, |
{"cli", 0x94f8, 0}, |
{"ses", 0x9448, 0}, |
{"cls", 0x94c8, 0}, |
{"sev", 0x9438, 0}, |
{"clv", 0x94b8, 0}, |
{"set", 0x9468, 0}, |
{"clt", 0x94e8, 0}, |
{"seh", 0x9458, 0}, |
{"clh", 0x94d8, 0}, |
{"sleep", 0x9588, 0}, |
{"wdr", 0x95a8, 0}, |
{"ijmp", 0x9409, DF_TINY1X}, |
{"eijmp", 0x9419, DF_NO_EIJMP}, |
{"icall", 0x9509, DF_TINY1X}, |
{"eicall",0x9519, DF_NO_EICALL}, |
{"ret", 0x9508, 0}, |
{"reti", 0x9518, 0}, |
{"spm", 0x95e8, DF_NO_SPM}, |
{"espm", 0x95f8, DF_NO_ESPM}, |
{"break", 0x9598, DF_NO_BREAK}, |
{"lpm", 0x95c8, DF_NO_LPM}, |
{"elpm", 0x95d8, DF_NO_ELPM}, |
{"bset", 0x9408, 0}, |
{"bclr", 0x9488, 0}, |
{"ser", 0xef0f, 0}, |
{"com", 0x9400, 0}, |
{"neg", 0x9401, 0}, |
{"inc", 0x9403, 0}, |
{"dec", 0x940a, 0}, |
{"lsr", 0x9406, 0}, |
{"ror", 0x9407, 0}, |
{"asr", 0x9405, 0}, |
{"swap", 0x9402, 0}, |
{"push", 0x920f, DF_TINY1X}, |
{"pop", 0x900f, DF_TINY1X}, |
{"tst", 0x2000, 0}, |
{"clr", 0x2400, 0}, |
{"lsl", 0x0c00, 0}, |
{"rol", 0x1c00, 0}, |
{"breq", 0xf001, 0}, |
{"brne", 0xf401, 0}, |
{"brcs", 0xf000, 0}, |
{"brcc", 0xf400, 0}, |
{"brsh", 0xf400, 0}, |
{"brlo", 0xf000, 0}, |
{"brmi", 0xf002, 0}, |
{"brpl", 0xf402, 0}, |
{"brge", 0xf404, 0}, |
{"brlt", 0xf004, 0}, |
{"brhs", 0xf005, 0}, |
{"brhc", 0xf405, 0}, |
{"brts", 0xf006, 0}, |
{"brtc", 0xf406, 0}, |
{"brvs", 0xf003, 0}, |
{"brvc", 0xf403, 0}, |
{"brie", 0xf007, 0}, |
{"brid", 0xf407, 0}, |
{"rjmp", 0xc000, 0}, |
{"rcall", 0xd000, 0}, |
{"jmp", 0x940c, DF_NO_JMP}, |
{"call", 0x940e, DF_NO_JMP}, |
{"brbs", 0xf000, 0}, |
{"brbc", 0xf400, 0}, |
{"add", 0x0c00, 0}, |
{"adc", 0x1c00, 0}, |
{"sub", 0x1800, 0}, |
{"sbc", 0x0800, 0}, |
{"and", 0x2000, 0}, |
{"or", 0x2800, 0}, |
{"eor", 0x2400, 0}, |
{"cp", 0x1400, 0}, |
{"cpc", 0x0400, 0}, |
{"cpse", 0x1000, 0}, |
{"mov", 0x2c00, 0}, |
{"mul", 0x9c00, DF_NO_MUL}, |
{"movw", 0x0100, DF_NO_MOVW}, |
{"muls", 0x0200, DF_NO_MUL}, |
{"mulsu", 0x0300, DF_NO_MUL}, |
{"fmul", 0x0308, DF_NO_MUL}, |
{"fmuls", 0x0380, DF_NO_MUL}, |
{"fmulsu",0x0388, DF_NO_MUL}, |
{"adiw", 0x9600, DF_TINY1X}, |
{"sbiw", 0x9700, DF_TINY1X}, |
{"subi", 0x5000, 0}, |
{"sbci", 0x4000, 0}, |
{"andi", 0x7000, 0}, |
{"ori", 0x6000, 0}, |
{"sbr", 0x6000, 0}, |
{"cpi", 0x3000, 0}, |
{"ldi", 0xe000, 0}, |
{"cbr", 0x7000, 0}, |
{"sbrc", 0xfc00, 0}, |
{"sbrs", 0xfe00, 0}, |
{"bst", 0xfa00, 0}, |
{"bld", 0xf800, 0}, |
{"in", 0xb000, 0}, |
{"out", 0xb800, 0}, |
{"sbic", 0x9900, 0}, |
{"sbis", 0x9b00, 0}, |
{"sbi", 0x9a00, 0}, |
{"cbi", 0x9800, 0}, |
{"lds", 0x9000, DF_TINY1X}, |
{"sts", 0x9200, DF_TINY1X}, |
{"ld", 0, 0}, |
{"st", 0, 0}, |
{"ldd", 0, DF_TINY1X}, |
{"std", 0, DF_TINY1X}, |
{"count", 0, 0}, |
{"lpm", 0x9004, DF_NO_LPM|DF_NO_LPM_X}, |
{"lpm", 0x9005, DF_NO_LPM|DF_NO_LPM_X}, |
{"elpm", 0x9006, DF_NO_ELPM|DF_NO_ELPM_X}, |
{"elpm", 0x9007, DF_NO_ELPM|DF_NO_ELPM_X}, |
{"ld", 0x900c, DF_NO_XREG}, |
{"ld", 0x900d, DF_NO_XREG}, |
{"ld", 0x900e, DF_NO_XREG}, |
{"ld", 0x8008, DF_NO_YREG}, |
{"ld", 0x9009, DF_NO_YREG}, |
{"ld", 0x900a, DF_NO_YREG}, |
{"ld", 0x8000, 0}, |
{"ld", 0x9001, DF_TINY1X}, |
{"ld", 0x9002, DF_TINY1X}, |
{"st", 0x920c, DF_NO_XREG}, |
{"st", 0x920d, DF_NO_XREG}, |
{"st", 0x920e, DF_NO_XREG}, |
{"st", 0x8208, DF_NO_YREG}, |
{"st", 0x9209, DF_NO_YREG}, |
{"st", 0x920a, DF_NO_YREG}, |
{"st", 0x8200, 0}, |
{"st", 0x9201, DF_TINY1X}, |
{"st", 0x9202, DF_TINY1X}, |
{"ldd", 0x8008, DF_TINY1X}, |
{"ldd", 0x8000, DF_TINY1X}, |
{"std", 0x8208, DF_TINY1X}, |
{"std", 0x8200, DF_TINY1X}, |
{"end", 0, 0} |
}; |
/* We try to parse the command name. Is it a assembler mnemonic or anything else ? |
* If so, it may be a macro. |
*/ |
int parse_mnemonic(struct prog_info *pi) |
{ |
int mnemonic; |
int i; |
int opcode = 0; |
int opcode2 = 0; |
int instruction_long = False; |
char *operand1; |
char *operand2; |
struct macro *macro; |
char temp[MAX_MNEMONIC_LEN + 1]; |
operand1 = get_next_token(pi->fi->scratch, TERM_SPACE); // we get the first word on line |
mnemonic = get_mnemonic_type(my_strlwr(pi->fi->scratch)); |
if(mnemonic == -1) { // if -1 this must be a macro name |
macro = get_macro(pi, pi->fi->scratch); // and so, we try to get the corresponding macro struct. |
if(macro) { |
return(expand_macro(pi, macro, operand1)); // we expand the macro |
} else { // if we cant find a name, this is a unknown word. |
print_msg(pi, MSGTYPE_ERROR, "Unknown mnemonic/macro: %s", pi->fi->scratch); |
return(True); |
} |
} |
if(pi->pass == PASS_2) { |
if(mnemonic <= MNEMONIC_BREAK) { |
if(operand1) { |
+ } |
+ opcode = 0; // No operand |
+ } else if(mnemonic <= MNEMONIC_ELPM) { |
+ if(operand1) { |
+ operand2 = get_next_token(operand1, TERM_COMMA); |
+ if(!operand2) { |
+ print_msg(pi, MSGTYPE_ERROR, "%s needs a second operand", instruction_list[mnemonic].mnemonic); |
+ } |
+ get_next_token(operand2, TERM_END); |
+ i = get_register(pi, operand1); |
+ opcode = i << 4; |
+ i = get_indirect(pi, operand2); |
+ if(i == 6) { // Means Z |
+ if(mnemonic == MNEMONIC_LPM) |
+ mnemonic = MNEMONIC_LPM_Z; |
+ else if(mnemonic == MNEMONIC_ELPM) |
+ mnemonic = MNEMONIC_ELPM_Z; |
+ } else if(i == 7) { // Means Z+ |
+ if(mnemonic == MNEMONIC_LPM) |
+ mnemonic = MNEMONIC_LPM_ZP; |
+ else if(mnemonic == MNEMONIC_ELPM) |
+ mnemonic = MNEMONIC_ELPM_ZP; |
+ } else { |
+ print_msg(pi, MSGTYPE_ERROR, "Unsupported operand: %s", operand2); |
+ return(True); |
+ } |
+ } else |
+ opcode = 0; |
+ } else { |
+ if(!operand1) { |
+ print_msg(pi, MSGTYPE_ERROR, "%s needs an operand", instruction_list[mnemonic].mnemonic); |
+ return(True); |
+ } |
+ operand2 = get_next_token(operand1, TERM_COMMA); |
+ if(mnemonic >= MNEMONIC_BRBS) { |
+ if(!operand2) { |
+ print_msg(pi, MSGTYPE_ERROR, "%s needs a second operand", instruction_list[mnemonic].mnemonic); |
+ return(True); |
+ } |
+ get_next_token(operand2, TERM_END); |
+ } |
+ if(mnemonic <= MNEMONIC_BCLR) { |
+ if(!get_bitnum(pi, operand1, &i)) |
+ return(False); |
+ opcode = i << 4; |
+ } else if(mnemonic <= MNEMONIC_ROL) { |
+ i = get_register(pi, operand1); |
+ if((mnemonic == MNEMONIC_SER) && (i < 16)) { |
+ print_msg(pi, MSGTYPE_ERROR, "%s can only use a high register (r16 - r31)", instruction_list[mnemonic].mnemonic); |
+ i &= 0x0f; |
+ } |
+ opcode = i << 4; |
+ if(mnemonic >= MNEMONIC_TST) |
+ opcode |= ((i & 0x10) << 5) | (i & 0x0f); |
+ } else if(mnemonic <= MNEMONIC_RCALL) { |
+ if(!get_expr(pi, operand1, &i)) |
+ return(False); |
+ i -= pi->cseg_addr + 1; |
+ if(mnemonic <= MNEMONIC_BRID) { |
+ if((i < -64) || (i > 63)) |
+ print_msg(pi, MSGTYPE_ERROR, "Branch out of range (-64 <= k <= 63)"); |
+ opcode = (i & 0x7f) << 3; |
+ } else { |
+ if(((i < -2048) || (i > 2047)) && (pi->device->flash_size != 4096)) |
+ print_msg(pi, MSGTYPE_ERROR, "Relative address out of range (-2048 <= k <= 2047)"); |
+ opcode = i & 0x0fff; |
+ } |
+ } else if(mnemonic <= MNEMONIC_CALL) { |
+ if(!get_expr(pi, operand1, &i)) |
+ return(False); |
+ if((i < 0) || (i > 4194303)) |
+ print_msg(pi, MSGTYPE_ERROR, "Address out of range (0 <= k <= 4194303)"); |
+ opcode = ((i & 0x3e0000) >> 13) | ((i & 0x010000) >> 16); |
+ opcode2 = i & 0xffff; |
+ instruction_long = True; |
+ } else if(mnemonic <= MNEMONIC_BRBC) { |
+ if(!get_bitnum(pi, operand1, &i)) |
+ return(False); |
+ opcode = i; |
+ if(!get_expr(pi, operand2, &i)) |
+ return(False); |
+ i -= pi->cseg_addr + 1; |
+ if((i < -64) || (i > 63)) |
+ print_msg(pi, MSGTYPE_ERROR, "Branch out of range (-64 <= k <= 63)"); |
+ opcode |= (i & 0x7f) << 3; |
+ } else if(mnemonic <= MNEMONIC_MUL) { |
+ i = get_register(pi, operand1); |
+ opcode = i << 4; |
+ i = get_register(pi, operand2); |
+ opcode |= ((i & 0x10) << 5) | (i & 0x0f); |
+ } else if(mnemonic <= MNEMONIC_MOVW) { |
+ i = get_register(pi, operand1); |
+ if((i % 2) == 1) |
+ print_msg(pi, MSGTYPE_ERROR, "%s must use a even numbered register for Rd", instruction_list[mnemonic].mnemonic); |
+ opcode = (i / 2) << 4; |
+ i = get_register(pi, operand2); |
+ if((i % 2) == 1) |
+ print_msg(pi, MSGTYPE_ERROR, "%s must use a even numbered register for Rr", instruction_list[mnemonic].mnemonic); |
+ opcode |= i / 2; |
+ } else if(mnemonic <= MNEMONIC_MULS) { |
+ i = get_register(pi, operand1); |
+ if(i < 16) |
+ print_msg(pi, MSGTYPE_ERROR, "%s can only use a high register (r16 - r31)", instruction_list[mnemonic].mnemonic); |
+ opcode = (i & 0x0f) << 4; |
+ i = get_register(pi, operand2); |
+ if(i < 16) |
+ print_msg(pi, MSGTYPE_ERROR, "%s can only use a high register (r16 - r31)", instruction_list[mnemonic].mnemonic); |
+ opcode |= (i & 0x0f); |
+ } else if(mnemonic <= MNEMONIC_FMULSU) { |
+ i = get_register(pi, operand1); |
+ if((i < 16) || (i >= 24)) |
+ print_msg(pi, MSGTYPE_ERROR, "%s can only use registers (r16 - r23)", instruction_list[mnemonic].mnemonic); |
+ opcode = (i & 0x07) << 4; |
+ i = get_register(pi, operand2); |
+ if((i < 16) || (i >= 24)) |
+ print_msg(pi, MSGTYPE_ERROR, "%s can only use registers (r16 - r23)", instruction_list[mnemonic].mnemonic); |
+ opcode |= (i & 0x07); |
+ } else if(mnemonic <= MNEMONIC_SBIW) { |
+ i = get_register(pi, operand1); |
+ if(!((i == 24) || (i == 26) || (i == 28) || (i == 30))) |
+ print_msg(pi, MSGTYPE_ERROR, "%s can only use registers R24, R26, R28 or R30", instruction_list[mnemonic].mnemonic); |
+ opcode = ((i - 24) / 2) << 4; |
+ if(!get_expr(pi, operand2, &i)) |
+ return(False); |
+ if((i < 0) || (i > 63)) |
+ print_msg(pi, MSGTYPE_ERROR, "Constant out of range (0 <= k <= 63)"); |
+ opcode |= ((i & 0x30) << 2) | (i & 0x0f); |
+ } else if(mnemonic <= MNEMONIC_CBR) { |
+ i = get_register(pi, operand1); |
+ if(i < 16) |
+ print_msg(pi, MSGTYPE_ERROR, "%s can only use a high register (r16 - r31)", instruction_list[mnemonic].mnemonic); |
+ opcode = (i & 0x0f) << 4; |
+ if(!get_expr(pi, operand2, &i)) |
+ return(False); |
+ if((i < -128) || (i > 255)) |
+ print_msg(pi, MSGTYPE_WARNING, "Constant out of range (-128 <= k <= 255). Will be masked"); |
+ if(mnemonic == MNEMONIC_CBR) |
+ i = ~i; |
+ opcode |= ((i & 0xf0) << 4) | (i & 0x0f); |
+ } else if(mnemonic <= MNEMONIC_BLD) { |
+ i = get_register(pi, operand1); |
+ opcode = i << 4; |
+ if(!get_bitnum(pi, operand2, &i)) |
+ return(False); |
+ opcode |= i; |
+ } else if(mnemonic == MNEMONIC_IN) { |
+ i = get_register(pi, operand1); |
+ opcode = i << 4; |
+ if(!get_expr(pi, operand2, &i)) |
+ return(False); |
+ if((i < 0) || (i > 63)) |
+ print_msg(pi, MSGTYPE_ERROR, "I/O out of range (0 <= P <= 63)"); |
+ opcode |= ((i & 0x30) << 5) | (i & 0x0f); |
+ } else if(mnemonic == MNEMONIC_OUT) { |
+ if(!get_expr(pi, operand1, &i)) |
+ return(False); |
+ if((i < 0) || (i > 63)) |
+ print_msg(pi, MSGTYPE_ERROR, "I/O out of range (0 <= P <= 63)"); |
+ opcode = ((i & 0x30) << 5) | (i & 0x0f); |
+ i = get_register(pi, operand2); |
+ opcode |= i << 4; |
+ } else if(mnemonic <= MNEMONIC_CBI) { |
+ if(!get_expr(pi, operand1, &i)) |
+ return(False); |
+ if((i < 0) || (i > 31)) |
+ print_msg(pi, MSGTYPE_ERROR, "I/O out of range (0 <= P <= 31)"); |
+ opcode = i << 3; |
+ if(!get_bitnum(pi, operand2, &i)) |
+ return(False); |
+ opcode |= i; |
+ } else if(mnemonic == MNEMONIC_LDS) { |
+ i = get_register(pi, operand1); |
+ opcode = i << 4; |
+ if(!get_expr(pi, operand2, &i)) |
+ return(False); |
+ if((i < 0) || (i > 65535)) |
+ print_msg(pi, MSGTYPE_ERROR, "SRAM out of range (0 <= k <= 65535)"); |
+ opcode2 = i; |
+ instruction_long = True; |
+ } else if(mnemonic == MNEMONIC_STS) { |
+ if(!get_expr(pi, operand1, &i)) |
+ return(False); |
+ if((i < 0) || (i > 65535)) |
+ print_msg(pi, MSGTYPE_ERROR, "SRAM out of range (0 <= k <= 65535)"); |
+ opcode2 = i; |
+ i = get_register(pi, operand2); |
+ opcode = i << 4; |
+ instruction_long = True; |
+ } else if(mnemonic == MNEMONIC_LD) { |
+ i = get_register(pi, operand1); |
+ opcode = i << 4; |
+ mnemonic = MNEMONIC_LD_X + get_indirect(pi, operand2); |
+ } else if(mnemonic == MNEMONIC_ST) { |
+ mnemonic = MNEMONIC_ST_X + get_indirect(pi, operand1); |
+ i = get_register(pi, operand2); |
+ opcode = i << 4; |
+ } else if(mnemonic == MNEMONIC_LDD) { |
+ i = get_register(pi, operand1); |
+ opcode = i << 4; |
+ if(tolower(operand2[0]) == 'z') |
+ mnemonic = MNEMONIC_LDD_Z; |
+ else if(tolower(operand2[0]) == 'y') |
+ mnemonic = MNEMONIC_LDD_Y; |
+ else |
+ print_msg(pi, MSGTYPE_ERROR, "Garbage in second operand (%s)", operand2); |
+ i = 1; |
+ while((operand2[i] != '\0') && (operand2[i] != '+')) i++; |
+ if(operand2[i] == '\0') { |
+ print_msg(pi, MSGTYPE_ERROR, "Garbage in second operand (%s)", operand2); |
+ return(False); |
+ } |
+ if(!get_expr(pi, &operand2[i + 1], &i)) |
+ return(False); |
+ if((i < 0) || (i > 63)) |
+ print_msg(pi, MSGTYPE_ERROR, "Displacement out of range (0 <= q <= 63)"); |
+ opcode |= ((i & 0x20) << 8) | ((i & 0x18) << 7) | (i & 0x07); |
+ } else if(mnemonic == MNEMONIC_STD) { |
+ if(tolower(operand1[0]) == 'z') |
+ mnemonic = MNEMONIC_STD_Z; |
+ else if(tolower(operand1[0]) == 'y') |
+ mnemonic = MNEMONIC_STD_Y; |
+ else |
+ print_msg(pi, MSGTYPE_ERROR, "Garbage in first operand (%s)", operand1); |
+ i = 1; |
+ while((operand1[i] != '\0') && (operand1[i] != '+')) i++; |
+ if(operand1[i] == '\0') { |
+ print_msg(pi, MSGTYPE_ERROR, "Garbage in first operand (%s)", operand1); |
+ return(False); |
+ } |
+ if(!get_expr(pi, &operand1[i + 1], &i)) |
+ return(False); |
+ if((i < 0) || (i > 63)) |
+ print_msg(pi, MSGTYPE_ERROR, "Displacement out of range (0 <= q <= 63)"); |
+ opcode = ((i & 0x20) << 8) | ((i & 0x18) << 7) | (i & 0x07); |
+ i = get_register(pi, operand2); |
+ opcode |= i << 4; |
+ } else |
+ print_msg(pi, MSGTYPE_ERROR, "Shit! Missing opcode check [%d]...", mnemonic); |
+ } |
+ if (pi->device->flag & instruction_list[mnemonic].flag) { |
+ strncpy(temp, instruction_list[mnemonic].mnemonic, MAX_MNEMONIC_LEN); |
+ print_msg(pi, MSGTYPE_ERROR, "%s instruction is not supported on %s", |
+ my_strupr(temp), pi->device->name); |
+ } |
+ opcode |= instruction_list[mnemonic].opcode; |
+ if(pi->list_on && pi->list_line) { |
+ if(instruction_long) |
+ fprintf(pi->list_file, "C:%06x %04x %04x %s\n", pi->cseg_addr, opcode, opcode2, pi->list_line); |
+ else |
+ fprintf(pi->list_file, "C:%06x %04x %s\n", pi->cseg_addr, opcode, pi->list_line); |
+ pi->list_line = NULL; |
+ } |
+ if(pi->hfi) { |
+ write_prog_word(pi, pi->cseg_addr, opcode); |
+ if(instruction_long) |
+ write_prog_word(pi, pi->cseg_addr + 1, opcode2); |
+ } |
+ if(instruction_long) |
+ pi->cseg_addr += 2; |
+ else |
+ pi->cseg_addr++; |
+ } else { // Pass 1 |
+ if((mnemonic == MNEMONIC_JMP) || (mnemonic == MNEMONIC_CALL) |
+ || (mnemonic == MNEMONIC_LDS) || (mnemonic == MNEMONIC_STS)) { |
+ pi->cseg_addr += 2; |
+ pi->cseg_count += 2; |
+ } else { |
+ pi->cseg_addr++; |
+ pi->cseg_count++; |
+ } |
+ } |
+ return(True); |
+} |
+ |
+ |
+int get_mnemonic_type(char *mnemonic) |
+{ |
+ int i; |
+ |
+ for(i = 0; i < MNEMONIC_COUNT; i++) { |
+ if(!strcmp(mnemonic, instruction_list[i].mnemonic)) { |
+ return(i); |
+ } |
+ } |
+ return(-1); |
+} |
+ |
+ |
+int get_register(struct prog_info *pi, char *data) |
+{ |
+ char *second_reg; |
+ int reg = 0; |
+ struct def *def; |
+ |
+ // Check for any occurence of r1:r0 pairs, and if so skip to second register |
+ second_reg = strchr(data, ':'); |
+ if(second_reg != NULL) |
+ data = second_reg + 1; |
+ |
+ for(def = pi->first_def; def; def = def->next) |
+ if(!nocase_strcmp(def->name, data)) |
+ { |
+ reg = def->reg; |
+ return(reg); |
+ } |
+ if((tolower(data[0]) == 'r') && isdigit(data[1])) { |
+ reg = atoi(&data[1]); |
+ if(reg > 31) |
+ print_msg(pi, MSGTYPE_ERROR, "R%d is not a valid register", reg); |
+ } |
+ else |
+ print_msg(pi, MSGTYPE_ERROR, "No register associated with %s", data); |
+ return(reg); |
+} |
+ |
+ |
+int get_bitnum(struct prog_info *pi, char *data, int *ret) |
+{ |
+ if(!get_expr(pi, data, ret)) |
+ return(False); |
+ if((*ret < 0) || (*ret > 7)) { |
+ print_msg(pi, MSGTYPE_ERROR, "Operand out of range (0 <= s <= 7)"); |
+ return(False); |
+ } |
+ return(True); |
+} |
+ |
+ |
+int get_indirect(struct prog_info *pi, char *operand) |
+{ |
+ int i = 1; |
+ |
+ switch(tolower(operand[0])) { |
+ case '-': |
+ while(IS_HOR_SPACE(operand[i])) i++; |
+ if(operand[i + 1] != '\0') |
+ print_msg(pi, MSGTYPE_ERROR, "Garbage in operand (%s)", operand); |
+ switch(tolower(operand[i])) { |
+ case 'x': |
+ if (pi->device->flag & DF_NO_XREG) |
+ print_msg(pi, MSGTYPE_ERROR, "X register is not supported on %s", pi->device->name); |
+ return(2); |
+ case 'y': |
+ if (pi->device->flag & DF_NO_YREG) |
+ print_msg(pi, MSGTYPE_ERROR, "Y register is not supported on %s", pi->device->name); |
+ return(5); |
+ case 'z': |
+ return(8); |
+ default: |
+ print_msg(pi, MSGTYPE_ERROR, "Garbage in operand (%s)", operand); |
+ return(0); |
+ } |
+ case 'x': |
+ if (pi->device->flag & DF_NO_XREG) |
+ print_msg(pi, MSGTYPE_ERROR, "X register is not supported on %s", pi->device->name); |
+ while(IS_HOR_SPACE(operand[i])) i++; |
+ if(operand[i] == '+') { |
+ if(operand[i + 1] != '\0') |
+ print_msg(pi, MSGTYPE_ERROR, "Garbage in operand (%s)", operand); |
+ return(1); |
+ } |
+ else if(operand[i] == '\0') |
+ return(0); |
+ else |
+ print_msg(pi, MSGTYPE_ERROR, "Garbage after operand (%s)", operand); |
+ return(0); |
+ case 'y': |
+ if (pi->device->flag & DF_NO_YREG) |
+ print_msg(pi, MSGTYPE_ERROR, "Y register is not supported on %s", pi->device->name); |
+ while(IS_HOR_SPACE(operand[i])) i++; |
+ if(operand[i] == '+') { |
+ if(operand[i + 1] != '\0') |
+ print_msg(pi, MSGTYPE_ERROR, "Garbage in operand (%s)", operand); |
+ return(4); |
+ } |
+ else if(operand[i] == '\0') |
+ return(3); |
+ else |
+ print_msg(pi, MSGTYPE_ERROR, "Garbage after operand (%s)", operand); |
+ return(0); |
+ case 'z': |
+ while(IS_HOR_SPACE(operand[i])) i++; |
+ if(operand[i] == '+') { |
+ if(operand[i + 1] != '\0') |
+ print_msg(pi, MSGTYPE_ERROR, "Garbage in operand (%s)", operand); |
+ return(7); |
+ } |
+ else if(operand[i] == '\0') |
+ return(6); |
+ else |
+ print_msg(pi, MSGTYPE_ERROR, "Garbage after operand (%s)", operand); |
+ return(0); |
+ default: |
+ print_msg(pi, MSGTYPE_ERROR, "Garbage in operand (%s)", operand); |
+ } |
+ return(0); |
+} |
+ |
+/* Return 1 if instruction name is supported by the current device, |
+ 0 if unsupported, -1 if it is invalid */ |
+int is_supported(struct prog_info *pi, char *name) { |
+ char temp[MAX_MNEMONIC_LEN+1]; |
+ int mnemonic; |
+ |
+ strncpy(temp,name,MAX_MNEMONIC_LEN); |
+ mnemonic = get_mnemonic_type(my_strlwr(temp)); |
+ if (mnemonic == -1) return -1; |
+ if (pi->device->flag & instruction_list[mnemonic].flag) return 0; |
+ return 1; |
+} |
+ |
+int count_supported_instructions(int flags) |
+{ |
+ int i = 0, count = 0; |
+ while(i < MNEMONIC_END) { |
+ if((i < MNEMONIC_LD) || (i > MNEMONIC_COUNT)) |
+ if(!(flags & instruction_list[i].flag)) |
+ count++; |
+ i++; |
+ } |
+ return(count); |
+} |
+ |
+/* end of mnemonic.c */ |
+ |
/contrib/toolchain/avra/src/parser.c |
---|
0,0 → 1,412 |
/*********************************************************************** |
* |
* avra - Assembler for the Atmel AVR microcontroller series |
* |
* Copyright (C) 1998-2004 Jon Anders Haugum, Tobias Weber |
* |
* This program is free software; you can redistribute it and/or modify |
* it under the terms of the GNU General Public License as published by |
* the Free Software Foundation; either version 2 of the License, or |
* (at your option) any later version. |
* |
* This program is distributed in the hope that it will be useful, |
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
* GNU General Public License for more details. |
* |
* You should have received a copy of the GNU General Public License |
* along with this program; see the file COPYING. If not, write to |
* the Free Software Foundation, Inc., 59 Temple Place - Suite 330, |
* Boston, MA 02111-1307, USA. |
* |
* |
* Authors of avra can be reached at: |
* email: jonah@omegav.ntnu.no, tobiw@suprafluid.com |
* www: http://sourceforge.net/projects/avra |
* |
* |
* SourceForge.net: Detail:713798 Strings are not always correctly handled |
* Change made by JEG 5-01-03 |
* |
* global keyword is now .global to match common sytnax. TW 10-11-05 |
*/ |
#include <stdio.h> |
#include <stdlib.h> |
#include <string.h> |
#include <ctype.h> |
#include <time.h> |
#include "misc.h" |
#include "avra.h" |
#include "args.h" |
/* Special fgets. Like fgets, but with better check for CR, LF and FF and without the ending \n char */ |
/* size must be >=2. No checks for s=NULL, size<2 or stream=NULL. B.A. */ |
char *fgets_new(struct prog_info *pi, char *s, int size, FILE *stream) |
{ |
int c; |
char *ptr=s; |
do { |
if((c=fgetc(stream))==EOF || IS_ENDLINE(c)) // Terminate at chr$ 10,12,13,0 and EOF |
break; |
/* |
** concatenate lines terminated with \ only... |
*/ |
if (c == '\\') |
{ |
/* only newline and cr may follow... */ |
if((c=fgetc(stream))==EOF) |
break; |
if(!IS_ENDLINE(c)) // Terminate at chr$ 10,12,13,0 and EOF |
{ |
*ptr++ = '\\'; // no concatenation, insert it |
} |
else |
{ |
// mit be additional LF (DOS) |
c=fgetc(stream); |
if (IS_ENDLINE(c)) |
c=fgetc(stream); |
if (c == EOF) |
break; |
} |
} |
*ptr++=c; |
} while(--size); |
if((c==EOF) && (ptr==s)) // EOF and no chars read -> that's all folks |
return NULL; |
if(!size) { |
print_msg(pi, MSGTYPE_ERROR, "Line to long"); |
return NULL; |
} |
*ptr=0; |
if(c==12) // Check for Formfeed (Bug [1462886]) |
print_msg(pi, MSGTYPE_WARNING, "Found Formfeed char. Please remove it."); |
if(c==13) { // Check for CR LF sequence (DOS/ Windows line termination) |
if((c=fgetc(stream)) != 10) { |
ungetc(c,stream); |
print_msg(pi, MSGTYPE_WARNING, "Found CR (0x0d) without LF (0x0a). Please add a LF."); |
} |
} |
return s; |
} |
/* |
* Parses given assembler file |
*/ |
int parse_file(struct prog_info *pi, char *filename) |
{ |
#if debug == 1 |
printf("parse_file\n"); |
#endif |
int ok; |
int loopok; |
struct file_info *fi; |
struct include_file *include_file; |
ok = True; |
if((fi=malloc(sizeof(struct file_info)))==NULL) { |
print_msg(pi, MSGTYPE_OUT_OF_MEM,NULL); |
return(False); |
} |
pi->fi = fi; |
if(pi->pass == PASS_1) { |
if((include_file = malloc(sizeof(struct include_file)))==NULL) { |
print_msg(pi, MSGTYPE_OUT_OF_MEM, NULL); |
free(fi); |
return(False); |
} |
include_file->next = NULL; |
if(pi->last_include_file) { |
pi->last_include_file->next = include_file; |
include_file->num = pi->last_include_file->num + 1; |
} else { |
pi->first_include_file = include_file; |
include_file->num = 0; |
} |
pi->last_include_file = include_file; |
if((include_file->name = malloc(strlen(filename) + 1))==NULL) { |
print_msg(pi, MSGTYPE_OUT_OF_MEM, NULL); |
free(fi); |
return(False); |
} |
strcpy(include_file->name, filename); |
} else { // PASS 2 |
for(include_file = pi->first_include_file; include_file; include_file = include_file->next) { |
if(!strcmp(include_file->name, filename)) |
break; |
} |
} |
if(!include_file) { |
print_msg(pi, MSGTYPE_ERROR, "Internal assembler error"); |
free(fi); |
return(False); |
} |
fi->include_file = include_file; |
fi->line_number = 0; |
fi->exit_file = False; |
#if debug == 1 |
printf("Opening %s\n",filename); |
#endif |
if((fi->fp = fopen(filename, "r"))==NULL) { |
perror(filename); |
free(fi); |
return(False); |
} |
loopok = True; |
while(loopok && !fi->exit_file) { |
if(fgets_new(pi,fi->buff, LINEBUFFER_LENGTH, fi->fp)) { |
fi->line_number++; |
pi->list_line = fi->buff; |
ok = parse_line(pi, fi->buff); |
#if debug == 1 |
printf("parse_line was %i\n", ok); |
#endif |
if(ok) { |
if((pi->pass == PASS_2) && pi->list_line && pi->list_on) |
fprintf(pi->list_file, " %s\n", pi->list_line); |
if(pi->error_count >= pi->max_errors) { |
print_msg(pi, MSGTYPE_MESSAGE, "Maximum error count reached. Exiting..."); |
loopok = False; |
} |
} else { |
loopok = False; |
} |
} else { |
loopok = False; |
if(!feof(fi->fp)) { |
ok = False; |
perror(filename); |
} |
} |
} |
fclose(fi->fp); |
free(fi); |
return(ok); |
} |
/**************************************************************************** |
* |
* function parse_line |
* |
* Parses one line |
* |
****************************************************************************/ |
int parse_line(struct prog_info *pi, char *line) |
{ |
char *ptr=NULL; |
int k; |
int flag=0, i; |
int global_label = False; |
char temp[LINEBUFFER_LENGTH]; |
struct label *label = NULL; |
struct macro_call *macro_call; |
while(IS_HOR_SPACE(*line)) line++; /* At first remove leading spaces / tabs */ |
if(IS_END_OR_COMMENT(*line)) /* Skip comment line or empty line */ |
return(True); |
/* Filter out .stab debugging information */ |
/* .stabs sometimes contains colon : symbol - might be interpreted as label */ |
if(*line == '.') { /* minimal slowdown of existing code */ |
if(strncmp(temp,".stabs ",7) == 0 ) { /* compiler output is always lower case */ |
strcpy(temp,line); /* TODO : Do we need this temp variable ? Please check */ |
return parse_stabs( pi, temp ); |
} |
if(strncmp(temp,".stabn ",7) == 0 ) { |
strcpy(temp,line); |
return parse_stabn( pi, temp ); |
} |
} |
/* Meta information translation */ |
ptr=line; |
k=0; |
while((ptr=strchr(ptr, '%')) != NULL) { |
if(!strncmp(ptr, "%MINUTE%", 8) ) { /* Replacement always shorter than tag -> no length check */ |
k=strftime(ptr,3,"%M", localtime(&pi->time)); |
strcpy(ptr+k,ptr+8); |
ptr+=k; |
continue; |
} |
if(!strncmp(ptr, "%HOUR%", 6) ) { |
k=strftime(ptr,3,"%H", localtime(&pi->time)); |
strcpy(ptr+k,ptr+6); |
ptr+=k; |
continue; |
} |
if(!strncmp(ptr, "%DAY%", 5) ) { |
k=strftime(ptr,3,"%d", localtime(&pi->time)); |
strcpy(ptr+k,ptr+5); |
ptr+=k; |
continue; |
} |
if(!strncmp(ptr, "%MONTH%", 7) ) { |
k=strftime(ptr,3,"%m", localtime(&pi->time)); |
strcpy(ptr+k,ptr+7); |
ptr+=k; |
continue; |
} |
if(!strncmp(ptr, "%YEAR%", 6) ) { |
k=strftime(ptr,5,"%Y", localtime(&pi->time)); |
strcpy(ptr+k,ptr+6); |
ptr+=k; |
continue; |
} |
ptr++; |
} |
// if(pi->pass == PASS_2) // TODO : Test |
// strcpy(pi->list_line, line); |
strcpy(pi->fi->scratch,line); |
for(i = 0; IS_LABEL(pi->fi->scratch[i]) || (pi->fi->scratch[i] == ':'); i++) |
if(pi->fi->scratch[i] == ':') { /* it is a label */ |
pi->fi->scratch[i] = '\0'; |
if(pi->pass == PASS_1) { |
for(macro_call = pi->macro_call; macro_call; macro_call = macro_call->prev_on_stack) { |
for(label = pi->macro_call->first_label; label; label = label->next) { |
if(!nocase_strcmp(label->name, &pi->fi->scratch[0])) { |
print_msg(pi, MSGTYPE_ERROR, "Can't redefine local label %s", &pi->fi->scratch[0]); |
break; |
} |
} |
} |
if(test_label(pi,&pi->fi->scratch[0],"Can't redefine label %s")!=NULL) |
break; |
if(test_variable(pi,&pi->fi->scratch[0],"%s have already been defined as a .SET variable")!=NULL) |
break; |
if(test_constant(pi,&pi->fi->scratch[0],"%s has already been defined as a .EQU constant")!=NULL) |
break; |
label = malloc(sizeof(struct label)); |
if(!label) { |
print_msg(pi, MSGTYPE_OUT_OF_MEM, NULL); |
return(False); |
} |
label->next = NULL; |
label->name = malloc(strlen(&pi->fi->scratch[0]) + 1); |
if(!label->name) { |
print_msg(pi, MSGTYPE_OUT_OF_MEM, NULL); |
return(False); |
} |
strcpy(label->name, &pi->fi->scratch[0]); |
switch(pi->segment) { |
case SEGMENT_CODE: |
label->value = pi->cseg_addr; |
break; |
case SEGMENT_DATA: |
label->value = pi->dseg_addr; |
break; |
case SEGMENT_EEPROM: |
label->value = pi->eseg_addr; |
break; |
} |
if(pi->macro_call && !global_label) { |
if(pi->macro_call->last_label) |
pi->macro_call->last_label->next = label; |
else |
pi->macro_call->first_label = label; |
pi->macro_call->last_label = label; |
} else { |
if(pi->last_label) |
pi->last_label->next = label; |
else |
pi->first_label = label; |
pi->last_label = label; |
} |
} |
i++; |
while(IS_HOR_SPACE(pi->fi->scratch[i]) && !IS_END_OR_COMMENT(pi->fi->scratch[i])) i++; |
if(IS_END_OR_COMMENT(pi->fi->scratch[i])) { |
if((pi->pass == PASS_2) && pi->list_on) { // Diff tilpassing |
fprintf(pi->list_file, " %s\n", pi->list_line); |
pi->list_line = NULL; |
} |
return(True); |
} |
strcpy(pi->fi->scratch, &pi->fi->scratch[i]); |
break; |
} |
#if 0 |
if(pi->fi->scratch[0] == '.') { |
#else |
if((pi->fi->scratch[0] == '.') || (pi->fi->scratch[0] == '#')) { |
#endif |
pi->fi->label = label; |
flag = parse_directive(pi); |
if((pi->pass == PASS_2) && pi->list_on && pi->list_line) { // Diff tilpassing |
fprintf(pi->list_file, " %s\n", pi->list_line); |
pi->list_line = NULL; |
} |
return(flag); |
} else { |
return parse_mnemonic(pi); |
} |
} |
/* |
* Get the next token, and terminate the last one. |
* Termination identifier is specified. |
*/ |
char *get_next_token(char *data, int term) |
{ |
int i = 0, j, anti_comma = False; |
switch(term) { |
case TERM_END: |
// while(!IS_END_OR_COMMENT(data[i])) i++; Problems with 2. operand == ';' |
while( ((data[i] != ',') || anti_comma) && !(((data[i] == ';') && !anti_comma) || IS_ENDLINE(data[i])) ) { |
if((data[i] == '\'') || (data[i] == '"')) |
anti_comma = anti_comma ? False : True; |
i++; |
} |
break; |
case TERM_SPACE: |
while(!IS_HOR_SPACE(data[i]) && !IS_END_OR_COMMENT(data[i])) i++; |
break; |
case TERM_DASH: |
while((data[i] != '-') && !IS_END_OR_COMMENT(data[i])) i++; |
break; |
case TERM_COLON: |
while((data[i] != ':') && !IS_ENDLINE(data[i])) i++; |
break; |
case TERM_DOUBLEQUOTE: |
while((data[i] != '"') && !IS_ENDLINE(data[i])) i++; |
break; |
case TERM_COMMA: |
while(((data[i] != ',') || anti_comma) && !(((data[i] == ';') && !anti_comma) || IS_ENDLINE(data[i])) ) { |
if((data[i] == '\'') || (data[i] == '"')) |
anti_comma = anti_comma ? False : True; |
i++; |
} |
break; |
case TERM_EQUAL: |
while((data[i] != '=') && !IS_END_OR_COMMENT(data[i])) i++; |
break; |
} |
if(IS_END_OR_COMMENT(data[i])) { |
data[i--] = '\0'; |
while(IS_HOR_SPACE(data[i])) data[i--] = '\0'; |
return(0); |
} |
j = i - 1; |
while(IS_HOR_SPACE(data[j])) data[j--] = '\0'; |
data[i++] = '\0'; |
while(IS_HOR_SPACE(data[i]) && !IS_END_OR_COMMENT(data[i])) i++; |
if(IS_END_OR_COMMENT(data[i])) |
return(0); |
return(&data[i]); |
} |
/* end of parser.c */ |
/contrib/toolchain/avra/src/stab.h |
---|
0,0 → 1,114 |
/* @(#)stab.h 1.11 92/05/11 SMI */ |
/* $Id: stab.h,v 1.2 2005/10/11 08:44:56 tobias-weber Exp $ */ |
/* |
* Copyright (c) 1990 by Sun Microsystems, Inc. |
*/ |
/* |
* This file gives definitions supplementing <a.out.h> |
* for permanent symbol table entries. |
* These must have one of the N_STAB bits on, |
* and are subject to relocation according to the masks in <a.out.h>. |
*/ |
#ifndef _STAB_H |
#define _STAB_H |
#if !defined(_a_out_h) && !defined(_A_OUT_H) |
/* this file contains fragments of a.out.h and stab.h relevant to |
* support of stabX processing within ELF files - see the |
* Format of a symbol table entry |
*/ |
struct nlist { |
union { |
char *n_name; /* for use when in-core */ |
long n_strx; /* index into file string table */ |
} n_un; |
unsigned char n_type; /* type flag (N_TEXT,..) */ |
char n_other; /* unused */ |
short n_desc; /* see <stab.h> */ |
unsigned long n_value; /* value of symbol (or sdb offset) */ |
}; |
/* |
* Simple values for n_type. |
*/ |
#define N_UNDF 0x0 /* undefined */ |
#define N_ABS 0x2 /* absolute */ |
#define N_TEXT 0x4 /* text */ |
#define N_DATA 0x6 /* data */ |
#define N_BSS 0x8 /* bss */ |
#define N_COMM 0x12 /* common (internal to ld) */ |
#define N_FN 0x1f /* file name symbol */ |
#define N_EXT 01 /* external bit, or'ed in */ |
#define N_TYPE 0x1e /* mask for all the type bits */ |
#endif |
/* |
* for symbolic debugger, sdb(1): |
*/ |
#define N_GSYM 0x20 /* global symbol: name,,0,type,0 */ |
#define N_FNAME 0x22 /* procedure name (f77 kludge): name,,0 */ |
#define N_FUN 0x24 /* procedure: name,,0,linenumber,address */ |
#define N_STSYM 0x26 /* static symbol: name,,0,type,address */ |
#define N_LCSYM 0x28 /* .lcomm symbol: name,,0,type,address */ |
#define N_MAIN 0x2a /* name of main routine : name,,0,0,0 */ |
#define N_ROSYM 0x2c /* ro_data objects */ |
#define N_OBJ 0x38 /* object file path or name */ |
#define N_OPT 0x3c /* compiler options */ |
#define N_RSYM 0x40 /* register sym: name,,0,type,register */ |
#define N_SLINE 0x44 /* src line: 0,,0,linenumber,address */ |
#define N_FLINE 0x4c /* function start.end */ |
#define N_SSYM 0x60 /* structure elt: name,,0,type,struct_offset */ |
#define N_ENDM 0x62 /* last stab emitted for module */ |
#define N_SO 0x64 /* source file name: name,,0,0,address */ |
#define N_LSYM 0x80 /* local sym: name,,0,type,offset */ |
#define N_BINCL 0x82 /* header file: name,,0,0,0 */ |
#define N_SOL 0x84 /* #included file name: name,,0,0,address */ |
#define N_PSYM 0xa0 /* parameter: name,,0,type,offset */ |
#define N_EINCL 0xa2 /* end of include file */ |
#define N_ENTRY 0xa4 /* alternate entry: name,linenumber,address */ |
#define N_LBRAC 0xc0 /* left bracket: 0,,0,nesting level,address */ |
#define N_EXCL 0xc2 /* excluded include file */ |
#define N_RBRAC 0xe0 /* right bracket: 0,,0,nesting level,address */ |
#define N_BCOMM 0xe2 /* begin common: name,, */ |
#define N_ECOMM 0xe4 /* end common: name,, */ |
#define N_ECOML 0xe8 /* end common (local name): ,,address */ |
#define N_LENG 0xfe /* second stab entry with length information */ |
/* |
* for the berkeley pascal compiler, pc(1): |
*/ |
#define N_PC 0x30 /* global pascal symbol: name,,0,subtype,line */ |
#define N_WITH 0xea /* pascal with statement: type,,0,0,offset */ |
/* |
* for code browser only |
*/ |
#define N_BROWS 0x48 /* path to associated .cb file */ |
/* |
* Optional langauge designations for N_SO |
*/ |
#define N_SO_AS 1 /* Assembler */ |
#define N_SO_C 2 /* C */ |
#define N_SO_ANSI_C 3 /* ANSI C */ |
#define N_SO_CC 4 /* C++ */ |
#define N_SO_FORTRAN 5 /* Fortran 77 */ |
#define N_SO_PASCAL 6 /* Pascal */ |
/* |
* Floating point type values |
*/ |
#define NF_NONE 0 /* Undefined type */ |
#define NF_SINGLE 1 /* IEEE 32 bit float */ |
#define NF_DOUBLE 2 /* IEEE 64 bit float */ |
#define NF_COMPLEX 3 /* Fortran complex */ |
#define NF_COMPLEX16 4 /* Fortran double complex */ |
#define NF_COMPLEX32 5 /* Fortran complex*16 */ |
#define NF_LDOUBLE 6 /* Long double */ |
#endif |
/contrib/toolchain/avra/src/stdextra.c |
---|
0,0 → 1,191 |
/*********************************************************************** |
* |
* avra - Assembler for the Atmel AVR microcontroller series |
* |
* Copyright (C) 1998-2003 Jon Anders Haugum, Tobias Weber |
* |
* This program is free software; you can redistribute it and/or modify |
* it under the terms of the GNU General Public License as published by |
* the Free Software Foundation; either version 2 of the License, or |
* (at your option) any later version. |
* |
* This program is distributed in the hope that it will be useful, |
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
* GNU General Public License for more details. |
* |
* You should have received a copy of the GNU General Public License |
* along with this program; see the file COPYING. If not, write to |
* the Free Software Foundation, Inc., 59 Temple Place - Suite 330, |
* Boston, MA 02111-1307, USA. |
* |
* |
* Authors of avra can be reached at: |
* email: jonah@omegav.ntnu.no, tobiw@suprafluid.com |
* www: http://sourceforge.net/projects/avra |
*/ |
/******************************************************************** |
* Extra standard functions |
*/ |
#include <stdio.h> |
#include <ctype.h> |
#include "misc.h" |
/******************************************************************** |
* Case insensetive strcmp() |
*/ |
int nocase_strcmp(char *s, char *t) |
{ |
int i; |
for(i = 0; tolower(s[i]) == tolower(t[i]); i++) |
if(s[i] == '\0') |
return(0); |
return(tolower(s[i]) - tolower(t[i])); |
} |
/******************************************************************** |
* Case insensetive strncmp() |
*/ |
int nocase_strncmp(char *s, char *t, int n) |
{ |
int i; |
for(i = 0; (tolower(s[i]) == tolower(t[i])); i++, n--) |
if((s[i] == '\0') || (n == 1)) |
return(0); |
return(tolower(s[i]) - tolower(t[i])); |
} |
/******************************************************************** |
* Case insensetive strstr() |
*/ |
char *nocase_strstr(char *s, char *t) |
{ |
int i = 0, j, found = False; |
while((s[i] != '\0') && !found) { |
j = 0; |
while(tolower(t[j]) == tolower(s[i + j])) { |
j++; |
if(t[j] == '\0') { |
found = True; |
break; |
} |
else if(s[i + j] == '\0') |
break; |
} |
i++; |
} |
i--; |
if(found) |
return(&s[i]); |
return(NULL); |
} |
/******************************************************************** |
* ascii to hex |
* ignores "0x" |
*/ |
int atox(char *s) |
{ |
int i = 0, ret = 0; |
while(s[i] != '\0') { |
ret <<= 4; |
if((s[i] <= 'F') && (s[i] >= 'A')) |
ret |= s[i] - 'A' + 10; |
else if((s[i] <= 'f') && (s[i] >= 'a')) |
ret |= s[i] - 'a' + 10; |
else if((s[i] <= '9') && (s[i] >= '0')) |
ret |= s[i] - '0'; |
i++; |
} |
return(ret); |
} |
/******************************************************************** |
* n ascii chars to int |
*/ |
int atoi_n(char *s, int n) |
{ |
int i = 0, ret = 0; |
while((s[i] != '\0') && n) { |
ret = 10 * ret + (s[i] - '0'); |
i++; |
n--; |
} |
return(ret); |
} |
/******************************************************************** |
* n ascii chars to hex |
* 0 < n <= 8 |
* ignores "0x" |
*/ |
int atox_n(char *s, int n) |
{ |
int i = 0, ret = 0; |
while((s[i] != '\0') && n) { |
ret <<= 4; |
if((s[i] <= 'F') && (s[i] >= 'A')) |
ret |= s[i] - 'A' + 10; |
else if((s[i] <= 'f') && (s[i] >= 'a')) |
ret |= s[i] - 'a' + 10; |
else if((s[i] <= '9') && (s[i] >= '0')) |
ret |= s[i] - '0'; |
i++; |
n--; |
} |
return(ret); |
} |
/* |
* My own strlwr function since this one only exists in win |
*/ |
char *my_strlwr(char *in) |
{ |
int i; |
for(i = 0; in[i] != '\0'; i++) |
in[i] = tolower(in[i]); |
return(in); |
} |
/* |
* My own strupr function since this one only exists in win |
*/ |
char *my_strupr(char *in) |
{ |
int i; |
for(i = 0; in[i] != '\0'; i++) |
in[i] = toupper(in[i]); |
return(in); |
} |
/* stdextra.c */ |