/programs/system/drivers/ati2d/syscall.h |
---|
File deleted |
/programs/system/drivers/ati2d/ati2d.h |
---|
File deleted |
/programs/system/drivers/ati2d/types.h |
---|
File deleted |
/programs/system/drivers/ati2d/accel_2d.h |
---|
44,8 → 44,9 |
unsigned height; |
u32_t format; |
u32_t flags; |
unsigned pitch; |
size_t pitch; |
void *mapped; |
u32_t handle; |
}pixmap_t; |
56,12 → 57,11 |
unsigned height; |
u32_t format; |
u32_t flags; |
unsigned pitch; |
size_t pitch; |
void *mapped; |
unsigned pitch_offset; |
void *local; |
addr_t local; |
}local_pixmap_t; |
#define PX_MEM_SYSTEM 0 |
70,7 → 70,6 |
#define PX_MEM_MASK 3 |
#define PX_LOCK 1 |
typedef struct |
142,6 → 141,9 |
}io_blit_t; |
static addr_t bind_pixmap(local_pixmap_t *pixmap); |
int CreatePixmap(pixmap_t *io); |
int DestroyPixmap(pixmap_t *io); |
/programs/system/drivers/ati2d/accel_2d.inc |
---|
572,9 → 572,10 |
static int blit_host(u32_t dstpitch, int dstx, int dsty, |
u32_t src, int srcx, int srcy, |
int w, int h, int srcpitch) |
int w, int h, int srcpitch, Bool trans, color_t key) |
{ |
u32_t ifl; |
u32_t dp_cntl; |
color_t *src_addr; |
ifl = safe_cli(); |
581,33 → 582,40 |
#if R300_PIO |
R5xxFIFOWait(5); |
OUTREG(R5XX_DP_GUI_MASTER_CNTL, |
RADEON_GMC_DST_PITCH_OFFSET_CNTL | |
// RADEON_GMC_DST_CLIPPING | |
dp_cntl = RADEON_GMC_DST_PITCH_OFFSET_CNTL | |
RADEON_GMC_BRUSH_NONE | |
RADEON_GMC_DST_32BPP | |
RADEON_GMC_SRC_DATATYPE_COLOR | |
RADEON_DP_SRC_SOURCE_HOST_DATA | |
// RADEON_GMC_BYTE_MSB_TO_LSB | |
R5XX_GMC_CLR_CMP_CNTL_DIS | |
R5XX_GMC_WR_MSK_DIS | |
R5XX_ROP3_S |
); |
R5XX_ROP3_S; |
if( trans == FALSE ) |
{ |
dp_cntl|= R5XX_GMC_CLR_CMP_CNTL_DIS; |
R5xxFIFOWait(5); |
} |
else |
R5xxFIFOWait(8); |
OUTREG(R5XX_DP_GUI_MASTER_CNTL, dp_cntl); |
OUTREG(R5XX_DP_CNTL, R5XX_DST_X_LEFT_TO_RIGHT | |
R5XX_DST_Y_TOP_TO_BOTTOM); |
OUTREG(R5XX_DST_PITCH_OFFSET, dstpitch); |
// OUTREG(RADEON_SC_TOP_LEFT, (y << 16) | ((x+skipleft) & 0xffff)); |
// OUTREG(RADEON_SC_BOTTOM_RIGHT, ((y+h) << 16) | ((x+w) & 0xffff)); |
if( trans ) |
{ |
OUTREG(R5XX_CLR_CMP_CLR_SRC, key); |
OUTREG(R5XX_CLR_CMP_MASK, R5XX_CLR_CMP_MSK); |
OUTREG(R5XX_CLR_CMP_CNTL, R5XX_SRC_CMP_EQ_COLOR | |
R5XX_CLR_CMP_SRC_SOURCE); |
}; |
OUTREG(RADEON_DST_Y_X, (dsty << 16) | (dstx & 0xffff)); |
OUTREG(RADEON_DST_HEIGHT_WIDTH, (h << 16) | w); |
src_addr = &((color_t*)src)[srcpitch*srcy/4+srcx]; |
while ( h-- ) |
664,18 → 672,11 |
local_pixmap_t *srcpixmap; |
local_pixmap_t *dstpixmap; |
//dbgprintf("Pixblit src: %x dst: %x\n",blit->srcpix, blit->dstpix); |
u32_t srcpitchoffset; |
dstpixmap = (blit->dstpix == (void*)-1) ? &scr_pixmap : blit->dstpix ; |
srcpixmap = (blit->srcpix == (void*)-1) ? &scr_pixmap : blit->srcpix ; |
//dbgprintf("srcpixmap: %x dstpixmap: %x\n",srcpixmap, dstpixmap); |
//dbgprintf("dst.width: %d dst.height: %d\n", dstpixmap->width,dstpixmap->height); |
//dbgprintf("src.width: %d src.height: %d\n", srcpixmap->width,srcpixmap->height); |
//dbgprintf("srcpitch: %x dstpitch: %x\n", |
// srcpixmap->pitch_offset,dstpixmap->pitch_offset); |
src_clip.xmin = 0; |
src_clip.ymin = 0; |
src_clip.xmax = srcpixmap->width-1; |
692,7 → 693,7 |
{ |
u32_t *ring, write; |
u32_t ifl; |
/* |
if( (srcpixmap->flags & PX_MEM_MASK)==PX_MEM_SYSTEM) |
return blit_host(dstpixmap->pitch_offset, |
blit->dst_x, blit->dst_y, |
699,8 → 700,15 |
srcpixmap->mapped, |
blit->src_x, blit->src_y, |
blit->w, blit->h, |
srcpixmap->pitch); |
srcpixmap->pitch, |
FALSE, 0 ); |
*/ |
if( (srcpixmap->flags & PX_MEM_MASK)==PX_MEM_SYSTEM) |
srcpitchoffset = bind_pixmap(srcpixmap); |
else |
srcpitchoffset = srcpixmap->pitch_offset; |
ifl = safe_cli(); |
#if R300_PIO |
722,7 → 730,7 |
OUTREG(R5XX_DP_CNTL, R5XX_DST_X_LEFT_TO_RIGHT | R5XX_DST_Y_TOP_TO_BOTTOM); |
OUTREG(R5XX_DST_PITCH_OFFSET, dstpixmap->pitch_offset); |
OUTREG(R5XX_SRC_PITCH_OFFSET, srcpixmap->pitch_offset); |
OUTREG(R5XX_SRC_PITCH_OFFSET, srcpitchoffset); |
OUTREG(R5XX_SRC_Y_X,(blit->src_y<<16)|blit->src_x); |
OUTREG(R5XX_DST_Y_X,(blit->dst_y<<16)|blit->dst_x); |
744,7 → 752,7 |
R5XX_ROP3_S |
); |
OUT_RING(srcpixmap->pitch_offset); |
OUT_RING(srcpitchoffset); |
OUT_RING(dstpixmap->pitch_offset); |
OUT_RING((blit->src_x<<16)|blit->src_y); |
754,11 → 762,15 |
#endif |
safe_sti(ifl); |
if( (srcpixmap->flags & PX_MEM_MASK)==PX_MEM_SYSTEM) |
R5xx2DIdleLocal(); |
}; |
return ERR_OK; |
}; |
int BlitTransparent(io_blit_t *blit) |
{ |
clip_t src_clip, dst_clip; |
766,6 → 778,8 |
local_pixmap_t *srcpixmap; |
local_pixmap_t *dstpixmap; |
u32_t srcpitchoffset; |
// dbgprintf("Transblit src: %x dst: %x\n",blit->srcpix, blit->dstpix); |
dstpixmap = (blit->dstpix == (void*)-1) ? &scr_pixmap : blit->dstpix ; |
792,9 → 806,14 |
&blit->w, &blit->h) ) |
{ |
u32_t *ring, write; |
u32_t ifl; |
if( (srcpixmap->flags & PX_MEM_MASK)==PX_MEM_SYSTEM) |
srcpitchoffset = bind_pixmap(srcpixmap); |
else |
srcpitchoffset = srcpixmap->pitch_offset; |
ifl = safe_cli(); |
#if R300_PIO |
819,7 → 838,7 |
OUTREG(R5XX_CLR_CMP_CNTL, R5XX_SRC_CMP_EQ_COLOR | R5XX_CLR_CMP_SRC_SOURCE); |
OUTREG(R5XX_DST_PITCH_OFFSET, dstpixmap->pitch_offset); |
OUTREG(R5XX_SRC_PITCH_OFFSET, srcpixmap->pitch_offset); |
OUTREG(R5XX_SRC_PITCH_OFFSET, srcpitchoffset); |
OUTREG(R5XX_SRC_Y_X,(blit->src_y<<16)|blit->src_x); |
OUTREG(R5XX_DST_Y_X,(blit->dst_y<<16)|blit->dst_x); |
841,7 → 860,7 |
R5XX_ROP3_S |
); |
OUT_RING(srcpixmap->pitch_offset); |
OUT_RING(srcpitchoffset); |
OUT_RING(dstpixmap->pitch_offset); |
OUT_RING(R5XX_CLR_CMP_SRC_SOURCE | R5XX_SRC_CMP_EQ_COLOR); |
857,78 → 876,13 |
#endif |
safe_sti(ifl); |
}; |
return ERR_OK; |
} |
if( (srcpixmap->flags & PX_MEM_MASK)==PX_MEM_SYSTEM) |
R5xx2DIdleLocal(); |
#if 0 |
int LockPixmap(userpixmap_t *io) |
{ |
pixmap_t *pixmap; |
size_t size; |
void *usermap; |
dbgprintf("Lock pixmap %x\n", io->pixmap); |
if(io->pixmap == (pixmap_t*)-1) |
return ERR_PARAM; |
else |
pixmap = io->pixmap; |
if( (pixmap->flags & 1) == PX_LOCK ) |
return ERR_PARAM; |
size = (pixmap->pitch*pixmap->width+4095) & ~ 4095; |
if (usermap = UserAlloc(size)) |
{ |
CommitPages(usermap, ((u32_t)pixmap->raw+rhd.PhisBase)|7|(1<<9), size); |
pixmap->flags |= PX_LOCK; |
pixmap->usermap = usermap; |
io->usermap = usermap; |
io->pitch = pixmap->pitch; |
dbgprintf("map at %x\n", io->usermap); |
}; |
return ERR_OK; |
} |
else |
return ERR_PARAM; |
}; |
int UnlockPixmap(userpixmap_t *io) |
{ |
pixmap_t *pixmap; |
size_t size; |
dbgprintf("Unlock pixmap %x\n", io->pixmap); |
if(io->pixmap == (pixmap_t*)-1) |
return ERR_PARAM; |
else |
pixmap = io->pixmap; |
if( (pixmap->flags & 1) != PX_LOCK ) |
return ERR_PARAM; |
/* Sanity checks */ |
if( (pixmap->usermap == 0)|| |
((u32_t)pixmap->usermap >= 0x80000000) || |
((u32_t)pixmap->usermap & 4095) |
) |
return ERR_PARAM; |
size = (pixmap->pitch*pixmap->width+4095) & ~ 4095; |
UnmapPages(pixmap->usermap, size); |
UserFree(pixmap->usermap); |
pixmap->usermap = NULL; |
pixmap->flags &= ~PX_LOCK; |
io->usermap = NULL; |
io->pitch = 0; |
return ERR_OK; |
}; |
#endif |
/programs/system/drivers/ati2d/ati2d.c |
---|
20,7 → 20,8 |
#include "radeon_reg.h" |
#include "ati2d.h" |
#include "atihw.h" |
#include "accel_2d.h" |
RHD_t rhd __attribute__ ((aligned (128))); /* reduce cache lock */ |
29,7 → 30,6 |
static local_pixmap_t scr_pixmap; |
int Init3DEngine(RHDPtr info); |
int __stdcall srv_2d(ioctl_t *io); |
43,7 → 43,7 |
if(action != 1) |
return 0; |
if(!dbg_open("/rd/1/drivers/ati2d.log")) |
if(!dbg_open("/bd0/2/ati2d.log")) |
{ |
printf("Can't open /rd/1/drivers/ati2d.log\nExit\n"); |
return 0; |
148,14 → 148,18 |
return BlitTransparent((io_blit_t*)inp); |
break; |
#if !R300_PIO |
case PX_BLIT_ALPHA: |
if(io->inp_size==9) |
return RadeonComposite((io_blit_t*)inp); |
break; |
#endif |
default: |
return ERR_PARAM; |
}; |
return ERR_PARAM; |
} |
165,12 → 169,18 |
#include "ati_mem.c" |
#include "init_cp.c" |
#include "r500.inc" |
#include "clip.inc" |
#include "pixmap.inc" |
#include "accel_2d.inc" |
#if !R300_PIO |
#include "init_3d.inc" |
#include "blend.inc" |
#endif |
/programs/system/drivers/ati2d/ati_mem.c |
---|
43,7 → 43,7 |
{ |
struct mem_block *next; |
struct mem_block *prev; |
u32_t start; |
addr_t start; |
size_t size; |
}; |
168,13 → 168,13 |
return init_heap(&rhdPtr->fb_heap, base, rhdPtr->FbFreeSize); |
}; |
void *rhd_mem_alloc(RHDPtr rhdPtr,int region, int size) |
addr_t rhd_mem_alloc(RHDPtr rhdPtr,int region, int size) |
{ |
struct mem_block *block, **heap; |
heap = get_heap(rhdPtr, region); |
if (!heap || !*heap) |
return NULL; |
return 0; |
/* Make things easier on ourselves: all allocations at least |
* 4k aligned. |
185,12 → 185,12 |
block = alloc_block(*heap, size); |
if (!block) |
return NULL; |
return 0; |
return (void*)(block->start & ~USED_BLOCK); |
return (block->start & ~USED_BLOCK); |
} |
int rhd_mem_free(RHDPtr rhdPtr, int region, void *offset) |
int rhd_mem_free(RHDPtr rhdPtr, int region, addr_t offset) |
{ |
struct mem_block *block, **heap; |
/programs/system/drivers/ati2d/atihw.h |
---|
0,0 → 1,515 |
typedef void *pointer; |
typedef unsigned int memType; |
typedef struct { float hi, lo; } range; |
typedef enum |
{ |
CHIP_FAMILY_UNKNOW, |
CHIP_FAMILY_LEGACY, |
CHIP_FAMILY_RADEON, |
CHIP_FAMILY_RV100, |
CHIP_FAMILY_RS100, /* U1 (IGP320M) or A3 (IGP320)*/ |
CHIP_FAMILY_RV200, |
CHIP_FAMILY_RS200, /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350), RS250 (IGP 7000) */ |
CHIP_FAMILY_R200, |
CHIP_FAMILY_RV250, |
CHIP_FAMILY_RS300, /* RS300/RS350 */ |
CHIP_FAMILY_RV280, |
CHIP_FAMILY_R300, |
CHIP_FAMILY_R350, |
CHIP_FAMILY_RV350, |
CHIP_FAMILY_RV380, /* RV370/RV380/M22/M24 */ |
CHIP_FAMILY_R420, /* R420/R423/M18 */ |
CHIP_FAMILY_RV410, /* RV410, M26 */ |
CHIP_FAMILY_RS400, /* xpress 200, 200m (RS400) Intel */ |
CHIP_FAMILY_RS480, /* xpress 200, 200m (RS410/480/482/485) AMD */ |
CHIP_FAMILY_RV515, /* rv515 */ |
CHIP_FAMILY_R520, /* r520 */ |
CHIP_FAMILY_RV530, /* rv530 */ |
CHIP_FAMILY_R580, /* r580 */ |
CHIP_FAMILY_RV560, /* rv560 */ |
CHIP_FAMILY_RV570, /* rv570 */ |
CHIP_FAMILY_RS600, |
CHIP_FAMILY_RS690, |
CHIP_FAMILY_RS740, |
CHIP_FAMILY_R600, /* r600 */ |
CHIP_FAMILY_R630, |
CHIP_FAMILY_RV610, |
CHIP_FAMILY_RV630, |
CHIP_FAMILY_RV670, |
CHIP_FAMILY_RV620, |
CHIP_FAMILY_RV635, |
CHIP_FAMILY_RS780, |
CHIP_FAMILY_RV770, |
CHIP_FAMILY_LAST |
} RADEONChipFamily; |
#define IS_RV100_VARIANT ((rhdPtr->ChipFamily == CHIP_FAMILY_RV100) || \ |
(rhdPtr->ChipFamily == CHIP_FAMILY_RV200) || \ |
(rhdPtr->ChipFamily == CHIP_FAMILY_RS100) || \ |
(rhdPtr->ChipFamily == CHIP_FAMILY_RS200) || \ |
(rhdPtr->ChipFamily == CHIP_FAMILY_RV250) || \ |
(rhdPtr->ChipFamily == CHIP_FAMILY_RV280) || \ |
(rhdPtr->ChipFamily == CHIP_FAMILY_RS300)) |
#define IS_R300_VARIANT ((info->ChipFamily == CHIP_FAMILY_R300) || \ |
(info->ChipFamily == CHIP_FAMILY_RV350) || \ |
(info->ChipFamily == CHIP_FAMILY_R350) || \ |
(info->ChipFamily == CHIP_FAMILY_RV380) || \ |
(info->ChipFamily == CHIP_FAMILY_R420) || \ |
(info->ChipFamily == CHIP_FAMILY_RV410) || \ |
(info->ChipFamily == CHIP_FAMILY_RS400) || \ |
(info->ChipFamily == CHIP_FAMILY_RS480)) |
#define IS_AVIVO_VARIANT ((info->ChipFamily >= CHIP_FAMILY_RV515)) |
#define IS_DCE3_VARIANT ((info->ChipFamily >= CHIP_FAMILY_RV620)) |
#define IS_R500_3D ((info->ChipFamily == CHIP_FAMILY_RV515) || \ |
(info->ChipFamily == CHIP_FAMILY_R520) || \ |
(info->ChipFamily == CHIP_FAMILY_RV530) || \ |
(info->ChipFamily == CHIP_FAMILY_R580) || \ |
(info->ChipFamily == CHIP_FAMILY_RV560) || \ |
(info->ChipFamily == CHIP_FAMILY_RV570)) |
#define IS_R300_3D ((info->ChipFamily == CHIP_FAMILY_R300) || \ |
(info->ChipFamily == CHIP_FAMILY_RV350) || \ |
(info->ChipFamily == CHIP_FAMILY_R350) || \ |
(info->ChipFamily == CHIP_FAMILY_RV380) || \ |
(info->ChipFamily == CHIP_FAMILY_R420) || \ |
(info->ChipFamily == CHIP_FAMILY_RV410) || \ |
(info->ChipFamily == CHIP_FAMILY_RS690) || \ |
(info->ChipFamily == CHIP_FAMILY_RS600) || \ |
(info->ChipFamily == CHIP_FAMILY_RS740) || \ |
(info->ChipFamily == CHIP_FAMILY_RS400) || \ |
(info->ChipFamily == CHIP_FAMILY_RS480)) |
typedef enum { |
CARD_PCI, |
CARD_AGP, |
CARD_PCIE |
} RADEONCardType; |
/* |
* Errata workarounds |
*/ |
typedef enum { |
CHIP_ERRATA_R300_CG = 0x00000001, |
CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, |
CHIP_ERRATA_PLL_DELAY = 0x00000004 |
} RADEONErrata; |
typedef struct |
{ |
u32_t pci_device_id; |
RADEONChipFamily chip_family; |
int mobility; |
int igp; |
int nocrtc2; |
int nointtvout; |
int singledac; |
} RADEONCardInfo; |
#define RHD_FB_BAR 0 |
#define RHD_MMIO_BAR 2 |
#define RHD_MEM_GART 1 |
#define RHD_MEM_FB 2 |
#define RADEON_DEFAULT_GART_SIZE 8 /* MB (must be 2^n and > 4MB) */ |
#define R300_DEFAULT_GART_SIZE 32 /* MB (for R300 and above) */ |
#define RADEON_DEFAULT_RING_SIZE 1 /* MB (must be page aligned) */ |
#define RADEON_DEFAULT_BUFFER_SIZE 2 /* MB (must be page aligned) */ |
#define RADEON_DEFAULT_GART_TEX_SIZE 1 /* MB (must be page aligned) */ |
#define RADEON_DEFAULT_CP_TIMEOUT 100000 /* usecs */ |
#define RADEON_DEFAULT_PCI_APER_SIZE 32 /* in MB */ |
#define RADEON_PCIGART_TABLE_SIZE (32*1024) |
typedef struct RHDRec |
{ |
addr_t MMIOBase; |
size_t MMIOMapSize; |
addr_t FbFreeStart; |
addr_t FbFreeSize; |
/* visible part of the framebuffer */ |
// unsigned int FbScanoutStart; |
// unsigned int FbScanoutSize; |
// u32_t LinearAddr; /* Frame buffer physical address */ |
addr_t fbLocation; /* Frame buffer physical address */ |
u32_t mc_fb_location; |
u32_t mc_agp_location; |
u32_t mc_agp_location_hi; |
size_t videoRam; |
u32_t MemCntl; |
u32_t BusCntl; |
unsigned long FbMapSize; /* Size of frame buffer, in bytes */ |
unsigned long FbSecureSize; /* Size of secured fb area at end of |
framebuffer */ |
RADEONChipFamily ChipFamily; |
RADEONErrata ChipErrata; |
char *chipset; |
Bool IsIGP; |
Bool IsMobility; |
Bool HasCRTC2; |
u32_t bus; |
u32_t devfn; |
PCITAG PciTag; |
u16_t PciDeviceID; |
u16_t subvendor_id; |
u16_t subdevice_id; |
RADEONCardType cardType; /* Current card is a PCI card */ |
u32_t memBase[6]; |
u32_t ioBase[6]; |
u32_t memtype[6]; |
u32_t memsize[6]; |
struct mem_block *fb_heap; |
struct mem_block *gart_heap; |
u32_t displayWidth; |
u32_t displayHeight; |
u32_t *gart_table; |
addr_t gart_table_dma; |
addr_t gart_vm_start; |
size_t gart_size; |
u32_t* ringBase; |
u32_t ring_rp; |
u32_t ring_wp; |
u32_t ringSize; |
u32_t ring_avail; |
u32_t bufSize; |
u32_t pciAperSize; |
u32_t CPusecTimeout; |
int __xmin; |
int __ymin; |
int __xmax; |
int __ymax; |
u32_t gui_control; |
u32_t dst_pitch_offset; |
u32_t surface_cntl; |
volatile u32_t host_rp __attribute__ ((aligned (128))); |
volatile u32_t scratch0 __attribute__ ((aligned (128))); |
volatile u32_t scratch1; |
volatile u32_t scratch2; |
volatile u32_t scratch3; |
volatile u32_t scratch4; |
volatile u32_t scratch5; |
volatile u32_t scratch6; |
volatile u32_t scratch7; |
int RamWidth __attribute__ ((aligned (128))); |
Bool IsDDR; |
int num_gb_pipes; |
int has_tcl; |
}RHD_t, *RHDPtr; |
extern RHD_t rhd; |
#define CP_PACKET0(reg, n) \ |
(RADEON_CP_PACKET0 | ((n - 1 ) << 16) | ((reg) >> 2)) |
#define CP_PACKET1(reg0, reg1) \ |
(RADEON_CP_PACKET1 | (((reg1) >> 2) << 11) | ((reg0) >> 2)) |
#define CP_PACKET2() \ |
(RADEON_CP_PACKET2) |
#define CP_PACKET3( pkt, n ) \ |
(RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) |
#define BEGIN_RING( req ) do { \ |
int avail = rhd.ring_rp-rhd.ring_wp; \ |
if (avail <=0 ) avail+= 0x4000; \ |
if( (req)+128 > avail) \ |
{ \ |
rhd.ring_rp = INREG(RADEON_CP_RB_RPTR); \ |
avail = rhd.ring_rp-rhd.ring_wp; \ |
if (avail <= 0) avail+= 0x4000; \ |
if( (req)+128 > avail){ \ |
safe_sti(ifl); \ |
return 0; \ |
}; \ |
} \ |
ring = &rhd.ringBase[rhd.ring_wp]; \ |
}while(0); |
#define ADVANCE_RING() |
#define OUT_RING( x ) *ring++ = (x) |
#define CP_REG(reg, val) \ |
do { \ |
ring[0] = CP_PACKET0((reg), 1); \ |
ring[1] = (val); \ |
ring+= 2; \ |
} while (0) |
#define DRM_MEMORYBARRIER() __asm__ volatile("lock; addl $0,0(%%esp)" : : : "memory"); |
#define COMMIT_RING() do { \ |
rhd.ring_wp = (ring - rhd.ringBase) & 0x3FFF; \ |
/* Flush writes to ring */ \ |
DRM_MEMORYBARRIER(); \ |
/*GET_RING_HEAD( dev_priv ); */ \ |
OUTREG( RADEON_CP_RB_WPTR, rhd.ring_wp); \ |
/* read from PCI bus to ensure correct posting */ \ |
/* INREG( RADEON_CP_RB_RPTR ); */ \ |
} while (0) |
#define BEGIN_ACCEL(n) BEGIN_RING(2*(n)) |
#define FINISH_ACCEL() COMMIT_RING() |
#define OUT_ACCEL_REG(reg, val) CP_REG((reg), (val)) |
typedef struct { |
int token; /* id of the token */ |
const char * name; /* token name */ |
} SymTabRec, *SymTabPtr; |
extern inline void |
OUTREG8(u16_t offset, u8_t value) |
{ |
*(volatile u8_t *)((u8_t *)(rhd.MMIOBase + offset)) = value; |
} |
extern inline u32_t INREG(u16_t offset) |
{ |
return *(volatile u32_t *)((u8_t*)(rhd.MMIOBase + offset)); |
} |
extern inline void OUTREG(u16_t offset, u32_t value) |
{ |
*(volatile u32_t *)((u8_t *)(rhd.MMIOBase + offset)) = value; |
} |
//#define OUTREG( offset, value) \ |
// *(volatile u32_t *)((u8_t *)(rhd.MMIOBase + (u32_t)(offset))) = (u32_t)value |
extern inline u32_t _RHDRegRead(RHDPtr rhdPtr, u16_t offset) |
{ |
return *(volatile u32_t *)((u8_t*)(rhdPtr->MMIOBase + offset)); |
} |
extern inline void |
MASKREG(u16_t offset, u32_t value, u32_t mask) |
{ |
u32_t tmp; |
tmp = INREG(offset); |
tmp &= ~mask; |
tmp |= (value & mask); |
OUTREG(offset, tmp); |
}; |
#define INPLL( addr) RADEONINPLL( addr) |
#define OUTPLL( addr, val) RADEONOUTPLL( addr, val) |
extern inline void |
_RHDRegWrite(RHDPtr rhdPtr, u16_t offset, u32_t value) |
{ |
*(volatile u32_t *)((u8_t *)(rhdPtr->MMIOBase + offset)) = value; |
} |
extern inline void |
_RHDRegMask(RHDPtr rhdPtr, u16_t offset, u32_t value, u32_t mask) |
{ |
u32_t tmp; |
tmp = _RHDRegRead(rhdPtr, offset); |
tmp &= ~mask; |
tmp |= (value & mask); |
_RHDRegWrite(rhdPtr, offset, tmp); |
}; |
#define RHDRegRead(ptr, offset) _RHDRegRead((ptr)->rhdPtr, (offset)) |
#define RHDRegWrite(ptr, offset, value) _RHDRegWrite((ptr)->rhdPtr, (offset), (value)) |
#define RHDRegMask(ptr, offset, value, mask) _RHDRegMask((ptr)->rhdPtr, (offset), (value), (mask)) |
#define RHDFUNC(ptr) |
#define DBG(x) x |
// #define DBG(x) |
#pragma pack (push,1) |
typedef struct s_cursor |
{ |
u32_t magic; // 'CURS' |
void (*destroy)(struct s_cursor*); // destructor |
u32_t fd; // next object in list |
u32_t bk; // prev object in list |
u32_t pid; // owner id |
void *base; // allocated memory |
u32_t hot_x; // hotspot coords |
u32_t hot_y; |
}cursor_t; |
#pragma pack (pop) |
#define LOAD_FROM_FILE 0 |
#define LOAD_FROM_MEM 1 |
#define LOAD_INDIRECT 2 |
cursor_t *create_cursor(u32_t pid, void *src, u32_t flags); |
void __stdcall copy_cursor(void *img, void *src); |
void destroy_cursor(cursor_t *cursor); |
void __destroy_cursor(cursor_t *cursor); // wrap |
void __stdcall r500_SelectCursor(cursor_t *cursor); |
void __stdcall r500_SetCursor(cursor_t *cursor, int x, int y); |
void __stdcall r500_CursorRestore(int x, int y); |
typedef struct { |
u32_t x ; |
u32_t y ; |
} xPointFixed; |
typedef u32_t xFixed_16_16; |
typedef xFixed_16_16 xFixed; |
#define XFIXED_BITS 16 |
#define xFixedToInt(f) (int) ((f) >> XFIXED_BITS) |
#define IntToxFixed(i) ((xFixed) (i) << XFIXED_BITS) |
#define xFixedToFloat(f) (((float) (f)) / 65536) |
#define PICT_FORMAT(bpp,type,a,r,g,b) (((bpp) << 24) | \ |
((type) << 16) | \ |
((a) << 12) | \ |
((r) << 8) | \ |
((g) << 4) | \ |
((b))) |
#define PICT_FORMAT_A(f) (((f) >> 12) & 0x0f) |
#define PICT_FORMAT_RGB(f) (((f) ) & 0xfff) |
#define PICT_TYPE_OTHER 0 |
#define PICT_TYPE_A 1 |
#define PICT_TYPE_ARGB 2 |
#define PICT_TYPE_ABGR 3 |
#define PICT_TYPE_COLOR 4 |
#define PICT_TYPE_GRAY 5 |
typedef enum _PictFormatShort { |
PICT_a8r8g8b8 = PICT_FORMAT(32,PICT_TYPE_ARGB,8,8,8,8), |
PICT_x8r8g8b8 = PICT_FORMAT(32,PICT_TYPE_ARGB,0,8,8,8), |
PICT_a8b8g8r8 = PICT_FORMAT(32,PICT_TYPE_ABGR,8,8,8,8), |
PICT_x8b8g8r8 = PICT_FORMAT(32,PICT_TYPE_ABGR,0,8,8,8), |
/* 24bpp formats */ |
PICT_r8g8b8 = PICT_FORMAT(24,PICT_TYPE_ARGB,0,8,8,8), |
PICT_b8g8r8 = PICT_FORMAT(24,PICT_TYPE_ABGR,0,8,8,8), |
/* 16bpp formats */ |
PICT_r5g6b5 = PICT_FORMAT(16,PICT_TYPE_ARGB,0,5,6,5), |
PICT_b5g6r5 = PICT_FORMAT(16,PICT_TYPE_ABGR,0,5,6,5), |
PICT_a1r5g5b5 = PICT_FORMAT(16,PICT_TYPE_ARGB,1,5,5,5), |
PICT_x1r5g5b5 = PICT_FORMAT(16,PICT_TYPE_ARGB,0,5,5,5), |
PICT_a1b5g5r5 = PICT_FORMAT(16,PICT_TYPE_ABGR,1,5,5,5), |
PICT_x1b5g5r5 = PICT_FORMAT(16,PICT_TYPE_ABGR,0,5,5,5), |
PICT_a4r4g4b4 = PICT_FORMAT(16,PICT_TYPE_ARGB,4,4,4,4), |
PICT_x4r4g4b4 = PICT_FORMAT(16,PICT_TYPE_ARGB,0,4,4,4), |
PICT_a4b4g4r4 = PICT_FORMAT(16,PICT_TYPE_ABGR,4,4,4,4), |
PICT_x4b4g4r4 = PICT_FORMAT(16,PICT_TYPE_ABGR,0,4,4,4), |
/* 8bpp formats */ |
PICT_a8 = PICT_FORMAT(8,PICT_TYPE_A,8,0,0,0), |
PICT_r3g3b2 = PICT_FORMAT(8,PICT_TYPE_ARGB,0,3,3,2), |
PICT_b2g3r3 = PICT_FORMAT(8,PICT_TYPE_ABGR,0,3,3,2), |
PICT_a2r2g2b2 = PICT_FORMAT(8,PICT_TYPE_ARGB,2,2,2,2), |
PICT_a2b2g2r2 = PICT_FORMAT(8,PICT_TYPE_ABGR,2,2,2,2), |
PICT_c8 = PICT_FORMAT(8,PICT_TYPE_COLOR,0,0,0,0), |
PICT_g8 = PICT_FORMAT(8,PICT_TYPE_GRAY,0,0,0,0), |
PICT_x4a4 = PICT_FORMAT(8,PICT_TYPE_A,4,0,0,0), |
PICT_x4c4 = PICT_FORMAT(8,PICT_TYPE_COLOR,0,0,0,0), |
PICT_x4g4 = PICT_FORMAT(8,PICT_TYPE_GRAY,0,0,0,0), |
/* 4bpp formats */ |
PICT_a4 = PICT_FORMAT(4,PICT_TYPE_A,4,0,0,0), |
PICT_r1g2b1 = PICT_FORMAT(4,PICT_TYPE_ARGB,0,1,2,1), |
PICT_b1g2r1 = PICT_FORMAT(4,PICT_TYPE_ABGR,0,1,2,1), |
PICT_a1r1g1b1 = PICT_FORMAT(4,PICT_TYPE_ARGB,1,1,1,1), |
PICT_a1b1g1r1 = PICT_FORMAT(4,PICT_TYPE_ABGR,1,1,1,1), |
PICT_c4 = PICT_FORMAT(4,PICT_TYPE_COLOR,0,0,0,0), |
PICT_g4 = PICT_FORMAT(4,PICT_TYPE_GRAY,0,0,0,0), |
/* 1bpp formats */ |
PICT_a1 = PICT_FORMAT(1,PICT_TYPE_A,1,0,0,0), |
PICT_g1 = PICT_FORMAT(1,PICT_TYPE_GRAY,0,0,0,0), |
} PictFormatShort; |
void dump_mem(); |
RHDPtr FindPciDevice(); |
Bool RHDPreInit(); |
void R5xx2DInit(); |
int Init3DEngine(RHDPtr info); |
void init_gart(RHDPtr info); |
int rhdInitHeap(RHDPtr rhdPtr); |
/programs/system/drivers/ati2d/init.c |
---|
3,7 → 3,7 |
static Bool rhdMapMMIO(RHDPtr rhdPtr) |
{ |
rhdPtr->MMIOMapSize = 1 << rhdPtr->memsize[RHD_MMIO_BAR]; |
rhdPtr->MMIOBase = MapIoMem((void*)rhdPtr->memBase[RHD_MMIO_BAR], |
rhdPtr->MMIOBase = MapIoMem(rhdPtr->memBase[RHD_MMIO_BAR], |
rhdPtr->MMIOMapSize,PG_SW+PG_NOCACHE); |
if( rhdPtr->MMIOBase==0) |
return 0; |
115,7 → 115,8 |
u32_t *fb_loc, u32_t *agp_loc, u32_t *agp_loc_hi) |
{ |
if (info->ChipFamily >= CHIP_FAMILY_RV770) { |
if (info->ChipFamily >= CHIP_FAMILY_RV770) |
{ |
if (mask & LOC_FB) |
*fb_loc = INREG(R700_MC_VM_FB_LOCATION); |
if (mask & LOC_AGP) { |
122,7 → 123,9 |
*agp_loc = INREG(R600_MC_VM_AGP_BOT); |
*agp_loc_hi = INREG(R600_MC_VM_AGP_TOP); |
} |
} else if (info->ChipFamily >= CHIP_FAMILY_R600) { |
} |
else if (info->ChipFamily >= CHIP_FAMILY_R600) |
{ |
if (mask & LOC_FB) |
*fb_loc = INREG(R600_MC_VM_FB_LOCATION); |
if (mask & LOC_AGP) { |
129,7 → 132,9 |
*agp_loc = INREG(R600_MC_VM_AGP_BOT); |
*agp_loc_hi = INREG(R600_MC_VM_AGP_TOP); |
} |
} else if (info->ChipFamily == CHIP_FAMILY_RV515) { |
} |
else if (info->ChipFamily == CHIP_FAMILY_RV515) |
{ |
if (mask & LOC_FB) |
*fb_loc = INMC(info, RV515_MC_FB_LOCATION); |
if (mask & LOC_AGP) { |
136,7 → 141,9 |
*agp_loc = INMC(info, RV515_MC_AGP_LOCATION); |
*agp_loc_hi = 0; |
} |
} else if (info->ChipFamily == CHIP_FAMILY_RS600) { |
} |
else if (info->ChipFamily == CHIP_FAMILY_RS600) |
{ |
if (mask & LOC_FB) |
*fb_loc = INMC(info, RS600_MC_FB_LOCATION); |
if (mask & LOC_AGP) { |
143,8 → 150,10 |
*agp_loc = 0;//INMC(pScrn, RS600_MC_AGP_LOCATION); |
*agp_loc_hi = 0; |
} |
} else if ((info->ChipFamily == CHIP_FAMILY_RS690) || |
(info->ChipFamily == CHIP_FAMILY_RS740)) { |
} |
else if ((info->ChipFamily == CHIP_FAMILY_RS690) || |
(info->ChipFamily == CHIP_FAMILY_RS740)) |
{ |
if (mask & LOC_FB) |
*fb_loc = INMC(info, RS690_MC_FB_LOCATION); |
if (mask & LOC_AGP) { |
151,7 → 160,9 |
*agp_loc = INMC(info, RS690_MC_AGP_LOCATION); |
*agp_loc_hi = 0; |
} |
} else if (info->ChipFamily >= CHIP_FAMILY_R520) { |
} |
else if (info->ChipFamily >= CHIP_FAMILY_R520) |
{ |
if (mask & LOC_FB) |
*fb_loc = INMC(info, R520_MC_FB_LOCATION); |
if (mask & LOC_AGP) { |
158,7 → 169,9 |
*agp_loc = INMC(info, R520_MC_AGP_LOCATION); |
*agp_loc_hi = 0; |
} |
} else { |
} |
else |
{ |
if (mask & LOC_FB) |
*fb_loc = INREG(RADEON_MC_FB_LOCATION); |
if (mask & LOC_AGP) |
226,7 → 239,6 |
} |
} |
#if !R300_PIO |
static void RADEONUpdateMemMapRegisters(RHDPtr info) |
{ |
259,7 → 271,7 |
tmp = INREG(AVIVO_D2CRTC_CONTROL); |
usleep(10000); |
usleep(1000); |
timeout = 0; |
while (!(avivo_get_mc_idle(info))) |
{ |
272,7 → 284,7 |
* to maybe hit the disk and continue trying to setup despite |
* the MC being non-idle |
*/ |
usleep(2000000); |
usleep(20000); |
} |
usleep(10); |
} |
445,9 → 457,7 |
}; |
}; |
#endif |
static void RADEONInitMemoryMap(RHDPtr info) |
{ |
u32_t mem_size; |
536,17 → 546,17 |
* re-enabled later by the DRM |
*/ |
// if (IS_AVIVO_VARIANT) { |
// if (info->ChipFamily >= CHIP_FAMILY_R600) { |
// OUTREG(R600_HDP_NONSURFACE_BASE, (info->mc_fb_location << 16) & 0xff0000); |
// } |
// else { |
// OUTREG(AVIVO_HDP_FB_LOCATION, info->mc_fb_location); |
// } |
// info->mc_agp_location = 0x003f0000; |
// } |
// else |
// info->mc_agp_location = 0xffffffc0; |
if (IS_AVIVO_VARIANT) { |
if (info->ChipFamily >= CHIP_FAMILY_R600) { |
OUTREG(R600_HDP_NONSURFACE_BASE, (info->mc_fb_location << 16) & 0xff0000); |
} |
else { |
OUTREG(AVIVO_HDP_FB_LOCATION, info->mc_fb_location); |
} |
info->mc_agp_location = 0x003f0000; |
} |
else |
info->mc_agp_location = 0xffffffc0; |
dbgprintf("RADEONInitMemoryMap() : \n"); |
dbgprintf(" mem_size : 0x%08x\n", (u32_t)mem_size); |
554,11 → 564,9 |
dbgprintf(" MC_AGP_LOCATION : 0x%08x\n", (unsigned)info->mc_agp_location); |
dbgprintf(" FB_LOCATION : 0x%08x\n", (unsigned)info->fbLocation); |
#if !R300_PIO |
RADEONUpdateMemMapRegisters(info); |
#endif |
} |
788,11 → 796,11 |
info->videoRam &= ~1023; |
info->FbMapSize = info->videoRam * 1024; |
info->gartSize = RADEON_DEFAULT_GART_SIZE; |
// info->gartSize = RADEON_DEFAULT_GART_SIZE; |
info->ringSize = RADEON_DEFAULT_RING_SIZE; |
info->bufSize = RADEON_DEFAULT_BUFFER_SIZE; |
info->gartTexSize = info->gartSize - (info->ringSize + info->bufSize); |
// info->gartTexSize = info->gartSize - (info->ringSize + info->bufSize); |
info->pciAperSize = RADEON_DEFAULT_PCI_APER_SIZE; |
info->CPusecTimeout = RADEON_DEFAULT_CP_TIMEOUT; |
878,7 → 886,7 |
rhdPtr->has_tcl = TRUE; |
} |
rhdPtr->LinearAddr = rhdPtr->memBase[RHD_FB_BAR]; |
// rhdPtr->LinearAddr = rhdPtr->memBase[RHD_FB_BAR]; |
return TRUE; |
} |
979,15 → 987,10 |
} |
dbgprintf("VideoRAM: %d kByte\n",rhd.videoRam); |
// rhd.FbFreeStart = 0; |
init_gart(&rhd); |
rhd.FbFreeSize = rhd.videoRam << 10; |
// if( !rhdMapFB(&rhd)) |
// return FALSE; |
// rhd.FbScanoutStart = 0; |
// rhd.FbScanoutSize = 8*1024*1024; |
rhd.FbFreeStart = 10*1024*1024; |
rhd.FbFreeSize = rhd.FbMapSize - rhd.FbFreeStart - rhd.FbSecureSize; |
1115,4 → 1118,143 |
OUTREG(RADEON_RB3D_CNTL, 0); |
}; |
#define RADEON_AIC_PT_BASE 0x01d8 |
#define RADEON_AIC_LO_ADDR 0x01dc |
#define RADEON_AIC_HI_ADDR 0x01e0 |
#define RADEON_AIC_TLB_ADDR 0x01e4 |
#define RADEON_AIC_TLB_DATA 0x01e8 |
#define RADEON_PCIE_INDEX 0x0030 |
#define RADEON_PCIE_DATA 0x0034 |
#define RADEON_PCIE_TX_GART_CNTL 0x10 |
# define RADEON_PCIE_TX_GART_EN (1 << 0) |
# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1) |
# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1 << 1) |
# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3 << 1) |
# define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0 << 3) |
# define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1 << 3) |
# define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1 << 5) |
# define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1 << 8) |
#define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11 |
#define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12 |
#define RADEON_PCIE_TX_GART_BASE 0x13 |
#define RADEON_PCIE_TX_GART_START_LO 0x14 |
#define RADEON_PCIE_TX_GART_START_HI 0x15 |
#define RADEON_PCIE_TX_GART_END_LO 0x16 |
#define RADEON_PCIE_TX_GART_END_HI 0x17 |
#define RADEON_WRITE8(offset, val) \ |
*(volatile u8_t*)((addr_t)rhd.MMIOBase + (offset)) = val |
#define RADEON_WRITE_PCIE( addr, val ) \ |
do { \ |
RADEON_WRITE8( RADEON_PCIE_INDEX, \ |
((addr) & 0xff)); \ |
OUTREG( RADEON_PCIE_DATA, (val) ); \ |
} while (0) |
static u32_t RADEON_READ_PCIE(int addr) |
{ |
RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff); |
return INREG(RADEON_PCIE_DATA); |
} |
static void radeon_set_pciegart(RHDPtr info, int on) |
{ |
u32_t tmp = RADEON_READ_PCIE(RADEON_PCIE_TX_GART_CNTL); |
if (on) |
{ |
RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, |
info->gart_vm_start); |
RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE, |
info->gart_table_dma); |
RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO, |
info->gart_vm_start); |
RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO, |
info->gart_vm_start + info->gart_size - 1); |
// radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */ |
OUTREG(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */ |
RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, |
RADEON_PCIE_TX_GART_EN); |
} else { |
RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, |
tmp & ~RADEON_PCIE_TX_GART_EN); |
} |
} |
static void radeon_set_pcigart(RHDPtr info, int on) |
{ |
u32_t tmp; |
tmp = INREG(RADEON_AIC_CNTL); |
if( on ) |
{ |
OUTREG(RADEON_AIC_CNTL, tmp | RADEON_PCIGART_TRANSLATE_EN); |
/* set PCI GART page-table base address |
*/ |
OUTREG(RADEON_AIC_PT_BASE, info->gart_table_dma); |
/* set address range for PCI address translate |
*/ |
OUTREG(RADEON_AIC_LO_ADDR, info->gart_vm_start); |
OUTREG(RADEON_AIC_HI_ADDR, info->gart_vm_start |
+ info->gart_size - 1); |
/* Turn off AGP aperture -- is this required for PCI GART? |
*/ |
// radeon_write_agp_location(dev_priv, 0xffffffc0); |
OUTREG(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */ |
} |
else OUTREG(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN); |
} |
void init_gart(RHDPtr info) |
{ |
u32_t *pci_gart; |
count_t pages; |
info->gart_size = 16*1024*1024; |
info->gart_vm_start = info->fbLocation + (info->videoRam << 10); |
// info->gart_vm_start = info->fbLocation - info->gart_size; |
// info->gart_table = (u32_t*)KernelAlloc( RADEON_PCIGART_TABLE_SIZE ); |
// if ( ! info->gart_table) { |
// dbgprintf("cannot allocate PCI GART page!\n"); |
// return; |
// } |
// info->gart_table_dma = GetPgAddr(info->gart_table); |
info->gart_table_dma = info->gart_vm_start - RADEON_PCIGART_TABLE_SIZE; |
info->gart_table = (u32_t*)MapIoMem(info->gart_table_dma, |
RADEON_PCIGART_TABLE_SIZE, |
PG_SW | PG_NOCACHE); |
pci_gart = info->gart_table; |
memset(pci_gart, 0, RADEON_PCIGART_TABLE_SIZE); |
__asm__ __volatile( |
"wbinvd" |
:::"memory"); |
radeon_set_pciegart(info, 1); |
dbgprintf("gart size 0x%x\n", info->gart_size); |
dbgprintf("gart base 0x%x\n", info->gart_vm_start); |
dbgprintf("gart table 0x%x\n", info->gart_table); |
dbgprintf("gart table dma 0x%x\n", info->gart_table_dma); |
} |
/programs/system/drivers/ati2d/makefile |
---|
8,7 → 8,7 |
HFILES:= ../include/types.h \ |
../include/syscall.h \ |
ati2d.h \ |
atihw.h \ |
pci.h \ |
accel_2d.h \ |
r5xx_regs.h \ |
/programs/system/drivers/ati2d/pci.h |
---|
67,6 → 67,9 |
#define PCI_DFN_FROM_TAG(tag) (((tag) & 0x0000ff00u) >> 8) |
#define PCI_CMD_STAT_REG 0x04 |
typedef unsigned int PCITAG; |
extern inline PCITAG |
/programs/system/drivers/ati2d/pixmap.inc |
---|
6,7 → 6,9 |
unsigned pitch; |
size_t size; |
void *local; |
addr_t mem_local = 0; |
addr_t mem_dma = 0; |
void *mapped; |
if( (io->width == 0) || (io->width > 2048)|| |
(io->height == 0)|| (io->height > 2048)) |
15,33 → 17,37 |
return ERR_PARAM; |
}; |
pixmap = malloc(sizeof(local_pixmap_t)); |
if(!pixmap) |
return ERR_PARAM; |
pitch = ((io->width+15)&~15)*4; |
size = pitch*io->height; |
dbgprintf("pitch = %d\n", pitch); |
local = rhd_mem_alloc(&rhd,RHD_MEM_FB,size) ; |
if ( !local) |
{ |
if( (io->flags & PX_MEM_MASK) == PX_MEM_LOCAL ) { |
mem_local = rhd_mem_alloc(&rhd,RHD_MEM_FB,size); |
mem_dma = mem_local + rhd.fbLocation; |
} |
else |
mem_local = mem_dma = AllocPages( size >> 12 ); |
if ( !mem_local) { |
dbgprintf("Not enough memory for pixmap\n"); |
free(pixmap); |
return ERR_PARAM; |
}; |
pixmap = malloc(sizeof(local_pixmap_t)); |
if(!pixmap) |
{ |
rhd_mem_free(&rhd, RHD_MEM_FB,local); |
return ERR_PARAM; |
} |
else |
{ |
void *mapped; |
pixmap->pitch_offset = ((pitch/64)<<22)| (mem_dma>>10); |
pixmap->local = mem_dma; |
size = (size+4095) & ~ 4095; |
if (mapped = UserAlloc(size)) |
{ |
CommitPages(mapped, ((u32_t)local+rhd.LinearAddr)|7|(1<<9), size); |
CommitPages(mapped, mem_dma|7|(1<<9), size); |
io->mapped = mapped; |
io->pitch = pitch; |
50,11 → 56,9 |
pixmap->width = io->width; |
pixmap->height = io->height; |
pixmap->format = PICT_a8r8g8b8; |
pixmap->flags = PX_MEM_LOCAL; //io->flags; |
pixmap->flags = io->flags; |
pixmap->pitch = pitch; |
pixmap->mapped = mapped; |
pixmap->pitch_offset = ((pitch/64)<<22)| (((u32_t)local+rhd.fbLocation)>>10); |
pixmap->local = local+rhd.fbLocation; |
dbgprintf("pixmap.pitch_offset: %x\n", pixmap->pitch_offset); |
dbgprintf("width: %d height: %d\n",pixmap->width,pixmap->height ); |
62,9 → 66,9 |
return ERR_OK; |
}; |
rhd_mem_free(&rhd, RHD_MEM_FB,local); |
rhd_mem_free(&rhd, RHD_MEM_FB, mem_local); |
free(pixmap); |
}; |
return ERR_PARAM; |
}; |
86,7 → 90,25 |
UnmapPages(pixmap->mapped, size); |
UserFree(pixmap->mapped); |
if( (io->flags & PX_MEM_MASK) == PX_MEM_LOCAL ) |
{ |
rhd_mem_free(&rhd,RHD_MEM_FB,pixmap->local-rhd.fbLocation); |
} |
else |
{ |
count_t pages = size >> 12; |
addr_t base = pixmap->local; |
while( pages--) |
{ |
addr_t tmp; |
// __asm__ __volatile__( |
// "call *__imp__PageFree" |
// :"=eax" (tmp):"a" (base) ); |
// base+= 4096; |
}; |
} |
free(pixmap); |
io->format = 0; |
96,3 → 118,128 |
return ERR_OK; |
}; |
# define ATI_PCIGART_PAGE_SIZE 4096 /**< PCI GART page size */ |
# define ATI_PCIGART_PAGE_MASK (~(ATI_PCIGART_PAGE_SIZE-1)) |
#define ATI_PCIE_WRITE 0x4 |
#define ATI_PCIE_READ 0x8 |
#define upper_32_bits(n) ((u32_t)(((n) >> 16) >> 16)) |
static addr_t bind_pixmap(local_pixmap_t *pixmap) |
{ |
count_t pages; |
addr_t base; |
u32_t tmp; |
u32_t *gart = rhd.gart_table; |
pages = ((pixmap->height * pixmap->pitch+4095)&~4095)>>12; |
base = pixmap->local; |
// tmp = INREG(RADEON_AIC_CNTL); |
// OUTREG(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN); |
while(pages--) |
{ |
addr_t page_base; |
// *gart = base & ATI_PCIGART_PAGE_MASK; |
// base+= 4096; |
// gart++; |
page_base = base & ATI_PCIGART_PAGE_MASK; |
page_base >>= 8; |
page_base |= (upper_32_bits(base) & 0xff) << 24; |
page_base |= ATI_PCIE_READ | ATI_PCIE_WRITE; |
*gart = page_base; |
base+= 4096; |
gart++; |
} |
__asm__ __volatile("sfence":::"memory"); |
// OUTREG(RADEON_AIC_CNTL, tmp | RADEON_PCIGART_TRANSLATE_EN); |
// OUTREG(RADEON_AIC_PT_BASE, rhd.gart_table_dma); |
RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, |
RADEON_PCIE_TX_GART_EN |
| RADEON_PCIE_TX_GART_INVALIDATE_TLB); |
return ((pixmap->pitch / 64) << 22) | (rhd.gart_vm_start >> 10); |
} |
#if 0 |
int LockPixmap(userpixmap_t *io) |
{ |
pixmap_t *pixmap; |
size_t size; |
void *usermap; |
dbgprintf("Lock pixmap %x\n", io->pixmap); |
if(io->pixmap == (pixmap_t*)-1) |
return ERR_PARAM; |
else |
pixmap = io->pixmap; |
if( (pixmap->flags & 1) == PX_LOCK ) |
return ERR_PARAM; |
size = (pixmap->pitch*pixmap->width+4095) & ~ 4095; |
if (usermap = UserAlloc(size)) |
{ |
CommitPages(usermap, ((u32_t)pixmap->raw+rhd.PhisBase)|7|(1<<9), size); |
pixmap->flags |= PX_LOCK; |
pixmap->usermap = usermap; |
io->usermap = usermap; |
io->pitch = pixmap->pitch; |
dbgprintf("map at %x\n", io->usermap); |
return ERR_OK; |
} |
else |
return ERR_PARAM; |
}; |
int UnlockPixmap(userpixmap_t *io) |
{ |
pixmap_t *pixmap; |
size_t size; |
dbgprintf("Unlock pixmap %x\n", io->pixmap); |
if(io->pixmap == (pixmap_t*)-1) |
return ERR_PARAM; |
else |
pixmap = io->pixmap; |
if( (pixmap->flags & 1) != PX_LOCK ) |
return ERR_PARAM; |
/* Sanity checks */ |
if( (pixmap->usermap == 0)|| |
((u32_t)pixmap->usermap >= 0x80000000) || |
((u32_t)pixmap->usermap & 4095) |
) |
return ERR_PARAM; |
size = (pixmap->pitch*pixmap->width+4095) & ~ 4095; |
UnmapPages(pixmap->usermap, size); |
UserFree(pixmap->usermap); |
pixmap->usermap = NULL; |
pixmap->flags &= ~PX_LOCK; |
io->usermap = NULL; |
io->pitch = 0; |
return ERR_OK; |
}; |
#endif |
/programs/system/drivers/ati2d/r500.inc |
---|
175,9 → 175,9 |
scr_pixmap.format = PICT_a8r8g8b8; |
scr_pixmap.flags = PX_MEM_LOCAL; |
scr_pixmap.pitch = rhd.displayWidth * 4 ;//screenpitch; |
scr_pixmap.local = (void*)rhd.fbLocation; |
scr_pixmap.local = rhd.fbLocation; |
scr_pixmap.pitch_offset = rhd.dst_pitch_offset; |
scr_pixmap.mapped = (void*)0; |
scr_pixmap.mapped = 0; |
R5xxFIFOWaitLocal(2); |
OUTREG(R5XX_DST_PITCH_OFFSET,rhd.dst_pitch_offset); |
/programs/system/drivers/include/syscall.h |
---|
49,10 → 49,13 |
u32_t STDCALL RegService(char *name, srv_proc_t proc)__asm__("RegService"); |
int STDCALL AttachIntHandler(int irq, void *handler, u32_t access) __asm__("AttachIntHandler"); |
//void *CreateObject(u32 pid, size_t size); |
//void *DestroyObject(void *obj); |
addr_t STDCALL MapIoMem(void* base,size_t size,u32_t flags)__asm__("MapIoMem"); |
addr_t STDCALL MapIoMem(addr_t base, size_t size, u32_t flags)__asm__("MapIoMem"); |
/////////////////////////////////////////////////////////////////////////////// |
271,6 → 274,14 |
("outl %1, %0\n" : : "dN"(port), "a"(val)); |
} |
extern inline u8_t in8(const u16_t port) |
{ |
u8_t tmp; |
__asm__ __volatile__ |
("inb %1, %0\n" : "=a"(tmp) : "dN"(port)); |
return tmp; |
}; |
extern inline u16_t in16(const u16_t port) |
{ |
u16_t tmp; |