8,7 → 8,6 |
;; ;; |
;; Extended PCI express services ;; |
;; ;; |
;; Author: ;; |
;; art_zh <artem@jerdev.co.uk> ;; |
;; ;; |
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
30,8 → 29,8 |
;*************************************************************************** |
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PCIe_CONFIG_SPACE equ 0xF0000000 ; to be moved to const.inc |
mmio_pcie_cfg_addr dd 0x0 ; not defined by default |
mmio_pcie_cfg_lim dd 0x0 ; each bus needs 1Mb |
mmio_pcie_cfg_addr dd 0x0 ; intel pcie space may be defined here |
mmio_pcie_cfg_lim dd 0x0 ; upper pcie space address |
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align 4 |
38,7 → 37,19 |
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pci_ext_config: |
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push ebx |
mov ebx, [mmio_pcie_cfg_addr] |
or ebx,ebx |
jz @f |
or ebx, 0x7FFFFFFF ; required by PCI-SIG standards |
jnz .pcie_failed |
add ebx, 0x0FFFFC |
cmp ebx, [mmio_pcie_cfg_lim]; is the space limit correct? |
ja .pcie_failed |
jmp .pcie_cfg_mapped |
@@: |
mov ebx, [cpu_vendor] |
cmp ebx, dword [AMD_str] |
jne .pcie_failed |
mov bx, 0xC184 ; dev = 24, fn = 01, reg = 84h |
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.check_HT_mmio: |
48,7 → 59,7 |
mov bx, cx |
sub bl, 4 |
and al, 0x80 ; check the NP bit |
jz .not_pcie_cfg |
jz .no_pcie_cfg |
shl eax, 8 ; bus:[27..20], dev:[19:15] |
or eax, 0x00007FFC ; fun:[14..12], reg:[11:2] |
mov [mmio_pcie_cfg_lim], eax |
57,17 → 68,17 |
call pci_read_reg |
mov bx, cx |
test al, 0x03 ; MMIO Base RW enabled? |
jz .not_pcie_cfg |
jz .no_pcie_cfg |
test al, 0x0C ; MMIO Base locked? |
jnz .not_pcie_cfg |
jnz .no_pcie_cfg |
xor al, al |
shl eax, 8 |
; test eax, 0x000F0000 ; MMIO Base must be bus0-aligned |
; jnz .not_pcie_cfg |
test eax, 0x000F0000 ; MMIO Base must be bus0-aligned |
jnz .no_pcie_cfg |
mov [mmio_pcie_cfg_addr], eax |
add eax, 0x000FFFFC |
sub eax,[mmio_pcie_cfg_lim] ; MMIO must cover at least one bus |
ja .not_pcie_cfg |
ja .no_pcie_cfg |
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; -- it looks like a true PCIe config space; |
mov eax,[mmio_pcie_cfg_addr] ; physical address |
89,12 → 100,11 |
.pcie_cfg_mapped: |
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; -- glad to have the extended PCIe config field found |
mov esi, boot_pcie_ok |
pop ebx |
call boot_log |
; mov esi, boot_pcie_ok |
; call boot_log |
ret ; <<<<<<<<<<< OK >>>>>>>>>>> |
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.not_pcie_cfg: |
.no_pcie_cfg: |
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xor eax, eax |
mov [mmio_pcie_cfg_addr], eax |
102,8 → 112,8 |
add bl, 12 |
cmp bl, 0xC0 ; MMIO regs lay below this offset |
jb .check_HT_mmio |
mov esi, boot_pcie_fail |
pop ebx |
call boot_log |
.pcie_failed: |
; mov esi, boot_pcie_fail |
; call boot_log |
ret ; <<<<<<<<< FAILURE >>>>>>>>> |
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