Subversion Repositories Kolibri OS

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Regard whitespace Rev 1550 → Rev 1551

/kernel/branches/Kolibri-A/trunk/bus/HT.INC
0,0 → 1,144
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; ;;
;; Copyright (C) 2010 KolibriOS team. All rights reserved. ;;
;; Distributed under terms of the GNU General Public License ;;
;; ;;
;; HT.inc ;; ;;
;; ;;
;; AMD HyperTransport bus control ;;
;; ;;
;; art_zh <artem@jerdev.co.uk> ;;
;; ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 
 
align 4
 
;=============================================================================
;
; This code is a part of Kolibri-A and will only work with AMD RS760+ chipsets
;
;=============================================================================
 
;------------------------------------------
; params: al = nbconfig register#
; returns: eax = register content
;
rs7xx_nbconfig_read_pci:
and eax, 0x0FC ; leave register# only
or eax, 0x80000000 ; bdf = 0:0.0
mov dx, 0x0CF8 ; write to index reg
out dx, eax
add dl, 4
in eax, dx
ret
 
rs7xx_nbconfig_flush_pci:
mov eax, 0x0B0 ; a scratch reg
mov dx, 0xCF8
out dx, eax
ret
 
 
rs7xx_nbconfig_write_pci:
and eax, 0x0FC ; leave register# only
or eax, 0x80000000 ; bdf = 0:0.0
mov dx, 0x0CF8 ; write to index reg
out dx, eax
add dl, 4
mov eax, ebx
out dx, eax
ret
 
;***************************************************************************
; Function
; rs7xx_pcie_init:
;
; Description
; PCIe extended (memory-mapped) config space detection
;
;***************************************************************************
 
rs7xx_pcie_init:
; mov al, 0x7C ; NB_IOC_CFG_CNTL
; mov ebx, 0x20000000
; call rs7xx_nbconfig_write_pci
mov al, 0x7C ; NB_IOC_CFG_CNTL
call rs7xx_nbconfig_read_pci
mov ebx, eax
call rs7xx_nbconfig_flush_pci
test ebx, 0x20000000 ; BAR3 locked?
jz .rs7xx_pcie_blocked
mov al, 0x84 ; NB_PCI_ARB
call rs7xx_nbconfig_read_pci
shr eax,16
and ax, 7 ; the Bus range lays here:
jnz @f
mov ax, 8 ; 1=2Mb, 2=4MB, 3=8MB, 4=16MB
@@:
mov [PCIe_bus_range], ax ; 5=32Mb, 6=64MB, 7=128Mb, 8=256Mb
mov cl, al
call rs7xx_nbconfig_flush_pci
dec cl ; <4M ?
jnz @f
inc cl ; one PDE needed anyway
@@:
dec cl
mov ebx, 1
shl ebx, cl
mov [mmio_pcie_cfg_pdes], bx ; 1..64 PDE(s) needed,
shl ebx, 22
mov [mmio_pcie_cfg_lim], ebx ; or 4..256Mb space to map
dec [mmio_pcie_cfg_lim]
 
mov al, 0x1C ; NB_BAR3_PCIEXP_MMCFG
call rs7xx_nbconfig_read_pci
mov ebx, eax
call rs7xx_nbconfig_flush_pci
mov eax, ebx
and eax, 0xFFE00000 ; valid bits [31..21]
jnz @f ; NB BAR3 may be invisible!
call pci_ext_config ; try to get pcie ecfg address indirectly
@@:
or eax, eax
jz .rs7xx_pcie_fail
mov [mmio_pcie_cfg_addr], eax ; physical address (lower 32 bits)
add [mmio_pcie_cfg_lim], eax
 
; -- map the whole PCIe config space;
or eax, (PG_SHARED + PG_LARGE + PG_UW) ; by the way, UW is unsafe!
mov ecx, PCIe_CONFIG_SPACE ; linear address
mov ebx, ecx
shr ebx, 20
add ebx, sys_pgdir ; PgDir entry @
xor dx, dx ; PDEs counter
@@:
mov dword[ebx], eax ; map 4 buses
invlpg [ecx] ; next PgDir entry
add bx, 4 ; new PDE
add eax, 0x400000 ; +4M phys.
add ecx, 0x400000 ; +4M lin.
inc dx
cmp dx, [mmio_pcie_cfg_pdes] ; all mapped yet?
jnz @b
 
.pcie_cfg_mapped:
mov esi, boot_pcie_ok
call boot_log
ret ; <<<<<<<<<<< OK >>>>>>>>>>>
 
.rs7xx_pcie_fail:
mov esi, boot_rs7xx_fail
call boot_log
ret
 
.rs7xx_pcie_blocked:
mov esi, boot_rs7xx_blkd
call boot_log
 
 
ret
 
 
 
/kernel/branches/Kolibri-A/trunk/bus/pci/PCIe.inc
28,12 → 28,14
;
;***************************************************************************
 
align 4
mmio_pcie_cfg_addr dd 0x00000000 ; pcie space may be defined here
mmio_pcie_cfg_lim dd 0x000FFFFF ; upper pcie space address
mmio_pcie_cfg_pdes dw 0 ; number of PDEs to map the space
PCIe_bus_range dw 0 ; the Bus range: power-of-2 Megabytes
 
 
align 4
 
pci_ext_config:
mov ebx, [mmio_pcie_cfg_addr]
or ebx,ebx
60,7 → 62,7
jz .no_pcie_cfg
shl eax, 8 ; bus:[27..20], dev:[19:15]
or eax, 0x00007FFC ; fun:[14..12], reg:[11:2]
mov [mmio_pcie_cfg_lim], eax
; mov [mmio_pcie_cfg_lim], eax
mov cl, bl
mov ax, 0x0002 ; bus = 0, 1dword to read
call pci_read_reg
74,30 → 76,14
test eax, 0x000F0000 ; MMIO Base must be bus0-aligned
jnz .no_pcie_cfg
mov [mmio_pcie_cfg_addr], eax
add eax, 0x000FFFFC
sub eax,[mmio_pcie_cfg_lim] ; MMIO must cover at least one bus
ja .no_pcie_cfg
; add eax, 0x000FFFFC
; sub eax,[mmio_pcie_cfg_lim] ; MMIO must cover at least one bus
; ja .no_pcie_cfg
 
; -- it looks like a true PCIe config space;
mov eax,[mmio_pcie_cfg_addr] ; physical address
or eax, (PG_SHARED + PG_LARGE + PG_USER)
mov ebx, PCIe_CONFIG_SPACE ; linear address
mov ecx, ebx
shr ebx, 20
add ebx, sys_pgdir ; PgDir entry @
@@:
mov dword[ebx], eax ; map 4 buses
invlpg [ecx]
cmp bl, 4
jz .pcie_cfg_mapped ; fix it later
add bl, 4 ; next PgDir entry
add eax, 0x400000 ; eax += 4M
add ecx, 0x400000
jmp @b
 
.pcie_cfg_mapped:
; -- glad to have the extended PCIe config field found
mov esi, boot_pcie_ok
call boot_log
ret ; <<<<<<<<<<< OK >>>>>>>>>>>