42,8 → 42,843 |
static void rv770_gpu_init(struct radeon_device *rdev); |
void rv770_fini(struct radeon_device *rdev); |
static void rv770_pcie_gen2_enable(struct radeon_device *rdev); |
int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk); |
|
int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) |
{ |
unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; |
int r; |
|
/* RV740 uses evergreen uvd clk programming */ |
if (rdev->family == CHIP_RV740) |
return evergreen_set_uvd_clocks(rdev, vclk, dclk); |
|
/* bypass vclk and dclk with bclk */ |
WREG32_P(CG_UPLL_FUNC_CNTL_2, |
VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1), |
~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); |
|
if (!vclk || !dclk) { |
/* keep the Bypass mode, put PLL to sleep */ |
WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK); |
return 0; |
} |
|
// r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000, |
// 43663, 0x03FFFFFE, 1, 30, ~0, |
// &fb_div, &vclk_div, &dclk_div); |
// if (r) |
return r; |
|
fb_div |= 1; |
vclk_div -= 1; |
dclk_div -= 1; |
|
/* set UPLL_FB_DIV to 0x50000 */ |
WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(0x50000), ~UPLL_FB_DIV_MASK); |
|
/* deassert UPLL_RESET and UPLL_SLEEP */ |
WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~(UPLL_RESET_MASK | UPLL_SLEEP_MASK)); |
|
/* assert BYPASS EN and FB_DIV[0] <- ??? why? */ |
WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK); |
WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(1), ~UPLL_FB_DIV(1)); |
|
// r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); |
// if (r) |
return r; |
|
/* assert PLL_RESET */ |
WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK); |
|
/* set the required FB_DIV, REF_DIV, Post divder values */ |
WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REF_DIV(1), ~UPLL_REF_DIV_MASK); |
WREG32_P(CG_UPLL_FUNC_CNTL_2, |
UPLL_SW_HILEN(vclk_div >> 1) | |
UPLL_SW_LOLEN((vclk_div >> 1) + (vclk_div & 1)) | |
UPLL_SW_HILEN2(dclk_div >> 1) | |
UPLL_SW_LOLEN2((dclk_div >> 1) + (dclk_div & 1)), |
~UPLL_SW_MASK); |
|
WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), |
~UPLL_FB_DIV_MASK); |
|
/* give the PLL some time to settle */ |
mdelay(15); |
|
/* deassert PLL_RESET */ |
WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); |
|
mdelay(15); |
|
/* deassert BYPASS EN and FB_DIV[0] <- ??? why? */ |
WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK); |
WREG32_P(CG_UPLL_FUNC_CNTL_3, 0, ~UPLL_FB_DIV(1)); |
|
// r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); |
// if (r) |
return r; |
|
/* switch VCLK and DCLK selection */ |
WREG32_P(CG_UPLL_FUNC_CNTL_2, |
VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2), |
~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); |
|
mdelay(100); |
|
return 0; |
} |
|
static const u32 r7xx_golden_registers[] = |
{ |
0x8d00, 0xffffffff, 0x0e0e0074, |
0x8d04, 0xffffffff, 0x013a2b34, |
0x9508, 0xffffffff, 0x00000002, |
0x8b20, 0xffffffff, 0, |
0x88c4, 0xffffffff, 0x000000c2, |
0x28350, 0xffffffff, 0, |
0x9058, 0xffffffff, 0x0fffc40f, |
0x240c, 0xffffffff, 0x00000380, |
0x733c, 0xffffffff, 0x00000002, |
0x2650, 0x00040000, 0, |
0x20bc, 0x00040000, 0, |
0x7300, 0xffffffff, 0x001000f0 |
}; |
|
static const u32 r7xx_golden_dyn_gpr_registers[] = |
{ |
0x8db0, 0xffffffff, 0x98989898, |
0x8db4, 0xffffffff, 0x98989898, |
0x8db8, 0xffffffff, 0x98989898, |
0x8dbc, 0xffffffff, 0x98989898, |
0x8dc0, 0xffffffff, 0x98989898, |
0x8dc4, 0xffffffff, 0x98989898, |
0x8dc8, 0xffffffff, 0x98989898, |
0x8dcc, 0xffffffff, 0x98989898, |
0x88c4, 0xffffffff, 0x00000082 |
}; |
|
static const u32 rv770_golden_registers[] = |
{ |
0x562c, 0xffffffff, 0, |
0x3f90, 0xffffffff, 0, |
0x9148, 0xffffffff, 0, |
0x3f94, 0xffffffff, 0, |
0x914c, 0xffffffff, 0, |
0x9698, 0x18000000, 0x18000000 |
}; |
|
static const u32 rv770ce_golden_registers[] = |
{ |
0x562c, 0xffffffff, 0, |
0x3f90, 0xffffffff, 0x00cc0000, |
0x9148, 0xffffffff, 0x00cc0000, |
0x3f94, 0xffffffff, 0x00cc0000, |
0x914c, 0xffffffff, 0x00cc0000, |
0x9b7c, 0xffffffff, 0x00fa0000, |
0x3f8c, 0xffffffff, 0x00fa0000, |
0x9698, 0x18000000, 0x18000000 |
}; |
|
static const u32 rv770_mgcg_init[] = |
{ |
0x8bcc, 0xffffffff, 0x130300f9, |
0x5448, 0xffffffff, 0x100, |
0x55e4, 0xffffffff, 0x100, |
0x160c, 0xffffffff, 0x100, |
0x5644, 0xffffffff, 0x100, |
0xc164, 0xffffffff, 0x100, |
0x8a18, 0xffffffff, 0x100, |
0x897c, 0xffffffff, 0x8000100, |
0x8b28, 0xffffffff, 0x3c000100, |
0x9144, 0xffffffff, 0x100, |
0x9a1c, 0xffffffff, 0x10000, |
0x9a50, 0xffffffff, 0x100, |
0x9a1c, 0xffffffff, 0x10001, |
0x9a50, 0xffffffff, 0x100, |
0x9a1c, 0xffffffff, 0x10002, |
0x9a50, 0xffffffff, 0x100, |
0x9a1c, 0xffffffff, 0x10003, |
0x9a50, 0xffffffff, 0x100, |
0x9a1c, 0xffffffff, 0x0, |
0x9870, 0xffffffff, 0x100, |
0x8d58, 0xffffffff, 0x100, |
0x9500, 0xffffffff, 0x0, |
0x9510, 0xffffffff, 0x100, |
0x9500, 0xffffffff, 0x1, |
0x9510, 0xffffffff, 0x100, |
0x9500, 0xffffffff, 0x2, |
0x9510, 0xffffffff, 0x100, |
0x9500, 0xffffffff, 0x3, |
0x9510, 0xffffffff, 0x100, |
0x9500, 0xffffffff, 0x4, |
0x9510, 0xffffffff, 0x100, |
0x9500, 0xffffffff, 0x5, |
0x9510, 0xffffffff, 0x100, |
0x9500, 0xffffffff, 0x6, |
0x9510, 0xffffffff, 0x100, |
0x9500, 0xffffffff, 0x7, |
0x9510, 0xffffffff, 0x100, |
0x9500, 0xffffffff, 0x8, |
0x9510, 0xffffffff, 0x100, |
0x9500, 0xffffffff, 0x9, |
0x9510, 0xffffffff, 0x100, |
0x9500, 0xffffffff, 0x8000, |
0x9490, 0xffffffff, 0x0, |
0x949c, 0xffffffff, 0x100, |
0x9490, 0xffffffff, 0x1, |
0x949c, 0xffffffff, 0x100, |
0x9490, 0xffffffff, 0x2, |
0x949c, 0xffffffff, 0x100, |
0x9490, 0xffffffff, 0x3, |
0x949c, 0xffffffff, 0x100, |
0x9490, 0xffffffff, 0x4, |
0x949c, 0xffffffff, 0x100, |
0x9490, 0xffffffff, 0x5, |
0x949c, 0xffffffff, 0x100, |
0x9490, 0xffffffff, 0x6, |
0x949c, 0xffffffff, 0x100, |
0x9490, 0xffffffff, 0x7, |
0x949c, 0xffffffff, 0x100, |
0x9490, 0xffffffff, 0x8, |
0x949c, 0xffffffff, 0x100, |
0x9490, 0xffffffff, 0x9, |
0x949c, 0xffffffff, 0x100, |
0x9490, 0xffffffff, 0x8000, |
0x9604, 0xffffffff, 0x0, |
0x9654, 0xffffffff, 0x100, |
0x9604, 0xffffffff, 0x1, |
0x9654, 0xffffffff, 0x100, |
0x9604, 0xffffffff, 0x2, |
0x9654, 0xffffffff, 0x100, |
0x9604, 0xffffffff, 0x3, |
0x9654, 0xffffffff, 0x100, |
0x9604, 0xffffffff, 0x4, |
0x9654, 0xffffffff, 0x100, |
0x9604, 0xffffffff, 0x5, |
0x9654, 0xffffffff, 0x100, |
0x9604, 0xffffffff, 0x6, |
0x9654, 0xffffffff, 0x100, |
0x9604, 0xffffffff, 0x7, |
0x9654, 0xffffffff, 0x100, |
0x9604, 0xffffffff, 0x8, |
0x9654, 0xffffffff, 0x100, |
0x9604, 0xffffffff, 0x9, |
0x9654, 0xffffffff, 0x100, |
0x9604, 0xffffffff, 0x80000000, |
0x9030, 0xffffffff, 0x100, |
0x9034, 0xffffffff, 0x100, |
0x9038, 0xffffffff, 0x100, |
0x903c, 0xffffffff, 0x100, |
0x9040, 0xffffffff, 0x100, |
0xa200, 0xffffffff, 0x100, |
0xa204, 0xffffffff, 0x100, |
0xa208, 0xffffffff, 0x100, |
0xa20c, 0xffffffff, 0x100, |
0x971c, 0xffffffff, 0x100, |
0x915c, 0xffffffff, 0x00020001, |
0x9160, 0xffffffff, 0x00040003, |
0x916c, 0xffffffff, 0x00060005, |
0x9170, 0xffffffff, 0x00080007, |
0x9174, 0xffffffff, 0x000a0009, |
0x9178, 0xffffffff, 0x000c000b, |
0x917c, 0xffffffff, 0x000e000d, |
0x9180, 0xffffffff, 0x0010000f, |
0x918c, 0xffffffff, 0x00120011, |
0x9190, 0xffffffff, 0x00140013, |
0x9194, 0xffffffff, 0x00020001, |
0x9198, 0xffffffff, 0x00040003, |
0x919c, 0xffffffff, 0x00060005, |
0x91a8, 0xffffffff, 0x00080007, |
0x91ac, 0xffffffff, 0x000a0009, |
0x91b0, 0xffffffff, 0x000c000b, |
0x91b4, 0xffffffff, 0x000e000d, |
0x91b8, 0xffffffff, 0x0010000f, |
0x91c4, 0xffffffff, 0x00120011, |
0x91c8, 0xffffffff, 0x00140013, |
0x91cc, 0xffffffff, 0x00020001, |
0x91d0, 0xffffffff, 0x00040003, |
0x91d4, 0xffffffff, 0x00060005, |
0x91e0, 0xffffffff, 0x00080007, |
0x91e4, 0xffffffff, 0x000a0009, |
0x91e8, 0xffffffff, 0x000c000b, |
0x91ec, 0xffffffff, 0x00020001, |
0x91f0, 0xffffffff, 0x00040003, |
0x91f4, 0xffffffff, 0x00060005, |
0x9200, 0xffffffff, 0x00080007, |
0x9204, 0xffffffff, 0x000a0009, |
0x9208, 0xffffffff, 0x000c000b, |
0x920c, 0xffffffff, 0x000e000d, |
0x9210, 0xffffffff, 0x0010000f, |
0x921c, 0xffffffff, 0x00120011, |
0x9220, 0xffffffff, 0x00140013, |
0x9224, 0xffffffff, 0x00020001, |
0x9228, 0xffffffff, 0x00040003, |
0x922c, 0xffffffff, 0x00060005, |
0x9238, 0xffffffff, 0x00080007, |
0x923c, 0xffffffff, 0x000a0009, |
0x9240, 0xffffffff, 0x000c000b, |
0x9244, 0xffffffff, 0x000e000d, |
0x9248, 0xffffffff, 0x0010000f, |
0x9254, 0xffffffff, 0x00120011, |
0x9258, 0xffffffff, 0x00140013, |
0x925c, 0xffffffff, 0x00020001, |
0x9260, 0xffffffff, 0x00040003, |
0x9264, 0xffffffff, 0x00060005, |
0x9270, 0xffffffff, 0x00080007, |
0x9274, 0xffffffff, 0x000a0009, |
0x9278, 0xffffffff, 0x000c000b, |
0x927c, 0xffffffff, 0x000e000d, |
0x9280, 0xffffffff, 0x0010000f, |
0x928c, 0xffffffff, 0x00120011, |
0x9290, 0xffffffff, 0x00140013, |
0x9294, 0xffffffff, 0x00020001, |
0x929c, 0xffffffff, 0x00040003, |
0x92a0, 0xffffffff, 0x00060005, |
0x92a4, 0xffffffff, 0x00080007 |
}; |
|
static const u32 rv710_golden_registers[] = |
{ |
0x3f90, 0x00ff0000, 0x00fc0000, |
0x9148, 0x00ff0000, 0x00fc0000, |
0x3f94, 0x00ff0000, 0x00fc0000, |
0x914c, 0x00ff0000, 0x00fc0000, |
0xb4c, 0x00000020, 0x00000020, |
0xa180, 0xffffffff, 0x00003f3f |
}; |
|
static const u32 rv710_mgcg_init[] = |
{ |
0x8bcc, 0xffffffff, 0x13030040, |
0x5448, 0xffffffff, 0x100, |
0x55e4, 0xffffffff, 0x100, |
0x160c, 0xffffffff, 0x100, |
0x5644, 0xffffffff, 0x100, |
0xc164, 0xffffffff, 0x100, |
0x8a18, 0xffffffff, 0x100, |
0x897c, 0xffffffff, 0x8000100, |
0x8b28, 0xffffffff, 0x3c000100, |
0x9144, 0xffffffff, 0x100, |
0x9a1c, 0xffffffff, 0x10000, |
0x9a50, 0xffffffff, 0x100, |
0x9a1c, 0xffffffff, 0x0, |
0x9870, 0xffffffff, 0x100, |
0x8d58, 0xffffffff, 0x100, |
0x9500, 0xffffffff, 0x0, |
0x9510, 0xffffffff, 0x100, |
0x9500, 0xffffffff, 0x1, |
0x9510, 0xffffffff, 0x100, |
0x9500, 0xffffffff, 0x8000, |
0x9490, 0xffffffff, 0x0, |
0x949c, 0xffffffff, 0x100, |
0x9490, 0xffffffff, 0x1, |
0x949c, 0xffffffff, 0x100, |
0x9490, 0xffffffff, 0x8000, |
0x9604, 0xffffffff, 0x0, |
0x9654, 0xffffffff, 0x100, |
0x9604, 0xffffffff, 0x1, |
0x9654, 0xffffffff, 0x100, |
0x9604, 0xffffffff, 0x80000000, |
0x9030, 0xffffffff, 0x100, |
0x9034, 0xffffffff, 0x100, |
0x9038, 0xffffffff, 0x100, |
0x903c, 0xffffffff, 0x100, |
0x9040, 0xffffffff, 0x100, |
0xa200, 0xffffffff, 0x100, |
0xa204, 0xffffffff, 0x100, |
0xa208, 0xffffffff, 0x100, |
0xa20c, 0xffffffff, 0x100, |
0x971c, 0xffffffff, 0x100, |
0x915c, 0xffffffff, 0x00020001, |
0x9174, 0xffffffff, 0x00000003, |
0x9178, 0xffffffff, 0x00050001, |
0x917c, 0xffffffff, 0x00030002, |
0x918c, 0xffffffff, 0x00000004, |
0x9190, 0xffffffff, 0x00070006, |
0x9194, 0xffffffff, 0x00050001, |
0x9198, 0xffffffff, 0x00030002, |
0x91a8, 0xffffffff, 0x00000004, |
0x91ac, 0xffffffff, 0x00070006, |
0x91e8, 0xffffffff, 0x00000001, |
0x9294, 0xffffffff, 0x00000001, |
0x929c, 0xffffffff, 0x00000002, |
0x92a0, 0xffffffff, 0x00040003, |
0x9150, 0xffffffff, 0x4d940000 |
}; |
|
static const u32 rv730_golden_registers[] = |
{ |
0x3f90, 0x00ff0000, 0x00f00000, |
0x9148, 0x00ff0000, 0x00f00000, |
0x3f94, 0x00ff0000, 0x00f00000, |
0x914c, 0x00ff0000, 0x00f00000, |
0x900c, 0xffffffff, 0x003b033f, |
0xb4c, 0x00000020, 0x00000020, |
0xa180, 0xffffffff, 0x00003f3f |
}; |
|
static const u32 rv730_mgcg_init[] = |
{ |
0x8bcc, 0xffffffff, 0x130300f9, |
0x5448, 0xffffffff, 0x100, |
0x55e4, 0xffffffff, 0x100, |
0x160c, 0xffffffff, 0x100, |
0x5644, 0xffffffff, 0x100, |
0xc164, 0xffffffff, 0x100, |
0x8a18, 0xffffffff, 0x100, |
0x897c, 0xffffffff, 0x8000100, |
0x8b28, 0xffffffff, 0x3c000100, |
0x9144, 0xffffffff, 0x100, |
0x9a1c, 0xffffffff, 0x10000, |
0x9a50, 0xffffffff, 0x100, |
0x9a1c, 0xffffffff, 0x10001, |
0x9a50, 0xffffffff, 0x100, |
0x9a1c, 0xffffffff, 0x0, |
0x9870, 0xffffffff, 0x100, |
0x8d58, 0xffffffff, 0x100, |
0x9500, 0xffffffff, 0x0, |
0x9510, 0xffffffff, 0x100, |
0x9500, 0xffffffff, 0x1, |
0x9510, 0xffffffff, 0x100, |
0x9500, 0xffffffff, 0x2, |
0x9510, 0xffffffff, 0x100, |
0x9500, 0xffffffff, 0x3, |
0x9510, 0xffffffff, 0x100, |
0x9500, 0xffffffff, 0x4, |
0x9510, 0xffffffff, 0x100, |
0x9500, 0xffffffff, 0x5, |
0x9510, 0xffffffff, 0x100, |
0x9500, 0xffffffff, 0x6, |
0x9510, 0xffffffff, 0x100, |
0x9500, 0xffffffff, 0x7, |
0x9510, 0xffffffff, 0x100, |
0x9500, 0xffffffff, 0x8000, |
0x9490, 0xffffffff, 0x0, |
0x949c, 0xffffffff, 0x100, |
0x9490, 0xffffffff, 0x1, |
0x949c, 0xffffffff, 0x100, |
0x9490, 0xffffffff, 0x2, |
0x949c, 0xffffffff, 0x100, |
0x9490, 0xffffffff, 0x3, |
0x949c, 0xffffffff, 0x100, |
0x9490, 0xffffffff, 0x4, |
0x949c, 0xffffffff, 0x100, |
0x9490, 0xffffffff, 0x5, |
0x949c, 0xffffffff, 0x100, |
0x9490, 0xffffffff, 0x6, |
0x949c, 0xffffffff, 0x100, |
0x9490, 0xffffffff, 0x7, |
0x949c, 0xffffffff, 0x100, |
0x9490, 0xffffffff, 0x8000, |
0x9604, 0xffffffff, 0x0, |
0x9654, 0xffffffff, 0x100, |
0x9604, 0xffffffff, 0x1, |
0x9654, 0xffffffff, 0x100, |
0x9604, 0xffffffff, 0x2, |
0x9654, 0xffffffff, 0x100, |
0x9604, 0xffffffff, 0x3, |
0x9654, 0xffffffff, 0x100, |
0x9604, 0xffffffff, 0x4, |
0x9654, 0xffffffff, 0x100, |
0x9604, 0xffffffff, 0x5, |
0x9654, 0xffffffff, 0x100, |
0x9604, 0xffffffff, 0x6, |
0x9654, 0xffffffff, 0x100, |
0x9604, 0xffffffff, 0x7, |
0x9654, 0xffffffff, 0x100, |
0x9604, 0xffffffff, 0x80000000, |
0x9030, 0xffffffff, 0x100, |
0x9034, 0xffffffff, 0x100, |
0x9038, 0xffffffff, 0x100, |
0x903c, 0xffffffff, 0x100, |
0x9040, 0xffffffff, 0x100, |
0xa200, 0xffffffff, 0x100, |
0xa204, 0xffffffff, 0x100, |
0xa208, 0xffffffff, 0x100, |
0xa20c, 0xffffffff, 0x100, |
0x971c, 0xffffffff, 0x100, |
0x915c, 0xffffffff, 0x00020001, |
0x916c, 0xffffffff, 0x00040003, |
0x9170, 0xffffffff, 0x00000005, |
0x9178, 0xffffffff, 0x00050001, |
0x917c, 0xffffffff, 0x00030002, |
0x918c, 0xffffffff, 0x00000004, |
0x9190, 0xffffffff, 0x00070006, |
0x9194, 0xffffffff, 0x00050001, |
0x9198, 0xffffffff, 0x00030002, |
0x91a8, 0xffffffff, 0x00000004, |
0x91ac, 0xffffffff, 0x00070006, |
0x91b0, 0xffffffff, 0x00050001, |
0x91b4, 0xffffffff, 0x00030002, |
0x91c4, 0xffffffff, 0x00000004, |
0x91c8, 0xffffffff, 0x00070006, |
0x91cc, 0xffffffff, 0x00050001, |
0x91d0, 0xffffffff, 0x00030002, |
0x91e0, 0xffffffff, 0x00000004, |
0x91e4, 0xffffffff, 0x00070006, |
0x91e8, 0xffffffff, 0x00000001, |
0x91ec, 0xffffffff, 0x00050001, |
0x91f0, 0xffffffff, 0x00030002, |
0x9200, 0xffffffff, 0x00000004, |
0x9204, 0xffffffff, 0x00070006, |
0x9208, 0xffffffff, 0x00050001, |
0x920c, 0xffffffff, 0x00030002, |
0x921c, 0xffffffff, 0x00000004, |
0x9220, 0xffffffff, 0x00070006, |
0x9224, 0xffffffff, 0x00050001, |
0x9228, 0xffffffff, 0x00030002, |
0x9238, 0xffffffff, 0x00000004, |
0x923c, 0xffffffff, 0x00070006, |
0x9240, 0xffffffff, 0x00050001, |
0x9244, 0xffffffff, 0x00030002, |
0x9254, 0xffffffff, 0x00000004, |
0x9258, 0xffffffff, 0x00070006, |
0x9294, 0xffffffff, 0x00000001, |
0x929c, 0xffffffff, 0x00000002, |
0x92a0, 0xffffffff, 0x00040003, |
0x92a4, 0xffffffff, 0x00000005 |
}; |
|
static const u32 rv740_golden_registers[] = |
{ |
0x88c4, 0xffffffff, 0x00000082, |
0x28a50, 0xfffffffc, 0x00000004, |
0x2650, 0x00040000, 0, |
0x20bc, 0x00040000, 0, |
0x733c, 0xffffffff, 0x00000002, |
0x7300, 0xffffffff, 0x001000f0, |
0x3f90, 0x00ff0000, 0, |
0x9148, 0x00ff0000, 0, |
0x3f94, 0x00ff0000, 0, |
0x914c, 0x00ff0000, 0, |
0x240c, 0xffffffff, 0x00000380, |
0x8a14, 0x00000007, 0x00000007, |
0x8b24, 0xffffffff, 0x00ff0fff, |
0x28a4c, 0xffffffff, 0x00004000, |
0xa180, 0xffffffff, 0x00003f3f, |
0x8d00, 0xffffffff, 0x0e0e003a, |
0x8d04, 0xffffffff, 0x013a0e2a, |
0x8c00, 0xffffffff, 0xe400000f, |
0x8db0, 0xffffffff, 0x98989898, |
0x8db4, 0xffffffff, 0x98989898, |
0x8db8, 0xffffffff, 0x98989898, |
0x8dbc, 0xffffffff, 0x98989898, |
0x8dc0, 0xffffffff, 0x98989898, |
0x8dc4, 0xffffffff, 0x98989898, |
0x8dc8, 0xffffffff, 0x98989898, |
0x8dcc, 0xffffffff, 0x98989898, |
0x9058, 0xffffffff, 0x0fffc40f, |
0x900c, 0xffffffff, 0x003b033f, |
0x28350, 0xffffffff, 0, |
0x8cf0, 0x1fffffff, 0x08e00420, |
0x9508, 0xffffffff, 0x00000002, |
0x88c4, 0xffffffff, 0x000000c2, |
0x9698, 0x18000000, 0x18000000 |
}; |
|
static const u32 rv740_mgcg_init[] = |
{ |
0x8bcc, 0xffffffff, 0x13030100, |
0x5448, 0xffffffff, 0x100, |
0x55e4, 0xffffffff, 0x100, |
0x160c, 0xffffffff, 0x100, |
0x5644, 0xffffffff, 0x100, |
0xc164, 0xffffffff, 0x100, |
0x8a18, 0xffffffff, 0x100, |
0x897c, 0xffffffff, 0x100, |
0x8b28, 0xffffffff, 0x100, |
0x9144, 0xffffffff, 0x100, |
0x9a1c, 0xffffffff, 0x10000, |
0x9a50, 0xffffffff, 0x100, |
0x9a1c, 0xffffffff, 0x10001, |
0x9a50, 0xffffffff, 0x100, |
0x9a1c, 0xffffffff, 0x10002, |
0x9a50, 0xffffffff, 0x100, |
0x9a1c, 0xffffffff, 0x10003, |
0x9a50, 0xffffffff, 0x100, |
0x9a1c, 0xffffffff, 0x0, |
0x9870, 0xffffffff, 0x100, |
0x8d58, 0xffffffff, 0x100, |
0x9500, 0xffffffff, 0x0, |
0x9510, 0xffffffff, 0x100, |
0x9500, 0xffffffff, 0x1, |
0x9510, 0xffffffff, 0x100, |
0x9500, 0xffffffff, 0x2, |
0x9510, 0xffffffff, 0x100, |
0x9500, 0xffffffff, 0x3, |
0x9510, 0xffffffff, 0x100, |
0x9500, 0xffffffff, 0x4, |
0x9510, 0xffffffff, 0x100, |
0x9500, 0xffffffff, 0x5, |
0x9510, 0xffffffff, 0x100, |
0x9500, 0xffffffff, 0x6, |
0x9510, 0xffffffff, 0x100, |
0x9500, 0xffffffff, 0x7, |
0x9510, 0xffffffff, 0x100, |
0x9500, 0xffffffff, 0x8000, |
0x9490, 0xffffffff, 0x0, |
0x949c, 0xffffffff, 0x100, |
0x9490, 0xffffffff, 0x1, |
0x949c, 0xffffffff, 0x100, |
0x9490, 0xffffffff, 0x2, |
0x949c, 0xffffffff, 0x100, |
0x9490, 0xffffffff, 0x3, |
0x949c, 0xffffffff, 0x100, |
0x9490, 0xffffffff, 0x4, |
0x949c, 0xffffffff, 0x100, |
0x9490, 0xffffffff, 0x5, |
0x949c, 0xffffffff, 0x100, |
0x9490, 0xffffffff, 0x6, |
0x949c, 0xffffffff, 0x100, |
0x9490, 0xffffffff, 0x7, |
0x949c, 0xffffffff, 0x100, |
0x9490, 0xffffffff, 0x8000, |
0x9604, 0xffffffff, 0x0, |
0x9654, 0xffffffff, 0x100, |
0x9604, 0xffffffff, 0x1, |
0x9654, 0xffffffff, 0x100, |
0x9604, 0xffffffff, 0x2, |
0x9654, 0xffffffff, 0x100, |
0x9604, 0xffffffff, 0x3, |
0x9654, 0xffffffff, 0x100, |
0x9604, 0xffffffff, 0x4, |
0x9654, 0xffffffff, 0x100, |
0x9604, 0xffffffff, 0x5, |
0x9654, 0xffffffff, 0x100, |
0x9604, 0xffffffff, 0x6, |
0x9654, 0xffffffff, 0x100, |
0x9604, 0xffffffff, 0x7, |
0x9654, 0xffffffff, 0x100, |
0x9604, 0xffffffff, 0x80000000, |
0x9030, 0xffffffff, 0x100, |
0x9034, 0xffffffff, 0x100, |
0x9038, 0xffffffff, 0x100, |
0x903c, 0xffffffff, 0x100, |
0x9040, 0xffffffff, 0x100, |
0xa200, 0xffffffff, 0x100, |
0xa204, 0xffffffff, 0x100, |
0xa208, 0xffffffff, 0x100, |
0xa20c, 0xffffffff, 0x100, |
0x971c, 0xffffffff, 0x100, |
0x915c, 0xffffffff, 0x00020001, |
0x9160, 0xffffffff, 0x00040003, |
0x916c, 0xffffffff, 0x00060005, |
0x9170, 0xffffffff, 0x00080007, |
0x9174, 0xffffffff, 0x000a0009, |
0x9178, 0xffffffff, 0x000c000b, |
0x917c, 0xffffffff, 0x000e000d, |
0x9180, 0xffffffff, 0x0010000f, |
0x918c, 0xffffffff, 0x00120011, |
0x9190, 0xffffffff, 0x00140013, |
0x9194, 0xffffffff, 0x00020001, |
0x9198, 0xffffffff, 0x00040003, |
0x919c, 0xffffffff, 0x00060005, |
0x91a8, 0xffffffff, 0x00080007, |
0x91ac, 0xffffffff, 0x000a0009, |
0x91b0, 0xffffffff, 0x000c000b, |
0x91b4, 0xffffffff, 0x000e000d, |
0x91b8, 0xffffffff, 0x0010000f, |
0x91c4, 0xffffffff, 0x00120011, |
0x91c8, 0xffffffff, 0x00140013, |
0x91cc, 0xffffffff, 0x00020001, |
0x91d0, 0xffffffff, 0x00040003, |
0x91d4, 0xffffffff, 0x00060005, |
0x91e0, 0xffffffff, 0x00080007, |
0x91e4, 0xffffffff, 0x000a0009, |
0x91e8, 0xffffffff, 0x000c000b, |
0x91ec, 0xffffffff, 0x00020001, |
0x91f0, 0xffffffff, 0x00040003, |
0x91f4, 0xffffffff, 0x00060005, |
0x9200, 0xffffffff, 0x00080007, |
0x9204, 0xffffffff, 0x000a0009, |
0x9208, 0xffffffff, 0x000c000b, |
0x920c, 0xffffffff, 0x000e000d, |
0x9210, 0xffffffff, 0x0010000f, |
0x921c, 0xffffffff, 0x00120011, |
0x9220, 0xffffffff, 0x00140013, |
0x9224, 0xffffffff, 0x00020001, |
0x9228, 0xffffffff, 0x00040003, |
0x922c, 0xffffffff, 0x00060005, |
0x9238, 0xffffffff, 0x00080007, |
0x923c, 0xffffffff, 0x000a0009, |
0x9240, 0xffffffff, 0x000c000b, |
0x9244, 0xffffffff, 0x000e000d, |
0x9248, 0xffffffff, 0x0010000f, |
0x9254, 0xffffffff, 0x00120011, |
0x9258, 0xffffffff, 0x00140013, |
0x9294, 0xffffffff, 0x00020001, |
0x929c, 0xffffffff, 0x00040003, |
0x92a0, 0xffffffff, 0x00060005, |
0x92a4, 0xffffffff, 0x00080007 |
}; |
|
static void rv770_init_golden_registers(struct radeon_device *rdev) |
{ |
switch (rdev->family) { |
case CHIP_RV770: |
radeon_program_register_sequence(rdev, |
r7xx_golden_registers, |
(const u32)ARRAY_SIZE(r7xx_golden_registers)); |
radeon_program_register_sequence(rdev, |
r7xx_golden_dyn_gpr_registers, |
(const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers)); |
if (rdev->pdev->device == 0x994e) |
radeon_program_register_sequence(rdev, |
rv770ce_golden_registers, |
(const u32)ARRAY_SIZE(rv770ce_golden_registers)); |
else |
radeon_program_register_sequence(rdev, |
rv770_golden_registers, |
(const u32)ARRAY_SIZE(rv770_golden_registers)); |
radeon_program_register_sequence(rdev, |
rv770_mgcg_init, |
(const u32)ARRAY_SIZE(rv770_mgcg_init)); |
break; |
case CHIP_RV730: |
radeon_program_register_sequence(rdev, |
r7xx_golden_registers, |
(const u32)ARRAY_SIZE(r7xx_golden_registers)); |
radeon_program_register_sequence(rdev, |
r7xx_golden_dyn_gpr_registers, |
(const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers)); |
radeon_program_register_sequence(rdev, |
rv730_golden_registers, |
(const u32)ARRAY_SIZE(rv770_golden_registers)); |
radeon_program_register_sequence(rdev, |
rv730_mgcg_init, |
(const u32)ARRAY_SIZE(rv770_mgcg_init)); |
break; |
case CHIP_RV710: |
radeon_program_register_sequence(rdev, |
r7xx_golden_registers, |
(const u32)ARRAY_SIZE(r7xx_golden_registers)); |
radeon_program_register_sequence(rdev, |
r7xx_golden_dyn_gpr_registers, |
(const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers)); |
radeon_program_register_sequence(rdev, |
rv710_golden_registers, |
(const u32)ARRAY_SIZE(rv770_golden_registers)); |
radeon_program_register_sequence(rdev, |
rv710_mgcg_init, |
(const u32)ARRAY_SIZE(rv770_mgcg_init)); |
break; |
case CHIP_RV740: |
radeon_program_register_sequence(rdev, |
rv740_golden_registers, |
(const u32)ARRAY_SIZE(rv770_golden_registers)); |
radeon_program_register_sequence(rdev, |
rv740_mgcg_init, |
(const u32)ARRAY_SIZE(rv770_mgcg_init)); |
break; |
default: |
break; |
} |
} |
|
#define PCIE_BUS_CLK 10000 |
#define TCLK (PCIE_BUS_CLK / 10) |
|
/** |
* rv770_get_xclk - get the xclk |
* |
* @rdev: radeon_device pointer |
* |
* Returns the reference clock used by the gfx engine |
* (r7xx-cayman). |
*/ |
u32 rv770_get_xclk(struct radeon_device *rdev) |
{ |
u32 reference_clock = rdev->clock.spll.reference_freq; |
u32 tmp = RREG32(CG_CLKPIN_CNTL); |
|
if (tmp & MUX_TCLK_TO_XCLK) |
return TCLK; |
|
if (tmp & XTALIN_DIVIDE) |
return reference_clock / 4; |
|
return reference_clock; |
} |
|
u32 rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) |
{ |
struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; |
u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset); |
int i; |
|
/* Lock the graphics update lock */ |
tmp |= AVIVO_D1GRPH_UPDATE_LOCK; |
WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); |
|
/* update the scanout addresses */ |
if (radeon_crtc->crtc_id) { |
WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); |
WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); |
} else { |
WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); |
WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); |
} |
WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, |
(u32)crtc_base); |
WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, |
(u32)crtc_base); |
|
/* Wait for update_pending to go high. */ |
for (i = 0; i < rdev->usec_timeout; i++) { |
if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) |
break; |
udelay(1); |
} |
DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); |
|
/* Unlock the lock, so double-buffering can take place inside vblank */ |
tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK; |
WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); |
|
/* Return current update_pending status: */ |
return RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING; |
} |
|
/* get temperature in millidegrees */ |
int rv770_get_temp(struct radeon_device *rdev) |
{ |
u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >> |
ASIC_T_SHIFT; |
int actual_temp; |
|
if (temp & 0x400) |
actual_temp = -256; |
else if (temp & 0x200) |
actual_temp = 255; |
else if (temp & 0x100) { |
actual_temp = temp & 0x1ff; |
actual_temp |= ~0x1ff; |
} else |
actual_temp = temp & 0xff; |
|
return (actual_temp * 1000) / 2; |
} |
|
void rv770_pm_misc(struct radeon_device *rdev) |
{ |
int req_ps_idx = rdev->pm.requested_power_state_index; |
int req_cm_idx = rdev->pm.requested_clock_mode_index; |
struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx]; |
struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; |
|
if ((voltage->type == VOLTAGE_SW) && voltage->voltage) { |
/* 0xff01 is a flag rather then an actual voltage */ |
if (voltage->voltage == 0xff01) |
return; |
if (voltage->voltage != rdev->pm.current_vddc) { |
radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); |
rdev->pm.current_vddc = voltage->voltage; |
DRM_DEBUG("Setting: v: %d\n", voltage->voltage); |
} |
} |
} |
|
/* |
* GART |
*/ |
502,6 → 1337,11 |
WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); |
WREG32(DMA_TILING_CONFIG, (gb_tiling_config & 0xffff)); |
WREG32(DMA_TILING_CONFIG2, (gb_tiling_config & 0xffff)); |
if (rdev->family == CHIP_RV730) { |
WREG32(UVD_UDEC_DB_TILING_CONFIG, (gb_tiling_config & 0xffff)); |
WREG32(UVD_UDEC_DBW_TILING_CONFIG, (gb_tiling_config & 0xffff)); |
WREG32(UVD_UDEC_TILING_CONFIG, (gb_tiling_config & 0xffff)); |
} |
|
WREG32(CGTS_SYS_TCC_DISABLE, 0); |
WREG32(CGTS_TCC_DISABLE, 0); |
731,7 → 1571,7 |
} |
if (rdev->flags & RADEON_IS_AGP) { |
size_bf = mc->gtt_start; |
size_af = 0xFFFFFFFF - mc->gtt_end; |
size_af = mc->mc_mask - mc->gtt_end; |
if (size_bf > size_af) { |
if (mc->mc_vram_size > size_bf) { |
dev_warn(rdev->dev, "limiting VRAM\n"); |
803,6 → 1643,80 |
return 0; |
} |
|
/** |
* rv770_copy_dma - copy pages using the DMA engine |
* |
* @rdev: radeon_device pointer |
* @src_offset: src GPU address |
* @dst_offset: dst GPU address |
* @num_gpu_pages: number of GPU pages to xfer |
* @fence: radeon fence object |
* |
* Copy GPU paging using the DMA engine (r7xx). |
* Used by the radeon ttm implementation to move pages if |
* registered as the asic copy callback. |
*/ |
int rv770_copy_dma(struct radeon_device *rdev, |
uint64_t src_offset, uint64_t dst_offset, |
unsigned num_gpu_pages, |
struct radeon_fence **fence) |
{ |
struct radeon_semaphore *sem = NULL; |
int ring_index = rdev->asic->copy.dma_ring_index; |
struct radeon_ring *ring = &rdev->ring[ring_index]; |
u32 size_in_dw, cur_size_in_dw; |
int i, num_loops; |
int r = 0; |
|
r = radeon_semaphore_create(rdev, &sem); |
if (r) { |
DRM_ERROR("radeon: moving bo (%d).\n", r); |
return r; |
} |
|
size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4; |
num_loops = DIV_ROUND_UP(size_in_dw, 0xFFFF); |
r = radeon_ring_lock(rdev, ring, num_loops * 5 + 8); |
if (r) { |
DRM_ERROR("radeon: moving bo (%d).\n", r); |
radeon_semaphore_free(rdev, &sem, NULL); |
return r; |
} |
|
if (radeon_fence_need_sync(*fence, ring->idx)) { |
radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring, |
ring->idx); |
radeon_fence_note_sync(*fence, ring->idx); |
} else { |
radeon_semaphore_free(rdev, &sem, NULL); |
} |
|
for (i = 0; i < num_loops; i++) { |
cur_size_in_dw = size_in_dw; |
if (cur_size_in_dw > 0xFFFF) |
cur_size_in_dw = 0xFFFF; |
size_in_dw -= cur_size_in_dw; |
radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw)); |
radeon_ring_write(ring, dst_offset & 0xfffffffc); |
radeon_ring_write(ring, src_offset & 0xfffffffc); |
radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); |
radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff); |
src_offset += cur_size_in_dw * 4; |
dst_offset += cur_size_in_dw * 4; |
} |
|
r = radeon_fence_emit(rdev, fence, ring->idx); |
if (r) { |
radeon_ring_unlock_undo(rdev, ring); |
return r; |
} |
|
radeon_ring_unlock_commit(rdev, ring); |
radeon_semaphore_free(rdev, &sem, *fence); |
|
return r; |
} |
|
static int rv770_startup(struct radeon_device *rdev) |
{ |
struct radeon_ring *ring; |
840,13 → 1754,6 |
dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); |
} |
|
// r = r600_video_init(rdev); |
// if (r) { |
// r600_video_fini(rdev); |
// rdev->asic->copy = NULL; |
// dev_warn(rdev->dev, "failed video blitter (%d) falling back to memcpy\n", r); |
// } |
|
/* allocate wb buffer */ |
r = radeon_wb_init(rdev); |
if (r) |
864,7 → 1771,24 |
return r; |
} |
|
// r = rv770_uvd_resume(rdev); |
// if (!r) { |
// r = radeon_fence_driver_start_ring(rdev, |
// R600_RING_TYPE_UVD_INDEX); |
// if (r) |
// dev_err(rdev->dev, "UVD fences init error (%d).\n", r); |
// } |
|
// if (r) |
// rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0; |
|
/* Enable IRQ */ |
if (!rdev->irq.installed) { |
r = radeon_irq_kms_init(rdev); |
if (r) |
return r; |
} |
|
r = r600_irq_init(rdev); |
if (r) { |
DRM_ERROR("radeon: IH init failed (%d).\n", r); |
898,6 → 1822,19 |
if (r) |
return r; |
|
// ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; |
// if (ring->ring_size) { |
// r = radeon_ring_init(rdev, ring, ring->ring_size, |
// R600_WB_UVD_RPTR_OFFSET, |
// UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR, |
// 0, 0xfffff, RADEON_CP_PACKET2); |
// if (!r) |
// r = r600_uvd_init(rdev); |
|
// if (r) |
// DRM_ERROR("radeon: failed initializing UVD (%d).\n", r); |
// } |
|
r = radeon_ib_pool_init(rdev); |
if (r) { |
dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
946,6 → 1883,8 |
DRM_INFO("GPU not posted. posting now...\n"); |
atom_asic_init(rdev->mode_info.atom_context); |
} |
/* init golden registers */ |
rv770_init_golden_registers(rdev); |
/* Initialize scratch registers */ |
r600_scratch_init(rdev); |
/* Initialize surface registers */ |
970,10 → 1909,6 |
if (r) |
return r; |
|
r = radeon_irq_kms_init(rdev); |
if (r) |
return r; |
|
rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; |
r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); |
|
980,6 → 1915,13 |
rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL; |
r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024); |
|
// r = radeon_uvd_init(rdev); |
// if (!r) { |
// rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL; |
// r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], |
// 4096); |
// } |
|
rdev->ih.ring_obj = NULL; |
r600_ih_ring_init(rdev, 64 * 1024); |
|
1002,8 → 1944,6 |
{ |
u32 link_width_cntl, lanes, speed_cntl, tmp; |
u16 link_cntl2; |
u32 mask; |
int ret; |
|
if (radeon_pcie_gen2 == 0) |
return; |
1018,20 → 1958,17 |
if (ASIC_IS_X2(rdev)) |
return; |
|
ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); |
if (ret != 0) |
if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) && |
(rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT)) |
return; |
|
if (!(mask & DRM_PCIE_SPEED_50)) |
return; |
|
DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"); |
|
/* advertise upconfig capability */ |
link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); |
link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); |
link_width_cntl &= ~LC_UPCONFIGURE_DIS; |
WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); |
link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); |
WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); |
link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); |
if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) { |
lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; |
link_width_cntl &= ~(LC_LINK_WIDTH_MASK | |
1038,13 → 1975,13 |
LC_RECONFIG_ARC_MISSING_ESCAPE); |
link_width_cntl |= lanes | LC_RECONFIG_NOW | |
LC_RENEGOTIATE_EN | LC_UPCONFIGURE_SUPPORT; |
WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); |
WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); |
} else { |
link_width_cntl |= LC_UPCONFIGURE_DIS; |
WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); |
WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); |
} |
|
speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); |
speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); |
if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) && |
(speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { |
|
1057,29 → 1994,29 |
WREG16(0x4088, link_cntl2); |
WREG32(MM_CFGREGS_CNTL, 0); |
|
speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); |
speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); |
speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN; |
WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); |
WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); |
|
speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); |
speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); |
speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT; |
WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); |
WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); |
|
speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); |
speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); |
speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT; |
WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); |
WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); |
|
speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL); |
speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); |
speed_cntl |= LC_GEN2_EN_STRAP; |
WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl); |
WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); |
|
} else { |
link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL); |
link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); |
/* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */ |
if (1) |
link_width_cntl |= LC_UPCONFIGURE_DIS; |
else |
link_width_cntl &= ~LC_UPCONFIGURE_DIS; |
WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); |
WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); |
} |
} |