| 303,8 → 303,10 |
|---|
| tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); |
| if (!(tmp & AVIVO_CRTC_DISP_READ_REQUEST_DISABLE)) { |
| radeon_wait_for_vblank(rdev, i); |
| WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1); |
| tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; |
| WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); |
| WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0); |
| } |
| /* wait for the next frame */ |
| frame_count = radeon_get_vblank_counter(rdev, i); |
| 313,6 → 315,15 |
|---|
| break; |
| udelay(1); |
| } |
| |
| /* XXX this is a hack to avoid strange behavior with EFI on certain systems */ |
| WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1); |
| tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); |
| tmp &= ~AVIVO_CRTC_EN; |
| WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); |
| WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0); |
| save->crtc_enabled[i] = false; |
| /* ***** */ |
| } else { |
| save->crtc_enabled[i] = false; |
| } |
| 336,7 → 347,25 |
|---|
| WREG32(R600_CITF_CNTL, blackout); |
| } |
| } |
| /* wait for the MC to settle */ |
| udelay(100); |
| |
| /* lock double buffered regs */ |
| for (i = 0; i < rdev->num_crtc; i++) { |
| if (save->crtc_enabled[i]) { |
| tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); |
| if (!(tmp & AVIVO_D1GRPH_UPDATE_LOCK)) { |
| tmp |= AVIVO_D1GRPH_UPDATE_LOCK; |
| WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp); |
| } |
| tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]); |
| if (!(tmp & 1)) { |
| tmp |= 1; |
| WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); |
| } |
| } |
| } |
| } |
| |
| void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save) |
| { |
| 346,7 → 375,7 |
|---|
| /* update crtc base addresses */ |
| for (i = 0; i < rdev->num_crtc; i++) { |
| if (rdev->family >= CHIP_RV770) { |
| if (i == 1) { |
| if (i == 0) { |
| WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, |
| upper_32_bits(rdev->mc.vram_start)); |
| WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, |
| 365,6 → 394,33 |
|---|
| } |
| WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start); |
| |
| /* unlock regs and wait for update */ |
| for (i = 0; i < rdev->num_crtc; i++) { |
| if (save->crtc_enabled[i]) { |
| tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i]); |
| if ((tmp & 0x3) != 0) { |
| tmp &= ~0x3; |
| WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i], tmp); |
| } |
| tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); |
| if (tmp & AVIVO_D1GRPH_UPDATE_LOCK) { |
| tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK; |
| WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp); |
| } |
| tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]); |
| if (tmp & 1) { |
| tmp &= ~1; |
| WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); |
| } |
| for (j = 0; j < rdev->usec_timeout; j++) { |
| tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); |
| if ((tmp & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) == 0) |
| break; |
| udelay(1); |
| } |
| } |
| } |
| |
| if (rdev->family >= CHIP_R600) { |
| /* unblackout the MC */ |
| if (rdev->family >= CHIP_RV770) |
| 476,6 → 532,12 |
|---|
| } |
| |
| /* Enable IRQ */ |
| if (!rdev->irq.installed) { |
| r = radeon_irq_kms_init(rdev); |
| if (r) |
| return r; |
| } |
| |
| rs600_irq_set(rdev); |
| rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
| /* 1M ring buffer */ |
| 551,9 → 613,6 |
|---|
| r = radeon_fence_driver_init(rdev); |
| if (r) |
| return r; |
| r = radeon_irq_kms_init(rdev); |
| if (r) |
| return r; |
| /* Memory manager */ |
| r = radeon_bo_init(rdev); |
| if (r) |
| 568,11 → 627,6 |
|---|
| if (r) { |
| /* Somethings want wront with the accel init stop accel */ |
| dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
| // r100_cp_fini(rdev); |
| // r100_wb_fini(rdev); |
| // r100_ib_fini(rdev); |
| rv370_pcie_gart_fini(rdev); |
| // radeon_agp_fini(rdev); |
| rdev->accel_working = false; |
| } |
| return 0; |