142,8 → 142,6 |
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void rv515_vga_render_disable(struct radeon_device *rdev) |
{ |
WREG32(R_000330_D1VGA_CONTROL, 0); |
WREG32(R_000338_D2VGA_CONTROL, 0); |
WREG32(R_000300_VGA_RENDER_CONTROL, |
RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL); |
} |
391,7 → 389,6 |
save->d2crtc_control = RREG32(R_006880_D2CRTC_CONTROL); |
|
/* Stop all video */ |
WREG32(R_000330_D1VGA_CONTROL, 0); |
WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0); |
WREG32(R_000300_VGA_RENDER_CONTROL, 0); |
WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1); |
400,6 → 397,8 |
WREG32(R_006880_D2CRTC_CONTROL, 0); |
WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0); |
WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0); |
WREG32(R_000330_D1VGA_CONTROL, 0); |
WREG32(R_000338_D2VGA_CONTROL, 0); |
} |
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void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save) |
413,6 → 412,8 |
WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control); |
mdelay(1); |
/* Restore video state */ |
WREG32(R_000330_D1VGA_CONTROL, save->d1vga_control); |
WREG32(R_000338_D2VGA_CONTROL, save->d2vga_control); |
WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1); |
WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1); |
WREG32(R_006080_D1CRTC_CONTROL, save->d1crtc_control); |
419,8 → 420,6 |
WREG32(R_006880_D2CRTC_CONTROL, save->d2crtc_control); |
WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0); |
WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0); |
WREG32(R_000330_D1VGA_CONTROL, save->d1vga_control); |
WREG32(R_000338_D2VGA_CONTROL, save->d2vga_control); |
WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control); |
} |
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