| 52,19 → 52,60 |
|---|
| AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL |
| }; |
| |
| static bool avivo_is_in_vblank(struct radeon_device *rdev, int crtc) |
| { |
| if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK) |
| return true; |
| else |
| return false; |
| } |
| |
| static bool avivo_is_counter_moving(struct radeon_device *rdev, int crtc) |
| { |
| u32 pos1, pos2; |
| |
| pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); |
| pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); |
| |
| if (pos1 != pos2) |
| return true; |
| else |
| return false; |
| } |
| |
| /** |
| * avivo_wait_for_vblank - vblank wait asic callback. |
| * |
| * @rdev: radeon_device pointer |
| * @crtc: crtc to wait for vblank on |
| * |
| * Wait for vblank on the requested crtc (r5xx-r7xx). |
| */ |
| void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc) |
| { |
| int i; |
| unsigned i = 0; |
| |
| if (crtc >= rdev->num_crtc) |
| return; |
| |
| if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN) { |
| for (i = 0; i < rdev->usec_timeout; i++) { |
| if (!(RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK)) |
| if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN)) |
| return; |
| |
| /* depending on when we hit vblank, we may be close to active; if so, |
| * wait for another frame. |
| */ |
| while (avivo_is_in_vblank(rdev, crtc)) { |
| if (i++ % 100 == 0) { |
| if (!avivo_is_counter_moving(rdev, crtc)) |
| break; |
| udelay(1); |
| } |
| } |
| |
| while (!avivo_is_in_vblank(rdev, crtc)) { |
| if (i++ % 100 == 0) { |
| if (!avivo_is_counter_moving(rdev, crtc)) |
| break; |
| } |
| for (i = 0; i < rdev->usec_timeout; i++) { |
| if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK) |
| break; |
| 712,6 → 753,12 |
|---|
| } |
| |
| /* Enable IRQ */ |
| if (!rdev->irq.installed) { |
| r = radeon_irq_kms_init(rdev); |
| if (r) |
| return r; |
| } |
| |
| rs600_irq_set(rdev); |
| rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
| /* 1M ring buffer */ |
| 778,9 → 825,6 |
|---|
| r = radeon_fence_driver_init(rdev); |
| if (r) |
| return r; |
| r = radeon_irq_kms_init(rdev); |
| if (r) |
| return r; |
| /* Memory manager */ |
| r = radeon_bo_init(rdev); |
| if (r) |