65,7 → 65,18 |
|
void radeon_pm_acpi_event_handler(struct radeon_device *rdev) |
{ |
if (rdev->pm.pm_method == PM_METHOD_PROFILE) { |
if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { |
mutex_lock(&rdev->pm.mutex); |
if (power_supply_is_system_supplied() > 0) |
rdev->pm.dpm.ac_power = true; |
else |
rdev->pm.dpm.ac_power = false; |
if (rdev->family == CHIP_ARUBA) { |
if (rdev->asic->dpm.enable_bapm) |
radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power); |
} |
mutex_unlock(&rdev->pm.mutex); |
} else if (rdev->pm.pm_method == PM_METHOD_PROFILE) { |
if (rdev->pm.profile == PM_PROFILE_AUTO) { |
mutex_lock(&rdev->pm.mutex); |
radeon_pm_update_profile(rdev); |
134,7 → 145,11 |
if (list_empty(&rdev->gem.objects)) |
return; |
|
list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) { |
if (bo->tbo.mem.mem_type == TTM_PL_VRAM) |
ttm_bo_unmap_virtual(&bo->tbo); |
} |
} |
|
static void radeon_sync_with_vblank(struct radeon_device *rdev) |
{ |
245,7 → 260,7 |
if (!ring->ready) { |
continue; |
} |
r = radeon_fence_wait_empty_locked(rdev, i); |
r = radeon_fence_wait_empty(rdev, i); |
if (r) { |
/* needs a GPU reset dont reset here */ |
mutex_unlock(&rdev->ring_lock); |
327,7 → 342,7 |
struct device_attribute *attr, |
char *buf) |
{ |
struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev)); |
struct drm_device *ddev = dev_get_drvdata(dev); |
struct radeon_device *rdev = ddev->dev_private; |
int cp = rdev->pm.profile; |
|
343,9 → 358,14 |
const char *buf, |
size_t count) |
{ |
struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev)); |
struct drm_device *ddev = dev_get_drvdata(dev); |
struct radeon_device *rdev = ddev->dev_private; |
|
/* Can't set profile when the card is off */ |
if ((rdev->flags & RADEON_IS_PX) && |
(ddev->switch_power_state != DRM_SWITCH_POWER_ON)) |
return -EINVAL; |
|
mutex_lock(&rdev->pm.mutex); |
if (rdev->pm.pm_method == PM_METHOD_PROFILE) { |
if (strncmp("default", buf, strlen("default")) == 0) |
377,12 → 397,13 |
struct device_attribute *attr, |
char *buf) |
{ |
struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev)); |
struct drm_device *ddev = dev_get_drvdata(dev); |
struct radeon_device *rdev = ddev->dev_private; |
int pm = rdev->pm.pm_method; |
|
return snprintf(buf, PAGE_SIZE, "%s\n", |
(pm == PM_METHOD_DYNPM) ? "dynpm" : "profile"); |
(pm == PM_METHOD_DYNPM) ? "dynpm" : |
(pm == PM_METHOD_PROFILE) ? "profile" : "dpm"); |
} |
|
static ssize_t radeon_set_pm_method(struct device *dev, |
390,10 → 411,22 |
const char *buf, |
size_t count) |
{ |
struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev)); |
struct drm_device *ddev = dev_get_drvdata(dev); |
struct radeon_device *rdev = ddev->dev_private; |
|
/* Can't set method when the card is off */ |
if ((rdev->flags & RADEON_IS_PX) && |
(ddev->switch_power_state != DRM_SWITCH_POWER_ON)) { |
count = -EINVAL; |
goto fail; |
} |
|
/* we don't support the legacy modes with dpm */ |
if (rdev->pm.pm_method == PM_METHOD_DPM) { |
count = -EINVAL; |
goto fail; |
} |
|
if (strncmp("dynpm", buf, strlen("dynpm")) == 0) { |
mutex_lock(&rdev->pm.mutex); |
rdev->pm.pm_method = PM_METHOD_DYNPM; |
417,65 → 450,542 |
return count; |
} |
|
//static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile); |
//static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method); |
static ssize_t radeon_get_dpm_state(struct device *dev, |
struct device_attribute *attr, |
char *buf) |
{ |
struct drm_device *ddev = dev_get_drvdata(dev); |
struct radeon_device *rdev = ddev->dev_private; |
enum radeon_pm_state_type pm = rdev->pm.dpm.user_state; |
|
return snprintf(buf, PAGE_SIZE, "%s\n", |
(pm == POWER_STATE_TYPE_BATTERY) ? "battery" : |
(pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance"); |
} |
|
static ssize_t radeon_set_dpm_state(struct device *dev, |
struct device_attribute *attr, |
const char *buf, |
size_t count) |
{ |
struct drm_device *ddev = dev_get_drvdata(dev); |
struct radeon_device *rdev = ddev->dev_private; |
|
mutex_lock(&rdev->pm.mutex); |
if (strncmp("battery", buf, strlen("battery")) == 0) |
rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY; |
else if (strncmp("balanced", buf, strlen("balanced")) == 0) |
rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; |
else if (strncmp("performance", buf, strlen("performance")) == 0) |
rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE; |
else { |
mutex_unlock(&rdev->pm.mutex); |
count = -EINVAL; |
goto fail; |
} |
mutex_unlock(&rdev->pm.mutex); |
|
/* Can't set dpm state when the card is off */ |
if (!(rdev->flags & RADEON_IS_PX) || |
(ddev->switch_power_state == DRM_SWITCH_POWER_ON)) |
radeon_pm_compute_clocks(rdev); |
|
fail: |
return count; |
} |
|
static ssize_t radeon_get_dpm_forced_performance_level(struct device *dev, |
struct device_attribute *attr, |
char *buf) |
{ |
struct drm_device *ddev = dev_get_drvdata(dev); |
struct radeon_device *rdev = ddev->dev_private; |
enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level; |
|
if ((rdev->flags & RADEON_IS_PX) && |
(ddev->switch_power_state != DRM_SWITCH_POWER_ON)) |
return snprintf(buf, PAGE_SIZE, "off\n"); |
|
return snprintf(buf, PAGE_SIZE, "%s\n", |
(level == RADEON_DPM_FORCED_LEVEL_AUTO) ? "auto" : |
(level == RADEON_DPM_FORCED_LEVEL_LOW) ? "low" : "high"); |
} |
|
static ssize_t radeon_set_dpm_forced_performance_level(struct device *dev, |
struct device_attribute *attr, |
const char *buf, |
size_t count) |
{ |
struct drm_device *ddev = dev_get_drvdata(dev); |
struct radeon_device *rdev = ddev->dev_private; |
enum radeon_dpm_forced_level level; |
int ret = 0; |
|
/* Can't force performance level when the card is off */ |
if ((rdev->flags & RADEON_IS_PX) && |
(ddev->switch_power_state != DRM_SWITCH_POWER_ON)) |
return -EINVAL; |
|
mutex_lock(&rdev->pm.mutex); |
if (strncmp("low", buf, strlen("low")) == 0) { |
level = RADEON_DPM_FORCED_LEVEL_LOW; |
} else if (strncmp("high", buf, strlen("high")) == 0) { |
level = RADEON_DPM_FORCED_LEVEL_HIGH; |
} else if (strncmp("auto", buf, strlen("auto")) == 0) { |
level = RADEON_DPM_FORCED_LEVEL_AUTO; |
} else { |
count = -EINVAL; |
goto fail; |
} |
if (rdev->asic->dpm.force_performance_level) { |
if (rdev->pm.dpm.thermal_active) { |
count = -EINVAL; |
goto fail; |
} |
ret = radeon_dpm_force_performance_level(rdev, level); |
if (ret) |
count = -EINVAL; |
} |
fail: |
mutex_unlock(&rdev->pm.mutex); |
|
return count; |
} |
|
|
static ssize_t radeon_hwmon_show_temp(struct device *dev, |
struct device_attribute *attr, |
char *buf) |
{ |
struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev)); |
struct radeon_device *rdev = ddev->dev_private; |
struct radeon_device *rdev = dev_get_drvdata(dev); |
struct drm_device *ddev = rdev->ddev; |
int temp; |
|
/* Can't get temperature when the card is off */ |
if ((rdev->flags & RADEON_IS_PX) && |
(ddev->switch_power_state != DRM_SWITCH_POWER_ON)) |
return -EINVAL; |
|
if (rdev->asic->pm.get_temperature) |
temp = radeon_get_temperature(rdev); |
else |
temp = 0; |
|
return snprintf(buf, PAGE_SIZE, "%d\n", temp); |
} |
|
static ssize_t radeon_hwmon_show_temp_thresh(struct device *dev, |
struct device_attribute *attr, |
char *buf) |
{ |
struct radeon_device *rdev = dev_get_drvdata(dev); |
// int hyst = to_sensor_dev_attr(attr)->index; |
int temp; |
|
// if (hyst) |
// temp = rdev->pm.dpm.thermal.min_temp; |
// else |
temp = rdev->pm.dpm.thermal.max_temp; |
|
return snprintf(buf, PAGE_SIZE, "%d\n", temp); |
} |
|
|
static struct attribute *hwmon_attributes[] = { |
// &sensor_dev_attr_temp1_input.dev_attr.attr, |
// &sensor_dev_attr_temp1_crit.dev_attr.attr, |
// &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr, |
NULL |
}; |
|
|
|
static int radeon_hwmon_init(struct radeon_device *rdev) |
{ |
int err = 0; |
|
switch (rdev->pm.int_thermal_type) { |
case THERMAL_TYPE_RV6XX: |
temp = rv6xx_get_temp(rdev); |
break; |
case THERMAL_TYPE_RV770: |
temp = rv770_get_temp(rdev); |
break; |
case THERMAL_TYPE_EVERGREEN: |
case THERMAL_TYPE_NI: |
temp = evergreen_get_temp(rdev); |
break; |
case THERMAL_TYPE_SUMO: |
temp = sumo_get_temp(rdev); |
break; |
case THERMAL_TYPE_SI: |
temp = si_get_temp(rdev); |
case THERMAL_TYPE_CI: |
case THERMAL_TYPE_KV: |
if (rdev->asic->pm.get_temperature == NULL) |
return err; |
|
break; |
default: |
temp = 0; |
break; |
} |
|
return snprintf(buf, PAGE_SIZE, "%d\n", temp); |
return err; |
} |
|
static ssize_t radeon_hwmon_show_name(struct device *dev, |
struct device_attribute *attr, |
char *buf) |
static void radeon_hwmon_fini(struct radeon_device *rdev) |
{ |
return sprintf(buf, "radeon\n"); |
// if (rdev->pm.int_hwmon_dev) |
// hwmon_device_unregister(rdev->pm.int_hwmon_dev); |
} |
|
static int radeon_hwmon_init(struct radeon_device *rdev) |
static void radeon_dpm_thermal_work_handler(struct work_struct *work) |
{ |
int err = 0; |
struct radeon_device *rdev = |
container_of(work, struct radeon_device, |
pm.dpm.thermal.work); |
/* switch to the thermal state */ |
enum radeon_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL; |
|
rdev->pm.int_hwmon_dev = NULL; |
if (!rdev->pm.dpm_enabled) |
return; |
|
return err; |
if (rdev->asic->pm.get_temperature) { |
int temp = radeon_get_temperature(rdev); |
|
if (temp < rdev->pm.dpm.thermal.min_temp) |
/* switch back the user state */ |
dpm_state = rdev->pm.dpm.user_state; |
} else { |
if (rdev->pm.dpm.thermal.high_to_low) |
/* switch back the user state */ |
dpm_state = rdev->pm.dpm.user_state; |
} |
mutex_lock(&rdev->pm.mutex); |
if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL) |
rdev->pm.dpm.thermal_active = true; |
else |
rdev->pm.dpm.thermal_active = false; |
rdev->pm.dpm.state = dpm_state; |
mutex_unlock(&rdev->pm.mutex); |
|
static void radeon_hwmon_fini(struct radeon_device *rdev) |
radeon_pm_compute_clocks(rdev); |
} |
|
static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev, |
enum radeon_pm_state_type dpm_state) |
{ |
int i; |
struct radeon_ps *ps; |
u32 ui_class; |
bool single_display = (rdev->pm.dpm.new_active_crtc_count < 2) ? |
true : false; |
|
/* check if the vblank period is too short to adjust the mclk */ |
if (single_display && rdev->asic->dpm.vblank_too_short) { |
if (radeon_dpm_vblank_too_short(rdev)) |
single_display = false; |
} |
|
void radeon_pm_suspend(struct radeon_device *rdev) |
/* certain older asics have a separare 3D performance state, |
* so try that first if the user selected performance |
*/ |
if (dpm_state == POWER_STATE_TYPE_PERFORMANCE) |
dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF; |
/* balanced states don't exist at the moment */ |
if (dpm_state == POWER_STATE_TYPE_BALANCED) |
dpm_state = POWER_STATE_TYPE_PERFORMANCE; |
|
restart_search: |
/* Pick the best power state based on current conditions */ |
for (i = 0; i < rdev->pm.dpm.num_ps; i++) { |
ps = &rdev->pm.dpm.ps[i]; |
ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK; |
switch (dpm_state) { |
/* user states */ |
case POWER_STATE_TYPE_BATTERY: |
if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) { |
if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) { |
if (single_display) |
return ps; |
} else |
return ps; |
} |
break; |
case POWER_STATE_TYPE_BALANCED: |
if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) { |
if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) { |
if (single_display) |
return ps; |
} else |
return ps; |
} |
break; |
case POWER_STATE_TYPE_PERFORMANCE: |
if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) { |
if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) { |
if (single_display) |
return ps; |
} else |
return ps; |
} |
break; |
/* internal states */ |
case POWER_STATE_TYPE_INTERNAL_UVD: |
if (rdev->pm.dpm.uvd_ps) |
return rdev->pm.dpm.uvd_ps; |
else |
break; |
case POWER_STATE_TYPE_INTERNAL_UVD_SD: |
if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE) |
return ps; |
break; |
case POWER_STATE_TYPE_INTERNAL_UVD_HD: |
if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE) |
return ps; |
break; |
case POWER_STATE_TYPE_INTERNAL_UVD_HD2: |
if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE) |
return ps; |
break; |
case POWER_STATE_TYPE_INTERNAL_UVD_MVC: |
if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC) |
return ps; |
break; |
case POWER_STATE_TYPE_INTERNAL_BOOT: |
return rdev->pm.dpm.boot_ps; |
case POWER_STATE_TYPE_INTERNAL_THERMAL: |
if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL) |
return ps; |
break; |
case POWER_STATE_TYPE_INTERNAL_ACPI: |
if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) |
return ps; |
break; |
case POWER_STATE_TYPE_INTERNAL_ULV: |
if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) |
return ps; |
break; |
case POWER_STATE_TYPE_INTERNAL_3DPERF: |
if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE) |
return ps; |
break; |
default: |
break; |
} |
} |
/* use a fallback state if we didn't match */ |
switch (dpm_state) { |
case POWER_STATE_TYPE_INTERNAL_UVD_SD: |
dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD; |
goto restart_search; |
case POWER_STATE_TYPE_INTERNAL_UVD_HD: |
case POWER_STATE_TYPE_INTERNAL_UVD_HD2: |
case POWER_STATE_TYPE_INTERNAL_UVD_MVC: |
if (rdev->pm.dpm.uvd_ps) { |
return rdev->pm.dpm.uvd_ps; |
} else { |
dpm_state = POWER_STATE_TYPE_PERFORMANCE; |
goto restart_search; |
} |
case POWER_STATE_TYPE_INTERNAL_THERMAL: |
dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI; |
goto restart_search; |
case POWER_STATE_TYPE_INTERNAL_ACPI: |
dpm_state = POWER_STATE_TYPE_BATTERY; |
goto restart_search; |
case POWER_STATE_TYPE_BATTERY: |
case POWER_STATE_TYPE_BALANCED: |
case POWER_STATE_TYPE_INTERNAL_3DPERF: |
dpm_state = POWER_STATE_TYPE_PERFORMANCE; |
goto restart_search; |
default: |
break; |
} |
|
return NULL; |
} |
|
static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev) |
{ |
int i; |
struct radeon_ps *ps; |
enum radeon_pm_state_type dpm_state; |
int ret; |
|
/* if dpm init failed */ |
if (!rdev->pm.dpm_enabled) |
return; |
|
if (rdev->pm.dpm.user_state != rdev->pm.dpm.state) { |
/* add other state override checks here */ |
if ((!rdev->pm.dpm.thermal_active) && |
(!rdev->pm.dpm.uvd_active)) |
rdev->pm.dpm.state = rdev->pm.dpm.user_state; |
} |
dpm_state = rdev->pm.dpm.state; |
|
ps = radeon_dpm_pick_power_state(rdev, dpm_state); |
if (ps) |
rdev->pm.dpm.requested_ps = ps; |
else |
return; |
|
/* no need to reprogram if nothing changed unless we are on BTC+ */ |
if (rdev->pm.dpm.current_ps == rdev->pm.dpm.requested_ps) { |
/* vce just modifies an existing state so force a change */ |
if (ps->vce_active != rdev->pm.dpm.vce_active) |
goto force; |
if ((rdev->family < CHIP_BARTS) || (rdev->flags & RADEON_IS_IGP)) { |
/* for pre-BTC and APUs if the num crtcs changed but state is the same, |
* all we need to do is update the display configuration. |
*/ |
if (rdev->pm.dpm.new_active_crtcs != rdev->pm.dpm.current_active_crtcs) { |
/* update display watermarks based on new power state */ |
radeon_bandwidth_update(rdev); |
/* update displays */ |
radeon_dpm_display_configuration_changed(rdev); |
rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs; |
rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count; |
} |
return; |
} else { |
/* for BTC+ if the num crtcs hasn't changed and state is the same, |
* nothing to do, if the num crtcs is > 1 and state is the same, |
* update display configuration. |
*/ |
if (rdev->pm.dpm.new_active_crtcs == |
rdev->pm.dpm.current_active_crtcs) { |
return; |
} else { |
if ((rdev->pm.dpm.current_active_crtc_count > 1) && |
(rdev->pm.dpm.new_active_crtc_count > 1)) { |
/* update display watermarks based on new power state */ |
radeon_bandwidth_update(rdev); |
/* update displays */ |
radeon_dpm_display_configuration_changed(rdev); |
rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs; |
rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count; |
return; |
} |
} |
} |
} |
|
force: |
if (radeon_dpm == 1) { |
printk("switching from power state:\n"); |
radeon_dpm_print_power_state(rdev, rdev->pm.dpm.current_ps); |
printk("switching to power state:\n"); |
radeon_dpm_print_power_state(rdev, rdev->pm.dpm.requested_ps); |
} |
|
mutex_lock(&rdev->ddev->struct_mutex); |
// down_write(&rdev->pm.mclk_lock); |
mutex_lock(&rdev->ring_lock); |
|
/* update whether vce is active */ |
ps->vce_active = rdev->pm.dpm.vce_active; |
|
ret = radeon_dpm_pre_set_power_state(rdev); |
if (ret) |
goto done; |
|
/* update display watermarks based on new power state */ |
radeon_bandwidth_update(rdev); |
/* update displays */ |
radeon_dpm_display_configuration_changed(rdev); |
|
rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs; |
rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count; |
|
/* wait for the rings to drain */ |
for (i = 0; i < RADEON_NUM_RINGS; i++) { |
struct radeon_ring *ring = &rdev->ring[i]; |
if (ring->ready) |
radeon_fence_wait_empty(rdev, i); |
} |
|
/* program the new power state */ |
radeon_dpm_set_power_state(rdev); |
|
/* update current power state */ |
rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps; |
|
radeon_dpm_post_set_power_state(rdev); |
|
if (rdev->asic->dpm.force_performance_level) { |
if (rdev->pm.dpm.thermal_active) { |
enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level; |
/* force low perf level for thermal */ |
radeon_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_LOW); |
/* save the user's level */ |
rdev->pm.dpm.forced_level = level; |
} else { |
/* otherwise, user selected level */ |
radeon_dpm_force_performance_level(rdev, rdev->pm.dpm.forced_level); |
} |
} |
|
done: |
mutex_unlock(&rdev->ring_lock); |
// up_write(&rdev->pm.mclk_lock); |
mutex_unlock(&rdev->ddev->struct_mutex); |
} |
|
void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable) |
{ |
enum radeon_pm_state_type dpm_state; |
|
if (rdev->asic->dpm.powergate_uvd) { |
mutex_lock(&rdev->pm.mutex); |
/* don't powergate anything if we |
have active but pause streams */ |
enable |= rdev->pm.dpm.sd > 0; |
enable |= rdev->pm.dpm.hd > 0; |
/* enable/disable UVD */ |
radeon_dpm_powergate_uvd(rdev, !enable); |
mutex_unlock(&rdev->pm.mutex); |
} else { |
if (enable) { |
mutex_lock(&rdev->pm.mutex); |
rdev->pm.dpm.uvd_active = true; |
/* disable this for now */ |
#if 0 |
if ((rdev->pm.dpm.sd == 1) && (rdev->pm.dpm.hd == 0)) |
dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_SD; |
else if ((rdev->pm.dpm.sd == 2) && (rdev->pm.dpm.hd == 0)) |
dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD; |
else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 1)) |
dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD; |
else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 2)) |
dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD2; |
else |
#endif |
dpm_state = POWER_STATE_TYPE_INTERNAL_UVD; |
rdev->pm.dpm.state = dpm_state; |
mutex_unlock(&rdev->pm.mutex); |
} else { |
mutex_lock(&rdev->pm.mutex); |
rdev->pm.dpm.uvd_active = false; |
mutex_unlock(&rdev->pm.mutex); |
} |
|
radeon_pm_compute_clocks(rdev); |
} |
} |
|
void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable) |
{ |
if (enable) { |
mutex_lock(&rdev->pm.mutex); |
rdev->pm.dpm.vce_active = true; |
/* XXX select vce level based on ring/task */ |
rdev->pm.dpm.vce_level = RADEON_VCE_LEVEL_AC_ALL; |
mutex_unlock(&rdev->pm.mutex); |
} else { |
mutex_lock(&rdev->pm.mutex); |
rdev->pm.dpm.vce_active = false; |
mutex_unlock(&rdev->pm.mutex); |
} |
|
radeon_pm_compute_clocks(rdev); |
} |
|
static void radeon_pm_suspend_old(struct radeon_device *rdev) |
{ |
mutex_lock(&rdev->pm.mutex); |
if (rdev->pm.pm_method == PM_METHOD_DYNPM) { |
if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) |
rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED; |
482,11 → 992,44 |
} |
mutex_unlock(&rdev->pm.mutex); |
|
// cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work); |
} |
|
void radeon_pm_resume(struct radeon_device *rdev) |
static void radeon_pm_suspend_dpm(struct radeon_device *rdev) |
{ |
mutex_lock(&rdev->pm.mutex); |
/* disable dpm */ |
radeon_dpm_disable(rdev); |
/* reset the power state */ |
rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps; |
rdev->pm.dpm_enabled = false; |
mutex_unlock(&rdev->pm.mutex); |
} |
|
void radeon_pm_suspend(struct radeon_device *rdev) |
{ |
if (rdev->pm.pm_method == PM_METHOD_DPM) |
radeon_pm_suspend_dpm(rdev); |
else |
radeon_pm_suspend_old(rdev); |
} |
|
static void radeon_pm_resume_old(struct radeon_device *rdev) |
{ |
/* set up the default clocks if the MC ucode is loaded */ |
if ((rdev->family >= CHIP_BARTS) && |
(rdev->family <= CHIP_CAYMAN) && |
rdev->mc_fw) { |
if (rdev->pm.default_vddc) |
radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, |
SET_VOLTAGE_TYPE_ASIC_VDDC); |
if (rdev->pm.default_vddci) |
radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, |
SET_VOLTAGE_TYPE_ASIC_VDDCI); |
if (rdev->pm.default_sclk) |
radeon_set_engine_clock(rdev, rdev->pm.default_sclk); |
if (rdev->pm.default_mclk) |
radeon_set_memory_clock(rdev, rdev->pm.default_mclk); |
} |
/* asic init will reset the default power state */ |
mutex_lock(&rdev->pm.mutex); |
rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; |
493,8 → 1036,10 |
rdev->pm.current_clock_mode_index = 0; |
rdev->pm.current_sclk = rdev->pm.default_sclk; |
rdev->pm.current_mclk = rdev->pm.default_mclk; |
if (rdev->pm.power_state) { |
rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage; |
rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci; |
} |
if (rdev->pm.pm_method == PM_METHOD_DYNPM |
&& rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) { |
rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; |
505,12 → 1050,51 |
radeon_pm_compute_clocks(rdev); |
} |
|
int radeon_pm_init(struct radeon_device *rdev) |
static void radeon_pm_resume_dpm(struct radeon_device *rdev) |
{ |
int ret; |
|
/* default to profile method */ |
rdev->pm.pm_method = PM_METHOD_PROFILE; |
/* asic init will reset to the boot state */ |
mutex_lock(&rdev->pm.mutex); |
rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps; |
radeon_dpm_setup_asic(rdev); |
ret = radeon_dpm_enable(rdev); |
mutex_unlock(&rdev->pm.mutex); |
if (ret) |
goto dpm_resume_fail; |
rdev->pm.dpm_enabled = true; |
return; |
|
dpm_resume_fail: |
DRM_ERROR("radeon: dpm resume failed\n"); |
if ((rdev->family >= CHIP_BARTS) && |
(rdev->family <= CHIP_CAYMAN) && |
rdev->mc_fw) { |
if (rdev->pm.default_vddc) |
radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, |
SET_VOLTAGE_TYPE_ASIC_VDDC); |
if (rdev->pm.default_vddci) |
radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, |
SET_VOLTAGE_TYPE_ASIC_VDDCI); |
if (rdev->pm.default_sclk) |
radeon_set_engine_clock(rdev, rdev->pm.default_sclk); |
if (rdev->pm.default_mclk) |
radeon_set_memory_clock(rdev, rdev->pm.default_mclk); |
} |
} |
|
void radeon_pm_resume(struct radeon_device *rdev) |
{ |
if (rdev->pm.pm_method == PM_METHOD_DPM) |
radeon_pm_resume_dpm(rdev); |
else |
radeon_pm_resume_old(rdev); |
} |
|
static int radeon_pm_init_old(struct radeon_device *rdev) |
{ |
int ret; |
|
rdev->pm.profile = PM_PROFILE_DEFAULT; |
rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; |
rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; |
529,7 → 1113,22 |
radeon_combios_get_power_modes(rdev); |
radeon_pm_print_states(rdev); |
radeon_pm_init_profile(rdev); |
/* set up the default clocks if the MC ucode is loaded */ |
if ((rdev->family >= CHIP_BARTS) && |
(rdev->family <= CHIP_CAYMAN) && |
rdev->mc_fw) { |
if (rdev->pm.default_vddc) |
radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, |
SET_VOLTAGE_TYPE_ASIC_VDDC); |
if (rdev->pm.default_vddci) |
radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, |
SET_VOLTAGE_TYPE_ASIC_VDDCI); |
if (rdev->pm.default_sclk) |
radeon_set_engine_clock(rdev, rdev->pm.default_sclk); |
if (rdev->pm.default_mclk) |
radeon_set_memory_clock(rdev, rdev->pm.default_mclk); |
} |
} |
|
/* set up the internal thermal sensor if applicable */ |
ret = radeon_hwmon_init(rdev); |
536,8 → 1135,12 |
if (ret) |
return ret; |
|
// INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler); |
|
if (rdev->pm.num_power_states > 1) { |
/* where's the best place to put these? */ |
|
|
DRM_INFO("radeon: power management initialized\n"); |
} |
|
544,8 → 1147,165 |
return 0; |
} |
|
void radeon_pm_fini(struct radeon_device *rdev) |
static void radeon_dpm_print_power_states(struct radeon_device *rdev) |
{ |
int i; |
|
for (i = 0; i < rdev->pm.dpm.num_ps; i++) { |
printk("== power state %d ==\n", i); |
radeon_dpm_print_power_state(rdev, &rdev->pm.dpm.ps[i]); |
} |
} |
|
static int radeon_pm_init_dpm(struct radeon_device *rdev) |
{ |
int ret; |
|
/* default to balanced state */ |
rdev->pm.dpm.state = POWER_STATE_TYPE_BALANCED; |
rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; |
rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO; |
rdev->pm.default_sclk = rdev->clock.default_sclk; |
rdev->pm.default_mclk = rdev->clock.default_mclk; |
rdev->pm.current_sclk = rdev->clock.default_sclk; |
rdev->pm.current_mclk = rdev->clock.default_mclk; |
rdev->pm.int_thermal_type = THERMAL_TYPE_NONE; |
|
if (rdev->bios && rdev->is_atom_bios) |
radeon_atombios_get_power_modes(rdev); |
else |
return -EINVAL; |
|
/* set up the internal thermal sensor if applicable */ |
ret = radeon_hwmon_init(rdev); |
if (ret) |
return ret; |
|
INIT_WORK(&rdev->pm.dpm.thermal.work, radeon_dpm_thermal_work_handler); |
mutex_lock(&rdev->pm.mutex); |
radeon_dpm_init(rdev); |
rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps; |
if (radeon_dpm == 1) |
radeon_dpm_print_power_states(rdev); |
radeon_dpm_setup_asic(rdev); |
ret = radeon_dpm_enable(rdev); |
mutex_unlock(&rdev->pm.mutex); |
if (ret) |
goto dpm_failed; |
rdev->pm.dpm_enabled = true; |
|
DRM_INFO("radeon: dpm initialized\n"); |
|
return 0; |
|
dpm_failed: |
rdev->pm.dpm_enabled = false; |
if ((rdev->family >= CHIP_BARTS) && |
(rdev->family <= CHIP_CAYMAN) && |
rdev->mc_fw) { |
if (rdev->pm.default_vddc) |
radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, |
SET_VOLTAGE_TYPE_ASIC_VDDC); |
if (rdev->pm.default_vddci) |
radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, |
SET_VOLTAGE_TYPE_ASIC_VDDCI); |
if (rdev->pm.default_sclk) |
radeon_set_engine_clock(rdev, rdev->pm.default_sclk); |
if (rdev->pm.default_mclk) |
radeon_set_memory_clock(rdev, rdev->pm.default_mclk); |
} |
DRM_ERROR("radeon: dpm initialization failed\n"); |
return ret; |
} |
|
int radeon_pm_init(struct radeon_device *rdev) |
{ |
/* enable dpm on rv6xx+ */ |
switch (rdev->family) { |
case CHIP_RV610: |
case CHIP_RV630: |
case CHIP_RV620: |
case CHIP_RV635: |
case CHIP_RV670: |
case CHIP_RS780: |
case CHIP_RS880: |
case CHIP_RV770: |
/* DPM requires the RLC, RV770+ dGPU requires SMC */ |
if (!rdev->rlc_fw) |
rdev->pm.pm_method = PM_METHOD_PROFILE; |
else if ((rdev->family >= CHIP_RV770) && |
(!(rdev->flags & RADEON_IS_IGP)) && |
(!rdev->smc_fw)) |
rdev->pm.pm_method = PM_METHOD_PROFILE; |
else if (radeon_dpm == 1) |
rdev->pm.pm_method = PM_METHOD_DPM; |
else |
rdev->pm.pm_method = PM_METHOD_PROFILE; |
break; |
case CHIP_RV730: |
case CHIP_RV710: |
case CHIP_RV740: |
case CHIP_CEDAR: |
case CHIP_REDWOOD: |
case CHIP_JUNIPER: |
case CHIP_CYPRESS: |
case CHIP_HEMLOCK: |
case CHIP_PALM: |
case CHIP_SUMO: |
case CHIP_SUMO2: |
case CHIP_BARTS: |
case CHIP_TURKS: |
case CHIP_CAICOS: |
case CHIP_CAYMAN: |
case CHIP_ARUBA: |
case CHIP_TAHITI: |
case CHIP_PITCAIRN: |
case CHIP_VERDE: |
case CHIP_OLAND: |
case CHIP_HAINAN: |
case CHIP_BONAIRE: |
case CHIP_KABINI: |
case CHIP_KAVERI: |
case CHIP_HAWAII: |
case CHIP_MULLINS: |
/* DPM requires the RLC, RV770+ dGPU requires SMC */ |
if (!rdev->rlc_fw) |
rdev->pm.pm_method = PM_METHOD_PROFILE; |
else if ((rdev->family >= CHIP_RV770) && |
(!(rdev->flags & RADEON_IS_IGP)) && |
(!rdev->smc_fw)) |
rdev->pm.pm_method = PM_METHOD_PROFILE; |
else if (radeon_dpm == 0) |
rdev->pm.pm_method = PM_METHOD_PROFILE; |
else |
rdev->pm.pm_method = PM_METHOD_DPM; |
break; |
default: |
/* default to profile method */ |
rdev->pm.pm_method = PM_METHOD_PROFILE; |
break; |
} |
|
if (rdev->pm.pm_method == PM_METHOD_DPM) |
return radeon_pm_init_dpm(rdev); |
else |
return radeon_pm_init_old(rdev); |
} |
|
int radeon_pm_late_init(struct radeon_device *rdev) |
{ |
int ret = 0; |
|
if (rdev->pm.pm_method == PM_METHOD_DPM) { |
mutex_lock(&rdev->pm.mutex); |
ret = radeon_dpm_late_enable(rdev); |
mutex_unlock(&rdev->pm.mutex); |
} |
return ret; |
} |
|
static void radeon_pm_fini_old(struct radeon_device *rdev) |
{ |
if (rdev->pm.num_power_states > 1) { |
mutex_lock(&rdev->pm.mutex); |
if (rdev->pm.pm_method == PM_METHOD_PROFILE) { |
565,10 → 1325,32 |
} |
|
radeon_hwmon_fini(rdev); |
kfree(rdev->pm.power_state); |
} |
|
void radeon_pm_compute_clocks(struct radeon_device *rdev) |
static void radeon_pm_fini_dpm(struct radeon_device *rdev) |
{ |
if (rdev->pm.num_power_states > 1) { |
mutex_lock(&rdev->pm.mutex); |
radeon_dpm_disable(rdev); |
mutex_unlock(&rdev->pm.mutex); |
} |
radeon_dpm_fini(rdev); |
|
radeon_hwmon_fini(rdev); |
kfree(rdev->pm.power_state); |
} |
|
void radeon_pm_fini(struct radeon_device *rdev) |
{ |
if (rdev->pm.pm_method == PM_METHOD_DPM) |
radeon_pm_fini_dpm(rdev); |
else |
radeon_pm_fini_old(rdev); |
} |
|
static void radeon_pm_compute_clocks_old(struct radeon_device *rdev) |
{ |
struct drm_device *ddev = rdev->ddev; |
struct drm_crtc *crtc; |
struct radeon_crtc *radeon_crtc; |
580,6 → 1362,7 |
|
rdev->pm.active_crtcs = 0; |
rdev->pm.active_crtc_count = 0; |
if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) { |
list_for_each_entry(crtc, |
&ddev->mode_config.crtc_list, head) { |
radeon_crtc = to_radeon_crtc(crtc); |
588,6 → 1371,7 |
rdev->pm.active_crtc_count++; |
} |
} |
} |
|
if (rdev->pm.pm_method == PM_METHOD_PROFILE) { |
radeon_pm_update_profile(rdev); |
638,6 → 1422,51 |
mutex_unlock(&rdev->pm.mutex); |
} |
|
static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev) |
{ |
struct drm_device *ddev = rdev->ddev; |
struct drm_crtc *crtc; |
struct radeon_crtc *radeon_crtc; |
|
if (!rdev->pm.dpm_enabled) |
return; |
|
mutex_lock(&rdev->pm.mutex); |
|
/* update active crtc counts */ |
rdev->pm.dpm.new_active_crtcs = 0; |
rdev->pm.dpm.new_active_crtc_count = 0; |
if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) { |
list_for_each_entry(crtc, |
&ddev->mode_config.crtc_list, head) { |
radeon_crtc = to_radeon_crtc(crtc); |
if (crtc->enabled) { |
rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id); |
rdev->pm.dpm.new_active_crtc_count++; |
} |
} |
} |
|
/* update battery/ac status */ |
if (power_supply_is_system_supplied() > 0) |
rdev->pm.dpm.ac_power = true; |
else |
rdev->pm.dpm.ac_power = false; |
|
radeon_dpm_change_power_state_locked(rdev); |
|
mutex_unlock(&rdev->pm.mutex); |
|
} |
|
void radeon_pm_compute_clocks(struct radeon_device *rdev) |
{ |
if (rdev->pm.pm_method == PM_METHOD_DPM) |
radeon_pm_compute_clocks_dpm(rdev); |
else |
radeon_pm_compute_clocks_old(rdev); |
} |
|
static bool radeon_pm_in_vbl(struct radeon_device *rdev) |
{ |
int crtc, vpos, hpos, vbl_status; |
648,7 → 1477,7 |
*/ |
for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) { |
if (rdev->pm.active_crtcs & (1 << crtc)) { |
vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, &vpos, &hpos); |
vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, 0, &vpos, &hpos, NULL, NULL); |
if ((vbl_status & DRM_SCANOUTPOS_VALID) && |
!(vbl_status & DRM_SCANOUTPOS_INVBL)) |
in_vbl = false; |
680,7 → 1509,19 |
struct drm_info_node *node = (struct drm_info_node *) m->private; |
struct drm_device *dev = node->minor->dev; |
struct radeon_device *rdev = dev->dev_private; |
struct drm_device *ddev = rdev->ddev; |
|
if ((rdev->flags & RADEON_IS_PX) && |
(ddev->switch_power_state != DRM_SWITCH_POWER_ON)) { |
seq_printf(m, "PX asic powered off\n"); |
} else if (rdev->pm.dpm_enabled) { |
mutex_lock(&rdev->pm.mutex); |
if (rdev->asic->dpm.debugfs_print_current_performance_level) |
radeon_dpm_debugfs_print_current_performance_level(rdev, m); |
else |
seq_printf(m, "Debugfs support not implemented for this asic\n"); |
mutex_unlock(&rdev->pm.mutex); |
} else { |
seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk); |
/* radeon_get_engine_clock is not reliable on APUs so just print the current clock */ |
if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP)) |
694,6 → 1535,7 |
seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc); |
if (rdev->asic->pm.get_pcie_lanes) |
seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev)); |
} |
|
return 0; |
} |