26,6 → 26,7 |
#include "drmP.h" |
#include "radeon_drm.h" |
#include "radeon.h" |
#include "atom.h" |
|
/** |
* radeon_ddc_probe |
59,7 → 60,7 |
} |
|
|
void radeon_i2c_do_lock(struct radeon_i2c_chan *i2c, int lock_state) |
static void radeon_i2c_do_lock(struct radeon_i2c_chan *i2c, int lock_state) |
{ |
struct radeon_device *rdev = i2c->dev->dev_private; |
struct radeon_i2c_bus_rec *rec = &i2c->rec; |
71,7 → 72,18 |
*/ |
if (rec->hw_capable) { |
if ((rdev->family >= CHIP_R200) && !ASIC_IS_AVIVO(rdev)) { |
if (rec->a_clk_reg == RADEON_GPIO_MONID) { |
u32 reg; |
|
if (rdev->family >= CHIP_RV350) |
reg = RADEON_GPIO_MONID; |
else if ((rdev->family == CHIP_R300) || |
(rdev->family == CHIP_R350)) |
reg = RADEON_GPIO_DVI_DDC; |
else |
reg = RADEON_GPIO_CRT2_DDC; |
|
mutex_lock(&rdev->dc_hw_i2c_mutex); |
if (rec->a_clk_reg == reg) { |
WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST | |
R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1))); |
} else { |
168,6 → 180,692 |
WREG32(rec->en_data_reg, val); |
} |
|
static u32 radeon_get_i2c_prescale(struct radeon_device *rdev) |
{ |
struct radeon_pll *spll = &rdev->clock.spll; |
u32 sclk = radeon_get_engine_clock(rdev); |
u32 prescale = 0; |
u32 n, m; |
u8 loop; |
int i2c_clock; |
|
switch (rdev->family) { |
case CHIP_R100: |
case CHIP_RV100: |
case CHIP_RS100: |
case CHIP_RV200: |
case CHIP_RS200: |
case CHIP_R200: |
case CHIP_RV250: |
case CHIP_RS300: |
case CHIP_RV280: |
case CHIP_R300: |
case CHIP_R350: |
case CHIP_RV350: |
n = (spll->reference_freq) / (4 * 6); |
for (loop = 1; loop < 255; loop++) { |
if ((loop * (loop - 1)) > n) |
break; |
} |
m = loop - 1; |
prescale = m | (loop << 8); |
break; |
case CHIP_RV380: |
case CHIP_RS400: |
case CHIP_RS480: |
case CHIP_R420: |
case CHIP_R423: |
case CHIP_RV410: |
sclk = radeon_get_engine_clock(rdev); |
prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128; |
break; |
case CHIP_RS600: |
case CHIP_RS690: |
case CHIP_RS740: |
/* todo */ |
break; |
case CHIP_RV515: |
case CHIP_R520: |
case CHIP_RV530: |
case CHIP_RV560: |
case CHIP_RV570: |
case CHIP_R580: |
i2c_clock = 50; |
sclk = radeon_get_engine_clock(rdev); |
if (rdev->family == CHIP_R520) |
prescale = (127 << 8) + ((sclk * 10) / (4 * 127 * i2c_clock)); |
else |
prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128; |
break; |
case CHIP_R600: |
case CHIP_RV610: |
case CHIP_RV630: |
case CHIP_RV670: |
/* todo */ |
break; |
case CHIP_RV620: |
case CHIP_RV635: |
case CHIP_RS780: |
case CHIP_RS880: |
case CHIP_RV770: |
case CHIP_RV730: |
case CHIP_RV710: |
case CHIP_RV740: |
/* todo */ |
break; |
case CHIP_CEDAR: |
case CHIP_REDWOOD: |
case CHIP_JUNIPER: |
case CHIP_CYPRESS: |
case CHIP_HEMLOCK: |
/* todo */ |
break; |
default: |
DRM_ERROR("i2c: unhandled radeon chip\n"); |
break; |
} |
return prescale; |
} |
|
|
/* hw i2c engine for r1xx-4xx hardware |
* hw can buffer up to 15 bytes |
*/ |
static int r100_hw_i2c_xfer(struct i2c_adapter *i2c_adap, |
struct i2c_msg *msgs, int num) |
{ |
struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); |
struct radeon_device *rdev = i2c->dev->dev_private; |
struct radeon_i2c_bus_rec *rec = &i2c->rec; |
struct i2c_msg *p; |
int i, j, k, ret = num; |
u32 prescale; |
u32 i2c_cntl_0, i2c_cntl_1, i2c_data; |
u32 tmp, reg; |
|
mutex_lock(&rdev->dc_hw_i2c_mutex); |
/* take the pm lock since we need a constant sclk */ |
mutex_lock(&rdev->pm.mutex); |
|
prescale = radeon_get_i2c_prescale(rdev); |
|
reg = ((prescale << RADEON_I2C_PRESCALE_SHIFT) | |
RADEON_I2C_START | |
RADEON_I2C_STOP | |
RADEON_I2C_GO); |
|
if (rdev->is_atom_bios) { |
tmp = RREG32(RADEON_BIOS_6_SCRATCH); |
WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE); |
} |
|
if (rec->mm_i2c) { |
i2c_cntl_0 = RADEON_I2C_CNTL_0; |
i2c_cntl_1 = RADEON_I2C_CNTL_1; |
i2c_data = RADEON_I2C_DATA; |
} else { |
i2c_cntl_0 = RADEON_DVI_I2C_CNTL_0; |
i2c_cntl_1 = RADEON_DVI_I2C_CNTL_1; |
i2c_data = RADEON_DVI_I2C_DATA; |
|
switch (rdev->family) { |
case CHIP_R100: |
case CHIP_RV100: |
case CHIP_RS100: |
case CHIP_RV200: |
case CHIP_RS200: |
case CHIP_RS300: |
switch (rec->mask_clk_reg) { |
case RADEON_GPIO_DVI_DDC: |
/* no gpio select bit */ |
break; |
default: |
DRM_ERROR("gpio not supported with hw i2c\n"); |
ret = -EINVAL; |
goto done; |
} |
break; |
case CHIP_R200: |
/* only bit 4 on r200 */ |
switch (rec->mask_clk_reg) { |
case RADEON_GPIO_DVI_DDC: |
reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); |
break; |
case RADEON_GPIO_MONID: |
reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); |
break; |
default: |
DRM_ERROR("gpio not supported with hw i2c\n"); |
ret = -EINVAL; |
goto done; |
} |
break; |
case CHIP_RV250: |
case CHIP_RV280: |
/* bits 3 and 4 */ |
switch (rec->mask_clk_reg) { |
case RADEON_GPIO_DVI_DDC: |
reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); |
break; |
case RADEON_GPIO_VGA_DDC: |
reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2); |
break; |
case RADEON_GPIO_CRT2_DDC: |
reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); |
break; |
default: |
DRM_ERROR("gpio not supported with hw i2c\n"); |
ret = -EINVAL; |
goto done; |
} |
break; |
case CHIP_R300: |
case CHIP_R350: |
/* only bit 4 on r300/r350 */ |
switch (rec->mask_clk_reg) { |
case RADEON_GPIO_VGA_DDC: |
reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); |
break; |
case RADEON_GPIO_DVI_DDC: |
reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); |
break; |
default: |
DRM_ERROR("gpio not supported with hw i2c\n"); |
ret = -EINVAL; |
goto done; |
} |
break; |
case CHIP_RV350: |
case CHIP_RV380: |
case CHIP_R420: |
case CHIP_R423: |
case CHIP_RV410: |
case CHIP_RS400: |
case CHIP_RS480: |
/* bits 3 and 4 */ |
switch (rec->mask_clk_reg) { |
case RADEON_GPIO_VGA_DDC: |
reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); |
break; |
case RADEON_GPIO_DVI_DDC: |
reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2); |
break; |
case RADEON_GPIO_MONID: |
reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); |
break; |
default: |
DRM_ERROR("gpio not supported with hw i2c\n"); |
ret = -EINVAL; |
goto done; |
} |
break; |
default: |
DRM_ERROR("unsupported asic\n"); |
ret = -EINVAL; |
goto done; |
break; |
} |
} |
|
/* check for bus probe */ |
p = &msgs[0]; |
if ((num == 1) && (p->len == 0)) { |
WREG32(i2c_cntl_0, (RADEON_I2C_DONE | |
RADEON_I2C_NACK | |
RADEON_I2C_HALT | |
RADEON_I2C_SOFT_RST)); |
WREG32(i2c_data, (p->addr << 1) & 0xff); |
WREG32(i2c_data, 0); |
WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | |
(1 << RADEON_I2C_ADDR_COUNT_SHIFT) | |
RADEON_I2C_EN | |
(48 << RADEON_I2C_TIME_LIMIT_SHIFT))); |
WREG32(i2c_cntl_0, reg); |
for (k = 0; k < 32; k++) { |
udelay(10); |
tmp = RREG32(i2c_cntl_0); |
if (tmp & RADEON_I2C_GO) |
continue; |
tmp = RREG32(i2c_cntl_0); |
if (tmp & RADEON_I2C_DONE) |
break; |
else { |
DRM_DEBUG("i2c write error 0x%08x\n", tmp); |
WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); |
ret = -EIO; |
goto done; |
} |
} |
goto done; |
} |
|
for (i = 0; i < num; i++) { |
p = &msgs[i]; |
for (j = 0; j < p->len; j++) { |
if (p->flags & I2C_M_RD) { |
WREG32(i2c_cntl_0, (RADEON_I2C_DONE | |
RADEON_I2C_NACK | |
RADEON_I2C_HALT | |
RADEON_I2C_SOFT_RST)); |
WREG32(i2c_data, ((p->addr << 1) & 0xff) | 0x1); |
WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | |
(1 << RADEON_I2C_ADDR_COUNT_SHIFT) | |
RADEON_I2C_EN | |
(48 << RADEON_I2C_TIME_LIMIT_SHIFT))); |
WREG32(i2c_cntl_0, reg | RADEON_I2C_RECEIVE); |
for (k = 0; k < 32; k++) { |
udelay(10); |
tmp = RREG32(i2c_cntl_0); |
if (tmp & RADEON_I2C_GO) |
continue; |
tmp = RREG32(i2c_cntl_0); |
if (tmp & RADEON_I2C_DONE) |
break; |
else { |
DRM_DEBUG("i2c read error 0x%08x\n", tmp); |
WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); |
ret = -EIO; |
goto done; |
} |
} |
p->buf[j] = RREG32(i2c_data) & 0xff; |
} else { |
WREG32(i2c_cntl_0, (RADEON_I2C_DONE | |
RADEON_I2C_NACK | |
RADEON_I2C_HALT | |
RADEON_I2C_SOFT_RST)); |
WREG32(i2c_data, (p->addr << 1) & 0xff); |
WREG32(i2c_data, p->buf[j]); |
WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | |
(1 << RADEON_I2C_ADDR_COUNT_SHIFT) | |
RADEON_I2C_EN | |
(48 << RADEON_I2C_TIME_LIMIT_SHIFT))); |
WREG32(i2c_cntl_0, reg); |
for (k = 0; k < 32; k++) { |
udelay(10); |
tmp = RREG32(i2c_cntl_0); |
if (tmp & RADEON_I2C_GO) |
continue; |
tmp = RREG32(i2c_cntl_0); |
if (tmp & RADEON_I2C_DONE) |
break; |
else { |
DRM_DEBUG("i2c write error 0x%08x\n", tmp); |
WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); |
ret = -EIO; |
goto done; |
} |
} |
} |
} |
} |
|
done: |
WREG32(i2c_cntl_0, 0); |
WREG32(i2c_cntl_1, 0); |
WREG32(i2c_cntl_0, (RADEON_I2C_DONE | |
RADEON_I2C_NACK | |
RADEON_I2C_HALT | |
RADEON_I2C_SOFT_RST)); |
|
if (rdev->is_atom_bios) { |
tmp = RREG32(RADEON_BIOS_6_SCRATCH); |
tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE; |
WREG32(RADEON_BIOS_6_SCRATCH, tmp); |
} |
|
mutex_unlock(&rdev->pm.mutex); |
mutex_unlock(&rdev->dc_hw_i2c_mutex); |
|
return ret; |
} |
|
/* hw i2c engine for r5xx hardware |
* hw can buffer up to 15 bytes |
*/ |
static int r500_hw_i2c_xfer(struct i2c_adapter *i2c_adap, |
struct i2c_msg *msgs, int num) |
{ |
struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); |
struct radeon_device *rdev = i2c->dev->dev_private; |
struct radeon_i2c_bus_rec *rec = &i2c->rec; |
struct i2c_msg *p; |
int i, j, remaining, current_count, buffer_offset, ret = num; |
u32 prescale; |
u32 tmp, reg; |
u32 saved1, saved2; |
|
mutex_lock(&rdev->dc_hw_i2c_mutex); |
/* take the pm lock since we need a constant sclk */ |
mutex_lock(&rdev->pm.mutex); |
|
prescale = radeon_get_i2c_prescale(rdev); |
|
/* clear gpio mask bits */ |
tmp = RREG32(rec->mask_clk_reg); |
tmp &= ~rec->mask_clk_mask; |
WREG32(rec->mask_clk_reg, tmp); |
tmp = RREG32(rec->mask_clk_reg); |
|
tmp = RREG32(rec->mask_data_reg); |
tmp &= ~rec->mask_data_mask; |
WREG32(rec->mask_data_reg, tmp); |
tmp = RREG32(rec->mask_data_reg); |
|
/* clear pin values */ |
tmp = RREG32(rec->a_clk_reg); |
tmp &= ~rec->a_clk_mask; |
WREG32(rec->a_clk_reg, tmp); |
tmp = RREG32(rec->a_clk_reg); |
|
tmp = RREG32(rec->a_data_reg); |
tmp &= ~rec->a_data_mask; |
WREG32(rec->a_data_reg, tmp); |
tmp = RREG32(rec->a_data_reg); |
|
/* set the pins to input */ |
tmp = RREG32(rec->en_clk_reg); |
tmp &= ~rec->en_clk_mask; |
WREG32(rec->en_clk_reg, tmp); |
tmp = RREG32(rec->en_clk_reg); |
|
tmp = RREG32(rec->en_data_reg); |
tmp &= ~rec->en_data_mask; |
WREG32(rec->en_data_reg, tmp); |
tmp = RREG32(rec->en_data_reg); |
|
/* */ |
tmp = RREG32(RADEON_BIOS_6_SCRATCH); |
WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE); |
saved1 = RREG32(AVIVO_DC_I2C_CONTROL1); |
saved2 = RREG32(0x494); |
WREG32(0x494, saved2 | 0x1); |
|
WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C); |
for (i = 0; i < 50; i++) { |
udelay(1); |
if (RREG32(AVIVO_DC_I2C_ARBITRATION) & AVIVO_DC_I2C_SW_CAN_USE_I2C) |
break; |
} |
if (i == 50) { |
DRM_ERROR("failed to get i2c bus\n"); |
ret = -EBUSY; |
goto done; |
} |
|
reg = AVIVO_DC_I2C_START | AVIVO_DC_I2C_STOP | AVIVO_DC_I2C_EN; |
switch (rec->mask_clk_reg) { |
case AVIVO_DC_GPIO_DDC1_MASK: |
reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC1); |
break; |
case AVIVO_DC_GPIO_DDC2_MASK: |
reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC2); |
break; |
case AVIVO_DC_GPIO_DDC3_MASK: |
reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC3); |
break; |
default: |
DRM_ERROR("gpio not supported with hw i2c\n"); |
ret = -EINVAL; |
goto done; |
} |
|
/* check for bus probe */ |
p = &msgs[0]; |
if ((num == 1) && (p->len == 0)) { |
WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | |
AVIVO_DC_I2C_NACK | |
AVIVO_DC_I2C_HALT)); |
WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); |
udelay(1); |
WREG32(AVIVO_DC_I2C_RESET, 0); |
|
WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff); |
WREG32(AVIVO_DC_I2C_DATA, 0); |
|
WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); |
WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | |
AVIVO_DC_I2C_DATA_COUNT(1) | |
(prescale << 16))); |
WREG32(AVIVO_DC_I2C_CONTROL1, reg); |
WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); |
for (j = 0; j < 200; j++) { |
udelay(50); |
tmp = RREG32(AVIVO_DC_I2C_STATUS1); |
if (tmp & AVIVO_DC_I2C_GO) |
continue; |
tmp = RREG32(AVIVO_DC_I2C_STATUS1); |
if (tmp & AVIVO_DC_I2C_DONE) |
break; |
else { |
DRM_DEBUG("i2c write error 0x%08x\n", tmp); |
WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); |
ret = -EIO; |
goto done; |
} |
} |
goto done; |
} |
|
for (i = 0; i < num; i++) { |
p = &msgs[i]; |
remaining = p->len; |
buffer_offset = 0; |
if (p->flags & I2C_M_RD) { |
while (remaining) { |
if (remaining > 15) |
current_count = 15; |
else |
current_count = remaining; |
WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | |
AVIVO_DC_I2C_NACK | |
AVIVO_DC_I2C_HALT)); |
WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); |
udelay(1); |
WREG32(AVIVO_DC_I2C_RESET, 0); |
|
WREG32(AVIVO_DC_I2C_DATA, ((p->addr << 1) & 0xff) | 0x1); |
WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); |
WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | |
AVIVO_DC_I2C_DATA_COUNT(current_count) | |
(prescale << 16))); |
WREG32(AVIVO_DC_I2C_CONTROL1, reg | AVIVO_DC_I2C_RECEIVE); |
WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); |
for (j = 0; j < 200; j++) { |
udelay(50); |
tmp = RREG32(AVIVO_DC_I2C_STATUS1); |
if (tmp & AVIVO_DC_I2C_GO) |
continue; |
tmp = RREG32(AVIVO_DC_I2C_STATUS1); |
if (tmp & AVIVO_DC_I2C_DONE) |
break; |
else { |
DRM_DEBUG("i2c read error 0x%08x\n", tmp); |
WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); |
ret = -EIO; |
goto done; |
} |
} |
for (j = 0; j < current_count; j++) |
p->buf[buffer_offset + j] = RREG32(AVIVO_DC_I2C_DATA) & 0xff; |
remaining -= current_count; |
buffer_offset += current_count; |
} |
} else { |
while (remaining) { |
if (remaining > 15) |
current_count = 15; |
else |
current_count = remaining; |
WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | |
AVIVO_DC_I2C_NACK | |
AVIVO_DC_I2C_HALT)); |
WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); |
udelay(1); |
WREG32(AVIVO_DC_I2C_RESET, 0); |
|
WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff); |
for (j = 0; j < current_count; j++) |
WREG32(AVIVO_DC_I2C_DATA, p->buf[buffer_offset + j]); |
|
WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); |
WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | |
AVIVO_DC_I2C_DATA_COUNT(current_count) | |
(prescale << 16))); |
WREG32(AVIVO_DC_I2C_CONTROL1, reg); |
WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); |
for (j = 0; j < 200; j++) { |
udelay(50); |
tmp = RREG32(AVIVO_DC_I2C_STATUS1); |
if (tmp & AVIVO_DC_I2C_GO) |
continue; |
tmp = RREG32(AVIVO_DC_I2C_STATUS1); |
if (tmp & AVIVO_DC_I2C_DONE) |
break; |
else { |
DRM_DEBUG("i2c write error 0x%08x\n", tmp); |
WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); |
ret = -EIO; |
goto done; |
} |
} |
remaining -= current_count; |
buffer_offset += current_count; |
} |
} |
} |
|
done: |
WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | |
AVIVO_DC_I2C_NACK | |
AVIVO_DC_I2C_HALT)); |
WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); |
udelay(1); |
WREG32(AVIVO_DC_I2C_RESET, 0); |
|
WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_DONE_USING_I2C); |
WREG32(AVIVO_DC_I2C_CONTROL1, saved1); |
WREG32(0x494, saved2); |
tmp = RREG32(RADEON_BIOS_6_SCRATCH); |
tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE; |
WREG32(RADEON_BIOS_6_SCRATCH, tmp); |
|
mutex_unlock(&rdev->pm.mutex); |
mutex_unlock(&rdev->dc_hw_i2c_mutex); |
|
return ret; |
} |
|
static int radeon_sw_i2c_xfer(struct i2c_adapter *i2c_adap, |
struct i2c_msg *msgs, int num) |
{ |
struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); |
int ret; |
|
radeon_i2c_do_lock(i2c, 1); |
ret = i2c_transfer(&i2c->algo.radeon.bit_adapter, msgs, num); |
radeon_i2c_do_lock(i2c, 0); |
|
return ret; |
} |
|
static int radeon_i2c_xfer(struct i2c_adapter *i2c_adap, |
struct i2c_msg *msgs, int num) |
{ |
struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); |
struct radeon_device *rdev = i2c->dev->dev_private; |
struct radeon_i2c_bus_rec *rec = &i2c->rec; |
int ret; |
|
switch (rdev->family) { |
case CHIP_R100: |
case CHIP_RV100: |
case CHIP_RS100: |
case CHIP_RV200: |
case CHIP_RS200: |
case CHIP_R200: |
case CHIP_RV250: |
case CHIP_RS300: |
case CHIP_RV280: |
case CHIP_R300: |
case CHIP_R350: |
case CHIP_RV350: |
case CHIP_RV380: |
case CHIP_R420: |
case CHIP_R423: |
case CHIP_RV410: |
case CHIP_RS400: |
case CHIP_RS480: |
if (rec->hw_capable) |
ret = r100_hw_i2c_xfer(i2c_adap, msgs, num); |
else |
ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num); |
break; |
case CHIP_RS600: |
case CHIP_RS690: |
case CHIP_RS740: |
/* XXX fill in hw i2c implementation */ |
ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num); |
break; |
case CHIP_RV515: |
case CHIP_R520: |
case CHIP_RV530: |
case CHIP_RV560: |
case CHIP_RV570: |
case CHIP_R580: |
if (rec->hw_capable) { |
if (rec->mm_i2c) |
ret = r100_hw_i2c_xfer(i2c_adap, msgs, num); |
else |
ret = r500_hw_i2c_xfer(i2c_adap, msgs, num); |
} else |
ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num); |
break; |
case CHIP_R600: |
case CHIP_RV610: |
case CHIP_RV630: |
case CHIP_RV670: |
/* XXX fill in hw i2c implementation */ |
ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num); |
break; |
case CHIP_RV620: |
case CHIP_RV635: |
case CHIP_RS780: |
case CHIP_RS880: |
case CHIP_RV770: |
case CHIP_RV730: |
case CHIP_RV710: |
case CHIP_RV740: |
/* XXX fill in hw i2c implementation */ |
ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num); |
break; |
case CHIP_CEDAR: |
case CHIP_REDWOOD: |
case CHIP_JUNIPER: |
case CHIP_CYPRESS: |
case CHIP_HEMLOCK: |
/* XXX fill in hw i2c implementation */ |
ret = radeon_sw_i2c_xfer(i2c_adap, msgs, num); |
break; |
default: |
DRM_ERROR("i2c: unhandled radeon chip\n"); |
ret = -EIO; |
break; |
} |
|
return ret; |
} |
|
static u32 radeon_i2c_func(struct i2c_adapter *adap) |
{ |
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; |
} |
|
static const struct i2c_algorithm radeon_i2c_algo = { |
.master_xfer = radeon_i2c_xfer, |
.functionality = radeon_i2c_func, |
}; |
|
struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, |
struct radeon_i2c_bus_rec *rec, |
const char *name) |
179,23 → 877,33 |
if (i2c == NULL) |
return NULL; |
|
i2c->dev = dev; |
i2c->adapter.algo_data = &i2c->algo.bit; |
i2c->algo.bit.setsda = set_data; |
i2c->algo.bit.setscl = set_clock; |
i2c->algo.bit.getsda = get_data; |
i2c->algo.bit.getscl = get_clock; |
i2c->algo.bit.udelay = 20; |
/* set the internal bit adapter */ |
// i2c->algo.radeon.bit_adapter.owner = THIS_MODULE; |
i2c_set_adapdata(&i2c->algo.radeon.bit_adapter, i2c); |
// sprintf(i2c->algo.radeon.bit_adapter.name, "Radeon internal i2c bit bus %s", name); |
i2c->algo.radeon.bit_adapter.algo_data = &i2c->algo.radeon.bit_data; |
i2c->algo.radeon.bit_data.setsda = set_data; |
i2c->algo.radeon.bit_data.setscl = set_clock; |
i2c->algo.radeon.bit_data.getsda = get_data; |
i2c->algo.radeon.bit_data.getscl = get_clock; |
i2c->algo.radeon.bit_data.udelay = 20; |
/* vesa says 2.2 ms is enough, 1 jiffy doesn't seem to always |
* make this, 2 jiffies is a lot more reliable */ |
i2c->algo.bit.timeout = 2; |
i2c->algo.bit.data = i2c; |
i2c->rec = *rec; |
ret = i2c_bit_add_bus(&i2c->adapter); |
i2c->algo.radeon.bit_data.timeout = 2; |
i2c->algo.radeon.bit_data.data = i2c; |
ret = i2c_bit_add_bus(&i2c->algo.radeon.bit_adapter); |
if (ret) { |
DRM_INFO("Failed to register i2c %s\n", name); |
DRM_ERROR("Failed to register internal bit i2c %s\n", name); |
goto out_free; |
} |
/* set the radeon i2c adapter */ |
i2c->dev = dev; |
i2c->rec = *rec; |
// i2c->adapter.owner = THIS_MODULE; |
i2c_set_adapdata(&i2c->adapter, i2c); |
// sprintf(i2c->adapter.name, "Radeon i2c %s", name); |
i2c->adapter.algo_data = &i2c->algo.radeon; |
i2c->adapter.algo = &radeon_i2c_algo; |
|
return i2c; |
out_free: |
218,6 → 926,7 |
i2c->rec = *rec; |
// i2c->adapter.owner = THIS_MODULE; |
i2c->dev = dev; |
i2c_set_adapdata(&i2c->adapter, i2c); |
i2c->adapter.algo_data = &i2c->algo.dp; |
i2c->algo.dp.aux_ch = radeon_dp_i2c_aux_ch; |
i2c->algo.dp.address = 0; |
234,12 → 943,18 |
|
} |
|
|
void radeon_i2c_destroy(struct radeon_i2c_chan *i2c) |
{ |
if (!i2c) |
return; |
kfree(i2c); |
} |
|
void radeon_i2c_destroy_dp(struct radeon_i2c_chan *i2c) |
{ |
if (!i2c) |
return; |
|
kfree(i2c); |
} |
|
248,7 → 963,7 |
return NULL; |
} |
|
void radeon_i2c_sw_get_byte(struct radeon_i2c_chan *i2c_bus, |
void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, |
u8 slave_addr, |
u8 addr, |
u8 *val) |
282,7 → 997,7 |
} |
} |
|
void radeon_i2c_sw_put_byte(struct radeon_i2c_chan *i2c_bus, |
void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c_bus, |
u8 slave_addr, |
u8 addr, |
u8 val) |