26,7 → 26,7 |
* Jerome Glisse |
*/ |
//#include <linux/console.h> |
|
#include <linux/slab.h> |
#include <drm/drmP.h> |
#include <drm/drm_crtc_helper.h> |
#include <drm/radeon_drm.h> |
55,7 → 55,9 |
int radeon_hw_i2c = 0; |
int radeon_pcie_gen2 = 0; |
int radeon_disp_priority = 0; |
int radeon_lockup_timeout = 10000; |
|
|
int irq_override = 0; |
|
|
65,7 → 67,7 |
int init_display(struct radeon_device *rdev, videomode_t *mode); |
int init_display_kms(struct radeon_device *rdev, videomode_t *mode); |
|
int get_modes(videomode_t *mode, int *count); |
int get_modes(videomode_t *mode, u32_t *count); |
int set_user_mode(videomode_t *mode); |
int r100_2D_test(struct radeon_device *rdev); |
|
132,11 → 134,19 |
"TURKS", |
"CAICOS", |
"CAYMAN", |
"ARUBA", |
"TAHITI", |
"PITCAIRN", |
"VERDE", |
"LAST", |
}; |
|
/* |
* Clear GPU surface registers. |
/** |
* radeon_surface_init - Clear GPU surface registers. |
* |
* @rdev: radeon_device pointer |
* |
* Clear GPU surface registers (r1xx-r5xx). |
*/ |
void radeon_surface_init(struct radeon_device *rdev) |
{ |
155,6 → 165,13 |
/* |
* GPU scratch registers helpers function. |
*/ |
/** |
* radeon_scratch_init - Init scratch register driver information. |
* |
* @rdev: radeon_device pointer |
* |
* Init CP scratch register driver information (r1xx-r5xx) |
*/ |
void radeon_scratch_init(struct radeon_device *rdev) |
{ |
int i; |
172,6 → 189,15 |
} |
} |
|
/** |
* radeon_scratch_get - Allocate a scratch register |
* |
* @rdev: radeon_device pointer |
* @reg: scratch register mmio offset |
* |
* Allocate a CP scratch register for use by the driver (all asics). |
* Returns 0 on success or -EINVAL on failure. |
*/ |
int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg) |
{ |
int i; |
186,6 → 212,14 |
return -EINVAL; |
} |
|
/** |
* radeon_scratch_free - Free a scratch register |
* |
* @rdev: radeon_device pointer |
* @reg: scratch register mmio offset |
* |
* Free a CP scratch register allocated for use by the driver (all asics) |
*/ |
void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg) |
{ |
int i; |
198,6 → 232,20 |
} |
} |
|
/* |
* radeon_wb_*() |
* Writeback is the the method by which the the GPU updates special pages |
* in memory with the status of certain GPU events (fences, ring pointers, |
* etc.). |
*/ |
|
/** |
* radeon_wb_disable - Disable Writeback |
* |
* @rdev: radeon_device pointer |
* |
* Disables Writeback (all asics). Used for suspend. |
*/ |
void radeon_wb_disable(struct radeon_device *rdev) |
{ |
int r; |
213,6 → 261,14 |
rdev->wb.enabled = false; |
} |
|
/** |
* radeon_wb_fini - Disable Writeback and free memory |
* |
* @rdev: radeon_device pointer |
* |
* Disables Writeback and frees the Writeback memory (all asics). |
* Used at driver shutdown. |
*/ |
void radeon_wb_fini(struct radeon_device *rdev) |
{ |
radeon_wb_disable(rdev); |
223,6 → 279,15 |
} |
} |
|
/** |
* radeon_wb_init- Init Writeback driver info and allocate memory |
* |
* @rdev: radeon_device pointer |
* |
* Disables Writeback and frees the Writeback memory (all asics). |
* Used at driver startup. |
* Returns 0 on success or an -error on failure. |
*/ |
int radeon_wb_init(struct radeon_device *rdev) |
{ |
int r; |
229,7 → 294,7 |
|
if (rdev->wb.wb_obj == NULL) { |
r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true, |
RADEON_GEM_DOMAIN_GTT, &rdev->wb.wb_obj); |
RADEON_GEM_DOMAIN_GTT, NULL, &rdev->wb.wb_obj); |
if (r) { |
dev_warn(rdev->dev, "(%d) create WB bo failed\n", r); |
return r; |
261,21 → 326,25 |
/* disable event_write fences */ |
rdev->wb.use_event = false; |
/* disabled via module param */ |
if (radeon_no_wb == 1) |
if (radeon_no_wb == 1) { |
rdev->wb.enabled = false; |
else { |
} else { |
if (rdev->flags & RADEON_IS_AGP) { |
/* often unreliable on AGP */ |
// if (rdev->flags & RADEON_IS_AGP) { |
// rdev->wb.enabled = false; |
// } else { |
rdev->wb.enabled = false; |
} else if (rdev->family < CHIP_R300) { |
/* often unreliable on pre-r300 */ |
rdev->wb.enabled = false; |
} else { |
rdev->wb.enabled = true; |
/* event_write fences are only available on r600+ */ |
if (rdev->family >= CHIP_R600) |
if (rdev->family >= CHIP_R600) { |
rdev->wb.use_event = true; |
// } |
} |
/* always use writeback/events on NI */ |
if (ASIC_IS_DCE5(rdev)) { |
} |
} |
/* always use writeback/events on NI, APUs */ |
if (rdev->family >= CHIP_PALM) { |
rdev->wb.enabled = true; |
rdev->wb.use_event = true; |
} |
328,6 → 397,8 |
*/ |
void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base) |
{ |
uint64_t limit = (uint64_t)radeon_vram_limit << 20; |
|
mc->vram_start = base; |
if (mc->mc_vram_size > (0xFFFFFFFF - base + 1)) { |
dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); |
341,6 → 412,8 |
mc->mc_vram_size = mc->aper_size; |
} |
mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; |
if (limit && limit < mc->real_vram_size) |
mc->real_vram_size = limit; |
dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", |
mc->mc_vram_size >> 20, mc->vram_start, |
mc->vram_end, mc->real_vram_size >> 20); |
385,6 → 458,15 |
/* |
* GPU helpers function. |
*/ |
/** |
* radeon_card_posted - check if the hw has already been initialized |
* |
* @rdev: radeon_device pointer |
* |
* Check if the asic has been initialized (all asics). |
* Used at driver startup. |
* Returns true if initialized or false if not. |
*/ |
bool radeon_card_posted(struct radeon_device *rdev) |
{ |
uint32_t reg; |
431,6 → 513,14 |
|
} |
|
/** |
* radeon_update_bandwidth_info - update display bandwidth params |
* |
* @rdev: radeon_device pointer |
* |
* Used when sclk/mclk are switched or display modes are set. |
* params are used to calculate display watermarks (all asics) |
*/ |
void radeon_update_bandwidth_info(struct radeon_device *rdev) |
{ |
fixed20_12 a; |
451,6 → 541,15 |
} |
} |
|
/** |
* radeon_boot_test_post_card - check and possibly initialize the hw |
* |
* @rdev: radeon_device pointer |
* |
* Check if the asic is initialized and if not, attempt to initialize |
* it (all asics). |
* Returns true if initialized or false if not. |
*/ |
bool radeon_boot_test_post_card(struct radeon_device *rdev) |
{ |
if (radeon_card_posted(rdev)) |
469,14 → 568,24 |
} |
} |
|
/** |
* radeon_dummy_page_init - init dummy page used by the driver |
* |
* @rdev: radeon_device pointer |
* |
* Allocate the dummy page used by the driver (all asics). |
* This dummy page is used by the driver as a filler for gart entries |
* when pages are taken out of the GART |
* Returns 0 on sucess, -ENOMEM on failure. |
*/ |
int radeon_dummy_page_init(struct radeon_device *rdev) |
{ |
if (rdev->dummy_page.page) |
return 0; |
rdev->dummy_page.page = AllocPage(); |
rdev->dummy_page.page = (void*)AllocPage(); |
if (rdev->dummy_page.page == NULL) |
return -ENOMEM; |
rdev->dummy_page.addr = MapIoMem(rdev->dummy_page.page, 4096, 5); |
rdev->dummy_page.addr = MapIoMem((addr_t)rdev->dummy_page.page, 4096, 3); |
if (!rdev->dummy_page.addr) { |
// __free_page(rdev->dummy_page.page); |
rdev->dummy_page.page = NULL; |
485,16 → 594,40 |
return 0; |
} |
|
/** |
* radeon_dummy_page_fini - free dummy page used by the driver |
* |
* @rdev: radeon_device pointer |
* |
* Frees the dummy page used by the driver (all asics). |
*/ |
void radeon_dummy_page_fini(struct radeon_device *rdev) |
{ |
if (rdev->dummy_page.page == NULL) |
return; |
KernelFree(rdev->dummy_page.addr); |
KernelFree((void*)rdev->dummy_page.addr); |
rdev->dummy_page.page = NULL; |
} |
|
|
/* ATOM accessor methods */ |
/* |
* ATOM is an interpreted byte code stored in tables in the vbios. The |
* driver registers callbacks to access registers and the interpreter |
* in the driver parses the tables and executes then to program specific |
* actions (set display modes, asic init, etc.). See radeon_atombios.c, |
* atombios.h, and atom.c |
*/ |
|
/** |
* cail_pll_read - read PLL register |
* |
* @info: atom card_info pointer |
* @reg: PLL register offset |
* |
* Provides a PLL register accessor for the atom interpreter (r4xx+). |
* Returns the value of the PLL register. |
*/ |
static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) |
{ |
struct radeon_device *rdev = info->dev->dev_private; |
504,6 → 637,15 |
return r; |
} |
|
/** |
* cail_pll_write - write PLL register |
* |
* @info: atom card_info pointer |
* @reg: PLL register offset |
* @val: value to write to the pll register |
* |
* Provides a PLL register accessor for the atom interpreter (r4xx+). |
*/ |
static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) |
{ |
struct radeon_device *rdev = info->dev->dev_private; |
511,6 → 653,15 |
rdev->pll_wreg(rdev, reg, val); |
} |
|
/** |
* cail_mc_read - read MC (Memory Controller) register |
* |
* @info: atom card_info pointer |
* @reg: MC register offset |
* |
* Provides an MC register accessor for the atom interpreter (r4xx+). |
* Returns the value of the MC register. |
*/ |
static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) |
{ |
struct radeon_device *rdev = info->dev->dev_private; |
520,6 → 671,15 |
return r; |
} |
|
/** |
* cail_mc_write - write MC (Memory Controller) register |
* |
* @info: atom card_info pointer |
* @reg: MC register offset |
* @val: value to write to the pll register |
* |
* Provides a MC register accessor for the atom interpreter (r4xx+). |
*/ |
static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) |
{ |
struct radeon_device *rdev = info->dev->dev_private; |
527,6 → 687,15 |
rdev->mc_wreg(rdev, reg, val); |
} |
|
/** |
* cail_reg_write - write MMIO register |
* |
* @info: atom card_info pointer |
* @reg: MMIO register offset |
* @val: value to write to the pll register |
* |
* Provides a MMIO register accessor for the atom interpreter (r4xx+). |
*/ |
static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) |
{ |
struct radeon_device *rdev = info->dev->dev_private; |
534,6 → 703,15 |
WREG32(reg*4, val); |
} |
|
/** |
* cail_reg_read - read MMIO register |
* |
* @info: atom card_info pointer |
* @reg: MMIO register offset |
* |
* Provides an MMIO register accessor for the atom interpreter (r4xx+). |
* Returns the value of the MMIO register. |
*/ |
static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) |
{ |
struct radeon_device *rdev = info->dev->dev_private; |
543,6 → 721,15 |
return r; |
} |
|
/** |
* cail_ioreg_write - write IO register |
* |
* @info: atom card_info pointer |
* @reg: IO register offset |
* @val: value to write to the pll register |
* |
* Provides a IO register accessor for the atom interpreter (r4xx+). |
*/ |
static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val) |
{ |
struct radeon_device *rdev = info->dev->dev_private; |
550,6 → 737,15 |
WREG32_IO(reg*4, val); |
} |
|
/** |
* cail_ioreg_read - read IO register |
* |
* @info: atom card_info pointer |
* @reg: IO register offset |
* |
* Provides an IO register accessor for the atom interpreter (r4xx+). |
* Returns the value of the IO register. |
*/ |
static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg) |
{ |
struct radeon_device *rdev = info->dev->dev_private; |
559,6 → 755,16 |
return r; |
} |
|
/** |
* radeon_atombios_init - init the driver info and callbacks for atombios |
* |
* @rdev: radeon_device pointer |
* |
* Initializes the driver info and register access callbacks for the |
* ATOM interpreter (r4xx+). |
* Returns 0 on sucess, -ENOMEM on failure. |
* Called at driver startup. |
*/ |
int radeon_atombios_init(struct radeon_device *rdev) |
{ |
struct card_info *atom_card_info = |
592,6 → 798,15 |
return 0; |
} |
|
/** |
* radeon_atombios_fini - free the driver info and callbacks for atombios |
* |
* @rdev: radeon_device pointer |
* |
* Frees the driver info and register access callbacks for the ATOM |
* interpreter (r4xx+). |
* Called at driver shutdown. |
*/ |
void radeon_atombios_fini(struct radeon_device *rdev) |
{ |
if (rdev->mode_info.atom_context) { |
601,6 → 816,22 |
kfree(rdev->mode_info.atom_card_info); |
} |
|
/* COMBIOS */ |
/* |
* COMBIOS is the bios format prior to ATOM. It provides |
* command tables similar to ATOM, but doesn't have a unified |
* parser. See radeon_combios.c |
*/ |
|
/** |
* radeon_combios_init - init the driver info for combios |
* |
* @rdev: radeon_device pointer |
* |
* Initializes the driver info for combios (r1xx-r3xx). |
* Returns 0 on sucess. |
* Called at driver startup. |
*/ |
int radeon_combios_init(struct radeon_device *rdev) |
{ |
radeon_combios_initialize_bios_scratch_regs(rdev->ddev); |
607,11 → 838,28 |
return 0; |
} |
|
/** |
* radeon_combios_fini - free the driver info for combios |
* |
* @rdev: radeon_device pointer |
* |
* Frees the driver info for combios (r1xx-r3xx). |
* Called at driver shutdown. |
*/ |
void radeon_combios_fini(struct radeon_device *rdev) |
{ |
} |
|
/* if we get transitioned to only one device, tak VGA back */ |
/* if we get transitioned to only one device, take VGA back */ |
/** |
* radeon_vga_set_decode - enable/disable vga decode |
* |
* @cookie: radeon_device pointer |
* @state: enable/disable vga decode |
* |
* Enable/disable vga decode (all asics). |
* Returns VGA resource flags. |
*/ |
static unsigned int radeon_vga_set_decode(void *cookie, bool state) |
{ |
struct radeon_device *rdev = cookie; |
623,55 → 871,49 |
return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; |
} |
|
void radeon_check_arguments(struct radeon_device *rdev) |
/** |
* radeon_check_pot_argument - check that argument is a power of two |
* |
* @arg: value to check |
* |
* Validates that a certain argument is a power of two (all asics). |
* Returns true if argument is valid. |
*/ |
static bool radeon_check_pot_argument(int arg) |
{ |
return (arg & (arg - 1)) == 0; |
} |
|
/** |
* radeon_check_arguments - validate module params |
* |
* @rdev: radeon_device pointer |
* |
* Validates certain module parameters and updates |
* the associated values used by the driver (all asics). |
*/ |
static void radeon_check_arguments(struct radeon_device *rdev) |
{ |
/* vramlimit must be a power of two */ |
switch (radeon_vram_limit) { |
case 0: |
case 4: |
case 8: |
case 16: |
case 32: |
case 64: |
case 128: |
case 256: |
case 512: |
case 1024: |
case 2048: |
case 4096: |
break; |
default: |
if (!radeon_check_pot_argument(radeon_vram_limit)) { |
dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n", |
radeon_vram_limit); |
radeon_vram_limit = 0; |
break; |
} |
radeon_vram_limit = radeon_vram_limit << 20; |
|
/* gtt size must be power of two and greater or equal to 32M */ |
switch (radeon_gart_size) { |
case 4: |
case 8: |
case 16: |
if (radeon_gart_size < 32) { |
dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n", |
radeon_gart_size); |
radeon_gart_size = 512; |
break; |
case 32: |
case 64: |
case 128: |
case 256: |
case 512: |
case 1024: |
case 2048: |
case 4096: |
break; |
default: |
|
} else if (!radeon_check_pot_argument(radeon_gart_size)) { |
dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n", |
radeon_gart_size); |
radeon_gart_size = 512; |
break; |
} |
rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; |
rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20; |
|
/* AGP mode can only be -1, 1, 2, 4, 8 */ |
switch (radeon_agpmode) { |
case -1: |
705,25 → 947,38 |
rdev->is_atom_bios = false; |
rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT; |
rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; |
rdev->gpu_lockup = false; |
rdev->accel_working = false; |
/* set up ring ids */ |
for (i = 0; i < RADEON_NUM_RINGS; i++) { |
rdev->ring[i].idx = i; |
} |
|
DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X).\n", |
radeon_family_name[rdev->family], pdev->vendor, pdev->device); |
DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n", |
radeon_family_name[rdev->family], pdev->vendor, pdev->device, |
pdev->subsystem_vendor, pdev->subsystem_device); |
|
/* mutex initialization are all done here so we |
* can recall function without having locking issues */ |
mutex_init(&rdev->cs_mutex); |
mutex_init(&rdev->ib_pool.mutex); |
mutex_init(&rdev->cp.mutex); |
mutex_init(&rdev->ring_lock); |
mutex_init(&rdev->dc_hw_i2c_mutex); |
if (rdev->family >= CHIP_R600) |
spin_lock_init(&rdev->ih.lock); |
atomic_set(&rdev->ih.lock, 0); |
mutex_init(&rdev->gem.mutex); |
mutex_init(&rdev->pm.mutex); |
mutex_init(&rdev->vram_mutex); |
rwlock_init(&rdev->fence_drv.lock); |
INIT_LIST_HEAD(&rdev->gem.objects); |
mutex_init(&rdev->gpu_clock_mutex); |
init_rwsem(&rdev->pm.mclk_lock); |
init_rwsem(&rdev->exclusive_lock); |
init_waitqueue_head(&rdev->irq.vblank_queue); |
r = radeon_gem_init(rdev); |
if (r) |
return r; |
/* initialize vm here */ |
mutex_init(&rdev->vm_manager.lock); |
/* Adjust VM size here. |
* Currently set to 4GB ((1 << 20) 4k pages). |
* Max GPUVM size for cayman and SI is 40 bits. |
*/ |
rdev->vm_manager.max_pfn = 1 << 20; |
INIT_LIST_HEAD(&rdev->vm_manager.lru_vm); |
|
/* Set asic functions */ |
r = radeon_asic_init(rdev); |
745,14 → 1000,15 |
|
/* set DMA mask + need_dma32 flags. |
* PCIE - can handle 40-bits. |
* IGP - can handle 40-bits (in theory) |
* IGP - can handle 40-bits |
* AGP - generally dma32 is safest |
* PCI - only dma32 |
* PCI - dma32 for legacy pci gart, 40 bits on newer asics |
*/ |
rdev->need_dma32 = false; |
if (rdev->flags & RADEON_IS_AGP) |
rdev->need_dma32 = true; |
if (rdev->flags & RADEON_IS_PCI) |
if ((rdev->flags & RADEON_IS_PCI) && |
(rdev->family <= CHIP_RS740)) |
rdev->need_dma32 = true; |
|
dma_bits = rdev->need_dma32 ? 32 : 40; |
759,6 → 1015,7 |
r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); |
if (r) { |
rdev->need_dma32 = true; |
dma_bits = 32; |
printk(KERN_WARNING "radeon: No suitable DMA available.\n"); |
} |
|
766,10 → 1023,7 |
/* TODO: block userspace mapping of io register */ |
rdev->rmmio_base = pci_resource_start(rdev->pdev, 2); |
rdev->rmmio_size = pci_resource_len(rdev->pdev, 2); |
|
rdev->rmmio = (void*)MapIoMem(rdev->rmmio_base, rdev->rmmio_size, |
PG_SW+PG_NOCACHE); |
|
rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size); |
if (rdev->rmmio == NULL) { |
return -ENOMEM; |
} |
776,6 → 1030,18 |
DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base); |
DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size); |
|
/* io port mapping */ |
for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { |
if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) { |
rdev->rio_mem_size = pci_resource_len(rdev->pdev, i); |
rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size); |
break; |
} |
} |
if (rdev->rio_mem == NULL) |
DRM_ERROR("Unable to find PCI I/O BAR\n"); |
|
|
r = radeon_init(rdev); |
if (r) |
return r; |
794,13 → 1060,94 |
// if (radeon_testing) { |
// radeon_test_moves(rdev); |
// } |
// if ((radeon_testing & 2)) { |
// radeon_test_syncing(rdev); |
// } |
if (radeon_benchmarking) { |
radeon_benchmark(rdev); |
radeon_benchmark(rdev, radeon_benchmarking); |
} |
return 0; |
} |
|
/** |
* radeon_gpu_reset - reset the asic |
* |
* @rdev: radeon device pointer |
* |
* Attempt the reset the GPU if it has hung (all asics). |
* Returns 0 for success or an error on failure. |
*/ |
int radeon_gpu_reset(struct radeon_device *rdev) |
{ |
unsigned ring_sizes[RADEON_NUM_RINGS]; |
uint32_t *ring_data[RADEON_NUM_RINGS]; |
|
bool saved = false; |
|
int i, r; |
int resched; |
|
// down_write(&rdev->exclusive_lock); |
radeon_save_bios_scratch_regs(rdev); |
/* block TTM */ |
// resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev); |
radeon_suspend(rdev); |
|
for (i = 0; i < RADEON_NUM_RINGS; ++i) { |
ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i], |
&ring_data[i]); |
if (ring_sizes[i]) { |
saved = true; |
dev_info(rdev->dev, "Saved %d dwords of commands " |
"on ring %d.\n", ring_sizes[i], i); |
} |
} |
|
retry: |
r = radeon_asic_reset(rdev); |
if (!r) { |
dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n"); |
radeon_resume(rdev); |
} |
|
radeon_restore_bios_scratch_regs(rdev); |
drm_helper_resume_force_mode(rdev->ddev); |
|
if (!r) { |
for (i = 0; i < RADEON_NUM_RINGS; ++i) { |
radeon_ring_restore(rdev, &rdev->ring[i], |
ring_sizes[i], ring_data[i]); |
ring_sizes[i] = 0; |
ring_data[i] = NULL; |
} |
|
r = radeon_ib_ring_tests(rdev); |
if (r) { |
dev_err(rdev->dev, "ib ring test failed (%d).\n", r); |
if (saved) { |
saved = false; |
radeon_suspend(rdev); |
goto retry; |
} |
} |
} else { |
for (i = 0; i < RADEON_NUM_RINGS; ++i) { |
kfree(ring_data[i]); |
} |
} |
|
// ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched); |
if (r) { |
/* bad news, how to tell it to userspace ? */ |
dev_info(rdev->dev, "GPU reset failed\n"); |
} |
|
// up_write(&rdev->exclusive_lock); |
return r; |
} |
|
|
|
/* |
* Driver load/unload |
*/ |
901,15 → 1248,6 |
init_display(dev->dev_private, &usermode); |
|
|
uint32_t route0 = PciRead32(0, 31<<3, 0x60); |
|
uint32_t route1 = PciRead32(0, 31<<3, 0x68); |
|
uint8_t elcr0 = in8(0x4D0); |
uint8_t elcr1 = in8(0x4D1); |
|
dbgprintf("pci route: %x %x elcr: %x %x\n", route0, route1, elcr0, elcr1); |
|
LEAVE(); |
|
return 0; |
1022,7 → 1360,6 |
dbgprintf("SRV_ENUM_MODES inp %x inp_size %x out_size %x\n", |
inp, io->inp_size, io->out_size ); |
check_output(4); |
check_input(*outp * sizeof(videomode_t)); |
if( radeon_modeset) |
retval = get_modes((videomode_t*)inp, outp); |
break; |
1036,12 → 1373,12 |
break; |
|
case SRV_CREATE_VIDEO: |
retval = r600_create_video(inp[0], inp[1], outp); |
// retval = r600_create_video(inp[0], inp[1], outp); |
break; |
|
case SRV_BLIT_VIDEO: |
r600_video_blit( ((uint64_t*)inp)[0], inp[2], inp[3], |
inp[4], inp[5], inp[6]); |
// r600_video_blit( ((uint64_t*)inp)[0], inp[2], inp[3], |
// inp[4], inp[5], inp[6]); |
|
retval = 0; |
break; |
1049,7 → 1386,7 |
case SRV_CREATE_BITMAP: |
check_input(8); |
check_output(4); |
retval = create_bitmap(outp, inp[0], inp[1]); |
// retval = create_bitmap(outp, inp[0], inp[1]); |
break; |
|
}; |
1064,7 → 1401,7 |
{ |
struct radeon_device *rdev = NULL; |
|
struct pci_device_id *ent; |
const struct pci_device_id *ent; |
|
int err; |
u32_t retval = 0; |
1088,7 → 1425,7 |
return 0; |
}; |
} |
dbgprintf("Radeon RC11 cmdline %s\n", cmdline); |
dbgprintf("Radeon RC12 preview 1 cmdline %s\n", cmdline); |
|
enum_pci_devices(); |
|
1121,3 → 1458,26 |
void drm_vblank_pre_modeset(struct drm_device *dev, int crtc) |
{}; |
|
|
#define PCI_CLASS_REVISION 0x08 |
#define PCI_CLASS_DISPLAY_VGA 0x0300 |
|
int pci_scan_filter(u32_t id, u32_t busnr, u32_t devfn) |
{ |
u16_t vendor, device; |
u32_t class; |
int ret = 0; |
|
vendor = id & 0xffff; |
device = (id >> 16) & 0xffff; |
|
if(vendor == 0x1002) |
{ |
class = PciRead32(busnr, devfn, PCI_CLASS_REVISION); |
class >>= 16; |
|
if( class == PCI_CLASS_DISPLAY_VGA) |
ret = 1; |
} |
return ret; |
} |