39,7 → 39,7 |
|
/* from radeon_encoder.c */ |
extern uint32_t |
radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, |
radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, |
uint8_t dac); |
extern void radeon_link_encoder_connector(struct drm_device *dev); |
|
55,7 → 55,7 |
|
/* from radeon_legacy_encoder.c */ |
extern void |
radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id, |
radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum, |
uint32_t supported_device); |
|
/* old legacy ATI BIOS routines */ |
448,19 → 448,20 |
|
bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev) |
{ |
int edid_info; |
int edid_info, size; |
struct edid *edid; |
unsigned char *raw; |
edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE); |
if (!edid_info) |
return false; |
|
edid = kmalloc(EDID_LENGTH * (DRM_MAX_EDID_EXT_NUM + 1), |
GFP_KERNEL); |
raw = rdev->bios + edid_info; |
size = EDID_LENGTH * (raw[0x7e] + 1); |
edid = kmalloc(size, GFP_KERNEL); |
if (edid == NULL) |
return false; |
|
memcpy((unsigned char *)edid, |
(unsigned char *)(rdev->bios + edid_info), EDID_LENGTH); |
memcpy((unsigned char *)edid, raw, size); |
|
if (!drm_edid_is_valid(edid)) { |
kfree(edid); |
468,22 → 469,105 |
} |
|
rdev->mode_info.bios_hardcoded_edid = edid; |
rdev->mode_info.bios_hardcoded_edid_size = size; |
return true; |
} |
|
/* this is used for atom LCDs as well */ |
struct edid * |
radeon_combios_get_hardcoded_edid(struct radeon_device *rdev) |
radeon_bios_get_hardcoded_edid(struct radeon_device *rdev) |
{ |
if (rdev->mode_info.bios_hardcoded_edid) |
return rdev->mode_info.bios_hardcoded_edid; |
struct edid *edid; |
|
if (rdev->mode_info.bios_hardcoded_edid) { |
edid = kmalloc(rdev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL); |
if (edid) { |
memcpy((unsigned char *)edid, |
(unsigned char *)rdev->mode_info.bios_hardcoded_edid, |
rdev->mode_info.bios_hardcoded_edid_size); |
return edid; |
} |
} |
return NULL; |
} |
|
static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev, |
int ddc_line) |
enum radeon_combios_ddc ddc, |
u32 clk_mask, |
u32 data_mask) |
{ |
struct radeon_i2c_bus_rec i2c; |
int ddc_line = 0; |
|
/* ddc id = mask reg |
* DDC_NONE_DETECTED = none |
* DDC_DVI = RADEON_GPIO_DVI_DDC |
* DDC_VGA = RADEON_GPIO_VGA_DDC |
* DDC_LCD = RADEON_GPIOPAD_MASK |
* DDC_GPIO = RADEON_MDGPIO_MASK |
* r1xx |
* DDC_MONID = RADEON_GPIO_MONID |
* DDC_CRT2 = RADEON_GPIO_CRT2_DDC |
* r200 |
* DDC_MONID = RADEON_GPIO_MONID |
* DDC_CRT2 = RADEON_GPIO_DVI_DDC |
* r300/r350 |
* DDC_MONID = RADEON_GPIO_DVI_DDC |
* DDC_CRT2 = RADEON_GPIO_DVI_DDC |
* rv2xx/rv3xx |
* DDC_MONID = RADEON_GPIO_MONID |
* DDC_CRT2 = RADEON_GPIO_MONID |
* rs3xx/rs4xx |
* DDC_MONID = RADEON_GPIOPAD_MASK |
* DDC_CRT2 = RADEON_GPIO_MONID |
*/ |
switch (ddc) { |
case DDC_NONE_DETECTED: |
default: |
ddc_line = 0; |
break; |
case DDC_DVI: |
ddc_line = RADEON_GPIO_DVI_DDC; |
break; |
case DDC_VGA: |
ddc_line = RADEON_GPIO_VGA_DDC; |
break; |
case DDC_LCD: |
ddc_line = RADEON_GPIOPAD_MASK; |
break; |
case DDC_GPIO: |
ddc_line = RADEON_MDGPIO_MASK; |
break; |
case DDC_MONID: |
if (rdev->family == CHIP_RS300 || |
rdev->family == CHIP_RS400 || |
rdev->family == CHIP_RS480) |
ddc_line = RADEON_GPIOPAD_MASK; |
else if (rdev->family == CHIP_R300 || |
rdev->family == CHIP_R350) { |
ddc_line = RADEON_GPIO_DVI_DDC; |
ddc = DDC_DVI; |
} else |
ddc_line = RADEON_GPIO_MONID; |
break; |
case DDC_CRT2: |
if (rdev->family == CHIP_R200 || |
rdev->family == CHIP_R300 || |
rdev->family == CHIP_R350) { |
ddc_line = RADEON_GPIO_DVI_DDC; |
ddc = DDC_DVI; |
} else if (rdev->family == CHIP_RS300 || |
rdev->family == CHIP_RS400 || |
rdev->family == CHIP_RS480) |
ddc_line = RADEON_GPIO_MONID; |
else if (rdev->family >= CHIP_RV350) { |
ddc_line = RADEON_GPIO_MONID; |
ddc = DDC_MONID; |
} else |
ddc_line = RADEON_GPIO_CRT2_DDC; |
break; |
} |
|
if (ddc_line == RADEON_GPIOPAD_MASK) { |
i2c.mask_clk_reg = RADEON_GPIOPAD_MASK; |
i2c.mask_data_reg = RADEON_GPIOPAD_MASK; |
503,15 → 587,6 |
i2c.y_clk_reg = RADEON_MDGPIO_Y; |
i2c.y_data_reg = RADEON_MDGPIO_Y; |
} else { |
i2c.mask_clk_mask = RADEON_GPIO_EN_1; |
i2c.mask_data_mask = RADEON_GPIO_EN_0; |
i2c.a_clk_mask = RADEON_GPIO_A_1; |
i2c.a_data_mask = RADEON_GPIO_A_0; |
i2c.en_clk_mask = RADEON_GPIO_EN_1; |
i2c.en_data_mask = RADEON_GPIO_EN_0; |
i2c.y_clk_mask = RADEON_GPIO_Y_1; |
i2c.y_data_mask = RADEON_GPIO_Y_0; |
|
i2c.mask_clk_reg = ddc_line; |
i2c.mask_data_reg = ddc_line; |
i2c.a_clk_reg = ddc_line; |
522,6 → 597,39 |
i2c.y_data_reg = ddc_line; |
} |
|
if (clk_mask && data_mask) { |
/* system specific masks */ |
i2c.mask_clk_mask = clk_mask; |
i2c.mask_data_mask = data_mask; |
i2c.a_clk_mask = clk_mask; |
i2c.a_data_mask = data_mask; |
i2c.en_clk_mask = clk_mask; |
i2c.en_data_mask = data_mask; |
i2c.y_clk_mask = clk_mask; |
i2c.y_data_mask = data_mask; |
} else if ((ddc_line == RADEON_GPIOPAD_MASK) || |
(ddc_line == RADEON_MDGPIO_MASK)) { |
/* default gpiopad masks */ |
i2c.mask_clk_mask = (0x20 << 8); |
i2c.mask_data_mask = 0x80; |
i2c.a_clk_mask = (0x20 << 8); |
i2c.a_data_mask = 0x80; |
i2c.en_clk_mask = (0x20 << 8); |
i2c.en_data_mask = 0x80; |
i2c.y_clk_mask = (0x20 << 8); |
i2c.y_data_mask = 0x80; |
} else { |
/* default masks for ddc pads */ |
i2c.mask_clk_mask = RADEON_GPIO_EN_1; |
i2c.mask_data_mask = RADEON_GPIO_EN_0; |
i2c.a_clk_mask = RADEON_GPIO_A_1; |
i2c.a_data_mask = RADEON_GPIO_A_0; |
i2c.en_clk_mask = RADEON_GPIO_EN_1; |
i2c.en_data_mask = RADEON_GPIO_EN_0; |
i2c.y_clk_mask = RADEON_GPIO_Y_1; |
i2c.y_data_mask = RADEON_GPIO_Y_0; |
} |
|
switch (rdev->family) { |
case CHIP_R100: |
case CHIP_RV100: |
531,10 → 639,7 |
case CHIP_RS300: |
switch (ddc_line) { |
case RADEON_GPIO_DVI_DDC: |
/* in theory this should be hw capable, |
* but it doesn't seem to work |
*/ |
i2c.hw_capable = false; |
i2c.hw_capable = true; |
break; |
default: |
i2c.hw_capable = false; |
602,9 → 707,10 |
break; |
} |
i2c.mm_i2c = false; |
i2c.i2c_id = 0; |
i2c.hpd_id = 0; |
|
i2c.i2c_id = ddc; |
i2c.hpd = RADEON_HPD_NONE; |
|
if (ddc_line) |
i2c.valid = true; |
else |
613,6 → 719,80 |
return i2c; |
} |
|
void radeon_combios_i2c_init(struct radeon_device *rdev) |
{ |
struct drm_device *dev = rdev->ddev; |
struct radeon_i2c_bus_rec i2c; |
|
/* actual hw pads |
* r1xx/rs2xx/rs3xx |
* 0x60, 0x64, 0x68, 0x6c, gpiopads, mm |
* r200 |
* 0x60, 0x64, 0x68, mm |
* r300/r350 |
* 0x60, 0x64, mm |
* rv2xx/rv3xx/rs4xx |
* 0x60, 0x64, 0x68, gpiopads, mm |
*/ |
|
/* 0x60 */ |
i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
rdev->i2c_bus[0] = radeon_i2c_create(dev, &i2c, "DVI_DDC"); |
/* 0x64 */ |
i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
rdev->i2c_bus[1] = radeon_i2c_create(dev, &i2c, "VGA_DDC"); |
|
/* mm i2c */ |
i2c.valid = true; |
i2c.hw_capable = true; |
i2c.mm_i2c = true; |
i2c.i2c_id = 0xa0; |
rdev->i2c_bus[2] = radeon_i2c_create(dev, &i2c, "MM_I2C"); |
|
if (rdev->family == CHIP_R300 || |
rdev->family == CHIP_R350) { |
/* only 2 sw i2c pads */ |
} else if (rdev->family == CHIP_RS300 || |
rdev->family == CHIP_RS400 || |
rdev->family == CHIP_RS480) { |
u16 offset; |
u8 id, blocks, clk, data; |
int i; |
|
/* 0x68 */ |
i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); |
rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID"); |
|
offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE); |
if (offset) { |
blocks = RBIOS8(offset + 2); |
for (i = 0; i < blocks; i++) { |
id = RBIOS8(offset + 3 + (i * 5) + 0); |
if (id == 136) { |
clk = RBIOS8(offset + 3 + (i * 5) + 3); |
data = RBIOS8(offset + 3 + (i * 5) + 4); |
/* gpiopad */ |
i2c = combios_setup_i2c_bus(rdev, DDC_MONID, |
(1 << clk), (1 << data)); |
rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK"); |
break; |
} |
} |
} |
} else if (rdev->family >= CHIP_R200) { |
/* 0x68 */ |
i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); |
rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID"); |
} else { |
/* 0x68 */ |
i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); |
rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID"); |
/* 0x6c */ |
i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); |
rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "CRT2_DDC"); |
} |
} |
|
bool radeon_combios_get_clock_info(struct drm_device *dev) |
{ |
struct radeon_device *rdev = dev->dev_private; |
633,6 → 813,8 |
p1pll->reference_div = RBIOS16(pll_info + 0x10); |
p1pll->pll_out_min = RBIOS32(pll_info + 0x12); |
p1pll->pll_out_max = RBIOS32(pll_info + 0x16); |
p1pll->lcd_pll_out_min = p1pll->pll_out_min; |
p1pll->lcd_pll_out_max = p1pll->pll_out_max; |
|
if (rev > 9) { |
p1pll->pll_in_min = RBIOS32(pll_info + 0x36); |
684,6 → 866,11 |
rdev->clock.default_sclk = sclk; |
rdev->clock.default_mclk = mclk; |
|
if (RBIOS32(pll_info + 0x16)) |
rdev->clock.max_pixel_clock = RBIOS32(pll_info + 0x16); |
else |
rdev->clock.max_pixel_clock = 35000; /* might need something asic specific */ |
|
return true; |
} |
return false; |
694,6 → 881,10 |
struct drm_device *dev = rdev->ddev; |
u16 igp_info; |
|
/* sideport is AMD only */ |
if (rdev->family == CHIP_RS400) |
return false; |
|
igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE); |
|
if (igp_info) { |
761,6 → 952,8 |
dac = RBIOS8(dac_info + 0x3) & 0xf; |
p_dac->ps2_pdac_adj = (bg << 8) | (dac); |
} |
/* if the values are all zeros, use the table */ |
if (p_dac->ps2_pdac_adj) |
found = 1; |
} |
|
783,31 → 976,31 |
switch (RBIOS8(tv_info + 7) & 0xf) { |
case 1: |
tv_std = TV_STD_NTSC; |
DRM_INFO("Default TV standard: NTSC\n"); |
DRM_DEBUG_KMS("Default TV standard: NTSC\n"); |
break; |
case 2: |
tv_std = TV_STD_PAL; |
DRM_INFO("Default TV standard: PAL\n"); |
DRM_DEBUG_KMS("Default TV standard: PAL\n"); |
break; |
case 3: |
tv_std = TV_STD_PAL_M; |
DRM_INFO("Default TV standard: PAL-M\n"); |
DRM_DEBUG_KMS("Default TV standard: PAL-M\n"); |
break; |
case 4: |
tv_std = TV_STD_PAL_60; |
DRM_INFO("Default TV standard: PAL-60\n"); |
DRM_DEBUG_KMS("Default TV standard: PAL-60\n"); |
break; |
case 5: |
tv_std = TV_STD_NTSC_J; |
DRM_INFO("Default TV standard: NTSC-J\n"); |
DRM_DEBUG_KMS("Default TV standard: NTSC-J\n"); |
break; |
case 6: |
tv_std = TV_STD_SCART_PAL; |
DRM_INFO("Default TV standard: SCART-PAL\n"); |
DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n"); |
break; |
default: |
tv_std = TV_STD_NTSC; |
DRM_INFO |
DRM_DEBUG_KMS |
("Unknown TV standard; defaulting to NTSC\n"); |
break; |
} |
814,16 → 1007,16 |
|
switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) { |
case 0: |
DRM_INFO("29.498928713 MHz TV ref clk\n"); |
DRM_DEBUG_KMS("29.498928713 MHz TV ref clk\n"); |
break; |
case 1: |
DRM_INFO("28.636360000 MHz TV ref clk\n"); |
DRM_DEBUG_KMS("28.636360000 MHz TV ref clk\n"); |
break; |
case 2: |
DRM_INFO("14.318180000 MHz TV ref clk\n"); |
DRM_DEBUG_KMS("14.318180000 MHz TV ref clk\n"); |
break; |
case 3: |
DRM_INFO("27.000000000 MHz TV ref clk\n"); |
DRM_DEBUG_KMS("27.000000000 MHz TV ref clk\n"); |
break; |
default: |
break; |
896,6 → 1089,8 |
bg = RBIOS8(dac_info + 0x10) & 0xf; |
dac = RBIOS8(dac_info + 0x11) & 0xf; |
tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); |
/* if the values are all zeros, use the table */ |
if (tv_dac->ps2_tvdac_adj) |
found = 1; |
} else if (rev > 1) { |
bg = RBIOS8(dac_info + 0xc) & 0xf; |
909,6 → 1104,8 |
bg = RBIOS8(dac_info + 0xe) & 0xf; |
dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf; |
tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); |
/* if the values are all zeros, use the table */ |
if (tv_dac->ps2_tvdac_adj) |
found = 1; |
} |
tv_dac->tv_std = radeon_combios_get_tv_info(rdev); |
926,6 → 1123,8 |
(bg << 16) | (dac << 20); |
tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; |
tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; |
/* if the values are all zeros, use the table */ |
if (tv_dac->ps2_tvdac_adj) |
found = 1; |
} else { |
bg = RBIOS8(dac_info + 0x4) & 0xf; |
934,6 → 1133,8 |
(bg << 16) | (dac << 20); |
tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; |
tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; |
/* if the values are all zeros, use the table */ |
if (tv_dac->ps2_tvdac_adj) |
found = 1; |
} |
} else { |
1104,18 → 1305,20 |
break; |
|
if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) && |
(RBIOS16(tmp + 2) == |
lvds->native_mode.vdisplay)) { |
lvds->native_mode.htotal = RBIOS16(tmp + 17) * 8; |
lvds->native_mode.hsync_start = RBIOS16(tmp + 21) * 8; |
lvds->native_mode.hsync_end = (RBIOS8(tmp + 23) + |
RBIOS16(tmp + 21)) * 8; |
(RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) { |
lvds->native_mode.htotal = lvds->native_mode.hdisplay + |
(RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8; |
lvds->native_mode.hsync_start = lvds->native_mode.hdisplay + |
(RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8; |
lvds->native_mode.hsync_end = lvds->native_mode.hsync_start + |
(RBIOS8(tmp + 23) * 8); |
|
lvds->native_mode.vtotal = RBIOS16(tmp + 24); |
lvds->native_mode.vsync_start = RBIOS16(tmp + 28) & 0x7ff; |
lvds->native_mode.vsync_end = |
((RBIOS16(tmp + 28) & 0xf800) >> 11) + |
(RBIOS16(tmp + 28) & 0x7ff); |
lvds->native_mode.vtotal = lvds->native_mode.vdisplay + |
(RBIOS16(tmp + 24) - RBIOS16(tmp + 26)); |
lvds->native_mode.vsync_start = lvds->native_mode.vdisplay + |
((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26)); |
lvds->native_mode.vsync_end = lvds->native_mode.vsync_start + |
((RBIOS16(tmp + 28) & 0xf800) >> 11); |
|
lvds->native_mode.clock = RBIOS16(tmp + 9) * 10; |
lvds->native_mode.flags = 0; |
1184,7 → 1387,7 |
|
if (tmds_info) { |
ver = RBIOS8(tmds_info); |
DRM_INFO("DFP table revision: %d\n", ver); |
DRM_DEBUG_KMS("DFP table revision: %d\n", ver); |
if (ver == 3) { |
n = RBIOS8(tmds_info + 5) + 1; |
if (n > 4) |
1194,7 → 1397,7 |
RBIOS32(tmds_info + i * 10 + 0x08); |
tmds->tmds_pll[i].freq = |
RBIOS16(tmds_info + i * 10 + 0x10); |
DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n", |
DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n", |
tmds->tmds_pll[i].freq, |
tmds->tmds_pll[i].value); |
} |
1212,7 → 1415,7 |
stride += 10; |
else |
stride += 6; |
DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n", |
DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n", |
tmds->tmds_pll[i].freq, |
tmds->tmds_pll[i].value); |
} |
1232,8 → 1435,8 |
struct radeon_i2c_bus_rec i2c_bus; |
|
/* default for macs */ |
i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID); |
tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO"); |
i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); |
tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); |
|
/* XXX some macs have duallink chips */ |
switch (rdev->mode_info.connector_table) { |
1254,88 → 1457,35 |
struct drm_device *dev = encoder->base.dev; |
struct radeon_device *rdev = dev->dev_private; |
uint16_t offset; |
uint8_t ver, id, blocks, clk, data; |
int i; |
uint8_t ver; |
enum radeon_combios_ddc gpio; |
struct radeon_i2c_bus_rec i2c_bus; |
|
tmds->i2c_bus = NULL; |
if (rdev->flags & RADEON_IS_IGP) { |
offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE); |
if (offset) { |
ver = RBIOS8(offset); |
DRM_INFO("GPIO Table revision: %d\n", ver); |
blocks = RBIOS8(offset + 2); |
for (i = 0; i < blocks; i++) { |
id = RBIOS8(offset + 3 + (i * 5) + 0); |
if (id == 136) { |
clk = RBIOS8(offset + 3 + (i * 5) + 3); |
data = RBIOS8(offset + 3 + (i * 5) + 4); |
i2c_bus.valid = true; |
i2c_bus.mask_clk_mask = (1 << clk); |
i2c_bus.mask_data_mask = (1 << data); |
i2c_bus.a_clk_mask = (1 << clk); |
i2c_bus.a_data_mask = (1 << data); |
i2c_bus.en_clk_mask = (1 << clk); |
i2c_bus.en_data_mask = (1 << data); |
i2c_bus.y_clk_mask = (1 << clk); |
i2c_bus.y_data_mask = (1 << data); |
i2c_bus.mask_clk_reg = RADEON_GPIOPAD_MASK; |
i2c_bus.mask_data_reg = RADEON_GPIOPAD_MASK; |
i2c_bus.a_clk_reg = RADEON_GPIOPAD_A; |
i2c_bus.a_data_reg = RADEON_GPIOPAD_A; |
i2c_bus.en_clk_reg = RADEON_GPIOPAD_EN; |
i2c_bus.en_data_reg = RADEON_GPIOPAD_EN; |
i2c_bus.y_clk_reg = RADEON_GPIOPAD_Y; |
i2c_bus.y_data_reg = RADEON_GPIOPAD_Y; |
tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO"); |
i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); |
tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); |
tmds->dvo_chip = DVO_SIL164; |
tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */ |
break; |
} |
} |
} |
} else { |
offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); |
if (offset) { |
ver = RBIOS8(offset); |
DRM_INFO("External TMDS Table revision: %d\n", ver); |
DRM_DEBUG_KMS("External TMDS Table revision: %d\n", ver); |
tmds->slave_addr = RBIOS8(offset + 4 + 2); |
tmds->slave_addr >>= 1; /* 7 bit addressing */ |
gpio = RBIOS8(offset + 4 + 3); |
switch (gpio) { |
case DDC_MONID: |
i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID); |
tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO"); |
break; |
case DDC_DVI: |
i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); |
tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO"); |
break; |
case DDC_VGA: |
i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); |
tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO"); |
break; |
case DDC_CRT2: |
/* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */ |
if (rdev->family >= CHIP_R300) |
i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID); |
else |
i2c_bus = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC); |
tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO"); |
break; |
case DDC_LCD: /* MM i2c */ |
if (gpio == DDC_LCD) { |
/* MM i2c */ |
i2c_bus.valid = true; |
i2c_bus.hw_capable = true; |
i2c_bus.mm_i2c = true; |
tmds->i2c_bus = radeon_i2c_create(dev, &i2c_bus, "DVO"); |
break; |
default: |
DRM_ERROR("Unsupported gpio %d\n", gpio); |
break; |
i2c_bus.i2c_id = 0xa0; |
} else |
i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0); |
tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); |
} |
} |
} |
|
if (!tmds->i2c_bus) { |
DRM_INFO("No valid Ext TMDS info found in BIOS\n"); |
1398,8 → 1548,22 |
/* PowerMac8,1 ? */ |
/* imac g5 isight */ |
rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT; |
} else if ((rdev->pdev->device == 0x4a48) && |
(rdev->pdev->subsystem_vendor == 0x1002) && |
(rdev->pdev->subsystem_device == 0x4a48)) { |
/* Mac X800 */ |
rdev->mode_info.connector_table = CT_MAC_X800; |
} else if (of_machine_is_compatible("PowerMac7,2") || |
of_machine_is_compatible("PowerMac7,3")) { |
/* Mac G5 9600 */ |
rdev->mode_info.connector_table = CT_MAC_G5_9600; |
} else |
#endif /* CONFIG_PPC_PMAC */ |
#ifdef CONFIG_PPC64 |
if (ASIC_IS_RN50(rdev)) |
rdev->mode_info.connector_table = CT_RN50_POWER; |
else |
#endif |
rdev->mode_info.connector_table = CT_GENERIC; |
} |
|
1410,10 → 1574,10 |
/* these are the most common settings */ |
if (rdev->flags & RADEON_SINGLE_CRTC) { |
/* VGA - primary dac */ |
ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); |
ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
hpd.hpd = RADEON_HPD_NONE; |
radeon_add_legacy_encoder(dev, |
radeon_get_encoder_id(dev, |
radeon_get_encoder_enum(dev, |
ATOM_DEVICE_CRT1_SUPPORT, |
1), |
ATOM_DEVICE_CRT1_SUPPORT); |
1425,10 → 1589,10 |
&hpd); |
} else if (rdev->flags & RADEON_IS_MOBILITY) { |
/* LVDS */ |
ddc_i2c = combios_setup_i2c_bus(rdev, 0); |
ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0); |
hpd.hpd = RADEON_HPD_NONE; |
radeon_add_legacy_encoder(dev, |
radeon_get_encoder_id(dev, |
radeon_get_encoder_enum(dev, |
ATOM_DEVICE_LCD1_SUPPORT, |
0), |
ATOM_DEVICE_LCD1_SUPPORT); |
1440,10 → 1604,10 |
&hpd); |
|
/* VGA - primary dac */ |
ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); |
ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
hpd.hpd = RADEON_HPD_NONE; |
radeon_add_legacy_encoder(dev, |
radeon_get_encoder_id(dev, |
radeon_get_encoder_enum(dev, |
ATOM_DEVICE_CRT1_SUPPORT, |
1), |
ATOM_DEVICE_CRT1_SUPPORT); |
1455,15 → 1619,15 |
&hpd); |
} else { |
/* DVI-I - tv dac, int tmds */ |
ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); |
ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
hpd.hpd = RADEON_HPD_1; |
radeon_add_legacy_encoder(dev, |
radeon_get_encoder_id(dev, |
radeon_get_encoder_enum(dev, |
ATOM_DEVICE_DFP1_SUPPORT, |
0), |
ATOM_DEVICE_DFP1_SUPPORT); |
radeon_add_legacy_encoder(dev, |
radeon_get_encoder_id(dev, |
radeon_get_encoder_enum(dev, |
ATOM_DEVICE_CRT2_SUPPORT, |
2), |
ATOM_DEVICE_CRT2_SUPPORT); |
1476,10 → 1640,10 |
&hpd); |
|
/* VGA - primary dac */ |
ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); |
ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
hpd.hpd = RADEON_HPD_NONE; |
radeon_add_legacy_encoder(dev, |
radeon_get_encoder_id(dev, |
radeon_get_encoder_enum(dev, |
ATOM_DEVICE_CRT1_SUPPORT, |
1), |
ATOM_DEVICE_CRT1_SUPPORT); |
1496,7 → 1660,7 |
ddc_i2c.valid = false; |
hpd.hpd = RADEON_HPD_NONE; |
radeon_add_legacy_encoder(dev, |
radeon_get_encoder_id(dev, |
radeon_get_encoder_enum(dev, |
ATOM_DEVICE_TV1_SUPPORT, |
2), |
ATOM_DEVICE_TV1_SUPPORT); |
1512,10 → 1676,10 |
DRM_INFO("Connector Table: %d (ibook)\n", |
rdev->mode_info.connector_table); |
/* LVDS */ |
ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); |
ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
hpd.hpd = RADEON_HPD_NONE; |
radeon_add_legacy_encoder(dev, |
radeon_get_encoder_id(dev, |
radeon_get_encoder_enum(dev, |
ATOM_DEVICE_LCD1_SUPPORT, |
0), |
ATOM_DEVICE_LCD1_SUPPORT); |
1524,10 → 1688,10 |
CONNECTOR_OBJECT_ID_LVDS, |
&hpd); |
/* VGA - TV DAC */ |
ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); |
ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
hpd.hpd = RADEON_HPD_NONE; |
radeon_add_legacy_encoder(dev, |
radeon_get_encoder_id(dev, |
radeon_get_encoder_enum(dev, |
ATOM_DEVICE_CRT2_SUPPORT, |
2), |
ATOM_DEVICE_CRT2_SUPPORT); |
1539,7 → 1703,7 |
ddc_i2c.valid = false; |
hpd.hpd = RADEON_HPD_NONE; |
radeon_add_legacy_encoder(dev, |
radeon_get_encoder_id(dev, |
radeon_get_encoder_enum(dev, |
ATOM_DEVICE_TV1_SUPPORT, |
2), |
ATOM_DEVICE_TV1_SUPPORT); |
1553,10 → 1717,10 |
DRM_INFO("Connector Table: %d (powerbook external tmds)\n", |
rdev->mode_info.connector_table); |
/* LVDS */ |
ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); |
ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
hpd.hpd = RADEON_HPD_NONE; |
radeon_add_legacy_encoder(dev, |
radeon_get_encoder_id(dev, |
radeon_get_encoder_enum(dev, |
ATOM_DEVICE_LCD1_SUPPORT, |
0), |
ATOM_DEVICE_LCD1_SUPPORT); |
1565,15 → 1729,15 |
CONNECTOR_OBJECT_ID_LVDS, |
&hpd); |
/* DVI-I - primary dac, ext tmds */ |
ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); |
ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
hpd.hpd = RADEON_HPD_2; /* ??? */ |
radeon_add_legacy_encoder(dev, |
radeon_get_encoder_id(dev, |
radeon_get_encoder_enum(dev, |
ATOM_DEVICE_DFP2_SUPPORT, |
0), |
ATOM_DEVICE_DFP2_SUPPORT); |
radeon_add_legacy_encoder(dev, |
radeon_get_encoder_id(dev, |
radeon_get_encoder_enum(dev, |
ATOM_DEVICE_CRT1_SUPPORT, |
1), |
ATOM_DEVICE_CRT1_SUPPORT); |
1588,7 → 1752,7 |
ddc_i2c.valid = false; |
hpd.hpd = RADEON_HPD_NONE; |
radeon_add_legacy_encoder(dev, |
radeon_get_encoder_id(dev, |
radeon_get_encoder_enum(dev, |
ATOM_DEVICE_TV1_SUPPORT, |
2), |
ATOM_DEVICE_TV1_SUPPORT); |
1602,10 → 1766,10 |
DRM_INFO("Connector Table: %d (powerbook internal tmds)\n", |
rdev->mode_info.connector_table); |
/* LVDS */ |
ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); |
ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
hpd.hpd = RADEON_HPD_NONE; |
radeon_add_legacy_encoder(dev, |
radeon_get_encoder_id(dev, |
radeon_get_encoder_enum(dev, |
ATOM_DEVICE_LCD1_SUPPORT, |
0), |
ATOM_DEVICE_LCD1_SUPPORT); |
1614,15 → 1778,15 |
CONNECTOR_OBJECT_ID_LVDS, |
&hpd); |
/* DVI-I - primary dac, int tmds */ |
ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); |
ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
hpd.hpd = RADEON_HPD_1; /* ??? */ |
radeon_add_legacy_encoder(dev, |
radeon_get_encoder_id(dev, |
radeon_get_encoder_enum(dev, |
ATOM_DEVICE_DFP1_SUPPORT, |
0), |
ATOM_DEVICE_DFP1_SUPPORT); |
radeon_add_legacy_encoder(dev, |
radeon_get_encoder_id(dev, |
radeon_get_encoder_enum(dev, |
ATOM_DEVICE_CRT1_SUPPORT, |
1), |
ATOM_DEVICE_CRT1_SUPPORT); |
1636,7 → 1800,7 |
ddc_i2c.valid = false; |
hpd.hpd = RADEON_HPD_NONE; |
radeon_add_legacy_encoder(dev, |
radeon_get_encoder_id(dev, |
radeon_get_encoder_enum(dev, |
ATOM_DEVICE_TV1_SUPPORT, |
2), |
ATOM_DEVICE_TV1_SUPPORT); |
1650,10 → 1814,10 |
DRM_INFO("Connector Table: %d (powerbook vga)\n", |
rdev->mode_info.connector_table); |
/* LVDS */ |
ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); |
ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
hpd.hpd = RADEON_HPD_NONE; |
radeon_add_legacy_encoder(dev, |
radeon_get_encoder_id(dev, |
radeon_get_encoder_enum(dev, |
ATOM_DEVICE_LCD1_SUPPORT, |
0), |
ATOM_DEVICE_LCD1_SUPPORT); |
1662,10 → 1826,10 |
CONNECTOR_OBJECT_ID_LVDS, |
&hpd); |
/* VGA - primary dac */ |
ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); |
ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
hpd.hpd = RADEON_HPD_NONE; |
radeon_add_legacy_encoder(dev, |
radeon_get_encoder_id(dev, |
radeon_get_encoder_enum(dev, |
ATOM_DEVICE_CRT1_SUPPORT, |
1), |
ATOM_DEVICE_CRT1_SUPPORT); |
1677,7 → 1841,7 |
ddc_i2c.valid = false; |
hpd.hpd = RADEON_HPD_NONE; |
radeon_add_legacy_encoder(dev, |
radeon_get_encoder_id(dev, |
radeon_get_encoder_enum(dev, |
ATOM_DEVICE_TV1_SUPPORT, |
2), |
ATOM_DEVICE_TV1_SUPPORT); |
1691,15 → 1855,15 |
DRM_INFO("Connector Table: %d (mini external tmds)\n", |
rdev->mode_info.connector_table); |
/* DVI-I - tv dac, ext tmds */ |
ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC); |
ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); |
hpd.hpd = RADEON_HPD_2; /* ??? */ |
radeon_add_legacy_encoder(dev, |
radeon_get_encoder_id(dev, |
radeon_get_encoder_enum(dev, |
ATOM_DEVICE_DFP2_SUPPORT, |
0), |
ATOM_DEVICE_DFP2_SUPPORT); |
radeon_add_legacy_encoder(dev, |
radeon_get_encoder_id(dev, |
radeon_get_encoder_enum(dev, |
ATOM_DEVICE_CRT2_SUPPORT, |
2), |
ATOM_DEVICE_CRT2_SUPPORT); |
1714,7 → 1878,7 |
ddc_i2c.valid = false; |
hpd.hpd = RADEON_HPD_NONE; |
radeon_add_legacy_encoder(dev, |
radeon_get_encoder_id(dev, |
radeon_get_encoder_enum(dev, |
ATOM_DEVICE_TV1_SUPPORT, |
2), |
ATOM_DEVICE_TV1_SUPPORT); |
1728,15 → 1892,15 |
DRM_INFO("Connector Table: %d (mini internal tmds)\n", |
rdev->mode_info.connector_table); |
/* DVI-I - tv dac, int tmds */ |
ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC); |
ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); |
hpd.hpd = RADEON_HPD_1; /* ??? */ |
radeon_add_legacy_encoder(dev, |
radeon_get_encoder_id(dev, |
radeon_get_encoder_enum(dev, |
ATOM_DEVICE_DFP1_SUPPORT, |
0), |
ATOM_DEVICE_DFP1_SUPPORT); |
radeon_add_legacy_encoder(dev, |
radeon_get_encoder_id(dev, |
radeon_get_encoder_enum(dev, |
ATOM_DEVICE_CRT2_SUPPORT, |
2), |
ATOM_DEVICE_CRT2_SUPPORT); |
1750,7 → 1914,7 |
ddc_i2c.valid = false; |
hpd.hpd = RADEON_HPD_NONE; |
radeon_add_legacy_encoder(dev, |
radeon_get_encoder_id(dev, |
radeon_get_encoder_enum(dev, |
ATOM_DEVICE_TV1_SUPPORT, |
2), |
ATOM_DEVICE_TV1_SUPPORT); |
1764,10 → 1928,10 |
DRM_INFO("Connector Table: %d (imac g5 isight)\n", |
rdev->mode_info.connector_table); |
/* DVI-D - int tmds */ |
ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID); |
ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); |
hpd.hpd = RADEON_HPD_1; /* ??? */ |
radeon_add_legacy_encoder(dev, |
radeon_get_encoder_id(dev, |
radeon_get_encoder_enum(dev, |
ATOM_DEVICE_DFP1_SUPPORT, |
0), |
ATOM_DEVICE_DFP1_SUPPORT); |
1776,10 → 1940,10 |
CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D, |
&hpd); |
/* VGA - tv dac */ |
ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); |
ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
hpd.hpd = RADEON_HPD_NONE; |
radeon_add_legacy_encoder(dev, |
radeon_get_encoder_id(dev, |
radeon_get_encoder_enum(dev, |
ATOM_DEVICE_CRT2_SUPPORT, |
2), |
ATOM_DEVICE_CRT2_SUPPORT); |
1791,7 → 1955,7 |
ddc_i2c.valid = false; |
hpd.hpd = RADEON_HPD_NONE; |
radeon_add_legacy_encoder(dev, |
radeon_get_encoder_id(dev, |
radeon_get_encoder_enum(dev, |
ATOM_DEVICE_TV1_SUPPORT, |
2), |
ATOM_DEVICE_TV1_SUPPORT); |
1805,10 → 1969,10 |
DRM_INFO("Connector Table: %d (emac)\n", |
rdev->mode_info.connector_table); |
/* VGA - primary dac */ |
ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); |
ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
hpd.hpd = RADEON_HPD_NONE; |
radeon_add_legacy_encoder(dev, |
radeon_get_encoder_id(dev, |
radeon_get_encoder_enum(dev, |
ATOM_DEVICE_CRT1_SUPPORT, |
1), |
ATOM_DEVICE_CRT1_SUPPORT); |
1817,10 → 1981,10 |
CONNECTOR_OBJECT_ID_VGA, |
&hpd); |
/* VGA - tv dac */ |
ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC); |
ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); |
hpd.hpd = RADEON_HPD_NONE; |
radeon_add_legacy_encoder(dev, |
radeon_get_encoder_id(dev, |
radeon_get_encoder_enum(dev, |
ATOM_DEVICE_CRT2_SUPPORT, |
2), |
ATOM_DEVICE_CRT2_SUPPORT); |
1832,7 → 1996,7 |
ddc_i2c.valid = false; |
hpd.hpd = RADEON_HPD_NONE; |
radeon_add_legacy_encoder(dev, |
radeon_get_encoder_id(dev, |
radeon_get_encoder_enum(dev, |
ATOM_DEVICE_TV1_SUPPORT, |
2), |
ATOM_DEVICE_TV1_SUPPORT); |
1842,6 → 2006,130 |
CONNECTOR_OBJECT_ID_SVIDEO, |
&hpd); |
break; |
case CT_RN50_POWER: |
DRM_INFO("Connector Table: %d (rn50-power)\n", |
rdev->mode_info.connector_table); |
/* VGA - primary dac */ |
ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
hpd.hpd = RADEON_HPD_NONE; |
radeon_add_legacy_encoder(dev, |
radeon_get_encoder_enum(dev, |
ATOM_DEVICE_CRT1_SUPPORT, |
1), |
ATOM_DEVICE_CRT1_SUPPORT); |
radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT, |
DRM_MODE_CONNECTOR_VGA, &ddc_i2c, |
CONNECTOR_OBJECT_ID_VGA, |
&hpd); |
ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); |
hpd.hpd = RADEON_HPD_NONE; |
radeon_add_legacy_encoder(dev, |
radeon_get_encoder_enum(dev, |
ATOM_DEVICE_CRT2_SUPPORT, |
2), |
ATOM_DEVICE_CRT2_SUPPORT); |
radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, |
DRM_MODE_CONNECTOR_VGA, &ddc_i2c, |
CONNECTOR_OBJECT_ID_VGA, |
&hpd); |
break; |
case CT_MAC_X800: |
DRM_INFO("Connector Table: %d (mac x800)\n", |
rdev->mode_info.connector_table); |
/* DVI - primary dac, internal tmds */ |
ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
hpd.hpd = RADEON_HPD_1; /* ??? */ |
radeon_add_legacy_encoder(dev, |
radeon_get_encoder_enum(dev, |
ATOM_DEVICE_DFP1_SUPPORT, |
0), |
ATOM_DEVICE_DFP1_SUPPORT); |
radeon_add_legacy_encoder(dev, |
radeon_get_encoder_enum(dev, |
ATOM_DEVICE_CRT1_SUPPORT, |
1), |
ATOM_DEVICE_CRT1_SUPPORT); |
radeon_add_legacy_connector(dev, 0, |
ATOM_DEVICE_DFP1_SUPPORT | |
ATOM_DEVICE_CRT1_SUPPORT, |
DRM_MODE_CONNECTOR_DVII, &ddc_i2c, |
CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, |
&hpd); |
/* DVI - tv dac, dvo */ |
ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); |
hpd.hpd = RADEON_HPD_2; /* ??? */ |
radeon_add_legacy_encoder(dev, |
radeon_get_encoder_enum(dev, |
ATOM_DEVICE_DFP2_SUPPORT, |
0), |
ATOM_DEVICE_DFP2_SUPPORT); |
radeon_add_legacy_encoder(dev, |
radeon_get_encoder_enum(dev, |
ATOM_DEVICE_CRT2_SUPPORT, |
2), |
ATOM_DEVICE_CRT2_SUPPORT); |
radeon_add_legacy_connector(dev, 1, |
ATOM_DEVICE_DFP2_SUPPORT | |
ATOM_DEVICE_CRT2_SUPPORT, |
DRM_MODE_CONNECTOR_DVII, &ddc_i2c, |
CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, |
&hpd); |
break; |
case CT_MAC_G5_9600: |
DRM_INFO("Connector Table: %d (mac g5 9600)\n", |
rdev->mode_info.connector_table); |
/* DVI - tv dac, dvo */ |
ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
hpd.hpd = RADEON_HPD_1; /* ??? */ |
radeon_add_legacy_encoder(dev, |
radeon_get_encoder_enum(dev, |
ATOM_DEVICE_DFP2_SUPPORT, |
0), |
ATOM_DEVICE_DFP2_SUPPORT); |
radeon_add_legacy_encoder(dev, |
radeon_get_encoder_enum(dev, |
ATOM_DEVICE_CRT2_SUPPORT, |
2), |
ATOM_DEVICE_CRT2_SUPPORT); |
radeon_add_legacy_connector(dev, 0, |
ATOM_DEVICE_DFP2_SUPPORT | |
ATOM_DEVICE_CRT2_SUPPORT, |
DRM_MODE_CONNECTOR_DVII, &ddc_i2c, |
CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, |
&hpd); |
/* ADC - primary dac, internal tmds */ |
ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
hpd.hpd = RADEON_HPD_2; /* ??? */ |
radeon_add_legacy_encoder(dev, |
radeon_get_encoder_enum(dev, |
ATOM_DEVICE_DFP1_SUPPORT, |
0), |
ATOM_DEVICE_DFP1_SUPPORT); |
radeon_add_legacy_encoder(dev, |
radeon_get_encoder_enum(dev, |
ATOM_DEVICE_CRT1_SUPPORT, |
1), |
ATOM_DEVICE_CRT1_SUPPORT); |
radeon_add_legacy_connector(dev, 1, |
ATOM_DEVICE_DFP1_SUPPORT | |
ATOM_DEVICE_CRT1_SUPPORT, |
DRM_MODE_CONNECTOR_DVII, &ddc_i2c, |
CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, |
&hpd); |
/* TV - TV DAC */ |
ddc_i2c.valid = false; |
hpd.hpd = RADEON_HPD_NONE; |
radeon_add_legacy_encoder(dev, |
radeon_get_encoder_enum(dev, |
ATOM_DEVICE_TV1_SUPPORT, |
2), |
ATOM_DEVICE_TV1_SUPPORT); |
radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, |
DRM_MODE_CONNECTOR_SVIDEO, |
&ddc_i2c, |
CONNECTOR_OBJECT_ID_SVIDEO, |
&hpd); |
break; |
default: |
DRM_INFO("Connector table: %d (invalid)\n", |
rdev->mode_info.connector_table); |
1860,32 → 2148,7 |
struct radeon_i2c_bus_rec *ddc_i2c, |
struct radeon_hpd *hpd) |
{ |
struct radeon_device *rdev = dev->dev_private; |
|
/* XPRESS DDC quirks */ |
if ((rdev->family == CHIP_RS400 || |
rdev->family == CHIP_RS480) && |
ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC) |
*ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID); |
else if ((rdev->family == CHIP_RS400 || |
rdev->family == CHIP_RS480) && |
ddc_i2c->mask_clk_reg == RADEON_GPIO_MONID) { |
*ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIOPAD_MASK); |
ddc_i2c->mask_clk_mask = (0x20 << 8); |
ddc_i2c->mask_data_mask = 0x80; |
ddc_i2c->a_clk_mask = (0x20 << 8); |
ddc_i2c->a_data_mask = 0x80; |
ddc_i2c->en_clk_mask = (0x20 << 8); |
ddc_i2c->en_data_mask = 0x80; |
ddc_i2c->y_clk_mask = (0x20 << 8); |
ddc_i2c->y_data_mask = 0x80; |
} |
|
/* R3xx+ chips don't have GPIO_CRT2_DDC gpio pad */ |
if ((rdev->family >= CHIP_R300) && |
ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC) |
*ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); |
|
/* Certain IBM chipset RN50s have a BIOS reporting two VGAs, |
one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */ |
if (dev->pdev->device == 0x515e && |
1895,15 → 2158,6 |
return false; |
} |
|
/* Some RV100 cards with 2 VGA ports show up with DVI+VGA */ |
if (dev->pdev->device == 0x5159 && |
dev->pdev->subsystem_vendor == 0x1002 && |
dev->pdev->subsystem_device == 0x013a) { |
if (*legacy_connector == CONNECTOR_DVI_I_LEGACY) |
*legacy_connector = CONNECTOR_CRT_LEGACY; |
|
} |
|
/* X300 card with extra non-existent DVI port */ |
if (dev->pdev->device == 0x5B60 && |
dev->pdev->subsystem_vendor == 0x17af && |
1997,26 → 2251,7 |
connector = (tmp >> 12) & 0xf; |
|
ddc_type = (tmp >> 8) & 0xf; |
switch (ddc_type) { |
case DDC_MONID: |
ddc_i2c = |
combios_setup_i2c_bus(rdev, RADEON_GPIO_MONID); |
break; |
case DDC_DVI: |
ddc_i2c = |
combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); |
break; |
case DDC_VGA: |
ddc_i2c = |
combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); |
break; |
case DDC_CRT2: |
ddc_i2c = |
combios_setup_i2c_bus(rdev, RADEON_GPIO_CRT2_DDC); |
break; |
default: |
break; |
} |
ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0); |
|
switch (connector) { |
case CONNECTOR_PROPRIETARY_LEGACY: |
2043,7 → 2278,7 |
else |
devices = ATOM_DEVICE_DFP1_SUPPORT; |
radeon_add_legacy_encoder(dev, |
radeon_get_encoder_id |
radeon_get_encoder_enum |
(dev, devices, 0), |
devices); |
radeon_add_legacy_connector(dev, i, devices, |
2057,7 → 2292,7 |
if (tmp & 0x1) { |
devices = ATOM_DEVICE_CRT2_SUPPORT; |
radeon_add_legacy_encoder(dev, |
radeon_get_encoder_id |
radeon_get_encoder_enum |
(dev, |
ATOM_DEVICE_CRT2_SUPPORT, |
2), |
2065,7 → 2300,7 |
} else { |
devices = ATOM_DEVICE_CRT1_SUPPORT; |
radeon_add_legacy_encoder(dev, |
radeon_get_encoder_id |
radeon_get_encoder_enum |
(dev, |
ATOM_DEVICE_CRT1_SUPPORT, |
1), |
2085,7 → 2320,7 |
if (tmp & 0x1) { |
devices |= ATOM_DEVICE_CRT2_SUPPORT; |
radeon_add_legacy_encoder(dev, |
radeon_get_encoder_id |
radeon_get_encoder_enum |
(dev, |
ATOM_DEVICE_CRT2_SUPPORT, |
2), |
2093,7 → 2328,7 |
} else { |
devices |= ATOM_DEVICE_CRT1_SUPPORT; |
radeon_add_legacy_encoder(dev, |
radeon_get_encoder_id |
radeon_get_encoder_enum |
(dev, |
ATOM_DEVICE_CRT1_SUPPORT, |
1), |
2102,7 → 2337,7 |
if ((tmp >> 4) & 0x1) { |
devices |= ATOM_DEVICE_DFP2_SUPPORT; |
radeon_add_legacy_encoder(dev, |
radeon_get_encoder_id |
radeon_get_encoder_enum |
(dev, |
ATOM_DEVICE_DFP2_SUPPORT, |
0), |
2111,7 → 2346,7 |
} else { |
devices |= ATOM_DEVICE_DFP1_SUPPORT; |
radeon_add_legacy_encoder(dev, |
radeon_get_encoder_id |
radeon_get_encoder_enum |
(dev, |
ATOM_DEVICE_DFP1_SUPPORT, |
0), |
2136,7 → 2371,7 |
connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; |
} |
radeon_add_legacy_encoder(dev, |
radeon_get_encoder_id |
radeon_get_encoder_enum |
(dev, devices, 0), |
devices); |
radeon_add_legacy_connector(dev, i, devices, |
2149,7 → 2384,7 |
case CONNECTOR_CTV_LEGACY: |
case CONNECTOR_STV_LEGACY: |
radeon_add_legacy_encoder(dev, |
radeon_get_encoder_id |
radeon_get_encoder_enum |
(dev, |
ATOM_DEVICE_TV1_SUPPORT, |
2), |
2173,21 → 2408,21 |
uint16_t tmds_info = |
combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE); |
if (tmds_info) { |
DRM_DEBUG("Found DFP table, assuming DVI connector\n"); |
DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n"); |
|
radeon_add_legacy_encoder(dev, |
radeon_get_encoder_id(dev, |
radeon_get_encoder_enum(dev, |
ATOM_DEVICE_CRT1_SUPPORT, |
1), |
ATOM_DEVICE_CRT1_SUPPORT); |
radeon_add_legacy_encoder(dev, |
radeon_get_encoder_id(dev, |
radeon_get_encoder_enum(dev, |
ATOM_DEVICE_DFP1_SUPPORT, |
0), |
ATOM_DEVICE_DFP1_SUPPORT); |
|
ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_DVI_DDC); |
hpd.hpd = RADEON_HPD_NONE; |
ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); |
hpd.hpd = RADEON_HPD_1; |
radeon_add_legacy_connector(dev, |
0, |
ATOM_DEVICE_CRT1_SUPPORT | |
2199,14 → 2434,14 |
} else { |
uint16_t crt_info = |
combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); |
DRM_DEBUG("Found CRT table, assuming VGA connector\n"); |
DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n"); |
if (crt_info) { |
radeon_add_legacy_encoder(dev, |
radeon_get_encoder_id(dev, |
radeon_get_encoder_enum(dev, |
ATOM_DEVICE_CRT1_SUPPORT, |
1), |
ATOM_DEVICE_CRT1_SUPPORT); |
ddc_i2c = combios_setup_i2c_bus(rdev, RADEON_GPIO_VGA_DDC); |
ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); |
hpd.hpd = RADEON_HPD_NONE; |
radeon_add_legacy_connector(dev, |
0, |
2216,7 → 2451,7 |
CONNECTOR_OBJECT_ID_VGA, |
&hpd); |
} else { |
DRM_DEBUG("No connector info found\n"); |
DRM_DEBUG_KMS("No connector info found\n"); |
return false; |
} |
} |
2231,7 → 2466,7 |
COMBIOS_LCD_DDC_INFO_TABLE); |
|
radeon_add_legacy_encoder(dev, |
radeon_get_encoder_id(dev, |
radeon_get_encoder_enum(dev, |
ATOM_DEVICE_LCD1_SUPPORT, |
0), |
ATOM_DEVICE_LCD1_SUPPORT); |
2239,73 → 2474,28 |
if (lcd_ddc_info) { |
ddc_type = RBIOS8(lcd_ddc_info + 2); |
switch (ddc_type) { |
case DDC_MONID: |
ddc_i2c = |
combios_setup_i2c_bus |
(rdev, RADEON_GPIO_MONID); |
break; |
case DDC_DVI: |
ddc_i2c = |
combios_setup_i2c_bus |
(rdev, RADEON_GPIO_DVI_DDC); |
break; |
case DDC_VGA: |
ddc_i2c = |
combios_setup_i2c_bus |
(rdev, RADEON_GPIO_VGA_DDC); |
break; |
case DDC_CRT2: |
ddc_i2c = |
combios_setup_i2c_bus |
(rdev, RADEON_GPIO_CRT2_DDC); |
break; |
case DDC_LCD: |
ddc_i2c = |
combios_setup_i2c_bus |
(rdev, RADEON_GPIOPAD_MASK); |
ddc_i2c.mask_clk_mask = |
RBIOS32(lcd_ddc_info + 3); |
ddc_i2c.mask_data_mask = |
RBIOS32(lcd_ddc_info + 7); |
ddc_i2c.a_clk_mask = |
RBIOS32(lcd_ddc_info + 3); |
ddc_i2c.a_data_mask = |
RBIOS32(lcd_ddc_info + 7); |
ddc_i2c.en_clk_mask = |
RBIOS32(lcd_ddc_info + 3); |
ddc_i2c.en_data_mask = |
RBIOS32(lcd_ddc_info + 7); |
ddc_i2c.y_clk_mask = |
RBIOS32(lcd_ddc_info + 3); |
ddc_i2c.y_data_mask = |
RBIOS32(lcd_ddc_info + 7); |
combios_setup_i2c_bus(rdev, |
DDC_LCD, |
RBIOS32(lcd_ddc_info + 3), |
RBIOS32(lcd_ddc_info + 7)); |
radeon_i2c_add(rdev, &ddc_i2c, "LCD"); |
break; |
case DDC_GPIO: |
ddc_i2c = |
combios_setup_i2c_bus |
(rdev, RADEON_MDGPIO_MASK); |
ddc_i2c.mask_clk_mask = |
RBIOS32(lcd_ddc_info + 3); |
ddc_i2c.mask_data_mask = |
RBIOS32(lcd_ddc_info + 7); |
ddc_i2c.a_clk_mask = |
RBIOS32(lcd_ddc_info + 3); |
ddc_i2c.a_data_mask = |
RBIOS32(lcd_ddc_info + 7); |
ddc_i2c.en_clk_mask = |
RBIOS32(lcd_ddc_info + 3); |
ddc_i2c.en_data_mask = |
RBIOS32(lcd_ddc_info + 7); |
ddc_i2c.y_clk_mask = |
RBIOS32(lcd_ddc_info + 3); |
ddc_i2c.y_data_mask = |
RBIOS32(lcd_ddc_info + 7); |
combios_setup_i2c_bus(rdev, |
DDC_GPIO, |
RBIOS32(lcd_ddc_info + 3), |
RBIOS32(lcd_ddc_info + 7)); |
radeon_i2c_add(rdev, &ddc_i2c, "LCD"); |
break; |
default: |
ddc_i2c.valid = false; |
ddc_i2c = |
combios_setup_i2c_bus(rdev, ddc_type, 0, 0); |
break; |
} |
DRM_DEBUG("LCD DDC Info Table found!\n"); |
DRM_DEBUG_KMS("LCD DDC Info Table found!\n"); |
} else |
ddc_i2c.valid = false; |
|
2328,8 → 2518,9 |
if (RBIOS8(tv_info + 6) == 'T') { |
if (radeon_apply_legacy_tv_quirks(dev)) { |
hpd.hpd = RADEON_HPD_NONE; |
ddc_i2c.valid = false; |
radeon_add_legacy_encoder(dev, |
radeon_get_encoder_id |
radeon_get_encoder_enum |
(dev, |
ATOM_DEVICE_TV1_SUPPORT, |
2), |
2350,6 → 2541,12 |
return true; |
} |
|
static const char *thermal_controller_names[] = { |
"NONE", |
"lm63", |
"adm1032", |
}; |
|
void radeon_combios_get_power_modes(struct radeon_device *rdev) |
{ |
struct drm_device *dev = rdev->ddev; |
2357,8 → 2554,67 |
u8 rev, blocks, tmp; |
int state_index = 0; |
|
rdev->pm.default_power_state = NULL; |
rdev->pm.default_power_state_index = -1; |
|
/* allocate 2 power states */ |
rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * 2, GFP_KERNEL); |
if (!rdev->pm.power_state) { |
rdev->pm.default_power_state_index = state_index; |
rdev->pm.num_power_states = 0; |
|
rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; |
rdev->pm.current_clock_mode_index = 0; |
return; |
} |
|
/* check for a thermal chip */ |
offset = combios_get_table_offset(dev, COMBIOS_OVERDRIVE_INFO_TABLE); |
if (offset) { |
u8 thermal_controller = 0, gpio = 0, i2c_addr = 0, clk_bit = 0, data_bit = 0; |
struct radeon_i2c_bus_rec i2c_bus; |
|
rev = RBIOS8(offset); |
|
if (rev == 0) { |
thermal_controller = RBIOS8(offset + 3); |
gpio = RBIOS8(offset + 4) & 0x3f; |
i2c_addr = RBIOS8(offset + 5); |
} else if (rev == 1) { |
thermal_controller = RBIOS8(offset + 4); |
gpio = RBIOS8(offset + 5) & 0x3f; |
i2c_addr = RBIOS8(offset + 6); |
} else if (rev == 2) { |
thermal_controller = RBIOS8(offset + 4); |
gpio = RBIOS8(offset + 5) & 0x3f; |
i2c_addr = RBIOS8(offset + 6); |
clk_bit = RBIOS8(offset + 0xa); |
data_bit = RBIOS8(offset + 0xb); |
} |
if ((thermal_controller > 0) && (thermal_controller < 3)) { |
DRM_INFO("Possible %s thermal controller at 0x%02x\n", |
thermal_controller_names[thermal_controller], |
i2c_addr >> 1); |
if (gpio == DDC_LCD) { |
/* MM i2c */ |
i2c_bus.valid = true; |
i2c_bus.hw_capable = true; |
i2c_bus.mm_i2c = true; |
i2c_bus.i2c_id = 0xa0; |
} else if (gpio == DDC_GPIO) |
i2c_bus = combios_setup_i2c_bus(rdev, gpio, 1 << clk_bit, 1 << data_bit); |
else |
i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0); |
rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); |
if (rdev->pm.i2c_bus) { |
struct i2c_board_info info = { }; |
const char *name = thermal_controller_names[thermal_controller]; |
info.addr = i2c_addr >> 1; |
strlcpy(info.type, name, sizeof(info.type)); |
i2c_new_device(&rdev->pm.i2c_bus->adapter, &info); |
} |
} |
} |
|
if (rdev->flags & RADEON_IS_MOBILITY) { |
offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE); |
if (offset) { |
2371,17 → 2627,13 |
if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || |
(rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) |
goto default_mode; |
/* skip overclock modes for now */ |
if ((rdev->pm.power_state[state_index].clock_info[0].mclk > |
rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) || |
(rdev->pm.power_state[state_index].clock_info[0].sclk > |
rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN)) |
goto default_mode; |
rdev->pm.power_state[state_index].type = |
POWER_STATE_TYPE_BATTERY; |
misc = RBIOS16(offset + 0x5 + 0x0); |
if (rev > 4) |
misc2 = RBIOS16(offset + 0x5 + 0xe); |
rdev->pm.power_state[state_index].misc = misc; |
rdev->pm.power_state[state_index].misc2 = misc2; |
if (misc & 0x4) { |
rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO; |
if (misc & 0x8) |
2428,8 → 2680,9 |
} else |
rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; |
if (rev > 6) |
rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = |
rdev->pm.power_state[state_index].pcie_lanes = |
RBIOS8(offset + 0x5 + 0x10); |
rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; |
state_index++; |
} else { |
/* XXX figure out some good default low power mode for mobility cards w/out power tables */ |
2446,17 → 2699,19 |
rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk; |
rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk; |
rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0]; |
if ((state_index > 0) && |
(rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO)) |
rdev->pm.power_state[state_index].clock_info[0].voltage = |
rdev->pm.power_state[0].clock_info[0].voltage; |
else |
rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; |
if (rdev->asic->get_pcie_lanes) |
rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = radeon_get_pcie_lanes(rdev); |
else |
rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = 16; |
rdev->pm.default_power_state = &rdev->pm.power_state[state_index]; |
rdev->pm.power_state[state_index].pcie_lanes = 16; |
rdev->pm.power_state[state_index].flags = 0; |
rdev->pm.default_power_state_index = state_index; |
rdev->pm.num_power_states = state_index + 1; |
|
rdev->pm.current_power_state = rdev->pm.default_power_state; |
rdev->pm.current_clock_mode = |
rdev->pm.default_power_state->default_clock_mode; |
rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; |
rdev->pm.current_clock_mode_index = 0; |
} |
|
void radeon_external_tmds_setup(struct drm_encoder *encoder) |
2906,9 → 3161,8 |
if (rev < 3) { |
mem_cntl = RBIOS32(offset + 1); |
mem_size = RBIOS16(offset + 5); |
if (((rdev->flags & RADEON_FAMILY_MASK) < CHIP_R200) && |
((dev->pdev->device != 0x515e) |
&& (dev->pdev->device != 0x5969))) |
if ((rdev->family < CHIP_R200) && |
!ASIC_IS_RN50(rdev)) |
WREG32(RADEON_MEM_CNTL, mem_cntl); |
} |
} |
2919,10 → 3173,8 |
if (offset) { |
rev = RBIOS8(offset - 1); |
if (rev < 1) { |
if (((rdev->flags & RADEON_FAMILY_MASK) < |
CHIP_R200) |
&& ((dev->pdev->device != 0x515e) |
&& (dev->pdev->device != 0x5969))) { |
if ((rdev->family < CHIP_R200) |
&& !ASIC_IS_RN50(rdev)) { |
int ram = 0; |
int mem_addr_mapping = 0; |
|
3007,6 → 3259,22 |
combios_write_ram_size(dev); |
} |
|
/* quirk for rs4xx HP nx6125 laptop to make it resume |
* - it hangs on resume inside the dynclk 1 table. |
*/ |
if (rdev->family == CHIP_RS480 && |
rdev->pdev->subsystem_vendor == 0x103c && |
rdev->pdev->subsystem_device == 0x308b) |
return; |
|
/* quirk for rs4xx HP dv5000 laptop to make it resume |
* - it hangs on resume inside the dynclk 1 table. |
*/ |
if (rdev->family == CHIP_RS480 && |
rdev->pdev->subsystem_vendor == 0x103c && |
rdev->pdev->subsystem_device == 0x30a4) |
return; |
|
/* DYN CLK 1 */ |
table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE); |
if (table) |
3070,7 → 3338,7 |
if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) && |
(radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) { |
if (connected) { |
DRM_DEBUG("TV1 connected\n"); |
DRM_DEBUG_KMS("TV1 connected\n"); |
/* fix me */ |
bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO; |
/*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */ |
3077,7 → 3345,7 |
bios_5_scratch |= RADEON_TV1_ON; |
bios_5_scratch |= RADEON_ACC_REQ_TV1; |
} else { |
DRM_DEBUG("TV1 disconnected\n"); |
DRM_DEBUG_KMS("TV1 disconnected\n"); |
bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK; |
bios_5_scratch &= ~RADEON_TV1_ON; |
bios_5_scratch &= ~RADEON_ACC_REQ_TV1; |
3086,12 → 3354,12 |
if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) && |
(radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) { |
if (connected) { |
DRM_DEBUG("LCD1 connected\n"); |
DRM_DEBUG_KMS("LCD1 connected\n"); |
bios_4_scratch |= RADEON_LCD1_ATTACHED; |
bios_5_scratch |= RADEON_LCD1_ON; |
bios_5_scratch |= RADEON_ACC_REQ_LCD1; |
} else { |
DRM_DEBUG("LCD1 disconnected\n"); |
DRM_DEBUG_KMS("LCD1 disconnected\n"); |
bios_4_scratch &= ~RADEON_LCD1_ATTACHED; |
bios_5_scratch &= ~RADEON_LCD1_ON; |
bios_5_scratch &= ~RADEON_ACC_REQ_LCD1; |
3100,12 → 3368,12 |
if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) && |
(radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) { |
if (connected) { |
DRM_DEBUG("CRT1 connected\n"); |
DRM_DEBUG_KMS("CRT1 connected\n"); |
bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR; |
bios_5_scratch |= RADEON_CRT1_ON; |
bios_5_scratch |= RADEON_ACC_REQ_CRT1; |
} else { |
DRM_DEBUG("CRT1 disconnected\n"); |
DRM_DEBUG_KMS("CRT1 disconnected\n"); |
bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK; |
bios_5_scratch &= ~RADEON_CRT1_ON; |
bios_5_scratch &= ~RADEON_ACC_REQ_CRT1; |
3114,12 → 3382,12 |
if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) && |
(radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) { |
if (connected) { |
DRM_DEBUG("CRT2 connected\n"); |
DRM_DEBUG_KMS("CRT2 connected\n"); |
bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR; |
bios_5_scratch |= RADEON_CRT2_ON; |
bios_5_scratch |= RADEON_ACC_REQ_CRT2; |
} else { |
DRM_DEBUG("CRT2 disconnected\n"); |
DRM_DEBUG_KMS("CRT2 disconnected\n"); |
bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK; |
bios_5_scratch &= ~RADEON_CRT2_ON; |
bios_5_scratch &= ~RADEON_ACC_REQ_CRT2; |
3128,12 → 3396,12 |
if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) && |
(radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) { |
if (connected) { |
DRM_DEBUG("DFP1 connected\n"); |
DRM_DEBUG_KMS("DFP1 connected\n"); |
bios_4_scratch |= RADEON_DFP1_ATTACHED; |
bios_5_scratch |= RADEON_DFP1_ON; |
bios_5_scratch |= RADEON_ACC_REQ_DFP1; |
} else { |
DRM_DEBUG("DFP1 disconnected\n"); |
DRM_DEBUG_KMS("DFP1 disconnected\n"); |
bios_4_scratch &= ~RADEON_DFP1_ATTACHED; |
bios_5_scratch &= ~RADEON_DFP1_ON; |
bios_5_scratch &= ~RADEON_ACC_REQ_DFP1; |
3142,12 → 3410,12 |
if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) && |
(radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) { |
if (connected) { |
DRM_DEBUG("DFP2 connected\n"); |
DRM_DEBUG_KMS("DFP2 connected\n"); |
bios_4_scratch |= RADEON_DFP2_ATTACHED; |
bios_5_scratch |= RADEON_DFP2_ON; |
bios_5_scratch |= RADEON_ACC_REQ_DFP2; |
} else { |
DRM_DEBUG("DFP2 disconnected\n"); |
DRM_DEBUG_KMS("DFP2 disconnected\n"); |
bios_4_scratch &= ~RADEON_DFP2_ATTACHED; |
bios_5_scratch &= ~RADEON_DFP2_ON; |
bios_5_scratch &= ~RADEON_ACC_REQ_DFP2; |