33,6 → 33,7 |
*/ |
uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev); |
void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); |
uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev); |
void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
|
uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev); |
76,7 → 77,6 |
void r100_bandwidth_update(struct radeon_device *rdev); |
void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); |
int r100_ring_test(struct radeon_device *rdev); |
void r100_hdp_flush(struct radeon_device *rdev); |
void r100_hpd_init(struct radeon_device *rdev); |
void r100_hpd_fini(struct radeon_device *rdev); |
bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
106,7 → 106,7 |
// .copy = &r100_copy_blit, |
.get_engine_clock = &radeon_legacy_get_engine_clock, |
.set_engine_clock = &radeon_legacy_set_engine_clock, |
.get_memory_clock = NULL, |
.get_memory_clock = &radeon_legacy_get_memory_clock, |
.set_memory_clock = NULL, |
.set_pcie_lanes = NULL, |
.set_clock_gating = &radeon_legacy_set_clock_gating, |
113,7 → 113,6 |
.set_surface_reg = r100_set_surface_reg, |
.clear_surface_reg = r100_clear_surface_reg, |
.bandwidth_update = &r100_bandwidth_update, |
.hdp_flush = &r100_hdp_flush, |
.hpd_init = &r100_hpd_init, |
.hpd_fini = &r100_hpd_fini, |
.hpd_sense = &r100_hpd_sense, |
166,7 → 165,7 |
// .copy = &r100_copy_blit, |
.get_engine_clock = &radeon_legacy_get_engine_clock, |
.set_engine_clock = &radeon_legacy_set_engine_clock, |
.get_memory_clock = NULL, |
.get_memory_clock = &radeon_legacy_get_memory_clock, |
.set_memory_clock = NULL, |
.set_pcie_lanes = &rv370_set_pcie_lanes, |
.set_clock_gating = &radeon_legacy_set_clock_gating, |
173,7 → 172,6 |
.set_surface_reg = r100_set_surface_reg, |
.clear_surface_reg = r100_clear_surface_reg, |
.bandwidth_update = &r100_bandwidth_update, |
.hdp_flush = &r100_hdp_flush, |
.hpd_init = &r100_hpd_init, |
.hpd_fini = &r100_hpd_fini, |
.hpd_sense = &r100_hpd_sense, |
217,7 → 215,6 |
.set_surface_reg = r100_set_surface_reg, |
.clear_surface_reg = r100_clear_surface_reg, |
.bandwidth_update = &r100_bandwidth_update, |
.hdp_flush = &r100_hdp_flush, |
.hpd_init = &r100_hpd_init, |
.hpd_fini = &r100_hpd_fini, |
.hpd_sense = &r100_hpd_sense, |
259,7 → 256,7 |
// .copy = &r100_copy_blit, |
.get_engine_clock = &radeon_legacy_get_engine_clock, |
.set_engine_clock = &radeon_legacy_set_engine_clock, |
.get_memory_clock = NULL, |
.get_memory_clock = &radeon_legacy_get_memory_clock, |
.set_memory_clock = NULL, |
.set_pcie_lanes = NULL, |
.set_clock_gating = &radeon_legacy_set_clock_gating, |
266,7 → 263,6 |
.set_surface_reg = r100_set_surface_reg, |
.clear_surface_reg = r100_clear_surface_reg, |
.bandwidth_update = &r100_bandwidth_update, |
.hdp_flush = &r100_hdp_flush, |
.hpd_init = &r100_hpd_init, |
.hpd_fini = &r100_hpd_fini, |
.hpd_sense = &r100_hpd_sense, |
323,7 → 319,6 |
.set_pcie_lanes = NULL, |
.set_clock_gating = &radeon_atom_set_clock_gating, |
.bandwidth_update = &rs600_bandwidth_update, |
.hdp_flush = &r100_hdp_flush, |
.hpd_init = &rs600_hpd_init, |
.hpd_fini = &rs600_hpd_fini, |
.hpd_sense = &rs600_hpd_sense, |
371,7 → 366,6 |
.set_surface_reg = r100_set_surface_reg, |
.clear_surface_reg = r100_clear_surface_reg, |
.bandwidth_update = &rs690_bandwidth_update, |
.hdp_flush = &r100_hdp_flush, |
.hpd_init = &rs600_hpd_init, |
.hpd_fini = &rs600_hpd_fini, |
.hpd_sense = &rs600_hpd_sense, |
423,7 → 417,6 |
.set_surface_reg = r100_set_surface_reg, |
.clear_surface_reg = r100_clear_surface_reg, |
.bandwidth_update = &rv515_bandwidth_update, |
.hdp_flush = &r100_hdp_flush, |
.hpd_init = &rs600_hpd_init, |
.hpd_fini = &rs600_hpd_fini, |
.hpd_sense = &rs600_hpd_sense, |
466,7 → 459,6 |
.set_surface_reg = r100_set_surface_reg, |
.clear_surface_reg = r100_clear_surface_reg, |
.bandwidth_update = &rv515_bandwidth_update, |
.hdp_flush = &r100_hdp_flush, |
.hpd_init = &rs600_hpd_init, |
.hpd_fini = &rs600_hpd_fini, |
.hpd_sense = &rs600_hpd_sense, |
507,7 → 499,6 |
int r600_copy_blit(struct radeon_device *rdev, |
uint64_t src_offset, uint64_t dst_offset, |
unsigned num_pages, struct radeon_fence *fence); |
void r600_hdp_flush(struct radeon_device *rdev); |
void r600_hpd_init(struct radeon_device *rdev); |
void r600_hpd_fini(struct radeon_device *rdev); |
bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
542,7 → 533,6 |
.set_surface_reg = r600_set_surface_reg, |
.clear_surface_reg = r600_clear_surface_reg, |
.bandwidth_update = &rv515_bandwidth_update, |
.hdp_flush = &r600_hdp_flush, |
.hpd_init = &r600_hpd_init, |
.hpd_fini = &r600_hpd_fini, |
.hpd_sense = &r600_hpd_sense, |
586,7 → 576,6 |
.set_surface_reg = r600_set_surface_reg, |
.clear_surface_reg = r600_clear_surface_reg, |
.bandwidth_update = &rv515_bandwidth_update, |
.hdp_flush = &r600_hdp_flush, |
.hpd_init = &r600_hpd_init, |
.hpd_fini = &r600_hpd_fini, |
.hpd_sense = &r600_hpd_sense, |