| 119,6 → 119,7 |
|---|
| #define DB_DEBUG 0x9830 |
| #define PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31) |
| #define DB_DEPTH_BASE 0x2800C |
| #define DB_HTILE_DATA_BASE 0x28014 |
| #define DB_WATERMARKS 0x9838 |
| #define DEPTH_FREE(x) ((x) << 0) |
| #define DEPTH_FLUSH(x) ((x) << 5) |
| 171,6 → 172,14 |
|---|
| #define SQ_STACK_RESOURCE_MGMT_2 0x8c14 |
| # define NUM_GS_STACK_ENTRIES(x) ((x) << 0) |
| # define NUM_ES_STACK_ENTRIES(x) ((x) << 16) |
| #define SQ_ESGS_RING_BASE 0x8c40 |
| #define SQ_GSVS_RING_BASE 0x8c48 |
| #define SQ_ESTMP_RING_BASE 0x8c50 |
| #define SQ_GSTMP_RING_BASE 0x8c58 |
| #define SQ_VSTMP_RING_BASE 0x8c60 |
| #define SQ_PSTMP_RING_BASE 0x8c68 |
| #define SQ_FBUF_RING_BASE 0x8c70 |
| #define SQ_REDUC_RING_BASE 0x8c78 |
| |
| #define GRBM_CNTL 0x8000 |
| # define GRBM_READ_TIMEOUT(x) ((x) << 0) |
| 271,6 → 280,10 |
|---|
| #define PCIE_PORT_INDEX 0x0038 |
| #define PCIE_PORT_DATA 0x003C |
| |
| #define CHMAP 0x2004 |
| #define NOOFCHAN_SHIFT 12 |
| #define NOOFCHAN_MASK 0x00003000 |
| |
| #define RAMCFG 0x2408 |
| #define NOOFBANK_SHIFT 0 |
| #define NOOFBANK_MASK 0x00000001 |
| 352,6 → 365,7 |
|---|
| |
| |
| #define SX_MISC 0x28350 |
| #define SX_MEMORY_EXPORT_BASE 0x9010 |
| #define SX_DEBUG_1 0x9054 |
| #define SMX_EVENT_RELEASE (1 << 0) |
| #define ENABLE_NEW_SMX_ADDRESS (1 << 16) |