| 81,11 → 81,16 |
|---|
| #define R600_MEDIUM_VID_LOWER_GPIO_CNTL 0x720 |
| #define R600_LOW_VID_LOWER_GPIO_CNTL 0x724 |
| |
| #define R600_D1GRPH_SWAP_CONTROL 0x610C |
| # define R600_D1GRPH_SWAP_ENDIAN_NONE (0 << 0) |
| # define R600_D1GRPH_SWAP_ENDIAN_16BIT (1 << 0) |
| # define R600_D1GRPH_SWAP_ENDIAN_32BIT (2 << 0) |
| # define R600_D1GRPH_SWAP_ENDIAN_64BIT (3 << 0) |
| |
| |
| #define R600_HDP_NONSURFACE_BASE 0x2c04 |
| |
| #define R600_BUS_CNTL 0x5420 |
| # define R600_BIOS_ROM_DIS (1 << 1) |
| #define R600_CONFIG_CNTL 0x5424 |
| #define R600_CONFIG_MEMSIZE 0x5428 |
| #define R600_CONFIG_F0_BASE 0x542C |
| 152,14 → 157,17 |
|---|
| #define R600_AUDIO_STATUS_BITS 0x73d8 |
| |
| /* HDMI base register addresses */ |
| #define R600_HDMI_TMDS1 0x7400 |
| #define R600_HDMI_TMDS2 0x7700 |
| #define R600_HDMI_DIG 0x7800 |
| #define R600_HDMI_BLOCK1 0x7400 |
| #define R600_HDMI_BLOCK2 0x7700 |
| #define R600_HDMI_BLOCK3 0x7800 |
| |
| /* HDMI registers */ |
| #define R600_HDMI_ENABLE 0x00 |
| #define R600_HDMI_STATUS 0x04 |
| # define R600_HDMI_INT_PENDING (1 << 29) |
| #define R600_HDMI_CNTL 0x08 |
| # define R600_HDMI_INT_EN (1 << 28) |
| # define R600_HDMI_INT_ACK (1 << 29) |
| #define R600_HDMI_UNKNOWN_0 0x0C |
| #define R600_HDMI_AUDIOCNTL 0x10 |
| #define R600_HDMI_VIDEOCNTL 0x14 |
| 185,4 → 193,8 |
|---|
| #define R600_HDMI_AUDIO_DEBUG_2 0xe8 |
| #define R600_HDMI_AUDIO_DEBUG_3 0xec |
| |
| /* HDMI additional config base register addresses */ |
| #define R600_HDMI_CONFIG1 0x7600 |
| #define R600_HDMI_CONFIG2 0x7a00 |
| |
| #endif |