Subversion Repositories Kolibri OS

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Regard whitespace Rev 3763 → Rev 3764

/drivers/video/drm/radeon/evergreen.c
53,6 → 53,864
extern void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
int ring, u32 cp_int_cntl);
 
static const u32 evergreen_golden_registers[] =
{
0x3f90, 0xffff0000, 0xff000000,
0x9148, 0xffff0000, 0xff000000,
0x3f94, 0xffff0000, 0xff000000,
0x914c, 0xffff0000, 0xff000000,
0x9b7c, 0xffffffff, 0x00000000,
0x8a14, 0xffffffff, 0x00000007,
0x8b10, 0xffffffff, 0x00000000,
0x960c, 0xffffffff, 0x54763210,
0x88c4, 0xffffffff, 0x000000c2,
0x88d4, 0xffffffff, 0x00000010,
0x8974, 0xffffffff, 0x00000000,
0xc78, 0x00000080, 0x00000080,
0x5eb4, 0xffffffff, 0x00000002,
0x5e78, 0xffffffff, 0x001000f0,
0x6104, 0x01000300, 0x00000000,
0x5bc0, 0x00300000, 0x00000000,
0x7030, 0xffffffff, 0x00000011,
0x7c30, 0xffffffff, 0x00000011,
0x10830, 0xffffffff, 0x00000011,
0x11430, 0xffffffff, 0x00000011,
0x12030, 0xffffffff, 0x00000011,
0x12c30, 0xffffffff, 0x00000011,
0xd02c, 0xffffffff, 0x08421000,
0x240c, 0xffffffff, 0x00000380,
0x8b24, 0xffffffff, 0x00ff0fff,
0x28a4c, 0x06000000, 0x06000000,
0x10c, 0x00000001, 0x00000001,
0x8d00, 0xffffffff, 0x100e4848,
0x8d04, 0xffffffff, 0x00164745,
0x8c00, 0xffffffff, 0xe4000003,
0x8c04, 0xffffffff, 0x40600060,
0x8c08, 0xffffffff, 0x001c001c,
0x8cf0, 0xffffffff, 0x08e00620,
0x8c20, 0xffffffff, 0x00800080,
0x8c24, 0xffffffff, 0x00800080,
0x8c18, 0xffffffff, 0x20202078,
0x8c1c, 0xffffffff, 0x00001010,
0x28350, 0xffffffff, 0x00000000,
0xa008, 0xffffffff, 0x00010000,
0x5cc, 0xffffffff, 0x00000001,
0x9508, 0xffffffff, 0x00000002,
0x913c, 0x0000000f, 0x0000000a
};
 
static const u32 evergreen_golden_registers2[] =
{
0x2f4c, 0xffffffff, 0x00000000,
0x54f4, 0xffffffff, 0x00000000,
0x54f0, 0xffffffff, 0x00000000,
0x5498, 0xffffffff, 0x00000000,
0x549c, 0xffffffff, 0x00000000,
0x5494, 0xffffffff, 0x00000000,
0x53cc, 0xffffffff, 0x00000000,
0x53c8, 0xffffffff, 0x00000000,
0x53c4, 0xffffffff, 0x00000000,
0x53c0, 0xffffffff, 0x00000000,
0x53bc, 0xffffffff, 0x00000000,
0x53b8, 0xffffffff, 0x00000000,
0x53b4, 0xffffffff, 0x00000000,
0x53b0, 0xffffffff, 0x00000000
};
 
static const u32 cypress_mgcg_init[] =
{
0x802c, 0xffffffff, 0xc0000000,
0x5448, 0xffffffff, 0x00000100,
0x55e4, 0xffffffff, 0x00000100,
0x160c, 0xffffffff, 0x00000100,
0x5644, 0xffffffff, 0x00000100,
0xc164, 0xffffffff, 0x00000100,
0x8a18, 0xffffffff, 0x00000100,
0x897c, 0xffffffff, 0x06000100,
0x8b28, 0xffffffff, 0x00000100,
0x9144, 0xffffffff, 0x00000100,
0x9a60, 0xffffffff, 0x00000100,
0x9868, 0xffffffff, 0x00000100,
0x8d58, 0xffffffff, 0x00000100,
0x9510, 0xffffffff, 0x00000100,
0x949c, 0xffffffff, 0x00000100,
0x9654, 0xffffffff, 0x00000100,
0x9030, 0xffffffff, 0x00000100,
0x9034, 0xffffffff, 0x00000100,
0x9038, 0xffffffff, 0x00000100,
0x903c, 0xffffffff, 0x00000100,
0x9040, 0xffffffff, 0x00000100,
0xa200, 0xffffffff, 0x00000100,
0xa204, 0xffffffff, 0x00000100,
0xa208, 0xffffffff, 0x00000100,
0xa20c, 0xffffffff, 0x00000100,
0x971c, 0xffffffff, 0x00000100,
0x977c, 0xffffffff, 0x00000100,
0x3f80, 0xffffffff, 0x00000100,
0xa210, 0xffffffff, 0x00000100,
0xa214, 0xffffffff, 0x00000100,
0x4d8, 0xffffffff, 0x00000100,
0x9784, 0xffffffff, 0x00000100,
0x9698, 0xffffffff, 0x00000100,
0x4d4, 0xffffffff, 0x00000200,
0x30cc, 0xffffffff, 0x00000100,
0xd0c0, 0xffffffff, 0xff000100,
0x802c, 0xffffffff, 0x40000000,
0x915c, 0xffffffff, 0x00010000,
0x9160, 0xffffffff, 0x00030002,
0x9178, 0xffffffff, 0x00070000,
0x917c, 0xffffffff, 0x00030002,
0x9180, 0xffffffff, 0x00050004,
0x918c, 0xffffffff, 0x00010006,
0x9190, 0xffffffff, 0x00090008,
0x9194, 0xffffffff, 0x00070000,
0x9198, 0xffffffff, 0x00030002,
0x919c, 0xffffffff, 0x00050004,
0x91a8, 0xffffffff, 0x00010006,
0x91ac, 0xffffffff, 0x00090008,
0x91b0, 0xffffffff, 0x00070000,
0x91b4, 0xffffffff, 0x00030002,
0x91b8, 0xffffffff, 0x00050004,
0x91c4, 0xffffffff, 0x00010006,
0x91c8, 0xffffffff, 0x00090008,
0x91cc, 0xffffffff, 0x00070000,
0x91d0, 0xffffffff, 0x00030002,
0x91d4, 0xffffffff, 0x00050004,
0x91e0, 0xffffffff, 0x00010006,
0x91e4, 0xffffffff, 0x00090008,
0x91e8, 0xffffffff, 0x00000000,
0x91ec, 0xffffffff, 0x00070000,
0x91f0, 0xffffffff, 0x00030002,
0x91f4, 0xffffffff, 0x00050004,
0x9200, 0xffffffff, 0x00010006,
0x9204, 0xffffffff, 0x00090008,
0x9208, 0xffffffff, 0x00070000,
0x920c, 0xffffffff, 0x00030002,
0x9210, 0xffffffff, 0x00050004,
0x921c, 0xffffffff, 0x00010006,
0x9220, 0xffffffff, 0x00090008,
0x9224, 0xffffffff, 0x00070000,
0x9228, 0xffffffff, 0x00030002,
0x922c, 0xffffffff, 0x00050004,
0x9238, 0xffffffff, 0x00010006,
0x923c, 0xffffffff, 0x00090008,
0x9240, 0xffffffff, 0x00070000,
0x9244, 0xffffffff, 0x00030002,
0x9248, 0xffffffff, 0x00050004,
0x9254, 0xffffffff, 0x00010006,
0x9258, 0xffffffff, 0x00090008,
0x925c, 0xffffffff, 0x00070000,
0x9260, 0xffffffff, 0x00030002,
0x9264, 0xffffffff, 0x00050004,
0x9270, 0xffffffff, 0x00010006,
0x9274, 0xffffffff, 0x00090008,
0x9278, 0xffffffff, 0x00070000,
0x927c, 0xffffffff, 0x00030002,
0x9280, 0xffffffff, 0x00050004,
0x928c, 0xffffffff, 0x00010006,
0x9290, 0xffffffff, 0x00090008,
0x9294, 0xffffffff, 0x00000000,
0x929c, 0xffffffff, 0x00000001,
0x802c, 0xffffffff, 0x40010000,
0x915c, 0xffffffff, 0x00010000,
0x9160, 0xffffffff, 0x00030002,
0x9178, 0xffffffff, 0x00070000,
0x917c, 0xffffffff, 0x00030002,
0x9180, 0xffffffff, 0x00050004,
0x918c, 0xffffffff, 0x00010006,
0x9190, 0xffffffff, 0x00090008,
0x9194, 0xffffffff, 0x00070000,
0x9198, 0xffffffff, 0x00030002,
0x919c, 0xffffffff, 0x00050004,
0x91a8, 0xffffffff, 0x00010006,
0x91ac, 0xffffffff, 0x00090008,
0x91b0, 0xffffffff, 0x00070000,
0x91b4, 0xffffffff, 0x00030002,
0x91b8, 0xffffffff, 0x00050004,
0x91c4, 0xffffffff, 0x00010006,
0x91c8, 0xffffffff, 0x00090008,
0x91cc, 0xffffffff, 0x00070000,
0x91d0, 0xffffffff, 0x00030002,
0x91d4, 0xffffffff, 0x00050004,
0x91e0, 0xffffffff, 0x00010006,
0x91e4, 0xffffffff, 0x00090008,
0x91e8, 0xffffffff, 0x00000000,
0x91ec, 0xffffffff, 0x00070000,
0x91f0, 0xffffffff, 0x00030002,
0x91f4, 0xffffffff, 0x00050004,
0x9200, 0xffffffff, 0x00010006,
0x9204, 0xffffffff, 0x00090008,
0x9208, 0xffffffff, 0x00070000,
0x920c, 0xffffffff, 0x00030002,
0x9210, 0xffffffff, 0x00050004,
0x921c, 0xffffffff, 0x00010006,
0x9220, 0xffffffff, 0x00090008,
0x9224, 0xffffffff, 0x00070000,
0x9228, 0xffffffff, 0x00030002,
0x922c, 0xffffffff, 0x00050004,
0x9238, 0xffffffff, 0x00010006,
0x923c, 0xffffffff, 0x00090008,
0x9240, 0xffffffff, 0x00070000,
0x9244, 0xffffffff, 0x00030002,
0x9248, 0xffffffff, 0x00050004,
0x9254, 0xffffffff, 0x00010006,
0x9258, 0xffffffff, 0x00090008,
0x925c, 0xffffffff, 0x00070000,
0x9260, 0xffffffff, 0x00030002,
0x9264, 0xffffffff, 0x00050004,
0x9270, 0xffffffff, 0x00010006,
0x9274, 0xffffffff, 0x00090008,
0x9278, 0xffffffff, 0x00070000,
0x927c, 0xffffffff, 0x00030002,
0x9280, 0xffffffff, 0x00050004,
0x928c, 0xffffffff, 0x00010006,
0x9290, 0xffffffff, 0x00090008,
0x9294, 0xffffffff, 0x00000000,
0x929c, 0xffffffff, 0x00000001,
0x802c, 0xffffffff, 0xc0000000
};
 
static const u32 redwood_mgcg_init[] =
{
0x802c, 0xffffffff, 0xc0000000,
0x5448, 0xffffffff, 0x00000100,
0x55e4, 0xffffffff, 0x00000100,
0x160c, 0xffffffff, 0x00000100,
0x5644, 0xffffffff, 0x00000100,
0xc164, 0xffffffff, 0x00000100,
0x8a18, 0xffffffff, 0x00000100,
0x897c, 0xffffffff, 0x06000100,
0x8b28, 0xffffffff, 0x00000100,
0x9144, 0xffffffff, 0x00000100,
0x9a60, 0xffffffff, 0x00000100,
0x9868, 0xffffffff, 0x00000100,
0x8d58, 0xffffffff, 0x00000100,
0x9510, 0xffffffff, 0x00000100,
0x949c, 0xffffffff, 0x00000100,
0x9654, 0xffffffff, 0x00000100,
0x9030, 0xffffffff, 0x00000100,
0x9034, 0xffffffff, 0x00000100,
0x9038, 0xffffffff, 0x00000100,
0x903c, 0xffffffff, 0x00000100,
0x9040, 0xffffffff, 0x00000100,
0xa200, 0xffffffff, 0x00000100,
0xa204, 0xffffffff, 0x00000100,
0xa208, 0xffffffff, 0x00000100,
0xa20c, 0xffffffff, 0x00000100,
0x971c, 0xffffffff, 0x00000100,
0x977c, 0xffffffff, 0x00000100,
0x3f80, 0xffffffff, 0x00000100,
0xa210, 0xffffffff, 0x00000100,
0xa214, 0xffffffff, 0x00000100,
0x4d8, 0xffffffff, 0x00000100,
0x9784, 0xffffffff, 0x00000100,
0x9698, 0xffffffff, 0x00000100,
0x4d4, 0xffffffff, 0x00000200,
0x30cc, 0xffffffff, 0x00000100,
0xd0c0, 0xffffffff, 0xff000100,
0x802c, 0xffffffff, 0x40000000,
0x915c, 0xffffffff, 0x00010000,
0x9160, 0xffffffff, 0x00030002,
0x9178, 0xffffffff, 0x00070000,
0x917c, 0xffffffff, 0x00030002,
0x9180, 0xffffffff, 0x00050004,
0x918c, 0xffffffff, 0x00010006,
0x9190, 0xffffffff, 0x00090008,
0x9194, 0xffffffff, 0x00070000,
0x9198, 0xffffffff, 0x00030002,
0x919c, 0xffffffff, 0x00050004,
0x91a8, 0xffffffff, 0x00010006,
0x91ac, 0xffffffff, 0x00090008,
0x91b0, 0xffffffff, 0x00070000,
0x91b4, 0xffffffff, 0x00030002,
0x91b8, 0xffffffff, 0x00050004,
0x91c4, 0xffffffff, 0x00010006,
0x91c8, 0xffffffff, 0x00090008,
0x91cc, 0xffffffff, 0x00070000,
0x91d0, 0xffffffff, 0x00030002,
0x91d4, 0xffffffff, 0x00050004,
0x91e0, 0xffffffff, 0x00010006,
0x91e4, 0xffffffff, 0x00090008,
0x91e8, 0xffffffff, 0x00000000,
0x91ec, 0xffffffff, 0x00070000,
0x91f0, 0xffffffff, 0x00030002,
0x91f4, 0xffffffff, 0x00050004,
0x9200, 0xffffffff, 0x00010006,
0x9204, 0xffffffff, 0x00090008,
0x9294, 0xffffffff, 0x00000000,
0x929c, 0xffffffff, 0x00000001,
0x802c, 0xffffffff, 0xc0000000
};
 
static const u32 cedar_golden_registers[] =
{
0x3f90, 0xffff0000, 0xff000000,
0x9148, 0xffff0000, 0xff000000,
0x3f94, 0xffff0000, 0xff000000,
0x914c, 0xffff0000, 0xff000000,
0x9b7c, 0xffffffff, 0x00000000,
0x8a14, 0xffffffff, 0x00000007,
0x8b10, 0xffffffff, 0x00000000,
0x960c, 0xffffffff, 0x54763210,
0x88c4, 0xffffffff, 0x000000c2,
0x88d4, 0xffffffff, 0x00000000,
0x8974, 0xffffffff, 0x00000000,
0xc78, 0x00000080, 0x00000080,
0x5eb4, 0xffffffff, 0x00000002,
0x5e78, 0xffffffff, 0x001000f0,
0x6104, 0x01000300, 0x00000000,
0x5bc0, 0x00300000, 0x00000000,
0x7030, 0xffffffff, 0x00000011,
0x7c30, 0xffffffff, 0x00000011,
0x10830, 0xffffffff, 0x00000011,
0x11430, 0xffffffff, 0x00000011,
0xd02c, 0xffffffff, 0x08421000,
0x240c, 0xffffffff, 0x00000380,
0x8b24, 0xffffffff, 0x00ff0fff,
0x28a4c, 0x06000000, 0x06000000,
0x10c, 0x00000001, 0x00000001,
0x8d00, 0xffffffff, 0x100e4848,
0x8d04, 0xffffffff, 0x00164745,
0x8c00, 0xffffffff, 0xe4000003,
0x8c04, 0xffffffff, 0x40600060,
0x8c08, 0xffffffff, 0x001c001c,
0x8cf0, 0xffffffff, 0x08e00410,
0x8c20, 0xffffffff, 0x00800080,
0x8c24, 0xffffffff, 0x00800080,
0x8c18, 0xffffffff, 0x20202078,
0x8c1c, 0xffffffff, 0x00001010,
0x28350, 0xffffffff, 0x00000000,
0xa008, 0xffffffff, 0x00010000,
0x5cc, 0xffffffff, 0x00000001,
0x9508, 0xffffffff, 0x00000002
};
 
static const u32 cedar_mgcg_init[] =
{
0x802c, 0xffffffff, 0xc0000000,
0x5448, 0xffffffff, 0x00000100,
0x55e4, 0xffffffff, 0x00000100,
0x160c, 0xffffffff, 0x00000100,
0x5644, 0xffffffff, 0x00000100,
0xc164, 0xffffffff, 0x00000100,
0x8a18, 0xffffffff, 0x00000100,
0x897c, 0xffffffff, 0x06000100,
0x8b28, 0xffffffff, 0x00000100,
0x9144, 0xffffffff, 0x00000100,
0x9a60, 0xffffffff, 0x00000100,
0x9868, 0xffffffff, 0x00000100,
0x8d58, 0xffffffff, 0x00000100,
0x9510, 0xffffffff, 0x00000100,
0x949c, 0xffffffff, 0x00000100,
0x9654, 0xffffffff, 0x00000100,
0x9030, 0xffffffff, 0x00000100,
0x9034, 0xffffffff, 0x00000100,
0x9038, 0xffffffff, 0x00000100,
0x903c, 0xffffffff, 0x00000100,
0x9040, 0xffffffff, 0x00000100,
0xa200, 0xffffffff, 0x00000100,
0xa204, 0xffffffff, 0x00000100,
0xa208, 0xffffffff, 0x00000100,
0xa20c, 0xffffffff, 0x00000100,
0x971c, 0xffffffff, 0x00000100,
0x977c, 0xffffffff, 0x00000100,
0x3f80, 0xffffffff, 0x00000100,
0xa210, 0xffffffff, 0x00000100,
0xa214, 0xffffffff, 0x00000100,
0x4d8, 0xffffffff, 0x00000100,
0x9784, 0xffffffff, 0x00000100,
0x9698, 0xffffffff, 0x00000100,
0x4d4, 0xffffffff, 0x00000200,
0x30cc, 0xffffffff, 0x00000100,
0xd0c0, 0xffffffff, 0xff000100,
0x802c, 0xffffffff, 0x40000000,
0x915c, 0xffffffff, 0x00010000,
0x9178, 0xffffffff, 0x00050000,
0x917c, 0xffffffff, 0x00030002,
0x918c, 0xffffffff, 0x00010004,
0x9190, 0xffffffff, 0x00070006,
0x9194, 0xffffffff, 0x00050000,
0x9198, 0xffffffff, 0x00030002,
0x91a8, 0xffffffff, 0x00010004,
0x91ac, 0xffffffff, 0x00070006,
0x91e8, 0xffffffff, 0x00000000,
0x9294, 0xffffffff, 0x00000000,
0x929c, 0xffffffff, 0x00000001,
0x802c, 0xffffffff, 0xc0000000
};
 
static const u32 juniper_mgcg_init[] =
{
0x802c, 0xffffffff, 0xc0000000,
0x5448, 0xffffffff, 0x00000100,
0x55e4, 0xffffffff, 0x00000100,
0x160c, 0xffffffff, 0x00000100,
0x5644, 0xffffffff, 0x00000100,
0xc164, 0xffffffff, 0x00000100,
0x8a18, 0xffffffff, 0x00000100,
0x897c, 0xffffffff, 0x06000100,
0x8b28, 0xffffffff, 0x00000100,
0x9144, 0xffffffff, 0x00000100,
0x9a60, 0xffffffff, 0x00000100,
0x9868, 0xffffffff, 0x00000100,
0x8d58, 0xffffffff, 0x00000100,
0x9510, 0xffffffff, 0x00000100,
0x949c, 0xffffffff, 0x00000100,
0x9654, 0xffffffff, 0x00000100,
0x9030, 0xffffffff, 0x00000100,
0x9034, 0xffffffff, 0x00000100,
0x9038, 0xffffffff, 0x00000100,
0x903c, 0xffffffff, 0x00000100,
0x9040, 0xffffffff, 0x00000100,
0xa200, 0xffffffff, 0x00000100,
0xa204, 0xffffffff, 0x00000100,
0xa208, 0xffffffff, 0x00000100,
0xa20c, 0xffffffff, 0x00000100,
0x971c, 0xffffffff, 0x00000100,
0xd0c0, 0xffffffff, 0xff000100,
0x802c, 0xffffffff, 0x40000000,
0x915c, 0xffffffff, 0x00010000,
0x9160, 0xffffffff, 0x00030002,
0x9178, 0xffffffff, 0x00070000,
0x917c, 0xffffffff, 0x00030002,
0x9180, 0xffffffff, 0x00050004,
0x918c, 0xffffffff, 0x00010006,
0x9190, 0xffffffff, 0x00090008,
0x9194, 0xffffffff, 0x00070000,
0x9198, 0xffffffff, 0x00030002,
0x919c, 0xffffffff, 0x00050004,
0x91a8, 0xffffffff, 0x00010006,
0x91ac, 0xffffffff, 0x00090008,
0x91b0, 0xffffffff, 0x00070000,
0x91b4, 0xffffffff, 0x00030002,
0x91b8, 0xffffffff, 0x00050004,
0x91c4, 0xffffffff, 0x00010006,
0x91c8, 0xffffffff, 0x00090008,
0x91cc, 0xffffffff, 0x00070000,
0x91d0, 0xffffffff, 0x00030002,
0x91d4, 0xffffffff, 0x00050004,
0x91e0, 0xffffffff, 0x00010006,
0x91e4, 0xffffffff, 0x00090008,
0x91e8, 0xffffffff, 0x00000000,
0x91ec, 0xffffffff, 0x00070000,
0x91f0, 0xffffffff, 0x00030002,
0x91f4, 0xffffffff, 0x00050004,
0x9200, 0xffffffff, 0x00010006,
0x9204, 0xffffffff, 0x00090008,
0x9208, 0xffffffff, 0x00070000,
0x920c, 0xffffffff, 0x00030002,
0x9210, 0xffffffff, 0x00050004,
0x921c, 0xffffffff, 0x00010006,
0x9220, 0xffffffff, 0x00090008,
0x9224, 0xffffffff, 0x00070000,
0x9228, 0xffffffff, 0x00030002,
0x922c, 0xffffffff, 0x00050004,
0x9238, 0xffffffff, 0x00010006,
0x923c, 0xffffffff, 0x00090008,
0x9240, 0xffffffff, 0x00070000,
0x9244, 0xffffffff, 0x00030002,
0x9248, 0xffffffff, 0x00050004,
0x9254, 0xffffffff, 0x00010006,
0x9258, 0xffffffff, 0x00090008,
0x925c, 0xffffffff, 0x00070000,
0x9260, 0xffffffff, 0x00030002,
0x9264, 0xffffffff, 0x00050004,
0x9270, 0xffffffff, 0x00010006,
0x9274, 0xffffffff, 0x00090008,
0x9278, 0xffffffff, 0x00070000,
0x927c, 0xffffffff, 0x00030002,
0x9280, 0xffffffff, 0x00050004,
0x928c, 0xffffffff, 0x00010006,
0x9290, 0xffffffff, 0x00090008,
0x9294, 0xffffffff, 0x00000000,
0x929c, 0xffffffff, 0x00000001,
0x802c, 0xffffffff, 0xc0000000,
0x977c, 0xffffffff, 0x00000100,
0x3f80, 0xffffffff, 0x00000100,
0xa210, 0xffffffff, 0x00000100,
0xa214, 0xffffffff, 0x00000100,
0x4d8, 0xffffffff, 0x00000100,
0x9784, 0xffffffff, 0x00000100,
0x9698, 0xffffffff, 0x00000100,
0x4d4, 0xffffffff, 0x00000200,
0x30cc, 0xffffffff, 0x00000100,
0x802c, 0xffffffff, 0xc0000000
};
 
static const u32 supersumo_golden_registers[] =
{
0x5eb4, 0xffffffff, 0x00000002,
0x5cc, 0xffffffff, 0x00000001,
0x7030, 0xffffffff, 0x00000011,
0x7c30, 0xffffffff, 0x00000011,
0x6104, 0x01000300, 0x00000000,
0x5bc0, 0x00300000, 0x00000000,
0x8c04, 0xffffffff, 0x40600060,
0x8c08, 0xffffffff, 0x001c001c,
0x8c20, 0xffffffff, 0x00800080,
0x8c24, 0xffffffff, 0x00800080,
0x8c18, 0xffffffff, 0x20202078,
0x8c1c, 0xffffffff, 0x00001010,
0x918c, 0xffffffff, 0x00010006,
0x91a8, 0xffffffff, 0x00010006,
0x91c4, 0xffffffff, 0x00010006,
0x91e0, 0xffffffff, 0x00010006,
0x9200, 0xffffffff, 0x00010006,
0x9150, 0xffffffff, 0x6e944040,
0x917c, 0xffffffff, 0x00030002,
0x9180, 0xffffffff, 0x00050004,
0x9198, 0xffffffff, 0x00030002,
0x919c, 0xffffffff, 0x00050004,
0x91b4, 0xffffffff, 0x00030002,
0x91b8, 0xffffffff, 0x00050004,
0x91d0, 0xffffffff, 0x00030002,
0x91d4, 0xffffffff, 0x00050004,
0x91f0, 0xffffffff, 0x00030002,
0x91f4, 0xffffffff, 0x00050004,
0x915c, 0xffffffff, 0x00010000,
0x9160, 0xffffffff, 0x00030002,
0x3f90, 0xffff0000, 0xff000000,
0x9178, 0xffffffff, 0x00070000,
0x9194, 0xffffffff, 0x00070000,
0x91b0, 0xffffffff, 0x00070000,
0x91cc, 0xffffffff, 0x00070000,
0x91ec, 0xffffffff, 0x00070000,
0x9148, 0xffff0000, 0xff000000,
0x9190, 0xffffffff, 0x00090008,
0x91ac, 0xffffffff, 0x00090008,
0x91c8, 0xffffffff, 0x00090008,
0x91e4, 0xffffffff, 0x00090008,
0x9204, 0xffffffff, 0x00090008,
0x3f94, 0xffff0000, 0xff000000,
0x914c, 0xffff0000, 0xff000000,
0x929c, 0xffffffff, 0x00000001,
0x8a18, 0xffffffff, 0x00000100,
0x8b28, 0xffffffff, 0x00000100,
0x9144, 0xffffffff, 0x00000100,
0x5644, 0xffffffff, 0x00000100,
0x9b7c, 0xffffffff, 0x00000000,
0x8030, 0xffffffff, 0x0000100a,
0x8a14, 0xffffffff, 0x00000007,
0x8b24, 0xffffffff, 0x00ff0fff,
0x8b10, 0xffffffff, 0x00000000,
0x28a4c, 0x06000000, 0x06000000,
0x4d8, 0xffffffff, 0x00000100,
0x913c, 0xffff000f, 0x0100000a,
0x960c, 0xffffffff, 0x54763210,
0x88c4, 0xffffffff, 0x000000c2,
0x88d4, 0xffffffff, 0x00000010,
0x8974, 0xffffffff, 0x00000000,
0xc78, 0x00000080, 0x00000080,
0x5e78, 0xffffffff, 0x001000f0,
0xd02c, 0xffffffff, 0x08421000,
0xa008, 0xffffffff, 0x00010000,
0x8d00, 0xffffffff, 0x100e4848,
0x8d04, 0xffffffff, 0x00164745,
0x8c00, 0xffffffff, 0xe4000003,
0x8cf0, 0x1fffffff, 0x08e00620,
0x28350, 0xffffffff, 0x00000000,
0x9508, 0xffffffff, 0x00000002
};
 
static const u32 sumo_golden_registers[] =
{
0x900c, 0x00ffffff, 0x0017071f,
0x8c18, 0xffffffff, 0x10101060,
0x8c1c, 0xffffffff, 0x00001010,
0x8c30, 0x0000000f, 0x00000005,
0x9688, 0x0000000f, 0x00000007
};
 
static const u32 wrestler_golden_registers[] =
{
0x5eb4, 0xffffffff, 0x00000002,
0x5cc, 0xffffffff, 0x00000001,
0x7030, 0xffffffff, 0x00000011,
0x7c30, 0xffffffff, 0x00000011,
0x6104, 0x01000300, 0x00000000,
0x5bc0, 0x00300000, 0x00000000,
0x918c, 0xffffffff, 0x00010006,
0x91a8, 0xffffffff, 0x00010006,
0x9150, 0xffffffff, 0x6e944040,
0x917c, 0xffffffff, 0x00030002,
0x9198, 0xffffffff, 0x00030002,
0x915c, 0xffffffff, 0x00010000,
0x3f90, 0xffff0000, 0xff000000,
0x9178, 0xffffffff, 0x00070000,
0x9194, 0xffffffff, 0x00070000,
0x9148, 0xffff0000, 0xff000000,
0x9190, 0xffffffff, 0x00090008,
0x91ac, 0xffffffff, 0x00090008,
0x3f94, 0xffff0000, 0xff000000,
0x914c, 0xffff0000, 0xff000000,
0x929c, 0xffffffff, 0x00000001,
0x8a18, 0xffffffff, 0x00000100,
0x8b28, 0xffffffff, 0x00000100,
0x9144, 0xffffffff, 0x00000100,
0x9b7c, 0xffffffff, 0x00000000,
0x8030, 0xffffffff, 0x0000100a,
0x8a14, 0xffffffff, 0x00000001,
0x8b24, 0xffffffff, 0x00ff0fff,
0x8b10, 0xffffffff, 0x00000000,
0x28a4c, 0x06000000, 0x06000000,
0x4d8, 0xffffffff, 0x00000100,
0x913c, 0xffff000f, 0x0100000a,
0x960c, 0xffffffff, 0x54763210,
0x88c4, 0xffffffff, 0x000000c2,
0x88d4, 0xffffffff, 0x00000010,
0x8974, 0xffffffff, 0x00000000,
0xc78, 0x00000080, 0x00000080,
0x5e78, 0xffffffff, 0x001000f0,
0xd02c, 0xffffffff, 0x08421000,
0xa008, 0xffffffff, 0x00010000,
0x8d00, 0xffffffff, 0x100e4848,
0x8d04, 0xffffffff, 0x00164745,
0x8c00, 0xffffffff, 0xe4000003,
0x8cf0, 0x1fffffff, 0x08e00410,
0x28350, 0xffffffff, 0x00000000,
0x9508, 0xffffffff, 0x00000002,
0x900c, 0xffffffff, 0x0017071f,
0x8c18, 0xffffffff, 0x10101060,
0x8c1c, 0xffffffff, 0x00001010
};
 
static const u32 barts_golden_registers[] =
{
0x5eb4, 0xffffffff, 0x00000002,
0x5e78, 0x8f311ff1, 0x001000f0,
0x3f90, 0xffff0000, 0xff000000,
0x9148, 0xffff0000, 0xff000000,
0x3f94, 0xffff0000, 0xff000000,
0x914c, 0xffff0000, 0xff000000,
0xc78, 0x00000080, 0x00000080,
0xbd4, 0x70073777, 0x00010001,
0xd02c, 0xbfffff1f, 0x08421000,
0xd0b8, 0x03773777, 0x02011003,
0x5bc0, 0x00200000, 0x50100000,
0x98f8, 0x33773777, 0x02011003,
0x98fc, 0xffffffff, 0x76543210,
0x7030, 0x31000311, 0x00000011,
0x2f48, 0x00000007, 0x02011003,
0x6b28, 0x00000010, 0x00000012,
0x7728, 0x00000010, 0x00000012,
0x10328, 0x00000010, 0x00000012,
0x10f28, 0x00000010, 0x00000012,
0x11b28, 0x00000010, 0x00000012,
0x12728, 0x00000010, 0x00000012,
0x240c, 0x000007ff, 0x00000380,
0x8a14, 0xf000001f, 0x00000007,
0x8b24, 0x3fff3fff, 0x00ff0fff,
0x8b10, 0x0000ff0f, 0x00000000,
0x28a4c, 0x07ffffff, 0x06000000,
0x10c, 0x00000001, 0x00010003,
0xa02c, 0xffffffff, 0x0000009b,
0x913c, 0x0000000f, 0x0100000a,
0x8d00, 0xffff7f7f, 0x100e4848,
0x8d04, 0x00ffffff, 0x00164745,
0x8c00, 0xfffc0003, 0xe4000003,
0x8c04, 0xf8ff00ff, 0x40600060,
0x8c08, 0x00ff00ff, 0x001c001c,
0x8cf0, 0x1fff1fff, 0x08e00620,
0x8c20, 0x0fff0fff, 0x00800080,
0x8c24, 0x0fff0fff, 0x00800080,
0x8c18, 0xffffffff, 0x20202078,
0x8c1c, 0x0000ffff, 0x00001010,
0x28350, 0x00000f01, 0x00000000,
0x9508, 0x3700001f, 0x00000002,
0x960c, 0xffffffff, 0x54763210,
0x88c4, 0x001f3ae3, 0x000000c2,
0x88d4, 0x0000001f, 0x00000010,
0x8974, 0xffffffff, 0x00000000
};
 
static const u32 turks_golden_registers[] =
{
0x5eb4, 0xffffffff, 0x00000002,
0x5e78, 0x8f311ff1, 0x001000f0,
0x8c8, 0x00003000, 0x00001070,
0x8cc, 0x000fffff, 0x00040035,
0x3f90, 0xffff0000, 0xfff00000,
0x9148, 0xffff0000, 0xfff00000,
0x3f94, 0xffff0000, 0xfff00000,
0x914c, 0xffff0000, 0xfff00000,
0xc78, 0x00000080, 0x00000080,
0xbd4, 0x00073007, 0x00010002,
0xd02c, 0xbfffff1f, 0x08421000,
0xd0b8, 0x03773777, 0x02010002,
0x5bc0, 0x00200000, 0x50100000,
0x98f8, 0x33773777, 0x00010002,
0x98fc, 0xffffffff, 0x33221100,
0x7030, 0x31000311, 0x00000011,
0x2f48, 0x33773777, 0x00010002,
0x6b28, 0x00000010, 0x00000012,
0x7728, 0x00000010, 0x00000012,
0x10328, 0x00000010, 0x00000012,
0x10f28, 0x00000010, 0x00000012,
0x11b28, 0x00000010, 0x00000012,
0x12728, 0x00000010, 0x00000012,
0x240c, 0x000007ff, 0x00000380,
0x8a14, 0xf000001f, 0x00000007,
0x8b24, 0x3fff3fff, 0x00ff0fff,
0x8b10, 0x0000ff0f, 0x00000000,
0x28a4c, 0x07ffffff, 0x06000000,
0x10c, 0x00000001, 0x00010003,
0xa02c, 0xffffffff, 0x0000009b,
0x913c, 0x0000000f, 0x0100000a,
0x8d00, 0xffff7f7f, 0x100e4848,
0x8d04, 0x00ffffff, 0x00164745,
0x8c00, 0xfffc0003, 0xe4000003,
0x8c04, 0xf8ff00ff, 0x40600060,
0x8c08, 0x00ff00ff, 0x001c001c,
0x8cf0, 0x1fff1fff, 0x08e00410,
0x8c20, 0x0fff0fff, 0x00800080,
0x8c24, 0x0fff0fff, 0x00800080,
0x8c18, 0xffffffff, 0x20202078,
0x8c1c, 0x0000ffff, 0x00001010,
0x28350, 0x00000f01, 0x00000000,
0x9508, 0x3700001f, 0x00000002,
0x960c, 0xffffffff, 0x54763210,
0x88c4, 0x001f3ae3, 0x000000c2,
0x88d4, 0x0000001f, 0x00000010,
0x8974, 0xffffffff, 0x00000000
};
 
static const u32 caicos_golden_registers[] =
{
0x5eb4, 0xffffffff, 0x00000002,
0x5e78, 0x8f311ff1, 0x001000f0,
0x8c8, 0x00003420, 0x00001450,
0x8cc, 0x000fffff, 0x00040035,
0x3f90, 0xffff0000, 0xfffc0000,
0x9148, 0xffff0000, 0xfffc0000,
0x3f94, 0xffff0000, 0xfffc0000,
0x914c, 0xffff0000, 0xfffc0000,
0xc78, 0x00000080, 0x00000080,
0xbd4, 0x00073007, 0x00010001,
0xd02c, 0xbfffff1f, 0x08421000,
0xd0b8, 0x03773777, 0x02010001,
0x5bc0, 0x00200000, 0x50100000,
0x98f8, 0x33773777, 0x02010001,
0x98fc, 0xffffffff, 0x33221100,
0x7030, 0x31000311, 0x00000011,
0x2f48, 0x33773777, 0x02010001,
0x6b28, 0x00000010, 0x00000012,
0x7728, 0x00000010, 0x00000012,
0x10328, 0x00000010, 0x00000012,
0x10f28, 0x00000010, 0x00000012,
0x11b28, 0x00000010, 0x00000012,
0x12728, 0x00000010, 0x00000012,
0x240c, 0x000007ff, 0x00000380,
0x8a14, 0xf000001f, 0x00000001,
0x8b24, 0x3fff3fff, 0x00ff0fff,
0x8b10, 0x0000ff0f, 0x00000000,
0x28a4c, 0x07ffffff, 0x06000000,
0x10c, 0x00000001, 0x00010003,
0xa02c, 0xffffffff, 0x0000009b,
0x913c, 0x0000000f, 0x0100000a,
0x8d00, 0xffff7f7f, 0x100e4848,
0x8d04, 0x00ffffff, 0x00164745,
0x8c00, 0xfffc0003, 0xe4000003,
0x8c04, 0xf8ff00ff, 0x40600060,
0x8c08, 0x00ff00ff, 0x001c001c,
0x8cf0, 0x1fff1fff, 0x08e00410,
0x8c20, 0x0fff0fff, 0x00800080,
0x8c24, 0x0fff0fff, 0x00800080,
0x8c18, 0xffffffff, 0x20202078,
0x8c1c, 0x0000ffff, 0x00001010,
0x28350, 0x00000f01, 0x00000000,
0x9508, 0x3700001f, 0x00000002,
0x960c, 0xffffffff, 0x54763210,
0x88c4, 0x001f3ae3, 0x000000c2,
0x88d4, 0x0000001f, 0x00000010,
0x8974, 0xffffffff, 0x00000000
};
 
static void evergreen_init_golden_registers(struct radeon_device *rdev)
{
switch (rdev->family) {
case CHIP_CYPRESS:
case CHIP_HEMLOCK:
radeon_program_register_sequence(rdev,
evergreen_golden_registers,
(const u32)ARRAY_SIZE(evergreen_golden_registers));
radeon_program_register_sequence(rdev,
evergreen_golden_registers2,
(const u32)ARRAY_SIZE(evergreen_golden_registers2));
radeon_program_register_sequence(rdev,
cypress_mgcg_init,
(const u32)ARRAY_SIZE(cypress_mgcg_init));
break;
case CHIP_JUNIPER:
radeon_program_register_sequence(rdev,
evergreen_golden_registers,
(const u32)ARRAY_SIZE(evergreen_golden_registers));
radeon_program_register_sequence(rdev,
evergreen_golden_registers2,
(const u32)ARRAY_SIZE(evergreen_golden_registers2));
radeon_program_register_sequence(rdev,
juniper_mgcg_init,
(const u32)ARRAY_SIZE(juniper_mgcg_init));
break;
case CHIP_REDWOOD:
radeon_program_register_sequence(rdev,
evergreen_golden_registers,
(const u32)ARRAY_SIZE(evergreen_golden_registers));
radeon_program_register_sequence(rdev,
evergreen_golden_registers2,
(const u32)ARRAY_SIZE(evergreen_golden_registers2));
radeon_program_register_sequence(rdev,
redwood_mgcg_init,
(const u32)ARRAY_SIZE(redwood_mgcg_init));
break;
case CHIP_CEDAR:
radeon_program_register_sequence(rdev,
cedar_golden_registers,
(const u32)ARRAY_SIZE(cedar_golden_registers));
radeon_program_register_sequence(rdev,
evergreen_golden_registers2,
(const u32)ARRAY_SIZE(evergreen_golden_registers2));
radeon_program_register_sequence(rdev,
cedar_mgcg_init,
(const u32)ARRAY_SIZE(cedar_mgcg_init));
break;
case CHIP_PALM:
radeon_program_register_sequence(rdev,
wrestler_golden_registers,
(const u32)ARRAY_SIZE(wrestler_golden_registers));
break;
case CHIP_SUMO:
radeon_program_register_sequence(rdev,
supersumo_golden_registers,
(const u32)ARRAY_SIZE(supersumo_golden_registers));
break;
case CHIP_SUMO2:
radeon_program_register_sequence(rdev,
supersumo_golden_registers,
(const u32)ARRAY_SIZE(supersumo_golden_registers));
radeon_program_register_sequence(rdev,
sumo_golden_registers,
(const u32)ARRAY_SIZE(sumo_golden_registers));
break;
case CHIP_BARTS:
radeon_program_register_sequence(rdev,
barts_golden_registers,
(const u32)ARRAY_SIZE(barts_golden_registers));
break;
case CHIP_TURKS:
radeon_program_register_sequence(rdev,
turks_golden_registers,
(const u32)ARRAY_SIZE(turks_golden_registers));
break;
case CHIP_CAICOS:
radeon_program_register_sequence(rdev,
caicos_golden_registers,
(const u32)ARRAY_SIZE(caicos_golden_registers));
break;
default:
break;
}
}
 
void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
unsigned *bankh, unsigned *mtaspect,
unsigned *tile_split)
84,6 → 942,142
}
}
 
static int sumo_set_uvd_clock(struct radeon_device *rdev, u32 clock,
u32 cntl_reg, u32 status_reg)
{
int r, i;
struct atom_clock_dividers dividers;
 
r = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
clock, false, &dividers);
if (r)
return r;
 
WREG32_P(cntl_reg, dividers.post_div, ~(DCLK_DIR_CNTL_EN|DCLK_DIVIDER_MASK));
 
for (i = 0; i < 100; i++) {
if (RREG32(status_reg) & DCLK_STATUS)
break;
mdelay(10);
}
if (i == 100)
return -ETIMEDOUT;
 
return 0;
}
 
int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
{
int r = 0;
u32 cg_scratch = RREG32(CG_SCRATCH1);
 
r = sumo_set_uvd_clock(rdev, vclk, CG_VCLK_CNTL, CG_VCLK_STATUS);
if (r)
goto done;
cg_scratch &= 0xffff0000;
cg_scratch |= vclk / 100; /* Mhz */
 
r = sumo_set_uvd_clock(rdev, dclk, CG_DCLK_CNTL, CG_DCLK_STATUS);
if (r)
goto done;
cg_scratch &= 0x0000ffff;
cg_scratch |= (dclk / 100) << 16; /* Mhz */
 
done:
WREG32(CG_SCRATCH1, cg_scratch);
 
return r;
}
 
int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
{
/* start off with something large */
unsigned fb_div = 0, vclk_div = 0, dclk_div = 0;
int r;
 
/* bypass vclk and dclk with bclk */
WREG32_P(CG_UPLL_FUNC_CNTL_2,
VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1),
~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
 
/* put PLL in bypass mode */
WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);
 
if (!vclk || !dclk) {
/* keep the Bypass mode, put PLL to sleep */
WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
return 0;
}
 
// r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 125000, 250000,
// 16384, 0x03FFFFFF, 0, 128, 5,
// &fb_div, &vclk_div, &dclk_div);
if (r)
return r;
 
/* set VCO_MODE to 1 */
WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK);
 
/* toggle UPLL_SLEEP to 1 then back to 0 */
WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK);
 
/* deassert UPLL_RESET */
WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
 
mdelay(1);
 
// r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
// if (r)
// return r;
 
/* assert UPLL_RESET again */
WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);
 
/* disable spread spectrum. */
WREG32_P(CG_UPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK);
 
/* set feedback divider */
WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK);
 
/* set ref divider to 0 */
WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_REF_DIV_MASK);
 
if (fb_div < 307200)
WREG32_P(CG_UPLL_FUNC_CNTL_4, 0, ~UPLL_SPARE_ISPARE9);
else
WREG32_P(CG_UPLL_FUNC_CNTL_4, UPLL_SPARE_ISPARE9, ~UPLL_SPARE_ISPARE9);
 
/* set PDIV_A and PDIV_B */
WREG32_P(CG_UPLL_FUNC_CNTL_2,
UPLL_PDIV_A(vclk_div) | UPLL_PDIV_B(dclk_div),
~(UPLL_PDIV_A_MASK | UPLL_PDIV_B_MASK));
 
/* give the PLL some time to settle */
mdelay(15);
 
/* deassert PLL_RESET */
WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
 
mdelay(15);
 
/* switch from bypass mode to normal mode */
WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);
 
// r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
// if (r)
// return r;
 
/* switch VCLK and DCLK selection */
WREG32_P(CG_UPLL_FUNC_CNTL_2,
VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2),
~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
 
mdelay(100);
 
return 0;
}
 
void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
{
u16 ctl, v;
105,6 → 1099,27
}
}
 
static bool dce4_is_in_vblank(struct radeon_device *rdev, int crtc)
{
if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK)
return true;
else
return false;
}
 
static bool dce4_is_counter_moving(struct radeon_device *rdev, int crtc)
{
u32 pos1, pos2;
 
pos1 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]);
pos2 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]);
 
if (pos1 != pos2)
return true;
else
return false;
}
 
/**
* dce4_wait_for_vblank - vblank wait asic callback.
*
115,21 → 1130,28
*/
void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc)
{
int i;
unsigned i = 0;
 
if (crtc >= rdev->num_crtc)
return;
 
if (RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN) {
for (i = 0; i < rdev->usec_timeout; i++) {
if (!(RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK))
if (!(RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN))
return;
 
/* depending on when we hit vblank, we may be close to active; if so,
* wait for another frame.
*/
while (dce4_is_in_vblank(rdev, crtc)) {
if (i++ % 100 == 0) {
if (!dce4_is_counter_moving(rdev, crtc))
break;
udelay(1);
}
for (i = 0; i < rdev->usec_timeout; i++) {
if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK)
}
 
while (!dce4_is_in_vblank(rdev, crtc)) {
if (i++ % 100 == 0) {
if (!dce4_is_counter_moving(rdev, crtc))
break;
udelay(1);
}
}
}
293,6 → 1315,64
}
 
/**
* btc_pm_init_profile - Initialize power profiles callback.
*
* @rdev: radeon_device pointer
*
* Initialize the power states used in profile mode
* (BTC, cayman).
* Used for profile mode only.
*/
void btc_pm_init_profile(struct radeon_device *rdev)
{
int idx;
 
/* default */
rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
/* starting with BTC, there is one state that is used for both
* MH and SH. Difference is that we always use the high clock index for
* mclk.
*/
if (rdev->flags & RADEON_IS_MOBILITY)
idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
else
idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
/* low sh */
rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
/* mid sh */
rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
/* high sh */
rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
/* low mh */
rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
/* mid mh */
rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
/* high mh */
rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
}
 
/**
* evergreen_pm_misc - set additional pm hw parameters callback.
*
* @rdev: radeon_device pointer
316,6 → 1396,19
rdev->pm.current_vddc = voltage->voltage;
DRM_DEBUG("Setting: vddc: %d\n", voltage->voltage);
}
 
/* starting with BTC, there is one state that is used for both
* MH and SH. Difference is that we always use the high clock index for
* mclk and vddci.
*/
if ((rdev->pm.pm_method == PM_METHOD_PROFILE) &&
(rdev->family >= CHIP_BARTS) &&
rdev->pm.active_crtc_count &&
((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) ||
(rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX)))
voltage = &rdev->pm.power_state[req_ps_idx].
clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].voltage;
 
/* 0xff01 is a flag rather then an actual voltage */
if (voltage->vddci == 0xff01)
return;
508,6 → 1601,16
 
list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 
if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
/* don't try to enable hpd on eDP or LVDS avoid breaking the
* aux dp channel on imac and help (but not completely fix)
* https://bugzilla.redhat.com/show_bug.cgi?id=726143
* also avoid interrupt storms during dpms.
*/
continue;
}
switch (radeon_connector->hpd.hpd) {
case RADEON_HPD_1:
WREG32(DC_HPD1_CONTROL, tmp);
1211,11 → 2314,13
u32 crtc_enabled, tmp, frame_count, blackout;
int i, j;
 
if (!ASIC_IS_NODCE(rdev)) {
save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
 
/* disable VGA render */
WREG32(VGA_RENDER_CONTROL, 0);
}
/* blank the display controllers */
for (i = 0; i < rdev->num_crtc; i++) {
crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN;
1225,6 → 2330,7
tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
if (!(tmp & EVERGREEN_CRTC_BLANK_DATA_EN)) {
radeon_wait_for_vblank(rdev, i);
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
}
1232,8 → 2338,10
tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
if (!(tmp & EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE)) {
radeon_wait_for_vblank(rdev, i);
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
}
}
/* wait for the next frame */
1243,6 → 2351,15
break;
udelay(1);
}
 
/* XXX this is a hack to avoid strange behavior with EFI on certain systems */
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
tmp &= ~EVERGREEN_CRTC_MASTER_EN;
WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
save->crtc_enabled[i] = false;
/* ***** */
} else {
save->crtc_enabled[i] = false;
}
1258,7 → 2375,25
blackout &= ~BLACKOUT_MODE_MASK;
WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1);
}
/* wait for the MC to settle */
udelay(100);
 
/* lock double buffered regs */
for (i = 0; i < rdev->num_crtc; i++) {
if (save->crtc_enabled[i]) {
tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
if (!(tmp & EVERGREEN_GRPH_UPDATE_LOCK)) {
tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp);
}
tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]);
if (!(tmp & 1)) {
tmp |= 1;
WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
}
}
}
}
 
void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
{
1276,9 → 2411,39
WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
(u32)rdev->mc.vram_start);
}
 
if (!ASIC_IS_NODCE(rdev)) {
WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
}
 
/* unlock regs and wait for update */
for (i = 0; i < rdev->num_crtc; i++) {
if (save->crtc_enabled[i]) {
tmp = RREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i]);
if ((tmp & 0x3) != 0) {
tmp &= ~0x3;
WREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
}
tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
if (tmp & EVERGREEN_GRPH_UPDATE_LOCK) {
tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp);
}
tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]);
if (tmp & 1) {
tmp &= ~1;
WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
}
for (j = 0; j < rdev->usec_timeout; j++) {
tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
if ((tmp & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING) == 0)
break;
udelay(1);
}
}
}
 
/* unblackout the MC */
tmp = RREG32(MC_SHARED_BLACKOUT_CNTL);
tmp &= ~BLACKOUT_MODE_MASK;
1291,11 → 2456,15
if (ASIC_IS_DCE6(rdev)) {
tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
} else {
tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
}
/* wait for the next frame */
frame_count = radeon_get_vblank_counter(rdev, i);
1306,11 → 2475,13
}
}
}
if (!ASIC_IS_NODCE(rdev)) {
/* Unlock vga access */
WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
mdelay(1);
WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
}
}
 
void evergreen_mc_program(struct radeon_device *rdev)
{
1940,6 → 3111,14
}
/* enabled rb are just the one not disabled :) */
disabled_rb_mask = tmp;
tmp = 0;
for (i = 0; i < rdev->config.evergreen.max_backends; i++)
tmp |= (1 << i);
/* if all the backends are disabled, fix it up here */
if ((disabled_rb_mask & tmp) == tmp) {
for (i = 0; i < rdev->config.evergreen.max_backends; i++)
disabled_rb_mask &= ~(1 << i);
}
 
WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
1948,10 → 3127,24
WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
WREG32(HDP_ADDR_CONFIG, gb_addr_config);
WREG32(DMA_TILING_CONFIG, gb_addr_config);
WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
 
if ((rdev->config.evergreen.max_backends == 1) &&
(rdev->flags & RADEON_IS_IGP)) {
if ((disabled_rb_mask & 3) == 1) {
/* RB0 disabled, RB1 enabled */
tmp = 0x11111111;
} else {
/* RB1 disabled, RB0 enabled */
tmp = 0x00000000;
}
} else {
tmp = gb_addr_config & NUM_PIPES_MASK;
tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.evergreen.max_backends,
EVERGREEN_MAX_BACKENDS, disabled_rb_mask);
}
WREG32(GB_BACKEND_MAP, tmp);
 
WREG32(CGTS_SYS_TCC_DISABLE, 0);
2190,8 → 3383,8
rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
} else {
/* size in MB on evergreen/cayman/tn */
rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;
rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;
}
rdev->mc.visible_vram_size = rdev->mc.aper_size;
r700_vram_gtt_location(rdev, &rdev->mc);
2200,34 → 3393,8
return 0;
}
 
bool evergreen_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
void evergreen_print_gpu_status_regs(struct radeon_device *rdev)
{
u32 srbm_status;
u32 grbm_status;
u32 grbm_status_se0, grbm_status_se1;
 
srbm_status = RREG32(SRBM_STATUS);
grbm_status = RREG32(GRBM_STATUS);
grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
if (!(grbm_status & GUI_ACTIVE)) {
radeon_ring_lockup_update(ring);
return false;
}
/* force CP activities */
radeon_ring_force_activity(rdev, ring);
return radeon_ring_test_lockup(rdev, ring);
}
 
static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
{
struct evergreen_mc_save save;
u32 grbm_reset = 0;
 
if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
return 0;
 
dev_info(rdev->dev, "GPU softreset \n");
dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
RREG32(GRBM_STATUS));
dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
2236,6 → 3403,8
RREG32(GRBM_STATUS_SE1));
dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
RREG32(SRBM_STATUS));
dev_info(rdev->dev, " SRBM_STATUS2 = 0x%08X\n",
RREG32(SRBM_STATUS2));
dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
RREG32(CP_STALLED_STAT1));
dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
2244,60 → 3413,291
RREG32(CP_BUSY_STAT));
dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
RREG32(CP_STAT));
dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
RREG32(DMA_STATUS_REG));
if (rdev->family >= CHIP_CAYMAN) {
dev_info(rdev->dev, " R_00D834_DMA_STATUS_REG = 0x%08X\n",
RREG32(DMA_STATUS_REG + 0x800));
}
}
 
bool evergreen_is_display_hung(struct radeon_device *rdev)
{
u32 crtc_hung = 0;
u32 crtc_status[6];
u32 i, j, tmp;
 
for (i = 0; i < rdev->num_crtc; i++) {
if (RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN) {
crtc_status[i] = RREG32(EVERGREEN_CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
crtc_hung |= (1 << i);
}
}
 
for (j = 0; j < 10; j++) {
for (i = 0; i < rdev->num_crtc; i++) {
if (crtc_hung & (1 << i)) {
tmp = RREG32(EVERGREEN_CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
if (tmp != crtc_status[i])
crtc_hung &= ~(1 << i);
}
}
if (crtc_hung == 0)
return false;
udelay(100);
}
 
return true;
}
 
static u32 evergreen_gpu_check_soft_reset(struct radeon_device *rdev)
{
u32 reset_mask = 0;
u32 tmp;
 
/* GRBM_STATUS */
tmp = RREG32(GRBM_STATUS);
if (tmp & (PA_BUSY | SC_BUSY |
SH_BUSY | SX_BUSY |
TA_BUSY | VGT_BUSY |
DB_BUSY | CB_BUSY |
SPI_BUSY | VGT_BUSY_NO_DMA))
reset_mask |= RADEON_RESET_GFX;
 
if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING |
CP_BUSY | CP_COHERENCY_BUSY))
reset_mask |= RADEON_RESET_CP;
 
if (tmp & GRBM_EE_BUSY)
reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
 
/* DMA_STATUS_REG */
tmp = RREG32(DMA_STATUS_REG);
if (!(tmp & DMA_IDLE))
reset_mask |= RADEON_RESET_DMA;
 
/* SRBM_STATUS2 */
tmp = RREG32(SRBM_STATUS2);
if (tmp & DMA_BUSY)
reset_mask |= RADEON_RESET_DMA;
 
/* SRBM_STATUS */
tmp = RREG32(SRBM_STATUS);
if (tmp & (RLC_RQ_PENDING | RLC_BUSY))
reset_mask |= RADEON_RESET_RLC;
 
if (tmp & IH_BUSY)
reset_mask |= RADEON_RESET_IH;
 
if (tmp & SEM_BUSY)
reset_mask |= RADEON_RESET_SEM;
 
if (tmp & GRBM_RQ_PENDING)
reset_mask |= RADEON_RESET_GRBM;
 
if (tmp & VMC_BUSY)
reset_mask |= RADEON_RESET_VMC;
 
if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY |
MCC_BUSY | MCD_BUSY))
reset_mask |= RADEON_RESET_MC;
 
if (evergreen_is_display_hung(rdev))
reset_mask |= RADEON_RESET_DISPLAY;
 
/* VM_L2_STATUS */
tmp = RREG32(VM_L2_STATUS);
if (tmp & L2_BUSY)
reset_mask |= RADEON_RESET_VMC;
 
/* Skip MC reset as it's mostly likely not hung, just busy */
if (reset_mask & RADEON_RESET_MC) {
DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
reset_mask &= ~RADEON_RESET_MC;
}
 
return reset_mask;
}
 
static void evergreen_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
{
struct evergreen_mc_save save;
u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
u32 tmp;
 
if (reset_mask == 0)
return;
 
dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
 
evergreen_print_gpu_status_regs(rdev);
 
/* Disable CP parsing/prefetching */
WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
 
if (reset_mask & RADEON_RESET_DMA) {
/* Disable DMA */
tmp = RREG32(DMA_RB_CNTL);
tmp &= ~DMA_RB_ENABLE;
WREG32(DMA_RB_CNTL, tmp);
}
 
udelay(50);
 
evergreen_mc_stop(rdev, &save);
if (evergreen_mc_wait_for_idle(rdev)) {
dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
}
/* Disable CP parsing/prefetching */
WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
 
/* reset all the gfx blocks */
grbm_reset = (SOFT_RESET_CP |
if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {
grbm_soft_reset |= SOFT_RESET_DB |
SOFT_RESET_CB |
SOFT_RESET_DB |
SOFT_RESET_PA |
SOFT_RESET_SC |
SOFT_RESET_SPI |
SOFT_RESET_SX |
SOFT_RESET_SH |
SOFT_RESET_SX |
SOFT_RESET_TC |
SOFT_RESET_TA |
SOFT_RESET_VC |
SOFT_RESET_VGT);
SOFT_RESET_VGT;
}
 
dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
WREG32(GRBM_SOFT_RESET, grbm_reset);
(void)RREG32(GRBM_SOFT_RESET);
if (reset_mask & RADEON_RESET_CP) {
grbm_soft_reset |= SOFT_RESET_CP |
SOFT_RESET_VGT;
 
srbm_soft_reset |= SOFT_RESET_GRBM;
}
 
if (reset_mask & RADEON_RESET_DMA)
srbm_soft_reset |= SOFT_RESET_DMA;
 
if (reset_mask & RADEON_RESET_DISPLAY)
srbm_soft_reset |= SOFT_RESET_DC;
 
if (reset_mask & RADEON_RESET_RLC)
srbm_soft_reset |= SOFT_RESET_RLC;
 
if (reset_mask & RADEON_RESET_SEM)
srbm_soft_reset |= SOFT_RESET_SEM;
 
if (reset_mask & RADEON_RESET_IH)
srbm_soft_reset |= SOFT_RESET_IH;
 
if (reset_mask & RADEON_RESET_GRBM)
srbm_soft_reset |= SOFT_RESET_GRBM;
 
if (reset_mask & RADEON_RESET_VMC)
srbm_soft_reset |= SOFT_RESET_VMC;
 
if (!(rdev->flags & RADEON_IS_IGP)) {
if (reset_mask & RADEON_RESET_MC)
srbm_soft_reset |= SOFT_RESET_MC;
}
 
if (grbm_soft_reset) {
tmp = RREG32(GRBM_SOFT_RESET);
tmp |= grbm_soft_reset;
dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
WREG32(GRBM_SOFT_RESET, tmp);
tmp = RREG32(GRBM_SOFT_RESET);
 
udelay(50);
WREG32(GRBM_SOFT_RESET, 0);
(void)RREG32(GRBM_SOFT_RESET);
 
tmp &= ~grbm_soft_reset;
WREG32(GRBM_SOFT_RESET, tmp);
tmp = RREG32(GRBM_SOFT_RESET);
}
 
if (srbm_soft_reset) {
tmp = RREG32(SRBM_SOFT_RESET);
tmp |= srbm_soft_reset;
dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
WREG32(SRBM_SOFT_RESET, tmp);
tmp = RREG32(SRBM_SOFT_RESET);
 
udelay(50);
 
tmp &= ~srbm_soft_reset;
WREG32(SRBM_SOFT_RESET, tmp);
tmp = RREG32(SRBM_SOFT_RESET);
}
 
/* Wait a little for things to settle down */
udelay(50);
dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
RREG32(GRBM_STATUS));
dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
RREG32(GRBM_STATUS_SE0));
dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
RREG32(GRBM_STATUS_SE1));
dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
RREG32(SRBM_STATUS));
dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
RREG32(CP_STALLED_STAT1));
dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
RREG32(CP_STALLED_STAT2));
dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n",
RREG32(CP_BUSY_STAT));
dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
RREG32(CP_STAT));
 
evergreen_mc_resume(rdev, &save);
return 0;
udelay(50);
 
evergreen_print_gpu_status_regs(rdev);
}
 
int evergreen_asic_reset(struct radeon_device *rdev)
{
return evergreen_gpu_soft_reset(rdev);
u32 reset_mask;
 
reset_mask = evergreen_gpu_check_soft_reset(rdev);
 
if (reset_mask)
r600_set_bios_scratch_engine_hung(rdev, true);
 
evergreen_gpu_soft_reset(rdev, reset_mask);
 
reset_mask = evergreen_gpu_check_soft_reset(rdev);
 
if (!reset_mask)
r600_set_bios_scratch_engine_hung(rdev, false);
 
return 0;
}
 
/**
* evergreen_gfx_is_lockup - Check if the GFX engine is locked up
*
* @rdev: radeon_device pointer
* @ring: radeon_ring structure holding ring information
*
* Check if the GFX engine is locked up.
* Returns true if the engine appears to be locked up, false if not.
*/
bool evergreen_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
{
u32 reset_mask = evergreen_gpu_check_soft_reset(rdev);
 
if (!(reset_mask & (RADEON_RESET_GFX |
RADEON_RESET_COMPUTE |
RADEON_RESET_CP))) {
radeon_ring_lockup_update(ring);
return false;
}
/* force CP activities */
radeon_ring_force_activity(rdev, ring);
return radeon_ring_test_lockup(rdev, ring);
}
 
/**
* evergreen_dma_is_lockup - Check if the DMA engine is locked up
*
* @rdev: radeon_device pointer
* @ring: radeon_ring structure holding ring information
*
* Check if the async DMA engine is locked up.
* Returns true if the engine appears to be locked up, false if not.
*/
bool evergreen_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
{
u32 reset_mask = evergreen_gpu_check_soft_reset(rdev);
 
if (!(reset_mask & RADEON_RESET_DMA)) {
radeon_ring_lockup_update(ring);
return false;
}
/* force ring activities */
radeon_ring_force_activity(rdev, ring);
return radeon_ring_test_lockup(rdev, ring);
}
 
/* Interrupts */
 
u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc)
3032,6 → 4432,9
DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
break;
}
case 124: /* UVD */
DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data);
radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX);
break;
case 146:
case 147:
3116,15 → 4519,15
struct radeon_ring *ring = &rdev->ring[fence->ring];
u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
/* write the fence */
radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0));
radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0));
radeon_ring_write(ring, addr & 0xfffffffc);
radeon_ring_write(ring, (upper_32_bits(addr) & 0xff));
radeon_ring_write(ring, fence->seq);
/* generate an interrupt */
radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0));
radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0));
/* flush HDP */
radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));
radeon_ring_write(ring, (0xf << 16) | HDP_MEM_COHERENCY_FLUSH_CNTL);
radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0));
radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2));
radeon_ring_write(ring, 1);
}
 
3146,7 → 4549,7
while ((next_rptr & 7) != 5)
next_rptr++;
next_rptr += 3;
radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 1));
radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);
radeon_ring_write(ring, next_rptr);
3156,8 → 4559,8
* Pad as necessary with NOPs.
*/
while ((ring->wptr & 7) != 5)
radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0, 0));
radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0));
radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0));
radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF));
 
3216,7 → 4619,7
if (cur_size_in_dw > 0xFFFFF)
cur_size_in_dw = 0xFFFFF;
size_in_dw -= cur_size_in_dw;
radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw));
radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, cur_size_in_dw));
radeon_ring_write(ring, dst_offset & 0xfffffffc);
radeon_ring_write(ring, src_offset & 0xfffffffc);
radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
3239,7 → 4642,7
 
static int evergreen_startup(struct radeon_device *rdev)
{
struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
struct radeon_ring *ring;
int r;
 
/* enable pcie gen2 link */
3306,7 → 4709,24
return r;
}
 
// r = rv770_uvd_resume(rdev);
// if (!r) {
// r = radeon_fence_driver_start_ring(rdev,
// R600_RING_TYPE_UVD_INDEX);
// if (r)
// dev_err(rdev->dev, "UVD fences init error (%d).\n", r);
// }
 
// if (r)
// rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
 
/* Enable IRQ */
if (!rdev->irq.installed) {
r = radeon_irq_kms_init(rdev);
if (r)
return r;
}
 
r = r600_irq_init(rdev);
if (r) {
DRM_ERROR("radeon: IH init failed (%d).\n", r);
3315,6 → 4735,7
}
evergreen_irq_set(rdev);
 
ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
R600_CP_RB_RPTR, R600_CP_RB_WPTR,
0, 0xfffff, RADEON_CP_PACKET2);
3324,7 → 4745,7
ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
DMA_RB_RPTR, DMA_RB_WPTR,
2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0));
if (r)
return r;
 
3338,6 → 4759,19
if (r)
return r;
 
ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
if (ring->ring_size) {
r = radeon_ring_init(rdev, ring, ring->ring_size,
R600_WB_UVD_RPTR_OFFSET,
UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,
0, 0xfffff, RADEON_CP_PACKET2);
if (!r)
r = r600_uvd_init(rdev);
 
if (r)
DRM_ERROR("radeon: error initializing UVD (%d).\n", r);
}
 
r = radeon_ib_pool_init(rdev);
if (r) {
dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
3410,6 → 4844,8
DRM_INFO("GPU not posted. posting now...\n");
atom_asic_init(rdev->mode_info.atom_context);
}
/* init golden registers */
evergreen_init_golden_registers(rdev);
/* Initialize scratch registers */
r600_scratch_init(rdev);
/* Initialize surface registers */
3435,10 → 4871,6
if (r)
return r;
 
r = radeon_irq_kms_init(rdev);
if (r)
return r;
 
rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
 
3445,6 → 4877,13
rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL;
r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024);
 
// r = radeon_uvd_init(rdev);
// if (!r) {
// rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL;
// r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX],
// 4096);
// }
 
rdev->ih.ring_obj = NULL;
r600_ih_ring_init(rdev, 64 * 1024);
 
3476,8 → 4915,7
 
void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
{
u32 link_width_cntl, speed_cntl, mask;
int ret;
u32 link_width_cntl, speed_cntl;
 
if (radeon_pcie_gen2 == 0)
return;
3492,14 → 4930,11
if (ASIC_IS_X2(rdev))
return;
 
ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
if (ret != 0)
if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) &&
(rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT))
return;
 
if (!(mask & DRM_PCIE_SPEED_50))
return;
 
speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
if (speed_cntl & LC_CURRENT_DATA_RATE) {
DRM_INFO("PCIE gen 2 link speeds already enabled\n");
return;
3510,33 → 4945,33
if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
(speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
 
link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
link_width_cntl &= ~LC_UPCONFIGURE_DIS;
WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
 
speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
 
speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
 
speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
 
speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
speed_cntl |= LC_GEN2_EN_STRAP;
WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
 
} else {
link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
/* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
if (1)
link_width_cntl |= LC_UPCONFIGURE_DIS;
else
link_width_cntl &= ~LC_UPCONFIGURE_DIS;
WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
}
}