183,9 → 183,15 |
struct backlight_properties props; |
struct radeon_backlight_privdata *pdata; |
struct radeon_encoder_atom_dig *dig; |
u8 backlight_level; |
char bl_name[16]; |
|
/* Mac laptops with multiple GPUs use the gmux driver for backlight |
* so don't register a backlight device |
*/ |
if ((rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) && |
(rdev->pdev->device == 0x6741)) |
return; |
|
if (!radeon_encoder->enc_priv) |
return; |
|
206,7 → 212,7 |
props.type = BACKLIGHT_RAW; |
snprintf(bl_name, sizeof(bl_name), |
"radeon_bl%d", dev->primary->index); |
bd = backlight_device_register(bl_name, &drm_connector->kdev, |
bd = backlight_device_register(bl_name, drm_connector->kdev, |
pdata, &radeon_atom_backlight_ops, &props); |
if (IS_ERR(bd)) { |
DRM_ERROR("Backlight registration failed\n"); |
215,12 → 221,17 |
|
pdata->encoder = radeon_encoder; |
|
backlight_level = radeon_atom_get_backlight_level_from_reg(rdev); |
|
dig = radeon_encoder->enc_priv; |
dig->bl_dev = bd; |
|
bd->props.brightness = radeon_atom_backlight_get_brightness(bd); |
/* Set a reasonable default here if the level is 0 otherwise |
* fbdev will attempt to turn the backlight on after console |
* unblanking and it will try and restore 0 which turns the backlight |
* off again. |
*/ |
if (bd->props.brightness == 0) |
bd->props.brightness = RADEON_MAX_BL_LEVEL; |
bd->props.power = FB_BLANK_UNBLANK; |
backlight_update_status(bd); |
|
296,6 → 307,7 |
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: |
return true; |
default: |
return false; |
319,12 → 331,10 |
&& (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2))) |
adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2; |
|
/* get the native mode for LVDS */ |
if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT|ATOM_DEVICE_DFP_SUPPORT)) |
/* get the native mode for scaling */ |
if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT|ATOM_DEVICE_DFP_SUPPORT)) { |
radeon_panel_mode_fixup(encoder, adjusted_mode); |
|
/* get the native mode for TV */ |
if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) { |
} else if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) { |
struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; |
if (tv_dac) { |
if (tv_dac->tv_std == TV_STD_NTSC || |
334,6 → 344,8 |
else |
radeon_atom_get_tv_timings(rdev, 1, adjusted_mode); |
} |
} else if (radeon_encoder->rmx_type != RMX_OFF) { |
radeon_panel_mode_fixup(encoder, adjusted_mode); |
} |
|
if (ASIC_IS_DCE3(rdev) && |
456,11 → 468,12 |
|
static u8 radeon_atom_get_bpc(struct drm_encoder *encoder) |
{ |
struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
int bpc = 8; |
|
if (connector) |
bpc = radeon_get_monitor_bpc(connector); |
if (encoder->crtc) { |
struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
bpc = radeon_crtc->bpc; |
} |
|
switch (bpc) { |
case 0: |
479,11 → 492,11 |
} |
} |
|
|
union dvo_encoder_control { |
ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds; |
DVO_ENCODER_CONTROL_PS_ALLOCATION dvo; |
DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3; |
DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4; |
}; |
|
void |
533,6 → 546,13 |
args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
args.dvo_v3.ucDVOConfig = 0; /* XXX */ |
break; |
case 4: |
/* DCE8 */ |
args.dvo_v4.ucAction = action; |
args.dvo_v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); |
args.dvo_v4.ucDVOConfig = 0; /* XXX */ |
args.dvo_v4.ucBitPerColor = radeon_atom_get_bpc(encoder); |
break; |
default: |
DRM_ERROR("Unknown table version %d, %d\n", frev, crev); |
break; |
667,8 → 687,6 |
int |
atombios_get_encoder_mode(struct drm_encoder *encoder) |
{ |
struct drm_device *dev = encoder->dev; |
struct radeon_device *rdev = dev->dev_private; |
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
struct drm_connector *connector; |
struct radeon_connector *radeon_connector; |
694,24 → 712,37 |
switch (connector->connector_type) { |
case DRM_MODE_CONNECTOR_DVII: |
case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ |
if (drm_detect_hdmi_monitor(radeon_connector->edid) && |
radeon_audio && |
!ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */ |
if (radeon_audio != 0) { |
if (radeon_connector->use_digital && |
(radeon_connector->audio == RADEON_AUDIO_ENABLE)) |
return ATOM_ENCODER_MODE_HDMI; |
else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && |
(radeon_connector->audio == RADEON_AUDIO_AUTO)) |
return ATOM_ENCODER_MODE_HDMI; |
else if (radeon_connector->use_digital) |
return ATOM_ENCODER_MODE_DVI; |
else |
return ATOM_ENCODER_MODE_CRT; |
} else if (radeon_connector->use_digital) { |
return ATOM_ENCODER_MODE_DVI; |
} else { |
return ATOM_ENCODER_MODE_CRT; |
} |
break; |
case DRM_MODE_CONNECTOR_DVID: |
case DRM_MODE_CONNECTOR_HDMIA: |
default: |
if (drm_detect_hdmi_monitor(radeon_connector->edid) && |
radeon_audio && |
!ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */ |
if (radeon_audio != 0) { |
if (radeon_connector->audio == RADEON_AUDIO_ENABLE) |
return ATOM_ENCODER_MODE_HDMI; |
else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && |
(radeon_connector->audio == RADEON_AUDIO_AUTO)) |
return ATOM_ENCODER_MODE_HDMI; |
else |
return ATOM_ENCODER_MODE_DVI; |
} else { |
return ATOM_ENCODER_MODE_DVI; |
} |
break; |
case DRM_MODE_CONNECTOR_LVDS: |
return ATOM_ENCODER_MODE_LVDS; |
719,14 → 750,19 |
case DRM_MODE_CONNECTOR_DisplayPort: |
dig_connector = radeon_connector->con_priv; |
if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || |
(dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) |
(dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { |
return ATOM_ENCODER_MODE_DP; |
else if (drm_detect_hdmi_monitor(radeon_connector->edid) && |
radeon_audio && |
!ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */ |
} else if (radeon_audio != 0) { |
if (radeon_connector->audio == RADEON_AUDIO_ENABLE) |
return ATOM_ENCODER_MODE_HDMI; |
else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) && |
(radeon_connector->audio == RADEON_AUDIO_AUTO)) |
return ATOM_ENCODER_MODE_HDMI; |
else |
return ATOM_ENCODER_MODE_DVI; |
} else { |
return ATOM_ENCODER_MODE_DVI; |
} |
break; |
case DRM_MODE_CONNECTOR_eDP: |
return ATOM_ENCODER_MODE_DP; |
915,10 → 951,14 |
args.v4.ucLaneNum = 4; |
|
if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) { |
if (dp_clock == 270000) |
if (dp_clock == 540000) |
args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ; |
else if (dp_clock == 324000) |
args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ; |
else if (dp_clock == 270000) |
args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ; |
else if (dp_clock == 540000) |
args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ; |
else |
args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ; |
} |
args.v4.acConfig.ucDigSel = dig->dig_encoder; |
args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder); |
1012,6 → 1052,7 |
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: |
index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl); |
break; |
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
1271,10 → 1312,13 |
else |
args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE; |
break; |
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: |
args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG; |
break; |
} |
if (is_dp) |
args.v5.ucLaneNum = dp_lane_count; |
else if (radeon_encoder->pixel_clock > 165000) |
else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
args.v5.ucLaneNum = 8; |
else |
args.v5.ucLaneNum = 4; |
1593,10 → 1637,16 |
struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); |
struct radeon_connector *radeon_connector = NULL; |
struct radeon_connector_atom_dig *radeon_dig_connector = NULL; |
bool travis_quirk = false; |
|
if (connector) { |
radeon_connector = to_radeon_connector(connector); |
radeon_dig_connector = radeon_connector->con_priv; |
if ((radeon_connector_encoder_get_dp_bridge_encoder_id(connector) == |
ENCODER_OBJECT_ID_TRAVIS) && |
(radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) && |
!ASIC_IS_DCE5(rdev)) |
travis_quirk = true; |
} |
|
switch (mode) { |
1617,21 → 1667,13 |
atombios_external_encoder_setup(encoder, ext_encoder, |
EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP); |
} |
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); |
} else if (ASIC_IS_DCE4(rdev)) { |
/* setup and enable the encoder */ |
atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0); |
/* enable the transmitter */ |
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); |
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0); |
} else { |
/* setup and enable the encoder and transmitter */ |
atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0); |
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0); |
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); |
/* some early dce3.2 boards have a bug in their transmitter control table */ |
if ((rdev->family != CHIP_RV710) && (rdev->family != CHIP_RV730)) |
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0); |
} |
if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { |
if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { |
1639,32 → 1681,50 |
ATOM_TRANSMITTER_ACTION_POWER_ON); |
radeon_dig_connector->edp_on = true; |
} |
} |
/* enable the transmitter */ |
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0); |
if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { |
/* DP_SET_POWER_D0 is set in radeon_dp_link_train */ |
radeon_dp_link_train(encoder, connector); |
if (ASIC_IS_DCE4(rdev)) |
atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0); |
} |
if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); |
atombios_dig_transmitter_setup(encoder, |
ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); |
if (ext_encoder) |
atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE); |
break; |
case DRM_MODE_DPMS_STANDBY: |
case DRM_MODE_DPMS_SUSPEND: |
case DRM_MODE_DPMS_OFF: |
if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) { |
if (ASIC_IS_DCE4(rdev)) { |
if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) |
atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0); |
} |
if (ext_encoder) |
atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE); |
if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
atombios_dig_transmitter_setup(encoder, |
ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); |
|
if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && |
connector && !travis_quirk) |
radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3); |
if (ASIC_IS_DCE4(rdev)) { |
/* disable the transmitter */ |
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); |
} else if (ASIC_IS_DCE4(rdev)) { |
/* disable the transmitter */ |
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0); |
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); |
atombios_dig_transmitter_setup(encoder, |
ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); |
} else { |
/* disable the encoder and transmitter */ |
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0); |
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); |
atombios_dig_transmitter_setup(encoder, |
ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0); |
atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0); |
} |
if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) { |
if (ASIC_IS_DCE4(rdev)) |
atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0); |
if (travis_quirk) |
radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3); |
if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { |
atombios_set_edp_panel_power(connector, |
ATOM_TRANSMITTER_ACTION_POWER_OFF); |
1671,52 → 1731,16 |
radeon_dig_connector->edp_on = false; |
} |
} |
if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0); |
break; |
} |
} |
|
static void |
radeon_atom_encoder_dpms_ext(struct drm_encoder *encoder, |
struct drm_encoder *ext_encoder, |
int mode) |
{ |
struct drm_device *dev = encoder->dev; |
struct radeon_device *rdev = dev->dev_private; |
|
switch (mode) { |
case DRM_MODE_DPMS_ON: |
default: |
if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) { |
atombios_external_encoder_setup(encoder, ext_encoder, |
EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT); |
atombios_external_encoder_setup(encoder, ext_encoder, |
EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF); |
} else |
atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE); |
break; |
case DRM_MODE_DPMS_STANDBY: |
case DRM_MODE_DPMS_SUSPEND: |
case DRM_MODE_DPMS_OFF: |
if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) { |
atombios_external_encoder_setup(encoder, ext_encoder, |
EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING); |
atombios_external_encoder_setup(encoder, ext_encoder, |
EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT); |
} else |
atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE); |
break; |
} |
} |
|
static void |
radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode) |
{ |
struct drm_device *dev = encoder->dev; |
struct radeon_device *rdev = dev->dev_private; |
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder); |
|
DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n", |
radeon_encoder->encoder_id, mode, radeon_encoder->devices, |
1735,6 → 1759,7 |
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: |
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
radeon_atom_encoder_dpms_dig(encoder, mode); |
break; |
1775,9 → 1800,6 |
return; |
} |
|
if (ext_encoder) |
radeon_atom_encoder_dpms_ext(encoder, ext_encoder, mode); |
|
radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); |
|
} |
1866,12 → 1888,16 |
args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT; |
else |
args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); |
} else |
} else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS; |
} else { |
args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder); |
} |
switch (radeon_encoder->encoder_id) { |
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: |
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
dig = radeon_encoder->enc_priv; |
switch (dig->dig_encoder) { |
1893,6 → 1919,9 |
case 5: |
args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID; |
break; |
case 6: |
args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID; |
break; |
} |
break; |
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
1955,8 → 1984,14 |
/* set scaler clears this on some chips */ |
if (ASIC_IS_AVIVO(rdev) && |
(!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) { |
if (ASIC_IS_DCE4(rdev)) { |
if (ASIC_IS_DCE8(rdev)) { |
if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, |
CIK_INTERLEAVE_EN); |
else |
WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0); |
} else if (ASIC_IS_DCE4(rdev)) { |
if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, |
EVERGREEN_INTERLEAVE_EN); |
else |
2002,6 → 2037,9 |
else |
return 4; |
break; |
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: |
return 6; |
break; |
} |
} else if (ASIC_IS_DCE4(rdev)) { |
/* DCE4/5 */ |
2086,6 → 2124,7 |
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: |
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0); |
break; |
2130,6 → 2169,7 |
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: |
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
/* handled in dpms */ |
break; |
2351,6 → 2391,15 |
|
/* this is needed for the pll/ss setup to work correctly in some cases */ |
atombios_set_encoder_crtc_source(encoder); |
/* set up the FMT blocks */ |
if (ASIC_IS_DCE8(rdev)) |
dce8_program_fmt(encoder); |
else if (ASIC_IS_DCE4(rdev)) |
dce4_program_fmt(encoder); |
else if (ASIC_IS_DCE3(rdev)) |
dce3_program_fmt(encoder); |
else if (ASIC_IS_AVIVO(rdev)) |
avivo_program_fmt(encoder); |
} |
|
static void radeon_atom_encoder_commit(struct drm_encoder *encoder) |
2395,6 → 2444,7 |
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: |
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
/* handled in dpms */ |
break; |
2626,6 → 2676,7 |
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: |
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: |
if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
radeon_encoder->rmx_type = RMX_FULL; |
drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS); |