74,6 → 74,8 |
#define ATOM_PPLL2 1 |
#define ATOM_DCPLL 2 |
#define ATOM_PPLL0 2 |
#define ATOM_PPLL3 3 |
|
#define ATOM_EXT_PLL1 8 |
#define ATOM_EXT_PLL2 9 |
#define ATOM_EXT_CLOCK 10 |
259,7 → 261,7 |
USHORT AdjustDisplayPll; //Atomic Table, used by various SW componentes. |
USHORT AdjustMemoryController; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock |
USHORT EnableASIC_StaticPwrMgt; //Atomic Table, only used by Bios |
USHORT ASIC_StaticPwrMgtStatusChange; //Obsolete , only used by Bios |
USHORT SetUniphyInstance; //Atomic Table, only used by Bios |
USHORT DAC_LoadDetection; //Atomic Table, directly used by various SW components,latest version 1.2 |
USHORT LVTMAEncoderControl; //Atomic Table,directly used by various SW components,latest version 1.3 |
USHORT HW_Misc_Operation; //Atomic Table, directly used by various SW components,latest version 1.1 |
271,7 → 273,7 |
USHORT TVEncoderControl; //Function Table,directly used by various SW components,latest version 1.1 |
USHORT PatchMCSetting; //only used by BIOS |
USHORT MC_SEQ_Control; //only used by BIOS |
USHORT TV1OutputControl; //Atomic Table, Obsolete from Ry6xx, use DAC2 Output instead |
USHORT Gfx_Harvesting; //Atomic Table, Obsolete from Ry6xx, Now only used by BIOS for GFX harvesting |
USHORT EnableScaler; //Atomic Table, used only by Bios |
USHORT BlankCRTC; //Atomic Table, directly used by various SW components,latest version 1.1 |
USHORT EnableCRTC; //Atomic Table, directly used by various SW components,latest version 1.1 |
328,7 → 330,7 |
#define UNIPHYTransmitterControl DIG1TransmitterControl |
#define LVTMATransmitterControl DIG2TransmitterControl |
#define SetCRTC_DPM_State GetConditionalGoldenSetting |
#define SetUniphyInstance ASIC_StaticPwrMgtStatusChange |
#define ASIC_StaticPwrMgtStatusChange SetUniphyInstance |
#define HPDInterruptService ReadHWAssistedI2CStatus |
#define EnableVGA_Access GetSCLKOverMCLKRatio |
#define EnableYUV GetDispObjectInfo |
338,8 → 340,8 |
#define TMDSAEncoderControl PatchMCSetting |
#define LVDSEncoderControl MC_SEQ_Control |
#define LCD1OutputControl HW_Misc_Operation |
#define TV1OutputControl Gfx_Harvesting |
|
|
typedef struct _ATOM_MASTER_COMMAND_TABLE |
{ |
ATOM_COMMON_TABLE_HEADER sHeader; |
478,11 → 480,11 |
typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 |
{ |
#if ATOM_BIG_ENDIAN |
ULONG ucPostDiv; //return parameter: post divider which is used to program to register directly |
ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register directly |
ULONG ulClock:24; //Input= target clock, output = actual clock |
#else |
ULONG ulClock:24; //Input= target clock, output = actual clock |
ULONG ucPostDiv; //return parameter: post divider which is used to program to register directly |
ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register directly |
#endif |
}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4; |
|
504,6 → 506,32 |
UCHAR ucReserved; |
}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5; |
|
|
typedef struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 |
{ |
ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter |
ULONG ulReserved[2]; |
}COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6; |
|
//ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag |
#define COMPUTE_GPUCLK_INPUT_FLAG_CLK_TYPE_MASK 0x0f |
#define COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK 0x00 |
#define COMPUTE_GPUCLK_INPUT_FLAG_SCLK 0x01 |
|
typedef struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 |
{ |
COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 ulClock; //Output Parameter: ucPostDiv=DFS divider |
ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter: PLL FB divider |
UCHAR ucPllRefDiv; //Output Parameter: PLL ref divider |
UCHAR ucPllPostDiv; //Output Parameter: PLL post divider |
UCHAR ucPllCntlFlag; //Output Flags: control flag |
UCHAR ucReserved; |
}COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6; |
|
//ucPllCntlFlag |
#define SPLL_CNTL_FLAG_VCO_MODE_MASK 0x03 |
|
|
// ucInputFlag |
#define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode |
|
1683,9 → 1711,12 |
#define PIXEL_CLOCK_V6_MISC_HDMI_BPP_MASK 0x0c |
#define PIXEL_CLOCK_V6_MISC_HDMI_24BPP 0x00 |
#define PIXEL_CLOCK_V6_MISC_HDMI_36BPP 0x04 |
#define PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6 0x08 //for V6, the correct defintion for 36bpp should be 2 for 36bpp(2:1) |
#define PIXEL_CLOCK_V6_MISC_HDMI_30BPP 0x08 |
#define PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6 0x04 //for V6, the correct defintion for 30bpp should be 1 for 36bpp(5:4) |
#define PIXEL_CLOCK_V6_MISC_HDMI_48BPP 0x0c |
#define PIXEL_CLOCK_V6_MISC_REF_DIV_SRC 0x10 |
#define PIXEL_CLOCK_V6_MISC_GEN_DPREFCLK 0x40 |
|
typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2 |
{ |
2102,6 → 2133,17 |
}DVO_ENCODER_CONTROL_PARAMETERS_V3; |
#define DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 DVO_ENCODER_CONTROL_PARAMETERS_V3 |
|
typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V1_4 |
{ |
USHORT usPixelClock; |
UCHAR ucDVOConfig; |
UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT |
UCHAR ucBitPerColor; //please refer to definition of PANEL_xBIT_PER_COLOR |
UCHAR ucReseved[3]; |
}DVO_ENCODER_CONTROL_PARAMETERS_V1_4; |
#define DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 DVO_ENCODER_CONTROL_PARAMETERS_V1_4 |
|
|
//ucTableFormatRevision=1 |
//ucTableContentRevision=3 structure is not changed but usMisc add bit 1 as another input for |
// bit1=0: non-coherent mode |
2183,7 → 2225,7 |
USHORT usVoltageLevel; // real voltage level |
}SET_VOLTAGE_PARAMETERS_V2; |
|
|
// used by both SetVoltageTable v1.3 and v1.4 |
typedef struct _SET_VOLTAGE_PARAMETERS_V1_3 |
{ |
UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI |
2200,9 → 2242,10 |
//SET_VOLTAGE_PARAMETERS_V3.ucVoltageMode |
#define ATOM_SET_VOLTAGE 0 //Set voltage Level |
#define ATOM_INIT_VOLTAGE_REGULATOR 3 //Init Regulator |
#define ATOM_SET_VOLTAGE_PHASE 4 //Set Vregulator Phase |
#define ATOM_GET_MAX_VOLTAGE 6 //Get Max Voltage, not used in SetVoltageTable v1.3 |
#define ATOM_GET_VOLTAGE_LEVEL 6 //Get Voltage level from vitual voltage ID |
#define ATOM_SET_VOLTAGE_PHASE 4 //Set Vregulator Phase, only for SVID/PVID regulator |
#define ATOM_GET_MAX_VOLTAGE 6 //Get Max Voltage, not used from SetVoltageTable v1.3 |
#define ATOM_GET_VOLTAGE_LEVEL 6 //Get Voltage level from vitual voltage ID, not used for SetVoltage v1.4 |
#define ATOM_GET_LEAKAGE_ID 8 //Get Leakage Voltage Id ( starting from SMU7x IP ), SetVoltage v1.4 |
|
// define vitual voltage id in usVoltageLevel |
#define ATOM_VIRTUAL_VOLTAGE_ID0 0xff01 |
2209,6 → 2252,10 |
#define ATOM_VIRTUAL_VOLTAGE_ID1 0xff02 |
#define ATOM_VIRTUAL_VOLTAGE_ID2 0xff03 |
#define ATOM_VIRTUAL_VOLTAGE_ID3 0xff04 |
#define ATOM_VIRTUAL_VOLTAGE_ID4 0xff05 |
#define ATOM_VIRTUAL_VOLTAGE_ID5 0xff06 |
#define ATOM_VIRTUAL_VOLTAGE_ID6 0xff07 |
#define ATOM_VIRTUAL_VOLTAGE_ID7 0xff08 |
|
typedef struct _SET_VOLTAGE_PS_ALLOCATION |
{ |
2245,15 → 2292,36 |
#define ATOM_GET_VOLTAGE_VID 0x00 |
#define ATOM_GET_VOTLAGE_INIT_SEQ 0x03 |
#define ATOM_GET_VOLTTAGE_PHASE_PHASE_VID 0x04 |
#define ATOM_GET_VOLTAGE_SVID2 0x07 //Get SVI2 Regulator Info |
|
// for SI, this state map to 0xff02 voltage state in Power Play table, which is power boost state |
#define ATOM_GET_VOLTAGE_STATE0_LEAKAGE_VID 0x10 |
|
// for SI, this state map to 0xff01 voltage state in Power Play table, which is performance state |
#define ATOM_GET_VOLTAGE_STATE1_LEAKAGE_VID 0x11 |
// undefined power state |
|
#define ATOM_GET_VOLTAGE_STATE2_LEAKAGE_VID 0x12 |
#define ATOM_GET_VOLTAGE_STATE3_LEAKAGE_VID 0x13 |
|
// New Added from CI Hawaii for GetVoltageInfoTable, input parameter structure |
typedef struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 |
{ |
UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI |
UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info |
USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id |
ULONG ulSCLKFreq; // Input: when ucVoltageMode= ATOM_GET_VOLTAGE_EVV_VOLTAGE, DPM state SCLK frequency, Define in PPTable SCLK/Voltage dependence table |
}GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2; |
|
// New in GetVoltageInfo v1.2 ucVoltageMode |
#define ATOM_GET_VOLTAGE_EVV_VOLTAGE 0x09 |
|
// New Added from CI Hawaii for EVV feature |
typedef struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 |
{ |
USHORT usVoltageLevel; // real voltage level in unit of mv |
USHORT usVoltageId; // Voltage Id programmed in Voltage Regulator |
ULONG ulReseved; |
}GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2; |
|
/****************************************************************************/ |
// Structures used by TVEncoderControlTable |
/****************************************************************************/ |
2628,7 → 2696,8 |
ULONG ulFirmwareRevision; |
ULONG ulDefaultEngineClock; //In 10Khz unit |
ULONG ulDefaultMemoryClock; //In 10Khz unit |
ULONG ulReserved[2]; |
ULONG ulSPLL_OutputFreq; //In 10Khz unit |
ULONG ulGPUPLL_OutputFreq; //In 10Khz unit |
ULONG ulReserved1; //Was ulMaxEngineClockPLL_Output; //In 10Khz unit* |
ULONG ulReserved2; //Was ulMaxMemoryClockPLL_Output; //In 10Khz unit* |
ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit |
3813,6 → 3882,14 |
UCHAR ucGPIO_ID; |
}ATOM_GPIO_PIN_ASSIGNMENT; |
|
//ucGPIO_ID pre-define id for multiple usage |
//from SMU7.x, if ucGPIO_ID=PP_AC_DC_SWITCH_GPIO_PINID in GPIO_LUTTable, AC/DC swithing feature is enable |
#define PP_AC_DC_SWITCH_GPIO_PINID 60 |
//from SMU7.x, if ucGPIO_ID=VDDC_REGULATOR_VRHOT_GPIO_PINID in GPIO_LUTable, VRHot feature is enable |
#define VDDC_VRHOT_GPIO_PINID 61 |
//if ucGPIO_ID=VDDC_PCC_GPIO_PINID in GPIO_LUTable, Peak Current Control feature is enabled |
#define VDDC_PCC_GPIO_PINID 62 |
|
typedef struct _ATOM_GPIO_PIN_LUT |
{ |
ATOM_COMMON_TABLE_HEADER sHeader; |
4074,6 → 4151,7 |
|
//usCaps |
#define EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE 0x01 |
#define EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN 0x02 |
|
typedef struct _ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO |
{ |
4084,7 → 4162,8 |
UCHAR uc3DStereoPinId; // use for eDP panel |
UCHAR ucRemoteDisplayConfig; |
UCHAR uceDPToLVDSRxId; |
UCHAR Reserved[4]; // for potential expansion |
UCHAR ucFixDPVoltageSwing; // usCaps[1]=1, this indicate DP_LANE_SET value |
UCHAR Reserved[3]; // for potential expansion |
}ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO; |
|
//Related definitions, all records are different but they have a commond header |
4115,10 → 4194,10 |
#define ATOM_OBJECT_LINK_RECORD_TYPE 18 //Once this record is present under one object, it indicats the oobject is linked to another obj described by the record |
#define ATOM_CONNECTOR_REMOTE_CAP_RECORD_TYPE 19 |
#define ATOM_ENCODER_CAP_RECORD_TYPE 20 |
#define ATOM_BRACKET_LAYOUT_RECORD_TYPE 21 |
|
|
//Must be updated when new record type is added,equal to that record definition! |
#define ATOM_MAX_OBJECT_RECORD_NUMBER ATOM_ENCODER_CAP_RECORD_TYPE |
#define ATOM_MAX_OBJECT_RECORD_NUMBER ATOM_BRACKET_LAYOUT_RECORD_TYPE |
|
typedef struct _ATOM_I2C_RECORD |
{ |
4343,6 → 4422,31 |
USHORT usReserved; |
}ATOM_CONNECTOR_REMOTE_CAP_RECORD; |
|
typedef struct _ATOM_CONNECTOR_LAYOUT_INFO |
{ |
USHORT usConnectorObjectId; |
UCHAR ucConnectorType; |
UCHAR ucPosition; |
}ATOM_CONNECTOR_LAYOUT_INFO; |
|
// define ATOM_CONNECTOR_LAYOUT_INFO.ucConnectorType to describe the display connector size |
#define CONNECTOR_TYPE_DVI_D 1 |
#define CONNECTOR_TYPE_DVI_I 2 |
#define CONNECTOR_TYPE_VGA 3 |
#define CONNECTOR_TYPE_HDMI 4 |
#define CONNECTOR_TYPE_DISPLAY_PORT 5 |
#define CONNECTOR_TYPE_MINI_DISPLAY_PORT 6 |
|
typedef struct _ATOM_BRACKET_LAYOUT_RECORD |
{ |
ATOM_COMMON_RECORD_HEADER sheader; |
UCHAR ucLength; |
UCHAR ucWidth; |
UCHAR ucConnNum; |
UCHAR ucReserved; |
ATOM_CONNECTOR_LAYOUT_INFO asConnInfo[1]; |
}ATOM_BRACKET_LAYOUT_RECORD; |
|
/****************************************************************************/ |
// ASIC voltage data table |
/****************************************************************************/ |
4416,6 → 4520,13 |
#define VOLTAGE_CONTROL_ID_CHL822x 0x08 |
#define VOLTAGE_CONTROL_ID_VT1586M 0x09 |
#define VOLTAGE_CONTROL_ID_UP1637 0x0A |
#define VOLTAGE_CONTROL_ID_CHL8214 0x0B |
#define VOLTAGE_CONTROL_ID_UP1801 0x0C |
#define VOLTAGE_CONTROL_ID_ST6788A 0x0D |
#define VOLTAGE_CONTROL_ID_CHLIR3564SVI2 0x0E |
#define VOLTAGE_CONTROL_ID_AD527x 0x0F |
#define VOLTAGE_CONTROL_ID_NCP81022 0x10 |
#define VOLTAGE_CONTROL_ID_LTC2635 0x11 |
|
typedef struct _ATOM_VOLTAGE_OBJECT |
{ |
4458,6 → 4569,16 |
USHORT usSize; //Size of Object |
}ATOM_VOLTAGE_OBJECT_HEADER_V3; |
|
// ATOM_VOLTAGE_OBJECT_HEADER_V3.ucVoltageMode |
#define VOLTAGE_OBJ_GPIO_LUT 0 //VOLTAGE and GPIO Lookup table ->ATOM_GPIO_VOLTAGE_OBJECT_V3 |
#define VOLTAGE_OBJ_VR_I2C_INIT_SEQ 3 //VOLTAGE REGULATOR INIT sequece through I2C -> ATOM_I2C_VOLTAGE_OBJECT_V3 |
#define VOLTAGE_OBJ_PHASE_LUT 4 //Set Vregulator Phase lookup table ->ATOM_GPIO_VOLTAGE_OBJECT_V3 |
#define VOLTAGE_OBJ_SVID2 7 //Indicate voltage control by SVID2 ->ATOM_SVID2_VOLTAGE_OBJECT_V3 |
#define VOLTAGE_OBJ_EVV 8 |
#define VOLTAGE_OBJ_PWRBOOST_LEAKAGE_LUT 0x10 //Powerboost Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 |
#define VOLTAGE_OBJ_HIGH_STATE_LEAKAGE_LUT 0x11 //High voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 |
#define VOLTAGE_OBJ_HIGH1_STATE_LEAKAGE_LUT 0x12 //High1 voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 |
|
typedef struct _VOLTAGE_LUT_ENTRY_V2 |
{ |
ULONG ulVoltageId; // The Voltage ID which is used to program GPIO register |
4473,7 → 4594,7 |
|
typedef struct _ATOM_I2C_VOLTAGE_OBJECT_V3 |
{ |
ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; |
ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_VR_I2C_INIT_SEQ |
UCHAR ucVoltageRegulatorId; //Indicate Voltage Regulator Id |
UCHAR ucVoltageControlI2cLine; |
UCHAR ucVoltageControlAddress; |
4482,9 → 4603,13 |
VOLTAGE_LUT_ENTRY asVolI2cLut[1]; // end with 0xff |
}ATOM_I2C_VOLTAGE_OBJECT_V3; |
|
// ATOM_I2C_VOLTAGE_OBJECT_V3.ucVoltageControlFlag |
#define VOLTAGE_DATA_ONE_BYTE 0 |
#define VOLTAGE_DATA_TWO_BYTE 1 |
|
typedef struct _ATOM_GPIO_VOLTAGE_OBJECT_V3 |
{ |
ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; |
ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_GPIO_LUT or VOLTAGE_OBJ_PHASE_LUT |
UCHAR ucVoltageGpioCntlId; // default is 0 which indicate control through CG VID mode |
UCHAR ucGpioEntryNum; // indiate the entry numbers of Votlage/Gpio value Look up table |
UCHAR ucPhaseDelay; // phase delay in unit of micro second |
4495,7 → 4620,7 |
|
typedef struct _ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 |
{ |
ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; |
ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = 0x10/0x11/0x12 |
UCHAR ucLeakageCntlId; // default is 0 |
UCHAR ucLeakageEntryNum; // indicate the entry number of LeakageId/Voltage Lut table |
UCHAR ucReserved[2]; |
4503,10 → 4628,27 |
LEAKAGE_VOLTAGE_LUT_ENTRY_V2 asLeakageIdLut[1]; |
}ATOM_LEAKAGE_VOLTAGE_OBJECT_V3; |
|
|
typedef struct _ATOM_SVID2_VOLTAGE_OBJECT_V3 |
{ |
ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_SVID2 |
// 14:7 PSI0_VID |
// 6 PSI0_EN |
// 5 PSI1 |
// 4:2 load line slope trim. |
// 1:0 offset trim, |
USHORT usLoadLine_PSI; |
// GPU GPIO pin Id to SVID2 regulator VRHot pin. possible value 0~31. 0 means GPIO0, 31 means GPIO31 |
UCHAR ucSVDGpioId; //0~31 indicate GPIO0~31 |
UCHAR ucSVCGpioId; //0~31 indicate GPIO0~31 |
ULONG ulReserved; |
}ATOM_SVID2_VOLTAGE_OBJECT_V3; |
|
typedef union _ATOM_VOLTAGE_OBJECT_V3{ |
ATOM_GPIO_VOLTAGE_OBJECT_V3 asGpioVoltageObj; |
ATOM_I2C_VOLTAGE_OBJECT_V3 asI2cVoltageObj; |
ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 asLeakageObj; |
ATOM_SVID2_VOLTAGE_OBJECT_V3 asSVID2Obj; |
}ATOM_VOLTAGE_OBJECT_V3; |
|
typedef struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 |
4536,6 → 4678,64 |
ATOM_ASIC_PROFILE_VOLTAGE asVoltage; |
}ATOM_ASIC_PROFILING_INFO; |
|
typedef struct _ATOM_ASIC_PROFILING_INFO_V2_1 |
{ |
ATOM_COMMON_TABLE_HEADER asHeader; |
UCHAR ucLeakageBinNum; // indicate the entry number of LeakageId/Voltage Lut table |
USHORT usLeakageBinArrayOffset; // offset of USHORT Leakage Bin list array ( from lower LeakageId to higher) |
|
UCHAR ucElbVDDC_Num; |
USHORT usElbVDDC_IdArrayOffset; // offset of USHORT virtual VDDC voltage id ( 0xff01~0xff08 ) |
USHORT usElbVDDC_LevelArrayOffset; // offset of 2 dimension voltage level USHORT array |
|
UCHAR ucElbVDDCI_Num; |
USHORT usElbVDDCI_IdArrayOffset; // offset of USHORT virtual VDDCI voltage id ( 0xff01~0xff08 ) |
USHORT usElbVDDCI_LevelArrayOffset; // offset of 2 dimension voltage level USHORT array |
}ATOM_ASIC_PROFILING_INFO_V2_1; |
|
typedef struct _ATOM_ASIC_PROFILING_INFO_V3_1 |
{ |
ATOM_COMMON_TABLE_HEADER asHeader; |
ULONG ulEvvDerateTdp; |
ULONG ulEvvDerateTdc; |
ULONG ulBoardCoreTemp; |
ULONG ulMaxVddc; |
ULONG ulMinVddc; |
ULONG ulLoadLineSlop; |
ULONG ulLeakageTemp; |
ULONG ulLeakageVoltage; |
ULONG ulCACmEncodeRange; |
ULONG ulCACmEncodeAverage; |
ULONG ulCACbEncodeRange; |
ULONG ulCACbEncodeAverage; |
ULONG ulKt_bEncodeRange; |
ULONG ulKt_bEncodeAverage; |
ULONG ulKv_mEncodeRange; |
ULONG ulKv_mEncodeAverage; |
ULONG ulKv_bEncodeRange; |
ULONG ulKv_bEncodeAverage; |
ULONG ulLkgEncodeLn_MaxDivMin; |
ULONG ulLkgEncodeMin; |
ULONG ulEfuseLogisticAlpha; |
USHORT usPowerDpm0; |
USHORT usCurrentDpm0; |
USHORT usPowerDpm1; |
USHORT usCurrentDpm1; |
USHORT usPowerDpm2; |
USHORT usCurrentDpm2; |
USHORT usPowerDpm3; |
USHORT usCurrentDpm3; |
USHORT usPowerDpm4; |
USHORT usCurrentDpm4; |
USHORT usPowerDpm5; |
USHORT usCurrentDpm5; |
USHORT usPowerDpm6; |
USHORT usCurrentDpm6; |
USHORT usPowerDpm7; |
USHORT usCurrentDpm7; |
}ATOM_ASIC_PROFILING_INFO_V3_1; |
|
|
typedef struct _ATOM_POWER_SOURCE_OBJECT |
{ |
UCHAR ucPwrSrcId; // Power source |
4652,6 → 4852,8 |
#define SYS_INFO_LVDSMISC__888_BPC 0x04 |
#define SYS_INFO_LVDSMISC__OVERRIDE_EN 0x08 |
#define SYS_INFO_LVDSMISC__BLON_ACTIVE_LOW 0x10 |
// new since Trinity |
#define SYS_INFO_LVDSMISC__TRAVIS_LVDS_VOL_OVERRIDE_EN 0x20 |
|
// not used any more |
#define SYS_INFO_LVDSMISC__VSYNC_ACTIVE_LOW 0x04 |
4752,6 → 4954,29 |
ATOM_INTEGRATED_SYSTEM_INFO_V6 sIntegratedSysInfo; |
ULONG ulPowerplayTable[128]; |
}ATOM_FUSION_SYSTEM_INFO_V1; |
|
|
typedef struct _ATOM_TDP_CONFIG_BITS |
{ |
#if ATOM_BIG_ENDIAN |
ULONG uReserved:2; |
ULONG uTDP_Value:14; // Original TDP value in tens of milli watts |
ULONG uCTDP_Value:14; // Override value in tens of milli watts |
ULONG uCTDP_Enable:2; // = (uCTDP_Value > uTDP_Value? 2: (uCTDP_Value < uTDP_Value)) |
#else |
ULONG uCTDP_Enable:2; // = (uCTDP_Value > uTDP_Value? 2: (uCTDP_Value < uTDP_Value)) |
ULONG uCTDP_Value:14; // Override value in tens of milli watts |
ULONG uTDP_Value:14; // Original TDP value in tens of milli watts |
ULONG uReserved:2; |
#endif |
}ATOM_TDP_CONFIG_BITS; |
|
typedef union _ATOM_TDP_CONFIG |
{ |
ATOM_TDP_CONFIG_BITS TDP_config; |
ULONG TDP_config_all; |
}ATOM_TDP_CONFIG; |
|
/********************************************************************************************************************** |
ATOM_FUSION_SYSTEM_INFO_V1 Description |
sIntegratedSysInfo: refer to ATOM_INTEGRATED_SYSTEM_INFO_V6 definition. |
4784,7 → 5009,8 |
UCHAR ucMemoryType; |
UCHAR ucUMAChannelNumber; |
UCHAR strVBIOSMsg[40]; |
ULONG ulReserved[20]; |
ATOM_TDP_CONFIG asTdpConfig; |
ULONG ulReserved[19]; |
ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; |
ULONG ulGMCRestoreResetTime; |
ULONG ulMinimumNClk; |
4809,7 → 5035,7 |
USHORT GnbTdpLimit; |
USHORT usMaxLVDSPclkFreqInSingleLink; |
UCHAR ucLvdsMisc; |
UCHAR ucLVDSReserved; |
UCHAR ucTravisLVDSVolAdjust; |
UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms; |
UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; |
UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; |
4817,7 → 5043,7 |
UCHAR ucLVDSOffToOnDelay_in4Ms; |
UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; |
UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; |
UCHAR ucLVDSReserved1; |
UCHAR ucMinAllowedBL_Level; |
ULONG ulLCDBitDepthControlVal; |
ULONG ulNbpStateMemclkFreq[4]; |
USHORT usNBP2Voltage; |
4846,6 → 5072,7 |
#define SYS_INFO_GPUCAPS__TMDSHDMI_COHERENT_SINGLEPLL_MODE 0x01 |
#define SYS_INFO_GPUCAPS__DP_SINGLEPLL_MODE 0x02 |
#define SYS_INFO_GPUCAPS__DISABLE_AUX_MODE_DETECT 0x08 |
#define SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS 0x10 |
|
/********************************************************************************************************************** |
ATOM_INTEGRATED_SYSTEM_INFO_V1_7 Description |
4945,6 → 5172,9 |
[bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color |
[bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used |
[bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low ) |
[bit5] Travid LVDS output voltage override enable, when =1, use ucTravisLVDSVolAdjust value to overwrite Traivs register LVDS_CTRL_4 |
ucTravisLVDSVolAdjust When ucLVDSMisc[5]=1,it means platform SBIOS want to overwrite TravisLVDSVoltage. Then VBIOS will use ucTravisLVDSVolAdjust |
value to program Travis register LVDS_CTRL_4 |
ucLVDSPwrOnSeqDIGONtoDE_in4Ms: LVDS power up sequence time in unit of 4ms, time delay from DIGON signal active to data enable signal active( DE ). |
=0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. |
This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. |
4964,18 → 5194,241 |
=0 means to use VBIOS default delay which is 125 ( 500ms ). |
This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. |
|
ucLVDSPwrOnVARY_BLtoBLON_in4Ms: LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal active. |
ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms: |
LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal active. |
=0 means to use VBIOS default delay which is 0 ( 0ms ). |
This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. |
|
ucLVDSPwrOffBLONtoVARY_BL_in4Ms: LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal off. |
ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms: |
LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal off. |
=0 means to use VBIOS default delay which is 0 ( 0ms ). |
This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. |
|
ucMinAllowedBL_Level: Lowest LCD backlight PWM level. This is customer platform specific parameters. By default it is 0. |
|
ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB pstate. |
|
**********************************************************************************************************************/ |
|
// this IntegrateSystemInfoTable is used for Kaveri & Kabini APU |
typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 |
{ |
ATOM_COMMON_TABLE_HEADER sHeader; |
ULONG ulBootUpEngineClock; |
ULONG ulDentistVCOFreq; |
ULONG ulBootUpUMAClock; |
ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; |
ULONG ulBootUpReqDisplayVector; |
ULONG ulVBIOSMisc; |
ULONG ulGPUCapInfo; |
ULONG ulDISP_CLK2Freq; |
USHORT usRequestedPWMFreqInHz; |
UCHAR ucHtcTmpLmt; |
UCHAR ucHtcHystLmt; |
ULONG ulReserved2; |
ULONG ulSystemConfig; |
ULONG ulCPUCapInfo; |
ULONG ulReserved3; |
USHORT usGPUReservedSysMemSize; |
USHORT usExtDispConnInfoOffset; |
USHORT usPanelRefreshRateRange; |
UCHAR ucMemoryType; |
UCHAR ucUMAChannelNumber; |
UCHAR strVBIOSMsg[40]; |
ATOM_TDP_CONFIG asTdpConfig; |
ULONG ulReserved[19]; |
ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; |
ULONG ulGMCRestoreResetTime; |
ULONG ulReserved4; |
ULONG ulIdleNClk; |
ULONG ulDDR_DLL_PowerUpTime; |
ULONG ulDDR_PLL_PowerUpTime; |
USHORT usPCIEClkSSPercentage; |
USHORT usPCIEClkSSType; |
USHORT usLvdsSSPercentage; |
USHORT usLvdsSSpreadRateIn10Hz; |
USHORT usHDMISSPercentage; |
USHORT usHDMISSpreadRateIn10Hz; |
USHORT usDVISSPercentage; |
USHORT usDVISSpreadRateIn10Hz; |
ULONG ulGPUReservedSysMemBaseAddrLo; |
ULONG ulGPUReservedSysMemBaseAddrHi; |
ULONG ulReserved5[3]; |
USHORT usMaxLVDSPclkFreqInSingleLink; |
UCHAR ucLvdsMisc; |
UCHAR ucTravisLVDSVolAdjust; |
UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms; |
UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; |
UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; |
UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms; |
UCHAR ucLVDSOffToOnDelay_in4Ms; |
UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; |
UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; |
UCHAR ucMinAllowedBL_Level; |
ULONG ulLCDBitDepthControlVal; |
ULONG ulNbpStateMemclkFreq[4]; |
ULONG ulReserved6; |
ULONG ulNbpStateNClkFreq[4]; |
USHORT usNBPStateVoltage[4]; |
USHORT usBootUpNBVoltage; |
USHORT usReserved2; |
ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; |
}ATOM_INTEGRATED_SYSTEM_INFO_V1_8; |
|
/********************************************************************************************************************** |
ATOM_INTEGRATED_SYSTEM_INFO_V1_8 Description |
ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock |
ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. |
ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. |
sDISPCLK_Voltage: Report Display clock frequency requirement on GNB voltage(up to 4 voltage levels). |
|
ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Trinity projects: |
ATOM_DEVICE_CRT1_SUPPORT 0x0001 |
ATOM_DEVICE_DFP1_SUPPORT 0x0008 |
ATOM_DEVICE_DFP6_SUPPORT 0x0040 |
ATOM_DEVICE_DFP2_SUPPORT 0x0080 |
ATOM_DEVICE_DFP3_SUPPORT 0x0200 |
ATOM_DEVICE_DFP4_SUPPORT 0x0400 |
ATOM_DEVICE_DFP5_SUPPORT 0x0800 |
ATOM_DEVICE_LCD1_SUPPORT 0x0002 |
|
ulVBIOSMisc: Miscellenous flags for VBIOS requirement and interface |
bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is not supported by SBIOS. |
=1: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is supported by SBIOS. |
bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS |
=1: INT15 callback function Get boot display( ax=4e08, bl=01h) is supported by SBIOS |
bit[2]=0: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is not supported by SBIOS |
=1: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is supported by SBIOS |
bit[3]=0: VBIOS fast boot is disable |
=1: VBIOS fast boot is enable. ( VBIOS skip display device detection in every set mode if LCD panel is connect and LID is open) |
|
ulGPUCapInfo: bit[0~2]= Reserved |
bit[3]=0: Enable AUX HW mode detection logic |
=1: Disable AUX HW mode detection logic |
bit[4]=0: Disable DFS bypass feature |
=1: Enable DFS bypass feature |
|
usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). |
Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0; |
|
When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below: |
1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use; |
VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result, |
Changing BL using VBIOS function is functional in both driver and non-driver present environment; |
and enabling VariBri under the driver environment from PP table is optional. |
|
2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating |
that BL control from GPU is expected. |
VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1 |
Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but |
it's per platform |
and enabling VariBri under the driver environment from PP table is optional. |
|
ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. Threshold on value to enter HTC_active state. |
ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. |
To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt. |
|
ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled |
=1: PCIE Power Gating Enabled |
Bit[1]=0: DDR-DLL shut-down feature disabled. |
1: DDR-DLL shut-down feature enabled. |
Bit[2]=0: DDR-PLL Power down feature disabled. |
1: DDR-PLL Power down feature enabled. |
Bit[3]=0: GNB DPM is disabled |
=1: GNB DPM is enabled |
ulCPUCapInfo: TBD |
|
usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure |
usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set |
to indicate a range. |
SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 |
SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 |
SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 |
SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 |
|
ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3;=5:GDDR5; [7:4] is reserved. |
ucUMAChannelNumber: System memory channel numbers. |
|
strVBIOSMsg[40]: VBIOS boot up customized message string |
|
sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high |
|
ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. |
ulIdleNClk: NCLK speed while memory runs in self-refresh state, used to calculate self-refresh latency. Unit in 10kHz. |
ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns. |
ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns. |
|
usPCIEClkSSPercentage: PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%. |
usPCIEClkSSType: PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 for Center spread. |
usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. |
usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. |
usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. |
usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. |
usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. |
usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. |
|
usGPUReservedSysMemSize: Reserved system memory size for ACP engine in APU GNB, units in MB. 0/2/4MB based on CMOS options, current default could be 0MB. KV only, not on KB. |
ulGPUReservedSysMemBaseAddrLo: Low 32 bits base address to the reserved system memory. |
ulGPUReservedSysMemBaseAddrHi: High 32 bits base address to the reserved system memory. |
|
usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz |
ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode |
[bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped |
[bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color |
[bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used |
[bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low ) |
[bit5] Travid LVDS output voltage override enable, when =1, use ucTravisLVDSVolAdjust value to overwrite Traivs register LVDS_CTRL_4 |
ucTravisLVDSVolAdjust When ucLVDSMisc[5]=1,it means platform SBIOS want to overwrite TravisLVDSVoltage. Then VBIOS will use ucTravisLVDSVolAdjust |
value to program Travis register LVDS_CTRL_4 |
ucLVDSPwrOnSeqDIGONtoDE_in4Ms: |
LVDS power up sequence time in unit of 4ms, time delay from DIGON signal active to data enable signal active( DE ). |
=0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. |
This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. |
ucLVDSPwrOnDEtoVARY_BL_in4Ms: |
LVDS power up sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brightness enable signal active( VARY_BL ). |
=0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. |
This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. |
ucLVDSPwrOffVARY_BLtoDE_in4Ms: |
LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off to LCDVCC (DIGON) off. |
=0 mean use VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON |
This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. |
ucLVDSPwrOffDEtoDIGON_in4Ms: |
LVDS power down sequence time in unit of 4ms, time delay from vary brightness enable signal( VARY_BL) off to data enable ( DE ) signal off. |
=0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON |
This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. |
ucLVDSOffToOnDelay_in4Ms: |
LVDS power down sequence time in unit of 4ms. Time delay from DIGON signal off to DIGON signal active. |
=0 means to use VBIOS default delay which is 125 ( 500ms ). |
This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. |
ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms: |
LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal active. |
=0 means to use VBIOS default delay which is 0 ( 0ms ). |
This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. |
|
ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms: |
LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal off. |
=0 means to use VBIOS default delay which is 0 ( 0ms ). |
This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. |
ucMinAllowedBL_Level: Lowest LCD backlight PWM level. This is customer platform specific parameters. By default it is 0. |
|
ulLCDBitDepthControlVal: GPU display control encoder bit dither control setting, used to program register mmFMT_BIT_DEPTH_CONTROL |
|
ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB P-State(P0, P1, P2 & P3). |
ulNbpStateNClkFreq[4]: NB P-State NClk frequency in different NB P-State |
usNBPStateVoltage[4]: NB P-State (P0/P1 & P2/P3) voltage; NBP3 refers to lowes voltage |
usBootUpNBVoltage: NB P-State voltage during boot up before driver loaded |
sExtDispConnInfo: Display connector information table provided to VBIOS |
|
**********************************************************************************************************************/ |
|
// this Table is used for Kaveri/Kabini APU |
typedef struct _ATOM_FUSION_SYSTEM_INFO_V2 |
{ |
ATOM_INTEGRATED_SYSTEM_INFO_V1_8 sIntegratedSysInfo; // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition |
ULONG ulPowerplayTable[128]; // Update comments here to link new powerplay table definition structure |
}ATOM_FUSION_SYSTEM_INFO_V2; |
|
|
/**************************************************************************/ |
// This portion is only used when ext thermal chip or engine/memory clock SS chip is populated on a design |
//Memory SS Info Table |
5036,12 → 5489,14 |
#define ASIC_INTERNAL_SS_ON_DCPLL 8 |
#define ASIC_EXTERNAL_SS_ON_DP_CLOCK 9 |
#define ASIC_INTERNAL_VCE_SS 10 |
#define ASIC_INTERNAL_GPUPLL_SS 11 |
|
|
typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V2 |
{ |
ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz |
//For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 ) |
USHORT usSpreadSpectrumPercentage; //in unit of 0.01% |
USHORT usSpreadSpectrumPercentage; //in unit of 0.01% or 0.001%, decided by ucSpreadSpectrumMode bit4 |
USHORT usSpreadRateIn10Hz; //in unit of 10Hz, modulation freq |
UCHAR ucClockIndication; //Indicate which clock source needs SS |
UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS |
5079,6 → 5534,11 |
UCHAR ucReserved[2]; |
}ATOM_ASIC_SS_ASSIGNMENT_V3; |
|
//ATOM_ASIC_SS_ASSIGNMENT_V3.ucSpreadSpectrumMode |
#define SS_MODE_V3_CENTRE_SPREAD_MASK 0x01 |
#define SS_MODE_V3_EXTERNAL_SS_MASK 0x02 |
#define SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK 0x10 |
|
typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 |
{ |
ATOM_COMMON_TABLE_HEADER sHeader; |
5447,6 → 5907,8 |
#define ATOM_S7_DOS_MODE_PIXEL_DEPTHb0 0x0C |
#define ATOM_S7_DOS_MODE_PIXEL_FORMATb0 0xF0 |
#define ATOM_S7_DOS_8BIT_DAC_ENb1 0x01 |
#define ATOM_S7_ASIC_INIT_COMPLETEb1 0x02 |
#define ATOM_S7_ASIC_INIT_COMPLETE_MASK 0x00000200 |
#define ATOM_S7_DOS_MODE_NUMBERw1 0x0FFFF |
|
#define ATOM_S7_DOS_8BIT_DAC_EN_SHIFT 8 |
5719,6 → 6181,7 |
#define INDIRECT_IO_PCIE 3 |
#define INDIRECT_IO_PCIEP 4 |
#define INDIRECT_IO_NBMISC 5 |
#define INDIRECT_IO_SMU 5 |
|
#define INDIRECT_IO_PLL_READ INDIRECT_IO_PLL | INDIRECT_READ |
#define INDIRECT_IO_PLL_WRITE INDIRECT_IO_PLL | INDIRECT_WRITE |
5730,6 → 6193,8 |
#define INDIRECT_IO_PCIEP_WRITE INDIRECT_IO_PCIEP | INDIRECT_WRITE |
#define INDIRECT_IO_NBMISC_READ INDIRECT_IO_NBMISC | INDIRECT_READ |
#define INDIRECT_IO_NBMISC_WRITE INDIRECT_IO_NBMISC | INDIRECT_WRITE |
#define INDIRECT_IO_SMU_READ INDIRECT_IO_SMU | INDIRECT_READ |
#define INDIRECT_IO_SMU_WRITE INDIRECT_IO_SMU | INDIRECT_WRITE |
|
typedef struct _ATOM_OEM_INFO |
{ |
5875,8 → 6340,10 |
#define _64Mx32 0x43 |
#define _128Mx8 0x51 |
#define _128Mx16 0x52 |
#define _128Mx32 0x53 |
#define _256Mx8 0x61 |
#define _256Mx16 0x62 |
#define _512Mx8 0x71 |
|
#define SAMSUNG 0x1 |
#define INFINEON 0x2 |
5893,7 → 6360,9 |
#define PROMOS MOSEL |
#define KRETON INFINEON |
#define ELIXIR NANYA |
#define MEZZA ELPIDA |
|
|
/////////////Support for GDDR5 MC uCode to reside in upper 64K of ROM///////////// |
|
#define UCODE_ROM_START_ADDRESS 0x1b800 |
6621,10 → 7090,15 |
UCHAR ucMaxActiveDispEngineNum; |
UCHAR ucMaxPPLLNum; |
UCHAR ucCoreRefClkSource; // value of CORE_REF_CLK_SOURCE |
UCHAR ucReserved[3]; |
UCHAR ucDispCaps; |
UCHAR ucReserved[2]; |
ASIC_TRANSMITTER_INFO_V2 asTransmitterInfo[1]; // for alligment only |
}ATOM_DISP_OUT_INFO_V3; |
|
//ucDispCaps |
#define DISPLAY_CAPS__DP_PCLK_FROM_PPLL 0x01 |
#define DISPLAY_CAPS__FORCE_DISPDEV_CONNECTED 0x02 |
|
typedef enum CORE_REF_CLK_SOURCE{ |
CLOCK_SRC_XTALIN=0, |
CLOCK_SRC_XO_IN=1, |
6829,6 → 7303,17 |
USHORT usPhyPllSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings |
}DIG_TRANSMITTER_INFO_HEADER_V3_1; |
|
typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_2{ |
ATOM_COMMON_TABLE_HEADER sHeader; |
USHORT usDPVsPreEmphSettingOffset; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock |
USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info |
USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range |
USHORT usPhyPllRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info |
USHORT usPhyPllSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings |
USHORT usDPSSRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy SS Pll register Info |
USHORT usDPSSSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy SS Pll Settings |
}DIG_TRANSMITTER_INFO_HEADER_V3_2; |
|
typedef struct _CLOCK_CONDITION_REGESTER_INFO{ |
USHORT usRegisterIndex; |
UCHAR ucStartBit; |
6852,6 → 7337,12 |
ULONG ulRegVal; |
}PHY_CONDITION_REG_VAL; |
|
typedef struct _PHY_CONDITION_REG_VAL_V2{ |
ULONG ulCondition; |
UCHAR ucCondition2; |
ULONG ulRegVal; |
}PHY_CONDITION_REG_VAL_V2; |
|
typedef struct _PHY_CONDITION_REG_INFO{ |
USHORT usRegIndex; |
USHORT usSize; |
6858,6 → 7349,12 |
PHY_CONDITION_REG_VAL asRegVal[1]; |
}PHY_CONDITION_REG_INFO; |
|
typedef struct _PHY_CONDITION_REG_INFO_V2{ |
USHORT usRegIndex; |
USHORT usSize; |
PHY_CONDITION_REG_VAL_V2 asRegVal[1]; |
}PHY_CONDITION_REG_INFO_V2; |
|
typedef struct _PHY_ANALOG_SETTING_INFO{ |
UCHAR ucEncodeMode; |
UCHAR ucPhySel; |
6865,6 → 7362,25 |
PHY_CONDITION_REG_INFO asAnalogSetting[1]; |
}PHY_ANALOG_SETTING_INFO; |
|
typedef struct _PHY_ANALOG_SETTING_INFO_V2{ |
UCHAR ucEncodeMode; |
UCHAR ucPhySel; |
USHORT usSize; |
PHY_CONDITION_REG_INFO_V2 asAnalogSetting[1]; |
}PHY_ANALOG_SETTING_INFO_V2; |
|
typedef struct _GFX_HAVESTING_PARAMETERS { |
UCHAR ucGfxBlkId; //GFX blk id to be harvested, like CU, RB or PRIM |
UCHAR ucReserved; //reserved |
UCHAR ucActiveUnitNumPerSH; //requested active CU/RB/PRIM number per shader array |
UCHAR ucMaxUnitNumPerSH; //max CU/RB/PRIM number per shader array |
} GFX_HAVESTING_PARAMETERS; |
|
//ucGfxBlkId |
#define GFX_HARVESTING_CU_ID 0 |
#define GFX_HARVESTING_RB_ID 1 |
#define GFX_HARVESTING_PRIM_ID 2 |
|
/****************************************************************************/ |
//Portion VI: Definitinos for vbios MC scratch registers that driver used |
/****************************************************************************/ |
6875,8 → 7391,17 |
#define MC_MISC0__MEMORY_TYPE__GDDR3 0x30000000 |
#define MC_MISC0__MEMORY_TYPE__GDDR4 0x40000000 |
#define MC_MISC0__MEMORY_TYPE__GDDR5 0x50000000 |
#define MC_MISC0__MEMORY_TYPE__HBM 0x60000000 |
#define MC_MISC0__MEMORY_TYPE__DDR3 0xB0000000 |
|
#define ATOM_MEM_TYPE_DDR_STRING "DDR" |
#define ATOM_MEM_TYPE_DDR2_STRING "DDR2" |
#define ATOM_MEM_TYPE_GDDR3_STRING "GDDR3" |
#define ATOM_MEM_TYPE_GDDR4_STRING "GDDR4" |
#define ATOM_MEM_TYPE_GDDR5_STRING "GDDR5" |
#define ATOM_MEM_TYPE_HBM_STRING "HBM" |
#define ATOM_MEM_TYPE_DDR3_STRING "DDR3" |
|
/****************************************************************************/ |
//Portion VI: Definitinos being oboselete |
/****************************************************************************/ |
7239,566 → 7764,7 |
ATOM_POWERMODE_INFO_V3 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; |
}ATOM_POWERPLAY_INFO_V3; |
|
/* New PPlib */ |
/**************************************************************************/ |
typedef struct _ATOM_PPLIB_THERMALCONTROLLER |
|
{ |
UCHAR ucType; // one of ATOM_PP_THERMALCONTROLLER_* |
UCHAR ucI2cLine; // as interpreted by DAL I2C |
UCHAR ucI2cAddress; |
UCHAR ucFanParameters; // Fan Control Parameters. |
UCHAR ucFanMinRPM; // Fan Minimum RPM (hundreds) -- for display purposes only. |
UCHAR ucFanMaxRPM; // Fan Maximum RPM (hundreds) -- for display purposes only. |
UCHAR ucReserved; // ---- |
UCHAR ucFlags; // to be defined |
} ATOM_PPLIB_THERMALCONTROLLER; |
|
#define ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK 0x0f |
#define ATOM_PP_FANPARAMETERS_NOFAN 0x80 // No fan is connected to this controller. |
|
#define ATOM_PP_THERMALCONTROLLER_NONE 0 |
#define ATOM_PP_THERMALCONTROLLER_LM63 1 // Not used by PPLib |
#define ATOM_PP_THERMALCONTROLLER_ADM1032 2 // Not used by PPLib |
#define ATOM_PP_THERMALCONTROLLER_ADM1030 3 // Not used by PPLib |
#define ATOM_PP_THERMALCONTROLLER_MUA6649 4 // Not used by PPLib |
#define ATOM_PP_THERMALCONTROLLER_LM64 5 |
#define ATOM_PP_THERMALCONTROLLER_F75375 6 // Not used by PPLib |
#define ATOM_PP_THERMALCONTROLLER_RV6xx 7 |
#define ATOM_PP_THERMALCONTROLLER_RV770 8 |
#define ATOM_PP_THERMALCONTROLLER_ADT7473 9 |
#define ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO 11 |
#define ATOM_PP_THERMALCONTROLLER_EVERGREEN 12 |
#define ATOM_PP_THERMALCONTROLLER_EMC2103 13 /* 0x0D */ // Only fan control will be implemented, do NOT show this in PPGen. |
#define ATOM_PP_THERMALCONTROLLER_SUMO 14 /* 0x0E */ // Sumo type, used internally |
#define ATOM_PP_THERMALCONTROLLER_NISLANDS 15 |
#define ATOM_PP_THERMALCONTROLLER_SISLANDS 16 |
#define ATOM_PP_THERMALCONTROLLER_LM96163 17 |
|
// Thermal controller 'combo type' to use an external controller for Fan control and an internal controller for thermal. |
// We probably should reserve the bit 0x80 for this use. |
// To keep the number of these types low we should also use the same code for all ASICs (i.e. do not distinguish RV6xx and RV7xx Internal here). |
// The driver can pick the correct internal controller based on the ASIC. |
|
#define ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL 0x89 // ADT7473 Fan Control + Internal Thermal Controller |
#define ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL 0x8D // EMC2103 Fan Control + Internal Thermal Controller |
|
typedef struct _ATOM_PPLIB_STATE |
{ |
UCHAR ucNonClockStateIndex; |
UCHAR ucClockStateIndices[1]; // variable-sized |
} ATOM_PPLIB_STATE; |
|
|
typedef struct _ATOM_PPLIB_FANTABLE |
{ |
UCHAR ucFanTableFormat; // Change this if the table format changes or version changes so that the other fields are not the same. |
UCHAR ucTHyst; // Temperature hysteresis. Integer. |
USHORT usTMin; // The temperature, in 0.01 centigrades, below which we just run at a minimal PWM. |
USHORT usTMed; // The middle temperature where we change slopes. |
USHORT usTHigh; // The high point above TMed for adjusting the second slope. |
USHORT usPWMMin; // The minimum PWM value in percent (0.01% increments). |
USHORT usPWMMed; // The PWM value (in percent) at TMed. |
USHORT usPWMHigh; // The PWM value at THigh. |
} ATOM_PPLIB_FANTABLE; |
|
typedef struct _ATOM_PPLIB_FANTABLE2 |
{ |
ATOM_PPLIB_FANTABLE basicTable; |
USHORT usTMax; // The max temperature |
} ATOM_PPLIB_FANTABLE2; |
|
typedef struct _ATOM_PPLIB_EXTENDEDHEADER |
{ |
USHORT usSize; |
ULONG ulMaxEngineClock; // For Overdrive. |
ULONG ulMaxMemoryClock; // For Overdrive. |
// Add extra system parameters here, always adjust size to include all fields. |
USHORT usVCETableOffset; //points to ATOM_PPLIB_VCE_Table |
USHORT usUVDTableOffset; //points to ATOM_PPLIB_UVD_Table |
} ATOM_PPLIB_EXTENDEDHEADER; |
|
//// ATOM_PPLIB_POWERPLAYTABLE::ulPlatformCaps |
#define ATOM_PP_PLATFORM_CAP_BACKBIAS 1 |
#define ATOM_PP_PLATFORM_CAP_POWERPLAY 2 |
#define ATOM_PP_PLATFORM_CAP_SBIOSPOWERSOURCE 4 |
#define ATOM_PP_PLATFORM_CAP_ASPM_L0s 8 |
#define ATOM_PP_PLATFORM_CAP_ASPM_L1 16 |
#define ATOM_PP_PLATFORM_CAP_HARDWAREDC 32 |
#define ATOM_PP_PLATFORM_CAP_GEMINIPRIMARY 64 |
#define ATOM_PP_PLATFORM_CAP_STEPVDDC 128 |
#define ATOM_PP_PLATFORM_CAP_VOLTAGECONTROL 256 |
#define ATOM_PP_PLATFORM_CAP_SIDEPORTCONTROL 512 |
#define ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1 1024 |
#define ATOM_PP_PLATFORM_CAP_HTLINKCONTROL 2048 |
#define ATOM_PP_PLATFORM_CAP_MVDDCONTROL 4096 |
#define ATOM_PP_PLATFORM_CAP_GOTO_BOOT_ON_ALERT 0x2000 // Go to boot state on alerts, e.g. on an AC->DC transition. |
#define ATOM_PP_PLATFORM_CAP_DONT_WAIT_FOR_VBLANK_ON_ALERT 0x4000 // Do NOT wait for VBLANK during an alert (e.g. AC->DC transition). |
#define ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL 0x8000 // Does the driver control VDDCI independently from VDDC. |
#define ATOM_PP_PLATFORM_CAP_REGULATOR_HOT 0x00010000 // Enable the 'regulator hot' feature. |
#define ATOM_PP_PLATFORM_CAP_BACO 0x00020000 // Does the driver supports BACO state. |
|
|
typedef struct _ATOM_PPLIB_POWERPLAYTABLE |
{ |
ATOM_COMMON_TABLE_HEADER sHeader; |
|
UCHAR ucDataRevision; |
|
UCHAR ucNumStates; |
UCHAR ucStateEntrySize; |
UCHAR ucClockInfoSize; |
UCHAR ucNonClockSize; |
|
// offset from start of this table to array of ucNumStates ATOM_PPLIB_STATE structures |
USHORT usStateArrayOffset; |
|
// offset from start of this table to array of ASIC-specific structures, |
// currently ATOM_PPLIB_CLOCK_INFO. |
USHORT usClockInfoArrayOffset; |
|
// offset from start of this table to array of ATOM_PPLIB_NONCLOCK_INFO |
USHORT usNonClockInfoArrayOffset; |
|
USHORT usBackbiasTime; // in microseconds |
USHORT usVoltageTime; // in microseconds |
USHORT usTableSize; //the size of this structure, or the extended structure |
|
ULONG ulPlatformCaps; // See ATOM_PPLIB_CAPS_* |
|
ATOM_PPLIB_THERMALCONTROLLER sThermalController; |
|
USHORT usBootClockInfoOffset; |
USHORT usBootNonClockInfoOffset; |
|
} ATOM_PPLIB_POWERPLAYTABLE; |
|
typedef struct _ATOM_PPLIB_POWERPLAYTABLE2 |
{ |
ATOM_PPLIB_POWERPLAYTABLE basicTable; |
UCHAR ucNumCustomThermalPolicy; |
USHORT usCustomThermalPolicyArrayOffset; |
}ATOM_PPLIB_POWERPLAYTABLE2, *LPATOM_PPLIB_POWERPLAYTABLE2; |
|
typedef struct _ATOM_PPLIB_POWERPLAYTABLE3 |
{ |
ATOM_PPLIB_POWERPLAYTABLE2 basicTable2; |
USHORT usFormatID; // To be used ONLY by PPGen. |
USHORT usFanTableOffset; |
USHORT usExtendendedHeaderOffset; |
} ATOM_PPLIB_POWERPLAYTABLE3, *LPATOM_PPLIB_POWERPLAYTABLE3; |
|
typedef struct _ATOM_PPLIB_POWERPLAYTABLE4 |
{ |
ATOM_PPLIB_POWERPLAYTABLE3 basicTable3; |
ULONG ulGoldenPPID; // PPGen use only |
ULONG ulGoldenRevision; // PPGen use only |
USHORT usVddcDependencyOnSCLKOffset; |
USHORT usVddciDependencyOnMCLKOffset; |
USHORT usVddcDependencyOnMCLKOffset; |
USHORT usMaxClockVoltageOnDCOffset; |
USHORT usVddcPhaseShedLimitsTableOffset; // Points to ATOM_PPLIB_PhaseSheddingLimits_Table |
USHORT usReserved; |
} ATOM_PPLIB_POWERPLAYTABLE4, *LPATOM_PPLIB_POWERPLAYTABLE4; |
|
typedef struct _ATOM_PPLIB_POWERPLAYTABLE5 |
{ |
ATOM_PPLIB_POWERPLAYTABLE4 basicTable4; |
ULONG ulTDPLimit; |
ULONG ulNearTDPLimit; |
ULONG ulSQRampingThreshold; |
USHORT usCACLeakageTableOffset; // Points to ATOM_PPLIB_CAC_Leakage_Table |
ULONG ulCACLeakage; // The iLeakage for driver calculated CAC leakage table |
USHORT usTDPODLimit; |
USHORT usLoadLineSlope; // in milliOhms * 100 |
} ATOM_PPLIB_POWERPLAYTABLE5, *LPATOM_PPLIB_POWERPLAYTABLE5; |
|
//// ATOM_PPLIB_NONCLOCK_INFO::usClassification |
#define ATOM_PPLIB_CLASSIFICATION_UI_MASK 0x0007 |
#define ATOM_PPLIB_CLASSIFICATION_UI_SHIFT 0 |
#define ATOM_PPLIB_CLASSIFICATION_UI_NONE 0 |
#define ATOM_PPLIB_CLASSIFICATION_UI_BATTERY 1 |
#define ATOM_PPLIB_CLASSIFICATION_UI_BALANCED 3 |
#define ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE 5 |
// 2, 4, 6, 7 are reserved |
|
#define ATOM_PPLIB_CLASSIFICATION_BOOT 0x0008 |
#define ATOM_PPLIB_CLASSIFICATION_THERMAL 0x0010 |
#define ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE 0x0020 |
#define ATOM_PPLIB_CLASSIFICATION_REST 0x0040 |
#define ATOM_PPLIB_CLASSIFICATION_FORCED 0x0080 |
#define ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE 0x0100 |
#define ATOM_PPLIB_CLASSIFICATION_OVERDRIVETEMPLATE 0x0200 |
#define ATOM_PPLIB_CLASSIFICATION_UVDSTATE 0x0400 |
#define ATOM_PPLIB_CLASSIFICATION_3DLOW 0x0800 |
#define ATOM_PPLIB_CLASSIFICATION_ACPI 0x1000 |
#define ATOM_PPLIB_CLASSIFICATION_HD2STATE 0x2000 |
#define ATOM_PPLIB_CLASSIFICATION_HDSTATE 0x4000 |
#define ATOM_PPLIB_CLASSIFICATION_SDSTATE 0x8000 |
|
//// ATOM_PPLIB_NONCLOCK_INFO::usClassification2 |
#define ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2 0x0001 |
#define ATOM_PPLIB_CLASSIFICATION2_ULV 0x0002 |
#define ATOM_PPLIB_CLASSIFICATION2_MVC 0x0004 //Multi-View Codec (BD-3D) |
|
//// ATOM_PPLIB_NONCLOCK_INFO::ulCapsAndSettings |
#define ATOM_PPLIB_SINGLE_DISPLAY_ONLY 0x00000001 |
#define ATOM_PPLIB_SUPPORTS_VIDEO_PLAYBACK 0x00000002 |
|
// 0 is 2.5Gb/s, 1 is 5Gb/s |
#define ATOM_PPLIB_PCIE_LINK_SPEED_MASK 0x00000004 |
#define ATOM_PPLIB_PCIE_LINK_SPEED_SHIFT 2 |
|
// lanes - 1: 1, 2, 4, 8, 12, 16 permitted by PCIE spec |
#define ATOM_PPLIB_PCIE_LINK_WIDTH_MASK 0x000000F8 |
#define ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT 3 |
|
// lookup into reduced refresh-rate table |
#define ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_MASK 0x00000F00 |
#define ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_SHIFT 8 |
|
#define ATOM_PPLIB_LIMITED_REFRESHRATE_UNLIMITED 0 |
#define ATOM_PPLIB_LIMITED_REFRESHRATE_50HZ 1 |
// 2-15 TBD as needed. |
|
#define ATOM_PPLIB_SOFTWARE_DISABLE_LOADBALANCING 0x00001000 |
#define ATOM_PPLIB_SOFTWARE_ENABLE_SLEEP_FOR_TIMESTAMPS 0x00002000 |
|
#define ATOM_PPLIB_DISALLOW_ON_DC 0x00004000 |
|
#define ATOM_PPLIB_ENABLE_VARIBRIGHT 0x00008000 |
|
//memory related flags |
#define ATOM_PPLIB_SWSTATE_MEMORY_DLL_OFF 0x000010000 |
|
//M3 Arb //2bits, current 3 sets of parameters in total |
#define ATOM_PPLIB_M3ARB_MASK 0x00060000 |
#define ATOM_PPLIB_M3ARB_SHIFT 17 |
|
#define ATOM_PPLIB_ENABLE_DRR 0x00080000 |
|
// remaining 16 bits are reserved |
typedef struct _ATOM_PPLIB_THERMAL_STATE |
{ |
UCHAR ucMinTemperature; |
UCHAR ucMaxTemperature; |
UCHAR ucThermalAction; |
}ATOM_PPLIB_THERMAL_STATE, *LPATOM_PPLIB_THERMAL_STATE; |
|
// Contained in an array starting at the offset |
// in ATOM_PPLIB_POWERPLAYTABLE::usNonClockInfoArrayOffset. |
// referenced from ATOM_PPLIB_STATE_INFO::ucNonClockStateIndex |
#define ATOM_PPLIB_NONCLOCKINFO_VER1 12 |
#define ATOM_PPLIB_NONCLOCKINFO_VER2 24 |
typedef struct _ATOM_PPLIB_NONCLOCK_INFO |
{ |
USHORT usClassification; |
UCHAR ucMinTemperature; |
UCHAR ucMaxTemperature; |
ULONG ulCapsAndSettings; |
UCHAR ucRequiredPower; |
USHORT usClassification2; |
ULONG ulVCLK; |
ULONG ulDCLK; |
UCHAR ucUnused[5]; |
} ATOM_PPLIB_NONCLOCK_INFO; |
|
// Contained in an array starting at the offset |
// in ATOM_PPLIB_POWERPLAYTABLE::usClockInfoArrayOffset. |
// referenced from ATOM_PPLIB_STATE::ucClockStateIndices |
typedef struct _ATOM_PPLIB_R600_CLOCK_INFO |
{ |
USHORT usEngineClockLow; |
UCHAR ucEngineClockHigh; |
|
USHORT usMemoryClockLow; |
UCHAR ucMemoryClockHigh; |
|
USHORT usVDDC; |
USHORT usUnused1; |
USHORT usUnused2; |
|
ULONG ulFlags; // ATOM_PPLIB_R600_FLAGS_* |
|
} ATOM_PPLIB_R600_CLOCK_INFO; |
|
// ulFlags in ATOM_PPLIB_R600_CLOCK_INFO |
#define ATOM_PPLIB_R600_FLAGS_PCIEGEN2 1 |
#define ATOM_PPLIB_R600_FLAGS_UVDSAFE 2 |
#define ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE 4 |
#define ATOM_PPLIB_R600_FLAGS_MEMORY_ODT_OFF 8 |
#define ATOM_PPLIB_R600_FLAGS_MEMORY_DLL_OFF 16 |
#define ATOM_PPLIB_R600_FLAGS_LOWPOWER 32 // On the RV770 use 'low power' setting (sequencer S0). |
|
typedef struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO |
{ |
USHORT usEngineClockLow; |
UCHAR ucEngineClockHigh; |
|
USHORT usMemoryClockLow; |
UCHAR ucMemoryClockHigh; |
|
USHORT usVDDC; |
USHORT usVDDCI; |
USHORT usUnused; |
|
ULONG ulFlags; // ATOM_PPLIB_R600_FLAGS_* |
|
} ATOM_PPLIB_EVERGREEN_CLOCK_INFO; |
|
typedef struct _ATOM_PPLIB_SI_CLOCK_INFO |
{ |
USHORT usEngineClockLow; |
UCHAR ucEngineClockHigh; |
|
USHORT usMemoryClockLow; |
UCHAR ucMemoryClockHigh; |
|
USHORT usVDDC; |
USHORT usVDDCI; |
UCHAR ucPCIEGen; |
UCHAR ucUnused1; |
|
ULONG ulFlags; // ATOM_PPLIB_SI_FLAGS_*, no flag is necessary for now |
|
} ATOM_PPLIB_SI_CLOCK_INFO; |
|
|
typedef struct _ATOM_PPLIB_RS780_CLOCK_INFO |
|
{ |
USHORT usLowEngineClockLow; // Low Engine clock in MHz (the same way as on the R600). |
UCHAR ucLowEngineClockHigh; |
USHORT usHighEngineClockLow; // High Engine clock in MHz. |
UCHAR ucHighEngineClockHigh; |
USHORT usMemoryClockLow; // For now one of the ATOM_PPLIB_RS780_SPMCLK_XXXX constants. |
UCHAR ucMemoryClockHigh; // Currentyl unused. |
UCHAR ucPadding; // For proper alignment and size. |
USHORT usVDDC; // For the 780, use: None, Low, High, Variable |
UCHAR ucMaxHTLinkWidth; // From SBIOS - {2, 4, 8, 16} |
UCHAR ucMinHTLinkWidth; // From SBIOS - {2, 4, 8, 16}. Effective only if CDLW enabled. Minimum down stream width could be bigger as display BW requriement. |
USHORT usHTLinkFreq; // See definition ATOM_PPLIB_RS780_HTLINKFREQ_xxx or in MHz(>=200). |
ULONG ulFlags; |
} ATOM_PPLIB_RS780_CLOCK_INFO; |
|
#define ATOM_PPLIB_RS780_VOLTAGE_NONE 0 |
#define ATOM_PPLIB_RS780_VOLTAGE_LOW 1 |
#define ATOM_PPLIB_RS780_VOLTAGE_HIGH 2 |
#define ATOM_PPLIB_RS780_VOLTAGE_VARIABLE 3 |
|
#define ATOM_PPLIB_RS780_SPMCLK_NONE 0 // We cannot change the side port memory clock, leave it as it is. |
#define ATOM_PPLIB_RS780_SPMCLK_LOW 1 |
#define ATOM_PPLIB_RS780_SPMCLK_HIGH 2 |
|
#define ATOM_PPLIB_RS780_HTLINKFREQ_NONE 0 |
#define ATOM_PPLIB_RS780_HTLINKFREQ_LOW 1 |
#define ATOM_PPLIB_RS780_HTLINKFREQ_HIGH 2 |
|
typedef struct _ATOM_PPLIB_SUMO_CLOCK_INFO{ |
USHORT usEngineClockLow; //clockfrequency & 0xFFFF. The unit is in 10khz |
UCHAR ucEngineClockHigh; //clockfrequency >> 16. |
UCHAR vddcIndex; //2-bit vddc index; |
USHORT tdpLimit; |
//please initalize to 0 |
USHORT rsv1; |
//please initialize to 0s |
ULONG rsv2[2]; |
}ATOM_PPLIB_SUMO_CLOCK_INFO; |
|
|
|
typedef struct _ATOM_PPLIB_STATE_V2 |
{ |
//number of valid dpm levels in this state; Driver uses it to calculate the whole |
//size of the state: sizeof(ATOM_PPLIB_STATE_V2) + (ucNumDPMLevels - 1) * sizeof(UCHAR) |
UCHAR ucNumDPMLevels; |
|
//a index to the array of nonClockInfos |
UCHAR nonClockInfoIndex; |
/** |
* Driver will read the first ucNumDPMLevels in this array |
*/ |
UCHAR clockInfoIndex[1]; |
} ATOM_PPLIB_STATE_V2; |
|
typedef struct _StateArray{ |
//how many states we have |
UCHAR ucNumEntries; |
|
ATOM_PPLIB_STATE_V2 states[1]; |
}StateArray; |
|
|
typedef struct _ClockInfoArray{ |
//how many clock levels we have |
UCHAR ucNumEntries; |
|
//sizeof(ATOM_PPLIB_CLOCK_INFO) |
UCHAR ucEntrySize; |
|
UCHAR clockInfo[1]; |
}ClockInfoArray; |
|
typedef struct _NonClockInfoArray{ |
|
//how many non-clock levels we have. normally should be same as number of states |
UCHAR ucNumEntries; |
//sizeof(ATOM_PPLIB_NONCLOCK_INFO) |
UCHAR ucEntrySize; |
|
ATOM_PPLIB_NONCLOCK_INFO nonClockInfo[1]; |
}NonClockInfoArray; |
|
typedef struct _ATOM_PPLIB_Clock_Voltage_Dependency_Record |
{ |
USHORT usClockLow; |
UCHAR ucClockHigh; |
USHORT usVoltage; |
}ATOM_PPLIB_Clock_Voltage_Dependency_Record; |
|
typedef struct _ATOM_PPLIB_Clock_Voltage_Dependency_Table |
{ |
UCHAR ucNumEntries; // Number of entries. |
ATOM_PPLIB_Clock_Voltage_Dependency_Record entries[1]; // Dynamically allocate entries. |
}ATOM_PPLIB_Clock_Voltage_Dependency_Table; |
|
typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Record |
{ |
USHORT usSclkLow; |
UCHAR ucSclkHigh; |
USHORT usMclkLow; |
UCHAR ucMclkHigh; |
USHORT usVddc; |
USHORT usVddci; |
}ATOM_PPLIB_Clock_Voltage_Limit_Record; |
|
typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Table |
{ |
UCHAR ucNumEntries; // Number of entries. |
ATOM_PPLIB_Clock_Voltage_Limit_Record entries[1]; // Dynamically allocate entries. |
}ATOM_PPLIB_Clock_Voltage_Limit_Table; |
|
typedef struct _ATOM_PPLIB_CAC_Leakage_Record |
{ |
USHORT usVddc; // We use this field for the "fake" standardized VDDC for power calculations |
ULONG ulLeakageValue; |
}ATOM_PPLIB_CAC_Leakage_Record; |
|
typedef struct _ATOM_PPLIB_CAC_Leakage_Table |
{ |
UCHAR ucNumEntries; // Number of entries. |
ATOM_PPLIB_CAC_Leakage_Record entries[1]; // Dynamically allocate entries. |
}ATOM_PPLIB_CAC_Leakage_Table; |
|
typedef struct _ATOM_PPLIB_PhaseSheddingLimits_Record |
{ |
USHORT usVoltage; |
USHORT usSclkLow; |
UCHAR ucSclkHigh; |
USHORT usMclkLow; |
UCHAR ucMclkHigh; |
}ATOM_PPLIB_PhaseSheddingLimits_Record; |
|
typedef struct _ATOM_PPLIB_PhaseSheddingLimits_Table |
{ |
UCHAR ucNumEntries; // Number of entries. |
ATOM_PPLIB_PhaseSheddingLimits_Record entries[1]; // Dynamically allocate entries. |
}ATOM_PPLIB_PhaseSheddingLimits_Table; |
|
typedef struct _VCEClockInfo{ |
USHORT usEVClkLow; |
UCHAR ucEVClkHigh; |
USHORT usECClkLow; |
UCHAR ucECClkHigh; |
}VCEClockInfo; |
|
typedef struct _VCEClockInfoArray{ |
UCHAR ucNumEntries; |
VCEClockInfo entries[1]; |
}VCEClockInfoArray; |
|
typedef struct _ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record |
{ |
USHORT usVoltage; |
UCHAR ucVCEClockInfoIndex; |
}ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record; |
|
typedef struct _ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table |
{ |
UCHAR numEntries; |
ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record entries[1]; |
}ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table; |
|
typedef struct _ATOM_PPLIB_VCE_State_Record |
{ |
UCHAR ucVCEClockInfoIndex; |
UCHAR ucClockInfoIndex; //highest 2 bits indicates memory p-states, lower 6bits indicates index to ClockInfoArrary |
}ATOM_PPLIB_VCE_State_Record; |
|
typedef struct _ATOM_PPLIB_VCE_State_Table |
{ |
UCHAR numEntries; |
ATOM_PPLIB_VCE_State_Record entries[1]; |
}ATOM_PPLIB_VCE_State_Table; |
|
|
typedef struct _ATOM_PPLIB_VCE_Table |
{ |
UCHAR revid; |
// VCEClockInfoArray array; |
// ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table limits; |
// ATOM_PPLIB_VCE_State_Table states; |
}ATOM_PPLIB_VCE_Table; |
|
|
typedef struct _UVDClockInfo{ |
USHORT usVClkLow; |
UCHAR ucVClkHigh; |
USHORT usDClkLow; |
UCHAR ucDClkHigh; |
}UVDClockInfo; |
|
typedef struct _UVDClockInfoArray{ |
UCHAR ucNumEntries; |
UVDClockInfo entries[1]; |
}UVDClockInfoArray; |
|
typedef struct _ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record |
{ |
USHORT usVoltage; |
UCHAR ucUVDClockInfoIndex; |
}ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record; |
|
typedef struct _ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table |
{ |
UCHAR numEntries; |
ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record entries[1]; |
}ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table; |
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typedef struct _ATOM_PPLIB_UVD_State_Record |
{ |
UCHAR ucUVDClockInfoIndex; |
UCHAR ucClockInfoIndex; //highest 2 bits indicates memory p-states, lower 6bits indicates index to ClockInfoArrary |
}ATOM_PPLIB_UVD_State_Record; |
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typedef struct _ATOM_PPLIB_UVD_State_Table |
{ |
UCHAR numEntries; |
ATOM_PPLIB_UVD_State_Record entries[1]; |
}ATOM_PPLIB_UVD_State_Table; |
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typedef struct _ATOM_PPLIB_UVD_Table |
{ |
UCHAR revid; |
// UVDClockInfoArray array; |
// ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table limits; |
// ATOM_PPLIB_UVD_State_Table states; |
}ATOM_PPLIB_UVD_Table; |
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/**************************************************************************/ |
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// Following definitions are for compatibility issue in different SW components. |
#define ATOM_MASTER_DATA_TABLE_REVISION 0x01 |
#define Object_Info Object_Header |
8010,3 → 7976,6 |
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#endif /* _ATOMBIOS_H */ |
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#include "pptable.h" |
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