| /drivers/video/drm/include/drm_crtc.h |
|---|
| 0,0 → 1,739 |
| /* |
| * Copyright © 2006 Keith Packard |
| * Copyright © 2007-2008 Dave Airlie |
| * Copyright © 2007-2008 Intel Corporation |
| * Jesse Barnes <jesse.barnes@intel.com> |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice shall be included in |
| * all copies or substantial portions of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| * OTHER DEALINGS IN THE SOFTWARE. |
| */ |
| #ifndef __DRM_CRTC_H__ |
| #define __DRM_CRTC_H__ |
| //#include <linux/i2c.h> |
| //#include <linux/spinlock.h> |
| //#include <linux/types.h> |
| //#include <linux/idr.h> |
| //#include <linux/fb.h> |
| struct drm_device; |
| struct drm_mode_set; |
| struct drm_framebuffer; |
| #define DRM_MODE_OBJECT_CRTC 0xcccccccc |
| #define DRM_MODE_OBJECT_CONNECTOR 0xc0c0c0c0 |
| #define DRM_MODE_OBJECT_ENCODER 0xe0e0e0e0 |
| #define DRM_MODE_OBJECT_MODE 0xdededede |
| #define DRM_MODE_OBJECT_PROPERTY 0xb0b0b0b0 |
| #define DRM_MODE_OBJECT_FB 0xfbfbfbfb |
| #define DRM_MODE_OBJECT_BLOB 0xbbbbbbbb |
| struct drm_mode_object { |
| uint32_t id; |
| uint32_t type; |
| }; |
| /* |
| * Note on terminology: here, for brevity and convenience, we refer to connector |
| * control chips as 'CRTCs'. They can control any type of connector, VGA, LVDS, |
| * DVI, etc. And 'screen' refers to the whole of the visible display, which |
| * may span multiple monitors (and therefore multiple CRTC and connector |
| * structures). |
| */ |
| enum drm_mode_status { |
| MODE_OK = 0, /* Mode OK */ |
| MODE_HSYNC, /* hsync out of range */ |
| MODE_VSYNC, /* vsync out of range */ |
| MODE_H_ILLEGAL, /* mode has illegal horizontal timings */ |
| MODE_V_ILLEGAL, /* mode has illegal horizontal timings */ |
| MODE_BAD_WIDTH, /* requires an unsupported linepitch */ |
| MODE_NOMODE, /* no mode with a maching name */ |
| MODE_NO_INTERLACE, /* interlaced mode not supported */ |
| MODE_NO_DBLESCAN, /* doublescan mode not supported */ |
| MODE_NO_VSCAN, /* multiscan mode not supported */ |
| MODE_MEM, /* insufficient video memory */ |
| MODE_VIRTUAL_X, /* mode width too large for specified virtual size */ |
| MODE_VIRTUAL_Y, /* mode height too large for specified virtual size */ |
| MODE_MEM_VIRT, /* insufficient video memory given virtual size */ |
| MODE_NOCLOCK, /* no fixed clock available */ |
| MODE_CLOCK_HIGH, /* clock required is too high */ |
| MODE_CLOCK_LOW, /* clock required is too low */ |
| MODE_CLOCK_RANGE, /* clock/mode isn't in a ClockRange */ |
| MODE_BAD_HVALUE, /* horizontal timing was out of range */ |
| MODE_BAD_VVALUE, /* vertical timing was out of range */ |
| MODE_BAD_VSCAN, /* VScan value out of range */ |
| MODE_HSYNC_NARROW, /* horizontal sync too narrow */ |
| MODE_HSYNC_WIDE, /* horizontal sync too wide */ |
| MODE_HBLANK_NARROW, /* horizontal blanking too narrow */ |
| MODE_HBLANK_WIDE, /* horizontal blanking too wide */ |
| MODE_VSYNC_NARROW, /* vertical sync too narrow */ |
| MODE_VSYNC_WIDE, /* vertical sync too wide */ |
| MODE_VBLANK_NARROW, /* vertical blanking too narrow */ |
| MODE_VBLANK_WIDE, /* vertical blanking too wide */ |
| MODE_PANEL, /* exceeds panel dimensions */ |
| MODE_INTERLACE_WIDTH, /* width too large for interlaced mode */ |
| MODE_ONE_WIDTH, /* only one width is supported */ |
| MODE_ONE_HEIGHT, /* only one height is supported */ |
| MODE_ONE_SIZE, /* only one resolution is supported */ |
| MODE_NO_REDUCED, /* monitor doesn't accept reduced blanking */ |
| MODE_UNVERIFIED = -3, /* mode needs to reverified */ |
| MODE_BAD = -2, /* unspecified reason */ |
| MODE_ERROR = -1 /* error condition */ |
| }; |
| #define DRM_MODE_TYPE_CLOCK_CRTC_C (DRM_MODE_TYPE_CLOCK_C | \ |
| DRM_MODE_TYPE_CRTC_C) |
| #define DRM_MODE(nm, t, c, hd, hss, hse, ht, hsk, vd, vss, vse, vt, vs, f) \ |
| .name = nm, .status = 0, .type = (t), .clock = (c), \ |
| .hdisplay = (hd), .hsync_start = (hss), .hsync_end = (hse), \ |
| .htotal = (ht), .hskew = (hsk), .vdisplay = (vd), \ |
| .vsync_start = (vss), .vsync_end = (vse), .vtotal = (vt), \ |
| .vscan = (vs), .flags = (f), .vrefresh = 0 |
| #define CRTC_INTERLACE_HALVE_V 0x1 /* halve V values for interlacing */ |
| struct drm_display_mode { |
| /* Header */ |
| // struct list_head head; |
| struct drm_mode_object base; |
| char name[DRM_DISPLAY_MODE_LEN]; |
| int connector_count; |
| enum drm_mode_status status; |
| int type; |
| /* Proposed mode values */ |
| int clock; |
| int hdisplay; |
| int hsync_start; |
| int hsync_end; |
| int htotal; |
| int hskew; |
| int vdisplay; |
| int vsync_start; |
| int vsync_end; |
| int vtotal; |
| int vscan; |
| unsigned int flags; |
| /* Addressable image size (may be 0 for projectors, etc.) */ |
| int width_mm; |
| int height_mm; |
| /* Actual mode we give to hw */ |
| int clock_index; |
| int synth_clock; |
| int crtc_hdisplay; |
| int crtc_hblank_start; |
| int crtc_hblank_end; |
| int crtc_hsync_start; |
| int crtc_hsync_end; |
| int crtc_htotal; |
| int crtc_hskew; |
| int crtc_vdisplay; |
| int crtc_vblank_start; |
| int crtc_vblank_end; |
| int crtc_vsync_start; |
| int crtc_vsync_end; |
| int crtc_vtotal; |
| int crtc_hadjusted; |
| int crtc_vadjusted; |
| /* Driver private mode info */ |
| int private_size; |
| int *private; |
| int private_flags; |
| int vrefresh; |
| float hsync; |
| }; |
| enum drm_connector_status { |
| connector_status_connected = 1, |
| connector_status_disconnected = 2, |
| connector_status_unknown = 3, |
| }; |
| enum subpixel_order { |
| SubPixelUnknown = 0, |
| SubPixelHorizontalRGB, |
| SubPixelHorizontalBGR, |
| SubPixelVerticalRGB, |
| SubPixelVerticalBGR, |
| SubPixelNone, |
| }; |
| /* |
| * Describes a given display (e.g. CRT or flat panel) and its limitations. |
| */ |
| struct drm_display_info { |
| char name[DRM_DISPLAY_INFO_LEN]; |
| /* Input info */ |
| bool serration_vsync; |
| bool sync_on_green; |
| bool composite_sync; |
| bool separate_syncs; |
| bool blank_to_black; |
| unsigned char video_level; |
| bool digital; |
| /* Physical size */ |
| unsigned int width_mm; |
| unsigned int height_mm; |
| /* Display parameters */ |
| unsigned char gamma; /* FIXME: storage format */ |
| bool gtf_supported; |
| bool standard_color; |
| enum { |
| monochrome = 0, |
| rgb, |
| other, |
| unknown, |
| } display_type; |
| bool active_off_supported; |
| bool suspend_supported; |
| bool standby_supported; |
| /* Color info FIXME: storage format */ |
| unsigned short redx, redy; |
| unsigned short greenx, greeny; |
| unsigned short bluex, bluey; |
| unsigned short whitex, whitey; |
| /* Clock limits FIXME: storage format */ |
| unsigned int min_vfreq, max_vfreq; |
| unsigned int min_hfreq, max_hfreq; |
| unsigned int pixel_clock; |
| /* White point indices FIXME: storage format */ |
| unsigned int wpx1, wpy1; |
| unsigned int wpgamma1; |
| unsigned int wpx2, wpy2; |
| unsigned int wpgamma2; |
| enum subpixel_order subpixel_order; |
| char *raw_edid; /* if any */ |
| }; |
| struct drm_framebuffer_funcs { |
| void (*destroy)(struct drm_framebuffer *framebuffer); |
| int (*create_handle)(struct drm_framebuffer *fb, |
| struct drm_file *file_priv, |
| unsigned int *handle); |
| }; |
| struct drm_framebuffer { |
| struct drm_device *dev; |
| // struct list_head head; |
| struct drm_mode_object base; |
| const struct drm_framebuffer_funcs *funcs; |
| unsigned int pitch; |
| unsigned int width; |
| unsigned int height; |
| /* depth can be 15 or 16 */ |
| unsigned int depth; |
| int bits_per_pixel; |
| int flags; |
| void *fbdev; |
| u32_t pseudo_palette[17]; |
| // struct list_head filp_head; |
| }; |
| struct drm_property_blob { |
| struct drm_mode_object base; |
| // struct list_head head; |
| unsigned int length; |
| void *data; |
| }; |
| struct drm_property_enum { |
| uint64_t value; |
| // struct list_head head; |
| char name[DRM_PROP_NAME_LEN]; |
| }; |
| struct drm_property { |
| // struct list_head head; |
| struct drm_mode_object base; |
| uint32_t flags; |
| char name[DRM_PROP_NAME_LEN]; |
| uint32_t num_values; |
| uint64_t *values; |
| // struct list_head enum_blob_list; |
| }; |
| struct drm_crtc; |
| struct drm_connector; |
| struct drm_encoder; |
| /** |
| * drm_crtc_funcs - control CRTCs for a given device |
| * @dpms: control display power levels |
| * @save: save CRTC state |
| * @resore: restore CRTC state |
| * @lock: lock the CRTC |
| * @unlock: unlock the CRTC |
| * @shadow_allocate: allocate shadow pixmap |
| * @shadow_create: create shadow pixmap for rotation support |
| * @shadow_destroy: free shadow pixmap |
| * @mode_fixup: fixup proposed mode |
| * @mode_set: set the desired mode on the CRTC |
| * @gamma_set: specify color ramp for CRTC |
| * @destroy: deinit and free object. |
| * |
| * The drm_crtc_funcs structure is the central CRTC management structure |
| * in the DRM. Each CRTC controls one or more connectors (note that the name |
| * CRTC is simply historical, a CRTC may control LVDS, VGA, DVI, TV out, etc. |
| * connectors, not just CRTs). |
| * |
| * Each driver is responsible for filling out this structure at startup time, |
| * in addition to providing other modesetting features, like i2c and DDC |
| * bus accessors. |
| */ |
| struct drm_crtc_funcs { |
| /* Save CRTC state */ |
| void (*save)(struct drm_crtc *crtc); /* suspend? */ |
| /* Restore CRTC state */ |
| void (*restore)(struct drm_crtc *crtc); /* resume? */ |
| /* cursor controls */ |
| int (*cursor_set)(struct drm_crtc *crtc, struct drm_file *file_priv, |
| uint32_t handle, uint32_t width, uint32_t height); |
| int (*cursor_move)(struct drm_crtc *crtc, int x, int y); |
| /* Set gamma on the CRTC */ |
| void (*gamma_set)(struct drm_crtc *crtc, u16_t *r, u16_t *g, u16_t *b, |
| uint32_t size); |
| /* Object destroy routine */ |
| void (*destroy)(struct drm_crtc *crtc); |
| int (*set_config)(struct drm_mode_set *set); |
| }; |
| /** |
| * drm_crtc - central CRTC control structure |
| * @enabled: is this CRTC enabled? |
| * @x: x position on screen |
| * @y: y position on screen |
| * @desired_mode: new desired mode |
| * @desired_x: desired x for desired_mode |
| * @desired_y: desired y for desired_mode |
| * @funcs: CRTC control functions |
| * |
| * Each CRTC may have one or more connectors associated with it. This structure |
| * allows the CRTC to be controlled. |
| */ |
| struct drm_crtc { |
| struct drm_device *dev; |
| // struct list_head head; |
| struct drm_mode_object base; |
| /* framebuffer the connector is currently bound to */ |
| struct drm_framebuffer *fb; |
| bool enabled; |
| struct drm_display_mode mode; |
| int x, y; |
| struct drm_display_mode *desired_mode; |
| int desired_x, desired_y; |
| const struct drm_crtc_funcs *funcs; |
| /* CRTC gamma size for reporting to userspace */ |
| uint32_t gamma_size; |
| uint16_t *gamma_store; |
| /* if you are using the helper */ |
| void *helper_private; |
| }; |
| /** |
| * drm_connector_funcs - control connectors on a given device |
| * @dpms: set power state (see drm_crtc_funcs above) |
| * @save: save connector state |
| * @restore: restore connector state |
| * @mode_valid: is this mode valid on the given connector? |
| * @mode_fixup: try to fixup proposed mode for this connector |
| * @mode_set: set this mode |
| * @detect: is this connector active? |
| * @get_modes: get mode list for this connector |
| * @set_property: property for this connector may need update |
| * @destroy: make object go away |
| * |
| * Each CRTC may have one or more connectors attached to it. The functions |
| * below allow the core DRM code to control connectors, enumerate available modes, |
| * etc. |
| */ |
| struct drm_connector_funcs { |
| void (*dpms)(struct drm_connector *connector, int mode); |
| void (*save)(struct drm_connector *connector); |
| void (*restore)(struct drm_connector *connector); |
| enum drm_connector_status (*detect)(struct drm_connector *connector); |
| int (*fill_modes)(struct drm_connector *connector, uint32_t max_width, uint32_t max_height); |
| int (*set_property)(struct drm_connector *connector, struct drm_property *property, |
| uint64_t val); |
| void (*destroy)(struct drm_connector *connector); |
| }; |
| struct drm_encoder_funcs { |
| void (*destroy)(struct drm_encoder *encoder); |
| }; |
| #define DRM_CONNECTOR_MAX_UMODES 16 |
| #define DRM_CONNECTOR_MAX_PROPERTY 16 |
| #define DRM_CONNECTOR_LEN 32 |
| #define DRM_CONNECTOR_MAX_ENCODER 2 |
| /** |
| * drm_encoder - central DRM encoder structure |
| */ |
| struct drm_encoder { |
| struct drm_device *dev; |
| // struct list_head head; |
| struct drm_mode_object base; |
| int encoder_type; |
| uint32_t possible_crtcs; |
| uint32_t possible_clones; |
| struct drm_crtc *crtc; |
| const struct drm_encoder_funcs *funcs; |
| void *helper_private; |
| }; |
| /** |
| * drm_connector - central DRM connector control structure |
| * @crtc: CRTC this connector is currently connected to, NULL if none |
| * @interlace_allowed: can this connector handle interlaced modes? |
| * @doublescan_allowed: can this connector handle doublescan? |
| * @available_modes: modes available on this connector (from get_modes() + user) |
| * @initial_x: initial x position for this connector |
| * @initial_y: initial y position for this connector |
| * @status: connector connected? |
| * @funcs: connector control functions |
| * |
| * Each connector may be connected to one or more CRTCs, or may be clonable by |
| * another connector if they can share a CRTC. Each connector also has a specific |
| * position in the broader display (referred to as a 'screen' though it could |
| * span multiple monitors). |
| */ |
| struct drm_connector { |
| struct drm_device *dev; |
| // struct device kdev; |
| struct device_attribute *attr; |
| // struct list_head head; |
| struct drm_mode_object base; |
| int connector_type; |
| int connector_type_id; |
| bool interlace_allowed; |
| bool doublescan_allowed; |
| // struct list_head modes; /* list of modes on this connector */ |
| int initial_x, initial_y; |
| enum drm_connector_status status; |
| /* these are modes added by probing with DDC or the BIOS */ |
| // struct list_head probed_modes; |
| struct drm_display_info display_info; |
| const struct drm_connector_funcs *funcs; |
| // struct list_head user_modes; |
| struct drm_property_blob *edid_blob_ptr; |
| u32_t property_ids[DRM_CONNECTOR_MAX_PROPERTY]; |
| uint64_t property_values[DRM_CONNECTOR_MAX_PROPERTY]; |
| /* requested DPMS state */ |
| int dpms; |
| void *helper_private; |
| uint32_t encoder_ids[DRM_CONNECTOR_MAX_ENCODER]; |
| uint32_t force_encoder_id; |
| struct drm_encoder *encoder; /* currently active encoder */ |
| }; |
| /** |
| * struct drm_mode_set |
| * |
| * Represents a single crtc the connectors that it drives with what mode |
| * and from which framebuffer it scans out from. |
| * |
| * This is used to set modes. |
| */ |
| struct drm_mode_set { |
| // struct list_head head; |
| struct drm_framebuffer *fb; |
| struct drm_crtc *crtc; |
| struct drm_display_mode *mode; |
| uint32_t x; |
| uint32_t y; |
| struct drm_connector **connectors; |
| size_t num_connectors; |
| }; |
| /** |
| * struct drm_mode_config_funcs - configure CRTCs for a given screen layout |
| * @resize: adjust CRTCs as necessary for the proposed layout |
| * |
| * Currently only a resize hook is available. DRM will call back into the |
| * driver with a new screen width and height. If the driver can't support |
| * the proposed size, it can return false. Otherwise it should adjust |
| * the CRTC<->connector mappings as needed and update its view of the screen. |
| */ |
| struct drm_mode_config_funcs { |
| struct drm_framebuffer *(*fb_create)(struct drm_device *dev, struct drm_file *file_priv, struct drm_mode_fb_cmd *mode_cmd); |
| int (*fb_changed)(struct drm_device *dev); |
| }; |
| struct drm_mode_group { |
| uint32_t num_crtcs; |
| uint32_t num_encoders; |
| uint32_t num_connectors; |
| /* list of object IDs for this group */ |
| uint32_t *id_list; |
| }; |
| /** |
| * drm_mode_config - Mode configuration control structure |
| * |
| */ |
| struct drm_mode_config { |
| // struct mutex mutex; /* protects configuration (mode lists etc.) */ |
| // struct mutex idr_mutex; /* for IDR management */ |
| // struct idr crtc_idr; /* use this idr for all IDs, fb, crtc, connector, modes - just makes life easier */ |
| /* this is limited to one for now */ |
| int num_fb; |
| // struct list_head fb_list; |
| int num_connector; |
| // struct list_head connector_list; |
| int num_encoder; |
| // struct list_head encoder_list; |
| int num_crtc; |
| // struct list_head crtc_list; |
| // struct list_head property_list; |
| /* in-kernel framebuffers - hung of filp_head in drm_framebuffer */ |
| // struct list_head fb_kernel_list; |
| int min_width, min_height; |
| int max_width, max_height; |
| struct drm_mode_config_funcs *funcs; |
| resource_size_t fb_base; |
| /* pointers to standard properties */ |
| // struct list_head property_blob_list; |
| struct drm_property *edid_property; |
| struct drm_property *dpms_property; |
| /* DVI-I properties */ |
| struct drm_property *dvi_i_subconnector_property; |
| struct drm_property *dvi_i_select_subconnector_property; |
| /* TV properties */ |
| struct drm_property *tv_subconnector_property; |
| struct drm_property *tv_select_subconnector_property; |
| struct drm_property *tv_mode_property; |
| struct drm_property *tv_left_margin_property; |
| struct drm_property *tv_right_margin_property; |
| struct drm_property *tv_top_margin_property; |
| struct drm_property *tv_bottom_margin_property; |
| /* Optional properties */ |
| struct drm_property *scaling_mode_property; |
| struct drm_property *dithering_mode_property; |
| }; |
| #define obj_to_crtc(x) container_of(x, struct drm_crtc, base) |
| #define obj_to_connector(x) container_of(x, struct drm_connector, base) |
| #define obj_to_encoder(x) container_of(x, struct drm_encoder, base) |
| #define obj_to_mode(x) container_of(x, struct drm_display_mode, base) |
| #define obj_to_fb(x) container_of(x, struct drm_framebuffer, base) |
| #define obj_to_property(x) container_of(x, struct drm_property, base) |
| #define obj_to_blob(x) container_of(x, struct drm_property_blob, base) |
| extern void drm_crtc_init(struct drm_device *dev, |
| struct drm_crtc *crtc, |
| const struct drm_crtc_funcs *funcs); |
| extern void drm_crtc_cleanup(struct drm_crtc *crtc); |
| extern void drm_connector_init(struct drm_device *dev, |
| struct drm_connector *connector, |
| const struct drm_connector_funcs *funcs, |
| int connector_type); |
| extern void drm_connector_cleanup(struct drm_connector *connector); |
| extern void drm_encoder_init(struct drm_device *dev, |
| struct drm_encoder *encoder, |
| const struct drm_encoder_funcs *funcs, |
| int encoder_type); |
| extern void drm_encoder_cleanup(struct drm_encoder *encoder); |
| extern char *drm_get_connector_name(struct drm_connector *connector); |
| extern char *drm_get_dpms_name(int val); |
| extern char *drm_get_dvi_i_subconnector_name(int val); |
| extern char *drm_get_dvi_i_select_name(int val); |
| extern char *drm_get_tv_subconnector_name(int val); |
| extern char *drm_get_tv_select_name(int val); |
| extern void drm_fb_release(struct drm_file *file_priv); |
| extern int drm_mode_group_init_legacy_group(struct drm_device *dev, struct drm_mode_group *group); |
| //extern struct edid *drm_get_edid(struct drm_connector *connector, |
| // struct i2c_adapter *adapter); |
| //extern int drm_do_probe_ddc_edid(struct i2c_adapter *adapter, |
| // unsigned char *buf, int len); |
| //extern int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid); |
| extern void drm_mode_probed_add(struct drm_connector *connector, struct drm_display_mode *mode); |
| extern void drm_mode_remove(struct drm_connector *connector, struct drm_display_mode *mode); |
| extern struct drm_display_mode *drm_mode_duplicate(struct drm_device *dev, |
| struct drm_display_mode *mode); |
| extern void drm_mode_debug_printmodeline(struct drm_display_mode *mode); |
| extern void drm_mode_config_init(struct drm_device *dev); |
| extern void drm_mode_config_cleanup(struct drm_device *dev); |
| extern void drm_mode_set_name(struct drm_display_mode *mode); |
| extern bool drm_mode_equal(struct drm_display_mode *mode1, struct drm_display_mode *mode2); |
| extern int drm_mode_width(struct drm_display_mode *mode); |
| extern int drm_mode_height(struct drm_display_mode *mode); |
| /* for us by fb module */ |
| extern int drm_mode_attachmode_crtc(struct drm_device *dev, |
| struct drm_crtc *crtc, |
| struct drm_display_mode *mode); |
| extern int drm_mode_detachmode_crtc(struct drm_device *dev, struct drm_display_mode *mode); |
| extern struct drm_display_mode *drm_mode_create(struct drm_device *dev); |
| extern void drm_mode_destroy(struct drm_device *dev, struct drm_display_mode *mode); |
| //extern void drm_mode_list_concat(struct list_head *head, |
| // struct list_head *new); |
| //extern void drm_mode_validate_size(struct drm_device *dev, |
| // struct list_head *mode_list, |
| // int maxX, int maxY, int maxPitch); |
| //extern void drm_mode_prune_invalid(struct drm_device *dev, |
| // struct list_head *mode_list, bool verbose); |
| //extern void drm_mode_sort(struct list_head *mode_list); |
| extern int drm_mode_vrefresh(struct drm_display_mode *mode); |
| extern void drm_mode_set_crtcinfo(struct drm_display_mode *p, |
| int adjust_flags); |
| extern void drm_mode_connector_list_update(struct drm_connector *connector); |
| //extern int drm_mode_connector_update_edid_property(struct drm_connector *connector, |
| // struct edid *edid); |
| extern int drm_connector_property_set_value(struct drm_connector *connector, |
| struct drm_property *property, |
| uint64_t value); |
| extern int drm_connector_property_get_value(struct drm_connector *connector, |
| struct drm_property *property, |
| uint64_t *value); |
| extern struct drm_display_mode *drm_crtc_mode_create(struct drm_device *dev); |
| extern void drm_framebuffer_set_object(struct drm_device *dev, |
| unsigned long handle); |
| extern int drm_framebuffer_init(struct drm_device *dev, |
| struct drm_framebuffer *fb, |
| const struct drm_framebuffer_funcs *funcs); |
| extern void drm_framebuffer_cleanup(struct drm_framebuffer *fb); |
| extern int drmfb_probe(struct drm_device *dev, struct drm_crtc *crtc); |
| extern int drmfb_remove(struct drm_device *dev, struct drm_framebuffer *fb); |
| extern void drm_crtc_probe_connector_modes(struct drm_device *dev, int maxX, int maxY); |
| extern bool drm_crtc_in_use(struct drm_crtc *crtc); |
| extern int drm_connector_attach_property(struct drm_connector *connector, |
| struct drm_property *property, uint64_t init_val); |
| extern struct drm_property *drm_property_create(struct drm_device *dev, int flags, |
| const char *name, int num_values); |
| extern void drm_property_destroy(struct drm_device *dev, struct drm_property *property); |
| extern int drm_property_add_enum(struct drm_property *property, int index, |
| uint64_t value, const char *name); |
| extern int drm_mode_create_dvi_i_properties(struct drm_device *dev); |
| extern int drm_mode_create_tv_properties(struct drm_device *dev, int num_formats, |
| char *formats[]); |
| extern int drm_mode_create_scaling_mode_property(struct drm_device *dev); |
| extern int drm_mode_create_dithering_property(struct drm_device *dev); |
| extern char *drm_get_encoder_name(struct drm_encoder *encoder); |
| extern int drm_mode_connector_attach_encoder(struct drm_connector *connector, |
| struct drm_encoder *encoder); |
| extern void drm_mode_connector_detach_encoder(struct drm_connector *connector, |
| struct drm_encoder *encoder); |
| extern bool drm_mode_crtc_set_gamma_size(struct drm_crtc *crtc, |
| int gamma_size); |
| extern void *drm_mode_object_find(struct drm_device *dev, uint32_t id, uint32_t type); |
| /* IOCTLs */ |
| extern int drm_mode_getresources(struct drm_device *dev, |
| void *data, struct drm_file *file_priv); |
| extern int drm_mode_getcrtc(struct drm_device *dev, |
| void *data, struct drm_file *file_priv); |
| extern int drm_mode_getconnector(struct drm_device *dev, |
| void *data, struct drm_file *file_priv); |
| extern int drm_mode_setcrtc(struct drm_device *dev, |
| void *data, struct drm_file *file_priv); |
| extern int drm_mode_cursor_ioctl(struct drm_device *dev, |
| void *data, struct drm_file *file_priv); |
| extern int drm_mode_addfb(struct drm_device *dev, |
| void *data, struct drm_file *file_priv); |
| extern int drm_mode_rmfb(struct drm_device *dev, |
| void *data, struct drm_file *file_priv); |
| extern int drm_mode_getfb(struct drm_device *dev, |
| void *data, struct drm_file *file_priv); |
| extern int drm_mode_addmode_ioctl(struct drm_device *dev, |
| void *data, struct drm_file *file_priv); |
| extern int drm_mode_rmmode_ioctl(struct drm_device *dev, |
| void *data, struct drm_file *file_priv); |
| extern int drm_mode_attachmode_ioctl(struct drm_device *dev, |
| void *data, struct drm_file *file_priv); |
| extern int drm_mode_detachmode_ioctl(struct drm_device *dev, |
| void *data, struct drm_file *file_priv); |
| extern int drm_mode_getproperty_ioctl(struct drm_device *dev, |
| void *data, struct drm_file *file_priv); |
| extern int drm_mode_getblob_ioctl(struct drm_device *dev, |
| void *data, struct drm_file *file_priv); |
| extern int drm_mode_connector_property_set_ioctl(struct drm_device *dev, |
| void *data, struct drm_file *file_priv); |
| extern int drm_mode_hotplug_ioctl(struct drm_device *dev, |
| void *data, struct drm_file *file_priv); |
| extern int drm_mode_replacefb(struct drm_device *dev, |
| void *data, struct drm_file *file_priv); |
| extern int drm_mode_getencoder(struct drm_device *dev, |
| void *data, struct drm_file *file_priv); |
| extern int drm_mode_gamma_get_ioctl(struct drm_device *dev, |
| void *data, struct drm_file *file_priv); |
| extern int drm_mode_gamma_set_ioctl(struct drm_device *dev, |
| void *data, struct drm_file *file_priv); |
| //extern bool drm_detect_hdmi_monitor(struct edid *edid); |
| #endif /* __DRM_CRTC_H__ */ |
| /drivers/video/drm/include/drm_mode.h |
|---|
| 0,0 → 1,268 |
| /* |
| * Copyright (c) 2007 Dave Airlie <airlied@linux.ie> |
| * Copyright (c) 2007 Jakob Bornecrantz <wallbraker@gmail.com> |
| * Copyright (c) 2008 Red Hat Inc. |
| * Copyright (c) 2007-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA |
| * Copyright (c) 2007-2008 Intel Corporation |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice shall be included in |
| * all copies or substantial portions of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
| * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| * IN THE SOFTWARE. |
| */ |
| #ifndef _DRM_MODE_H |
| #define _DRM_MODE_H |
| //#include <linux/kernel.h> |
| //#include <linux/types.h> |
| #define DRM_DISPLAY_INFO_LEN 32 |
| #define DRM_CONNECTOR_NAME_LEN 32 |
| #define DRM_DISPLAY_MODE_LEN 32 |
| #define DRM_PROP_NAME_LEN 32 |
| #define DRM_MODE_TYPE_BUILTIN (1<<0) |
| #define DRM_MODE_TYPE_CLOCK_C ((1<<1) | DRM_MODE_TYPE_BUILTIN) |
| #define DRM_MODE_TYPE_CRTC_C ((1<<2) | DRM_MODE_TYPE_BUILTIN) |
| #define DRM_MODE_TYPE_PREFERRED (1<<3) |
| #define DRM_MODE_TYPE_DEFAULT (1<<4) |
| #define DRM_MODE_TYPE_USERDEF (1<<5) |
| #define DRM_MODE_TYPE_DRIVER (1<<6) |
| /* Video mode flags */ |
| /* bit compatible with the xorg definitions. */ |
| #define DRM_MODE_FLAG_PHSYNC (1<<0) |
| #define DRM_MODE_FLAG_NHSYNC (1<<1) |
| #define DRM_MODE_FLAG_PVSYNC (1<<2) |
| #define DRM_MODE_FLAG_NVSYNC (1<<3) |
| #define DRM_MODE_FLAG_INTERLACE (1<<4) |
| #define DRM_MODE_FLAG_DBLSCAN (1<<5) |
| #define DRM_MODE_FLAG_CSYNC (1<<6) |
| #define DRM_MODE_FLAG_PCSYNC (1<<7) |
| #define DRM_MODE_FLAG_NCSYNC (1<<8) |
| #define DRM_MODE_FLAG_HSKEW (1<<9) /* hskew provided */ |
| #define DRM_MODE_FLAG_BCAST (1<<10) |
| #define DRM_MODE_FLAG_PIXMUX (1<<11) |
| #define DRM_MODE_FLAG_DBLCLK (1<<12) |
| #define DRM_MODE_FLAG_CLKDIV2 (1<<13) |
| /* DPMS flags */ |
| /* bit compatible with the xorg definitions. */ |
| #define DRM_MODE_DPMS_ON 0 |
| #define DRM_MODE_DPMS_STANDBY 1 |
| #define DRM_MODE_DPMS_SUSPEND 2 |
| #define DRM_MODE_DPMS_OFF 3 |
| /* Scaling mode options */ |
| #define DRM_MODE_SCALE_NON_GPU 0 |
| #define DRM_MODE_SCALE_FULLSCREEN 1 |
| #define DRM_MODE_SCALE_NO_SCALE 2 |
| #define DRM_MODE_SCALE_ASPECT 3 |
| /* Dithering mode options */ |
| #define DRM_MODE_DITHERING_OFF 0 |
| #define DRM_MODE_DITHERING_ON 1 |
| struct drm_mode_modeinfo { |
| __u32 clock; |
| __u16 hdisplay, hsync_start, hsync_end, htotal, hskew; |
| __u16 vdisplay, vsync_start, vsync_end, vtotal, vscan; |
| __u32 vrefresh; /* vertical refresh * 1000 */ |
| __u32 flags; |
| __u32 type; |
| char name[DRM_DISPLAY_MODE_LEN]; |
| }; |
| struct drm_mode_card_res { |
| __u64 fb_id_ptr; |
| __u64 crtc_id_ptr; |
| __u64 connector_id_ptr; |
| __u64 encoder_id_ptr; |
| __u32 count_fbs; |
| __u32 count_crtcs; |
| __u32 count_connectors; |
| __u32 count_encoders; |
| __u32 min_width, max_width; |
| __u32 min_height, max_height; |
| }; |
| struct drm_mode_crtc { |
| __u64 set_connectors_ptr; |
| __u32 count_connectors; |
| __u32 crtc_id; /**< Id */ |
| __u32 fb_id; /**< Id of framebuffer */ |
| __u32 x, y; /**< Position on the frameuffer */ |
| __u32 gamma_size; |
| __u32 mode_valid; |
| struct drm_mode_modeinfo mode; |
| }; |
| #define DRM_MODE_ENCODER_NONE 0 |
| #define DRM_MODE_ENCODER_DAC 1 |
| #define DRM_MODE_ENCODER_TMDS 2 |
| #define DRM_MODE_ENCODER_LVDS 3 |
| #define DRM_MODE_ENCODER_TVDAC 4 |
| struct drm_mode_get_encoder { |
| __u32 encoder_id; |
| __u32 encoder_type; |
| __u32 crtc_id; /**< Id of crtc */ |
| __u32 possible_crtcs; |
| __u32 possible_clones; |
| }; |
| /* This is for connectors with multiple signal types. */ |
| /* Try to match DRM_MODE_CONNECTOR_X as closely as possible. */ |
| #define DRM_MODE_SUBCONNECTOR_Automatic 0 |
| #define DRM_MODE_SUBCONNECTOR_Unknown 0 |
| #define DRM_MODE_SUBCONNECTOR_DVID 3 |
| #define DRM_MODE_SUBCONNECTOR_DVIA 4 |
| #define DRM_MODE_SUBCONNECTOR_Composite 5 |
| #define DRM_MODE_SUBCONNECTOR_SVIDEO 6 |
| #define DRM_MODE_SUBCONNECTOR_Component 8 |
| #define DRM_MODE_CONNECTOR_Unknown 0 |
| #define DRM_MODE_CONNECTOR_VGA 1 |
| #define DRM_MODE_CONNECTOR_DVII 2 |
| #define DRM_MODE_CONNECTOR_DVID 3 |
| #define DRM_MODE_CONNECTOR_DVIA 4 |
| #define DRM_MODE_CONNECTOR_Composite 5 |
| #define DRM_MODE_CONNECTOR_SVIDEO 6 |
| #define DRM_MODE_CONNECTOR_LVDS 7 |
| #define DRM_MODE_CONNECTOR_Component 8 |
| #define DRM_MODE_CONNECTOR_9PinDIN 9 |
| #define DRM_MODE_CONNECTOR_DisplayPort 10 |
| #define DRM_MODE_CONNECTOR_HDMIA 11 |
| #define DRM_MODE_CONNECTOR_HDMIB 12 |
| struct drm_mode_get_connector { |
| __u64 encoders_ptr; |
| __u64 modes_ptr; |
| __u64 props_ptr; |
| __u64 prop_values_ptr; |
| __u32 count_modes; |
| __u32 count_props; |
| __u32 count_encoders; |
| __u32 encoder_id; /**< Current Encoder */ |
| __u32 connector_id; /**< Id */ |
| __u32 connector_type; |
| __u32 connector_type_id; |
| __u32 connection; |
| __u32 mm_width, mm_height; /**< HxW in millimeters */ |
| __u32 subpixel; |
| }; |
| #define DRM_MODE_PROP_PENDING (1<<0) |
| #define DRM_MODE_PROP_RANGE (1<<1) |
| #define DRM_MODE_PROP_IMMUTABLE (1<<2) |
| #define DRM_MODE_PROP_ENUM (1<<3) /* enumerated type with text strings */ |
| #define DRM_MODE_PROP_BLOB (1<<4) |
| struct drm_mode_property_enum { |
| __u64 value; |
| char name[DRM_PROP_NAME_LEN]; |
| }; |
| struct drm_mode_get_property { |
| __u64 values_ptr; /* values and blob lengths */ |
| __u64 enum_blob_ptr; /* enum and blob id ptrs */ |
| __u32 prop_id; |
| __u32 flags; |
| char name[DRM_PROP_NAME_LEN]; |
| __u32 count_values; |
| __u32 count_enum_blobs; |
| }; |
| struct drm_mode_connector_set_property { |
| __u64 value; |
| __u32 prop_id; |
| __u32 connector_id; |
| }; |
| struct drm_mode_get_blob { |
| __u32 blob_id; |
| __u32 length; |
| __u64 data; |
| }; |
| struct drm_mode_fb_cmd { |
| __u32 fb_id; |
| __u32 width, height; |
| __u32 pitch; |
| __u32 bpp; |
| __u32 depth; |
| /* driver specific handle */ |
| __u32 handle; |
| }; |
| struct drm_mode_mode_cmd { |
| __u32 connector_id; |
| struct drm_mode_modeinfo mode; |
| }; |
| #define DRM_MODE_CURSOR_BO (1<<0) |
| #define DRM_MODE_CURSOR_MOVE (1<<1) |
| /* |
| * depending on the value in flags diffrent members are used. |
| * |
| * CURSOR_BO uses |
| * crtc |
| * width |
| * height |
| * handle - if 0 turns the cursor of |
| * |
| * CURSOR_MOVE uses |
| * crtc |
| * x |
| * y |
| */ |
| struct drm_mode_cursor { |
| __u32 flags; |
| __u32 crtc_id; |
| __s32 x; |
| __s32 y; |
| __u32 width; |
| __u32 height; |
| /* driver specific handle */ |
| __u32 handle; |
| }; |
| struct drm_mode_crtc_lut { |
| __u32 crtc_id; |
| __u32 gamma_size; |
| /* pointers to arrays */ |
| __u64 red; |
| __u64 green; |
| __u64 blue; |
| }; |
| #endif |
| /drivers/video/drm/include/errno-base.h |
|---|
| 0,0 → 1,39 |
| #ifndef _ASM_GENERIC_ERRNO_BASE_H |
| #define _ASM_GENERIC_ERRNO_BASE_H |
| #define EPERM 1 /* Operation not permitted */ |
| #define ENOENT 2 /* No such file or directory */ |
| #define ESRCH 3 /* No such process */ |
| #define EINTR 4 /* Interrupted system call */ |
| #define EIO 5 /* I/O error */ |
| #define ENXIO 6 /* No such device or address */ |
| #define E2BIG 7 /* Argument list too long */ |
| #define ENOEXEC 8 /* Exec format error */ |
| #define EBADF 9 /* Bad file number */ |
| #define ECHILD 10 /* No child processes */ |
| #define EAGAIN 11 /* Try again */ |
| #define ENOMEM 12 /* Out of memory */ |
| #define EACCES 13 /* Permission denied */ |
| #define EFAULT 14 /* Bad address */ |
| #define ENOTBLK 15 /* Block device required */ |
| #define EBUSY 16 /* Device or resource busy */ |
| #define EEXIST 17 /* File exists */ |
| #define EXDEV 18 /* Cross-device link */ |
| #define ENODEV 19 /* No such device */ |
| #define ENOTDIR 20 /* Not a directory */ |
| #define EISDIR 21 /* Is a directory */ |
| #define EINVAL 22 /* Invalid argument */ |
| #define ENFILE 23 /* File table overflow */ |
| #define EMFILE 24 /* Too many open files */ |
| #define ENOTTY 25 /* Not a typewriter */ |
| #define ETXTBSY 26 /* Text file busy */ |
| #define EFBIG 27 /* File too large */ |
| #define ENOSPC 28 /* No space left on device */ |
| #define ESPIPE 29 /* Illegal seek */ |
| #define EROFS 30 /* Read-only file system */ |
| #define EMLINK 31 /* Too many links */ |
| #define EPIPE 32 /* Broken pipe */ |
| #define EDOM 33 /* Math argument out of domain of func */ |
| #define ERANGE 34 /* Math result not representable */ |
| #endif |
| /drivers/video/drm/include/pci.h |
|---|
| 0,0 → 1,562 |
| #include <types.h> |
| #include <link.h> |
| #ifndef __PCI_H__ |
| #define __PCI_H__ |
| #define PCI_ANY_ID (~0) |
| #define PCI_CLASS_NOT_DEFINED 0x0000 |
| #define PCI_CLASS_NOT_DEFINED_VGA 0x0001 |
| #define PCI_BASE_CLASS_STORAGE 0x01 |
| #define PCI_CLASS_STORAGE_SCSI 0x0100 |
| #define PCI_CLASS_STORAGE_IDE 0x0101 |
| #define PCI_CLASS_STORAGE_FLOPPY 0x0102 |
| #define PCI_CLASS_STORAGE_IPI 0x0103 |
| #define PCI_CLASS_STORAGE_RAID 0x0104 |
| #define PCI_CLASS_STORAGE_SATA 0x0106 |
| #define PCI_CLASS_STORAGE_SATA_AHCI 0x010601 |
| #define PCI_CLASS_STORAGE_SAS 0x0107 |
| #define PCI_CLASS_STORAGE_OTHER 0x0180 |
| #define PCI_BASE_CLASS_NETWORK 0x02 |
| #define PCI_CLASS_NETWORK_ETHERNET 0x0200 |
| #define PCI_CLASS_NETWORK_TOKEN_RING 0x0201 |
| #define PCI_CLASS_NETWORK_FDDI 0x0202 |
| #define PCI_CLASS_NETWORK_ATM 0x0203 |
| #define PCI_CLASS_NETWORK_OTHER 0x0280 |
| #define PCI_BASE_CLASS_DISPLAY 0x03 |
| #define PCI_CLASS_DISPLAY_VGA 0x0300 |
| #define PCI_CLASS_DISPLAY_XGA 0x0301 |
| #define PCI_CLASS_DISPLAY_3D 0x0302 |
| #define PCI_CLASS_DISPLAY_OTHER 0x0380 |
| #define PCI_BASE_CLASS_MULTIMEDIA 0x04 |
| #define PCI_CLASS_MULTIMEDIA_VIDEO 0x0400 |
| #define PCI_CLASS_MULTIMEDIA_AUDIO 0x0401 |
| #define PCI_CLASS_MULTIMEDIA_PHONE 0x0402 |
| #define PCI_CLASS_MULTIMEDIA_OTHER 0x0480 |
| #define PCI_BASE_CLASS_MEMORY 0x05 |
| #define PCI_CLASS_MEMORY_RAM 0x0500 |
| #define PCI_CLASS_MEMORY_FLASH 0x0501 |
| #define PCI_CLASS_MEMORY_OTHER 0x0580 |
| #define PCI_BASE_CLASS_BRIDGE 0x06 |
| #define PCI_CLASS_BRIDGE_HOST 0x0600 |
| #define PCI_CLASS_BRIDGE_ISA 0x0601 |
| #define PCI_CLASS_BRIDGE_EISA 0x0602 |
| #define PCI_CLASS_BRIDGE_MC 0x0603 |
| #define PCI_CLASS_BRIDGE_PCI 0x0604 |
| #define PCI_CLASS_BRIDGE_PCMCIA 0x0605 |
| #define PCI_CLASS_BRIDGE_NUBUS 0x0606 |
| #define PCI_CLASS_BRIDGE_CARDBUS 0x0607 |
| #define PCI_CLASS_BRIDGE_RACEWAY 0x0608 |
| #define PCI_CLASS_BRIDGE_OTHER 0x0680 |
| #define PCI_BASE_CLASS_COMMUNICATION 0x07 |
| #define PCI_CLASS_COMMUNICATION_SERIAL 0x0700 |
| #define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701 |
| #define PCI_CLASS_COMMUNICATION_MULTISERIAL 0x0702 |
| #define PCI_CLASS_COMMUNICATION_MODEM 0x0703 |
| #define PCI_CLASS_COMMUNICATION_OTHER 0x0780 |
| #define PCI_BASE_CLASS_SYSTEM 0x08 |
| #define PCI_CLASS_SYSTEM_PIC 0x0800 |
| #define PCI_CLASS_SYSTEM_PIC_IOAPIC 0x080010 |
| #define PCI_CLASS_SYSTEM_PIC_IOXAPIC 0x080020 |
| #define PCI_CLASS_SYSTEM_DMA 0x0801 |
| #define PCI_CLASS_SYSTEM_TIMER 0x0802 |
| #define PCI_CLASS_SYSTEM_RTC 0x0803 |
| #define PCI_CLASS_SYSTEM_PCI_HOTPLUG 0x0804 |
| #define PCI_CLASS_SYSTEM_SDHCI 0x0805 |
| #define PCI_CLASS_SYSTEM_OTHER 0x0880 |
| #define PCI_BASE_CLASS_INPUT 0x09 |
| #define PCI_CLASS_INPUT_KEYBOARD 0x0900 |
| #define PCI_CLASS_INPUT_PEN 0x0901 |
| #define PCI_CLASS_INPUT_MOUSE 0x0902 |
| #define PCI_CLASS_INPUT_SCANNER 0x0903 |
| #define PCI_CLASS_INPUT_GAMEPORT 0x0904 |
| #define PCI_CLASS_INPUT_OTHER 0x0980 |
| #define PCI_BASE_CLASS_DOCKING 0x0a |
| #define PCI_CLASS_DOCKING_GENERIC 0x0a00 |
| #define PCI_CLASS_DOCKING_OTHER 0x0a80 |
| #define PCI_BASE_CLASS_PROCESSOR 0x0b |
| #define PCI_CLASS_PROCESSOR_386 0x0b00 |
| #define PCI_CLASS_PROCESSOR_486 0x0b01 |
| #define PCI_CLASS_PROCESSOR_PENTIUM 0x0b02 |
| #define PCI_CLASS_PROCESSOR_ALPHA 0x0b10 |
| #define PCI_CLASS_PROCESSOR_POWERPC 0x0b20 |
| #define PCI_CLASS_PROCESSOR_MIPS 0x0b30 |
| #define PCI_CLASS_PROCESSOR_CO 0x0b40 |
| #define PCI_BASE_CLASS_SERIAL 0x0c |
| #define PCI_CLASS_SERIAL_FIREWIRE 0x0c00 |
| #define PCI_CLASS_SERIAL_FIREWIRE_OHCI 0x0c0010 |
| #define PCI_CLASS_SERIAL_ACCESS 0x0c01 |
| #define PCI_CLASS_SERIAL_SSA 0x0c02 |
| #define PCI_CLASS_SERIAL_USB 0x0c03 |
| #define PCI_CLASS_SERIAL_USB_UHCI 0x0c0300 |
| #define PCI_CLASS_SERIAL_USB_OHCI 0x0c0310 |
| #define PCI_CLASS_SERIAL_USB_EHCI 0x0c0320 |
| #define PCI_CLASS_SERIAL_FIBER 0x0c04 |
| #define PCI_CLASS_SERIAL_SMBUS 0x0c05 |
| #define PCI_BASE_CLASS_WIRELESS 0x0d |
| #define PCI_CLASS_WIRELESS_RF_CONTROLLER 0x0d10 |
| #define PCI_CLASS_WIRELESS_WHCI 0x0d1010 |
| #define PCI_BASE_CLASS_INTELLIGENT 0x0e |
| #define PCI_CLASS_INTELLIGENT_I2O 0x0e00 |
| #define PCI_BASE_CLASS_SATELLITE 0x0f |
| #define PCI_CLASS_SATELLITE_TV 0x0f00 |
| #define PCI_CLASS_SATELLITE_AUDIO 0x0f01 |
| #define PCI_CLASS_SATELLITE_VOICE 0x0f03 |
| #define PCI_CLASS_SATELLITE_DATA 0x0f04 |
| #define PCI_BASE_CLASS_CRYPT 0x10 |
| #define PCI_CLASS_CRYPT_NETWORK 0x1000 |
| #define PCI_CLASS_CRYPT_ENTERTAINMENT 0x1001 |
| #define PCI_CLASS_CRYPT_OTHER 0x1080 |
| #define PCI_BASE_CLASS_SIGNAL_PROCESSING 0x11 |
| #define PCI_CLASS_SP_DPIO 0x1100 |
| #define PCI_CLASS_SP_OTHER 0x1180 |
| #define PCI_CLASS_OTHERS 0xff |
| /* |
| * Under PCI, each device has 256 bytes of configuration address space, |
| * of which the first 64 bytes are standardized as follows: |
| */ |
| #define PCI_VENDOR_ID 0x000 /* 16 bits */ |
| #define PCI_DEVICE_ID 0x002 /* 16 bits */ |
| #define PCI_COMMAND 0x004 /* 16 bits */ |
| #define PCI_COMMAND_IO 0x001 /* Enable response in I/O space */ |
| #define PCI_COMMAND_MEMORY 0x002 /* Enable response in Memory space */ |
| #define PCI_COMMAND_MASTER 0x004 /* Enable bus mastering */ |
| #define PCI_COMMAND_SPECIAL 0x008 /* Enable response to special cycles */ |
| #define PCI_COMMAND_INVALIDATE 0x010 /* Use memory write and invalidate */ |
| #define PCI_COMMAND_VGA_PALETTE 0x020 /* Enable palette snooping */ |
| #define PCI_COMMAND_PARITY 0x040 /* Enable parity checking */ |
| #define PCI_COMMAND_WAIT 0x080 /* Enable address/data stepping */ |
| #define PCI_COMMAND_SERR 0x100 /* Enable SERR */ |
| #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */ |
| #define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */ |
| #define PCI_STATUS 0x006 /* 16 bits */ |
| #define PCI_STATUS_CAP_LIST 0x010 /* Support Capability List */ |
| #define PCI_STATUS_66MHZ 0x020 /* Support 66 Mhz PCI 2.1 bus */ |
| #define PCI_STATUS_UDF 0x040 /* Support User Definable Features [obsolete] */ |
| #define PCI_STATUS_FAST_BACK 0x080 /* Accept fast-back to back */ |
| #define PCI_STATUS_PARITY 0x100 /* Detected parity error */ |
| #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */ |
| #define PCI_STATUS_DEVSEL_FAST 0x000 |
| #define PCI_STATUS_DEVSEL_MEDIUM 0x200 |
| #define PCI_STATUS_DEVSEL_SLOW 0x400 |
| #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */ |
| #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */ |
| #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */ |
| #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */ |
| #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */ |
| #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 revision */ |
| #define PCI_REVISION_ID 0x08 /* Revision ID */ |
| #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ |
| #define PCI_CLASS_DEVICE 0x0a /* Device class */ |
| #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ |
| #define PCI_LATENCY_TIMER 0x0d /* 8 bits */ |
| #define PCI_HEADER_TYPE 0x0e /* 8 bits */ |
| #define PCI_HEADER_TYPE_NORMAL 0 |
| #define PCI_HEADER_TYPE_BRIDGE 1 |
| #define PCI_HEADER_TYPE_CARDBUS 2 |
| #define PCI_BIST 0x0f /* 8 bits */ |
| #define PCI_BIST_CODE_MASK 0x0f /* Return result */ |
| #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ |
| #define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */ |
| /* |
| * Base addresses specify locations in memory or I/O space. |
| * Decoded size can be determined by writing a value of |
| * 0xffffffff to the register, and reading it back. Only |
| * 1 bits are decoded. |
| */ |
| #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */ |
| #define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */ |
| #define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */ |
| #define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */ |
| #define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */ |
| #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */ |
| #define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */ |
| #define PCI_BASE_ADDRESS_SPACE_IO 0x01 |
| #define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 |
| #define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06 |
| #define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */ |
| #define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */ |
| #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */ |
| #define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */ |
| #define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL) |
| #define PCI_BASE_ADDRESS_IO_MASK (~0x03UL) |
| /* bit 1 is reserved if address_space = 1 */ |
| #define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */ |
| /* Header type 0 (normal devices) */ |
| #define PCI_CARDBUS_CIS 0x28 |
| #define PCI_SUBSYSTEM_VENDOR_ID 0x2c |
| #define PCI_SUBSYSTEM_ID 0x2e |
| #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */ |
| #define PCI_ROM_ADDRESS_ENABLE 0x01 |
| #define PCI_ROM_ADDRESS_MASK (~0x7ffUL) |
| #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ |
| #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ |
| #define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40 |
| #define PCI_CB_SUBSYSTEM_ID 0x42 |
| #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */ |
| #define PCI_CB_CAPABILITY_LIST 0x14 |
| /* Capability lists */ |
| #define PCI_CAP_LIST_ID 0 /* Capability ID */ |
| #define PCI_CAP_ID_PM 0x01 /* Power Management */ |
| #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */ |
| #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */ |
| #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */ |
| #define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */ |
| #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ |
| #define PCI_CAP_ID_PCIX 0x07 /* PCI-X */ |
| #define PCI_CAP_ID_HT 0x08 /* HyperTransport */ |
| #define PCI_CAP_ID_VNDR 0x09 /* Vendor specific capability */ |
| #define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */ |
| #define PCI_CAP_ID_EXP 0x10 /* PCI Express */ |
| #define PCI_CAP_ID_MSIX 0x11 /* MSI-X */ |
| #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ |
| #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */ |
| #define PCI_CAP_SIZEOF 4 |
| /* AGP registers */ |
| #define PCI_AGP_VERSION 2 /* BCD version number */ |
| #define PCI_AGP_RFU 3 /* Rest of capability flags */ |
| #define PCI_AGP_STATUS 4 /* Status register */ |
| #define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */ |
| #define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */ |
| #define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */ |
| #define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */ |
| #define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */ |
| #define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */ |
| #define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */ |
| #define PCI_AGP_COMMAND 8 /* Control register */ |
| #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */ |
| #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */ |
| #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */ |
| #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */ |
| #define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */ |
| #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */ |
| #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate */ |
| #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate */ |
| #define PCI_AGP_SIZEOF 12 |
| #define PCI_MAP_REG_START 0x10 |
| #define PCI_MAP_REG_END 0x28 |
| #define PCI_MAP_ROM_REG 0x30 |
| #define PCI_MAP_MEMORY 0x00000000 |
| #define PCI_MAP_IO 0x00000001 |
| #define PCI_MAP_MEMORY_TYPE 0x00000007 |
| #define PCI_MAP_IO_TYPE 0x00000003 |
| #define PCI_MAP_MEMORY_TYPE_32BIT 0x00000000 |
| #define PCI_MAP_MEMORY_TYPE_32BIT_1M 0x00000002 |
| #define PCI_MAP_MEMORY_TYPE_64BIT 0x00000004 |
| #define PCI_MAP_MEMORY_TYPE_MASK 0x00000006 |
| #define PCI_MAP_MEMORY_CACHABLE 0x00000008 |
| #define PCI_MAP_MEMORY_ATTR_MASK 0x0000000e |
| #define PCI_MAP_MEMORY_ADDRESS_MASK 0xfffffff0 |
| #define PCI_MAP_IO_ATTR_MASK 0x00000003 |
| #define PCI_MAP_IS_IO(b) ((b) & PCI_MAP_IO) |
| #define PCI_MAP_IS_MEM(b) (!PCI_MAP_IS_IO(b)) |
| #define PCI_MAP_IS64BITMEM(b) \ |
| (((b) & PCI_MAP_MEMORY_TYPE_MASK) == PCI_MAP_MEMORY_TYPE_64BIT) |
| #define PCIGETMEMORY(b) ((b) & PCI_MAP_MEMORY_ADDRESS_MASK) |
| #define PCIGETMEMORY64HIGH(b) (*((CARD32*)&b + 1)) |
| #define PCIGETMEMORY64(b) \ |
| (PCIGETMEMORY(b) | ((CARD64)PCIGETMEMORY64HIGH(b) << 32)) |
| #define PCI_MAP_IO_ADDRESS_MASK 0xfffffffc |
| #define PCIGETIO(b) ((b) & PCI_MAP_IO_ADDRESS_MASK) |
| #define PCI_MAP_ROM_DECODE_ENABLE 0x00000001 |
| #define PCI_MAP_ROM_ADDRESS_MASK 0xfffff800 |
| #define PCIGETROM(b) ((b) & PCI_MAP_ROM_ADDRESS_MASK) |
| #ifndef PCI_DOM_MASK |
| # define PCI_DOM_MASK 0x0ffu |
| #endif |
| #define PCI_DOMBUS_MASK (((PCI_DOM_MASK) << 8) | 0x0ffu) |
| #define PCI_MAKE_TAG(b,d,f) ((((b) & (PCI_DOMBUS_MASK)) << 16) | \ |
| (((d) & 0x00001fu) << 11) | \ |
| (((f) & 0x000007u) << 8)) |
| #define PCI_BUS_FROM_TAG(tag) (((tag) >> 16) & (PCI_DOMBUS_MASK)) |
| #define PCI_DEV_FROM_TAG(tag) (((tag) & 0x0000f800u) >> 11) |
| #define PCI_FUNC_FROM_TAG(tag) (((tag) & 0x00000700u) >> 8) |
| #define PCI_DFN_FROM_TAG(tag) (((tag) & 0x0000ff00u) >> 8) |
| #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) |
| #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) |
| #define PCI_FUNC(devfn) ((devfn) & 0x07) |
| typedef unsigned int PCITAG; |
| extern inline PCITAG |
| pciTag(int busnum, int devnum, int funcnum) |
| { |
| return(PCI_MAKE_TAG(busnum,devnum,funcnum)); |
| } |
| struct resource |
| { |
| resource_size_t start; |
| resource_size_t end; |
| // const char *name; |
| unsigned long flags; |
| // struct resource *parent, *sibling, *child; |
| }; |
| /* |
| * IO resources have these defined flags. |
| */ |
| #define IORESOURCE_BITS 0x000000ff /* Bus-specific bits */ |
| #define IORESOURCE_IO 0x00000100 /* Resource type */ |
| #define IORESOURCE_MEM 0x00000200 |
| #define IORESOURCE_IRQ 0x00000400 |
| #define IORESOURCE_DMA 0x00000800 |
| #define IORESOURCE_PREFETCH 0x00001000 /* No side effects */ |
| #define IORESOURCE_READONLY 0x00002000 |
| #define IORESOURCE_CACHEABLE 0x00004000 |
| #define IORESOURCE_RANGELENGTH 0x00008000 |
| #define IORESOURCE_SHADOWABLE 0x00010000 |
| #define IORESOURCE_BUS_HAS_VGA 0x00080000 |
| #define IORESOURCE_DISABLED 0x10000000 |
| #define IORESOURCE_UNSET 0x20000000 |
| #define IORESOURCE_AUTO 0x40000000 |
| #define IORESOURCE_BUSY 0x80000000 /* Driver has marked this resource busy */ |
| /* ISA PnP IRQ specific bits (IORESOURCE_BITS) */ |
| #define IORESOURCE_IRQ_HIGHEDGE (1<<0) |
| #define IORESOURCE_IRQ_LOWEDGE (1<<1) |
| #define IORESOURCE_IRQ_HIGHLEVEL (1<<2) |
| #define IORESOURCE_IRQ_LOWLEVEL (1<<3) |
| #define IORESOURCE_IRQ_SHAREABLE (1<<4) |
| /* ISA PnP DMA specific bits (IORESOURCE_BITS) */ |
| #define IORESOURCE_DMA_TYPE_MASK (3<<0) |
| #define IORESOURCE_DMA_8BIT (0<<0) |
| #define IORESOURCE_DMA_8AND16BIT (1<<0) |
| #define IORESOURCE_DMA_16BIT (2<<0) |
| #define IORESOURCE_DMA_MASTER (1<<2) |
| #define IORESOURCE_DMA_BYTE (1<<3) |
| #define IORESOURCE_DMA_WORD (1<<4) |
| #define IORESOURCE_DMA_SPEED_MASK (3<<6) |
| #define IORESOURCE_DMA_COMPATIBLE (0<<6) |
| #define IORESOURCE_DMA_TYPEA (1<<6) |
| #define IORESOURCE_DMA_TYPEB (2<<6) |
| #define IORESOURCE_DMA_TYPEF (3<<6) |
| /* ISA PnP memory I/O specific bits (IORESOURCE_BITS) */ |
| #define IORESOURCE_MEM_WRITEABLE (1<<0) /* dup: IORESOURCE_READONLY */ |
| #define IORESOURCE_MEM_CACHEABLE (1<<1) /* dup: IORESOURCE_CACHEABLE */ |
| #define IORESOURCE_MEM_RANGELENGTH (1<<2) /* dup: IORESOURCE_RANGELENGTH */ |
| #define IORESOURCE_MEM_TYPE_MASK (3<<3) |
| #define IORESOURCE_MEM_8BIT (0<<3) |
| #define IORESOURCE_MEM_16BIT (1<<3) |
| #define IORESOURCE_MEM_8AND16BIT (2<<3) |
| #define IORESOURCE_MEM_32BIT (3<<3) |
| #define IORESOURCE_MEM_SHADOWABLE (1<<5) /* dup: IORESOURCE_SHADOWABLE */ |
| #define IORESOURCE_MEM_EXPANSIONROM (1<<6) |
| /* PCI ROM control bits (IORESOURCE_BITS) */ |
| #define IORESOURCE_ROM_ENABLE (1<<0) /* ROM is enabled, same as PCI_ROM_ADDRESS_ENABLE */ |
| #define IORESOURCE_ROM_SHADOW (1<<1) /* ROM is copy at C000:0 */ |
| #define IORESOURCE_ROM_COPY (1<<2) /* ROM is alloc'd copy, resource field overlaid */ |
| #define IORESOURCE_ROM_BIOS_COPY (1<<3) /* ROM is BIOS copy, resource field overlaid */ |
| /* PCI control bits. Shares IORESOURCE_BITS with above PCI ROM. */ |
| #define IORESOURCE_PCI_FIXED (1<<4) /* Do not move resource */ |
| /* |
| * For PCI devices, the region numbers are assigned this way: |
| * |
| * 0-5 standard PCI regions |
| * 6 expansion ROM |
| * 7-10 bridges: address space assigned to buses behind the bridge |
| */ |
| #define PCI_ROM_RESOURCE 6 |
| #define PCI_BRIDGE_RESOURCES 7 |
| #define PCI_NUM_RESOURCES 11 |
| #ifndef PCI_BUS_NUM_RESOURCES |
| #define PCI_BUS_NUM_RESOURCES 8 |
| #endif |
| #define DEVICE_COUNT_RESOURCE 12 |
| /* |
| * The pci_dev structure is used to describe PCI devices. |
| */ |
| struct pci_dev { |
| // struct list_head bus_list; /* node in per-bus list */ |
| // struct pci_bus *bus; /* bus this device is on */ |
| // struct pci_bus *subordinate; /* bus this device bridges to */ |
| // void *sysdata; /* hook for sys-specific extension */ |
| // struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */ |
| // struct pci_slot *slot; /* Physical slot this device is in */ |
| u32_t bus; |
| u32_t devfn; /* encoded device & function index */ |
| u16_t vendor; |
| u16_t device; |
| u16_t subsystem_vendor; |
| u16_t subsystem_device; |
| u32_t class; /* 3 bytes: (base,sub,prog-if) */ |
| uint8_t revision; /* PCI revision, low byte of class word */ |
| uint8_t hdr_type; /* PCI header type (`multi' flag masked out) */ |
| uint8_t pcie_type; /* PCI-E device/port type */ |
| uint8_t rom_base_reg; /* which config register controls the ROM */ |
| uint8_t pin; /* which interrupt pin this device uses */ |
| // struct pci_driver *driver; /* which driver has allocated this device */ |
| uint64_t dma_mask; /* Mask of the bits of bus address this |
| device implements. Normally this is |
| 0xffffffff. You only need to change |
| this if your device has broken DMA |
| or supports 64-bit transfers. */ |
| // struct device_dma_parameters dma_parms; |
| // pci_power_t current_state; /* Current operating state. In ACPI-speak, |
| // this is D0-D3, D0 being fully functional, |
| // and D3 being off. */ |
| // int pm_cap; /* PM capability offset in the |
| // configuration space */ |
| unsigned int pme_support:5; /* Bitmask of states from which PME# |
| can be generated */ |
| unsigned int d1_support:1; /* Low power state D1 is supported */ |
| unsigned int d2_support:1; /* Low power state D2 is supported */ |
| unsigned int no_d1d2:1; /* Only allow D0 and D3 */ |
| // pci_channel_state_t error_state; /* current connectivity state */ |
| // struct device dev; /* Generic device interface */ |
| // int cfg_size; /* Size of configuration space */ |
| /* |
| * Instead of touching interrupt line and base address registers |
| * directly, use the values stored here. They might be different! |
| */ |
| unsigned int irq; |
| struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ |
| /* These fields are used by common fixups */ |
| unsigned int transparent:1; /* Transparent PCI bridge */ |
| unsigned int multifunction:1;/* Part of multi-function device */ |
| /* keep track of device state */ |
| unsigned int is_added:1; |
| unsigned int is_busmaster:1; /* device is busmaster */ |
| unsigned int no_msi:1; /* device may not use msi */ |
| unsigned int block_ucfg_access:1; /* userspace config space access is blocked */ |
| unsigned int broken_parity_status:1; /* Device generates false positive parity */ |
| unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */ |
| unsigned int msi_enabled:1; |
| unsigned int msix_enabled:1; |
| unsigned int ari_enabled:1; /* ARI forwarding */ |
| unsigned int is_managed:1; |
| unsigned int is_pcie:1; |
| unsigned int state_saved:1; |
| unsigned int is_physfn:1; |
| unsigned int is_virtfn:1; |
| // pci_dev_flags_t dev_flags; |
| // atomic_t enable_cnt; /* pci_enable_device has been called */ |
| // u32 saved_config_space[16]; /* config space saved at suspend time */ |
| // struct hlist_head saved_cap_space; |
| // struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */ |
| // int rom_attr_enabled; /* has display of the rom attribute been enabled? */ |
| // struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ |
| // struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ |
| }; |
| #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) |
| #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) |
| #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) |
| #define pci_resource_len(dev,bar) \ |
| ((pci_resource_start((dev), (bar)) == 0 && \ |
| pci_resource_end((dev), (bar)) == \ |
| pci_resource_start((dev), (bar))) ? 0 : \ |
| \ |
| (pci_resource_end((dev), (bar)) - \ |
| pci_resource_start((dev), (bar)) + 1)) |
| struct pci_device_id |
| { |
| u16_t vendor, device; /* Vendor and device ID or PCI_ANY_ID*/ |
| u16_t subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */ |
| u32_t class, class_mask; /* (class,subclass,prog-if) triplet */ |
| u32_t driver_data; /* Data private to the driver */ |
| }; |
| typedef struct |
| { |
| link_t link; |
| struct pci_dev pci_dev; |
| }dev_t; |
| int enum_pci_devices(void); |
| struct pci_device_id* |
| find_pci_device(dev_t* pdev, struct pci_device_id *idlist); |
| #define pci_name(x) "radeon" |
| #endif //__PCI__H__ |
| /drivers/video/drm/include/syscall.h |
|---|
| 0,0 → 1,351 |
| #ifndef __SYSCALL_H__ |
| #define __SYSCALL_H__ |
| #define OS_BASE 0x80000000 |
| typedef struct |
| { |
| u32_t handle; |
| u32_t io_code; |
| void *input; |
| int inp_size; |
| void *output; |
| int out_size; |
| }ioctl_t; |
| typedef int (__stdcall *srv_proc_t)(ioctl_t *); |
| #define ERR_OK 0 |
| #define ERR_PARAM -1 |
| u32_t __stdcall drvEntry(int)__asm__("_drvEntry"); |
| /////////////////////////////////////////////////////////////////////////////// |
| #define STDCALL __attribute__ ((stdcall)) __attribute__ ((dllimport)) |
| #define IMPORT __attribute__ ((dllimport)) |
| /////////////////////////////////////////////////////////////////////////////// |
| #define SysMsgBoardStr __SysMsgBoardStr |
| #define PciApi __PciApi |
| //#define RegService __RegService |
| #define CreateObject __CreateObject |
| #define DestroyObject __DestroyObject |
| /////////////////////////////////////////////////////////////////////////////// |
| #define PG_SW 0x003 |
| #define PG_NOCACHE 0x018 |
| void* STDCALL AllocKernelSpace(size_t size)__asm__("AllocKernelSpace"); |
| void* STDCALL KernelAlloc(size_t size)__asm__("KernelAlloc"); |
| void* STDCALL KernelFree(void *mem)__asm__("KernelFree"); |
| void* STDCALL UserAlloc(size_t size)__asm__("UserAlloc"); |
| int STDCALL UserFree(void *mem)__asm__("UserFree"); |
| addr_t STDCALL AllocPages(count_t count)__asm__("AllocPages"); |
| void* STDCALL CreateRingBuffer(size_t size, u32_t map)__asm__("CreateRingBuffer"); |
| u32_t STDCALL RegService(char *name, srv_proc_t proc)__asm__("RegService"); |
| int STDCALL AttachIntHandler(int irq, void *handler, u32_t access) __asm__("AttachIntHandler"); |
| //void *CreateObject(u32 pid, size_t size); |
| //void *DestroyObject(void *obj); |
| addr_t STDCALL MapIoMem(addr_t base, size_t size, u32_t flags)__asm__("MapIoMem"); |
| /////////////////////////////////////////////////////////////////////////////// |
| void STDCALL SetMouseData(int btn, int x, int y, |
| int z, int h)__asm__("SetMouseData"); |
| static u32_t PciApi(int cmd); |
| u8_t STDCALL PciRead8 (u32_t bus, u32_t devfn, u32_t reg)__asm__("PciRead8"); |
| u16_t STDCALL PciRead16(u32_t bus, u32_t devfn, u32_t reg)__asm__("PciRead16"); |
| u32_t STDCALL PciRead32(u32_t bus, u32_t devfn, u32_t reg)__asm__("PciRead32"); |
| u32_t STDCALL PciWrite8 (u32_t bus, u32_t devfn, u32_t reg,u8_t val) __asm__("PciWrite8"); |
| u32_t STDCALL PciWrite16(u32_t bus, u32_t devfn, u32_t reg,u16_t val)__asm__("PciWrite16"); |
| u32_t STDCALL PciWrite32(u32_t bus, u32_t devfn, u32_t reg,u32_t val)__asm__("PciWrite32"); |
| #define pciReadByte(tag, reg) \ |
| PciRead8(PCI_BUS_FROM_TAG(tag),PCI_DFN_FROM_TAG(tag),(reg)) |
| #define pciReadWord(tag, reg) \ |
| PciRead16(PCI_BUS_FROM_TAG(tag),PCI_DFN_FROM_TAG(tag),(reg)) |
| #define pciReadLong(tag, reg) \ |
| PciRead32(PCI_BUS_FROM_TAG(tag),PCI_DFN_FROM_TAG(tag),(reg)) |
| #define pciWriteByte(tag, reg, val) \ |
| PciWrite8(PCI_BUS_FROM_TAG(tag),PCI_DFN_FROM_TAG(tag),(reg),(val)) |
| #define pciWriteWord(tag, reg, val) \ |
| PciWrite16(PCI_BUS_FROM_TAG(tag),PCI_DFN_FROM_TAG(tag),(reg),(val)) |
| #define pciWriteLong(tag, reg, val) \ |
| PciWrite32(PCI_BUS_FROM_TAG(tag),PCI_DFN_FROM_TAG(tag),(reg),(val)) |
| /////////////////////////////////////////////////////////////////////////////// |
| int dbg_open(char *path); |
| int dbgprintf(const char* format, ...); |
| /////////////////////////////////////////////////////////////////////////////// |
| extern inline int GetScreenSize() |
| { |
| int retval; |
| asm("int $0x40" |
| :"=a"(retval) |
| :"a"(61), "b"(1)); |
| return retval; |
| } |
| extern inline int GetScreenBpp() |
| { |
| int retval; |
| asm("int $0x40" |
| :"=a"(retval) |
| :"a"(61), "b"(2)); |
| return retval; |
| } |
| extern inline int GetScreenPitch() |
| { |
| int retval; |
| asm("int $0x40" |
| :"=a"(retval) |
| :"a"(61), "b"(3)); |
| return retval; |
| } |
| extern inline u32_t GetPgAddr(void *mem) |
| { |
| u32_t retval; |
| __asm__ __volatile__ ( |
| "call *__imp__GetPgAddr \n\t" |
| :"=eax" (retval) |
| :"a" (mem) ); |
| return retval; |
| }; |
| extern inline void CommitPages(void *mem, u32_t page, u32_t size) |
| { |
| size = (size+4095) & ~4095; |
| __asm__ __volatile__ ( |
| "call *__imp__CommitPages" |
| ::"a" (page), "b"(mem),"c"(size>>12) |
| :"edx" ); |
| __asm__ __volatile__ ("":::"eax","ebx","ecx"); |
| }; |
| extern inline void UnmapPages(void *mem, size_t size) |
| { |
| size = (size+4095) & ~4095; |
| __asm__ __volatile__ ( |
| "call *__imp__UnmapPages" |
| ::"a" (mem), "c"(size>>12) |
| :"edx"); |
| __asm__ __volatile__ ("":::"eax","ecx"); |
| }; |
| extern inline void usleep(u32_t delay) |
| { |
| if( !delay ) |
| delay++; |
| delay*=1000; |
| while(delay--) |
| __asm__ __volatile__ ( |
| "xorl %%eax, %%eax \n\t" |
| "cpuid \n\t" |
| :::"eax","ebx","ecx","edx"); |
| }; |
| static inline void udelay(u32_t delay) |
| { |
| if(!delay) delay++; |
| delay*=500; |
| while(delay--) |
| { |
| __asm__ __volatile__( |
| "xorl %%eax, %%eax \n\t" |
| "cpuid" |
| :::"eax","ebx","ecx","edx" ); |
| } |
| } |
| static inline void mdelay(u32_t time) |
| { |
| time /= 10; |
| if(!time) time = 1; |
| __asm__ __volatile__ ( |
| "call *__imp__Delay" |
| ::"b" (time)); |
| __asm__ __volatile__ ( |
| "":::"ebx"); |
| }; |
| extern inline u32_t __PciApi(int cmd) |
| { |
| u32_t retval; |
| __asm__ __volatile__ ( |
| "call *__imp__PciApi" |
| :"=a" (retval) |
| :"a" (cmd) |
| :"memory"); |
| return retval; |
| }; |
| extern inline void* __CreateObject(u32_t pid, size_t size) |
| { |
| void *retval; |
| __asm__ __volatile__ ( |
| "call *__imp__CreateObject \n\t" |
| :"=a" (retval) |
| :"a" (size),"b"(pid) |
| :"esi","edi", "memory"); |
| return retval; |
| } |
| extern inline void *__DestroyObject(void *obj) |
| { |
| __asm__ __volatile__ ( |
| "call *__imp__DestroyObject" |
| : |
| :"a" (obj) |
| :"ebx","edx","esi","edi", "memory"); |
| } |
| /* |
| u32 __RegService(char *name, srv_proc_t proc) |
| { |
| u32 retval; |
| asm __volatile__ |
| ( |
| "pushl %%eax \n\t" |
| "pushl %%ebx \n\t" |
| "call *__imp__RegService \n\t" |
| :"=eax" (retval) |
| :"a" (proc), "b" (name) |
| :"memory" |
| ); |
| return retval; |
| }; |
| */ |
| extern inline u32_t safe_cli(void) |
| { |
| u32_t ifl; |
| __asm__ __volatile__ ( |
| "pushf\n\t" |
| "popl %0\n\t" |
| "cli\n" |
| : "=r" (ifl)); |
| return ifl; |
| } |
| extern inline void safe_sti(u32_t ifl) |
| { |
| __asm__ __volatile__ ( |
| "pushl %0\n\t" |
| "popf\n" |
| : : "r" (ifl) |
| ); |
| } |
| extern inline void __clear (void * dst, unsigned len) |
| { |
| u32_t tmp; |
| __asm__ __volatile__ ( |
| // "xorl %%eax, %%eax \n\t" |
| "cld \n\t" |
| "rep stosb \n" |
| :"=c"(tmp),"=D"(tmp) |
| :"a"(0),"c"(len),"D"(dst)); |
| __asm__ __volatile__ ("":::"ecx","edi"); |
| }; |
| extern inline void out8(const u16_t port, const u8_t val) |
| { |
| __asm__ __volatile__ |
| ("outb %1, %0\n" : : "dN"(port), "a"(val)); |
| } |
| extern inline void out16(const u16_t port, const u16_t val) |
| { |
| __asm__ __volatile__ |
| ("outw %1, %0\n" : : "dN"(port), "a"(val)); |
| } |
| extern inline void out32(const u16_t port, const u32_t val) |
| { |
| __asm__ __volatile__ |
| ("outl %1, %0\n" : : "dN"(port), "a"(val)); |
| } |
| extern inline u8_t in8(const u16_t port) |
| { |
| u8_t tmp; |
| __asm__ __volatile__ |
| ("inb %1, %0\n" : "=a"(tmp) : "dN"(port)); |
| return tmp; |
| }; |
| extern inline u16_t in16(const u16_t port) |
| { |
| u16_t tmp; |
| __asm__ __volatile__ |
| ("inw %1, %0\n" : "=a"(tmp) : "dN"(port)); |
| return tmp; |
| }; |
| extern inline u32_t in32(const u16_t port) |
| { |
| u32_t tmp; |
| __asm__ __volatile__ |
| ("inl %1, %0\n" : "=a"(tmp) : "dN"(port)); |
| return tmp; |
| }; |
| extern inline void delay(int time) |
| { |
| __asm__ __volatile__ ( |
| "call *__imp__Delay" |
| ::"b" (time)); |
| __asm__ __volatile__ ( |
| "":::"ebx"); |
| } |
| extern inline void change_task() |
| { |
| __asm__ __volatile__ ( |
| "call *__imp__ChangeTask"); |
| } |
| int drm_order(unsigned long size); |
| #endif |
| /drivers/video/drm/include/types.h |
|---|
| 0,0 → 1,199 |
| #ifndef __TYPES_H__ |
| #define __TYPES_H__ |
| typedef int bool; |
| #define false 0 |
| #define true 1 |
| typedef unsigned int size_t; |
| typedef unsigned int count_t; |
| typedef unsigned int addr_t; |
| typedef unsigned char u8; |
| typedef unsigned short u16; |
| typedef unsigned int u32; |
| typedef unsigned long long u64; |
| typedef unsigned char __u8; |
| typedef unsigned short __u16; |
| typedef unsigned int __u32; |
| typedef unsigned long long __u64; |
| typedef signed char __s8; |
| typedef signed short __s16; |
| typedef signed int __s32; |
| typedef signed long long __s64; |
| typedef unsigned char uint8_t; |
| typedef unsigned short uint16_t; |
| typedef unsigned int uint32_t; |
| typedef unsigned long long uint64_t; |
| typedef unsigned char u8_t; |
| typedef unsigned short u16_t; |
| typedef unsigned int u32_t; |
| typedef unsigned long long u64_t; |
| #define NULL (void*)0 |
| typedef uint32_t dma_addr_t; |
| typedef uint32_t resource_size_t; |
| #define __user |
| #define cpu_to_le16(v16) (v16) |
| #define cpu_to_le32(v32) (v32) |
| #define cpu_to_le64(v64) (v64) |
| #define le16_to_cpu(v16) (v16) |
| #define le32_to_cpu(v32) (v32) |
| #define le64_to_cpu(v64) (v64) |
| #define likely(x) __builtin_expect(!!(x), 1) |
| #define unlikely(x) __builtin_expect(!!(x), 0) |
| #define KERN_EMERG "<0>" /* system is unusable */ |
| #define KERN_ALERT "<1>" /* action must be taken immediately */ |
| #define KERN_CRIT "<2>" /* critical conditions */ |
| #define KERN_ERR "<3>" /* error conditions */ |
| #define KERN_WARNING "<4>" /* warning conditions */ |
| #define KERN_NOTICE "<5>" /* normal but significant condition */ |
| #define KERN_INFO "<6>" /* informational */ |
| #define KERN_DEBUG "<7>" /* debug-level messages */ |
| //int printk(const char *fmt, ...); |
| #define printk(fmt, arg...) dbgprintf(fmt , ##arg) |
| #define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */ |
| #define DRM_INFO(fmt, arg...) dbgprintf("DRM: "fmt , ##arg) |
| #define DRM_DEBUG(fmt, arg...) \ |
| printk(KERN_ERR "[" DRM_NAME ":%s] *ERROR* " fmt , __func__ , ##arg) |
| #define DRM_ERROR(fmt, arg...) \ |
| printk(KERN_ERR "[" DRM_NAME ":%s] *ERROR* " fmt , __func__ , ##arg) |
| #define BUILD_BUG_ON_ZERO(e) (sizeof(char[1 - 2 * !!(e)]) - 1) |
| #define __must_be_array(a) \ |
| BUILD_BUG_ON_ZERO(__builtin_types_compatible_p(typeof(a), typeof(&a[0]))) |
| #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]) + __must_be_array(arr)) |
| #ifndef HAVE_ARCH_BUG |
| #define BUG() do { \ |
| printk("BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __FUNCTION__); \ |
| /* panic("BUG!"); */ \ |
| } while (0) |
| #endif |
| #ifndef HAVE_ARCH_BUG_ON |
| #define BUG_ON(condition) do { if (unlikely(condition)) BUG(); } while(0) |
| #endif |
| #define MTRR_TYPE_UNCACHABLE 0 |
| #define MTRR_TYPE_WRCOMB 1 |
| #define MTRR_TYPE_WRTHROUGH 4 |
| #define MTRR_TYPE_WRPROT 5 |
| #define MTRR_TYPE_WRBACK 6 |
| #define MTRR_NUM_TYPES 7 |
| int dbgprintf(const char* format, ...); |
| #define GFP_KERNEL 0 |
| //#include <string.h> |
| void* memcpy(void *s1, const void *s2, size_t n); |
| void* memset(void *s, int c, size_t n); |
| size_t strlen(const char *s); |
| void *malloc(size_t size); |
| #define kfree free |
| static inline void *kzalloc(size_t size, u32_t flags) |
| { |
| void *ret = malloc(size); |
| memset(ret, 0, size); |
| return ret; |
| } |
| struct drm_gem_object { |
| /** Reference count of this object */ |
| // struct kref refcount; |
| /** Handle count of this object. Each handle also holds a reference */ |
| // struct kref handlecount; |
| /** Related drm device */ |
| // struct drm_device *dev; |
| /** File representing the shmem storage */ |
| // struct file *filp; |
| /* Mapping info for this object */ |
| // struct drm_map_list map_list; |
| /** |
| * Size of the object, in bytes. Immutable over the object's |
| * lifetime. |
| */ |
| size_t size; |
| /** |
| * Global name for this object, starts at 1. 0 means unnamed. |
| * Access is covered by the object_name_lock in the related drm_device |
| */ |
| int name; |
| /** |
| * Memory domains. These monitor which caches contain read/write data |
| * related to the object. When transitioning from one set of domains |
| * to another, the driver is called to ensure that caches are suitably |
| * flushed and invalidated |
| */ |
| uint32_t read_domains; |
| uint32_t write_domain; |
| /** |
| * While validating an exec operation, the |
| * new read/write domain values are computed here. |
| * They will be transferred to the above values |
| * at the point that any cache flushing occurs |
| */ |
| uint32_t pending_read_domains; |
| uint32_t pending_write_domain; |
| void *driver_private; |
| }; |
| struct drm_file; |
| #define offsetof(TYPE,MEMBER) __builtin_offsetof(TYPE,MEMBER) |
| #define container_of(ptr, type, member) ({ \ |
| const typeof( ((type *)0)->member ) *__mptr = (ptr); \ |
| (type *)( (char *)__mptr - offsetof(type,member) );}) |
| #define DRM_MEMORYBARRIER() __asm__ __volatile__("lock; addl $0,0(%esp)") |
| #endif //__TYPES_H__ |