| 1,6 → 1,17 |
|---|
| #ifndef _INTEL_RINGBUFFER_H_ |
| #define _INTEL_RINGBUFFER_H_ |
| |
| /* |
| * Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use" |
| * Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use" |
| * Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use" |
| * |
| * "If the Ring Buffer Head Pointer and the Tail Pointer are on the same |
| * cacheline, the Head Pointer must not be greater than the Tail |
| * Pointer." |
| */ |
| #define I915_RING_FREE_SPACE 64 |
| |
| struct intel_hw_status_page { |
| u32 *page_addr; |
| unsigned int gfx_addr; |
| 70,8 → 81,7 |
|---|
| int __must_check (*flush)(struct intel_ring_buffer *ring, |
| u32 invalidate_domains, |
| u32 flush_domains); |
| int (*add_request)(struct intel_ring_buffer *ring, |
| u32 *seqno); |
| int (*add_request)(struct intel_ring_buffer *ring); |
| /* Some chipsets are not quite as coherent as advertised and need |
| * an expensive kick to force a true read of the up-to-date seqno. |
| * However, the up-to-date seqno is not always required and the last |
| 81,7 → 91,10 |
|---|
| u32 (*get_seqno)(struct intel_ring_buffer *ring, |
| bool lazy_coherency); |
| int (*dispatch_execbuffer)(struct intel_ring_buffer *ring, |
| u32 offset, u32 length); |
| u32 offset, u32 length, |
| unsigned flags); |
| #define I915_DISPATCH_SECURE 0x1 |
| #define I915_DISPATCH_PINNED 0x2 |
| void (*cleanup)(struct intel_ring_buffer *ring); |
| int (*sync_to)(struct intel_ring_buffer *ring, |
| struct intel_ring_buffer *to, |
| 181,17 → 194,12 |
|---|
| * The area from dword 0x20 to 0x3ff is available for driver usage. |
| */ |
| #define I915_GEM_HWS_INDEX 0x20 |
| #define I915_GEM_HWS_SCRATCH_INDEX 0x30 |
| #define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT) |
| |
| void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring); |
| |
| int __must_check intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n); |
| static inline int intel_wait_ring_idle(struct intel_ring_buffer *ring) |
| { |
| return intel_wait_ring_buffer(ring, ring->size - 8); |
| } |
| |
| int __must_check intel_ring_begin(struct intel_ring_buffer *ring, int n); |
| |
| static inline void intel_ring_emit(struct intel_ring_buffer *ring, |
| u32 data) |
| { |
| 198,10 → 206,9 |
|---|
| iowrite32(data, ring->virtual_start + ring->tail); |
| ring->tail += 4; |
| } |
| |
| void intel_ring_advance(struct intel_ring_buffer *ring); |
| int __must_check intel_ring_idle(struct intel_ring_buffer *ring); |
| |
| u32 intel_ring_get_seqno(struct intel_ring_buffer *ring); |
| int intel_ring_flush_all_caches(struct intel_ring_buffer *ring); |
| int intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring); |
| |
| 217,6 → 224,12 |
|---|
| return ring->tail; |
| } |
| |
| static inline u32 intel_ring_get_seqno(struct intel_ring_buffer *ring) |
| { |
| BUG_ON(ring->outstanding_lazy_request == 0); |
| return ring->outstanding_lazy_request; |
| } |
| |
| static inline void i915_trace_irq_get(struct intel_ring_buffer *ring, u32 seqno) |
| { |
| if (ring->trace_irq_seqno == 0 && ring->irq_get(ring)) |