| 746,9 → 746,9 |
|---|
| |
| ret = i915_gem_render_state_init(req); |
| if (ret) |
| DRM_ERROR("init render state: %d\n", ret); |
| return ret; |
| |
| return ret; |
| return 0; |
| } |
| |
| static int wa_add(struct drm_i915_private *dev_priv, |
| 789,6 → 789,22 |
|---|
| |
| #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val) |
| |
| static int wa_ring_whitelist_reg(struct intel_engine_cs *ring, i915_reg_t reg) |
| { |
| struct drm_i915_private *dev_priv = ring->dev->dev_private; |
| struct i915_workarounds *wa = &dev_priv->workarounds; |
| const uint32_t index = wa->hw_whitelist_count[ring->id]; |
| |
| if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS)) |
| return -EINVAL; |
| |
| WA_WRITE(RING_FORCE_TO_NONPRIV(ring->mmio_base, index), |
| i915_mmio_reg_offset(reg)); |
| wa->hw_whitelist_count[ring->id]++; |
| |
| return 0; |
| } |
| |
| static int gen8_init_workarounds(struct intel_engine_cs *ring) |
| { |
| struct drm_device *dev = ring->dev; |
| 894,6 → 910,7 |
|---|
| struct drm_device *dev = ring->dev; |
| struct drm_i915_private *dev_priv = dev->dev_private; |
| uint32_t tmp; |
| int ret; |
| |
| /* WaEnableLbsSlaRetryTimerDecrement:skl */ |
| I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) | |
| 964,6 → 981,20 |
|---|
| /* WaDisableSTUnitPowerOptimization:skl,bxt */ |
| WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); |
| |
| /* WaOCLCoherentLineFlush:skl,bxt */ |
| I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) | |
| GEN8_LQSC_FLUSH_COHERENT_LINES)); |
| |
| /* WaEnablePreemptionGranularityControlByUMD:skl,bxt */ |
| ret= wa_ring_whitelist_reg(ring, GEN8_CS_CHICKEN1); |
| if (ret) |
| return ret; |
| |
| /* WaAllowUMDToModifyHDCChicken1:skl,bxt */ |
| ret = wa_ring_whitelist_reg(ring, GEN8_HDC_CHICKEN1); |
| if (ret) |
| return ret; |
| |
| return 0; |
| } |
| |
| 1019,6 → 1050,16 |
|---|
| if (ret) |
| return ret; |
| |
| /* |
| * Actual WA is to disable percontext preemption granularity control |
| * until D0 which is the default case so this is equivalent to |
| * !WaDisablePerCtxtPreemptionGranularityControl:skl |
| */ |
| if (IS_SKL_REVID(dev, SKL_REVID_E0, REVID_FOREVER)) { |
| I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1, |
| _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL)); |
| } |
| |
| if (IS_SKL_REVID(dev, 0, SKL_REVID_D0)) { |
| /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */ |
| I915_WRITE(FF_SLICE_CS_CHICKEN2, |
| 1072,6 → 1113,11 |
|---|
| GEN7_HALF_SLICE_CHICKEN1, |
| GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); |
| |
| /* WaDisableLSQCROPERFforOCL:skl */ |
| ret = wa_ring_whitelist_reg(ring, GEN8_L3SQCREG4); |
| if (ret) |
| return ret; |
| |
| return skl_tune_iz_hashing(ring); |
| } |
| |
| 1107,6 → 1153,20 |
|---|
| GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); |
| } |
| |
| /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */ |
| /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */ |
| /* WaDisableObjectLevelPreemtionForInstanceId:bxt */ |
| /* WaDisableLSQCROPERFforOCL:bxt */ |
| if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) { |
| ret = wa_ring_whitelist_reg(ring, GEN9_CS_DEBUG_MODE1); |
| if (ret) |
| return ret; |
| |
| ret = wa_ring_whitelist_reg(ring, GEN8_L3SQCREG4); |
| if (ret) |
| return ret; |
| } |
| |
| return 0; |
| } |
| |
| 1118,6 → 1178,7 |
|---|
| WARN_ON(ring->id != RCS); |
| |
| dev_priv->workarounds.count = 0; |
| dev_priv->workarounds.hw_whitelist_count[RCS] = 0; |
| |
| if (IS_BROADWELL(dev)) |
| return bdw_init_workarounds(ring); |
| 1868,15 → 1929,13 |
|---|
| offset = cs_offset; |
| } |
| |
| ret = intel_ring_begin(req, 4); |
| ret = intel_ring_begin(req, 2); |
| if (ret) |
| return ret; |
| |
| intel_ring_emit(ring, MI_BATCH_BUFFER); |
| intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
| intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ? |
| 0 : MI_BATCH_NON_SECURE)); |
| intel_ring_emit(ring, offset + len - 8); |
| intel_ring_emit(ring, MI_NOOP); |
| intel_ring_advance(ring); |
| |
| return 0; |
| 1997,11 → 2056,36 |
|---|
| |
| void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf) |
| { |
| if (HAS_LLC(ringbuf->obj->base.dev) && !ringbuf->obj->stolen) |
| vunmap(ringbuf->virtual_start); |
| else |
| iounmap(ringbuf->virtual_start); |
| ringbuf->virtual_start = NULL; |
| ringbuf->vma = NULL; |
| i915_gem_object_ggtt_unpin(ringbuf->obj); |
| } |
| |
| static u32 *vmap_obj(struct drm_i915_gem_object *obj) |
| { |
| struct sg_page_iter sg_iter; |
| struct page **pages; |
| void *addr; |
| int i; |
| |
| pages = drm_malloc_ab(obj->base.size >> PAGE_SHIFT, sizeof(*pages)); |
| if (pages == NULL) |
| return NULL; |
| |
| i = 0; |
| for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) |
| pages[i++] = sg_page_iter_page(&sg_iter); |
| |
| addr = vmap(pages, i, 0, PAGE_KERNEL); |
| drm_free_large(pages); |
| |
| return addr; |
| } |
| |
| int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev, |
| struct intel_ringbuffer *ringbuf) |
| { |
| 2011,10 → 2095,28 |
|---|
| unsigned flags = PIN_OFFSET_BIAS | 4096; |
| int ret; |
| |
| ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE); |
| if (HAS_LLC(dev_priv) && !obj->stolen) { |
| ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, flags); |
| if (ret) |
| return ret; |
| |
| ret = i915_gem_object_set_to_cpu_domain(obj, true); |
| if (ret) { |
| i915_gem_object_ggtt_unpin(obj); |
| return ret; |
| } |
| |
| ringbuf->virtual_start = vmap_obj(obj); |
| if (ringbuf->virtual_start == NULL) { |
| i915_gem_object_ggtt_unpin(obj); |
| return -ENOMEM; |
| } |
| } else { |
| ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, |
| flags | PIN_MAPPABLE); |
| if (ret) |
| return ret; |
| |
| ret = i915_gem_object_set_to_gtt_domain(obj, true); |
| if (ret) { |
| i915_gem_object_ggtt_unpin(obj); |
| 2021,6 → 2123,9 |
|---|
| return ret; |
| } |
| |
| /* Access through the GTT requires the device to be awake. */ |
| assert_rpm_wakelock_held(dev_priv); |
| |
| ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base + |
| i915_gem_obj_ggtt_offset(obj), ringbuf->size); |
| if (ringbuf->virtual_start == NULL) { |
| 2027,7 → 2132,10 |
|---|
| i915_gem_object_ggtt_unpin(obj); |
| return -EINVAL; |
| } |
| } |
| |
| ringbuf->vma = i915_gem_obj_to_ggtt(obj); |
| |
| return 0; |
| } |
| |
| 2643,6 → 2751,7 |
|---|
| |
| ring->name = "render ring"; |
| ring->id = RCS; |
| ring->exec_id = I915_EXEC_RENDER; |
| ring->mmio_base = RENDER_RING_BASE; |
| |
| if (INTEL_INFO(dev)->gen >= 8) { |
| 2791,6 → 2900,7 |
|---|
| |
| ring->name = "bsd ring"; |
| ring->id = VCS; |
| ring->exec_id = I915_EXEC_BSD; |
| |
| ring->write_tail = ring_write_tail; |
| if (INTEL_INFO(dev)->gen >= 6) { |
| 2867,6 → 2977,7 |
|---|
| |
| ring->name = "bsd2 ring"; |
| ring->id = VCS2; |
| ring->exec_id = I915_EXEC_BSD; |
| |
| ring->write_tail = ring_write_tail; |
| ring->mmio_base = GEN8_BSD2_RING_BASE; |
| 2897,6 → 3008,7 |
|---|
| |
| ring->name = "blitter ring"; |
| ring->id = BCS; |
| ring->exec_id = I915_EXEC_BLT; |
| |
| ring->mmio_base = BLT_RING_BASE; |
| ring->write_tail = ring_write_tail; |
| 2954,6 → 3066,7 |
|---|
| |
| ring->name = "video enhancement ring"; |
| ring->id = VECS; |
| ring->exec_id = I915_EXEC_VEBOX; |
| |
| ring->mmio_base = VEBOX_RING_BASE; |
| ring->write_tail = ring_write_tail; |