228,7 → 228,7 |
* need to wake up periodically and check that ourselves. */ |
I915_WRITE(GMBUS4 + reg_offset, gmbus4_irq_en); |
|
for (i = 0; i < msecs_to_jiffies(50) + 1; i++) { |
for (i = 0; i < msecs_to_jiffies_timeout(50); i++) { |
prepare_to_wait(&dev_priv->gmbus_wait_queue, &wait, |
TASK_UNINTERRUPTIBLE); |
|
263,7 → 263,8 |
/* Important: The hw handles only the first bit, so set only one! */ |
I915_WRITE(GMBUS4 + reg_offset, GMBUS_IDLE_EN); |
|
ret = wait_event_timeout(dev_priv->gmbus_wait_queue, C, 10); |
ret = wait_event_timeout(dev_priv->gmbus_wait_queue, C, |
msecs_to_jiffies_timeout(10)); |
|
I915_WRITE(GMBUS4 + reg_offset, 0); |
|
522,7 → 523,9 |
struct drm_i915_private *dev_priv = dev->dev_private; |
int ret, i; |
|
if (HAS_PCH_SPLIT(dev)) |
if (HAS_PCH_NOP(dev)) |
return 0; |
else if (HAS_PCH_SPLIT(dev)) |
dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA; |
else if (IS_VALLEYVIEW(dev)) |
dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE; |