478,8 → 478,8 |
|
DRM_DEBUG_KMS("\n"); |
|
intel_enable_dsi_pll(encoder); |
intel_dsi_prepare(encoder); |
intel_enable_dsi_pll(encoder); |
|
/* Panel Enable over CRC PMIC */ |
if (intel_dsi->gpio_panel) |
634,7 → 634,6 |
{ |
struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
u32 val; |
|
DRM_DEBUG_KMS("\n"); |
|
642,9 → 641,13 |
|
intel_dsi_clear_device_ready(encoder); |
|
if (!IS_BROXTON(dev_priv)) { |
u32 val; |
|
val = I915_READ(DSPCLK_GATE_D); |
val &= ~DPOUNIT_CLOCK_GATE_DISABLE; |
I915_WRITE(DSPCLK_GATE_D, val); |
} |
|
drm_panel_unprepare(intel_dsi->panel); |
|
709,7 → 712,7 |
static void intel_dsi_get_config(struct intel_encoder *encoder, |
struct intel_crtc_state *pipe_config) |
{ |
u32 pclk = 0; |
u32 pclk; |
DRM_DEBUG_KMS("\n"); |
|
pipe_config->has_dsi_encoder = true; |
720,12 → 723,7 |
*/ |
pipe_config->dpll_hw_state.dpll_md = 0; |
|
if (IS_BROXTON(encoder->base.dev)) |
pclk = bxt_get_dsi_pclk(encoder, pipe_config->pipe_bpp); |
else if (IS_VALLEYVIEW(encoder->base.dev) || |
IS_CHERRYVIEW(encoder->base.dev)) |
pclk = vlv_get_dsi_pclk(encoder, pipe_config->pipe_bpp); |
|
pclk = intel_dsi_get_pclk(encoder, pipe_config->pipe_bpp); |
if (!pclk) |
return; |
|
787,10 → 785,9 |
{ |
struct drm_device *dev = encoder->dev; |
struct drm_i915_private *dev_priv = dev->dev_private; |
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
enum port port; |
unsigned int bpp = intel_crtc->config->pipe_bpp; |
unsigned int bpp = dsi_pixel_format_bpp(intel_dsi->pixel_format); |
unsigned int lane_count = intel_dsi->lane_count; |
|
u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; |
861,7 → 858,7 |
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
enum port port; |
unsigned int bpp = intel_crtc->config->pipe_bpp; |
unsigned int bpp = dsi_pixel_format_bpp(intel_dsi->pixel_format); |
u32 val, tmp; |
u16 mode_hdisplay; |
|