344,7 → 344,7 |
DRM_DEBUG_KMS("\n"); |
|
power_domain = intel_display_port_power_domain(encoder); |
if (!intel_display_power_enabled(dev_priv, power_domain)) |
if (!intel_display_power_is_enabled(dev_priv, power_domain)) |
return false; |
|
/* XXX: this only works for one DSI output */ |
423,9 → 423,11 |
} |
|
/* return pixels in terms of txbyteclkhs */ |
static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count) |
static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count, |
u16 burst_mode_ratio) |
{ |
return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp, 8), lane_count); |
return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio, |
8 * 100), lane_count); |
} |
|
static void set_dsi_timings(struct drm_encoder *encoder, |
451,10 → 453,12 |
vbp = mode->vtotal - mode->vsync_end; |
|
/* horizontal values are in terms of high speed byte clock */ |
hactive = txbyteclkhs(hactive, bpp, lane_count); |
hfp = txbyteclkhs(hfp, bpp, lane_count); |
hsync = txbyteclkhs(hsync, bpp, lane_count); |
hbp = txbyteclkhs(hbp, bpp, lane_count); |
hactive = txbyteclkhs(hactive, bpp, lane_count, |
intel_dsi->burst_mode_ratio); |
hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio); |
hsync = txbyteclkhs(hsync, bpp, lane_count, |
intel_dsi->burst_mode_ratio); |
hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio); |
|
I915_WRITE(MIPI_HACTIVE_AREA_COUNT(pipe), hactive); |
I915_WRITE(MIPI_HFP_COUNT(pipe), hfp); |
541,12 → 545,14 |
intel_dsi->video_mode_format == VIDEO_MODE_BURST) { |
I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe), |
txbyteclkhs(adjusted_mode->htotal, bpp, |
intel_dsi->lane_count) + 1); |
intel_dsi->lane_count, |
intel_dsi->burst_mode_ratio) + 1); |
} else { |
I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe), |
txbyteclkhs(adjusted_mode->vtotal * |
adjusted_mode->htotal, |
bpp, intel_dsi->lane_count) + 1); |
bpp, intel_dsi->lane_count, |
intel_dsi->burst_mode_ratio) + 1); |
} |
I915_WRITE(MIPI_LP_RX_TIMEOUT(pipe), intel_dsi->lp_rx_timeout); |
I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(pipe), intel_dsi->turn_arnd_val); |