| 32,7 → 32,7 |
|---|
| #include <drm/drm_crtc.h> |
| #include <drm/drm_crtc_helper.h> |
| #include <drm/drm_fb_helper.h> |
| #include <drm/drm_dp_helper.h> |
| #include <drm/drm_dp_mst_helper.h> |
| |
| #define KBUILD_MODNAME "i915.dll" |
| |
| 48,10 → 48,10 |
|---|
| * we've never had a chance to check the condition before the timeout. |
| */ |
| #define _wait_for(COND, MS, W) ({ \ |
| unsigned long timeout__ = GetTimerTicks() + msecs_to_jiffies(MS); \ |
| unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \ |
| int ret__ = 0; \ |
| while (!(COND)) { \ |
| if (time_after(GetTimerTicks(), timeout__)) { \ |
| if (time_after(jiffies, timeout__)) { \ |
| if (!(COND)) \ |
| ret__ = -ETIMEDOUT; \ |
| break; \ |
| 83,6 → 83,12 |
|---|
| #define MAX_OUTPUTS 6 |
| /* maximum connectors per crtcs in the mode set */ |
| |
| /* Maximum cursor sizes */ |
| #define GEN2_CURSOR_WIDTH 64 |
| #define GEN2_CURSOR_HEIGHT 64 |
| #define MAX_CURSOR_WIDTH 256 |
| #define MAX_CURSOR_HEIGHT 256 |
| |
| #define INTEL_I2C_BUS_DVO 1 |
| #define INTEL_I2C_BUS_SDVO 2 |
| |
| 99,6 → 105,7 |
|---|
| #define INTEL_OUTPUT_EDP 8 |
| #define INTEL_OUTPUT_DSI 9 |
| #define INTEL_OUTPUT_UNKNOWN 10 |
| #define INTEL_OUTPUT_DP_MST 11 |
| |
| #define INTEL_DVO_CHIP_NONE 0 |
| #define INTEL_DVO_CHIP_LVDS 1 |
| 105,8 → 112,8 |
|---|
| #define INTEL_DVO_CHIP_TMDS 2 |
| #define INTEL_DVO_CHIP_TVOUT 4 |
| |
| #define INTEL_DSI_COMMAND_MODE 0 |
| #define INTEL_DSI_VIDEO_MODE 1 |
| #define INTEL_DSI_VIDEO_MODE 0 |
| #define INTEL_DSI_COMMAND_MODE 1 |
| |
| struct intel_framebuffer { |
| struct drm_framebuffer base; |
| 115,9 → 122,10 |
|---|
| |
| struct intel_fbdev { |
| struct drm_fb_helper helper; |
| struct intel_framebuffer ifb; |
| struct intel_framebuffer *fb; |
| struct list_head fbdev_list; |
| struct drm_display_mode *our_mode; |
| int preferred_bpp; |
| }; |
| |
| struct intel_encoder { |
| 129,11 → 137,7 |
|---|
| struct intel_crtc *new_crtc; |
| |
| int type; |
| /* |
| * Intel hw has only one MUX where encoders could be clone, hence a |
| * simple flag is enough to compute the possible_clones mask. |
| */ |
| bool cloneable; |
| unsigned int cloneable; |
| bool connectors_active; |
| void (*hot_plug)(struct intel_encoder *); |
| bool (*compute_config)(struct intel_encoder *, |
| 154,6 → 158,12 |
|---|
| * be set correctly before calling this function. */ |
| void (*get_config)(struct intel_encoder *, |
| struct intel_crtc_config *pipe_config); |
| /* |
| * Called during system suspend after all pending requests for the |
| * encoder are flushed (for example for DP AUX transactions) and |
| * device interrupts are disabled. |
| */ |
| void (*suspend)(struct intel_encoder *); |
| int crtc_mask; |
| enum hpd_pin hpd_pin; |
| }; |
| 167,6 → 177,7 |
|---|
| struct { |
| bool present; |
| u32 level; |
| u32 min; |
| u32 max; |
| bool enabled; |
| bool combination_mode; /* gen 2/4 only */ |
| 192,6 → 203,14 |
|---|
| * and active (i.e. dpms ON state). */ |
| bool (*get_hw_state)(struct intel_connector *); |
| |
| /* |
| * Removes all interfaces through which the connector is accessible |
| * - like sysfs, debugfs entries -, so that no new operations can be |
| * started on the connector. Also makes sure all currently pending |
| * operations finish before returing. |
| */ |
| void (*unregister)(struct intel_connector *); |
| |
| /* Panel info for eDP and LVDS */ |
| struct intel_panel panel; |
| |
| 201,6 → 220,10 |
|---|
| /* since POLL and HPD connectors may use the same HPD line keep the native |
| state of connector->polled in case hotplug storm detection changes it */ |
| u8 polled; |
| |
| void *port; /* store this opaque as its illegal to dereference it */ |
| |
| struct intel_dp *mst_port; |
| }; |
| |
| typedef struct dpll { |
| 215,6 → 238,12 |
|---|
| int p; |
| } intel_clock_t; |
| |
| struct intel_plane_config { |
| bool tiled; |
| int size; |
| u32 base; |
| }; |
| |
| struct intel_crtc_config { |
| /** |
| * quirks - bitfield with hw state readout quirks |
| 225,6 → 254,7 |
|---|
| * accordingly. |
| */ |
| #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */ |
| #define PIPE_CONFIG_QUIRK_INHERITED_MODE (1<<1) /* mode inherited from firmware */ |
| unsigned long quirks; |
| |
| /* User requested mode, only valid as a starting point to |
| 260,6 → 290,13 |
|---|
| * accordingly. */ |
| bool has_dp_encoder; |
| |
| /* Whether we should send NULL infoframes. Required for audio. */ |
| bool has_hdmi_sink; |
| |
| /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or |
| * has_dp_encoder is set. */ |
| bool has_audio; |
| |
| /* |
| * Enable dithering, used when the selected pipe bpp doesn't match the |
| * plane bpp. |
| 287,6 → 324,9 |
|---|
| /* Selected dpll when shared or DPLL_ID_PRIVATE. */ |
| enum intel_dpll_id shared_dpll; |
| |
| /* PORT_CLK_SEL for DDI ports. */ |
| uint32_t ddi_pll_sel; |
| |
| /* Actual register state of the dpll, for shared dpll cross-checking. */ |
| struct intel_dpll_hw_state dpll_hw_state; |
| |
| 293,6 → 333,9 |
|---|
| int pipe_bpp; |
| struct intel_link_m_n dp_m_n; |
| |
| /* m2_n2 for eDP downclock */ |
| struct intel_link_m_n dp_m2_n2; |
| |
| /* |
| * Frequence the dpll for the port should run at. Differs from the |
| * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also |
| 315,6 → 358,7 |
|---|
| u32 pos; |
| u32 size; |
| bool enabled; |
| bool force_thru; |
| } pch_pfit; |
| |
| /* FDI configuration, only valid if has_pch_encoder is set. */ |
| 324,6 → 368,9 |
|---|
| bool ips_enabled; |
| |
| bool double_wide; |
| |
| bool dp_encoder_is_mst; |
| int pbn; |
| }; |
| |
| struct intel_pipe_wm { |
| 330,8 → 377,16 |
|---|
| struct intel_wm_level wm[5]; |
| uint32_t linetime; |
| bool fbc_wm_enabled; |
| bool pipe_enabled; |
| bool sprites_enabled; |
| bool sprites_scaled; |
| }; |
| |
| struct intel_mmio_flip { |
| u32 seqno; |
| u32 ring_id; |
| }; |
| |
| struct intel_crtc { |
| struct drm_crtc base; |
| enum pipe pipe; |
| 344,7 → 399,6 |
|---|
| */ |
| bool active; |
| unsigned long enabled_power_domains; |
| bool eld_vld; |
| bool primary_enabled; /* is the primary plane (partially) visible? */ |
| bool lowfreq_avail; |
| struct intel_overlay *overlay; |
| 359,14 → 413,15 |
|---|
| |
| struct drm_i915_gem_object *cursor_bo; |
| uint32_t cursor_addr; |
| int16_t cursor_x, cursor_y; |
| int16_t cursor_width, cursor_height; |
| bool cursor_visible; |
| uint32_t cursor_cntl; |
| uint32_t cursor_base; |
| |
| struct intel_plane_config plane_config; |
| struct intel_crtc_config config; |
| struct intel_crtc_config *new_config; |
| bool new_enabled; |
| |
| uint32_t ddi_pll_sel; |
| |
| /* reset counter value when the last flip was submitted */ |
| unsigned int reset_counter; |
| |
| 379,10 → 434,15 |
|---|
| /* watermarks currently being used */ |
| struct intel_pipe_wm active; |
| } wm; |
| |
| wait_queue_head_t vbl_wait; |
| |
| int scanline_offset; |
| }; |
| |
| struct intel_plane_wm_parameters { |
| uint32_t horiz_pixels; |
| uint32_t vert_pixels; |
| uint8_t bytes_per_pixel; |
| bool enabled; |
| bool scaled; |
| 395,7 → 455,6 |
|---|
| struct drm_i915_gem_object *obj; |
| bool can_scale; |
| int max_downscale; |
| u32 lut_r[1024], lut_g[1024], lut_b[1024]; |
| int crtc_x, crtc_y; |
| unsigned int crtc_w, crtc_h; |
| uint32_t src_x, src_y; |
| 448,6 → 507,7 |
|---|
| #define to_intel_encoder(x) container_of(x, struct intel_encoder, base) |
| #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) |
| #define to_intel_plane(x) container_of(x, struct intel_plane, base) |
| #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL) |
| |
| struct intel_hdmi { |
| u32 hdmi_reg; |
| 458,15 → 518,29 |
|---|
| bool has_audio; |
| enum hdmi_force_audio force_audio; |
| bool rgb_quant_range_selectable; |
| enum hdmi_picture_aspect aspect_ratio; |
| void (*write_infoframe)(struct drm_encoder *encoder, |
| enum hdmi_infoframe_type type, |
| const void *frame, ssize_t len); |
| void (*set_infoframes)(struct drm_encoder *encoder, |
| bool enable, |
| struct drm_display_mode *adjusted_mode); |
| }; |
| |
| struct intel_dp_mst_encoder; |
| #define DP_MAX_DOWNSTREAM_PORTS 0x10 |
| |
| /** |
| * HIGH_RR is the highest eDP panel refresh rate read from EDID |
| * LOW_RR is the lowest eDP panel refresh rate found from EDID |
| * parsing for same resolution. |
| */ |
| enum edp_drrs_refresh_rate_type { |
| DRRS_HIGH_RR, |
| DRRS_LOW_RR, |
| DRRS_MAX_RR, /* RR count */ |
| }; |
| |
| struct intel_dp { |
| uint32_t output_reg; |
| uint32_t aux_ch_ctl_reg; |
| 480,8 → 554,7 |
|---|
| uint8_t dpcd[DP_RECEIVER_CAP_SIZE]; |
| uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; |
| uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; |
| struct i2c_adapter adapter; |
| struct i2c_algo_dp_aux_data algo; |
| struct drm_dp_aux aux; |
| uint8_t train_set[4]; |
| int panel_power_up_delay; |
| int panel_power_down_delay; |
| 490,8 → 563,36 |
|---|
| int backlight_off_delay; |
| struct delayed_work panel_vdd_work; |
| bool want_panel_vdd; |
| bool psr_setup_done; |
| unsigned long last_power_cycle; |
| unsigned long last_power_on; |
| unsigned long last_backlight_off; |
| |
| bool use_tps3; |
| bool can_mst; /* this port supports mst */ |
| bool is_mst; |
| int active_mst_links; |
| /* connector directly attached - won't be use for modeset in mst world */ |
| struct intel_connector *attached_connector; |
| |
| /* mst connector list */ |
| struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES]; |
| struct drm_dp_mst_topology_mgr mst_mgr; |
| |
| uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index); |
| /* |
| * This function returns the value we have to program the AUX_CTL |
| * register with to kick off an AUX transaction. |
| */ |
| uint32_t (*get_aux_send_ctl)(struct intel_dp *dp, |
| bool has_aux_irq, |
| int send_bytes, |
| uint32_t aux_clock_divider); |
| struct { |
| enum drrs_support_type type; |
| enum edp_drrs_refresh_rate_type refresh_rate_type; |
| struct mutex mutex; |
| } drrs_state; |
| |
| }; |
| |
| struct intel_digital_port { |
| 500,13 → 601,22 |
|---|
| u32 saved_port_bits; |
| struct intel_dp dp; |
| struct intel_hdmi hdmi; |
| bool (*hpd_pulse)(struct intel_digital_port *, bool); |
| }; |
| |
| struct intel_dp_mst_encoder { |
| struct intel_encoder base; |
| enum pipe pipe; |
| struct intel_digital_port *primary; |
| void *port; /* store this opaque as its illegal to dereference it */ |
| }; |
| |
| static inline int |
| vlv_dport_to_channel(struct intel_digital_port *dport) |
| { |
| switch (dport->port) { |
| case PORT_B: |
| case PORT_D: |
| return DPIO_CH0; |
| case PORT_C: |
| return DPIO_CH1; |
| 515,6 → 625,20 |
|---|
| } |
| } |
| |
| static inline int |
| vlv_pipe_to_channel(enum pipe pipe) |
| { |
| switch (pipe) { |
| case PIPE_A: |
| case PIPE_C: |
| return DPIO_CH0; |
| case PIPE_B: |
| return DPIO_CH1; |
| default: |
| BUG(); |
| } |
| } |
| |
| static inline struct drm_crtc * |
| intel_get_crtc_for_pipe(struct drm_device *dev, int pipe) |
| { |
| 539,6 → 663,8 |
|---|
| #define INTEL_FLIP_INACTIVE 0 |
| #define INTEL_FLIP_PENDING 1 |
| #define INTEL_FLIP_COMPLETE 2 |
| u32 flip_count; |
| u32 gtt_offset; |
| bool enable_stall_check; |
| }; |
| |
| 545,6 → 671,7 |
|---|
| struct intel_set_config { |
| struct drm_encoder **save_connector_encoders; |
| struct drm_crtc **save_encoder_crtcs; |
| bool *save_crtc_enabled; |
| |
| bool fb_changed; |
| bool mode_changed; |
| 568,6 → 695,12 |
|---|
| return container_of(encoder, struct intel_digital_port, base.base); |
| } |
| |
| static inline struct intel_dp_mst_encoder * |
| enc_to_mst(struct drm_encoder *encoder) |
| { |
| return container_of(encoder, struct intel_dp_mst_encoder, base.base); |
| } |
| |
| static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) |
| { |
| return &enc_to_dig_port(encoder)->dp; |
| 592,13 → 725,26 |
|---|
| bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev, |
| enum transcoder pch_transcoder, |
| bool enable); |
| void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
| void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
| void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
| void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
| void hsw_pc8_disable_interrupts(struct drm_device *dev); |
| void hsw_pc8_restore_interrupts(struct drm_device *dev); |
| void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
| void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
| void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
| void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
| void gen8_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
| void gen8_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); |
| void intel_runtime_pm_disable_interrupts(struct drm_device *dev); |
| void intel_runtime_pm_restore_interrupts(struct drm_device *dev); |
| static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv) |
| { |
| /* |
| * We only use drm_irq_uninstall() at unload and VT switch, so |
| * this is the only thing we need to check. |
| */ |
| return !dev_priv->pm._irqs_disabled; |
| } |
| |
| int intel_get_crtc_scanline(struct intel_crtc *crtc); |
| void i9xx_check_fifo_underruns(struct drm_device *dev); |
| void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv); |
| |
| /* intel_crt.c */ |
| void intel_crt_init(struct drm_device *dev); |
| 617,10 → 763,7 |
|---|
| enum transcoder cpu_transcoder); |
| void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc); |
| void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc); |
| void intel_ddi_setup_hw_pll_state(struct drm_device *dev); |
| bool intel_ddi_pll_select(struct intel_crtc *crtc); |
| void intel_ddi_pll_enable(struct intel_crtc *crtc); |
| void intel_ddi_put_crtc_pll(struct drm_crtc *crtc); |
| void intel_ddi_set_pipe_settings(struct drm_crtc *crtc); |
| void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder); |
| bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector); |
| 628,6 → 771,10 |
|---|
| void intel_ddi_get_config(struct intel_encoder *encoder, |
| struct intel_crtc_config *pipe_config); |
| |
| void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder); |
| void intel_ddi_clock_get(struct intel_encoder *encoder, |
| struct intel_crtc_config *pipe_config); |
| void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state); |
| |
| /* intel_display.c */ |
| const char *intel_output_name(int output); |
| 634,10 → 781,36 |
|---|
| bool intel_has_pending_fb_unpin(struct drm_device *dev); |
| int intel_pch_rawclk(struct drm_device *dev); |
| void intel_mark_busy(struct drm_device *dev); |
| void intel_mark_fb_busy(struct drm_i915_gem_object *obj, |
| struct intel_ring_buffer *ring); |
| void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj, |
| struct intel_engine_cs *ring); |
| void intel_frontbuffer_flip_prepare(struct drm_device *dev, |
| unsigned frontbuffer_bits); |
| void intel_frontbuffer_flip_complete(struct drm_device *dev, |
| unsigned frontbuffer_bits); |
| void intel_frontbuffer_flush(struct drm_device *dev, |
| unsigned frontbuffer_bits); |
| /** |
| * intel_frontbuffer_flip - prepare frontbuffer flip |
| * @dev: DRM device |
| * @frontbuffer_bits: frontbuffer plane tracking bits |
| * |
| * This function gets called after scheduling a flip on @obj. This is for |
| * synchronous plane updates which will happen on the next vblank and which will |
| * not get delayed by pending gpu rendering. |
| * |
| * Can be called without any locks held. |
| */ |
| static inline |
| void intel_frontbuffer_flip(struct drm_device *dev, |
| unsigned frontbuffer_bits) |
| { |
| intel_frontbuffer_flush(dev, frontbuffer_bits); |
| } |
| |
| void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire); |
| void intel_mark_idle(struct drm_device *dev); |
| void intel_crtc_restore_mode(struct drm_crtc *crtc); |
| void intel_crtc_control(struct drm_crtc *crtc, bool enable); |
| void intel_crtc_update_dpms(struct drm_crtc *crtc); |
| void intel_encoder_destroy(struct drm_encoder *encoder); |
| void intel_connector_dpms(struct drm_connector *, int mode); |
| 662,21 → 835,23 |
|---|
| struct intel_digital_port *dport); |
| bool intel_get_load_detect_pipe(struct drm_connector *connector, |
| struct drm_display_mode *mode, |
| struct intel_load_detect_pipe *old); |
| struct intel_load_detect_pipe *old, |
| struct drm_modeset_acquire_ctx *ctx); |
| void intel_release_load_detect_pipe(struct drm_connector *connector, |
| struct intel_load_detect_pipe *old); |
| int intel_pin_and_fence_fb_obj(struct drm_device *dev, |
| struct drm_i915_gem_object *obj, |
| struct intel_ring_buffer *pipelined); |
| struct intel_engine_cs *pipelined); |
| void intel_unpin_fb_obj(struct drm_i915_gem_object *obj); |
| int intel_framebuffer_init(struct drm_device *dev, |
| struct intel_framebuffer *ifb, |
| struct drm_framebuffer * |
| __intel_framebuffer_create(struct drm_device *dev, |
| struct drm_mode_fb_cmd2 *mode_cmd, |
| struct drm_i915_gem_object *obj); |
| void intel_framebuffer_fini(struct intel_framebuffer *fb); |
| void intel_prepare_page_flip(struct drm_device *dev, int plane); |
| void intel_finish_page_flip(struct drm_device *dev, int pipe); |
| void intel_finish_page_flip_plane(struct drm_device *dev, int plane); |
| |
| /* shared dpll functions */ |
| struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc); |
| void assert_shared_dpll(struct drm_i915_private *dev_priv, |
| struct intel_shared_dpll *pll, |
| 683,6 → 858,10 |
|---|
| bool state); |
| #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true) |
| #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false) |
| struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc); |
| void intel_put_shared_dpll(struct intel_crtc *crtc); |
| |
| /* modesetting asserts */ |
| void assert_pll(struct drm_i915_private *dev_priv, |
| enum pipe pipe, bool state); |
| #define assert_pll_enabled(d, p) assert_pll(d, p, true) |
| 701,9 → 880,8 |
|---|
| unsigned int bpp, |
| unsigned int pitch); |
| void intel_display_handle_reset(struct drm_device *dev); |
| void hsw_enable_pc8_work(struct work_struct *__work); |
| void hsw_enable_package_c8(struct drm_i915_private *dev_priv); |
| void hsw_disable_package_c8(struct drm_i915_private *dev_priv); |
| void hsw_enable_pc8(struct drm_i915_private *dev_priv); |
| void hsw_disable_pc8(struct drm_i915_private *dev_priv); |
| void intel_dp_get_m_n(struct intel_crtc *crtc, |
| struct intel_crtc_config *pipe_config); |
| int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n); |
| 713,9 → 891,15 |
|---|
| bool intel_crtc_active(struct drm_crtc *crtc); |
| void hsw_enable_ips(struct intel_crtc *crtc); |
| void hsw_disable_ips(struct intel_crtc *crtc); |
| void intel_display_set_init_power(struct drm_device *dev, bool enable); |
| int valleyview_get_vco(struct drm_i915_private *dev_priv); |
| void intel_display_set_init_power(struct drm_i915_private *dev, bool enable); |
| enum intel_display_power_domain |
| intel_display_port_power_domain(struct intel_encoder *intel_encoder); |
| void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
| struct intel_crtc_config *pipe_config); |
| int intel_format_to_fourcc(int format); |
| void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc); |
| |
| |
| /* intel_dp.c */ |
| void intel_dp_init(struct drm_device *dev, int output_reg, enum port port); |
| bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
| 726,22 → 910,38 |
|---|
| void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode); |
| void intel_dp_encoder_destroy(struct drm_encoder *encoder); |
| void intel_dp_check_link_status(struct intel_dp *intel_dp); |
| int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc); |
| bool intel_dp_compute_config(struct intel_encoder *encoder, |
| struct intel_crtc_config *pipe_config); |
| bool intel_dp_is_edp(struct drm_device *dev, enum port port); |
| void ironlake_edp_backlight_on(struct intel_dp *intel_dp); |
| void ironlake_edp_backlight_off(struct intel_dp *intel_dp); |
| void ironlake_edp_panel_on(struct intel_dp *intel_dp); |
| void ironlake_edp_panel_off(struct intel_dp *intel_dp); |
| void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp); |
| void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); |
| bool intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, |
| bool long_hpd); |
| void intel_edp_backlight_on(struct intel_dp *intel_dp); |
| void intel_edp_backlight_off(struct intel_dp *intel_dp); |
| void intel_edp_panel_vdd_on(struct intel_dp *intel_dp); |
| void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder); |
| void intel_edp_panel_on(struct intel_dp *intel_dp); |
| void intel_edp_panel_off(struct intel_dp *intel_dp); |
| void intel_edp_psr_enable(struct intel_dp *intel_dp); |
| void intel_edp_psr_disable(struct intel_dp *intel_dp); |
| void intel_edp_psr_update(struct drm_device *dev); |
| void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate); |
| void intel_edp_psr_invalidate(struct drm_device *dev, |
| unsigned frontbuffer_bits); |
| void intel_edp_psr_flush(struct drm_device *dev, |
| unsigned frontbuffer_bits); |
| void intel_edp_psr_init(struct drm_device *dev); |
| |
| |
| int intel_dp_handle_hpd_irq(struct intel_digital_port *digport, bool long_hpd); |
| void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector); |
| void intel_dp_mst_suspend(struct drm_device *dev); |
| void intel_dp_mst_resume(struct drm_device *dev); |
| int intel_dp_max_link_bw(struct intel_dp *intel_dp); |
| void intel_dp_hot_plug(struct intel_encoder *intel_encoder); |
| /* intel_dp_mst.c */ |
| int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id); |
| void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port); |
| /* intel_dsi.c */ |
| bool intel_dsi_init(struct drm_device *dev); |
| void intel_dsi_init(struct drm_device *dev); |
| |
| |
| /* intel_dvo.c */ |
| 813,7 → 1013,8 |
|---|
| |
| /* intel_panel.c */ |
| int intel_panel_init(struct intel_panel *panel, |
| struct drm_display_mode *fixed_mode); |
| struct drm_display_mode *fixed_mode, |
| struct drm_display_mode *downclock_mode); |
| void intel_panel_fini(struct intel_panel *panel); |
| void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode, |
| struct drm_display_mode *adjusted_mode); |
| 823,8 → 1024,8 |
|---|
| void intel_gmch_panel_fitting(struct intel_crtc *crtc, |
| struct intel_crtc_config *pipe_config, |
| int fitting_mode); |
| void intel_panel_set_backlight(struct intel_connector *connector, u32 level, |
| u32 max); |
| void intel_panel_set_backlight_acpi(struct intel_connector *connector, |
| u32 level, u32 max); |
| int intel_panel_setup_backlight(struct drm_connector *connector); |
| void intel_panel_enable_backlight(struct intel_connector *connector); |
| void intel_panel_disable_backlight(struct intel_connector *connector); |
| 839,10 → 1040,13 |
|---|
| /* intel_pm.c */ |
| void intel_init_clock_gating(struct drm_device *dev); |
| void intel_suspend_hw(struct drm_device *dev); |
| int ilk_wm_max_level(const struct drm_device *dev); |
| void intel_update_watermarks(struct drm_crtc *crtc); |
| void intel_update_sprite_watermarks(struct drm_plane *plane, |
| struct drm_crtc *crtc, |
| uint32_t sprite_width, int pixel_size, |
| uint32_t sprite_width, |
| uint32_t sprite_height, |
| int pixel_size, |
| bool enabled, bool scaled); |
| void intel_init_pm(struct drm_device *dev); |
| void intel_pm_setup(struct drm_device *dev); |
| 850,20 → 1054,23 |
|---|
| void intel_update_fbc(struct drm_device *dev); |
| void intel_gpu_ips_init(struct drm_i915_private *dev_priv); |
| void intel_gpu_ips_teardown(void); |
| int intel_power_domains_init(struct drm_device *dev); |
| void intel_power_domains_remove(struct drm_device *dev); |
| bool intel_display_power_enabled(struct drm_device *dev, |
| int intel_power_domains_init(struct drm_i915_private *); |
| void intel_power_domains_remove(struct drm_i915_private *); |
| bool intel_display_power_enabled(struct drm_i915_private *dev_priv, |
| enum intel_display_power_domain domain); |
| bool intel_display_power_enabled_sw(struct drm_device *dev, |
| bool intel_display_power_enabled_unlocked(struct drm_i915_private *dev_priv, |
| enum intel_display_power_domain domain); |
| void intel_display_power_get(struct drm_device *dev, |
| void intel_display_power_get(struct drm_i915_private *dev_priv, |
| enum intel_display_power_domain domain); |
| void intel_display_power_put(struct drm_device *dev, |
| void intel_display_power_put(struct drm_i915_private *dev_priv, |
| enum intel_display_power_domain domain); |
| void intel_power_domains_init_hw(struct drm_device *dev); |
| void intel_set_power_well(struct drm_device *dev, bool enable); |
| void intel_power_domains_init_hw(struct drm_i915_private *dev_priv); |
| void intel_init_gt_powersave(struct drm_device *dev); |
| void intel_cleanup_gt_powersave(struct drm_device *dev); |
| void intel_enable_gt_powersave(struct drm_device *dev); |
| void intel_disable_gt_powersave(struct drm_device *dev); |
| void intel_suspend_gt_powersave(struct drm_device *dev); |
| void intel_reset_gt_powersave(struct drm_device *dev); |
| void ironlake_teardown_rc6(struct drm_device *dev); |
| void gen6_update_ring_freq(struct drm_device *dev); |
| void gen6_rps_idle(struct drm_i915_private *dev_priv); |
| 871,6 → 1078,7 |
|---|
| void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv); |
| void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv); |
| void intel_runtime_pm_get(struct drm_i915_private *dev_priv); |
| void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv); |
| void intel_runtime_pm_put(struct drm_i915_private *dev_priv); |
| void intel_init_runtime_pm(struct drm_i915_private *dev_priv); |
| void intel_fini_runtime_pm(struct drm_i915_private *dev_priv); |