| 103,26 → 103,8 |
|---|
| #define INTEL_OUTPUT_HDMI 6 |
| #define INTEL_OUTPUT_DISPLAYPORT 7 |
| #define INTEL_OUTPUT_EDP 8 |
| #define INTEL_OUTPUT_UNKNOWN 9 |
| |
| /* Intel Pipe Clone Bit */ |
| #define INTEL_HDMIB_CLONE_BIT 1 |
| #define INTEL_HDMIC_CLONE_BIT 2 |
| #define INTEL_HDMID_CLONE_BIT 3 |
| #define INTEL_HDMIE_CLONE_BIT 4 |
| #define INTEL_HDMIF_CLONE_BIT 5 |
| #define INTEL_SDVO_NON_TV_CLONE_BIT 6 |
| #define INTEL_SDVO_TV_CLONE_BIT 7 |
| #define INTEL_SDVO_LVDS_CLONE_BIT 8 |
| #define INTEL_ANALOG_CLONE_BIT 9 |
| #define INTEL_TV_CLONE_BIT 10 |
| #define INTEL_DP_B_CLONE_BIT 11 |
| #define INTEL_DP_C_CLONE_BIT 12 |
| #define INTEL_DP_D_CLONE_BIT 13 |
| #define INTEL_LVDS_CLONE_BIT 14 |
| #define INTEL_DVO_TMDS_CLONE_BIT 15 |
| #define INTEL_DVO_LVDS_CLONE_BIT 16 |
| #define INTEL_EDP_CLONE_BIT 17 |
| |
| #define INTEL_DVO_CHIP_NONE 0 |
| #define INTEL_DVO_CHIP_LVDS 1 |
| #define INTEL_DVO_CHIP_TMDS 2 |
| 191,6 → 173,11 |
|---|
| int crtc_mask; |
| }; |
| |
| struct intel_panel { |
| struct drm_display_mode *fixed_mode; |
| int fitting_mode; |
| }; |
| |
| struct intel_connector { |
| struct drm_connector base; |
| /* |
| 207,6 → 194,12 |
|---|
| /* Reads out the current hw, returning true if the connector is enabled |
| * and active (i.e. dpms ON state). */ |
| bool (*get_hw_state)(struct intel_connector *); |
| |
| /* Panel info for eDP and LVDS */ |
| struct intel_panel panel; |
| |
| /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */ |
| struct edid *edid; |
| }; |
| |
| struct intel_crtc { |
| 213,6 → 206,7 |
|---|
| struct drm_crtc base; |
| enum pipe pipe; |
| enum plane plane; |
| enum transcoder cpu_transcoder; |
| u8 lut_r[256], lut_g[256], lut_b[256]; |
| /* |
| * Whether the crtc and the connected output pipeline is active. Implies |
| 226,6 → 220,8 |
|---|
| struct intel_unpin_work *unpin_work; |
| int fdi_lanes; |
| |
| atomic_t unpin_work_count; |
| |
| /* Display surface base address adjustement for pageflips. Note that on |
| * gen4+ this only adjusts up to a tile, offsets within a tile are |
| * handled in the hw itself (with the TILEOFF register). */ |
| 240,6 → 236,7 |
|---|
| |
| /* We can share PLLs across outputs if the timings match */ |
| struct intel_pch_pll *pch_pll; |
| uint32_t ddi_pll_sel; |
| }; |
| |
| struct intel_plane { |
| 246,6 → 243,7 |
|---|
| struct drm_plane base; |
| enum pipe pipe; |
| struct drm_i915_gem_object *obj; |
| bool can_scale; |
| int max_downscale; |
| u32 lut_r[1024], lut_g[1024], lut_b[1024]; |
| void (*update_plane)(struct drm_plane *plane, |
| 345,10 → 343,8 |
|---|
| } __attribute__((packed)); |
| |
| struct intel_hdmi { |
| struct intel_encoder base; |
| u32 sdvox_reg; |
| int ddc_bus; |
| int ddi_port; |
| uint32_t color_range; |
| bool has_hdmi_sink; |
| bool has_audio; |
| 359,18 → 355,15 |
|---|
| struct drm_display_mode *adjusted_mode); |
| }; |
| |
| #define DP_RECEIVER_CAP_SIZE 0xf |
| #define DP_MAX_DOWNSTREAM_PORTS 0x10 |
| #define DP_LINK_CONFIGURATION_SIZE 9 |
| |
| struct intel_dp { |
| struct intel_encoder base; |
| uint32_t output_reg; |
| uint32_t DP; |
| uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]; |
| bool has_audio; |
| enum hdmi_force_audio force_audio; |
| enum port port; |
| uint32_t color_range; |
| uint8_t link_bw; |
| uint8_t lane_count; |
| 385,13 → 378,18 |
|---|
| int panel_power_cycle_delay; |
| int backlight_on_delay; |
| int backlight_off_delay; |
| struct drm_display_mode *panel_fixed_mode; /* for eDP */ |
| struct delayed_work panel_vdd_work; |
| bool want_panel_vdd; |
| struct edid *edid; /* cached EDID for eDP */ |
| int edid_mode_count; |
| struct intel_connector *attached_connector; |
| }; |
| |
| struct intel_digital_port { |
| struct intel_encoder base; |
| enum port port; |
| struct intel_dp dp; |
| struct intel_hdmi hdmi; |
| }; |
| |
| static inline struct drm_crtc * |
| intel_get_crtc_for_pipe(struct drm_device *dev, int pipe) |
| { |
| 408,11 → 406,14 |
|---|
| |
| struct intel_unpin_work { |
| struct work_struct work; |
| struct drm_device *dev; |
| struct drm_crtc *crtc; |
| struct drm_i915_gem_object *old_fb_obj; |
| struct drm_i915_gem_object *pending_flip_obj; |
| struct drm_pending_vblank_event *event; |
| int pending; |
| atomic_t pending; |
| #define INTEL_FLIP_INACTIVE 0 |
| #define INTEL_FLIP_PENDING 1 |
| #define INTEL_FLIP_COMPLETE 2 |
| bool enable_stall_check; |
| }; |
| |
| 423,6 → 424,8 |
|---|
| int interval; |
| }; |
| |
| int intel_pch_rawclk(struct drm_device *dev); |
| |
| int intel_connector_update_modes(struct drm_connector *connector, |
| struct edid *edid); |
| int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter); |
| 433,7 → 436,12 |
|---|
| extern void intel_crt_init(struct drm_device *dev); |
| extern void intel_hdmi_init(struct drm_device *dev, |
| int sdvox_reg, enum port port); |
| extern void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
| struct intel_connector *intel_connector); |
| extern struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder); |
| extern bool intel_hdmi_mode_fixup(struct drm_encoder *encoder, |
| const struct drm_display_mode *mode, |
| struct drm_display_mode *adjusted_mode); |
| extern void intel_dip_infoframe_csum(struct dip_infoframe *avi_if); |
| extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, |
| bool is_sdvob); |
| 446,10 → 454,27 |
|---|
| extern bool intel_lvds_init(struct drm_device *dev); |
| extern void intel_dp_init(struct drm_device *dev, int output_reg, |
| enum port port); |
| extern void intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
| struct intel_connector *intel_connector); |
| void |
| intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, |
| struct drm_display_mode *adjusted_mode); |
| extern void intel_dp_init_link_config(struct intel_dp *intel_dp); |
| extern void intel_dp_start_link_train(struct intel_dp *intel_dp); |
| extern void intel_dp_complete_link_train(struct intel_dp *intel_dp); |
| extern void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode); |
| extern void intel_dp_encoder_destroy(struct drm_encoder *encoder); |
| extern void intel_dp_check_link_status(struct intel_dp *intel_dp); |
| extern bool intel_dp_mode_fixup(struct drm_encoder *encoder, |
| const struct drm_display_mode *mode, |
| struct drm_display_mode *adjusted_mode); |
| extern bool intel_dpd_is_edp(struct drm_device *dev); |
| extern void ironlake_edp_backlight_on(struct intel_dp *intel_dp); |
| extern void ironlake_edp_backlight_off(struct intel_dp *intel_dp); |
| extern void ironlake_edp_panel_on(struct intel_dp *intel_dp); |
| extern void ironlake_edp_panel_off(struct intel_dp *intel_dp); |
| extern void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp); |
| extern void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); |
| extern void intel_edp_link_config(struct intel_encoder *, int *, int *); |
| extern int intel_edp_target_clock(struct intel_encoder *, |
| struct drm_display_mode *mode); |
| 459,6 → 484,10 |
|---|
| enum plane plane); |
| |
| /* intel_panel.c */ |
| extern int intel_panel_init(struct intel_panel *panel, |
| struct drm_display_mode *fixed_mode); |
| extern void intel_panel_fini(struct intel_panel *panel); |
| |
| extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode, |
| struct drm_display_mode *adjusted_mode); |
| extern void intel_pch_panel_fitting(struct drm_device *dev, |
| 467,7 → 496,7 |
|---|
| struct drm_display_mode *adjusted_mode); |
| extern u32 intel_panel_get_max_backlight(struct drm_device *dev); |
| extern void intel_panel_set_backlight(struct drm_device *dev, u32 level); |
| extern int intel_panel_setup_backlight(struct drm_device *dev); |
| extern int intel_panel_setup_backlight(struct drm_connector *connector); |
| extern void intel_panel_enable_backlight(struct drm_device *dev, |
| enum pipe pipe); |
| extern void intel_panel_disable_backlight(struct drm_device *dev); |
| 501,6 → 530,31 |
|---|
| return to_intel_connector(connector)->encoder; |
| } |
| |
| static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) |
| { |
| struct intel_digital_port *intel_dig_port = |
| container_of(encoder, struct intel_digital_port, base.base); |
| return &intel_dig_port->dp; |
| } |
| |
| static inline struct intel_digital_port * |
| enc_to_dig_port(struct drm_encoder *encoder) |
| { |
| return container_of(encoder, struct intel_digital_port, base.base); |
| } |
| |
| static inline struct intel_digital_port * |
| dp_to_dig_port(struct intel_dp *intel_dp) |
| { |
| return container_of(intel_dp, struct intel_digital_port, dp); |
| } |
| |
| static inline struct intel_digital_port * |
| hdmi_to_dig_port(struct intel_hdmi *intel_hdmi) |
| { |
| return container_of(intel_hdmi, struct intel_digital_port, hdmi); |
| } |
| |
| extern void intel_connector_attach_encoder(struct intel_connector *connector, |
| struct intel_encoder *encoder); |
| extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector); |
| 509,8 → 563,12 |
|---|
| struct drm_crtc *crtc); |
| int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
| struct drm_file *file_priv); |
| extern enum transcoder |
| intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
| enum pipe pipe); |
| extern void intel_wait_for_vblank(struct drm_device *dev, int pipe); |
| extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe); |
| extern int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp); |
| |
| struct intel_load_detect_pipe { |
| struct drm_framebuffer *release_fb; |
| 578,6 → 636,10 |
|---|
| extern void intel_update_linetime_watermarks(struct drm_device *dev, int pipe, |
| struct drm_display_mode *mode); |
| |
| extern unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y, |
| unsigned int bpp, |
| unsigned int pitch); |
| |
| extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data, |
| struct drm_file *file_priv); |
| extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data, |
| 601,12 → 663,22 |
|---|
| extern void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv); |
| extern void ironlake_teardown_rc6(struct drm_device *dev); |
| |
| extern void intel_enable_ddi(struct intel_encoder *encoder); |
| extern void intel_disable_ddi(struct intel_encoder *encoder); |
| extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder, |
| enum pipe *pipe); |
| extern void intel_ddi_mode_set(struct drm_encoder *encoder, |
| struct drm_display_mode *mode, |
| struct drm_display_mode *adjusted_mode); |
| extern int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv); |
| extern void intel_ddi_pll_init(struct drm_device *dev); |
| extern void intel_ddi_enable_pipe_func(struct drm_crtc *crtc); |
| extern void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, |
| enum transcoder cpu_transcoder); |
| extern void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc); |
| extern void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc); |
| extern void intel_ddi_setup_hw_pll_state(struct drm_device *dev); |
| extern bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock); |
| extern void intel_ddi_put_crtc_pll(struct drm_crtc *crtc); |
| extern void intel_ddi_set_pipe_settings(struct drm_crtc *crtc); |
| extern void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder); |
| extern bool |
| intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector); |
| extern void intel_ddi_fdi_disable(struct drm_crtc *crtc); |
| |
| #endif /* __INTEL_DRV_H__ */ |