898,6 → 898,9 |
plls->spll_refcount++; |
reg = SPLL_CTL; |
intel_crtc->ddi_pll_sel = PORT_CLK_SEL_SPLL; |
} else { |
DRM_ERROR("SPLL already in use\n"); |
return false; |
} |
|
WARN(I915_READ(reg) & SPLL_PLL_ENABLE, |
921,7 → 924,7 |
struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); |
enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; |
enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
int type = intel_encoder->type; |
uint32_t temp; |
|
928,7 → 931,7 |
if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { |
|
temp = TRANS_MSA_SYNC_CLK; |
switch (intel_crtc->bpp) { |
switch (intel_crtc->config.pipe_bpp) { |
case 18: |
temp |= TRANS_MSA_6_BPC; |
break; |
942,15 → 945,13 |
temp |= TRANS_MSA_12_BPC; |
break; |
default: |
temp |= TRANS_MSA_8_BPC; |
WARN(1, "%d bpp unsupported by DDI function\n", |
intel_crtc->bpp); |
BUG(); |
} |
I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); |
} |
} |
|
void intel_ddi_enable_pipe_func(struct drm_crtc *crtc) |
void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc) |
{ |
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); |
957,7 → 958,7 |
struct drm_encoder *encoder = &intel_encoder->base; |
struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
enum pipe pipe = intel_crtc->pipe; |
enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; |
enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
enum port port = intel_ddi_get_encoder_port(intel_encoder); |
int type = intel_encoder->type; |
uint32_t temp; |
966,7 → 967,7 |
temp = TRANS_DDI_FUNC_ENABLE; |
temp |= TRANS_DDI_SELECT_PORT(port); |
|
switch (intel_crtc->bpp) { |
switch (intel_crtc->config.pipe_bpp) { |
case 18: |
temp |= TRANS_DDI_BPC_6; |
break; |
980,8 → 981,7 |
temp |= TRANS_DDI_BPC_12; |
break; |
default: |
WARN(1, "%d bpp unsupported by transcoder DDI function\n", |
intel_crtc->bpp); |
BUG(); |
} |
|
if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
1150,7 → 1150,7 |
|
DRM_DEBUG_KMS("No pipe for ddi port %i found\n", port); |
|
return true; |
return false; |
} |
|
static uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private *dev_priv, |
1157,7 → 1157,7 |
enum pipe pipe) |
{ |
uint32_t temp, ret; |
enum port port; |
enum port port = I915_MAX_PORTS; |
enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
pipe); |
int i; |
1173,11 → 1173,17 |
port = i; |
} |
|
if (port == I915_MAX_PORTS) { |
WARN(1, "Pipe %c enabled on an unknown port\n", |
pipe_name(pipe)); |
ret = PORT_CLK_SEL_NONE; |
} else { |
ret = I915_READ(PORT_CLK_SEL(port)); |
DRM_DEBUG_KMS("Pipe %c connected to port %c using clock " |
"0x%08x\n", pipe_name(pipe), port_name(port), |
ret); |
} |
|
DRM_DEBUG_KMS("Pipe %c connected to port %c using clock 0x%08x\n", |
pipe_name(pipe), port_name(port), ret); |
|
return ret; |
} |
|
1217,7 → 1223,7 |
struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); |
enum port port = intel_ddi_get_encoder_port(intel_encoder); |
enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; |
enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
|
if (cpu_transcoder != TRANSCODER_EDP) |
I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), |
1227,7 → 1233,7 |
void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc) |
{ |
struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; |
enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; |
enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
|
if (cpu_transcoder != TRANSCODER_EDP) |
I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), |
1259,6 → 1265,8 |
intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
intel_dp_start_link_train(intel_dp); |
intel_dp_complete_link_train(intel_dp); |
if (port != PORT_A) |
intel_dp_stop_link_train(intel_dp); |
} |
} |
|
1320,6 → 1328,9 |
} else if (type == INTEL_OUTPUT_EDP) { |
struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
|
if (port == PORT_A) |
intel_dp_stop_link_train(intel_dp); |
|
ironlake_edp_backlight_on(intel_dp); |
} |
|
1341,15 → 1352,15 |
struct drm_i915_private *dev_priv = dev->dev_private; |
uint32_t tmp; |
|
tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); |
tmp &= ~((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << (pipe * 4)); |
I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); |
|
if (type == INTEL_OUTPUT_EDP) { |
struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
|
ironlake_edp_backlight_off(intel_dp); |
} |
|
tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); |
tmp &= ~((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << (pipe * 4)); |
I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); |
} |
|
int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv) |
1467,19 → 1478,17 |
intel_dp_encoder_destroy(encoder); |
} |
|
static bool intel_ddi_mode_fixup(struct drm_encoder *encoder, |
const struct drm_display_mode *mode, |
struct drm_display_mode *adjusted_mode) |
static bool intel_ddi_compute_config(struct intel_encoder *encoder, |
struct intel_crtc_config *pipe_config) |
{ |
struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
int type = intel_encoder->type; |
int type = encoder->type; |
|
WARN(type == INTEL_OUTPUT_UNKNOWN, "mode_fixup() on unknown output!\n"); |
WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n"); |
|
if (type == INTEL_OUTPUT_HDMI) |
return intel_hdmi_mode_fixup(encoder, mode, adjusted_mode); |
return intel_hdmi_compute_config(encoder, pipe_config); |
else |
return intel_dp_mode_fixup(encoder, mode, adjusted_mode); |
return intel_dp_compute_config(encoder, pipe_config); |
} |
|
static const struct drm_encoder_funcs intel_ddi_funcs = { |
1487,7 → 1496,6 |
}; |
|
static const struct drm_encoder_helper_funcs intel_ddi_helper_funcs = { |
.mode_fixup = intel_ddi_mode_fixup, |
.mode_set = intel_ddi_mode_set, |
}; |
|
1527,6 → 1535,7 |
DRM_MODE_ENCODER_TMDS); |
drm_encoder_helper_add(encoder, &intel_ddi_helper_funcs); |
|
intel_encoder->compute_config = intel_ddi_compute_config; |
intel_encoder->enable = intel_enable_ddi; |
intel_encoder->pre_enable = intel_ddi_pre_enable; |
intel_encoder->disable = intel_disable_ddi; |
1537,9 → 1546,7 |
intel_dig_port->port_reversal = I915_READ(DDI_BUF_CTL(port)) & |
DDI_BUF_PORT_REVERSAL; |
if (hdmi_connector) |
intel_dig_port->hdmi.sdvox_reg = DDI_BUF_CTL(port); |
else |
intel_dig_port->hdmi.sdvox_reg = 0; |
intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); |
intel_dig_port->dp.output_reg = DDI_BUF_CTL(port); |
|
intel_encoder->type = INTEL_OUTPUT_UNKNOWN; |