29,6 → 29,7 |
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
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#include <linux/slab.h> |
#include <linux/circ_buf.h> |
#include <drm/drmP.h> |
#include <drm/i915_drm.h> |
#include "i915_drv.h" |
1444,7 → 1445,7 |
*pin_mask |= BIT(i); |
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// if (!intel_hpd_pin_to_port(i, &port)) |
continue; |
// continue; |
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if (long_pulse_detect(port, dig_hotplug_reg)) |
*long_mask |= BIT(i); |
1594,8 → 1595,8 |
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static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe) |
{ |
// if (!drm_handle_vblank(dev, pipe)) |
// return false; |
if (!drm_handle_vblank(dev, pipe)) |
return false; |
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return true; |
} |
2281,6 → 2282,9 |
ret = IRQ_HANDLED; |
I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir); |
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if (pipe_iir & GEN8_PIPE_VBLANK && |
intel_pipe_handle_vblank(dev, pipe)) |
/* intel_check_page_flip(dev, pipe)*/; |
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if (INTEL_INFO(dev_priv)->gen >= 9) |
flip_done = pipe_iir & GEN9_PIPE_PLANE1_FLIP_DONE; |
2419,7 → 2423,7 |
atomic_inc(&dev_priv->gpu_error.reset_counter); |
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} else { |
atomic_set_mask(I915_WEDGED, &error->reset_counter); |
atomic_or(I915_WEDGED, &error->reset_counter); |
} |
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/* |
3009,6 → 3013,7 |
// return i915_handle_error(dev, true); |
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} |
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static void ibx_irq_reset(struct drm_device *dev) |
{ |
struct drm_i915_private *dev_priv = dev->dev_private; |
3933,6 → 3938,7 |
struct drm_i915_private *dev_priv = dev->dev_private; |
u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); |
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if (!intel_pipe_handle_vblank(dev, pipe)) |
return false; |
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if ((iir & flip_pending) == 0) |