| 110,7 → 110,10 |
|---|
| uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; |
| uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; |
| |
| if (INTEL_INFO(dev)->gen >= 5) { |
| if (INTEL_INFO(dev)->gen >= 6) { |
| swizzle_x = I915_BIT_6_SWIZZLE_NONE; |
| swizzle_y = I915_BIT_6_SWIZZLE_NONE; |
| } else if (IS_GEN5(dev)) { |
| /* On Ironlake whatever DRAM config, GPU always do |
| * same swizzling setup. |
| */ |
| 459,14 → 462,9 |
|---|
| void |
| i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj) |
| { |
| struct drm_device *dev = obj->base.dev; |
| drm_i915_private_t *dev_priv = dev->dev_private; |
| int page_count = obj->base.size >> PAGE_SHIFT; |
| int i; |
| |
| if (dev_priv->mm.bit_6_swizzle_x != I915_BIT_6_SWIZZLE_9_10_17) |
| return; |
| |
| if (obj->bit_17 == NULL) |
| return; |
| |
| 483,14 → 481,9 |
|---|
| void |
| i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj) |
| { |
| struct drm_device *dev = obj->base.dev; |
| drm_i915_private_t *dev_priv = dev->dev_private; |
| int page_count = obj->base.size >> PAGE_SHIFT; |
| int i; |
| |
| if (dev_priv->mm.bit_6_swizzle_x != I915_BIT_6_SWIZZLE_9_10_17) |
| return; |
| |
| if (obj->bit_17 == NULL) { |
| obj->bit_17 = kmalloc(BITS_TO_LONGS(page_count) * |
| sizeof(long), GFP_KERNEL); |