| 1177,6 → 1177,10 |
|---|
| /* Always safe in the mode setting case. */ |
| /* FIXME: do pre/post-mode set stuff in core KMS code */ |
| dev->vblank_disable_allowed = 1; |
| if (INTEL_INFO(dev)->num_pipes == 0) { |
| dev_priv->mm.suspended = 0; |
| return 0; |
| } |
| |
| ret = intel_fbdev_init(dev); |
| if (ret) |
| 1243,6 → 1247,22 |
|---|
| } |
| |
| /** |
| * intel_early_sanitize_regs - clean up BIOS state |
| * @dev: DRM device |
| * |
| * This function must be called before we do any I915_READ or I915_WRITE. Its |
| * purpose is to clean up any state left by the BIOS that may affect us when |
| * reading and/or writing registers. |
| */ |
| static void intel_early_sanitize_regs(struct drm_device *dev) |
| { |
| struct drm_i915_private *dev_priv = dev->dev_private; |
| |
| if (IS_HASWELL(dev)) |
| I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
| } |
| |
| /** |
| * i915_driver_load - setup chip and create an initial config |
| * @dev: DRM device |
| * @flags: startup flags |
| 1278,24 → 1298,6 |
|---|
| goto free_priv; |
| } |
| |
| ret = i915_gem_gtt_init(dev); |
| if (ret) |
| goto put_bridge; |
| |
| |
| pci_set_master(dev->pdev); |
| |
| /* overlay on gen2 is broken and can't address above 1G */ |
| |
| /* 965GM sometimes incorrectly writes to hardware status page (HWS) |
| * using 32bit addressing, overwriting memory if HWS is located |
| * above 4GB. |
| * |
| * The documentation also mentions an issue with undefined |
| * behaviour if any general state is accessed within a page above 4GB, |
| * which also needs to be handled carefully. |
| */ |
| |
| mmio_bar = IS_GEN2(dev) ? 1 : 0; |
| /* Before gen4, the registers and the GTT are behind different BARs. |
| * However, from gen4 onwards, the registers and the GTT are shared |
| 1313,13 → 1315,32 |
|---|
| if (!dev_priv->regs) { |
| DRM_ERROR("failed to map registers\n"); |
| ret = -EIO; |
| goto put_gmch; |
| goto put_bridge; |
| } |
| |
| intel_early_sanitize_regs(dev); |
| |
| ret = i915_gem_gtt_init(dev); |
| if (ret) |
| goto put_bridge; |
| |
| |
| pci_set_master(dev->pdev); |
| |
| /* overlay on gen2 is broken and can't address above 1G */ |
| |
| /* 965GM sometimes incorrectly writes to hardware status page (HWS) |
| * using 32bit addressing, overwriting memory if HWS is located |
| * above 4GB. |
| * |
| * The documentation also mentions an issue with undefined |
| * behaviour if any general state is accessed within a page above 4GB, |
| * which also needs to be handled carefully. |
| */ |
| |
| aperture_size = dev_priv->gtt.mappable_end; |
| |
| |
| |
| /* The i915 workqueue is primarily used for batched retirement of |
| * requests (and thus managing bo) once the task has been completed |
| * by the GPU. i915_gem_retire_requests() is called directly when we |
| 1376,12 → 1397,9 |
|---|
| mutex_init(&dev_priv->rps.hw_lock); |
| mutex_init(&dev_priv->modeset_restore_lock); |
| |
| if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) |
| dev_priv->num_pipe = 3; |
| else if (IS_MOBILE(dev) || !IS_GEN2(dev)) |
| dev_priv->num_pipe = 2; |
| else |
| dev_priv->num_pipe = 1; |
| dev_priv->num_plane = 1; |
| if (IS_VALLEYVIEW(dev)) |
| dev_priv->num_plane = 2; |
| |
| // ret = drm_vblank_init(dev, dev_priv->num_pipe); |
| // if (ret) |