| 407,14 → 407,14 |
|---|
| * LRI. |
| */ |
| struct drm_i915_reg_descriptor { |
| u32 addr; |
| i915_reg_t addr; |
| u32 mask; |
| u32 value; |
| }; |
| |
| /* Convenience macro for adding 32-bit registers. */ |
| #define REG32(address, ...) \ |
| { .addr = address, __VA_ARGS__ } |
| #define REG32(_reg, ...) \ |
| { .addr = (_reg), __VA_ARGS__ } |
| |
| /* |
| * Convenience macro for adding 64-bit registers. |
| 423,9 → 423,14 |
|---|
| * access commands only allow 32-bit accesses. Hence, we have to include |
| * entries for both halves of the 64-bit registers. |
| */ |
| #define REG64(addr) \ |
| REG32(addr), REG32(addr + sizeof(u32)) |
| #define REG64(_reg) \ |
| { .addr = _reg }, \ |
| { .addr = _reg ## _UDW } |
| |
| #define REG64_IDX(_reg, idx) \ |
| { .addr = _reg(idx) }, \ |
| { .addr = _reg ## _UDW(idx) } |
| |
| static const struct drm_i915_reg_descriptor gen7_render_regs[] = { |
| REG64(GPGPU_THREADS_DISPATCHED), |
| REG64(HS_INVOCATION_COUNT), |
| 451,14 → 456,14 |
|---|
| REG32(GEN7_GPGPU_DISPATCHDIMX), |
| REG32(GEN7_GPGPU_DISPATCHDIMY), |
| REG32(GEN7_GPGPU_DISPATCHDIMZ), |
| REG64(GEN7_SO_NUM_PRIMS_WRITTEN(0)), |
| REG64(GEN7_SO_NUM_PRIMS_WRITTEN(1)), |
| REG64(GEN7_SO_NUM_PRIMS_WRITTEN(2)), |
| REG64(GEN7_SO_NUM_PRIMS_WRITTEN(3)), |
| REG64(GEN7_SO_PRIM_STORAGE_NEEDED(0)), |
| REG64(GEN7_SO_PRIM_STORAGE_NEEDED(1)), |
| REG64(GEN7_SO_PRIM_STORAGE_NEEDED(2)), |
| REG64(GEN7_SO_PRIM_STORAGE_NEEDED(3)), |
| REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 0), |
| REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 1), |
| REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 2), |
| REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 3), |
| REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 0), |
| REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 1), |
| REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 2), |
| REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 3), |
| REG32(GEN7_SO_WRITE_OFFSET(0)), |
| REG32(GEN7_SO_WRITE_OFFSET(1)), |
| REG32(GEN7_SO_WRITE_OFFSET(2)), |
| 592,7 → 597,7 |
|---|
| bool ret = true; |
| |
| for (i = 0; i < reg_count; i++) { |
| u32 curr = reg_table[i].addr; |
| u32 curr = i915_mmio_reg_offset(reg_table[i].addr); |
| |
| if (curr < previous) { |
| DRM_ERROR("CMD: table not sorted ring=%d entry=%d reg=0x%08X prev=0x%08X\n", |
| 847,7 → 852,7 |
|---|
| int i; |
| |
| for (i = 0; i < count; i++) { |
| if (table[i].addr == addr) |
| if (i915_mmio_reg_offset(table[i].addr) == addr) |
| return &table[i]; |
| } |
| } |
| 1023,7 → 1028,7 |
|---|
| * to the register. Hence, limit OACONTROL writes to |
| * only MI_LOAD_REGISTER_IMM commands. |
| */ |
| if (reg_addr == OACONTROL) { |
| if (reg_addr == i915_mmio_reg_offset(OACONTROL)) { |
| if (desc->cmd.value == MI_LOAD_REGISTER_MEM) { |
| DRM_DEBUG_DRIVER("CMD: Rejected LRM to OACONTROL\n"); |
| return false; |