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Regard whitespace Rev 5059 → Rev 5060

/drivers/video/drm/i915/Gtt/agp.h
247,6 → 247,7
 
/* Chipset independent registers (from AGP Spec) */
#define AGP_APBASE 0x10
#define AGP_APERTURE_BAR 0
 
#define AGPSTAT 0x4
#define AGPCMD 0x8
/drivers/video/drm/i915/Gtt/intel-agp.h
55,8 → 55,8
#define INTEL_I860_ERRSTS 0xc8
 
/* Intel i810 registers */
#define I810_GMADDR 0x10
#define I810_MMADDR 0x14
#define I810_GMADR_BAR 0
#define I810_MMADR_BAR 1
#define I810_PTE_BASE 0x10000
#define I810_PTE_MAIN_UNCACHED 0x00000000
#define I810_PTE_LOCAL 0x00000002
113,9 → 113,9
#define INTEL_I850_ERRSTS 0xc8
 
/* intel 915G registers */
#define I915_GMADDR 0x18
#define I915_MMADDR 0x10
#define I915_PTEADDR 0x1C
#define I915_GMADR_BAR 2
#define I915_MMADR_BAR 0
#define I915_PTE_BAR 3
#define I915_GMCH_GMS_STOLEN_48M (0x6 << 4)
#define I915_GMCH_GMS_STOLEN_64M (0x7 << 4)
#define G33_GMCH_GMS_STOLEN_128M (0x8 << 4)
/drivers/video/drm/i915/Gtt/intel-gtt.c
91,7 → 91,7
struct pci_dev *pcidev; /* device one */
struct pci_dev *bridge_dev;
u8 __iomem *registers;
phys_addr_t gtt_bus_addr;
phys_addr_t gtt_phys_addr;
u32 PGETBL_save;
u32 __iomem *gtt; /* I915G */
bool clear_fake_agp; /* on first access via agp, fill with scratch */
399,9 → 399,8
 
static int intel_gtt_init(void)
{
u32 gma_addr;
u32 gtt_map_size;
int ret;
int ret, bar;
 
ret = intel_private.driver->setup();
if (ret != 0)
427,7 → 426,7
 
intel_private.gtt = NULL;
if (intel_private.gtt == NULL)
intel_private.gtt = ioremap(intel_private.gtt_bus_addr,
intel_private.gtt = ioremap(intel_private.gtt_phys_addr,
gtt_map_size);
if (intel_private.gtt == NULL) {
intel_private.driver->cleanup();
435,7 → 434,9
return -ENOMEM;
}
 
asm volatile("wbinvd":::"memory");
#if IS_ENABLED(CONFIG_AGP_INTEL)
global_cache_flush(); /* FIXME: ? */
#endif
 
intel_private.stolen_size = intel_gtt_stolen_size();
 
448,18 → 449,15
}
 
if (INTEL_GTT_GEN <= 2)
pci_read_config_dword(intel_private.pcidev, I810_GMADDR,
&gma_addr);
bar = I810_GMADR_BAR;
else
pci_read_config_dword(intel_private.pcidev, I915_GMADDR,
&gma_addr);
bar = I915_GMADR_BAR;
 
intel_private.gma_bus_addr = (gma_addr & PCI_BASE_ADDRESS_MEM_MASK);
 
 
intel_private.gma_bus_addr = pci_bus_address(intel_private.pcidev, bar);
return 0;
}
 
 
static void i830_write_entry(dma_addr_t addr, unsigned int entry,
unsigned int flags)
{
552,6 → 550,7
}
EXPORT_SYMBOL(intel_gtt_insert_sg_entries);
 
#if IS_ENABLED(CONFIG_AGP_INTEL)
static void intel_gtt_insert_pages(unsigned int first_entry,
unsigned int num_entries,
struct page **pages,
567,7 → 566,58
readl(intel_private.gtt+j-1);
}
 
static int intel_fake_agp_insert_entries(struct agp_memory *mem,
off_t pg_start, int type)
{
int ret = -EINVAL;
 
if (intel_private.clear_fake_agp) {
int start = intel_private.stolen_size / PAGE_SIZE;
int end = intel_private.gtt_mappable_entries;
intel_gtt_clear_range(start, end - start);
intel_private.clear_fake_agp = false;
}
 
if (INTEL_GTT_GEN == 1 && type == AGP_DCACHE_MEMORY)
return i810_insert_dcache_entries(mem, pg_start, type);
 
if (mem->page_count == 0)
goto out;
 
if (pg_start + mem->page_count > intel_private.gtt_total_entries)
goto out_err;
 
if (type != mem->type)
goto out_err;
 
if (!intel_private.driver->check_flags(type))
goto out_err;
 
if (!mem->is_flushed)
global_cache_flush();
 
if (intel_private.needs_dmar) {
struct sg_table st;
 
ret = intel_gtt_map_memory(mem->pages, mem->page_count, &st);
if (ret != 0)
return ret;
 
intel_gtt_insert_sg_entries(&st, pg_start, type);
mem->sg_list = st.sgl;
mem->num_sg = st.nents;
} else
intel_gtt_insert_pages(pg_start, mem->page_count, mem->pages,
type);
 
out:
ret = 0;
out_err:
mem->is_flushed = true;
return ret;
}
#endif
 
void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries)
{
unsigned int i;
693,13 → 743,11
 
static int i9xx_setup(void)
{
u32 reg_addr, gtt_addr;
phys_addr_t reg_addr;
int size = KB(512);
 
pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &reg_addr);
reg_addr = pci_resource_start(intel_private.pcidev, I915_MMADR_BAR);
 
reg_addr &= 0xfff80000;
 
intel_private.registers = ioremap(reg_addr, size);
if (!intel_private.registers)
return -ENOMEM;
706,15 → 754,14
 
switch (INTEL_GTT_GEN) {
case 3:
pci_read_config_dword(intel_private.pcidev,
I915_PTEADDR, &gtt_addr);
intel_private.gtt_bus_addr = gtt_addr;
intel_private.gtt_phys_addr =
pci_resource_start(intel_private.pcidev, I915_PTE_BAR);
break;
case 5:
intel_private.gtt_bus_addr = reg_addr + MB(2);
intel_private.gtt_phys_addr = reg_addr + MB(2);
break;
default:
intel_private.gtt_bus_addr = reg_addr + KB(512);
intel_private.gtt_phys_addr = reg_addr + KB(512);
break;
}
 
894,10 → 941,13
 
intel_private.refcount++;
 
#if IS_ENABLED(CONFIG_AGP_INTEL)
if (bridge) {
bridge->driver = &intel_fake_agp_driver;
bridge->dev_private_data = &intel_private;
bridge->dev = bridge_pdev;
}
#endif
 
intel_private.bridge_dev = bridge_pdev;