/drivers/video/drm/i915/Gtt/agp.h |
---|
0,0 → 1,294 |
/* |
* AGPGART |
* Copyright (C) 2004 Silicon Graphics, Inc. |
* Copyright (C) 2002-2004 Dave Jones |
* Copyright (C) 1999 Jeff Hartmann |
* Copyright (C) 1999 Precision Insight, Inc. |
* Copyright (C) 1999 Xi Graphics, Inc. |
* |
* Permission is hereby granted, free of charge, to any person obtaining a |
* copy of this software and associated documentation files (the "Software"), |
* to deal in the Software without restriction, including without limitation |
* the rights to use, copy, modify, merge, publish, distribute, sublicense, |
* and/or sell copies of the Software, and to permit persons to whom the |
* Software is furnished to do so, subject to the following conditions: |
* |
* The above copyright notice and this permission notice shall be included |
* in all copies or substantial portions of the Software. |
* |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
* JEFF HARTMANN, OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM, |
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR |
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE |
* OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
* |
*/ |
#ifndef _AGP_BACKEND_PRIV_H |
#define _AGP_BACKEND_PRIV_H 1 |
//#include <asm/agp.h> /* for flush_agp_cache() */ |
enum chipset_type { |
NOT_SUPPORTED, |
SUPPORTED, |
}; |
#define PFX "agpgart: " |
//#define AGP_DEBUG 1 |
#ifdef AGP_DEBUG |
#define DBG(x,y...) printk (KERN_DEBUG PFX "%s: " x "\n", __func__ , ## y) |
#else |
#define DBG(x,y...) do { } while (0) |
#endif |
extern struct agp_bridge_data *agp_bridge; |
enum aper_size_type { |
U8_APER_SIZE, |
U16_APER_SIZE, |
U32_APER_SIZE, |
LVL2_APER_SIZE, |
FIXED_APER_SIZE |
}; |
struct gatt_mask { |
unsigned long mask; |
u32 type; |
/* totally device specific, for integrated chipsets that |
* might have different types of memory masks. For other |
* devices this will probably be ignored */ |
}; |
#define AGP_PAGE_DESTROY_UNMAP 1 |
#define AGP_PAGE_DESTROY_FREE 2 |
struct aper_size_info_8 { |
int size; |
int num_entries; |
int page_order; |
u8 size_value; |
}; |
struct aper_size_info_16 { |
int size; |
int num_entries; |
int page_order; |
u16 size_value; |
}; |
struct aper_size_info_32 { |
int size; |
int num_entries; |
int page_order; |
u32 size_value; |
}; |
struct aper_size_info_lvl2 { |
int size; |
int num_entries; |
u32 size_value; |
}; |
struct aper_size_info_fixed { |
int size; |
int num_entries; |
int page_order; |
}; |
struct agp_bridge_driver { |
struct module *owner; |
const void *aperture_sizes; |
int num_aperture_sizes; |
enum aper_size_type size_type; |
bool cant_use_aperture; |
bool needs_scratch_page; |
const struct gatt_mask *masks; |
int (*fetch_size)(void); |
int (*configure)(void); |
void (*agp_enable)(struct agp_bridge_data *, u32); |
void (*cleanup)(void); |
void (*tlb_flush)(struct agp_memory *); |
unsigned long (*mask_memory)(struct agp_bridge_data *, dma_addr_t, int); |
void (*cache_flush)(void); |
int (*create_gatt_table)(struct agp_bridge_data *); |
int (*free_gatt_table)(struct agp_bridge_data *); |
int (*insert_memory)(struct agp_memory *, off_t, int); |
int (*remove_memory)(struct agp_memory *, off_t, int); |
struct agp_memory *(*alloc_by_type) (size_t, int); |
void (*free_by_type)(struct agp_memory *); |
struct page *(*agp_alloc_page)(struct agp_bridge_data *); |
int (*agp_alloc_pages)(struct agp_bridge_data *, struct agp_memory *, size_t); |
void (*agp_destroy_page)(struct page *, int flags); |
void (*agp_destroy_pages)(struct agp_memory *); |
int (*agp_type_to_mask_type) (struct agp_bridge_data *, int); |
}; |
struct agp_bridge_data { |
const struct agp_version *version; |
const struct agp_bridge_driver *driver; |
const struct vm_operations_struct *vm_ops; |
void *previous_size; |
void *current_size; |
void *dev_private_data; |
struct pci_dev *dev; |
u32 __iomem *gatt_table; |
u32 *gatt_table_real; |
unsigned long scratch_page; |
struct page *scratch_page_page; |
dma_addr_t scratch_page_dma; |
unsigned long gart_bus_addr; |
unsigned long gatt_bus_addr; |
u32 mode; |
enum chipset_type type; |
unsigned long *key_list; |
atomic_t current_memory_agp; |
atomic_t agp_in_use; |
int max_memory_agp; /* in number of pages */ |
int aperture_size_idx; |
int capndx; |
int flags; |
char major_version; |
char minor_version; |
struct list_head list; |
u32 apbase_config; |
/* list of agp_memory mapped to the aperture */ |
struct list_head mapped_list; |
spinlock_t mapped_lock; |
}; |
#define KB(x) ((x) * 1024) |
#define MB(x) (KB (KB (x))) |
#define GB(x) (MB (KB (x))) |
#define A_SIZE_8(x) ((struct aper_size_info_8 *) x) |
#define A_SIZE_16(x) ((struct aper_size_info_16 *) x) |
#define A_SIZE_32(x) ((struct aper_size_info_32 *) x) |
#define A_SIZE_LVL2(x) ((struct aper_size_info_lvl2 *) x) |
#define A_SIZE_FIX(x) ((struct aper_size_info_fixed *) x) |
#define A_IDX8(bridge) (A_SIZE_8((bridge)->driver->aperture_sizes) + i) |
#define A_IDX16(bridge) (A_SIZE_16((bridge)->driver->aperture_sizes) + i) |
#define A_IDX32(bridge) (A_SIZE_32((bridge)->driver->aperture_sizes) + i) |
#define MAXKEY (4096 * 32) |
#define PGE_EMPTY(b, p) (!(p) || (p) == (unsigned long) (b)->scratch_page) |
struct agp_device_ids { |
unsigned short device_id; /* first, to make table easier to read */ |
enum chipset_type chipset; |
const char *chipset_name; |
int (*chipset_setup) (struct pci_dev *pdev); /* used to override generic */ |
}; |
/* Driver registration */ |
struct agp_bridge_data *agp_alloc_bridge(void); |
void agp_put_bridge(struct agp_bridge_data *bridge); |
int agp_add_bridge(struct agp_bridge_data *bridge); |
void agp_remove_bridge(struct agp_bridge_data *bridge); |
/* Frontend routines. */ |
int agp_frontend_initialize(void); |
void agp_frontend_cleanup(void); |
/* Generic routines. */ |
void agp_generic_enable(struct agp_bridge_data *bridge, u32 mode); |
int agp_generic_create_gatt_table(struct agp_bridge_data *bridge); |
int agp_generic_free_gatt_table(struct agp_bridge_data *bridge); |
struct agp_memory *agp_create_memory(int scratch_pages); |
int agp_generic_insert_memory(struct agp_memory *mem, off_t pg_start, int type); |
int agp_generic_remove_memory(struct agp_memory *mem, off_t pg_start, int type); |
struct agp_memory *agp_generic_alloc_by_type(size_t page_count, int type); |
void agp_generic_free_by_type(struct agp_memory *curr); |
struct page *agp_generic_alloc_page(struct agp_bridge_data *bridge); |
int agp_generic_alloc_pages(struct agp_bridge_data *agp_bridge, |
struct agp_memory *memory, size_t page_count); |
void agp_generic_destroy_page(struct page *page, int flags); |
void agp_generic_destroy_pages(struct agp_memory *memory); |
void agp_free_key(int key); |
int agp_num_entries(void); |
u32 agp_collect_device_status(struct agp_bridge_data *bridge, u32 mode, u32 command); |
void agp_device_command(u32 command, bool agp_v3); |
int agp_3_5_enable(struct agp_bridge_data *bridge); |
void global_cache_flush(void); |
void get_agp_version(struct agp_bridge_data *bridge); |
unsigned long agp_generic_mask_memory(struct agp_bridge_data *bridge, |
dma_addr_t phys, int type); |
int agp_generic_type_to_mask_type(struct agp_bridge_data *bridge, |
int type); |
struct agp_bridge_data *agp_generic_find_bridge(struct pci_dev *pdev); |
/* generic functions for user-populated AGP memory types */ |
struct agp_memory *agp_generic_alloc_user(size_t page_count, int type); |
void agp_alloc_page_array(size_t size, struct agp_memory *mem); |
void agp_free_page_array(struct agp_memory *mem); |
/* generic routines for agp>=3 */ |
int agp3_generic_fetch_size(void); |
void agp3_generic_tlbflush(struct agp_memory *mem); |
int agp3_generic_configure(void); |
void agp3_generic_cleanup(void); |
/* aperture sizes have been standardised since v3 */ |
#define AGP_GENERIC_SIZES_ENTRIES 11 |
extern const struct aper_size_info_16 agp3_generic_sizes[]; |
extern int agp_off; |
extern int agp_try_unsupported_boot; |
long compat_agp_ioctl(struct file *file, unsigned int cmd, unsigned long arg); |
/* Chipset independent registers (from AGP Spec) */ |
#define AGP_APBASE 0x10 |
#define AGPSTAT 0x4 |
#define AGPCMD 0x8 |
#define AGPNISTAT 0xc |
#define AGPCTRL 0x10 |
#define AGPAPSIZE 0x14 |
#define AGPNEPG 0x16 |
#define AGPGARTLO 0x18 |
#define AGPGARTHI 0x1c |
#define AGPNICMD 0x20 |
#define AGP_MAJOR_VERSION_SHIFT (20) |
#define AGP_MINOR_VERSION_SHIFT (16) |
#define AGPSTAT_RQ_DEPTH (0xff000000) |
#define AGPSTAT_RQ_DEPTH_SHIFT 24 |
#define AGPSTAT_CAL_MASK (1<<12|1<<11|1<<10) |
#define AGPSTAT_ARQSZ (1<<15|1<<14|1<<13) |
#define AGPSTAT_ARQSZ_SHIFT 13 |
#define AGPSTAT_SBA (1<<9) |
#define AGPSTAT_AGP_ENABLE (1<<8) |
#define AGPSTAT_FW (1<<4) |
#define AGPSTAT_MODE_3_0 (1<<3) |
#define AGPSTAT2_1X (1<<0) |
#define AGPSTAT2_2X (1<<1) |
#define AGPSTAT2_4X (1<<2) |
#define AGPSTAT3_RSVD (1<<2) |
#define AGPSTAT3_8X (1<<1) |
#define AGPSTAT3_4X (1) |
#define AGPCTRL_APERENB (1<<8) |
#define AGPCTRL_GTLBEN (1<<7) |
#define AGP2_RESERVED_MASK 0x00fffcc8 |
#define AGP3_RESERVED_MASK 0x00ff00c4 |
#define AGP_ERRATA_FASTWRITES 1<<0 |
#define AGP_ERRATA_SBA 1<<1 |
#define AGP_ERRATA_1X 1<<2 |
#endif /* _AGP_BACKEND_PRIV_H */ |
/drivers/video/drm/i915/Gtt/intel-agp.c |
---|
0,0 → 1,106 |
/* |
* Intel AGPGART routines. |
*/ |
#include <linux/kernel.h> |
#include <linux/module.h> |
#include <linux/mod_devicetable.h> |
#include <errno-base.h> |
#include <linux/pci.h> |
//#include <linux/agp_backend.h> |
//#include <asm/smp.h> |
#include <linux/spinlock.h> |
#include "agp.h" |
#include "intel-agp.h" |
#include <syscall.h> |
#define __devinit |
#define PCI_VENDOR_ID_INTEL 0x8086 |
int intel_gmch_probe(struct pci_dev *pdev, |
struct agp_bridge_data *bridge); |
int intel_agp_enabled; |
struct agp_bridge_data *agp_alloc_bridge(void) |
{ |
struct agp_bridge_data *bridge; |
bridge = kzalloc(sizeof(*bridge), GFP_KERNEL); |
if (!bridge) |
return NULL; |
atomic_set(&bridge->agp_in_use, 0); |
atomic_set(&bridge->current_memory_agp, 0); |
// if (list_empty(&agp_bridges)) |
// agp_bridge = bridge; |
return bridge; |
} |
static int __devinit agp_intel_probe(struct pci_dev *pdev, |
const struct pci_device_id *ent) |
{ |
struct agp_bridge_data *bridge; |
u8 cap_ptr = 0; |
int err = -ENODEV; |
cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); |
bridge = agp_alloc_bridge(); |
if (!bridge) |
return -ENOMEM; |
bridge->capndx = cap_ptr; |
if (intel_gmch_probe(pdev, bridge)) |
{ |
// pci_set_drvdata(pdev, bridge); |
// err = agp_add_bridge(bridge); |
// if (!err) |
intel_agp_enabled = 1; |
err = 0; |
} |
return err; |
} |
static struct pci_device_id agp_intel_pci_table[] = { |
#define ID(x) \ |
{ \ |
.class = (PCI_CLASS_BRIDGE_HOST << 8), \ |
.class_mask = ~0, \ |
.vendor = PCI_VENDOR_ID_INTEL, \ |
.device = x, \ |
.subvendor = PCI_ANY_ID, \ |
.subdevice = PCI_ANY_ID, \ |
} |
ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB), |
ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB), |
ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB), |
{ } |
}; |
static pci_dev_t agp_device; |
int init_agp(void) |
{ |
const struct pci_device_id *ent; |
ent = find_pci_device(&agp_device, agp_intel_pci_table); |
if( unlikely(ent == NULL) ) |
{ |
dbgprintf("host controller not found\n"); |
return -ENODEV; |
}; |
return agp_intel_probe(&agp_device.pci_dev, ent); |
} |
/drivers/video/drm/i915/Gtt/intel-agp.h |
---|
0,0 → 1,241 |
/* |
* Common Intel AGPGART and GTT definitions. |
*/ |
#ifndef _INTEL_AGP_H |
#define _INTEL_AGP_H |
/* Intel registers */ |
#define INTEL_APSIZE 0xb4 |
#define INTEL_ATTBASE 0xb8 |
#define INTEL_AGPCTRL 0xb0 |
#define INTEL_NBXCFG 0x50 |
#define INTEL_ERRSTS 0x91 |
/* Intel i830 registers */ |
#define I830_GMCH_CTRL 0x52 |
#define I830_GMCH_ENABLED 0x4 |
#define I830_GMCH_MEM_MASK 0x1 |
#define I830_GMCH_MEM_64M 0x1 |
#define I830_GMCH_MEM_128M 0 |
#define I830_GMCH_GMS_MASK 0x70 |
#define I830_GMCH_GMS_DISABLED 0x00 |
#define I830_GMCH_GMS_LOCAL 0x10 |
#define I830_GMCH_GMS_STOLEN_512 0x20 |
#define I830_GMCH_GMS_STOLEN_1024 0x30 |
#define I830_GMCH_GMS_STOLEN_8192 0x40 |
#define I830_RDRAM_CHANNEL_TYPE 0x03010 |
#define I830_RDRAM_ND(x) (((x) & 0x20) >> 5) |
#define I830_RDRAM_DDT(x) (((x) & 0x18) >> 3) |
/* This one is for I830MP w. an external graphic card */ |
#define INTEL_I830_ERRSTS 0x92 |
/* Intel 855GM/852GM registers */ |
#define I855_GMCH_GMS_MASK 0xF0 |
#define I855_GMCH_GMS_STOLEN_0M 0x0 |
#define I855_GMCH_GMS_STOLEN_1M (0x1 << 4) |
#define I855_GMCH_GMS_STOLEN_4M (0x2 << 4) |
#define I855_GMCH_GMS_STOLEN_8M (0x3 << 4) |
#define I855_GMCH_GMS_STOLEN_16M (0x4 << 4) |
#define I855_GMCH_GMS_STOLEN_32M (0x5 << 4) |
#define I85X_CAPID 0x44 |
#define I85X_VARIANT_MASK 0x7 |
#define I85X_VARIANT_SHIFT 5 |
#define I855_GME 0x0 |
#define I855_GM 0x4 |
#define I852_GME 0x2 |
#define I852_GM 0x5 |
/* Intel i845 registers */ |
#define INTEL_I845_AGPM 0x51 |
#define INTEL_I845_ERRSTS 0xc8 |
/* Intel i860 registers */ |
#define INTEL_I860_MCHCFG 0x50 |
#define INTEL_I860_ERRSTS 0xc8 |
/* Intel i810 registers */ |
#define I810_GMADDR 0x10 |
#define I810_MMADDR 0x14 |
#define I810_PTE_BASE 0x10000 |
#define I810_PTE_MAIN_UNCACHED 0x00000000 |
#define I810_PTE_LOCAL 0x00000002 |
#define I810_PTE_VALID 0x00000001 |
#define I830_PTE_SYSTEM_CACHED 0x00000006 |
/* GT PTE cache control fields */ |
#define GEN6_PTE_UNCACHED 0x00000002 |
#define GEN6_PTE_LLC 0x00000004 |
#define GEN6_PTE_LLC_MLC 0x00000006 |
#define GEN6_PTE_GFDT 0x00000008 |
#define I810_SMRAM_MISCC 0x70 |
#define I810_GFX_MEM_WIN_SIZE 0x00010000 |
#define I810_GFX_MEM_WIN_32M 0x00010000 |
#define I810_GMS 0x000000c0 |
#define I810_GMS_DISABLE 0x00000000 |
#define I810_PGETBL_CTL 0x2020 |
#define I810_PGETBL_ENABLED 0x00000001 |
/* Note: PGETBL_CTL2 has a different offset on G33. */ |
#define I965_PGETBL_CTL2 0x20c4 |
#define I965_PGETBL_SIZE_MASK 0x0000000e |
#define I965_PGETBL_SIZE_512KB (0 << 1) |
#define I965_PGETBL_SIZE_256KB (1 << 1) |
#define I965_PGETBL_SIZE_128KB (2 << 1) |
#define I965_PGETBL_SIZE_1MB (3 << 1) |
#define I965_PGETBL_SIZE_2MB (4 << 1) |
#define I965_PGETBL_SIZE_1_5MB (5 << 1) |
#define G33_GMCH_SIZE_MASK (3 << 8) |
#define G33_GMCH_SIZE_1M (1 << 8) |
#define G33_GMCH_SIZE_2M (2 << 8) |
#define G4x_GMCH_SIZE_MASK (0xf << 8) |
#define G4x_GMCH_SIZE_1M (0x1 << 8) |
#define G4x_GMCH_SIZE_2M (0x3 << 8) |
#define G4x_GMCH_SIZE_VT_EN (0x8 << 8) |
#define G4x_GMCH_SIZE_VT_1M (G4x_GMCH_SIZE_1M | G4x_GMCH_SIZE_VT_EN) |
#define G4x_GMCH_SIZE_VT_1_5M ((0x2 << 8) | G4x_GMCH_SIZE_VT_EN) |
#define G4x_GMCH_SIZE_VT_2M (G4x_GMCH_SIZE_2M | G4x_GMCH_SIZE_VT_EN) |
#define GFX_FLSH_CNTL 0x2170 /* 915+ */ |
#define I810_DRAM_CTL 0x3000 |
#define I810_DRAM_ROW_0 0x00000001 |
#define I810_DRAM_ROW_0_SDRAM 0x00000001 |
/* Intel 815 register */ |
#define INTEL_815_APCONT 0x51 |
#define INTEL_815_ATTBASE_MASK ~0x1FFFFFFF |
/* Intel i820 registers */ |
#define INTEL_I820_RDCR 0x51 |
#define INTEL_I820_ERRSTS 0xc8 |
/* Intel i840 registers */ |
#define INTEL_I840_MCHCFG 0x50 |
#define INTEL_I840_ERRSTS 0xc8 |
/* Intel i850 registers */ |
#define INTEL_I850_MCHCFG 0x50 |
#define INTEL_I850_ERRSTS 0xc8 |
/* intel 915G registers */ |
#define I915_GMADDR 0x18 |
#define I915_MMADDR 0x10 |
#define I915_PTEADDR 0x1C |
#define I915_GMCH_GMS_STOLEN_48M (0x6 << 4) |
#define I915_GMCH_GMS_STOLEN_64M (0x7 << 4) |
#define G33_GMCH_GMS_STOLEN_128M (0x8 << 4) |
#define G33_GMCH_GMS_STOLEN_256M (0x9 << 4) |
#define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4) |
#define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4) |
#define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4) |
#define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4) |
#define I915_IFPADDR 0x60 |
#define I830_HIC 0x70 |
/* Intel 965G registers */ |
#define I965_MSAC 0x62 |
#define I965_IFPADDR 0x70 |
/* Intel 7505 registers */ |
#define INTEL_I7505_APSIZE 0x74 |
#define INTEL_I7505_NCAPID 0x60 |
#define INTEL_I7505_NISTAT 0x6c |
#define INTEL_I7505_ATTBASE 0x78 |
#define INTEL_I7505_ERRSTS 0x42 |
#define INTEL_I7505_AGPCTRL 0x70 |
#define INTEL_I7505_MCHCFG 0x50 |
#define SNB_GMCH_CTRL 0x50 |
#define SNB_GMCH_GMS_STOLEN_MASK 0xF8 |
#define SNB_GMCH_GMS_STOLEN_32M (1 << 3) |
#define SNB_GMCH_GMS_STOLEN_64M (2 << 3) |
#define SNB_GMCH_GMS_STOLEN_96M (3 << 3) |
#define SNB_GMCH_GMS_STOLEN_128M (4 << 3) |
#define SNB_GMCH_GMS_STOLEN_160M (5 << 3) |
#define SNB_GMCH_GMS_STOLEN_192M (6 << 3) |
#define SNB_GMCH_GMS_STOLEN_224M (7 << 3) |
#define SNB_GMCH_GMS_STOLEN_256M (8 << 3) |
#define SNB_GMCH_GMS_STOLEN_288M (9 << 3) |
#define SNB_GMCH_GMS_STOLEN_320M (0xa << 3) |
#define SNB_GMCH_GMS_STOLEN_352M (0xb << 3) |
#define SNB_GMCH_GMS_STOLEN_384M (0xc << 3) |
#define SNB_GMCH_GMS_STOLEN_416M (0xd << 3) |
#define SNB_GMCH_GMS_STOLEN_448M (0xe << 3) |
#define SNB_GMCH_GMS_STOLEN_480M (0xf << 3) |
#define SNB_GMCH_GMS_STOLEN_512M (0x10 << 3) |
#define SNB_GTT_SIZE_0M (0 << 8) |
#define SNB_GTT_SIZE_1M (1 << 8) |
#define SNB_GTT_SIZE_2M (2 << 8) |
#define SNB_GTT_SIZE_MASK (3 << 8) |
/* pci devices ids */ |
#define PCI_DEVICE_ID_INTEL_E7221_HB 0x2588 |
#define PCI_DEVICE_ID_INTEL_E7221_IG 0x258a |
#define PCI_DEVICE_ID_INTEL_82946GZ_HB 0x2970 |
#define PCI_DEVICE_ID_INTEL_82946GZ_IG 0x2972 |
#define PCI_DEVICE_ID_INTEL_82G35_HB 0x2980 |
#define PCI_DEVICE_ID_INTEL_82G35_IG 0x2982 |
#define PCI_DEVICE_ID_INTEL_82965Q_HB 0x2990 |
#define PCI_DEVICE_ID_INTEL_82965Q_IG 0x2992 |
#define PCI_DEVICE_ID_INTEL_82965G_HB 0x29A0 |
#define PCI_DEVICE_ID_INTEL_82965G_IG 0x29A2 |
#define PCI_DEVICE_ID_INTEL_82965GM_HB 0x2A00 |
#define PCI_DEVICE_ID_INTEL_82965GM_IG 0x2A02 |
#define PCI_DEVICE_ID_INTEL_82965GME_HB 0x2A10 |
#define PCI_DEVICE_ID_INTEL_82965GME_IG 0x2A12 |
#define PCI_DEVICE_ID_INTEL_82945GME_HB 0x27AC |
#define PCI_DEVICE_ID_INTEL_82945GME_IG 0x27AE |
#define PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB 0xA010 |
#define PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG 0xA011 |
#define PCI_DEVICE_ID_INTEL_PINEVIEW_HB 0xA000 |
#define PCI_DEVICE_ID_INTEL_PINEVIEW_IG 0xA001 |
#define PCI_DEVICE_ID_INTEL_G33_HB 0x29C0 |
#define PCI_DEVICE_ID_INTEL_G33_IG 0x29C2 |
#define PCI_DEVICE_ID_INTEL_Q35_HB 0x29B0 |
#define PCI_DEVICE_ID_INTEL_Q35_IG 0x29B2 |
#define PCI_DEVICE_ID_INTEL_Q33_HB 0x29D0 |
#define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2 |
#define PCI_DEVICE_ID_INTEL_B43_HB 0x2E40 |
#define PCI_DEVICE_ID_INTEL_B43_IG 0x2E42 |
#define PCI_DEVICE_ID_INTEL_B43_1_HB 0x2E90 |
#define PCI_DEVICE_ID_INTEL_B43_1_IG 0x2E92 |
#define PCI_DEVICE_ID_INTEL_GM45_HB 0x2A40 |
#define PCI_DEVICE_ID_INTEL_GM45_IG 0x2A42 |
#define PCI_DEVICE_ID_INTEL_EAGLELAKE_HB 0x2E00 |
#define PCI_DEVICE_ID_INTEL_EAGLELAKE_IG 0x2E02 |
#define PCI_DEVICE_ID_INTEL_Q45_HB 0x2E10 |
#define PCI_DEVICE_ID_INTEL_Q45_IG 0x2E12 |
#define PCI_DEVICE_ID_INTEL_G45_HB 0x2E20 |
#define PCI_DEVICE_ID_INTEL_G45_IG 0x2E22 |
#define PCI_DEVICE_ID_INTEL_G41_HB 0x2E30 |
#define PCI_DEVICE_ID_INTEL_G41_IG 0x2E32 |
#define PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB 0x0040 |
#define PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG 0x0042 |
#define PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB 0x0044 |
#define PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB 0x0062 |
#define PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB 0x006a |
#define PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG 0x0046 |
#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB 0x0100 /* Desktop */ |
#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG 0x0102 |
#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG 0x0112 |
#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG 0x0122 |
#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB 0x0104 /* Mobile */ |
#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG 0x0106 |
#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG 0x0116 |
#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG 0x0126 |
#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB 0x0108 /* Server */ |
#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG 0x010A |
#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_HB 0x0150 /* Desktop */ |
#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT1_IG 0x0152 |
#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT2_IG 0x0162 |
#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_HB 0x0154 /* Mobile */ |
#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT1_IG 0x0156 |
#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT2_IG 0x0166 |
#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_HB 0x0158 /* Server */ |
#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT1_IG 0x015A |
int intel_gmch_probe(struct pci_dev *pdev, |
struct agp_bridge_data *bridge); |
void intel_gmch_remove(struct pci_dev *pdev); |
#endif |
/drivers/video/drm/i915/Gtt/intel-gtt.c |
---|
0,0 → 1,802 |
/* |
* Intel GTT (Graphics Translation Table) routines |
* |
* Caveat: This driver implements the linux agp interface, but this is far from |
* a agp driver! GTT support ended up here for purely historical reasons: The |
* old userspace intel graphics drivers needed an interface to map memory into |
* the GTT. And the drm provides a default interface for graphic devices sitting |
* on an agp port. So it made sense to fake the GTT support as an agp port to |
* avoid having to create a new api. |
* |
* With gem this does not make much sense anymore, just needlessly complicates |
* the code. But as long as the old graphics stack is still support, it's stuck |
* here. |
* |
* /fairy-tale-mode off |
*/ |
#include <linux/module.h> |
#include <errno-base.h> |
#include <linux/pci.h> |
#include <linux/kernel.h> |
//#include <linux/pagemap.h> |
//#include <linux/agp_backend.h> |
//#include <asm/smp.h> |
#include <linux/spinlock.h> |
#include "agp.h" |
#include "intel-agp.h" |
#include "intel-gtt.h" |
#include <syscall.h> |
struct pci_dev * |
pci_get_device(unsigned int vendor, unsigned int device, struct pci_dev *from); |
static bool intel_enable_gtt(void); |
#define PG_SW 0x003 |
#define PG_NOCACHE 0x018 |
#define PCI_VENDOR_ID_INTEL 0x8086 |
#define PCI_DEVICE_ID_INTEL_82830_HB 0x3575 |
#define PCI_DEVICE_ID_INTEL_82845G_HB 0x2560 |
#define AGP_NORMAL_MEMORY 0 |
#define AGP_USER_TYPES (1 << 16) |
#define AGP_USER_MEMORY (AGP_USER_TYPES) |
#define AGP_USER_CACHED_MEMORY (AGP_USER_TYPES + 1) |
static inline uint8_t __raw_readb(const volatile void __iomem *addr) |
{ |
return *(const volatile uint8_t __force *) addr; |
} |
static inline uint16_t __raw_readw(const volatile void __iomem *addr) |
{ |
return *(const volatile uint16_t __force *) addr; |
} |
static inline uint32_t __raw_readl(const volatile void __iomem *addr) |
{ |
return *(const volatile uint32_t __force *) addr; |
} |
#define readb __raw_readb |
#define readw __raw_readw |
#define readl __raw_readl |
static inline void __raw_writeb(uint8_t b, volatile void __iomem *addr) |
{ *(volatile uint8_t __force *) addr = b;} |
static inline void __raw_writew(uint16_t b, volatile void __iomem *addr) |
{ *(volatile uint16_t __force *) addr = b;} |
static inline void __raw_writel(uint32_t b, volatile void __iomem *addr) |
{ *(volatile uint32_t __force *) addr = b;} |
static inline void __raw_writeq(__u64 b, volatile void __iomem *addr) |
{ *(volatile __u64 *)addr = b;} |
#define writeb __raw_writeb |
#define writew __raw_writew |
#define writel __raw_writel |
#define writeq __raw_writeq |
static inline int pci_read_config_word(struct pci_dev *dev, int where, |
u16 *val) |
{ |
*val = PciRead16(dev->busnr, dev->devfn, where); |
return 1; |
} |
static inline int pci_read_config_dword(struct pci_dev *dev, int where, |
u32 *val) |
{ |
*val = PciRead32(dev->busnr, dev->devfn, where); |
return 1; |
} |
static inline int pci_write_config_word(struct pci_dev *dev, int where, |
u16 val) |
{ |
PciWrite16(dev->busnr, dev->devfn, where, val); |
return 1; |
} |
/* |
* If we have Intel graphics, we're not going to have anything other than |
* an Intel IOMMU. So make the correct use of the PCI DMA API contingent |
* on the Intel IOMMU support (CONFIG_DMAR). |
* Only newer chipsets need to bother with this, of course. |
*/ |
#ifdef CONFIG_DMAR |
#define USE_PCI_DMA_API 1 |
#else |
#define USE_PCI_DMA_API 0 |
#endif |
struct intel_gtt_driver { |
unsigned int gen : 8; |
unsigned int is_g33 : 1; |
unsigned int is_pineview : 1; |
unsigned int is_ironlake : 1; |
unsigned int has_pgtbl_enable : 1; |
unsigned int dma_mask_size : 8; |
/* Chipset specific GTT setup */ |
int (*setup)(void); |
/* This should undo anything done in ->setup() save the unmapping |
* of the mmio register file, that's done in the generic code. */ |
void (*cleanup)(void); |
void (*write_entry)(dma_addr_t addr, unsigned int entry, unsigned int flags); |
/* Flags is a more or less chipset specific opaque value. |
* For chipsets that need to support old ums (non-gem) code, this |
* needs to be identical to the various supported agp memory types! */ |
bool (*check_flags)(unsigned int flags); |
void (*chipset_flush)(void); |
}; |
static struct _intel_private { |
struct intel_gtt base; |
const struct intel_gtt_driver *driver; |
struct pci_dev *pcidev; /* device one */ |
struct pci_dev *bridge_dev; |
u8 __iomem *registers; |
phys_addr_t gtt_bus_addr; |
phys_addr_t gma_bus_addr; |
u32 PGETBL_save; |
u32 __iomem *gtt; /* I915G */ |
bool clear_fake_agp; /* on first access via agp, fill with scratch */ |
int num_dcache_entries; |
void __iomem *i9xx_flush_page; |
char *i81x_gtt_table; |
struct resource ifp_resource; |
int resource_valid; |
struct page *scratch_page; |
dma_addr_t scratch_page_dma; |
} intel_private; |
#define INTEL_GTT_GEN intel_private.driver->gen |
#define IS_G33 intel_private.driver->is_g33 |
#define IS_PINEVIEW intel_private.driver->is_pineview |
#define IS_IRONLAKE intel_private.driver->is_ironlake |
#define HAS_PGTBL_EN intel_private.driver->has_pgtbl_enable |
static int intel_gtt_setup_scratch_page(void) |
{ |
addr_t page; |
page = AllocPage(); |
if (page == 0) |
return -ENOMEM; |
intel_private.scratch_page_dma = page; |
intel_private.scratch_page = NULL; |
return 0; |
} |
static unsigned int intel_gtt_stolen_size(void) |
{ |
u16 gmch_ctrl; |
u8 rdct; |
int local = 0; |
static const int ddt[4] = { 0, 16, 32, 64 }; |
unsigned int stolen_size = 0; |
if (INTEL_GTT_GEN == 1) |
return 0; /* no stolen mem on i81x */ |
pci_read_config_word(intel_private.bridge_dev, |
I830_GMCH_CTRL, &gmch_ctrl); |
if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB || |
intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) { |
switch (gmch_ctrl & I830_GMCH_GMS_MASK) { |
case I830_GMCH_GMS_STOLEN_512: |
stolen_size = KB(512); |
break; |
case I830_GMCH_GMS_STOLEN_1024: |
stolen_size = MB(1); |
break; |
case I830_GMCH_GMS_STOLEN_8192: |
stolen_size = MB(8); |
break; |
case I830_GMCH_GMS_LOCAL: |
rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE); |
stolen_size = (I830_RDRAM_ND(rdct) + 1) * |
MB(ddt[I830_RDRAM_DDT(rdct)]); |
local = 1; |
break; |
default: |
stolen_size = 0; |
break; |
} |
} else if (INTEL_GTT_GEN == 6) { |
/* |
* SandyBridge has new memory control reg at 0x50.w |
*/ |
u16 snb_gmch_ctl; |
pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
switch (snb_gmch_ctl & SNB_GMCH_GMS_STOLEN_MASK) { |
case SNB_GMCH_GMS_STOLEN_32M: |
stolen_size = MB(32); |
break; |
case SNB_GMCH_GMS_STOLEN_64M: |
stolen_size = MB(64); |
break; |
case SNB_GMCH_GMS_STOLEN_96M: |
stolen_size = MB(96); |
break; |
case SNB_GMCH_GMS_STOLEN_128M: |
stolen_size = MB(128); |
break; |
case SNB_GMCH_GMS_STOLEN_160M: |
stolen_size = MB(160); |
break; |
case SNB_GMCH_GMS_STOLEN_192M: |
stolen_size = MB(192); |
break; |
case SNB_GMCH_GMS_STOLEN_224M: |
stolen_size = MB(224); |
break; |
case SNB_GMCH_GMS_STOLEN_256M: |
stolen_size = MB(256); |
break; |
case SNB_GMCH_GMS_STOLEN_288M: |
stolen_size = MB(288); |
break; |
case SNB_GMCH_GMS_STOLEN_320M: |
stolen_size = MB(320); |
break; |
case SNB_GMCH_GMS_STOLEN_352M: |
stolen_size = MB(352); |
break; |
case SNB_GMCH_GMS_STOLEN_384M: |
stolen_size = MB(384); |
break; |
case SNB_GMCH_GMS_STOLEN_416M: |
stolen_size = MB(416); |
break; |
case SNB_GMCH_GMS_STOLEN_448M: |
stolen_size = MB(448); |
break; |
case SNB_GMCH_GMS_STOLEN_480M: |
stolen_size = MB(480); |
break; |
case SNB_GMCH_GMS_STOLEN_512M: |
stolen_size = MB(512); |
break; |
} |
} else { |
switch (gmch_ctrl & I855_GMCH_GMS_MASK) { |
case I855_GMCH_GMS_STOLEN_1M: |
stolen_size = MB(1); |
break; |
case I855_GMCH_GMS_STOLEN_4M: |
stolen_size = MB(4); |
break; |
case I855_GMCH_GMS_STOLEN_8M: |
stolen_size = MB(8); |
break; |
case I855_GMCH_GMS_STOLEN_16M: |
stolen_size = MB(16); |
break; |
case I855_GMCH_GMS_STOLEN_32M: |
stolen_size = MB(32); |
break; |
case I915_GMCH_GMS_STOLEN_48M: |
stolen_size = MB(48); |
break; |
case I915_GMCH_GMS_STOLEN_64M: |
stolen_size = MB(64); |
break; |
case G33_GMCH_GMS_STOLEN_128M: |
stolen_size = MB(128); |
break; |
case G33_GMCH_GMS_STOLEN_256M: |
stolen_size = MB(256); |
break; |
case INTEL_GMCH_GMS_STOLEN_96M: |
stolen_size = MB(96); |
break; |
case INTEL_GMCH_GMS_STOLEN_160M: |
stolen_size = MB(160); |
break; |
case INTEL_GMCH_GMS_STOLEN_224M: |
stolen_size = MB(224); |
break; |
case INTEL_GMCH_GMS_STOLEN_352M: |
stolen_size = MB(352); |
break; |
default: |
stolen_size = 0; |
break; |
} |
} |
if (stolen_size > 0) { |
dbgprintf("detected %dK %s memory\n", |
stolen_size / KB(1), local ? "local" : "stolen"); |
} else { |
dbgprintf("no pre-allocated video memory detected\n"); |
stolen_size = 0; |
} |
return stolen_size; |
} |
static void i965_adjust_pgetbl_size(unsigned int size_flag) |
{ |
u32 pgetbl_ctl, pgetbl_ctl2; |
/* ensure that ppgtt is disabled */ |
pgetbl_ctl2 = readl(intel_private.registers+I965_PGETBL_CTL2); |
pgetbl_ctl2 &= ~I810_PGETBL_ENABLED; |
writel(pgetbl_ctl2, intel_private.registers+I965_PGETBL_CTL2); |
/* write the new ggtt size */ |
pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); |
pgetbl_ctl &= ~I965_PGETBL_SIZE_MASK; |
pgetbl_ctl |= size_flag; |
writel(pgetbl_ctl, intel_private.registers+I810_PGETBL_CTL); |
} |
static unsigned int i965_gtt_total_entries(void) |
{ |
int size; |
u32 pgetbl_ctl; |
u16 gmch_ctl; |
pci_read_config_word(intel_private.bridge_dev, |
I830_GMCH_CTRL, &gmch_ctl); |
if (INTEL_GTT_GEN == 5) { |
switch (gmch_ctl & G4x_GMCH_SIZE_MASK) { |
case G4x_GMCH_SIZE_1M: |
case G4x_GMCH_SIZE_VT_1M: |
i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1MB); |
break; |
case G4x_GMCH_SIZE_VT_1_5M: |
i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1_5MB); |
break; |
case G4x_GMCH_SIZE_2M: |
case G4x_GMCH_SIZE_VT_2M: |
i965_adjust_pgetbl_size(I965_PGETBL_SIZE_2MB); |
break; |
} |
} |
pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); |
switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) { |
case I965_PGETBL_SIZE_128KB: |
size = KB(128); |
break; |
case I965_PGETBL_SIZE_256KB: |
size = KB(256); |
break; |
case I965_PGETBL_SIZE_512KB: |
size = KB(512); |
break; |
/* GTT pagetable sizes bigger than 512KB are not possible on G33! */ |
case I965_PGETBL_SIZE_1MB: |
size = KB(1024); |
break; |
case I965_PGETBL_SIZE_2MB: |
size = KB(2048); |
break; |
case I965_PGETBL_SIZE_1_5MB: |
size = KB(1024 + 512); |
break; |
default: |
dbgprintf("unknown page table size, assuming 512KB\n"); |
size = KB(512); |
} |
return size/4; |
} |
static unsigned int intel_gtt_total_entries(void) |
{ |
int size; |
if (IS_G33 || INTEL_GTT_GEN == 4 || INTEL_GTT_GEN == 5) |
return i965_gtt_total_entries(); |
else if (INTEL_GTT_GEN == 6) { |
u16 snb_gmch_ctl; |
pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
switch (snb_gmch_ctl & SNB_GTT_SIZE_MASK) { |
default: |
case SNB_GTT_SIZE_0M: |
printk(KERN_ERR "Bad GTT size mask: 0x%04x.\n", snb_gmch_ctl); |
size = MB(0); |
break; |
case SNB_GTT_SIZE_1M: |
size = MB(1); |
break; |
case SNB_GTT_SIZE_2M: |
size = MB(2); |
break; |
} |
return size/4; |
} else { |
/* On previous hardware, the GTT size was just what was |
* required to map the aperture. |
*/ |
return intel_private.base.gtt_mappable_entries; |
} |
} |
static unsigned int intel_gtt_mappable_entries(void) |
{ |
unsigned int aperture_size; |
if (INTEL_GTT_GEN == 1) { |
u32 smram_miscc; |
pci_read_config_dword(intel_private.bridge_dev, |
I810_SMRAM_MISCC, &smram_miscc); |
if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) |
== I810_GFX_MEM_WIN_32M) |
aperture_size = MB(32); |
else |
aperture_size = MB(64); |
} else if (INTEL_GTT_GEN == 2) { |
u16 gmch_ctrl; |
pci_read_config_word(intel_private.bridge_dev, |
I830_GMCH_CTRL, &gmch_ctrl); |
if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_64M) |
aperture_size = MB(64); |
else |
aperture_size = MB(128); |
} else { |
/* 9xx supports large sizes, just look at the length */ |
aperture_size = pci_resource_len(intel_private.pcidev, 2); |
} |
return aperture_size >> PAGE_SHIFT; |
} |
static void intel_gtt_teardown_scratch_page(void) |
{ |
// FreePage(intel_private.scratch_page_dma); |
} |
static void intel_gtt_cleanup(void) |
{ |
intel_private.driver->cleanup(); |
FreeKernelSpace(intel_private.gtt); |
FreeKernelSpace(intel_private.registers); |
// intel_gtt_teardown_scratch_page(); |
} |
static int intel_gtt_init(void) |
{ |
u32 gtt_map_size; |
int ret; |
ENTER(); |
ret = intel_private.driver->setup(); |
if (ret != 0) |
{ |
LEAVE(); |
return ret; |
}; |
intel_private.base.gtt_mappable_entries = intel_gtt_mappable_entries(); |
intel_private.base.gtt_total_entries = intel_gtt_total_entries(); |
/* save the PGETBL reg for resume */ |
intel_private.PGETBL_save = |
readl(intel_private.registers+I810_PGETBL_CTL) |
& ~I810_PGETBL_ENABLED; |
/* we only ever restore the register when enabling the PGTBL... */ |
if (HAS_PGTBL_EN) |
intel_private.PGETBL_save |= I810_PGETBL_ENABLED; |
dbgprintf("detected gtt size: %dK total, %dK mappable\n", |
intel_private.base.gtt_total_entries * 4, |
intel_private.base.gtt_mappable_entries * 4); |
gtt_map_size = intel_private.base.gtt_total_entries * 4; |
intel_private.gtt = (u32*)MapIoMem(intel_private.gtt_bus_addr, |
gtt_map_size, PG_SW+PG_NOCACHE); |
if (!intel_private.gtt) { |
intel_private.driver->cleanup(); |
FreeKernelSpace(intel_private.registers); |
return -ENOMEM; |
} |
asm volatile("wbinvd"); |
intel_private.base.stolen_size = intel_gtt_stolen_size(); |
intel_private.base.needs_dmar = USE_PCI_DMA_API && INTEL_GTT_GEN > 2; |
ret = intel_gtt_setup_scratch_page(); |
if (ret != 0) { |
intel_gtt_cleanup(); |
return ret; |
} |
intel_enable_gtt(); |
LEAVE(); |
return 0; |
} |
static bool intel_enable_gtt(void) |
{ |
u32 gma_addr; |
u8 __iomem *reg; |
if (INTEL_GTT_GEN <= 2) |
pci_read_config_dword(intel_private.pcidev, I810_GMADDR, |
&gma_addr); |
else |
pci_read_config_dword(intel_private.pcidev, I915_GMADDR, |
&gma_addr); |
intel_private.gma_bus_addr = (gma_addr & PCI_BASE_ADDRESS_MEM_MASK); |
if (INTEL_GTT_GEN >= 6) |
return true; |
if (INTEL_GTT_GEN == 2) { |
u16 gmch_ctrl; |
pci_read_config_word(intel_private.bridge_dev, |
I830_GMCH_CTRL, &gmch_ctrl); |
gmch_ctrl |= I830_GMCH_ENABLED; |
pci_write_config_word(intel_private.bridge_dev, |
I830_GMCH_CTRL, gmch_ctrl); |
pci_read_config_word(intel_private.bridge_dev, |
I830_GMCH_CTRL, &gmch_ctrl); |
if ((gmch_ctrl & I830_GMCH_ENABLED) == 0) { |
dbgprintf("failed to enable the GTT: GMCH_CTRL=%x\n", |
gmch_ctrl); |
return false; |
} |
} |
/* On the resume path we may be adjusting the PGTBL value, so |
* be paranoid and flush all chipset write buffers... |
*/ |
if (INTEL_GTT_GEN >= 3) |
writel(0, intel_private.registers+GFX_FLSH_CNTL); |
reg = intel_private.registers+I810_PGETBL_CTL; |
writel(intel_private.PGETBL_save, reg); |
if (HAS_PGTBL_EN && (readl(reg) & I810_PGETBL_ENABLED) == 0) { |
dbgprintf("failed to enable the GTT: PGETBL=%x [expected %x]\n", |
readl(reg), intel_private.PGETBL_save); |
return false; |
} |
if (INTEL_GTT_GEN >= 3) |
writel(0, intel_private.registers+GFX_FLSH_CNTL); |
return true; |
} |
static void intel_i9xx_setup_flush(void) |
{ |
/* return if already configured */ |
if (intel_private.ifp_resource.start) |
return; |
if (INTEL_GTT_GEN == 6) |
return; |
#if 0 |
/* setup a resource for this object */ |
intel_private.ifp_resource.name = "Intel Flush Page"; |
intel_private.ifp_resource.flags = IORESOURCE_MEM; |
/* Setup chipset flush for 915 */ |
if (IS_G33 || INTEL_GTT_GEN >= 4) { |
intel_i965_g33_setup_chipset_flush(); |
} else { |
intel_i915_setup_chipset_flush(); |
} |
if (intel_private.ifp_resource.start) |
intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE); |
if (!intel_private.i9xx_flush_page) |
dev_err(&intel_private.pcidev->dev, |
"can't ioremap flush page - no chipset flushing\n"); |
#endif |
} |
static void i9xx_chipset_flush(void) |
{ |
if (intel_private.i9xx_flush_page) |
writel(1, intel_private.i9xx_flush_page); |
} |
static bool gen6_check_flags(unsigned int flags) |
{ |
return true; |
} |
static void gen6_write_entry(dma_addr_t addr, unsigned int entry, |
unsigned int flags) |
{ |
unsigned int type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT; |
unsigned int gfdt = flags & AGP_USER_CACHED_MEMORY_GFDT; |
u32 pte_flags; |
if (type_mask == AGP_USER_MEMORY) |
pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID; |
else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) { |
pte_flags = GEN6_PTE_LLC_MLC | I810_PTE_VALID; |
if (gfdt) |
pte_flags |= GEN6_PTE_GFDT; |
} else { /* set 'normal'/'cached' to LLC by default */ |
pte_flags = GEN6_PTE_LLC | I810_PTE_VALID; |
if (gfdt) |
pte_flags |= GEN6_PTE_GFDT; |
} |
/* gen6 has bit11-4 for physical addr bit39-32 */ |
addr |= (addr >> 28) & 0xff0; |
writel(addr | pte_flags, intel_private.gtt + entry); |
} |
static void gen6_cleanup(void) |
{ |
} |
static int i9xx_setup(void) |
{ |
u32 reg_addr; |
pci_read_config_dword(intel_private.pcidev, I915_MMADDR, ®_addr); |
reg_addr &= 0xfff80000; |
intel_private.registers = (u8*)MapIoMem(reg_addr, 128 * 4096, PG_SW+PG_NOCACHE); |
if (!intel_private.registers) |
return -ENOMEM; |
if (INTEL_GTT_GEN == 3) { |
u32 gtt_addr; |
pci_read_config_dword(intel_private.pcidev, |
I915_PTEADDR, >t_addr); |
intel_private.gtt_bus_addr = gtt_addr; |
} else { |
u32 gtt_offset; |
switch (INTEL_GTT_GEN) { |
case 5: |
case 6: |
gtt_offset = MB(2); |
break; |
case 4: |
default: |
gtt_offset = KB(512); |
break; |
} |
intel_private.gtt_bus_addr = reg_addr + gtt_offset; |
} |
intel_i9xx_setup_flush(); |
return 0; |
} |
static const struct intel_gtt_driver sandybridge_gtt_driver = { |
.gen = 6, |
.setup = i9xx_setup, |
.cleanup = gen6_cleanup, |
.write_entry = gen6_write_entry, |
.dma_mask_size = 40, |
.check_flags = gen6_check_flags, |
.chipset_flush = i9xx_chipset_flush, |
}; |
/* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of |
* driver and gmch_driver must be non-null, and find_gmch will determine |
* which one should be used if a gmch_chip_id is present. |
*/ |
static const struct intel_gtt_driver_description { |
unsigned int gmch_chip_id; |
char *name; |
const struct intel_gtt_driver *gtt_driver; |
} intel_gtt_chipsets[] = { |
{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG, |
"Sandybridge", &sandybridge_gtt_driver }, |
{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG, |
"Sandybridge", &sandybridge_gtt_driver }, |
{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG, |
"Sandybridge", &sandybridge_gtt_driver }, |
{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG, |
"Sandybridge", &sandybridge_gtt_driver }, |
{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG, |
"Sandybridge", &sandybridge_gtt_driver }, |
{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG, |
"Sandybridge", &sandybridge_gtt_driver }, |
{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG, |
"Sandybridge", &sandybridge_gtt_driver }, |
{ 0, NULL, NULL } |
}; |
static int find_gmch(u16 device) |
{ |
struct pci_dev *gmch_device; |
gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL); |
if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) { |
gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, |
device, gmch_device); |
} |
if (!gmch_device) |
return 0; |
intel_private.pcidev = gmch_device; |
return 1; |
} |
int intel_gmch_probe(struct pci_dev *pdev, |
struct agp_bridge_data *bridge) |
{ |
int i, mask; |
intel_private.driver = NULL; |
for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) { |
if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) { |
intel_private.driver = |
intel_gtt_chipsets[i].gtt_driver; |
break; |
} |
} |
if (!intel_private.driver) |
return 0; |
// bridge->driver = &intel_fake_agp_driver; |
bridge->dev_private_data = &intel_private; |
bridge->dev = pdev; |
intel_private.bridge_dev = pdev; |
dbgprintf("Intel %s Chipset\n", intel_gtt_chipsets[i].name); |
mask = intel_private.driver->dma_mask_size; |
// if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask))) |
// dev_err(&intel_private.pcidev->dev, |
// "set gfx device dma mask %d-bit failed!\n", mask); |
// else |
// pci_set_consistent_dma_mask(intel_private.pcidev, |
// DMA_BIT_MASK(mask)); |
/*if (bridge->driver == &intel_810_driver) |
return 1;*/ |
if (intel_gtt_init() != 0) |
return 0; |
return 1; |
} |
/drivers/video/drm/i915/Gtt/intel-gtt.h |
---|
0,0 → 1,41 |
/* Common header for intel-gtt.ko and i915.ko */ |
#ifndef _DRM_INTEL_GTT_H |
#define _DRM_INTEL_GTT_H |
const struct intel_gtt { |
/* Size of memory reserved for graphics by the BIOS */ |
unsigned int stolen_size; |
/* Total number of gtt entries. */ |
unsigned int gtt_total_entries; |
/* Part of the gtt that is mappable by the cpu, for those chips where |
* this is not the full gtt. */ |
unsigned int gtt_mappable_entries; |
/* Whether i915 needs to use the dmar apis or not. */ |
unsigned int needs_dmar : 1; |
} *intel_gtt_get(void); |
void intel_gtt_chipset_flush(void); |
void intel_gtt_unmap_memory(struct scatterlist *sg_list, int num_sg); |
void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries); |
int intel_gtt_map_memory(struct page **pages, unsigned int num_entries, |
struct scatterlist **sg_list, int *num_sg); |
void intel_gtt_insert_sg_entries(struct scatterlist *sg_list, |
unsigned int sg_len, |
unsigned int pg_start, |
unsigned int flags); |
void intel_gtt_insert_pages(unsigned int first_entry, unsigned int num_entries, |
struct page **pages, unsigned int flags); |
/* Special gtt memory types */ |
#define AGP_DCACHE_MEMORY 1 |
#define AGP_PHYS_MEMORY 2 |
/* New caching attributes for gen6/sandybridge */ |
#define AGP_USER_CACHED_MEMORY_LLC_MLC (AGP_USER_TYPES + 2) |
#define AGP_USER_UNCACHED_MEMORY (AGP_USER_TYPES + 4) |
/* flag for GFDT type */ |
#define AGP_USER_CACHED_MEMORY_GFDT (1 << 3) |
#endif |
/drivers/video/drm/i915/Gtt/. |
---|
Property changes: |
Added: bugtraq:number |
+true |
\ No newline at end of property |