/drivers/video/drm/i915/i915_drv.c |
---|
640,10 → 640,23 |
#define __i915_write(x, y) \ |
void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \ |
u32 __fifo_ret = 0; \ |
trace_i915_reg_rw(true, reg, val, sizeof(val)); \ |
if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
__gen6_gt_wait_for_fifo(dev_priv); \ |
__fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ |
} \ |
if (IS_VALLEYVIEW(dev_priv->dev) && IS_DISPLAYREG(reg)) { \ |
write##y(val, dev_priv->regs + reg + 0x180000); \ |
} else { \ |
write##y(val, dev_priv->regs + reg); \ |
} \ |
if (unlikely(__fifo_ret)) { \ |
gen6_gt_check_fifodbg(dev_priv); \ |
} \ |
if (IS_HASWELL(dev_priv->dev) && (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \ |
DRM_ERROR("Unclaimed write to %x\n", reg); \ |
writel(ERR_INT_MMIO_UNCLAIMED, dev_priv->regs + GEN7_ERR_INT); \ |
} \ |
} |
__i915_write(8, b) |
__i915_write(16, w) |
/drivers/video/drm/i915/intel_bios.c |
---|
498,12 → 498,8 |
edp = find_section(bdb, BDB_EDP); |
if (!edp) { |
if (SUPPORTS_EDP(dev_priv->dev) && dev_priv->edp.support) { |
DRM_DEBUG_KMS("No eDP BDB found but eDP panel " |
"supported, assume %dbpp panel color " |
"depth.\n", |
dev_priv->edp.bpp); |
} |
if (SUPPORTS_EDP(dev_priv->dev) && dev_priv->edp.support) |
DRM_DEBUG_KMS("No eDP BDB found but eDP panel supported.\n"); |
return; |
} |
656,11 → 652,9 |
dev_priv->lvds_use_ssc = 1; |
dev_priv->lvds_ssc_freq = intel_bios_ssc_frequency(dev, 1); |
DRM_DEBUG_KMS("Set default to SSC at %dMHz\n", dev_priv->lvds_ssc_freq); |
/* eDP data */ |
dev_priv->edp.bpp = 18; |
} |
/** |
* intel_parse_bios - find VBT and initialize settings from the BIOS |
* @dev: DRM device |
/drivers/video/drm/i915/intel_crt.c |
---|
142,7 → 142,7 |
int old_dpms; |
/* PCH platforms and VLV only support on/off. */ |
if (INTEL_INFO(dev)->gen < 5 && mode != DRM_MODE_DPMS_ON) |
if (INTEL_INFO(dev)->gen >= 5 && mode != DRM_MODE_DPMS_ON) |
mode = DRM_MODE_DPMS_OFF; |
if (mode == connector->dpms) |
/drivers/video/drm/i915/intel_display.c |
---|
3857,6 → 3857,17 |
} |
} |
if (intel_encoder->type == INTEL_OUTPUT_EDP) { |
/* Use VBT settings if we have an eDP panel */ |
unsigned int edp_bpc = dev_priv->edp.bpp / 3; |
if (edp_bpc < display_bpc) { |
DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc); |
display_bpc = edp_bpc; |
} |
continue; |
} |
/* |
* HDMI is either 12 or 8, so if the display lets 10bpc sneak |
* through, clamp it down. (Note: >12bpc will be caught below.) |
/drivers/video/drm/i915/intel_pm.c |
---|
2398,15 → 2398,9 |
if (i915_enable_rc6 >= 0) |
return i915_enable_rc6; |
if (INTEL_INFO(dev)->gen == 5) { |
#ifdef CONFIG_INTEL_IOMMU |
/* Disable rc6 on ilk if VT-d is on. */ |
if (intel_iommu_gfx_mapped) |
return false; |
#endif |
DRM_DEBUG_DRIVER("Ironlake: only RC6 available\n"); |
return INTEL_RC6_ENABLE; |
} |
/* Disable RC6 on Ironlake */ |
if (INTEL_INFO(dev)->gen == 5) |
return 0; |
if (IS_HASWELL(dev)) { |
DRM_DEBUG_DRIVER("Haswell: only RC6 available\n"); |
/drivers/video/drm/i915/intel_sdvo.c |
---|
2212,7 → 2212,6 |
connector->connector_type = DRM_MODE_CONNECTOR_HDMIA; |
intel_sdvo->is_hdmi = true; |
} |
intel_sdvo->base.cloneable = true; |
intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo); |
if (intel_sdvo->is_hdmi) |
2243,7 → 2242,6 |
intel_sdvo->is_tv = true; |
intel_sdvo->base.needs_tv_clock = true; |
intel_sdvo->base.cloneable = false; |
intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo); |
2286,8 → 2284,6 |
intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1; |
} |
intel_sdvo->base.cloneable = true; |
intel_sdvo_connector_init(intel_sdvo_connector, |
intel_sdvo); |
return true; |
2318,9 → 2314,6 |
intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1; |
} |
/* SDVO LVDS is not cloneable because the input mode gets adjusted by the encoder */ |
intel_sdvo->base.cloneable = false; |
intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo); |
if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) |
goto err; |
2393,6 → 2386,18 |
return true; |
} |
static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo) |
{ |
struct drm_device *dev = intel_sdvo->base.base.dev; |
struct drm_connector *connector, *tmp; |
list_for_each_entry_safe(connector, tmp, |
&dev->mode_config.connector_list, head) { |
if (intel_attached_encoder(connector) == &intel_sdvo->base) |
intel_sdvo_destroy(connector); |
} |
} |
static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, |
struct intel_sdvo_connector *intel_sdvo_connector, |
int type) |
2716,9 → 2721,20 |
intel_sdvo->caps.output_flags) != true) { |
DRM_DEBUG_KMS("SDVO output failed to setup on %s\n", |
SDVO_NAME(intel_sdvo)); |
goto err; |
/* Output_setup can leave behind connectors! */ |
goto err_output; |
} |
/* |
* Cloning SDVO with anything is often impossible, since the SDVO |
* encoder can request a special input timing mode. And even if that's |
* not the case we have evidence that cloning a plain unscaled mode with |
* VGA doesn't really work. Furthermore the cloning flags are way too |
* simplistic anyway to express such constraints, so just give up on |
* cloning for SDVO encoders. |
*/ |
intel_sdvo->base.cloneable = false; |
/* Only enable the hotplug irq if we need it, to work around noisy |
* hotplug lines. |
*/ |
2729,12 → 2745,12 |
/* Set the input timing to the screen. Assume always input 0. */ |
if (!intel_sdvo_set_target_input(intel_sdvo)) |
goto err; |
goto err_output; |
if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo, |
&intel_sdvo->pixel_clock_min, |
&intel_sdvo->pixel_clock_max)) |
goto err; |
goto err_output; |
DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, " |
"clock range %dMHz - %dMHz, " |
2754,6 → 2770,9 |
(SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N'); |
return true; |
err_output: |
intel_sdvo_output_cleanup(intel_sdvo); |
err: |
drm_encoder_cleanup(&intel_encoder->base); |
// i2c_del_adapter(&intel_sdvo->ddc); |
/drivers/video/drm/i915/kms_display.c |
---|
680,7 → 680,7 |
(void)i915_add_request(ring, file, NULL); |
} |
int blit_video(u32 hbitmap, int dst_x, int dst_y, |
int srv_blit_bitmap(u32 hbitmap, int dst_x, int dst_y, |
int src_x, int src_y, u32 w, u32 h) |
{ |
drm_i915_private_t *dev_priv = main_device->dev_private; |
713,7 → 713,19 |
return -1; |
GetWindowRect(&winrc); |
{ |
static warn_count; |
if(warn_count < 1) |
{ |
printf("left %d top %d right %d bottom %d\n", |
winrc.left, winrc.top, winrc.right, winrc.bottom); |
printf("bitmap width %d height %d\n", w, h); |
warn_count++; |
}; |
}; |
dst_clip.xmin = 0; |
dst_clip.ymin = 0; |
dst_clip.xmax = winrc.right-winrc.left; |
852,6 → 864,18 |
} |
#endif |
{ |
static warn_count; |
if(warn_count < 1) |
{ |
printf("blit width %d height %d\n", |
width, height); |
warn_count++; |
}; |
}; |
if((context->cmd_buffer & 0xFC0)==0xFC0) |
context->cmd_buffer&= 0xFFFFF000; |
/drivers/video/drm/i915/main.c |
---|
21,7 → 21,7 |
int _stdcall display_handler(ioctl_t *io); |
int init_agp(void); |
int blit_video(u32 hbitmap, int dst_x, int dst_y, |
int srv_blit_bitmap(u32 hbitmap, int dst_x, int dst_y, |
int src_x, int src_y, u32 w, u32 h); |
int blit_textured(u32 hbitmap, int dst_x, int dst_y, |
101,10 → 101,10 |
#define SRV_LOCK_SURFACE 12 |
#define SRV_UNLOCK_SURFACE 13 |
#define SRV_RESIZE_SURFACE 14 |
#define SRV_BLIT_BITMAP 15 |
#define SRV_BLIT_TEXTURE 16 |
#define SRV_BLIT_VIDEO 17 |
#define SRV_BLIT_VIDEO 20 |
#define check_input(size) \ |
if( unlikely((inp==NULL)||(io->inp_size != (size))) ) \ |
break; |
164,8 → 164,8 |
retval = resize_surface((struct io_call_14*)inp); |
break; |
case SRV_BLIT_VIDEO: |
blit_video( inp[0], inp[1], inp[2], |
case SRV_BLIT_BITMAP: |
srv_blit_bitmap( inp[0], inp[1], inp[2], |
inp[3], inp[4], inp[5], inp[6]); |
// blit_tex( inp[0], inp[1], inp[2], |